S1L50000 EPSON | Alldatasheet

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EPSO N ELEC TR O N IC S AM ER IC A, INC . /c105 150 River Oaks Pkw y /c105 San Jose, C A 95134 /c105 Tel: (408) 922-0200 /c105 Fax: (408) 922-0238 A SIC S1L50000 S1L50000 SERIES HIGH DENSITY GATE ARRAY Œ DESCRIPTION EPS O N Electronics Am erica, Inc.’s S1L50000 Series is a fam ily of ultra high-speed VLSI CM O S gate array utilizing a 0.35µm “sea-of-gates” architecture. The S1L50000H products feature 5V tolerant I/O buffers.

  • Ultra-high-speed, high density and low pow er consum ption
  • Low voltage operation: 3.3V and 2.0V
  • Nu m ber of raw gates: 28,710 ~ 815,468 gates Œ FEA TURES
  • Process 0.35µm 2/3/4 layer m etalization C M O S process
  • Integration A m axim um of 815,468 gates (2 input NAND gate equivalent)
  • O perating Speed Internal gates: 140 ps (3.3V Typ), 210 ps (2.0V Typ) (2-input pair NAND, F/O = 2, Typical w ire load) Input buffer: 380 ps (5.0V Typ) Built-in level shifter is used. 400 ps (3.3V Typ), 1.30 ns (2.0V Typ) (F/O = 2, Typical w ire load) O utput buffer: 2.12 ns (5.0V Typ) Built-in level shifter is used. 2.02 ns (3.3 V Typ), 3.90 ns (2.0V Typ) (CL = 15 pF)
  • I/F Levels Input/Output TTL/C M O S/LVT TL com patible
  • Input M odes TTL, CM O S, LVTTL, TTL Schm itt, CM O S Schm itt, LVTTL Schm itt, PCI Built-in pull-up and pull-dow n resistors can be usable. (2 types for each resistor value)
  • O utput M odes No rmal, 3-state, bi-directional, PCI
  • O utput D rive IO L = 0.1, 1, 3, 8, 12, 24 m A selectable (Built-in level shifter is used at 5.0V) IO L = 0.1, 1, 2, 6, 12 m A selectable (at 3.3V) IO L = 0.05, 0.3, 0.6, 2, 4 m A selectable (at 2.0V)
  • R AM Asynchronous 1-port, asynchronous 2-port
  • Dual Pow er O peration supported by using level-shifter circuit Internal logic: O peration supported by low voltage I/O Buffer: Built-in interfaces of both high and low voltages possible
  • O peration possible at VDD = 2.0 ± 0.2V

2 EPSON ELECTRONICS AMERICA, INC. /c105 150 River Oaks Pkwy /c105 San Jose, CA 95134 /c105 Tel: (408) 922-0200 /c105 Fax: (408) 922-0238 ASIC S1L50000 DATA SHEET ΠLINE UP The S1L50000 Series com prises 11 types of m asters, from w hich the custom er is able to select the master most suitable. Cell Utilization Ratio (U)*1 Master Total BC (Raw Gates) Number of Pads Number of Columns (X) Number of Rows (Y) 2-layer metal 3-layer metal 4-layer metal S1L50282/283/284 28710 88 319 90 50% 88% 95% S1L50752/753/754 75774 144 519 146 47% 85% 95% S1L50992/993/994 99198 168 594 167 47% 85% 95% S1L51252/253/254 125772 188 669 188 45% 80% 95% S1L51772/773/774 177062 224 794 223 45% 75% 95% S1L52502/503/504 250160 264 944 265 45% 75% 95% S1L53352/353/354 335858 308 1094 307 43% 75% 95% S1L54422/423/424 442112 352 1256 352 40% 70% 90% S1L55062/063/064 506688 376 1344 377 40% 70% 90% S1L56682/683/684 668552 432 1544 433 40% 70% 90% S1L58152/153/154 815468 480 1706 478 40% 70% 90% NOTE: *1: This is the value when there are no cells, such as RAM cells. The cell use efficiency is dependent not only on the scope of the circuits, but also on the number of signals, the number of branches per signal, etc.; thus, use the values in this table only as an estimate

EPSON ELECTRONICS AMERICA, INC. /c105 150 River Oaks Pkwy /c105 San Jose, CA 95134 /c105 Tel: (408) 922-0200 /c105 Fax: (408) 922-0238 ASIC S1L50000 Œ ELECTRICAL CHARACTERISTICS AND SPECIFICATIONS Absolute Maximum Ratings (For Single Power Supply): (Vss = 0V) Item Symbol Limits Unit Power Supply Voltage V DD -0.3 to 4.0 V Input Voltage V I -0.3 to VDD + 0.5*1 V Output Voltage V O -0.3 to VDD + 0.5*1 V Output Current/Pin I OUT ± 30 mA Storage Temperature T STG -65 to 150 °C *1: Possible to use from -0.3V to 7.5V of I/O buffer voltage in the open-drain systems and input buffer in the IDC and IDH systems. Absolute Maximum Ratings (For Dual Power Supplies): (Vss = 0V) Item Symbol Limits Unit HV DD -0.3 to 7.0 VPower Supply Voltage LVDD -0.3 to 4.0 V HV I -0.3 to HVDD + 0.5*1 VInput Voltage LVI -0.3 to LVDD + 0.5*1 V HV O -0.3 to HVDD + 0.5*1 VOutput Voltage LVO -0.3 to LVDD + 0.5*1 V Output Current/Pin I OUT ± 30 (± 50 *2) mA Storage Temperature T STG -65 to 150 °C **1: Possible to use from -0.3V to 7.5V of I/O buffer voltage in the open-drain systems and input buffer in the IDC and IDH systems. *2: Possible to use for 24mA of output buffer.

4 EPSON ELECTRONICS AMERICA, INC. /c105 150 River Oaks Pkwy /c105 San Jose, CA 95134 /c105 Tel: (408) 922-0200 /c105 Fax: (408) 922-0238 ASIC S1L50000 DATA SHEET Recommended Operating Conditions (For Single Power Supplies): Item Symbol Min Typ Max Unit Power Supply Voltage V DD 3.00 3.30 3.60 V Input Voltage V I VSS -- V DD *1 V Ambient Temperature T a 0 -40 85*3 Normal Input for Rising Edge Input tri -- -- 50 ns Normal Input for Falling Edge Input tfi -- -- 50 ns Schmitt Input for Rising Edge Input tri -- -- 5 ms Schmitt Input for Falling Edge Input tfi -- -- 5 ms *1: Possible to use 5.25 or 5.50V of I/O buffer in the open-drain systems and input buffer in the IDC and IDH systems. *2: The ambient temperature range is recommended for Tj = 0 to 80°C *3: The ambient temperature range is recommended for Tj = -40 to 125°C Recommended Operating Conditions (For Single Power Supplies): Item Symbol Min Typ Max Unit Power Supply Voltage V DD 1.80 2.00 2.20 V Input Voltage V I VSS -- V DD *1 V Ambient Temperature T a 0 -40 85*3 Normal Input for Rising Edge Input tri -- -- 100 ns Normal Input for Falling Edge Input tfi -- -- 100 ns Schmitt Input for Rising Edge Input tri -- -- 10 ms Schmitt Input for Falling Edge Input tfi -- -- 10 ms *1: Possible to use 5.25 or 5.50V of I/O buffer in the open-drain systems and input buffer in the IDC and IDH systems. *2: The ambient temperature range is recommended for Tj = 0 to 80°C *3: The ambient temperature range is recommended for Tj = -40 to 125°C

EPSON ELECTRONICS AMERICA, INC. /c105 150 River Oaks Pkwy /c105 San Jose, CA 95134 /c105 Tel: (408) 922-0200 /c105 Fax: (408) 922-0238 ASIC S1L50000 Recommended Operating Conditions (For Dual Power Supplies): Item Symbol Min Typ Max Unit Power Supply Voltage (High Voltage) HVDD 4.75 4.50 5.00 5.00 5.25 5.50 V Power Supply Voltage (Low Voltage) LVDD 3.00 3.30 3.60 V HV I VSS -- HV DDInput Voltage LVI VSS -- LV DD V Ambient Temperature T a 0 -40 85*3 Normal Input for Rising Edge Input tri -- -- 50 ns Normal Input for Falling Edge Input tri -- -- 50 ns Schmitt Input for Rising Edge Input tri -- -- 5 ms Schmitt Input for Falling Edge Input tri -- -- 5 ms *1: Possible to use 5.25 or 5.50V of I/O buffer in the open-drain systems and input buffer in the LIDC and LIDH systems. *2: The ambient temperature range is recommended for Tj = 0 to 80°C *3: The ambient temperature range is recommended for Tj = -40 to 125°C Recommended Operating Conditions (For Dual Power Supplies): Item Symbol Min Typ Max Unit Power Supply Voltage (High Voltage) HVDD 3.00 3.30 3.60 V Power Supply Voltage (Low Voltage) LVDD 1.80 2.00 2.20 V HV I VSS -- HV DDInput Voltage LVI VSS -- LV DD V Ambient Temperature T a 0 -40 85*2 H tri -- -- 50Normal Input for Rising Edge Input Ltri -- -- 100 ns H tfi -- -- 50Normal Input for Falling Edge Input Ltfi -- -- 100 ns H tri -- -- 5Schmitt Input for Rising Edge Input Ltri -- -- 10 ms H tfi -- -- 5Schmitt Input for Falling Edge Input Ltfi -- -- 10 ms *1: Possible to use 5.25 or 5.50V of I/O buffer in the open-drain systems and input buffer in the LIDC and LIDH systems or HIDC and HIDH systems. *2: The ambient temperature range is recommended for Tj = 0 to 80°C *3: The ambient temperature range is recommended for Tj = -40 to 125°C

6 EPSON ELECTRONICS AMERICA, INC. /c105 150 River Oaks Pkwy /c105 San Jose, CA 95134 /c105 Tel: (408) 922-0200 /c105 Fax: (408) 922-0238 ASIC S1L50000 DATA SHEET Electrical Characteristics of the S1L50000 Series: (VDD = 5.0V, VSS = 0V, Ta = -40 to 85°C) Item Symbol Conditions Min Typ Max Unit Input Leakage Current I LI -- -1 -- 1 µA Off State Leakage Current I OZ -- -1 -- 1 µA High Level Output Voltage V OH IOH = -0.1mA (Type S), -1mA (Type M), -3mA (Type 1), -8mA (Type 2), -12mA (Type 3, Type 4) V DD = Min HV DD -0.4 -- -- V Low Level Output Voltage V OL IOL = 0.1mA (Type S), 1mA (Type M), 3mA (Type 1), 8mA (Type 2), 12mA (Type 3), 24mA (Type 4) V DD = Min -- -- 0.4 V High Level Input Voltage V IH1 CMOS Level, HVDD = Max 3.5 -- -- V Low Level Input Voltage V IL1 CMOS Level, HVDD = Min -- -- 1.0 V High Level Input Voltage V T1+ CMOS Schmitt 2.0 -- 4.0 V Low Level Input Voltage V T1- CMOS Schmitt 0.8 -- 3.1 V Hysteresis Voltage V H1 CMOS Schmitt 0.3 -- -- V High Level Input Voltage V IH2 TTL Level, HVDD = Max 2.0 -- -- V Low Level Input Voltage V IL2 TTL Level, HVDD = Min -- -- 0.8 V High Level Input Voltage V T2+ TTL Schmitt 1.2 -- 2.4 V Low Level Input Voltage V T2- TTL Schmitt 0.6 -- 1.8 V Hysteresis Voltage V H2 TTL Schmitt 0.1 -- -- V High Level Input Voltage V IH3 PCI Level, HVDD = Max 2.0 -- -- V Low Level Input Voltage V IL3 PCI Level, HVDD = Min -- -- 0.8 V High Level Output Current I OH3 PCI Response, VOH = 1.4V, HVDD = Min VOH = 3.1V, HVDD = Max -44 -142 mA mA Low Level Output Current I OL3 PCI Response VOH = 2.20V, HVDD = Min VOL = 0.71V, HVDD = Max 206 mA mA Type 1 30 60 (120) 144 Pull-up Resistance* R PU VI = 0V Type 2 60 120 (240) 288 KΩ Type 1 30 60 (120) 144 Pull-down Resistance* R PD VI = VDD Type 2 60 120 (240) 288 KΩ High Level Maintenance Current IBHH Bus Hold Response, VIN = 2.0V (TTL) HVDD = Min -- -- -80 µA Low Level Maintenance Current IBHL Bus Hold Response, VIN = 0.8V (TTL) HVDD = Min -- -- 33 µA High Level Reversal Current I BHHO Bus Hold Response, VIN = 0.8V (TTL) HVDD = Max -550 -- -- µA Low Level Reversal Current I BHLO Bus Hold Response, VIN = 2.0V (TTL) HVDD = Max 330 -- -- µA Input Terminal Capacitance C I f = 1Mhz, VDD = 0V -- -- 10 pF Output Terminal Capacitance C O f = 1Mhz, VDD = 0V -- -- 10 pF Input/Output Terminal Capacitance C IO f = 1Mhz, VDD = 0V -- -- 10 pF * The values in parentheses are for the case of Ta = 0 to 70°C.

EPSON ELECTRONICS AMERICA, INC. /c105 150 River Oaks Pkwy /c105 San Jose, CA 95134 /c105 Tel: (408) 922-0200 /c105 Fax: (408) 922-0238 ASIC S1L50000 Electrical Characteristics of the S1L50000 Series: (VDD = 3.3V ± 0.3V, VSS = 0V, Ta = -40 to 85°C) Item Symbol Conditions Min Typ Max Unit Quiescent Current* IDDS Quiescent Conditions -- -- 170 µA Input Leakage Current I LI -- -1 -- 1 µA Off State Leakage Current IOZ -- -1 -- 1 µA High Level Output Voltage V OH IOH = -0.1mA (Type S), -1mA (Type M), -2mA (Type 1), -6mA (Type 2), -12mA (Type 3, Type 4) VDD = Min VDD -0.4 -- -- V Low Level Output Voltage V OL IOL = 0.1mA (Type S), 1mA (Type M), 2mA (Type 1), 6mA (Type 2), 12mA (Type 3), 24mA (Type 4) V DD = Min -- -- 0.4 V High Level Input Voltage V IH1 LVTTL Level, VDD = Max 2.0 -- -- V Low Level Input Voltage V IL1 LVTTL Level, VDD = Min -- -- 0.8 V High Level Input Voltage V T1+ LVTTL Schmitt 1.1 -- 2.4 V Low Level Input Voltage V T1- LVTTL Schmitt 0.6 -- 1.8 V Hysteresis Voltage V H1 LVTTL Schmitt 0.1 -- -- V High Level Input Voltage V IH3 PCI Level, VDD = Max 1.71 -- -- V Low Level Input Voltage V IL3 PCI Level, VDD = Min -- -- 0.98 V High Level Output Current IOH3 PCI Response, VOH = 0.90V, VDD = Min VOH = 2.52V, VDD = Max -36 -115 mA mA Low Level Output Current I OL3 PCI Response VOH = 1.80V, VDD = Min VOL = 2.52V, VDD = Max 137 mA mA Type 1 20 50 (100) 120 Pull-up Resistance R PU VI = 0V Type 2 40 100 (200) 240 KΩ Type 1 20 50 (100) 120 Pull-down Resistance R PD VI = VDD Type 2 40 100 (200) 240 KΩ High Level Maintenance Current IBHH Bus Hold Response, V IN = 2.0V, VDD = Min -- -- -20 µA Low Level Maintenance Current IBHL Bus Hold Response, V IN = 0.8V, VDD = Min -- -- 17 µA High Level Reversal Current IBHHO Bus Hold Response, VIN = 0.8V, VDD = Max -350 -- -- µA Low Level Reversal Current IBHLO Bus Hold Response, VIN = 2.0V, VDD = Max 210 -- -- µA Input Terminal Capacitance CI f = 1Mhz, VDD = 0V -- -- 10 pF Output Terminal Capacitance CO f = 1Mhz, VDD = 0V -- -- 10 pF Input/Output Terminal Capacitance C IO f = 1Mhz, VDD = 0V -- -- 10 pF * The quiescent current is a typical value (Tj=85°C) for each master. ** The values in parentheses are for the case of Ta = 0 to 70°C.

8 EPSON ELECTRONICS AMERICA, INC. /c105 150 River Oaks Pkwy /c105 San Jose, CA 95134 /c105 Tel: (408) 922-0200 /c105 Fax: (408) 922-0238 ASIC S1L50000 DATA SHEET Electrical Characteristics of the S1L50000 Series: (VDD = 2.0V ± 0.2V, VSS = 0V, Ta = -40 to 85°C) Item Symbol Conditions Min Typ Max Unit Quiescent Current* IDDS Quiescent Conditions -- -- 150 µA Input Leakage Current I LI -- -1 -- 1 µA Off State Leakage Current IOZ -- -1 -- 1 µA High Level Output Voltage V OH IOH = -0.05mA (Type S), -0.3mA (Type M), -0.6mA (Type 1), -2mA (Type 2), -4mA (Type 3, Type 4) V DD = Min VDD -0.2 -- -- V Low Level Output Voltage V OL IOL = 0.05mA (Type S), 0.3mA (Type M), 0.6mA (Type 1), 2mA (Type 2), 4mA (Type 3), 8mA (Type 4) V DD = Min -- -- 0.2 V High Level Input Voltage V IH1 CMOS Level, VDD = Max 1.6 -- -- V Low Level Input Voltage V IL1 CMOS Level, VDD = Min -- -- 0.3 V High Level Input Voltage V T1+ CMOS Schmitt 0.4 -- 1.6 V Low Level Input Voltage V T1- CMOS Schmitt 0.3 -- 1.4 V Hysteresis Voltage V H1 CMOS Schmitt 0 -- -- V Type 1 30 120 300Pull-up Resistance R PU VI = 0V Type 2 60 240 600 K Ω Type 1 30 120 300Pull-down Resistance R PD VI = VDD Type 2 60 240 600 K Ω High Level Maintenance Current IBHH Bus Hold Response, V IN = 1.6V, VDD = Min -- -- -2 µA Low Level Maintenance Current IBHL Bus Hold Response, V IN = 0.3V, VDD = Min -- -- 2 µA High Level Reversal Current IBHHO Bus Hold Response, VIN = 0.3V, VDD = Max -100 -- -- µA Low Level Reversal Current IBHLO Bus Hold Response, VIN = 1.6V, VDD = Max 100 -- -- µA Input Terminal Capacitance CI f = 1Mhz, VDD = 0V -- -- 10 pF Output Terminal Capacitance CO f = 1Mhz, VDD = 0V -- -- 10 pF Input/Output Terminal Capacitance C IO f = 1Mhz, VDD = 0V -- -- 10 pF * The quiescent current is a typical value (Tj=85°C) for each master.

EPSON ELECTRONICS AMERICA, INC. /c105 150 River Oaks Pkwy /c105 San Jose, CA 95134 /c105 Tel: (408) 922-0200 /c105 Fax: (408) 922-0238 ASIC S1L50000 Delivery Spec. Approval GATE ARRAY DEVELOPMENT FLOW CUSTOMER EE A Product Plan Functional Spec. Circuit Design Test Pattern Design Logical Check (Simulation) Verification ET(TS) Approve the Prototype Approve Delivery Spec. Delivery Spec. ES(TS) Proto. Approval Customer Spec. (Sign Off) Simulation List MP Delivery Spec. Publication MP Setup ES (Engr. Sample) Fabrication TS (Test Sample) Fabrication Make Masks Post Simulation Place & Route Timing Check (Simulation) * Jobs are done by customer and EEA engineer. Steps in shadowed boxes are based on customer’s requirement. NOTE: When the customer performs all tasks to the point of logical simulations and delay simulations on engineering workstations, etc., the route taken is (2, Joint Design). When EEA performs the logical simulations, the route taken is (1, Turnkey Design). Verification Verification Verification G/A Development Request Simulation File

  • Schematic
  • Pin assignment
  • Timing wave form
  • Marking diagram
  • P/O Schematic Pin G/A Development Re quest
  • Test pattern (timing chart)
  • Timing wave form
  • Marking diagram
  • P/O Assignment Logical Check (Simulation) Check Check OK NG OK NG OK NG NG EWS OK NG OK NG OK Delay Analyzing Delay Analyzing Refer to Note

10 EPSON ELECTRONICS AMERICA, INC. /c105 150 River Oaks Pkwy /c105 San Jose, CA 95134 /c105 Tel: (408) 922-0200 /c105 Fax: (408) 922-0238 ASIC S1L50000 DATA SHEET Œ EEA CUSTOMER ENGINEERING To help customers implement their design of EEA ASIC’s, we offer training at our design centers and at customer sites when required. When a design is started, an EEA engineer is assigned to the project and will remain with the project through its completion. EEA engineers will work with the customer on design, software and other technical issues. When the design files are transferred to EEA, the assigned engineer will verify the design’s integrity and prepare it for place and route. The EEA Customer Engineering Group provides all technical customer-support services including:

  • Pre-Sale Technical Support • Software Documentation
  • Customer Training • Simulation Support
  • Design Assistance • Turnkey Design
  • Custom Cell Development • Design Verification
  • Place and Route • Static Timing Analysis
  • Scan Insertion and ATPG • JTAG Insertion
  • Netlist Conversion and Synthesis • Test Vector Conversion Œ EDA/CAE SUPPORT
  • Schematic Capture Œ Viewlogic (Synopsys): Viewdraw Œ EEA: Auklet (ECS)
  • Synthesis Œ Synopsys: DesignCompiler Œ Exemplar Logic: Leonardo
  • Simulation Œ Cadence: Verilog-XL Œ Synopsys: VSS (VHDL) Œ Avant!: Polaris (Purespeed) Œ Viewlogic (Synopsys): Viewsim Œ Modeltech: V-System (VHDL)
  • DFT Œ Synopsys: TestCompiler+ Œ Viewlogic (Synopsys): TestGen (Sunrise)
  • Place & Route Œ Cadence: GateEnsemble Œ Avant!: Aquarius-GA (Apollo)
  • Delay Calculation (Post-Route) Œ EEA: Peacock (EXDT)

EPSON ELECTRONICS AMERICA, INC. /c105 150 River Oaks Pkwy /c105 San Jose, CA 95134 /c105 Tel: (408) 922-0200 /c105 Fax: (408) 922-0238 ASIC S1L50000 ΠEDA/CAE SUPPORT (continued)

  • Static Timing Œ Synopsys: PrimeTime (DesignTime) Œ Viewlogic (Synopsys): Motive
  • Layout Verification Œ Cadence: Dracula/LVS

12 EPSON ELECTRONICS AMERICA, INC. /c105 150 River Oaks Pkwy /c105 San Jose, CA 95134 /c105 Tel: (408) 922-0200 /c105 Fax: (408) 922-0238 ASIC S1L50000 DATA SHEET NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of EPSON ELECTRONICS AMERICA, INC.. EEA reserves the right to make changes to this material without notice. EEA does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions there of may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. EPSON implies SEIKO EPSON CORPORATION and EPSON affiliated company.  EPSON ELECTRONICS AMERICA, INC. 1999 All Rights Reserved, Rev. 2.3 Trademark & Company Name XNF is registered trademark of Synopsys Inc. All other product names mentioned herein are trademarks and/or registered trademarks of their respective owners. For additional information about EEA ASIC products and services, or to discuss a solution tailored to your specific requirements, call your local EEA sales office or contact the factory. Northwest Regional Northeast Regional Southeast Regional Central Regional Sales Office & Design Center Sales Office & Design Center Sales Office Sales Office /c20/c24 /c19/c3/c53/c76/c89/c72/c85/c3/c50 /c68/c78/c86/c3/c51/c68/c85/c78/c90 /c68/c92 /c22/c19 /c20/c3/c40 /c71/c74 /c72/c90 /c68/c87/c72/c85/c3 /c51/c79/c68/c70/c72/c15/c3/c54 /c88/c76/c87/c72/c3 /c20/c21 /c19 /c23/c22 /c19/c19/c3 /c54/c76/c91/c3/c41/c82/c85/c78/c86/c3/c53/c82 /c68/c71/c15/c3 /c54/c88/c76/c87/c72/c3 /c23/c22 /c19/c15 /c20/c23 /c24/c19/c3 /c40/c17/c3/c36/c80 /c72/c85/c76/c70/c68/c81/c3 /c47/c68 /c81 /c72/c15/c3/c54/c88/c76/c87 /c72/c3/c20 /c24/c24 /c19 /c54/c68 /c81/c3/c45/c82/c86/c72/c15/c3/c38 /c36/c3/c28 /c24/c20 /c22/c23 /c58/c68/c78/c72/c73/c76/c72/c79 /c71/c15/c3/c48 /c36/c3/c19 /c20/c27 /c27/c19 /c53/c68/c79 /c72/c76/c74 /c75/c15/c3/c49/c38/c3 /c21/c26 /c25/c19 /c28 /c54/c70/c75/c68 /c88/c80 /c69 /c88/c85/c74/c15/c3/c44/c47/c3/c25 /c19 /c20/c26 /c22 /c51/c75 /c82/c81 /c72/c29/c3/c3/c3/c3/c3/c11/c23/c19/c27/c12/c3/c28 /c21 /c21/c16/c19 /c21/c19 /c19 /c51/c75 /c82/c81 /c72/c29 /c11/c26/c27 /c20/c12/c3/c21/c23 /c25/c16/c22 /c25 /c19/c19 /c51/c75 /c82/c81 /c72/c29 /c11/c28/c20 /c28/c12/c3/c26/c27 /c20/c16/c26 /c25 /c25/c26 /c51/c75 /c82/c81 /c72/c29 /c11/c27/c23 /c26/c12/c3/c24/c20 /c26/c16/c26 /c25 /c25/c26 /c41/c68/c91/c29/c3/c3/c3/c3/c3/c3/c3/c3/c3/c11/c23/c19/c27/c12/c3/c28/c21 /c21/c16/c19 /c21/c22 /c27 /c41/c68/c91/c29 /c11/c26/c27 /c20/c12/c3/c21/c23 /c25/c16/c24 /c23 /c23/c22 /c41/c68/c91/c29 /c11/c28/c20 /c28/c12/c3/c26/c27 /c20/c16/c25 /c26 /c26/c27 /c41/c68/c91/c29 /c11/c27/c23 /c26/c12/c3/c24/c20 /c26/c16/c26 /c25 /c19/c20 http://www.eea.epson.com