Logic IC

S1L30000

Epson Company

GATE ARRAY

Manufacturer: Epson Company

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Technical content

Datasheet sections

1.1 Features of the S1L30000 Series
1.2 Master Structure of the S1L30000 Series
1.3 Electrical Characteristics and Specifications of the S1L30000 Series
1.4 Overview of Gate Array Development Flow
2.1 Dividing Up Logic Between Chips
2.2 Determining Gate Density
2.3 Estimating the Number of Input/Output Terminals
2.4 Selecting the Master
2.5 Estimating the BCs That Can Be Used in Circuits Which Include RAM
3.1 Inserting I/O Buffers
3.2 The Use of Differentiating Circuits is Forbidden
3.3 Wired Logic is Forbidden
3.4 Hazard Countermeasures
3.5 Fan-out Constraints
3.6 Bus Circuits
3.7 Bus Hold Circuits
3.8 Schematic Capture Guidelines
3.9 Clock Tree Synthesis
3.10 ATPG (Auto Test Pattern Generation)
3.11 Restrictions and Constraints on VHDL/Verilog-HDL Netlist
3.11.1 Common Restrictions and Constraints
3.11.2 Restrictions and Constraints for Verilog Netlist
3.11.3 Restrictions and Constraints on VHDL Netlist
4.1 Types of Input/Output Cells in the S1L30000 Series
4.2 I/O Buffer Configurations with a Single Power Supply
4.3 Oscillation Circuit
5.1 Features
5.2 RAM Configuration and Simulation Model Selection
5.3 RAM Size
5.4 Investigating RAM Placement on Master Slice
5.5 Explanation of Functions
5.6 Delay Parameters

Datasheet sections

5.7 Timing Charts
5.8 RAM Test Method
5.9 Estimating RAM Current Consumption
5.10 RAM Symbols and How They Are Used
6.1 Considerations Regarding Circuit Initialization
6.2 Considerations Regarding Compressing the Test Patterns
6.3 RAM Test Circuit
6.3.1 RAM Test Patterns
6.4 Function Cell Test Circuits
6.4.1 Test Circuit Structures
6.4.2 Test Patterns
6.4.3 Test Circuit Data
6.5 Test Circuit Which Simplifies AC and DC Testing
7.1 Simple Delay Models
7.2 Load Due to Input Capacitance (Load A)
7.3 Load Due to Interconnect Capacitance (Load B)
7.4 Propagation Delay Calculations
7.5 Calculating Output Buffer Delay
7.6 Sequential Cell Setup/Hold Time
7.7 Chip Internal Skew
8.1 Testability Considerations
8.2 Waveform Types
8.3 Constraints on the Types of Test Patterns
8.3.1 Test Period
8.3.2 Input Delay
8.3.3 Pulse Width
8.3.4 Input Waveform Format
8.3.5 Strobe
8.4 Notes Regarding DC Testing
8.5 Notes Regarding the Use of Oscillation Circuits
8.6 Regarding AC Testing
8.6.1 Constraints Regarding Measurement Events
8.6.2 Constraints on the Measurement Locations for AC Testing
8.6.3 Constraints Regarding the Path Delay Which is Tested
8.6.4 Other Constraints
8.7 Test Pattern Constraints for Bi-directional Terminals
9.1 Calculating the Power Consumption
9.2 Constraints on Power Consumption
10.1 Estimating the Number of Power Supply Terminals
10.2 Number of Simultaneous Operations and Adding Power Supplies
10.3 Cautions and Notes Regarding the Layout of Terminals
10.3.2 Selecting I/O Cells

Datasheet sections

10.3.3 Cautions and Notes Regarding the Pin Layout
10.3.4 Examples of Recommended Pin Connections
11.1 The Method of Adapting to Dual Power Supplies
11.2 Power Supplies for Dual Power Operation
11.3 I/O Buffers Compatible with Dual Power Supplies
11.3.1 I/O Buffers for the LV
11.3.1.1 Input Buffers for the LV
11.3.1.2 Output Buffers for the LV
11.3.1.3 Bi-directional Buffers for the LV
11.3.2 I/O Buffers for the HV
11.3.2.1 Input Buffers for the HV
11.3.2.2 Output Buffers for the HV
11.3.2.3 Bi-directional Buffers for the HV
11.4 Calculating Delay Times in Dual Power Supply Systems
11.5 Cautions and Notes Regarding Power Consumption Calculations
11.6 Estimating the Number of Power Supply Terminals

S1L30000 Series DESIGN GUIDE DESIGN GUIDE GATE ARRAY S1L30000 Series ssue February,1996 D rch, 2001 in Japan C A

No part of this material may be reproduced or duplicated in any from or by any means without the written permission of EPSON. EPSON reserves the right to make changes to this material without notice. EPSON does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this marerial will be free from any patent or copyright infringement of a third party. This material or portions there of may contain techology or the subject relating to strategic products under the control of the Forign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of international Trade and Industry or other approval from another government agency. ©SEIKO EPSON CORPORATION 2001, All rights reserved.

The information of the product number change Configuration of product number Comparison table between new and previous number Starting April 1, 2001 the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales representative. DEVICES S1 L 60843 F 00A0 Packing specification Specifications Shape (∗2) Model number Model name (∗1) Product classification (S1:semiconductor) Previous number New Number SLA30000 series S1L30000 series SLA3018 S1L30182 SLA301T S1L30183 SLA3030 S1L30302 SLA303T S1L30303 SLA3042 S1L30422 SLA304T S1L30423 SLA3055 S1L30552 SLA305T S1L30553 SLA3075 S1L30752 SLA307T S1L30753 SLA3109 S1L31092 SLA310T S1L31093 SLA3125 S1L31252 SLA312T S1L31253 SLA3216 S1L32162 SLA321T S1L32163 ∗1: Model name ∗2: Shape K Standard Cell L Gate Array X Embedded Array B Assembled on board, COB, BGA C Plastic DIP D Bare Chip F Plastic QFP H Ceramic DIP L Ceramic QFP M Plastic SOP R TAB–QFP T Tape Carrier (TAB)

2 TSOP (Standard Bent)

3 TSOP (Reverse Bent)

Chapter 1: Overview GATE ARRAY S1L30000 SERIES EPSON DESIGN GUIDE Chapter 1 Overview The S1L30000 Series is a family of ultra high-speed VLSI CMOS gate arrays utilizing a 0.6 micron “sea-of-gates” architecture.

1.1 Features of the S1L30000 Series

Integration A maximum of 216, 216 gates (2 input NAND gate equivalent). (2-input power NAND, F/O = 2, Al = 2mm) (F/O = 2, Al = 2 mm) C L = 50 pF)
Process CMOS 0.6 µm Al 2/3 interconnect layers
I/F Levels Input/Output TTL/CMOS compatible
Input Modes TTL, CMOS, TTL Schmitt, CMOS Schmitt, PCI Pull-up and pull-down resistors can be equipped internally (2 types for each resistor value)
Output Modes Normal, 3-state, bi-directional, PCI
Output Drive I OL = 0.1, 1, 4, 8, 12, 24 mA, selectable (at 5.0 V) I OL = 0.05, 0.5, 2, 4, 6, 12 mA, selectable (at 3.3 V)
RAM Asynchronous 1-port, asynchronous 2-port
Dual Power Simultaneous 5.0 V/3.3 V operation supported using internal volt- age level-shifting circuitry. (Core operating at 3.0 V or 3.3 V, while the primary I/O’s selectably operate at the core voltage or 5.0 V.)

1.2 Master Structure of the S1L30000 Series

The S1L30000 Series comprises 8 types of masters, from which the customer is able to select the master most suitable. NOTE: *1: This is the value when there are no cells, such as RAM cells. The cell use effciency is dependent not only on the scope of the circuits, but also on the number of signals, the number of branches per signal, etc.; thus, use the values in this table only as an estimate. Table 1.1 Overview of the S1L30000 Series Master BC Total Number of Pads Number of Columns (X) Number of Rows (Y) 2-layer cell use ratio (U) *1 3-layer cell use ratio (U) *1 S1L30182/30183 18544 128 244 76 50% 88% S1L30302/30303 30846 160 318 97 50% 85% S1L30422/30423 42262 184 374 113 47% 83% S1L30552/30553 55341 208 429 129 47% 80% S1L30752/30753 75450 240 503 150 45% 78% S1L31092/31093 109080 256 606 180 45% 75% S1L31252/31253 125836 304 652 193 43% 75% S1L32162/32163 216216 376 858 252 40% 70%

Chapter 1: Overview EPSON GATE ARRAY S1L30000 SERIES DESIGN GUIDE

1.3 Electrical Characteristics and Speciﬁcations of the

*1: Applies to the 24 mA output buffer cells Table 1.2 S1L30000 Absolute Maximum Ratings SS = 0 V) Item Symbol Limits Unit Power Supply Voltage V DD -0.3 to 6.0 V Input Voltage V I -0.3 to V DD + 0.5 V Output Voltage V O -0.3 to V DD + 0.5 V Output Current/Pin I OUT ±25 (±50 *1) mA Storage Temperature T STG -65 to 150 o C Table 1.3 Recommended Operating Conditions for the S1L30000 Series (For Single Power Supplies) Item Symbol Min. Typ. Max. Unit Power Supply Voltage V DD 2.70 3.00 4.70 4.50 3.00 3.30 5.00 5.00 3.30 3.60 5.25 5.50 V Input Voltage V I V SS -- V DD V Operating Temperature Topr 0 -40 o C o C Normal Input Rising Time t ri -- -- 50 ns Normal Input Falling Time t fa -- -- 50 ns Schmitt Input Rising Time t ri -- -- 5 ms Schmitt Input Falling Time t fa -- -- 5 ms Table 1.4 Recommended Operating Conditions for the S1L30000 (For Dual Power Supplies) Item Symbol Min. Typ. Max. Unit Power Supply Voltage (High Voltage) HV DD HV DD 4.75 4.50 5.00 5.00 5.25 5.50 V V Power Supply Voltage (Low Voltage) LV DD LV DD 2.70 3.00 3.00 3.30 3.30 3.60 V V Input Voltage HV I LV I V SS V SS HV DD LV DD V V Operating Temperature Topr 0 -40 o C o C Normal Input Rising Time t ri -- -- 50 ns Normal Input Falling Time t fa -- -- 50 ns Schmitt Input Rising Time t ri -- -- 5 ms Schmitt Input Falling Time t fa -- -- 5 ms

Chapter 1: Overview GATE ARRAY S1L30000 SERIES EPSON DESIGN GUIDE * The quiescent current is a value for each master. For details, please see Tables 1.8 and 1.9. Table 1.5 Electrical Characteristics of the S1L30000 Series DD = 5 V, V SS = 0 V, Ta = -40 to 85 o Item Symbol Conditions Min. Typ. Max. Unit Quiescent Current * I DDS Quiescent Conditions -- -- 400 µA Input Leakage Current I LI -- -1 -- 1 µA Off State Leakage CurrentI OZ -- -1 -- 1 µA High Level Output VoltageV OH I OH = -0.1 mA (Type S), -1 mA (Type M), -4 mA (Type 1), -8 mA (Type 2), -12 mA (Type 3, 4) V DD = Min. V DD -0.4 -- -- V Low Level Output Voltage V OL I OL = 0.1 mA (Type S), 1 mA (Type M), 4 mA (Type 1), 8 mA (Type 2), 12 mA (Type 3), 24 mA (Type 4) V DD = Min. -- -- 0.4 V High Level Input Voltage V IH1 CMOS Level, V DD = Max. 3.5 -- -- V Low Level Input Voltage V IL1 CMOS Level, V DD = Min. -- -- 1.0 V High Level Input Voltage V T1+ CMOS Schmitt, V DD Low Level Input Voltage V T1- CMOS Schmitt, V DD Hysteresis Voltage V CMOS Schmitt, V DD High Level Input Voltage V IH2 TTL Level, V DD = Max. 2.0 -- -- V Low Level Input Voltage V IL2 TTL Level, V DD = Min. -- -- 0.8 V High Level Input Voltage V T2+ TTL Schmitt, V DD Low Level Input Voltage V T2- TTL Schmitt, V DD Hysteresis Voltage V TTL Schmitt, V DD High Level Input Voltage V IH3 PCI Level, V DD = Max. 2.0 -- -- V Low Level Input Voltage V IL3 PCI Level, V DD = Min. -- -- 0.8 V High Level Output CurrentI OH3 PCI Response, V OH = 1.4 V, V DD = Min. V OH = 3.1 V, V DD = Max. -44 -142 mA mA Low Level Output Current I OL3 PCI Response, V OL = 2.2 V, V DD = Min. V OL = 0.71 V, V DD = Max. 206 mA mA Pull-up Resistance R PU V I = 0 V Type 1 25 50 100 k Ω Type 2 50 100 200 Pull-down Resistance R PD V I = V DD Type 1 25 50 100 k Ω Type 2 50 100 200 High Level Maintenance Current I BHH1 Bus Hold Response, V IN = 3.5 V (CMOS System) V DD = Max. -- -- -90 µA Low Level Maintenance Current I BHL1 Bus Hold Response, V IN = 1.0 V (CMOS System) V DD = Max. -- -- 60 µA High Level Maintenance Current I BHH2 Bus Hold Response, V IN = 2.0 V (TTL System) V DD = Max. -- -- -110 µA Low Level Maintenance Current I BHL2 Bus Hold Response, V IN = 0.8 V (TTL System) V DD = Max. -- -- 50 µA High Level Reversal CurrentI BHHO Bus Hold Response, V DD = Max. -900 -- -- µA Low Level Reversal CurrentI BHLO Bus Hold Response, V DD = Max. 530 -- -- µA Input Terminal CapacitanceC I f = 1 MHz V DD = 0 V -- -- 12 pF Output Terminal CapacitanceC O f = 1 MHz, V DD = 0 V -- -- 12 pF Input/Output Terminal Capacitance C IO f = 1 MHz, V DD = 0 V -- -- 12 pF

Chapter 1: Overview EPSON GATE ARRAY S1L30000 SERIES DESIGN GUIDE * The quiescent current is a typical value for each master. For details, please see Tables 1.8 and 1.9. Table 1.6 Electrical Characteristics of the S1L30000 Series (VDD = 3 V ± 0.3 V, VSS = 0 V, Ta = -40 to 85oC) Item Symbol Conditions Min. Typ. Max. Unit Quiescent Current * IDDS Quiescent Conditions -- -- 260 µA Input Leakage Current ILI -- -1 -- 1 µA Off State Leakage Current IOZ -- -1 -- 1 µA High Level Output Voltage VOH IOH = -0.05 mA (Type S), -0.5 mA (Type M), -1.8 mA (Type 1), -3.5 mA (Type 2), -5 mA (Type 3, 4) V DD = Min. VDD -0.3 -- -- V Low Level Output Voltage VOL IOL = 0.05 mA (Type S), 0.5 mA (Type M), 1.8 mA (Type 1), 3.5 mA (Type 2), 5 mA (Type 3), 10 mA (Type 4) V DD = Min. -- -- 0.3 V High Level Input Voltage VIH1 CMOS Level, VDD = Max. 2.0 -- -- V Low Level Input Voltage VIL1 CMOS Level, VDD = Min. -- -- 0.8 V High Level Input Voltage VT1+ CMOS Schmitt, VDD = 3.0 V -- -- 2.3 V Low Level Input Voltage VT1- CMOS Schmitt, VDD = 3.0 V 0.5 -- -- V Hysteresis Voltage VH1 CMOS Schmitt, VDD = 3.0 V 0.1 -- -- V High Level Input Voltage VIH3 PCI Level, VDD = Max. 1.58 -- -- V Low Level Input Voltage VIL3 PCI Level, VDD = Min. -- -- 0.88 V High Level Output Current IOH3 PCI Response, VOH = 0.81 V, VDD = Min. VOH = 2.31 V, VDD = Max. -33 -105 mA mA Low Level Output Current IOL3 PCI Response, VOL = 1.62 V, VDD = Min. VOL = 0.60 V, VDD = Max. 125 mA mA Pull-up Resistance R PU VI = 0 V Type 1 50 100 200 kΩType 2 100 200 400 Pull-down Resistance R PD VO = VDD Type 1 50 100 200 kΩType 2 100 200 400 High Level Maintenance Current IBHH Bus Hold Response, VIN = 2.0 V VDD = Max. -- -- -32 µA Low Level Maintenance CurrentIBHL Bus Hold Response, VIN = 0.8 V VDD = Max. -- -- 27 µA High Level Reversal CurrentIBHHO Bus Hold Response, VDD = Max. -290 -- -- µA Low Level Reversal Current IBHLO Bus Hold Response, VDD = Max. 170 -- -- µA Input Terminal Capacitance C I f = 1 MHz, VDD = 0 V -- -- 12 pF Output Terminal CapacitanceC O f = 1 MHz, VDD = 0 V -- -- 12 pF Input/Output Terminal Capacitance C IO f = 1 MHz, VDD = 0 V -- -- 12 pF

Chapter 1: Overview GATE ARRAY S1L30000 SERIES EPSON 5 DESIGN GUIDE * The quiescent current is a typical value for each master. For details, please see Tables 1.8 and 1.9. Table 1.7 Electrical Characteristics of the S1L30000 Series (VDD = 3.3 V ± 0.3 V, VSS = 0 V, Ta = -40 to 85oC) Item Symbol Conditions Min. Typ. Max. Unit Quiescent Current * IDDS Quiescent Conditions -- -- 290 µA Input Leakage Current ILI -- -1 -- 1 µA Off State Leakage Current IOZ -- -1 -- 1 µA High Level Output Voltage VOH IOH = -0.05 mA (Type S), -0.5 mA (Type M), -2 mA (Type 1), -4 mA (Type 2), -6 mA (Type 3, 4) V DD = Min. VDD -0.3 -- -- V Low Level Output Voltage VOL IOL = 0.05 mA (Type S), 0.5 mA (Type M), 2 mA (Type 1), 4 mA (Type 2), 6 mA (Type 3), 12 mA (Type 4) V DD = Min. -- -- 0.3 V High Level Input Voltage VIH1 CMOS Level, VDD = Max. 2.2 -- -- V Low Level Input Voltage VIL1 CMOS Level, VDD = Min. -- -- 0.8 V High Level Input Voltage VT1+ CMOS Schmitt, VDD = 3.3 V -- -- 2.4 V Low Level Input Voltage VT1- CMOS Schmitt, VDD = 3.3 V 0.6 -- -- V Hysteresis Voltage VH1 CMOS Schmitt, VDD = 3.3 V 0.1 -- -- V High Level Input Voltage VIH3 PCI Level, VDD = Max. 1.71 -- -- V Low Level Input Voltage VIL3 PCI Level, VDD = Min. -- -- 0.98 V High Level Output Current IOH3 PCI Response, VOH = 0.90, VDD = Min. VOH = 2.52 V, VDD = Max. -36 -115 mA mA Low Level Output Current IOL3 PCI Response, VOL = 1.8 V, VDD = Min. VOL = 0.65 V, VDD = Max. 137 mA mA Pull-up Resistance R PU VI = 0 V Type 1 45 90 180 kΩType 2 90 180 360 Pull-down Resistance R PD VI = VDD Type 1 45 90 180 kΩType 2 90 180 360 High Level Maintenance Current IBHH Bus Hold Response, VIN = 2.0 V VDD = Max. -- -- -40 µA Low Level Maintenance Current IBHL Bus Hold Response, VIN = 0.8 V VDD = Max. -- -- 30 µA High Level Reversal CurrentIBHHO Bus Hold Response, VDD = Max. -350 -- -- µA Low Level Reversal CurrentIBHLO Bus Hold Response, VDD = Max. 210 -- -- µA Input Terminal CapacitanceC I f = 1 MHz, VDD = 0 V -- -- 12 pF Output Terminal CapacitanceC O f = 1 MHz, VDD = 0 V -- -- 12 pF Input/Output Terminal Capacitance CIO f = 1 MHz, VDD = 0 V -- -- 12 pF

Chapter 1: Overview

6 EPSON GATE ARRAY S1L30000 SERIES

H IDDS : The quiescent current between HVDD and VSS LIDDS : The quiescent current between LVDD and VSS * For the case of dual power supplies, the sum of the quiescent current for both of the voltages used is given as the total quiescent current (HIDDS + LIDDS ). Table 1.8 Quiescent Current in the S1L30000 Series (For Single Power Supplies) (Ta = -40 to 85oC) Master 5 V ± 10% IDDS Max. 3.3 V ± 0.3 V IDDS Max. 3.0 V ± 0.3 V IDDS Max. Unit S1L30182/30183 S1L30302/30303 S1L30422/30423 300 220 200 µA S1L30552/30553 S1L30752/30753 S1L31092/31093 400 290 260 µA S1L31252/31253 S1L32162/32163 600 430 400 µA Table 1.9 Quiescent Current for the S1L30000 Series (For Dual Power supplies) (Ta = -40 to 85 oC) Master 5 V ± 10% HIDDS Max. 3.3 V ± 0.3 V LIDDS Max.

5.0 V ±10%

HIDDS Max. 3.0 V ± 0.3 V LIDDS Max. Unit S1L30182/30183 S1L30302/30303 S1L30422/30423 80 220 80 200 µA S1L30552/30553 S1L30752/30753 S1L31092/31093 100 290 100 260 µA S1L31252/31253 S1L32162/32163 160 430 160 400 µA

Chapter 1: Overview GATE ARRAY S1L30000 SERIES EPSON 7 DESIGN GUIDE

1.4 Overview of Gate Array Development Flow

Gate arrays are developed jointly by the customer and EPSON. System design, circuit design, and test pattern design is performed by the customer, based on various reference materials, including the cell libraries provided to the customer by EPSON. When interfacing with EPSON, the customer is to check the schematic data in advance based on the supplied data-release checklist, and then provide the necessary data and documents to EPSON. The customer performs simulations using EDA software it has in its possession or Auklet,* while EPSON carries out the place and route and successive work. NOTE)*: Auklet is EPSON’s ASIC design support system that runs on the MS-Windows 95/98, MS-Windows NT platforms. The currently available EDA software capable of performing simulations is as follows:

Verilog-XL (*1)
VSS(*2)
ModelSim(*3) NOTE)*1: Verilog-XL is a registered trademark of Cadence Desgin Systems Corporation. NOTE)*2: VSS is a refistered trandemark of Synopsys, Incorporated. NOTE)*3: ModelSim is a registered trademark of Model Technology. For more information, refer to the Gate Array Technical Guide or contact to our sales ofﬁce for tecnical support.

Chapter 1: Overview

8 EPSON GATE ARRAY S1L30000 SERIES

The process ﬂow of the gate array development process is shown below: Customer Product Plan Functional Spec. Distributor (Interface) EPSON Make Masks Verification G/A development request Simulation file Simulation list Customer Spec (Sign off) NG NG OK NG OK NG NG OK OK Circuit Design Test Pattern Design Logical Check (Simulation) Verification ( ) is based on customer’s requirement. Overall evaluation Approve the Prototype Protorype Approval Delivery Spec Delivery Spec Approval Approve Delivery Spec Verification Schematic Pin Assinment Timing wave from Marking diagram P/O Timing Check (Simulation) Place & Rout PostSimulation TS (Test Sample) fabrication ES (Engineering Sample) fabrication MP Setup MP Delivery Spec. publication Functional evaluation Delay-time analysis Delay-time analysis

Chapter 2: Estimating Gate Density and Selecting the Master GATE ARRAY S1L30000 SERIES EPSON 9 DESIGN GUIDE Chapter 2 Estimating Gate Density and Selecting the Master Methods and guidelines are described below to assist in deﬁning the logic which will be integrated into a gate array, estimating the array requirements, and determining the appropriate master for a given application.

2.1 Dividing Up Logic Between Chips

When extracting logic, which is to be integrated into gate arrays from the system being created by the user, the logic should be selected with the following criteria in mind.

Integration Criteria (1) Quantity of logic to integrate (2) Quantity of input, output and bi-directional signals required (3) Package to be used (4) Power consumption Generally, the larger the gate density, the more power is consumed, and the more input and output terminals required. Because of this, it may be better, from the perspective of total cost or from the perspective of power consumption, etc., to divide the circuit into multiple chips, rather than forcing them into a single chip.

2.2 Determining Gate Density

In the case of gate arrays, the scope of the array is deﬁned as the sum of gates or basic cells (BCs) used. One gate or basic cell is typically deﬁned as being equivalent to one two-input NAND gate (or four transistors). The “S1L30000 Series MSI Cell Library” can be used as reference to facilitate gate count estimation.

2.3 Estimating the Number of Input/Output Terminals

Deﬁning the number of I/O signals, test signals and power pins required for a given application has a bearing on the array member suitable for that application. The appropriate number of I/O pads must be available on the array member to satisfy the application signal requirements. Estimate the number of power supply pins using the method discussed in Chapter 10.

Chapter 2: Estimating Gate Density and Selecting the Master

10 EPSON GATE ARRAY S1L30000 SERIES

2.4 Selecting the Master

Select the appropriate master from the CMOS Device Catalog S1L30000 Series tables, based on the estimated number of BCs, the number of required input and output pins (including power supply pins) and the package to be used. The actual number of BCs (BC A) which can be used for each device type is estimated using the following formula from the gross number of BCs (BCG ) loaded on each master (shown in Table 1.1 of the previous chapter) and the cell utilization ratio (U). BC A = U x BCG where U= 0.50 to 0.60 for double layer metal (DLM) or U= 0.65 to 0.75 for triple layer metal (TLM) NOTE: When a RAM circuit is included, this estimate should be made after refering to the following section and after refering to Chapter 5. Also, when the estimate is for a circuit which will use dual power supplies, please refer to Chapter 11.

2.5 Estimating the BCs That Can Be Used in Circuits Which

RAM blocks, in comparison to MSI cells, are extremely large and have ﬁxed shapes (deﬁned vertical and horizontal dimensions). Because of this, some RAM blocks which may appear to ﬁt on the chip because of calculations based on the number of BCs may, in actuality, not be placable on a given master. Thus, the ﬁrst decision is that of whether or not the RAM conﬁguration is available on a given master. Please refer to Chapter 5. Once the masters which can accommodate the RAM have been selected, it becomes possible to estimate the number of BCs (BC AWR ) of random logic (excluding RAM) available using the formula below. BC AWR = 0.9 x U x (BCG - BCRAM ) where BCAWR is the number of BCs available for random logic BC G is the gross BCs available on a mater (raw gates) BC RAM is the BC use of RAM(s) (See Chapter 5 for BC calculation) U is the utilization ratio (0.50 to 0.60 for DLM, 0.65 to 0.75 for TLM) NOTE: Actual BCs available (BCAWR ) is design dependent. Use the formula above for estimation purposes only. Please consult EPSON for design specific information.

Chapter 3: Cautions and Notes Regarding Circuit Design GATE ARRAY S1L30000 SERIES EPSON 11 DESIGN GUIDE Chapter 3 Cautions and Notes Regarding Circuit Design

3.1 Inserting I/O Buffers

All external (or primary) input, output and bi-directional signals must be attached to I/O buffers. Due to CMOS IC’s extreme vulnerability to electrical static discharge (ESD), protection circuitry has been incorporated within the I/O buffers to ensure device reliability and quality.

3.2 The Use of Differentiating Circuits is Forbidden

The propagation delay (tpd) of internal cells within a gate array vary, depending on process variance during mass production and environment variance during device usage. Differentiating circuits such as the one shown in Figure 3.1 should be avoided due to difﬁculties associated with control of the resultant pulse width relative to variances in propagationdelays through each logic element. Figure 3.1 Example of a Differentiating Circuit

3.3 Wired Logic is Forbidden

Wired logic, available in bipolar devices, is not allowable in the S1L30000 Series, a CMOS technology. Consequently, cell output pins cannot be wired together, such as shown in Figure 3.2, with the exception of internal 3-state bus elements. Figure 3.2 Examples of Forbidden Wired Logic

Chapter 3: Cautions and Notes Regarding Circuit Design

12 EPSON GATE ARRAY S1L30000 SERIES

3.4 Hazard Countermeasures

In circuits such as decoders and multiplexors which are structured from combinational functions such as NAND gates or NOR gates, extremely short pulses can be produced by differences in the gate delay times. These short pulses are called hazards, and when these hazards propagate to clock, reset or set pins of sequential elements, malfunctions may occur. Because of this, it is necessary to use caution when designing circuits which may produce hazards, creating circuit structures which do not propagate hazards, having decoder circuits with “enable” terminals, etc.

3.5 Fan-out Constraints

Cell propagation delay is determined, in part, by the load capacitance at the output terminals. When the load capacitance is too large, the propagation delay increases, and malfunctions may result. Because of this, there are limitations on the number of loads which can be connected to the output terminals of each cell, and these limitations are referred to as “fan-out constraints.” The input terminal capacitance of each gate differs from gate input to gate input. The input capacitance of each gate input is deﬁned relative to the input capacitance of an inverter (which is deﬁned as being equal to 1) is called the “fan-in.” Circuits should be designed so that the sum of the fan-ins connected to the output terminals of each gate does not exceed the fan-out constraints of that output terminal. Also, high speed clock lines (40 MHz or more), should be designed so that the output terminal load of the associated logic gates is about half of the fan-out constraints to ensure high performance.

3.6 Bus Circuits

Internal 3-state bus circuits are constructed, using 3-state logic gates. The 3-state logic gates output terminals can be wired together if at all times one, and only one 3-state logic gate is active at a given time (while the remaining 3-state logic gate outputs are put in high impedance state). This circuit allows multiple signal sources to share a given net at different time intervals during circuit operation. Please keep the following recommendations in mind when bus circuits are used: Notes Regarding the Use of Bus Circuits (1) Bus cells cannot be used except in bus circuits. (Please refer to Table 3.1 regarding S1L30000 Series bus cells.) (2) When bus cells are used, please attach one (and only one) BLT cell (bus latch) to each 3- state bus net. (3) A maximum of 35 bus cells can be attached to a single bus. (Fan-out = 32) (4) One, and only one, 3-state cell can be active (output terminal driving a logic 0 state or logic 1 state) at a time. All other 3-state bus cells connected to that net must be inactive (output terminal in high impedance Z state).

Chapter 3: Cautions and Notes Regarding Circuit Design GATE ARRAY S1L30000 SERIES EPSON 13 DESIGN GUIDE (5) If all 3-state bus cells are inactive (output terminals in high impedance Z state) on a given bus net, the BLT (bus latch) will maintain the last valid state (either logic 1 state or logic 0 state). The BLT function is merely to avoid bus ﬂoating, therefore, the processing of inter- nal 3-state bus latch data must be performed while 3-state bus drivers are active rather than processing data while BLTs control bus data. (6) In order to improve testability, design the 3-state bus such that it can be initialized easily and quickly during device testing. This can be done by utilizing a separate test pin to con- trol the 3-state bus, or by instantiating default 3-sate bus drivers. (7) The 3-state cell control terminals must change only once during a single test vector event (cycle) to allow test vector set usage during IC device testing. (8) High speed 3-state bus operation may be inhibited by large fan-out loading on 3-state bus drivers. Figure 3.3 Example of Bus Cell Circuit Structure Table 3.1 Table of S1L30000 Series Bus Cells Cell Type Cell Name

1 Bit 4 Bit 8 Bit

Bus latches BLT 1 BLT 4 BLT 8 Bus drier TSB, TSBP T244H T244 Inverting bus driver TSV, TSVP T240H T240 Transparent latches with reset and 3-state output - T373H T373 D-ﬂip ﬂops with reset and 3-state output - T374H T374 1-bit RAM RM1 - - BLT1 TSB TSB NA2 IN1

Chapter 3: Cautions and Notes Regarding Circuit Design

14 EPSON GATE ARRAY S1L30000 SERIES

3.7 Bus Hold Circuits

In the S1L30000 Series, I/O cells with an added bus hold function (to maintain the output signal pin data) have been provided, so that output signal pin (or bi-directional signal pin) does not enter high-impedance state. However, to prevent these circuits from affecting normal operation, the latching capability of the bus hold circuit is weak; thus, the stored data output should not be used as valid data. This pin state can be overriden easily by an externally supplied signal. Please refer to the S1L30000 Series electrical characteristics in Tables 1.5 and 1.7 regarding the output maintenance current of the bus hold circuit. Figure 3.4 Examples of Structures of Bus Hold Circuits

3.8 Schematic Capture Guidelines

Please adhere to the following conventions when designing an ASIC via manual schematic entry:

Use logic cells found in Gate Array S1L30000 Series MSI Cell Library.
Use orthogonal (not oblique) connections when wiring logic cells to one another.
Primary uni-directional I/O signalnames and bi-directional I/O signalnames must be between 2 and 32 characters in length, and must begin with an alphabetic character. UC1HUO1H A E TD TE TS P N Bidirectional Input signal Output Enable for Test A E TD TE TS P N Output Enable for Test signal Output signal PDV2TPDV2T (b) UC1H + PDV2T(a) UO1H + PDV2T

Chapter 3: Cautions and Notes Regarding Circuit Design GATE ARRAY S1L30000 SERIES EPSON 15 DESIGN GUIDE

3.9 Clock Tree Synthesis

(1) Overview Clock Tree Synthesis is a support that automatically inserts the ClockTree into the buffer group that optimizes the skew and delay time of “Clock Line”. If a customer has a pro- gram to insert ClockTree to adjust the Fan-out of “ClockLine”, clock skew may be large, so the P & R tool is started and the placing and routing for designing the gate array are exe- cuted voluntarily. Also, the propagation delay time may be longer than estimated because there are many cases it is difﬁcult to maintain a good balance between the wire intercon- necting load and the intrinsic cell delay. The Clock Tree Synthesis is used to solve this problem. Refer to the actual results to use the Clock Tree Synthesis as follows: (2) How to Examine the Clock Tree Synthesis When the clock tree is inserted automatically, the customer must insert the special buffer to the Clock Line for the following three purposes.

Judging the place to insert the Clock Tree Synthesis.
Estimating the delay time of the Clock Tree inserted and execute the simulation of vir- tual wire interconnecting level (pre-simulation).
Back annotate the delay time of the inserted Clock Tree to accurately estimate the post-simulation. Select the special buffer for the Clock Tree Synthesis in the table of special buffers men- tioned later. Then insert the special buffer selected from the table into the Clock Line tak- ing into consideration the restriction or notes mentioned later and the same placing as the normal cells. Otherwise, if the logic are designed by HDL, as the special buffer can not insert automatically the Clock Line, assign directly the HDL of the content using the script language. Note that another buffer is not combined in the clock Line inserted in the spe- cial buffer, and execute the following command: set_don’t_touch_net net_name

Chapter 3: Cautions and Notes Regarding Circuit Design

16 EPSON GATE ARRAY S1L30000 SERIES

[The special buffer] Select the special buffer from the table below corresponding to the estimated number of fan- outs. Note 1: The value “K” (load delay of fan-out) of these cells is set “0” at the pre-simulation. Note 2:The number of fan-outs of these cells is set to the infinity. Note 3: Please consider that the load delay for the number of fan-outs is not accurately and only estimated. [Restriction and Notes]

Target series: S1L9000F , S1L30000, S1L35000, S1L50000
The special buffer can not be used for any purpose other than the Clock Tree Synthesis.
The Clock Tree Synthesis can also be used for data line and other control signals. How- ever, when the nets used in the synthesis are increased, the skew and propagation delay also became larger. Therefore, the number of nets to be used in the synthesis is less than 10 and the net which has a critical and large fan-out should be used.
If a net which has a small fan-out is used for the Clock Tree Synthesis, the propagation delay and skew may be larger. The target net with fan-out should be used more than scores.
As there are cases corresponding to the skew adjustment between multiple Clock lines, contact EPSON for handing in the detail schematic (the clock line conﬁguration is described very clearly) to be checked.
For the Clock group separated into multiple Clock Lines with the same Root of Clock by the gates, contact EPSON to obtain the materials of “Gated Clock Tree Synthesis Expla- nations”. S1L9000F , S1L30000, S1L50000 Series Cell Name To Max. (ns) Estimated number of fan-out CRBF2 2.00 0 to 500 CRBF3 3.00 500 to 3000 CRBF4 4.00 3000 to 10000 CRBF5 5.00 Over 10000 CRBF6 6.00 CRBF7 7.00 CRBF8 8.0 S1L35000 Series Cell Name To Max. (ns) Estimated number of fan-out XCRBF2 2.00 0 to 500 XCRBF3 3.00 500 to 3000 XCRBF4 4.00 3000 to 10000 XCRBF5 5.00 Over 10000 XCRBF6 6.00 XCRBF7 7.00 XCRBF8 8.0

Chapter 3: Cautions and Notes Regarding Circuit Design GATE ARRAY S1L30000 SERIES EPSON 17 DESIGN GUIDE [Necessary Information from a Customer] Send the following information until the data is released, because the Clock Tree Synthesis is used efﬁciently. Note 1: The target values on the table are needed to estimate to use the Synthesis. The target values are not always satisfied. Note 2: If there is no target values, write the comments for each item in the table. Example: As smaller as possible Instance name of CRBF* Target skew value Target propagation delay (Min./Max.)

Chapter 3: Cautions and Notes Regarding Circuit Design

18 EPSON GATE ARRAY S1L30000 SERIES

[Imaging schematic] The schematic created by a customer and the layout schematic after executing the Clock Tree Synthesis in EPSON are shown as follows: Figure 3.5 Layout schematic after executing the Clock Tree Synthesis in EPSON Clock Root Combining with the Clock Tree Back annotation of propagation delay CRBF* Figure 3.5 A customer’s shematic

Chapter 3: Cautions and Notes Regarding Circuit Design GATE ARRAY S1L30000 SERIES EPSON 19 DESIGN GUIDE

3.10 ATPG (Auto Test Pattern Generation)

(1) Introduction The so-called “ATPG” means tools to automatically generate test patterns that are released by tool-producing vendors. The “TestGen” of the tool executed to “ATPG” sup- plied by Synopsys Inc. is used in ASIC design at EPSON. By using “TestGen”, the scan- ning circuit can be inserted to the original circuit and the test patterns can be generated automatically. The word “control” described in this chapter is used to specify free level to the target pin without passing to the sequential circuit. This “control” meaning should be noted because it can not be used for dividing clocks and so on needed in some cycles to set the state. For example, when using “control” where a clock of each ﬂip-ﬂop circuit can be controlled externally, the circuit means that the external input clock (source clock) can reach each ﬂip-ﬂop circuit. (2) Outline When the scanning circuit is inserted into the design ruled circuit for “ATPG” support, some faults are detected in the circuit when using the “ATPG” tool. However, internal nodes are forced to move from external pins through the scanning circuit and are observed. Therefore, the test patterns outputted from the “ATPG” tool can not be used to check the operations of the user’s circuit. Users need to create the test patterns to check the standard operations of their circuit. The test patterns outputted from the “ATPG” tool can only be used to reach the level of the fault detecting rate in the circuit. When using the “ATPG” tool, the test patterns to get 100% of fault detecting can be gener- ated, except that nodes can not to be tested and faults can not be tested logically. The “ATPG” method is adapted to full scanning using “MUXSCAN type FF (Flip-ﬂop)”. (3) Fault Detecting Deﬁnition The single stuck-at fault mode is used. SA0: stack-at-zero fault (shorted) SA1: stack-at-one fault (shorted) The following test pattern circuit is created using TestGen of the ATPG tool. The circuit set to SA0, SA1 to respective nodes is created to observe detection of faults. In other words, a test pattern circuit should be created that causes malfunctions when each node is set to “0” or “1”. Figure 3.6 Example of Untestable fault S-a-1 S-a-0/1 IN1 D C DF S-a-0 Q XQ D C DF Q XQ

Chapter 3: Cautions and Notes Regarding Circuit Design

20 EPSON GATE ARRAY S1L30000 SERIES

(4) Design Flow (1/2) Figure 3.7 ATPG flow when designing by Auklet ATPG Rule Check Seiko EpsonCustomer ATPG Application Note Temporary netlist ATPG Check Sheet Temporary Pin Assignment Circuit Block Diagrams Verification Logical check Expected Values of Input Patters Netlist Circuit Data Netlist Circuit Data Pin Assignment ATPG Auklet Schematic Capture TP Creation Auklet ATPG Rule Check Pre-Simulation ATPG rule check ATPG Rule Check Scan Insersion Fault Detection Verification after ATPG OK or NG P & R P & R Clock Tree Synthesis Post-Simulation Post-Simulation Result Post-Simulation Verification Sign off Verification of Fault Detection Rate

Chapter 3: Cautions and Notes Regarding Circuit Design GATE ARRAY S1L30000 SERIES EPSON 21 DESIGN GUIDE (4) Design Flow (2/2) Figure 3.8 ATPG flow when designing by logic synthesis ATPG Rule Check Seiko EpsonCustomer ATPG Application Note Temporary Netlist ATPG Check Sheet Verification Logical check Netlist Circuit Data ATPG HDL Design Verilog-XL RTL Creation TP Creation ATPG Rule Check Logic Synthesis Pre-Simulation ATPG Rule Check ATPG Rule Check Scan Insersion Fault Detection OK or NG P & R P & R Clock Tree Synthesis Post-Simulation Post-Simulation Result List Post-Simulation Verification Sign off Temporary Pin Assignment Circuit Block Diagrams Expected Values of Input Patters Netlist Circuit DataPin Assignment Verification after ATPG Verification of Fault Detection Rate

Chapter 3: Cautions and Notes Regarding Circuit Design

22 EPSON GATE ARRAY S1L30000 SERIES

(5) Test pattern composition created by ATPG There are two test patters generated by ATPG, and their modes must be exchanged at the scanning enable input pin (SCANEN). The SCANEN pin needs to be used as the dedi- cated input pin because it is connected when the circuit is scanned.

Scanning shift mode This mode is used when the memory element (scan FF) in the circuit composed for the shift register is inputted or outputted data.
Scanning test mode This mode is used when the data inputted to the memory element on the scanning shift mode is used to operate on the circuit by the clock input. (6) I/O Pins for ATPG If two pins of SCANEN and ATPGEN are used, the ATPG can execute very efﬁciently. As a result, the delivery time is shortened and the fault detection rate goes up. The following explanation describes the pins needed to execute the ATPG.
Scan Enable Input Terminal (SCANEN) This pin is used to exchange the scan shift mode with the scan test mode. It is also used when resetting or setting to FF (Flip Flop) and to ﬁx the bi-directional I/O exchange signals while shifting each FF to scan. This pin must be ready for the dedi- cated pin because it is deﬁnitely needed to scan FF .
Test input pin for ATPG (ATPGEN) This pin is used to make the circuit suitable for ATPG. For example, the asynchronous part of the circuit should be ﬁxed by using the test input pin and if the clock line cannot be controlled externally, it can be controlled by using the pin for exchange. If the orig- inal circuit is adequate to the rule of ATPG, the pin is not needed for ATPG and the dedicated pin is used.
Scan data input pin This scan data input pin is used to set the data to the shift register generated by scan- ning FF . In case of multi-scan FF , the number of scan data input pins is increased. These pins can be shared with others. However, they can not be used to share with the control pin to set or reset to the scan data or the clock and other pins to scan FF . If the scan data input pins are used to share with the bi-directional pins, they should be designed to be always used for input by utilizing the ATPGEN pin.
Scan data output pin This scan data output pin is used to read the data from the shift register generated by scanning FF . In case of multi-scan FF , the number of scan data output pins is increased. These pins can be shared with other pins. If the scan data output pins are used to share with bi-directional pins, they should be designed to be always used for output by considering utilizing the ATPGEN pin.
Scan clock input pin This pin is the clock input pin at the test pattern generated by ATPG. This pin usually utilizes the system clock in normal operation.

Chapter 3: Cautions and Notes Regarding Circuit Design GATE ARRAY S1L30000 SERIES EPSON DESIGN GUIDE (7) Logic circuit design rule for ATPG (DFT) To operate ATPG, the logic circuits should be scanned. According to the following rules, the original circuits that are observed to check very well should be designed. The follow- ing contents show a concrete example, so please contact EPSON Sales division if logic circuit design has difﬁculty handling the ATPG design.

Target series: S1L50000, S1L30000, S1L9000F , S1X50000
Only one pin is needed for the dedicated pin used as the scan enable pin (SCANEN).
Please send the trial data to EPSON about a week before sending the formal data. EPSON will check the trial data of the logic circuit before getting the formal data. The process after obtaining the formal logic circuit data should be highly efﬁcient and the fault detection rate of the logic circuit must go up.
The clock, setting and resetting to the scan data in all of FF scanned must be control- led directly at the external pin. If they cannot be controlled, use the ATPG test pin (ATPGEN) separated from the SCANEN pin and design the logic circuit so that it can be controlled. When the logic circuit is conﬁgured to input multiple clocks from the external pin, the ATPGEN pin should be designed to be operated again in the active state by inputting only one clock for all FF scanned. However, if there is only one circuit, please contact EPSON sales division about the multiple circuits in this case. Figure 3.9 Example of Clock Line Process
It is forbidden to design the circuit used to scan FF at the original circuit.
Cope with the clock skew of clock nets by using Clock Tree Synthesis.
Allocate I/O cells at the top of the hierarchical design. CLK IBC IBCD1 ATPGEN LOGIC AO24A CRBF* DQ CX Q DF DQ CX Q DF

Chapter 3: Cautions and Notes Regarding Circuit Design EPSON GATE ARRAY S1L30000 SERIES DESIGN GUIDE

Do not use the internal 3-state bus. The internal 3-state bus should be composed of the multiplexer and so on. How- ever, if the circuit design needs an internal 3-state bus by any means, use the ATP- GEN pin and the bus circuit must be designed never to cause a contention. When the circuit is designed by using the internal 3-state bus, the fault detection rate in the circuit does not always go up. Please contact EPSON sales division if a high fault detection rate is desired. Figure 3.10 Process Example of Internal 3-state
When using the macro cells, for example-RAM, ROM, Mega cell and so on, design the circuit inserted in the scanned FF before or after the I/O ports of the macro cells. If circuit design is impossible, the faults can not often be detected before or after the macro cells.
Keep away using MSI macro cells included in the Flip ﬂop, for example-T175, A161 and so on. The MSI cells can not scan. Do not use them if a high fault detection rate is desired.
Do not use the asynchronous circuit and a circuit that causes racing at the RS latch, differentiating circuit and so on. If these circuits are used, ﬁx their output by using the ATPGEN pin. Furthermore, as the fault detection rate is not always up, do not use the circuit if a high fault detection rate is desired.
Fix the latch cell by using the ATPGEN so that it is always through. As the fault detection rate is not always up, do not use the circuit if a high fault detection rate is desired.
Design the bi-directional pin to be state of input in the scan shifting mode. If the bi-directional pin must be assigned to the scan data input and output pins, ﬁx it to be state of each condition. IBCD1 ATPGEN BLT1 TSB TSB

Chapter 3: Cautions and Notes Regarding Circuit Design GATE ARRAY S1L30000 SERIES EPSON DESIGN GUIDE Figure 3.11 Process Example of bi-directional pins

Fix the FF so that it is not scanned As the T -FF , MSI macro cells include the FF , and the output from the FF not to be scanned causes a malfunction in the ATPG test patterns. Also, fault detection of the circuit often can not be executed, so if possible they should be ﬁxed by the ATPGEN. (8) Others
The number of gates goes up about 15 to 20% compared to the original circuit, but it depends on the number of scanned FFs.
The working period for DFT and ATDG depends on the circuit conﬁguration and the scale of gates. At least three working days are needed for DFT and ATPG at EPSON. (In an unusual case, about ten working days may be needed depending on the circuit conﬁguration. Please refer to this book for the circuit conﬁguration before designing it.)
Please send the papers on “ATPG check sheet” and “External pin information” to EPSON before sending the logic circuit data. If there are problems with the logic cir- cuit, EPSON may ask to change the design. Please deﬁne the external pins (ATP- GEN, SCANEN and so on) added to scan FFs at the test patterns interfaced to EPSON. Please send the information required for Clock Tree Synthesis on page 20 at the same time, because when placing cells and routing interconnections, they are requested to cope with CTS (Clock Tree Synthesis). IBCD1 ATPGEN IBCD1 BC1 BC1 BC1 A E A E A E SCANOUT SCANIN SCANEN

Chapter 3: Cautions and Notes Regarding Circuit Design EPSON GATE ARRAY S1L30000 SERIES DESIGN GUIDE (9) ATPG check sheet Never delay sending this sheet a week before sending the logic circuit data. Please mark “Y es” or “No” at each item. 1. Which the netlist format (gate level) interfaced to EPSON? Verilog or EDIF 2. Is the scanned FF used at the original circuit? (Note 1) Y es or No Do you use macro cells, MSI cells and interval oscillator cells? Y es or No 4. If you answer “Y es” to the question above, write the cell name. : 5. Do you use the internal 3-state bus? Y es or No 6. Does your logic circuit have RS latch, differential circuit and asynchronous circuit? Y es or No 7. Do you use latch cells? Y es or No 8. Is there a bi-direction pin? Y es or No 9. Are there clocks that can not be directly controlled externally? Y es or No 10. Are there FF , reset and set pins of latch cells that can not be directly controlled externally? Y es or No 11. If the answers are “Y es” to question Nos.3 to 10, does the circuit design correspond to the DFT rule? (Note 2) Yes or No 12. Are I/O cells arranged on the top of the hierarchy? Yes or No 13. Do the clocknets cope with skew by CTS? Y es or No Note1: If you answered “Yes”, please design the logic circuit again, because the circuit can not scan. Note2: If you answered “No”, please insert the DFT, because the circuit can not scan. Also, if you ask to insert the DFT to EPSON, please contact EPSON sales division, because circuit information in addition to that on this sheet is required. External Terminals Enter the terminal names corresponding to the pin layout Table. The speciﬁc terminals required vary by circuit conﬁguration. (Be sure to enter all the terminal names you need.)

Clock Input Terminal

Chapter 3: Cautions and Notes Regarding Circuit Design GATE ARRAY S1L30000 SERIES EPSON DESIGN GUIDE Contents of control, operating level, etc. Contents of control, operating level, etc. Contents of control, operating level, etc. Contents of control, operating level, etc.

Input terminals that cannot be assigned to the scan data input terminal (Note 4)
Output terminals that cannot be assigned to the scan data output terminal (Note 4)
Remarks

Chapter 3: Cautions and Notes Regarding Circuit Design EPSON GATE ARRAY S1L30000 SERIES DESIGN GUIDE <Others> (Trial data: Check sheet, provisional net list, provisional pin layout Table, circuit block dia- gram)

Required error detection rate: _____ %
Along with this sheet, please submit circuit blocks and hierarchies (module and instance names) and information conﬁrming the data path between the clock line and blocks. (Note 3) If the insertion does not involve the original circuit, please specify the required contents. (Note 4) If this is left unspecified, a selection will be assigned by SEIKO EPSON.

3.11 Restrictions and Constraints on VHDL/Verilog-HDL Netlist

The VHDL/Verilog-HDL net list to be interfaced to EPSON shall be a pure gate-level net list (not containing description of operation). The restrictions and constraints in developing EPSON ASIC using VHDL/Verilog HDL are as follows.

3.11.1 Common Restrictions and Constraints

(1) Names of External Terminal (I/O Terminal)

Use only upper-case letters.
Number of characters: 2 to 32
Usable characters: Alphanumeric characters and “_.” Use an alphabetical letter at the head.
Examples of prohibited character strings : 2 INPUT : A digit is at the head. \\2INPUT : ” is at the head. InputA : Lower-case letters are included. _INPUTA : “_” is at the head. TNA[3:0] : A bus is used for the name of the external terminal. INA[3] : A bus is used for the name of the external terminal. (2) Names of Internal Terminal (including bus net names)
Upper-and lower-case letters can be used in combination, except the following. Combinations of the same words expressed in upper-and lower-case letters, such as
Number of characters: 2 to 32
Usable characters: Alphanumeric characters, “_,” “_[ ]_” (Verilog bus blanket), and “_()_” (VHDL bus blanket) with an alphabetical letter at the head.

Chapter 3: Cautions and Notes Regarding Circuit Design GATE ARRAY S1L30000 SERIES EPSON DESIGN GUIDE (3) Bus description is prohibited at the most signiﬁcant place of the module. Examples: DATA [0:3], DATA [3], and DATA [2] are prohibited. DATA0, DATA1, and DATA2 are all allowed. (4) Y ou can use I/O cells of the same library series, but cannot combine those of different series. (5) It is not possible to describe operations in behaviors or in the C language. Such descrip- tions existing in the net list are invalid. (6) Precision of the time scale of the library of each series is 1 ps.

3.11.2 Restrictions and Constraints for Verilog Netlist

(7) Descriptions using the functions “assign” and “tran” are prohibited in the gate-level Verilog net list. (8) Descriptions of connection with cell pin names are recommended in the Verilog net list. Example:Connection with pin names: IN2 inst_1 (.A(inst_2),.X(inst_3)); Recommended Connection with net names: IN2 inst_1(net1, net2): (9) Y ou cannot use the Verilog command “force” as a description of ﬂip-ﬂop operation. (Example: force logic .singal = 0;) (10) The time scale description is added at the head of the gate-level net list generated by the Synopsys design compiler. Set it at the value described in the EPSON Verilog library. See (6) for the time scale of each series. Example:'timescale 1ps/1ps (11) EPSON prohibits combination of a bus single port name and a name that includes “_\\_”, such as the following, in the same module. input A [0]; wire \\A [0]; (12) The following letter strings are reserved for Verilog, which cannot be used as a user- deﬁned name. always, and, assign, begin, buf, buﬁf0, buﬁf1, case, design,default, defparam, disable, else, end, endcase, endfunction, endmodule, endtask, event, for, force, forever, fork, func- tion, highz0, highz1, if, initial, inout, input, integer, join, large, medium, module, nand, negedge, nor, not, notif0, notif1, or, output, parameter, posedge, pull0, pull1, reg, release, repeat, scalared, small, specify, strong0, strong1, supply0, supply1, task, time, tri, tri0, tri1, trinand, trior, trireg, vectored, wait, wand, weak0, weak1, while, wire, wor, xor, xnor

3.11.3 Restrictions and Constraints on VHDL Netlist

(13) In addition to the constraints in (1), the following letter strings are also prohibited. INPUTA_ : “_” is used at the end. INPUT_ _A : “_” is used twice or more in succession. read : Used in the system. write : Used in the system.

Chapter 3: Cautions and Notes Regarding Circuit Design

30 EPSON GATE ARRAY S1L30000 SERIES

(14) The following letter strings are reserved for VHDL, which cannot be used as a user- deﬁned name. abs, access, after, alias, all, and, architecture, array, assert, attribute, begin, block, body, buffer, bus, case, component, conﬁguration, constant, disconnect, downto, else, elsif, end, entity, exit, ﬁle, for, function, generate, generic, guarded, if, in, inout, is, label, library, linkage, loop, map, mod, nand, new, next, nor, not, null, of, on, open, or, others, out, package, port, procedure, process, range, record, register, rem, report, return, select, severity, signal, subtype, then, to, transport, type, units, until, use, variable, wait, when, while, with, xor (15) To use EPSON utilities and tools, it is necessary to change the VHDL format into the Ver- ilog format. Therefore, the letter strings reserved for Verilog in (12) are also prohibited.

Chapter 4: Input/Out Cells and Their Use GATE ARRAY S1L30000 SERIES EPSON 31 DESIGN GUIDE Chapter 4 Input/Out Cells and Their Use

4.1 Types of Input/Output Cells in the S1L30000 Series

S1L30000 Series ASICs operate by using a single power supply source (either 3.0 V, 3.3 V or cell usage is dependent upon the power supply scheme. * I/O Interface Level 1) 5.0 V system single power supply or dual power supply 5.0 V system Input le vel TTL level, CMOS level, TTL Schmitt, CMOS Schmitt, PCI(Note 1) Output level TTL level, CMOS level, PCI(Note 1) 2) 3.0 V/3.3 V system single power supply or dual power supply 3.0 V/ 3.3 V system Input level CMOS level, CMOS Schmitt, PCI(Note 1) Output level CMOS level, PCI(Note 1) NOTE: Please direct inquiries regarding the PCI interface to the EPSON. The 3.0 V/ 3.3 V system CMOS level is about the same value as the 5.0 V system TTL level. When a single 3.0/3.3 V power supply is used, TTL level input cannot be used. * Output Drive Capability See the electrical characteristics (Tables 1.5 to 1.7). * Pull-up/Pull-down Resistances See the electrical characteristics (Tables 1.5 to 1.7). The input buffer, output buffer, and bi-directional buffer conﬁgurations for single power supplies are explained in detail beginning with Section 4.2. Moreover, I/O cell conﬁgurations for dual power supplies are explained in Chapter 11.

4.2 I/O Buffer Conﬁgurations with a Single Power Supply

When the I/O buffer is used with a single power supply, the power-supply voltage can be selected between 5.0 V and 3.0 V (or 3.3 V). Basically, the single-power-supply I/O cells can be operated using a 5.0-V single power supply, or a 3.0-V or 3.3-V single power supply. The following describes the structure of single-power-supply I/O cells separately for cases in which the power-supply voltage is 5.0 V and 3.0 V (or 3.3 V).

Chapter 4: Input/Out Cells and Their Use

32 EPSON GATE ARRAY S1L30000 SERIES

4.2.1 I/O Buffer Conﬁgurations with a Single 5.0 V Power Supply 4.2.1.1 Input Buffer Conﬁgurations with a Single 5.0 V Power Supply The input buffer function is structured of input cells only. NOTE: When ∗ value is 1 or 2, the pull-up/pull-down resistance values correspond to 1:50 kΩ , 2:100 kΩ respectively. 4.2.1.2 Output Buffer Conﬁgurations with a Single 5.0 V Power Supply Please conﬁgure the output buffers using pre-drivers (such as PDV1T, PDV1AT, PDV1BT, PDV2T, PDV2AT, PDV2BT, etc.), and output cells (such as U01 to U04). See Figure 4.1 for connectivity and reference Table 4.2 below regarding the pre-driver and output cell combinations. For PCI compliant signaling, please use PDV1AAT and PDV2AAT pre-drivers only. Figure 4.1 Examples of Pre-driver and Output Cell Configurations Table 4.1 Input Cell Cell Name Input Level Function Pull-up/Pull-down Resistance IBT IBTP∗ IBTD∗ TTL TTL TTL Buffer Buffer Buffer None Pull-up resistance (50 k Ω , 100 kΩ ) Pull-down resistance (50 kΩ , 100 kΩ ) IBC IBCP∗ IBCD ∗ CMOS CMOS CMOS Buffer Buffer Buffer None Pull-up resistance (50 k Ω , 100 kΩ ) Pull-down resistance (50 kΩ , 100 kΩ ) IBS IBSP∗ IBSD∗ TTL Schmitt TTL Schmitt TTL Schmitt Buffer Buffer Buffer None Pull-up resistance (50 k Ω , 100 kΩ ) Pull-down resistance (50 kΩ , 100 kΩ ) IBH IBHP∗ IBHD ∗ CMOS Schmitt CMOS Schmitt CMOS Schmitt Buffer Buffer Buffer None Pull-up resistance (50 k Ω , 100 kΩ ) Pull-down resistance (50 kΩ , 100 kΩ ) IBPA IBPAP∗ IBPAD∗ PCI PCI PCI Buffer Buffer Buffer None Pull-up resistance (50 k Ω , 100 kΩ ) Pull-down resistance (50 kΩ , 100 kΩ ) UO1 A E TD TE TS P N Output Enable for Test A TD TS P N Output for Test signal Output signal PDV2T PDV1T (b) UO1 + PDV2T = 3 - state output(a) UO1 + PDV1T = Normal output UO1 Output

Chapter 4: Input/Out Cells and Their Use GATE ARRAY S1L30000 SERIES EPSON 33 DESIGN GUIDE Table 4.2 Combinations of Pre-drivers and Output Cells Function IOL * / IOH Cell Structure* Normal output for low noise 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA UOS + PDV1T UOM + PDV1T UO1 + PDV1T UO2 + PDV1T UO3 + PDV1T UO4 + PDV1T Normal output for high speed 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA PCI UOS + PDV1AT UOM + PDV1AT UO1 + PDV1AT UO2 + PDV1AT UO3 + PDV1AAT UO4 + PDV1AAT UOPA + PDV1AAT Normal output with slew rate control 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA UOS + PDV1BT UOM + PDV1BT UO1 + PDV1BT UO2 + PDV1BT UO3 + PDV1BT UO4 + PDV1BT Normal output with slew rate control for falling edge only 12 mA / -12 mA 24 mA / -12 mA UO3L + PDV3T UO4L + PDV3T 3-state output for low noise 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA UOS + PDV2T UOM + PDV2T UO1 + PDV2T UO2 + PDV2T UO3 + PDV2T UO4 + PDV2T 3-state output for high speed 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA PCI UOS + PDV2AT UOM + PDV2AT UO1 + PDV2AT UO2 + PDV2AT UO3 + PDV2AAT UO4 + PDV2AAT UOPA + PDV2AAT 3-state output with low slew rate control 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA UOS + PDV2BT UOM + PDV2BT UO1 + PDV2BT UO2 + PDV2BT UO3 + PDV2BT UO4 + PDV2BT 3-state output with slew rate control for falling edge only 12 mA / -12 mA 24 mA / -12 mA UO3L + PDV4T UO4L + PDV4T

Chapter 4: Input/Out Cells and Their Use

34 EPSON GATE ARRAY S1L30000 SERIES

Table 4.2 Combinations of Pre-drivers and Output Cells (Countinued) NOTE: * V OL = 0.4 V (VDD = 5.0 V) VOH = VDD - 0.4 V (VDD = 5.0 V) * In addition to the configurations in Table 4.2, the output buffers may be configured with pre-drivers which do not have test terminals. Customers desiring to use such structures should direct inquiries to EPSON. The combinations of UO3L + PDV3T and UO4L + PDV3T in Table 4.2 comprise cells with a slew rate designed to be large on only the rising transition of output. PDV1BT and PDV2BT are predrivers with a slew rate designed to be large on both rising and falling transitions, which are used primarily in combination with UO3 or UO4. ODN (Open Drain Output Cell) Usage As is shown in Table 4.3, conﬁgure open drain output functionality using the ODNx output cell and pre-driver combinations with the N terminal connection only. Do not connect the P terminal of the pre-driver output. (See Figure 4.2) Figure 4.2 Example of Open Drain Configuration Function IOL * / IOH Cell Structure 3-state output for low noise (Bus hold circuit) 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA UOSH + PDV2T UOMH + PDV2T UO1H + PDV2T UO2H + PDV2T UO3H + PDV2T UO4H + PDV2T 3-state output for high speed (Bus hold circuit) 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA UOSH + PDV2AT UOMH + PDV2AT UO1H + PDV2AT UO2H + PDV2AT UO3H + PDV2AAT UO4H + PDV2AAT 3-state output with low slew rate control (Bus hold circuit) 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA UOSH + PDV2BT UOMH + PDV2BT UO1H + PDV2BT UO2H + PDV2BT UO3H + PDV2BT UO4H + PDV2BT 3-state output with slew rate control (Bus hold circuit) 12 mA / -12 mA 24 mA / -12 mA UO3HL + PDV4T UO4HL + PDV4T A TD TS P N Output for Test Output signal PDV1T (ODN1 + PDV1T = N-ch open drain) ODN1

Chapter 4: Input/Out Cells and Their Use GATE ARRAY S1L30000 SERIES EPSON 35 DESIGN GUIDE NOTE: * V OL = 0.4 V (VDD = 5 V) ** In addition to the configurations on Table 4.3, the output buffers may be configured with pre-drivers which do not have test terminals. Customers desiring to use such structures should direct inquiries to EPSON. 4.2.1.3 Bi-directional Buffer Conﬁgurations with a Single 5.0 V Power Supply Bi-directional buffers are conﬁgured from combinations of pre-drivers (with enable terminals) and bi-directional cells. (See Figure 4.3) For PCI speciﬁcation bi-directional buffer pre-drivers, use only the PDV2AAT. Figure 4.3 Examples of Pre-driver and Bi-directional Cell Configurations Table 4.3 Combinations of Pre-drivers and ODNx Cell Usage Function IOL * Cell Structure** Normal output for low noise 0.1 mA 1 mA 4 mA 8 mA 12 mA 24 mA ODNS + PDV1T ODNM + PDV1T ODN1 + PDV1T ODN2 + PDV1T ODN3 + PDV1T ODN4 + PDV1T Normal output for high speed 0.1 mA 1 mA 4 mA 8 mA 12 mA 24 mA ODNS + PDV1AT ODNM + PDV1AT ODN1 + PDV1AT ODN2 + PDV1AT ODN3 + PDV1AAT ODN4 + PDV1AAT Normal output with slew rate control 12 mA 24 mA ODN3L + PDV3T ODN4L + PDV3T UT1 A E TD TE TS P N Bidirec-Input signal Output Enable for Test signal PDV2T (a) UT1 + PDV2T = Bidirectional tional (b) UT3L + PDV4T = Bidirectional with slew rate UT3L A E TD TE TS P BidirectionalInput signal Output Enable for Test signal PDV4T

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36 EPSON GATE ARRAY S1L30000 SERIES

Table 4.4 Combinations of Pre-drivers and Bi-directional Cells Input Level Function IOL * / IOH Cell Structure* TTL Bi-directional for low noise output 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA UTS + PDV2T UTM + PDV2T UT1 + PDV2T UT2 + PDV2T UT3 + PDV2T UT4 + PDV2T TTL Bi-directional for high speed output 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA UTS + PDV2AT UTM + PDV2AT UT1 + PDV2AT UT2 + PDV2AT UT3 + PDV2AAT UT4 + PDV2AAT TTL Bi-directional with low slew rate control output 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA UTS + PDV2BT UTM + PDV2BT UT1 + PDV2BT UT2 + PDV2BT UT3 + PDV2BT UT4 + PDV2BT TTL Bi-directional with slew rate control output for falling edge only 12 mA / -12 mA 24 mA / -12 mA UT3L + PDV4T UT4L + PDV4T CMOS Bi-directional for low noise output 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA UCS + PDV2T UCM + PDV2T UC1 + PDV2T UC2 + PDV2T UC3 + PDV2T UC4 + PDV2T CMOS Bi-directional for high speed output 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA UCS + PDV2AT UCM + PDV2AT UC1 + PDV2AT UC2 + PDV2AT UC3 + PDV2AAT UC4 + PDV2AAT CMOS Bi-directional with low slew rate control output 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA UCS + PDV2BT UCM + PDV2BT UC1 + PDV2BT UC2 + PDV2BT UC3 + PDV2BT UC4 + PDV2BT CMOS Bi-directional with slew rate control output for falling edge only 12 mA / -12 mA 24 mA / -12 mA UC3L + PDV4T UC4L + PDV4T PCI Bi-directional for high speed output PCI UBPA + PDV2AAT TTL Schmitt Bi-directional for low noise output 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA USS + PDV2T USM + PDV2T US1 + PDV2T US2 + PDV2T US3 + PDV2T US4 + PDV2T

Chapter 4: Input/Out Cells and Their Use GATE ARRAY S1L30000 SERIES EPSON 37 DESIGN GUIDE TTL Schmitt Bi-directional for high speed output 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA USS + PDV2AT USM + PDV2AT US1 + PDV2AT US2 + PDV2AT US3 + PDV2AAT US4 + PDV2AAT TTL Schmitt Bi-directional with low slew rate control output 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA USS + PDV2BT USM + PDV2BT US1 + PDV2BT US2 + PDV2BT US3 + PDV2BT US4 + PDV2BT TTL Schmitt Bi-directional with slew rate control output for falling edge only 12 mA / -12 mA 24 mA / -12 mA US3L + PDV4T US4L + PDV4T CMOS Schmitt Bi-directional for low noise output 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA UHS + PDV2T UHM + PDV2T UH1 + PDV2T UH2 + PDV2T UH3 + PDV2T UH4 + PDV2T CMOS Schmitt Bi-directional for high speed output 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA UHS + PDV2AT UHM + PDV2AT UH1 + PDV2AT UH2 + PDV2AT UH3 + PDV2AAT UH4 + PDV2AAT CMOS Schmitt Bi-directional with low slew rate control output 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA UHS + PDV2BT UHM + PDV2BT UH1 + PDV2BT UH2 + PDV2BT UH3 + PDV2BT UH4 + PDV2BT CMOS Schmitt Bi-directional with slew rate control output for falling edge only 12 mA / -12 mA 24 mA / -12 mA UH3L + PDV4T UH4L + PDV4T TTL Bi-directional for low noise output (Bus hold circuit) 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA UTS + PDV2T UTM + PDV2T UT1 + PDV2T UT2 + PDV2T UT3 + PDV2T UT4 + PDV2T TTL Bi-directional for high speed output (Bus hold circuit) 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA UTSH + PDV2AT UTMH + PDV2AT UT1H + PDV2AT UT2H + PDV2AT UT3H + PDV2AAT UT4H + PDV2AAT TTL Bi-directional with low slew rate control output (Bus hold circuit) 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA UTSH + PDV2BT UTMH + PDV2BT UT1H + PDV2BT UT2H + PDV2BT UT3H + PDV2BT UT4H + PDV2BT Table 4.4 Combinations of Pre-drivers and Bi-directional Cells (Continued) Input Level Function IOL * / IOH Cell Structure*

Chapter 4: Input/Out Cells and Their Use

38 EPSON GATE ARRAY S1L30000 SERIES

Bi-directional with slew rate control output (Bus hold circuit) 12 mA / -12 mA 24 mA / -12 mA UT3HL + PDV4T UT4HL + PDV4T CMOS Bi-directional for low noise output (Bus hold circuit) 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA UCSH + PDV2T UCMH + PDV2T UC1H + PDV2T UC2H + PDV2T UC3H + PDV2T UC4H + PDV2T CMOS Bi-directional for high speed output (Bus hold circuit) 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA UCSH + PDV2AT UCMH + PDV2AT UC1H + PDV2AT UC2H + PDV2AT UC3H + PDV2AAT UC4H + PDV2AAT CMOS Bi-directional with low slew rate control output (Bus hold circuit) 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA UCSH + PDV2BT UCMH + PDV2BT UC1H + PDV2BT UC2H + PDV2BT UC3H + PDV2BT UC4H + PDV2BT CMOS Bi-directional with slew rate control output (Bus hold circuit) 12 mA / -12 mA 24 mA / -12 mA UC3HL + PDV4T UC4HL + PDV4T TTL Schmitt Bi-directional for low noise output (Bus hold circuit) 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA USSH + PDV2T USMH + PDV2T US1H + PDV2T US2H + PDV2T US3H + PDV2T US4H + PDV2T TTL Schmitt Bi-directional for high speed output (Bus hold circuit) 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA USSH + PDV2AT USMH + PDV2AT US1H + PDV2AT US2H + PDV2AT US3H + PDV2AAT US4H + PDV2AAT TTL Schmitt Bi-directional with low slew rate control output (Bus hold circuit) 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA USSH + PDV2BT USMH + PDV2BT US1H + PDV2BT US2H + PDV2BT US3H + PDV2BT US4H + PDV2BT TTL Schmitt Bi-directional with slew rate control output (Bus hold circuit) 12 mA / -12 mA 24 mA / -12 mA US3HL + PDV4T US4HL + PDV4T CMOS Schmitt Bi-directional for low noise output (Bus hold circuit) 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA UHSH + PDV2T UHMH + PDV2T UH1H + PDV2T UH2H + PDV2T UH3H + PDV2T UH4H + PDV2T Table 4.4 Combinations of Pre-drivers and Bi-directional Cells (Continued) Input Level Function IOL * / IOH Cell Structure*

Chapter 4: Input/Out Cells and Their Use GATE ARRAY S1L30000 SERIES EPSON 39 DESIGN GUIDE NOTE: * V OL = 0.4 V (VDD = 5.0 V) VOH = VDD - 0.4 V (VDD = 5.0 V) * In addition to the configurations in Table 4.4, bi-directional buffers may be configured with pre-drivers which do not have test terminals. Most bi-directional buffers have two types of pull-up resistance options and two types of pull-down resistance options. Customers desiring such should direct inquiries to EPSON. CMOS Schmitt Bi-directional for high speed output (Bus hold circuit) 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA UHSH + PDV2AT UHMH + PDV2AT UH1H + PDV2AT UH2H + PDV2AT UH3H + PDV2AAT UH4H + PDV2AAT CMOS Schmitt Bi-directional with low slew rate control output (Bus hold circuit) 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA UHSH + PDV2BT UHMH + PDV2BT UH1H + PDV2BT UH2H + PDV2BT UH3H + PDV2BT UH4H + PDV2BT CMOS Schmitt Bi-directional with slew rate control output (Bus hold circuit) 12 mA / -12 mA 24 mA / -12 mA UH3HL + PDV4T UH4HL + PDV4T Table 4.4 Combinations of Pre-drivers and Bi-directional Cells (Continued) Input Level Function IOL * / IOH Cell Structure*

Chapter 4: Input/Out Cells and Their Use

40 EPSON GATE ARRAY S1L30000 SERIES

4.2.2 I/O Buffer Conﬁgurations with a Single 3.0/3.3 V Power Supply NOTE: When ∗ value is 1 or 2, the pull-up/pull-down resistance values correspond to 1:90 kΩ , 2:180 kΩ respectively. In a 3.0 V/3.3 V single power supply TTL level input cannot be used. IDC (Input Cells) The IDC is a 5.0 V tolerant input buffer which can be used in a 3.0 V/3.3 V. The features of this cell include the fact that its protective diode on the VDD side has been removed, and that it functions as a simple level shifter. NOTE: When ∗ value is 1 or 2, the pull-up/pull-down resistance values correspond to 1:90 kΩ , 2:180 kΩ respectively. Table 4.5 Input Cells Cell Name Input Level Function Pull-up/Pull-down Resistance IBC IBCP∗ IBCD ∗ CMOS CMOS CMOS Buffer Buffer Buffer None Pull-up Resistance (90 kΩ , 180 kΩ ) Pull-down Resistance (90 kΩ , 180 kΩ ) IBH IBHP IBHD ∗ CMOS Schmitt CMOS Schmitt CMOS Schmitt Buffer Buffer Buffer None Pull-up Resistance (90 kΩ , 180 kΩ ) Pull-down Resistance (90 kΩ , 180 kΩ ) IBPB IBPBP IBPBP ∗ PCI PCI PCI Buffer Buffer Buffer None Pull-up Resistance (90 kΩ , 180 kΩ ) Pull-down Resistance (90 kΩ , 180 kΩ ) Table 4.6 Table of Input Level Shifters Cell Name Input Level Function Pull-up/Pull-down Resistance IDC IDCD ∗ CMOS CMOS Buffer Buffer None Pull-down Resistance (90 kΩ , 180 kΩ ) IDH IDHD ∗ CMOS Schmitt CMOS Schmitt Buffer Buffer None Pull-down Resistance (90 kΩ , 180 kΩ )

Chapter 4: Input/Out Cells and Their Use GATE ARRAY S1L30000 SERIES EPSON 41 DESIGN GUIDE When structuring the output buffer, use a combination of pre-drivers (such as PDV1T, PDV1AT, PDV2T, PDV2AT, etc.), which are structured of internal cells and output cells (such as UO1 to UO4). See Table 4.6, below, regarding these combinations. For PCI speciﬁcation output for pre-drivers, use PDV1AAT and PDV2AAT only. Table 4.7 Combinations of Pre-drivers and Output Cells Function IOL * / IOH Cell Structure* Normal output for low noise 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA UOS + PDV1T UOM + PDV1T UO1 + PDV1T UO2 + PDV1T UO3 + PDV1T UO4 + PDV1T Normal output for high speed 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA PCI UOS + PDV1AT UOM + PDV1AT UO1 + PDV1AT UO2 + PDV1AT UO3 + PDV1AAT UO4 + PDV1AAT UOPB + PDV1AAT Normal output with low slew rate control 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA UOS + PDV1BT UOM + PDV1BT UO1 + PDV1BT UO2 + PDV1BT UO3 + PDV1BT UO4 + PDV1BT Normal output with slew rate control for fallling edge only 6 mA / -6 mA 12 mA / -6 mA UO3L + PDV3T UO4L + PDV3T 3-state output for low noise 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA UOS + PDV2T UOM + PDV2T UO1 + PDV2T UO2 + PDV2T UO3 + PDV2T UO4 + PDV2T 3-state output for high speed 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA PCI UOS + PDV2AT UOM + PDV2AT UO1 + PDV2AT UO2 + PDV2AT UO3 + PDV2AAT UO4 + PDV2AAT UOPB + PDV2AAT 3-state output with low slew rate control 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA UOS + PDV2BT UOM + PDV2BT UO1 + PDV2BT UO2 + PDV2BT UO3 + PDV2BT UO4 + PDV2BT 3-state output with slew rate control for falling edge only 6 mA / -6 mA 12 mA / -6 mA UO3L + PDV4T UO4L + PDV4T

Chapter 4: Input/Out Cells and Their Use

42 EPSON GATE ARRAY S1L30000 SERIES

Table 4.7 Combinations of Pre-drivers and Output Cells (continued) NOTE: * V OL = 0.3 V (VDD = 3.3 V, 3.0 V) VOH = VDD - 0.3 V (VDD = 3.3 V, 3.0 V) * In addition to the configurations in Table 4.7, the output buffers may be configured with pre-drivers which do not have test terminals. Customers desiring to use such structures should direct inquiries to EPSON. ODN (Open Drain Output Cell) Usage As is shown in Table 4.8, conﬁgure open drain output functionality using the ODN output cell and pre-driver combinations with the N terminal connection only. Do not connect the P terminal of the pre-driver output. NOTE: * V OL = 0.3 V (VDD = 3.3 V, 3.0 V) ** In addition to the structuring methods of Table 4.8, the output buffers may be configured with pre-drivers which do not have test terminals. Customers desiring to use such structures should direct inquiries to EPSON. Function IOL * / IOH Cell Structure* 3-state output for low noise (Bus hold circuit) 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA UOSH + PDV2T UOMH + PDV2T UO1H + PDV2T UO2H + PDV2T UO3H + PDV2T UO4H + PDV2T 3-state output for high speed (Bus hold circuit) 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA UOSH + PDV2AT UOMH + PDV2AT UO1H + PDV2AT UO2H + PDV2AT UO3H + PDV2AAT UO4H + PDV2AAT 3-state output with low slew rate control (Bus hold circuit) 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA UOSH + PDV2BT UOMH + PDV2BT UO1H + PDV2BT UO2H + PDV2BT UO3H + PDV2BT UO4H + PDV2BT 3-state output with slew rate control (Bus hold circuit) 6 mA / -6 mA 12 mA / -6 mA UO3HL + PDV4T UO4HL + PDV4T Table 4.8 Combinations of Pre-drivers and the ODN System Cells Function IOL * Cell Structure*** Normal output for low noise 0.05 mA 0.5 mA 2 mA 4 mA 6 mA 12 mA ODNS + PDV1T ODNM + PDV1T ODN1 + PDV1T ODN2 + PDV1T ODN3 + PDV1T ODN4 + PDV1T Normal output for high speed 0.05 mA 0.5 mA 2 mA 4 mA 6 mA 12 mA ODNS + PDV1AT ODNM + PDV1AT ODN1 + PDV1AT ODN2 + PDV1AT ODN3 + PDV1AAT ODN4 + PDV1AAT Normal output with slew rate control 6 mA 12 mA ODN3L + PDV3T ODN4L + PDV3T

Chapter 4: Input/Out Cells and Their Use GATE ARRAY S1L30000 SERIES EPSON 43 DESIGN GUIDE Bi-directional buffers are conﬁgured from combinations of pre-drivers (with enable terminals) and bi-directional cells. (See Figure 4.3). For PCI speciﬁcation bi-directional buffer pre-drivers, use only PDV2AAT. Table 4.9 Combinations of Pre-drivers and Bi-directional Cells Input Level Function IOL * / IOH ** Cell Structure CMOS Bi-directional for low noise output 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA UCS + PDV2T UCM + PDV2T UC1 + PDV2T UC2 + PDV2T UC3 + PDV2T UC4 + PDV2T CMOS Bi-directional for high speed output 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA UCH + PDV2AT UCM + PDV2AT UC1 + PDV2AT UC2 + PDV2AT UC3 + PDV2AAT UC4 + PDV2AAT CMOS Bi-directional with low slew rate control output 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA UCS + PDV2BT UCM + PDV2BT UC1 + PDV2BT UC2 + PDV2BT UC3 + PDV2BT UC4 + PDV2BT CMOS Bi-directional with slew rate control output for falling edge only 6 mA / -6 mA 12 mA / -6 mA UC3L + PDV4T UC4L + PDV4T PCI Bi-directional for high speed output PCI UBPB + PDV2AAT CMOS Schmitt Bi-directional for low noise output 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA UHS + PDV2T UHM + PDV2T UH1 + PDV2T UH2 + PDV2T UH3 + PDV2T UH4 + PDV2T CMOS Schmitt Bi-directional for high speed output 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA UHS + PDV2AT UHM + PDV2AT UH1 + PDV2AT UH2 + PDV2AT UH3 + PDV2AAT UH4 + PDV2AAT CMOS Schmitt Bi-directional with low slew rate control output 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA UHS + PDV2BT UHM + PDV2BT UH1 + PDV2BT UH2 + PDV2BT UH3 + PDV2BT UH4 + PDV2BT CMOS Schmitt Bi-directional with slew rate control output for falling edge only 6 mA / -6 mA 12 mA / -6 mA UH3L + PDV4T UH4L + PDV4T

Chapter 4: Input/Out Cells and Their Use

44 EPSON GATE ARRAY S1L30000 SERIES

Table 4.9 Combinations of Pre-drivers and Bi-directional Cells (continued) NOTE: * V OL = 0.3 V (VDD = 3.3 V, 3.0 V) VOH = VDD - 0.3 V (VDD = 3.3 V, 3.0 V) * In addition to the configurations on Table 4.9, bi-directional buffers may be configured with pre-drivers which do not have test terminals. Most bi-directional buffers have two types of pull-up resistance options and two types of pull-down resistance options. Customers desiring to use a pre-driver without test terminals should direct inquiries to EPSON. **** TTL input levels are not available when using a 3.0 V/3.3 V single power supply. Input Level Function IOL * / IOH ** Cell Structure CMOS Bi-directional for low noise output (Bus hold circuit) 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA UCSH + PDV2T UCMH + PDV2T UC1H + PDV2T UC2H + PDV2T UC3H + PDV2T UC4H + PDV2T CMOS Bi-directional for high speed output (Bus hold circuit) 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA UCSH + PDV2AT UCMH + PDV2AT UC1H + PDV2AT UC2H + PDV2AT UC3H + PDV2AAT UC4H + PDV2AAT CMOS Bi-directional with low slew rate control output (Bus hold circuit) 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA UCSH + PDV2BT UCMH + PDV2BT UC1H + PDV2BT UC2H + PDV2BT UC3H + PDV2BT UC4H + PDV2BT CMOS Bi-directional with slew rate control output (Bus hold circuit) 6 mA / -6 mA 12 mA / -6 mA UC3HL + PDV4T UC4HL + PDV4T CMOS Schmitt Bi-directional for low noise output (Bus hold circuit) 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA UHSH + PDV2T UHMH + PDV2T UH1H + PDV2T UH2H + PDV2T UH3H + PDV2T UH4H + PDV2T CMOS Schmitt Bi-directional for high speed output (Bus hold circuit) 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA UHSH + PDV2AT UHMH + PDV2AT UH1H + PDV2AT UH2H + PDV2AT UH3H + PDV2AAT UH4H + PDV2AAT CMOS Schmitt Bi-directional with low slew rate control output (Bus hold circuit) 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA UHSH + PDV2BT UHMH + PDV2BT UH1H + PDV2BT UH2H + PDV2BT UH3H + PDV2BT UH4H + PDV2BT CMOS Schmitt Bi-directional with slew rate control output(Bus hold circuit) 6 mA / -6 mA 12 mA / -6 mA UH3HL + PDV4T UH4HL + PDV4T

Chapter 4: Input/Out Cells and Their Use GATE ARRAY S1L30000 SERIES EPSON 45 DESIGN GUIDE * BDC, BDH System Cells (Bi-directional Cells) BDC and BDH system cells are bi-directional cells which are constructed by combining IDC (5- volt tolerant input cells) and ODN (open drain output cells). Table 4.10 gives combinations of pre-drivers and BDC, BDH system cells. NOTE: * V OL = 0.3 V (VDD = 3.3 V, 3.0 V) ** In addition to the configurations in Table 4.10, bi-directional buffers may be configured with pre-drivers which do not have test terminals. Most bi-directional buffers have two types of pull-up resistance options and two types of pull-down resistance options. Customers desiring to use structures without test terminals should direct inquiries to EPSON. Table 4.10 Combinations of Pre-drivers and BDC/BDH System Cells Input Level Function IOL * Cell Structure CMOS Bi-directional for low noise output 0.05 mA 0.5 mA 2 mA 4 mA 6 mA 12 mA BDCS + PDV2T BDCM + PDV2T BDC1 + PDV2T BDC2 + PDV2T BDC3 + PDV2T BDC4 + PDV2T CMOS Bi-directional for high speed output 0.05 mA 0.5 mA 2 mA 4 mA 6 mA 12 mA BDCS + PDV2AT BDCM + PDV2AT BDC1 + PDV2AT BDC2 + PDV2AT BDC3 + PDV2AAT BDC4 + PDV2AAT CMOS Bi-directional with low slew rate control output 0.05 mA 0.5 mA 2 mA 4 mA 6 mA 12 mA BDCS + PDV2BT BDCM + PDV2BT BDC1 + PDV2BT BDC2 + PDV2BT BDC3 + PDV2BT BDC4 + PDV2BT CMOS Bi-directional with slew rate control output 6 mA 12 mA BDC3L + PDV4T BDC4L + PDV4T CMOS Schmitt Bi-directional for low noise output 0.05 mA 0.5 mA 2 mA 4 mA 6 mA 12 mA BDHS + PDV2T BDHM + PDV2T BDH1 + PDV2T BDH2 + PDV2T BDH3 + PDV2T BDH4 + PDV2T CMOS Schmitt Bi-directional for high speed output 0.05 mA 0.5 mA 2 mA 4 mA 6 mA 12 mA BDHS + PDV2AT BDHM + PDV2AT BDH1 + PDV2AT BDH2 + PDV2AT BDH3 + PDV2AAT BDH4 + PDV2AAT CMOS Schmitt Bi-directional with low slew rate control output 0.05 mA 0.5 mA 2 mA 4 mA 6 mA 12 mA BDHS + PDV2BT BDHM + PDV2BT BDH1 + PDV2BT BDH2 + PDV2BT BDH3 + PDV2BT BDH4 + PDV2BT CMOS Schmitt Bi-directional with slew rate control output 6 mA 12 mA BDH3L + PDV4T BDH4L + PDV4T

Chapter 4: Input/Out Cells and Their Use

46 EPSON GATE ARRAY S1L30000 SERIES

4.3 Oscillation Circuit

4.3.1 Oscillation Circuit Conﬁgurations

Oscillation circuits should be conﬁgured, as shown in Figure 4.4. Both standard and gated oscillator circuit conﬁgurations are supported as shown. Figure 4.4 Method of Structuring the Oscillator Circuit

4.3.2 Oscillator Circuit Considerations

(1) Pin Layout The inputs and outputs of the oscillator circuits should be positioned on adjacent pins, and should be located between power supply pins (VDD , VSS ). Do not locate high drive output pins near the input/output pins of the oscillator circuit. Be especially careful to locate any outputs having the same phase or the opposite phase of the oscillating wave form as far as possible from the oscillator circuit input/output pins. Whenever possible, locate the input/output pins of the oscillator circuit near the center of the edge of the package. (2) Oscillator Cell Selection Criteria The frequency at which oscillation is possible hanges approximately a few kHz to a tens of MHz. For details, please direct inquiries to EPSON. (3) Setting the external resistor and capacitor values The oscillation characteristics depend on the elements that comprise the circuit (IC, X’tal, R f, Rd, Cg, Cd, and the board). Because it is necessary to adjust the values of external Rf and Rd, as well as those of Cg and Cd, on the actual board to suit the X’tal used, be sure to select the optimum values for these resistors and capacitors based on careful evaluation of their performance through the use of ES samples and the like. Oscillation cell LIN LOT or LOT2 Inside of IC (a) Oscillation circuit without Enable Oscillation cell LIN LOT or LOT2 Inside of IC (b) Oscillation circuit with Enable E G X D G X D X’tal Cg Rf Cd Cg Rf Cd X’tal

Chapter 4: Input/Out Cells and Their Use GATE ARRAY S1L30000 SERIES EPSON 47 DESIGN GUIDE (4) Assurance Levels The oscillation characteristics depend on the elements that comprise the circuit (IC, X’tal, R f, Rd, Cg, Cd, and the board). Therefore, Epson cannot guarantee the oscillating opera- tion or characteristics on an actual board. Only the oscillation cells are guaranteed by Epson.Because of this, it is necessary for the customer to spend adequate time evaluat- ing the ES samples in terms of their oscillation characteristics. (5) Discerning between LOT and LOT2 LOT2 is a low-impedance type LOT, used for situations where the oscillation frequency is high. The selection of LOT vs. LOT2 is done in combination with the oscillator cell. Direct inquiries for details to EPSON. (6) Structuring Oscillator Circuits for Dual Power Supplies The structure of oscillator circuits for dual power supplies is essentially no different than the structure for single power supplies. The oscillator circuit operates on the LV DD system. Moreover, for input/output cells LIN, LOT, and LOT2, use LLIN, LLOT and LLOT2, which each have the preﬁx “L ” to denote operation using LV DD .

Chapter 5: RAM

48 EPSON GATE ARRAY S1L30000 SERIES

The S1L30000 Series supports 1 port RAM and 2 port RAM.

5.1 Features

(1) 1-Port RAM

Asynchronous
Static operation
1 read/write address port, 1 input data port, 1 output data port
RAM conﬁgurations supported: Word Depth = 8 to 128 (incremental by 4 words) Bit Width = 1 to 32 (incremental by 1 bit)
Maximum size: 4 K bits/module (128 words x 32 bits)
3.0 V operation available (2) 2-Port RAM
Asynchronous
Static operation
1 read address port, 1 write address port, 1 input data port, 1 output data port
RAM conﬁgurations supported: Word Depth = 8 to 128 (incremental by 4 words) Bit Width = 1 to 32 (incremental by 1 bit)
Maximum size: 4 K bits/module (128 words x 32 bits)
3.0 V operation available

5.2 RAM Conﬁguration and Simulation Model Selection

RAM delay parameters change depending on the word/bit structure. Six simulation models (three 1-port RAM models and three 2-port RAM models) have been prepared using performance characteristics indicative to the RAM word/bit conﬁguration. The 1-port RAM and 2-port RAM word/bit structure simulation models are shown in Table 5.1 and 5.2 respectively. For RAM with word/bit structures exceeding the limitations in the tables below, use combinations of multiple RAMs. NOTE: Although each simulation model supports a variety of RAM configurations, the customer specified RAM configuration will be used during layout. Table 5.1 Simulation Model Selection Chart (1-Port RAM Word/Bit Structure) Number of words/bits 1 to 4 5 to 8 9 to 16 17 to 32 8 to 32 RAM4 RAM4 RAM5 RAM6 36 to 64 RAM5 RAM5 RAM5 RAM6 68 to 128 RAM6 RAM6 RAM6 RAM6

Chapter 5: RAM GATE ARRAY S1L30000 SERIES EPSON 49 DESIGN GUIDE

5.3 RAM Size

The X-direction size, Y -direction size, and number of BCs used in the RAM are calculated using the formulas below. The formulas below include the interconnect region contained in the RAM. Use these formulas when investigating master selection when RAM is included (see Section 2.5). (1) 1-Port RAM a) For RAM4, RAM5, or RAM6 Size in the X direction: RX = Word + Bit/2 + 13 (Round up to the nearest whole number) Size in the Y direction: RY = 2 x Bit + 9 Number of BCs: RAMBCS = RX x RY NOTE: The numbers within this chart indicate RAMBCS (RX x RY) which includes interconnect area. (2) 2-Port RAM Size in the X direction: RX = Word + Bit/2 + 13 (Round up to the nearest whole number) Size in the Y direction: RY = 2 x Bit + 12 Number of BCs: RAMBCS= RX x RY NOTE: The numbers within this chart indicate BCRAM (RX x RY), which includes interconnect area. Table 5.2 Simulation Model Selection Chart (2-Port RAM Word/Bit Structure) Number of words/bits 1 to 8 9 to 16 17 to 32 8 to 32 RAM2P1 RAM2P2 RAM2P3 36 to 64 RAM2P2 RAM2P2 RAM2P3 68 to 128 RAM2P3 RAM2P3 RAM2P3 Table 5.3 An Example of the Structure of 1-Port RAM Word/Bit 4 8 16 32 32 799 (47*17) 1225 (49*25) 2173 (53*41) 4453 (61*73) 64 1343 (79*17) 2025 (81*25) 3485 (85*41) 6789 (93*73) 128 2431 (143*17) 3625 (145*25) 6109 (149*41) 11461 (157*73) Table 5.4 An Example of the Structure of 2-Port RAM Word/Bit 4 8 16 32 32 940 (47*20) 1372 (49*28) 2332 (53*44) 4636 (61*76) 64 1580 (79*20) 2268 (81*28) 3740 (85*44) 7068 (93*76) 128 2860 (143*20) 4060 (145*28) 6556 (149*44) 11932 (157*76)

Chapter 5: RAM

50 EPSON GATE ARRAY S1L30000 SERIES

5.4 Investigating RAM Placement on Master Slice

When investigating RAM placement on a master slice, please insure that sufﬁcient area is available in both the X direction (column) and the Y direction (row). When loading RAM onto a chip, it is necessary to insure that the capacity of the master exceeds the required RAM area in both the X and Y directions. When multiple RAMs are used, RAM blocks are placed adjacent to each other either horizontally or vertically; the decision regarding master slice selection is based simply on RX and RY . Please see Table 1.1 of Chapter 1 regarding the number of columns (X-direction) and number of rows (Y -direction). For example, if ﬁve 128 word x 4 bit 1-port RAMs are required. As shown in Figure 5.1, the total RAM layout area would be: X direction: 143 BCs Y direction: 85 BCs Because of this, S1L30182 is (X, Y) = (244, 76) is impossible due to area constraints, however, S1L30302 is (X, Y) = (318, 97) is possible. See Section 2.5 pertaining to estimating the number of gates, BC AWR , which can be used for random logic. Figure 5.1 Example of RAM Layout 128w x 4b RAM17 143 143 RAM(1) RAM(2) RAM(3) RAM(4) RAM(5) x 5

Chapter 5: RAM GATE ARRAY S1L30000 SERIES EPSON 51 DESIGN GUIDE

5.5 Explanation of Functions

(1) 1-Port RAM X: High or Low

Data Read The data is read by holding CS at High and RW at High and setting the address.
Data Write The data can be written in either of the following two ways: (1) Holding CS at High, setting the address, and sending a negative pulse to RW. (2) Holding RW at Low, setting the address, and sending a positive pulse to CS. When either method is used, the data is latched to the RAM at the trailing edge of the pulse.
The Wait State When CS is Low, the 1 port RAM enters a wait state and only maintains the data. The current consumed by the RAM is merely the leakage current, and is almost zero. (2) 2-Port RAM Table 5.5 1-Port RAM Signals Signal Name I/O Function Notes CS IN Chip select signal, H: RAM active FI = 1LU RW IN Read/write signal, H: Read, L: Write FI = 1LU A0, A1 ... A(m-1) IN Read/write address port, A0: LSB FI = 1LU D0, D1 ... D(n-1) IN Data input port, D0: LSB FI = 2LU Y0, Y1 ... Y(n-1) OUT Data output port, Y0: LSB FO = 20LU corresponds to K:IN2 Table 5.6 1-Port RAM Truth Table

0 X X Unknown Wait

Table 5.7 2-Port RAM Signals Signal Name I/O Function Notes CS IN Chip select signal, H: RAM active FI = 1LU RD IN Read signal, H: Read enable FI = 1LU WR IN Write signal, H: Write enable FI = 1LU RA0, . . . RA(m-1) IN Read address port, RA0: LSB FI = 1LU WA0, . . . WA(m-1) IN Write address port, WA0: LSB FI = 1LU D0, D1, . . . D(n-1) IN Data input port, D0: LSB FI = 2LU Y0, Y1, . . . Y(n-1) OUT Data output port, Y0: LSB F0 = 20LU, corresponding to K:IN2

Chapter 5: RAM

52 EPSON GATE ARRAY S1L30000 SERIES

X: High or Low

Data Read The data is read by holding CS at High and RD at High and setting the read address.
Data Write The data can be written in either of the following two ways: (1) Holding CS at High, setting the write address, and sending a positive pulse to WR. (2) Holding WR at High, setting the write address, and sending a positive pulse to CS.
Data Read/Write When reading is done at the same time as writing, it is possible by performing the respec- tive methods simultaneously. However, these two operations cannot be performed simul- taneously on the same address. The read cycle access time applies to data for which the writing has already been completed.
The Wait State The 2 port RAM enters a wait state in either of the situations below, and does nothing but maintain its data. The current consumed by the RAM is merely the leakage current, and is almost 0. (1) CS is Low. (2) CS is High, RD is Low, and WR is Low.

5.6 Delay Parameters

(1) 3.0 V Speciﬁcations (VDD = 2.7 to 3.3 V ; Ta = -40 to 85oC) Table 5.8 2-Port RAM Truth Table CS RD WR RA0, ... RA(n-1) WA0, ...WA(m-1) Y0, ... Y(n-1) Mode 0XXXX Unknown Wait 1 0 0 X X Unknown Wait 1 0 1 X Stable Unknown Write 1 1 0 Stable X Read Data Read 1 1 1 Stable Stable Read Data Read & Write Table 5.9 1-Port RAM Read Cycle Parameter Signal RAM 4 RAM 5 RAM 6 Read cycle tRC 11.92 - 15.37 - 24.15 - ns Address access time tACC - 11.92 - 15.37 - 24.15 CS access time tACS - 11.47 - 14.77 - 23.25 R/W access time tARW - 10.20 - 13.80 - 21.45 CS active time tRCS 11.92 - 15.37 - 24.15 - Output hold time after address change tOH 0.32 - 0.39 - 0.52 - Output hold time after CS disable tOHC S 0.32 - 0.39 - 0.52 - Output hold time after R/W disable tOHRW 0.33 - 0.45 - 0.52 -

Chapter 5: RAM GATE ARRAY S1L30000 SERIES EPSON 53 DESIGN GUIDE Table 5.10 1-Port RAM Write Cycle Parameter Signal RAM 4 RAM 5 RAM 6 Write cycle tWC 13.27 - 15.45 - 21.45 - ns Write pulse width tWP 9.07 - 10.72 - 15.60 - CS active time tWCS 9.07 - 10.72 - 15.60 - Address setup time tAS 1.87 - 2.17 - 2.70 - Address hold time tAH 2.32 - 2.62 - 3.15 - Data setup time tDS 2.92 - 3.30 - 4.20 - Data hold time tDH 4.05 - 6.60 - 9.30 - Table 5.11 2-Port RAM Read Cycle Parameter Signal RAM2P1 RAM2P2 RAM2P3 Read cycle tRC 11.92 15.37 24.15 - ns Address access time tACC - 11.92 - 15.37 - 24.15 CS access time tACS - 11.47 - 14.77 - 23.25 RD access time tARW - 10.20 - 13.80 - 21.45 CS active time tRCS 11.92 - 15.37 - 24.15 - Output hold time after address change tOH 0.32 - 0.39 - 0.52 - Output hold time after CS disable tOHCS 0.32 - 0.39 - 0.52 - Output hold time after RD disable tOHRW 0.33 - 0.45 - 0.52 - Table 5.12 2-Port RAM Write Cycle Parameter Signal RAM2P1 RAM2P2 RAM2P3 Write cycle tWC 13.27 - 15.45 - 21.45 - ns Write pulse width tWP 9.07 - 10.72 - 15.60 - CS active time tWCS 9.07 - 10.72 - 15.60 - Address setup time tAS 1.87 - 2.17 - 2.70 - Address hold time tAH 2.32 - 2.62 - 3.15 - Data setup time tDS 2.92 - 3.30 - 4.20 - Data hold time tDH 4.05 - 6.60 - 9.30 -

Chapter 5: RAM

54 EPSON GATE ARRAY S1L30000 SERIES

(2) 3.3 V Speciﬁcations (VDD = 3.0 to 3.6 V ; Ta = -40 to 85°C) Table 5.13 1-Port RAM Write Cycle Parameter Signal RAM4 RAM5 RAM6 Read cycle t RC 10.42 - 13.50 - 21.22 - ns Address access time t ACC - 10.42 - 13.50 - 21.22 CS access time t ACS - 10.05 - 12.97 - 20.40 R/W access time t ARW - 8.92 - 12.15 - 18.82 CS active time t RCS 10.42 - 13.50 - 21.22 - Output hold time after address change tOH 0.29 - 0.36 - 0.50 - Output hold time after CS disable tOHCS 0.29 - 0.36 - 0.50 - Output hold time after R/W disable tOHRW 0.30 - 0.42 - 0.53 - Table 5.14 1-Port RAM Write Cycle Parameter Signal RAM4 RAM5 RAM6 Write cycle t WC 11.62 - 13.57 - 18.82 - ns Write pulse width t WP 7.95 - 9.37 - 13.65 - CS active time t WCS 7.95 - 9.37 - 13.65 - Address setup time t AS 1.65 - 1.95 - 2.40 - Address hold time t AH 2.02 - 2.25 - 2.77 - Data setup time t DS 2.55 - 2.92 - 3.67 - Data hold time t DH 3.52 - 5.77 - 8.17 - Table 5.15 2-Port RAM Read Cycle Parameter Signal RAM2P1 RAM2P2 RAM2P3 Read cycle tRC 10.42 - 13.50 - 21.22 - ns Address access time tACC - 10.42 - 13.50 - 21.22 CS access time tACS - 10.05 - 12.97 - 20.40 RD access time tARW - 8.92 - 12.15 - 18.82 CS active time tRCS 10.42 - 13.50 - 21.22 - Output hold time after address change tOH 0.29 - 0.36 - 0.50 - Output hold time after CS disable tOHCS 0.29 - 0.36 - 0.50 - Output hold time after RD disable tOHRW 0.30 - 0.42 - 0.53 -

Chapter 5: RAM GATE ARRAY S1L30000 SERIES EPSON 55 DESIGN GUIDE (3) 5.0 V ± 5% Speciﬁcations (VDD = 4.75 to 5.25 V; Ta = 0 to 70°C) Table 5.16 2-Port RAM Write Cycle Parameter Signal RAM4 RAM5 RAM 6 Write cycle tWC 11.62 - 13.57 - 18.82 - ns Write pulse width tWP 7.95 - 9.37 - 13.65 - CS active time tWCS 7.95 - 9.37 - 13.65 - Address setup time tAS 1.65 - 1.95 - 2.40 - Address hold time tAH 2.02 - 2.25 - 2.77 - Data setup time tDS 2.55 - 2.92 - 3.67 - Data hold time tDH 3.52 - 5.77 - 8.17 - Table 5.17 1-Port RAM Read Cycle Parameter Signal RAM4 RAM5 RAM6 Read cycle tRC 5.92 - 7.57 - 11.70 - ns Address access time tACC - 5.92 - 7.57 - 11.70 CS access time tACS - 5.70 - 7.27 - 11.17 R/W access time tARW - 5.32 - 6.75 - 10.12 CS active time tRCS 5.92 - 7.57 - 11.70 - Output hold time after address change tOH 0.26 - 0.32 - 0.44 - Output hold time after CS disable tOHCS 0.27 - 0.33 - 0.45 - Output hold time after R/W disable tOHRW 0.27 - 0.33 - 0.45 - Table 5.18 1-Port RAM Write Cycle Parameter Signal RAM4 RAM5 RAM 6 Write cycle tWC 8.02 - 9.22 - 11.92 - ns Write pulse width tWP 5.55 - 6.52 - 8.40 - CS active time tWCS 5.55 - 6.52 - 8.40 - Address setup time tAS 1.12 - 1.20 - 1.50 - Address hold time tAH 1.35 - 1.50 - 2.02 - Data setup time tDS 1.65 - 1.87 - 2.32 - Data hold time tDH 2.85 - 3.60 - 5.10 -

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56 EPSON GATE ARRAY S1L30000 SERIES

Table 5.19 2-Port RAM Read Cycle Parameter Signal RAM2P1 RAM2P2 RAM2P3 Read cycle tRC 5.92 - 7.57 - 11.70 - ns Address access time tACC - 5.92 - 7.57 - 11.70 CS access time tACS - 5.70 - 7.27 - 11.17 RD access time tARW - 5.32 - 6.75 - 10.12 CS active time tRCS 5.92 - 7.57 - 11.70 - Output hold time after address change tOH 0.26 - 0.32 - 0.44 - Output hold time after CS disable tOHCS 0.27 - 0.33 - 0.45 - Output hold time after RD disable tOHRW 0.27 - 0.33 - 0.45 - Table 5.20 2-Port RAM Write Cycle Parameter Signal RAM2P1 RAM2P2 RAM2P3 Write cycle tWC 8.02 - 9.22 - 11.92 - ns Write pulse width tWP 5.55 - 6.52 - 8.40 - CS active time tWCS 5.55 - 6.52 - 8.40 - Address setup time tAS 1.12 - 1.20 - 1.50 - Address hold time tAH 1.35 - 1.50 - 2.02 - Data setup time tDS 1.65 - 1.87 - 2.32 - Data hold time tDH 2.85 - 3.60 - 5.10 -

Chapter 5: RAM GATE ARRAY S1L30000 SERIES EPSON 57 DESIGN GUIDE (4) 5.0 V ± 10% Speciﬁcations (VDD = 4.5 to 5.5 V ; Ta = -40 to 85°C) Table 5.21 1-Port RAM Read Cycle Parameter Signal RAM 4 RAM 5 RAM 6 Read cycle tRC 6.30 - 8.10 - 12.52 - ns Address access time tACC - 6.30 - 8.10 - 12.52 CS access time tACS - 6.08 - 7.80 - 12.00 R/W access time tARW - 5.70 - 7.20 - 10.87 CS active time tRCS 6.30 - 8.10 - 12.52 - Output hold time after address change tOH 0.23 - 0.28 - 0.39 - Output hold time after CS disable tOHCS 0.24 - 0.28 - 0.39 - Output hold time after R/W disable tOHRW 0.24 - 0.29 - 0.39 - Table 5.22 1-Port RAM Write Cycle Parameter Signal RAM 4 RAM 5 RAM 6 Write cycle tWC 8.62 - 9.90 - 12.80 - ns Write pulse width tWP 6.00 - 6.97 - 9.00 - CS active time tWCS 6.00 - 6.97 - 9.00 - Address setup time tAS 1.20 - 1.35 - 1.65 - Address hold time tAH 1.42 - 1.57 - 2.17 - Data setup time tDS 1.80 - 2.02 - 2.55 - Data hold time tDH 3.07 - 3.90 - 5.47 - Table 5.23 2-Port RAM Read Cycle Parameter Signal RAM2P1 RAM2P2 RAM2P3 Read cycle tRC 6.30 - 8.10 - 12.52 - ns Address access time tACC - 6.30 - 8.10 - 11.70 CS access time tACS - 6.08 - 7.80 - 12.00 RD access time tARW - 5.70 - 7.20 - 10.87 CS active time tRCS 6.30 - 8.10 - 12.52 - Output hold time after address change tOH 0.23 - 0.28 - 0.39 - Output hold time after CS disable tOHCS 0.24 - 0.28 - 0.39 - Output hold time after RD disable tOHRW 0.24 - 0.29 - 0.39 -

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58 EPSON GATE ARRAY S1L30000 SERIES

5.7 Timing Charts

(1) 1-Port RAM Figure 5.2 Read Cycle Figure 5.3 Write Cycle (R/W Control) Table 5.24 2-Port RAM Write Cycle Parameter Signal RAM2P1 RAM2P2 RAM2P3 Write cycle tWC 8.62 - 9.90 - 12.80 - ns Write pulse width tWP 6.00 - 6.97 - 9.00 - CS active time tWCS 6.00 - 6.97 - 9.00 - Address setup time tAS 1.20 - 1.35 - 1.65 - Address hold time tAH 1.42 - 1.57 - 2.17 - Data setup time tDS 1.80 - 2.02 - 2.55 - Data hold time tDH 3.07 - 3.90 - 5.47 - tOH XX XX tOHCS tACS tACC tACC tOHRW tARW A1 A2 A3ADDRESS CS RW Data out tRCS tRC A1 A1 A2 A3 A3 tWC tAS tWP tDH tAH ADDRESS CS RW Data in valid tDS

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60 EPSON GATE ARRAY S1L30000 SERIES

Figure 5.7 Write Cycle (CS Control)

5.8 RAM Test Method

When it comes to internal RAM, specialized tests are performed corresponding to the RAM, separate from the ramdom logic. Please structure test circuits which facilitate direct access to the internal RAM from external pins for this purpose. See Section 6.3 of Chapter 6 regarding the method of structuring the RAM test circuits. Also, although EPSON will generate an independent test pattern for the RAM, the customer should provide test patterns for the remaining random logic, in addition to a RAM test pattern template, as shown in Section 6.3.1.

5.9 Estimating RAM Current Consumption

The method for estimating the current consumption at VDD (Typ.) = 5.0 V is given below. Moreover, for VDD (Typ.) = 3.0 V or 3.3 V, the value is approximately 0.6 (60%) of the value which is calculated using the method shown below. (1) 1-Port RAM At standby (CS = 0):0[µA/Bit] During operation (CS = 1):0.18 x f[µA/Bit]f: MHz (average access cycles) (2) 2-Port RAM At standby (CS = 0):0[µA/Bit] During operation (CS = 1):0.18 x f[µA/Bit]f: MHz (average access cycles) tWC tAS tWCS tDH tAH ADDRESS CS WR Data in valid tDS

Chapter 5: RAM GATE ARRAY S1L30000 SERIES EPSON 61 DESIGN GUIDE

5.10 RAM Symbols and How They Are Used

When the 1 port RAM uses a 32 word x 8 bit structure, the use of symbols is as given in Figure 5.8. This structure requires 5 address pins and 8 data input pins. As is shown in Figure 5.8, any unused address pins or data input pins should be tied to “Low or High” beginning with the most signiﬁcant bits. In addition, when multiple pieces of RAM are used, be sure to use as many symbols as the number of RAMs in the conﬁguration of the circuit. Figure 5.8 Example of the Use of RAM Symbols (RAM4: 32 words x 8 Bits) D31 . . A A A A A A A R W C S Y31 . . Customer’s Circuit Customer’s Circuit RAM4 . . . .

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62 EPSON GATE ARRAY S1L30000 SERIES

Chapter 6 Circuit Design Taking Testability Into Account Before a gate array is shipped the product is tested using an LSI tester. It is necessary to design the circuit keeping testability in mind to facilitate this testing. When designing the circuit, the following points should be carefully considered.

6.1 Considerations Regarding Circuit Initialization

When testing ICs using an LSI tester, or when verifying circuit functionality using a software simulator, the initial state of all sequential element is X (unknown). Consequently, very large test patterns may be necessary, depending on the circuit structure, to initialize the sequential elements or it may not be possible to initialize the circuits at all. Because of this, the circuits should be structured to facilitate easy initialization when they are designed (for example, by using sequential elements which have reset, set or preset functions).

6.2 Considerations Regarding Compressing the Test Patterns

As the gate densities of circuits increase, there is a tendency for test patterns to become larger as well. However, one must understand that there are constraints, such as shown below, to the LSI device tests. Number of events per test pattern: 64 K events or less Number of test patterns: 20 test patterns or less Total number of test pattern events: 256 K events or less These event and test pattern constraints include the test patterns for DC testing, test patterns for leakage testing, test patterns for test circuits, and the test patterns for RAM/ROM and megacell testing (prepared by EPSON). Direct inquiries regarding the number of test patterns and number of events per test pattern for the RAM/ROM and megacell testing to EPSON. When designing, please structure circuits in such a way as to increase the testability of the circuit (and to allow the compression of the test patterns), using methods such as including test pins which allow the input of clocks between the counter stages and adding test pins by which to monitor internal signals.

6.3 RAM Test Circuit

When a RAM is used it is necessary to test all bits before shipping the product. RAM terminals must be accessible via primary I/O pins. RAM test circuitry can be implemented, which multiplexes existing pin functionality with direct RAM access functionality so as to avoid increasing the designs pin count. Also, when multiple RAMs are used, we recommend that each RAM’s pins be accessible via unique I/O pins. However, when the number of external I/O pins is inadequate, each RAM’s pins may share common external I/O pins. Please insure that while in RAM test mode, all RAM CS pins can be held Low simultaneously to facilitate quiescent current meas urement. Figure 6.1 is an example of a test circuit for two word x 2 bit RAMs. When the test pin TEST is Low, then normal functioning is performed. However, when the test pin TEST is High, then the

Chapter 6: Circuit Design Taking Testability Into Account GATE ARRAY S1L30000 SERIES EPSON 63 DESIGN GUIDE external pins ICS1, ICS2, IWR1, IWR2, ID0, ID1, and IA0 can write data directly to the RAM, and at the same time the RAM outputs can be read from the external pins AY0, AY1, BY0 and BY1. Although it is possible to share the RAM pins with bi-directional pins or 3-state output pins, it is necessary to tie the bi-directional pins to either an input or an output state during RAM test. However, please do not share a bi-directional cell with a pull-up resistor with the RAM output, and do not share a input cell with a pull-up with the RAM CS pin, because doing so would make it impossible to measure the quiescent current. Figure 6.1 Example of a RAM Test Circuit

6.3.1 RAM Test Patterns

After incorporating RAM test circuitry, it is necessary to make test patterns for both the normal operating state and the test state of the chip. Checks are performed in the normal state to verify the connection with the user circuits, and are performed to insure that the test circuit is correct in the test state. Also, we request a test pattern to serve as a template when EPSON generates the RAM test pattern. See Figures 6.2 and 6.3 for an outline of how to generate this test pattern. Customer’s Circuit

Chapter 6: Circuit Design Taking Testability Into Account

64 EPSON GATE ARRAY S1L30000 SERIES

Figure 6.2 Generating the 1-port RAM Test Pattern X A [2 : 0] R W Y [3 : 0] C S D [3 : 0] X (Read Data) Strobe Expect X (2) Write (2) Write(1) Setup (2) W rite (3) Read The tester may perform repetitive write operations with the timing shown in the timing chart on the right. The timing of the RW signal should take this into account. Timing Chart RAM Signals AAADDDDRC 0120123WS YYYY 0123 0000000000..0000.. 0000000001..1111.. 1234567890..1234.. IIIIIIIIIT..OOOO.. NNNNNNNNNE..UUUU.. PPPPPPPPPS..TTTT.. ABCDEFGHIT..ABCD.. 0000000200.. IIIIIIIIII..OOOO.. 0000000000.. 0000000000.. 0000000000.. 0000000000.. 100000 XXXX..0001010101.. XXXX..0001010N11.. HLHL..0001010111.. XXXX..1011111101.. XXXX..1011111N11.. HHHH..1011111111.. XXXX..1110101101.. XXXX..1110101N11.. LHLH..1110101111.. $CLO INPH 500000 This pattern serves as a template for 1-port RAM tests PRESS format It is useful to place comments here. Please provide all I/O pins used in performing simulation. Reference the timing chart below to set timing. When a sequence is necessary to set the test mode, input the pattern here. [1] Access the lowest address, a middle address and the highest address. [2] Structure a single access from 3 events (test cycles). In the first event, set the data and the address. In the next event, perform a write. In the third event, perform a read. [3] Use an RZ waveform to describe the RW signal so that the write operation can be completed in a single event. [4] Change the data to be written for each address tested. [5] Verify that the results are the same as expected from the results of the simulations. E.. N..

Chapter 6: Circuit Design Taking Testability Into Account GATE ARRAY S1L30000 SERIES EPSON 65 DESIGN GUIDE Figure 6.3 Generating the 1-port RAM Test Pattern $RATE 200000 $STROBE 185000 $RESOLUTION 0.001ns $NODE INPA I 0 INPB I 0 INPC I 0 INPD I 0 INPE I 0 INPF I 0 INPG I 0 INPH P 20000 520000 INPI I 0 TESTEN I 0 OUTA 0 OUTB 0 OUTC 0 OUTD 0 $ENDNODE $PATTERN AAADDDDRC YYYY 0120123WS 0123 0 0001010101..XXXX.. 1 0001010N11..XXXX.. 2 0001010111..HLHL.. 3 1011111101..XXXX.. 4 1011111N11..XXXX.. 5 1011111111..HHHH.. 6 1110101101..XXXX.. 7 1110101N11..XXXX.. 8 1110101111..LHLH.. Please provide all I/O pins used in performing simulation. Reference the timing chart below to set timing. *Example of test pattern for 1-port RAM (APF format) This pattern serves as a template for 1-port RAM tests It is useful to place comment here. When a sequence is necessary to set the test mode, input the pattern here. [1] Access the lowest address, a middle address and the highest address. [2] Structure a single access from 3 events (test cycles). In the first event, set the data and the address. In the next event, perform a write. In the third event, perform a read. [3] Use an RZ waveform to describe the RW signal so that the write operation can be completed in a single event. [4] Change the data to be written for each address tested. [5] Verify that the results are the same as expected from the results of the simulations. X (1) Setup A [2 : 0 ] R W Y [3 : 0] CS D [3 : 0] X (Read Data) Strobe Expect (2) Write (3) Read X (2) Write (2) Write Timing Chart The tester may perform repetitive write operations with the timing shown in the timing chart on the right. The timing of the RW signal should take this into account.

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66 EPSON GATE ARRAY S1L30000 SERIES

Figure 6.4 Generating the 2-port RAM Test Pattern X (1) Setup RA [2 : 0] WR Y [3 : 0] CS D [3 : 0 ] X (Read Data) Strobe Expect (2) Write (3) Read X R D (2) Write (2) Write WR [2 : 0] The tester may perform repetitive write operations with the timing shown in the timing chart on the right. The timing of the RW signal should take this into account. Timing Chart Reference the timing chart below to set timing. *Example of test pattern for 2-port RAM (PRESS format) This pattern serves as a template for 2-port RAM tests It is useful to place comment here.RAM Signals AAAAAADDDDRRC 0120120123DWS YYYY 0123 000000000000000000 000000000000011111 123456789778901234 IIIIIIIIIIIIITOOOO NNNNNNNNNNNNNEUUUU PPPPPPPPPPPPPSTTTT ABCDEFGHIJKLMTABCD E N 00000000000200 IIIIIIIIIIIIIIOOOO 00000000000000 00000000000000 00000000000000 00000000000000 1000000 XXXX0 00000010100001 XXXX1 00000010100P11 HLHL2 00000010101011 XXXX3 10110111110001 XXXX4 10110111110P11 HHHH5 10110111111011 XXXX6 11111101010001 XXXX7 11111101010P11 LHLH8 11111101011011 $CLO INPI 500000 RRRWWW

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• Please provide all I/O pins used in performing simulation. When a sequence is necessary to set the test mode, input the pattern here. [1] Access the lowest address, a middle address and the highest address. [2] Structure a single access from 3 events (test cycles). In the first event, set the data and the address. In the next event, perform a write. In the third event, perform a read. [3] Use an RZ waveform to describe the RW signal so that the write operation can be completed in a single event. [4] Change the data to be written for each address tested. [5] Verify that the results are the same as expected from the results of the simulations.

Chapter 6: Circuit Design Taking Testability Into Account GATE ARRAY S1L30000 SERIES EPSON 67 DESIGN GUIDE Figure 6.5 Generating the 2-port RAM Test Pattern $RATE 200000 $STROBE 185000 $RESOLUTION 0.001ns $NODE INPA I 0 INPB I 0 INPC I 0 INPD I 0 INPE I 0 INPF I 0 INPG I 0 INPH I 0 INPI I 0 INPJ I 0 INPK I 0 INPL P 20000 520000 INPM I 0 TESTEN I 0 OUTA 0 OUTB 0 OUTC 0 OUTD 0 $ENDNODE $PATTERN RRRWWW AAAAAADDDDRWC..YYYY.. 0120120123DRS..0123.. 0 00000010100001.XXXX.. 1 00000010100P11.XXXX.. 2 00000010101011.HLHL.. 3 10110111110001.XXXX.. 4 10110111110P11.XXXX.. 5 10110111111011.HHHH.. 6 11111101010001.XXXX.. 7 11111101010P11.XXXX.. 8 11111101011011.LHLH.. *Example of test pattern for 2-port RAM (APF format) This pattern serves as a template for 2-port RAM tests Please provide all I/O pins used in performing simulation. Reference the timing chart below to set timing. It is useful to place comment here. When a sequence is necessary to set the test mode, input the pattern here. [1] Access the lowest address, a middle address and the highest address. [2] Structure a single access from 3 events (test cycles). In the first event, set the data and the address. In the next event, perform a write. In the third event, perform a read. [3] Use an RZ waveform to describe the RW signal so that the write operation can be completed in a single event. [4] Change the data to be written for each address tested. [5] Verify that the results are the same as expected from the results of the simulations. X (1) Setup RA [2 : 0] WR Y [3 : 0] CS D [3 : 0] X (Read Data) Strobe Expect (2) Write (3) Read X R D (2) Write(2) Write WR [2 : 0] The tester may perform repetitive write operations with the timing shown in the timing chart on the right. The timing of the RW signal should take this into account. Timing Chart

Chapter 6: Circuit Design Taking Testability Into Account

68 EPSON GATE ARRAY S1L30000 SERIES

6.4 Function Cell Test Circuits

When function cells are used, then testing the operation of all circuits (including the user circuits) requires a vast number of test patterns and a great amount of time. It is because of this that it is necessary to design test circuits able to verify the operation of each independent functional cell and user circuit, as was done with the RAM blocks. When designing the test circuits, please keep the following cautions and considerations in mind. For more details, contact EPSON.

6.4.1 Test Circuit Structures

(1) Provide test circuitry which facilitates direct access to all pins of each functional cell via I/ O pins. Add a test circuit (connected to a terminal) which isolates each functional cell from the surrounding circuits. (2) Even when functional cell input pins are ﬁxed to logic 0 or logic 1, design test circuitry which insures access to all functional cell pins. (3) Even when functional cell output pins are not used, design test circuitry which insures access to all functional cell pins. (4) Each functional cell pin must be connected to a unique I/O pin. (5) Do not use sequential elements in the test circuitry for functional cells. (6) Do not invert the input signal from the test input terminal and input it into the functional cell. Similarly, do not invert the functional cell output signal and output it to the test output terminal. (7) There is no need to design a test circuit when the functional cell input pins and output pins are directly connected to the I/O pins. (8) Do not use an input cell with pull-up or a bi-directional cell with pull-up as the test mode switch pin (although a bi-directional cell with pull-down may be used).

6.4.2 Test Patterns

The test patterns can be categorized into the following two types: 1) Test patterns to test only the user’s circuit. 2) Test patterns to test all circuits. 3) Test patterns to test the functional cells only. Test patterns that the customers generate are of type 1. Customers are not required to generate test patterns of type 2. EPSON maintains test patterns to be used for type 2. Please be advised that EPSON will not dis- close information pertaining to the functional cell test patterns.

6.4.3 Test Circuit Data

Please provide the following information regarding functional test circuitry. This information is required for functional cell testing during simulation and IC device testing. (1) Please clearly deﬁne the I/O pin to functional cell pin connectivity while in test mode.

Chapter 6: Circuit Design Taking Testability Into Account GATE ARRAY S1L30000 SERIES EPSON 69 DESIGN GUIDE (2) When the test circuits are structured in such a way that a single test terminal is able to test multiple functional cells, please clearly deﬁne the names of the functional cells which can be selected and the type of the test modes, and their relationships. (3) Please clearly deﬁne pass numbers on the names of the functional cells on the drawings, and clearly deﬁne the test terminals and their association with functional cells, especially when identical functional cells are used more than once. (4) Please clearly deﬁne the method of switching into test mode. When functional cells are to be used, please contact Epson or its distributor. In addition, be sure to read the “Functional-Cell Design Guide.”

6.5 Test Circuit Which Simpliﬁes AC and DC Testing

The S1L30000 Series requires the construction of test circuits so that DC testing and AC testing can be done efﬁciently. If the customer experiences difﬁculties while implementing test circuitry, then the customer should contact EPSON. Figure 6.4 shows speciﬁc examples of test circuits. This ﬁgure should be referenced when designing test circuits. Recommended test circuit control and monitor pin conﬁgurations are shown below. (1) Test Circuit Control and Monitor Pins Please add or select the following 4 types of test pins. * Dedicated input pin for testing: 1 pin (test enable signal) * Test mode select input pin: 3 pins (can be functionally shared with input pins of application) * Monitor output pin for AC testing: 1 pin (can be functionally shared with output pin of application) * Monitor output pin for DC testing: 1 (can be functionally shared with output pin of appli- cation) Table 6.1 Table of Test Terminal Constraints Test Pin Type Number of Pins Name of Pins (See Fig. 6.4) Constraints, Notes, Etc. Test Enable Pin 1 pin TSTEN Dedicated input pin Use ITST1. H: Test mode L: Normal mode Test Mode Pins 3 terminals INP0 INP1 INP2 May be shared with existing input pin. Do not share with an input pin associated with a critical path. Monitor output pin for AC testing 1 pin OUT3 May be shared with existing output pin. Do not share with a bidirectional, 3- state terminal or with an N-channel open-drain cell.

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70 EPSON GATE ARRAY S1L30000 SERIES

(2) DC Testing Measurements are performed to insure that all input and output pins adhere to DC char- acteristic speciﬁcations. When test circuitry is not implemented, it is necessary for the customer to generate test patterns by which the DC characteristics can be measured. The amount of work in generating the test patterns may increase dramatically when there are no test circuits. The task of generating test patterns and measuring the DC characteristics is simpliﬁed by using test circuits. (3) AC Testing AC testing is a pin-to-pin (i.e. input pin to output pin) delay measurement. If device test- ing is not performed at actual operating frequency, device performance is assured through delay measurements along speciﬁc paths. Also, the AC test monitor output pin is used to evaluate the variance between lots in the manufacturing process by measuring a deﬁned AC path (cell name: ACP1). (When test circuits are used, be sure to insert cell ACP1 when designing the AC path test circuit.) (4) Adding the Test Mode Control Circuit The following items (a through j) pertain to test circuit implementation. Please refer to the test circuit examples of Figure 6.4. a. Select 4 test input pins and 2 test output pins. Dedicated input pin for test enable/disable:1 pin Dedicated/shared input pins for test mode select:3 pins Dedicated/shared output pin for AC monitor:1 pin Dedicated/shared output pin for DC monitor:1 pin b. The dedicated input pin for test enable/disable (TSTEN) must use cell ITST1. c. The dedicated or shared input pins for test mode selection (INP1, INP1 and INP2) can use any input buffer cell type. Avoid sharing these test inputs with critical path input pins of the application. d. The dedicated or shared output pins for AC and DC monitoring (OUT3 and OUT4) can use any uni-directional output buffer type (except 3-state type). Avoid sharing these test outputs with critical path output pins of the application. e. All pre-drivers for output and bi-directional pin conﬁgurations must have test mode functionality. f. Please utilize the test mode control circuit (TCIR). g. The primary test enable/disable signal (output pin ‘IN’ of cell ITST1) should be con- nected to the ‘TST’ input pin of functional block TCIR. When this signal is enabled (set to logic High), the test mode control circuitry (block TCIR) becomes functional and Monitor output pin for DC testing 1 pin OUT4 May be shared with existing output pin. Do not share with a bidirectional, 3- state terminal or with an N-channel open-drain cell. All output and bi- directional pins -- -- Uses pre-drivers with test mode select (i.e. PDV1AT, PDV2AT, etc.) Table 6.1 Table of Test Terminal Constraints

Chapter 6: Circuit Design Taking Testability Into Account GATE ARRAY S1L30000 SERIES EPSON 71 DESIGN GUIDE facilitates AC, DC and quiescent current testing. The secondary test enable/disable signal (output pin ‘LG’ of cell ITST1) should be con- nected to the ‘VTI’ input pin of functional block TCIR. This signal is used to test all input pin voltage levels (V IL and VIH). h. Three dedicated shared input signals (output pins of uni-directional input buffer cells) should be connected to the ‘IP0’, ‘IP1’ and ‘IP2’ input pins of functional block TCIR. A ﬁrst dedicated/shared input signal (INP0 in Figure 6.4) should be connected to input pin ‘IP0’ of functional block TCIR. This signal will control the mode of all bi-directional I/O cells which utilize pre-drivers with test functionality. When ‘IP0’ is state High and ‘IP2’ is state High , all bi-directional I/O will be placed in input mode, and all 3-state outputs will be in high-impedance state. When ‘IP0’ is state Low, all bi-directional and 3-state I/O will be in output mode. A second dedicated/shared input signal (INP1 in Figure 6.4) should be connected to input pin ‘IP1’ of functional block TCIR. This signal controls output data while in test mode. The data which appears at pin ‘IP1’ will be passed to all output and bi-direc- tional I/O cells when ‘IP2’ is state Low. This signal is used for DC characterization (V OH and VOL ) testing. A third dedicated/shared input signal (INP2 in Figure 6.4) should be connected to input signal pin ‘IP2’ of functional block TCIR. This signal controls all output and bi-direc- tional signals excluding the AC monitor output pin during AC testing. When input sig- nal ‘IP2’ is state High and all outputs remain in stable state High so as to minimize switching noise during AC testing. i. The following describes the recommended connections for the output pins of the test circuit functional block TCIR. The TCIR output pin ‘ACO’ is used for AC characterization testing. This output of TCIR must be connected to one and only one ‘TD’ input pin of a user selected pre-driver, which is connected to a uni-directional output driver (not 3-state). The TCIR output pin ‘VTO’ is used for DC monitoring of input pin voltage levels (V IL and VIH). This output of TCIR must be connected to one and only one ‘TD’ input pin of a user selected pre-driver, which is connected to a uni-directional output driver (not 3- state). The TCIR output pin ‘TS’ is the test mode control signal. This output is used to put all pre-drivers connected to output and bi-directional I/O’s into test mode. When ‘TS’ is state High, all pre-drivers are in test mode. The TCIR output pin ‘TD’ is used for DC characterization testing. This output is used as test data for all output and bi-directional I/O pre-drivers to facilitate V OH and VOL test- ing. The TCIR output pin ‘TE’ is used for test mode bi-directional enable (or control). This output is connected to all 3-state and bi-directional pre-driver’s ‘TE’ input pin. When ‘TE’ is state Low, all 3-state and bi-directional drivers are placed in output mode. j. Fan-out violations which may occur on TCIR output pins ‘TS’, ‘TD’ and ‘TE’ can be ignored.

Chapter 6: Circuit Design Taking Testability Into Account

72 EPSON GATE ARRAY S1L30000 SERIES

(5) Setting the Test Mode (Please refer to Figure 6.4) a. DC Test

Quiescent Current Measurement Mode TSTEN . . . High INP0 . . . Low INP1 . . . X (High or Low) INP2 . . . Low
Output Characteristics (V OH /VOL ) Measurement Mode TSTEN . . . High INP0 . . . High INP1 . . . High for V OH test and Low for VOL test INP2 . . . This controls the bi-directional and 3-state pin mode High . . . Hi-Z (input) mode* Low . . . Output mode * Can be used as 3-state and bi-directional off-state leakage current measurement mode.
Input Logic Level Mode TSTEN . . . High INP0 . . . High INP1 . . . High INP2 . . . High Measurement Terminal . . . High for V IH and Low for VIL OUT4 . . . Is used to monitor input pin functionality during testing b. Dedicated AC Path Measurement Mode TSTEN . . . High INP0 . . . Low INP1 . . . Change from High to Low, then change from Low to High OUT3 . . . Is used to monitor delay from INP1 INP2 . . . High Gener ating the Test Pattern It is necessary for the customer to design test patterns at the same time that the customer designs the test circuits so that the DC testing and the AC testing can be performed in an efﬁcient manner. Figures 6.5 and 6.6 show a speciﬁc example of the test pattern related to the test circuits in Figure 6.4. The following should be kept in mind when generating the test patterns: a. Please generate a test pattern to exercise test circuitry separate from standard appli- cation functional test patterns. b. Test circuit test patterns must specify all input, output and bi-directional I/O signals. c. Please insure that the dedicated test enable pin (i.e. TESTEN) is present and set input state to ‘0’. d. When the input level on the test pin (TSTEN) is high (= 1), all of the pullup/pulldown resistors and the output logic of the bus hold circuit are deactivated. In the creation of the test pattern, make sure that in this state no bidirectional pins will be in Hi-Z mode.

Chapter 6: Circuit Design Taking Testability Into Account GATE ARRAY S1L30000 SERIES EPSON 73 DESIGN GUIDE <Precautions on the test circuit> In cases in which there is only one dedicated test input pin, the input logic level of the input pins assigned for two test-mode select input pins (INP0, INP1) cannot be measured during test in input-logic-level veriﬁcation mode. <Inner Circuit of TCIR> Figure 6.6 Test mode control circuit “TCIR” IBC IN I_29 INP0 INP1 INP2 TSTEN IBC I_20 IBC I_28 IBC I_22 ITST1 I_1 IP0 IP1 IP2 TD TS TE ACO I_2 TCIR UO2 I_13 OUT1 I_17 A TD TS P N UO2 I_12 OUT3A TD TS P N PDV1T PDV1T I_16 A E TD P N PDV2AT I_8 TE TS I_23 UC2P1 BID1 OUT2 UO2 A E TD P N PDV2AT I_26 TE TS UO2 I_11 OUT4A TD TS P N PDV1T I_27 TST VTI VTO Application Circuit I_14 IP0 IP1 IP2 TST TD TE I_11 BUF1 I_10 BUF1 I_2 I_5 I_3 O2 I_4 VTI VTO I_9 BUF1 I_1 BUF1 ACO I_7 NA2 I_6 ACP1 TS

Chapter 6: Circuit Design Taking Testability Into Account

74 EPSON GATE ARRAY S1L30000 SERIES

Figure 6.7 Example of the generation of a test pattern when there is a test option 00000000000 00000000011 12345678901 TIIIIBBOOOO SNNNNIIUUUU TPPP DDTTTT E012 111234 N X I

1000000 IIIIII00000

000000..00 1 10.0..XXXXX 2 1001..HHHLX 3 1011..HHHHX 4 1001..HHHLX 5 1101.0ZHZLX 6 1111.1ZHZHX 7 1100..LLLLX 8 1110..HHHHX

Example of test pattern for AC & DC test (press format) ;pull-up/down off ;AC path output(Low), other output all High ;AC path output(High), other output all High ;AC path output(Low), other output all High ;Off state except normal output (Low input) ;Off state except normal output (High input) ;Output all Low ;Output all High note) . is 1 or 0 input Measure static current consumption Measure the dedicated AC path Measure the off-state leakage current Measure the output characteristics

Chapter 6: Circuit Design Taking Testability Into Account GATE ARRAY S1L30000 SERIES EPSON 75 DESIGN GUIDE Figure 6.8 Example of the generation of a test pattern when there is a test option $DESIGN testckt $RATE 200000 $STROBE 185000 $RESOLUTION 0.001ns $IOCONT AA08.E E0 BID1 $ENDIOCONT $NODE TESTEN I 0 INP0 I 0 INP1 I 0 INP2 I 0 IN I 0 BID1 BU 0 OUT1 0 OUT2 0 OUT3 0 OUT4 0 $ENDNODE $PATTERN

Example of test pattern for AC & DC test (APF format) pull-up/down off AC path output(Low), other output all High AC path output(High), other output all High AC path output(Low), other output all High Off state except normal output (Low input) Off state except normal output (High input) Output all Low Output all High TIIIIBOOOO SNNNNIUUUU TPPP DTTTT E012 11234 N IIIIIBOOOO U 0....XXXXX 10.0.XXXXX 1001.HHHLX 1011.HHHHX 1001.HHHLX 1101.0HZLX 1111.1HZHX 1100.LLLLX 1110.HHHHX $ ENDPATTERN # EOF note) .is 1 or 0 input

Chapter 7: Propagation Delay and Timing

76 EPSON GATE ARRAY S1L30000 SERIES

Chapter 7 Propagation Delay and Timing Propagation delay time is determined by the intrinsic cell delay and by the per-load delay, which is a function of the wire interconnect and fan-in capacitances. Delay times vary depending upon power supply voltage, ambient temperature, and process conditions. They also vary depending on factors involved in the structure of the circuit, input waveform, input logic level, and the mirror effect. Post Simulation uses more acculate environment.

7.1 Simple Delay Models

Simple propagation delay time tpd can be calculated using the following formula: tpd = T0 + K x (ΣLoad A + Load B) where, T0: Intrinsic cell delay [ps] K: Load delay coefﬁcient [ps/Lu] Load A: The input load capacitance due to fan-in [Lu] Load B: The interconnect load capacitance [Lu] NOTE: The values for T0 and K differ depending upon the operating voltage, the ambient temperature, and the process conditions. Use the values provided in the “Gate Array S1L30000 Series MSI Cell Library.” The unit “Lu” stands for loading unit, which is equivalent to one “IN1” input fan-in. Typ. values for T0 and K (VDD = nominal value, Ta = 25oC, and process = nominal value) are found in the “Gate Array S1L30000 Series MSI Cell Library.” Select Typ. values for T0 and K according to the target power supply voltage. The Min. value for T0 and K (where VDD is the Max. value, Ta = Min. value and process = fast) and the Max. value for T0 and K (where VDD = Min. value, Ta = Max. value, and process = slow) are calculated by multiplying the Typ. value, described above, by the delay coefﬁcient M. (These Min. and Max. values are required to verify ASIC operation over commercial and industrial variances in supply voltage, ambient temperature and process. The delay coefﬁcient M can be calculated using the following formula: M = M V x MT x MP where, M V: Delay Multiplier due to voltage variation M T: Delay Multiplier due to temperature variation M P: Delay Multiplier due to process variation Although values for MV and MT can be obtained by reading them off of the characteristic graphs in the “Gate Array S1L30000 Series MSI Cell Library,” please use the duration delay coefﬁcient vaues M, given in Table 7.1. Also, please direct inquiries to the EPSON regarding ASIC operation outside of the limits shown in Table 7.1. Note 1: The Typ. value for VDD = 3.0 V is not listed in the “Gate Array S1L30000 Series MSI Cell Library.” As is Note 2: The delay for the pre-driver with level shifter cannot be calculated by merely multiplying a coefficient as shown above. Pre-calculated Min. values and Max. values are listed in the “Gate Array S1L30000 Series MSI Cell Library” along with the Typ. values. Please see Section 11.4 of Chapter 11 “Delay Calculations for Dual Power Supplies.”

Chapter 7: Propagation Delay and Timing GATE ARRAY S1L30000 SERIES EPSON 77 DESIGN GUIDE However, the above calculation method applies to some dual-power-supply predrivers with I/O-cell-level shifters. For details, refer to the procedure for calculation of delay times for the case of the dual power supply in Chapter 11.

7.2 Load Due to Input Capacitance (Load A)

Cell propagation delay is dependent upon the sum of input pin capacitances (Load A) attached to the cell’s output terminal (i.e. the sum of the fan-ins). The input capacitances (fan-ins) of each gate and the output terminal load constraints (fan-outs) are listed in the “Gate Array S1L30000 Series MSI Cell Library. Cell output terminal fan-out must not exceed the listed Figure 7.1 Example Calculating Load A Table 7.1 Delay Coefﬁcient M (Used For All Cells Excluding Pre-Driver With Level Shifter) Conditions M Value Usage Min. Typ. Max. Power supply voltage: 5.0 V ± 5%; Ta: 0 to 70oC 0.59 1.00 1.62 Use after multiplying the Typ. values of T0 and K for VDD = 5.0 V Power supply voltage: 5.0 V ± 10%; Ta: -40 to 85oC 0.53 1.00 1.72 Power supply voltage: 3.3 V ± 10%; Ta: 0 to 70oC 0.51 1.00 1.82 Power supply voltage: 3.3 V ± 10%; Ta: -40 to 85oC 0.47 1.00 1.87 Use after multiplying the Typ. values of T0 and K for VDD = 3.3 V Power supply voltage: 3.0 V ± 10%; Ta: 0 to 70oC 0.56 1.11 2.05 Power supply voltage: 3.0 V ± 10%; Ta: -40 to 85oC 0.51 1.11 2.10 IN1 IN2 NA2 NO2 2.1

Chapter 7: Propagation Delay and Timing

78 EPSON GATE ARRAY S1L30000 SERIES

The fan-in values for IN2, NA2, and NO2 can be obtained from Table 7.2. Their sum is the Load A value, as seen by the IN1 output terminal in load units (Lu). ΣLoad A (IN1) = (Fan-in of IN2) + (Fan-in of NA2) + (Fan-in of NO2) = 2.1 + 1 + 1 = 4

7.3 Load Due to Interconnect Capacitance (Load B)

The load resulting from the capacitance of the interconnect between cells (Load B) cannot be accurately calculated until the ASIC layout has been performed. However, Load B is correlated with the number of branches (number of nodes) connected to the wire, so it is possible to statistically estimate the Load B value. The estimated interconnect capacitance for each master is listed in the “Gate Array S1L30000 Series MSI Library.”

7.4 Propagation Delay Calculations

Below we present a sample propagation delay time calculation using the circuit shown in Figure 7.2 (assume an operating voltage of 5.0 V) and the data of Table 7.3 Figure 7.2 Circuit for the Sample Calculation of the Propagation Delay Time Table 7.2 Data Used in the Example of Calculating Load A Cell Input Output Pin Fan-in Pin Fan-out IN1 A 1.0 X 23.8 IN2 A 2.1 X 44.1 NA2 A1 1.0 1.0 X 21.7 NO2 A1 1.0 1.0 X 11.5 IN1 IN2 NA2 NO2 B C D A P 2.1

Chapter 7: Propagation Delay and Timing GATE ARRAY S1L30000 SERIES EPSON 79 DESIGN GUIDE For this example, assume that Load B of NODE P = 2 (Lu), and assume that Load B of Nodes B, C and D = 0 (Lu). Also, note that propagation delay varies depending on the output terminal state transition (rising or falling edge). Below please ﬁnd examples calculating the propagation delays for paths A to P , A to B, A to C and A to D for both rising and falling cases under Typ. operating conditions at 5 V. 1. PATH A to P:t pd = t pd (IN1) tpd (Arising to Pfalling) = T0 + K x (Load A + Load B) = 197.8 (ps) tpd (Arising to Pfalling) = T0 + K x (Load A + Load B) = 303.4 (ps) 2. PATH A to B: tpd = tpd (IN1) + tpd (IN2) tpd (Arising to Brising) = tpd (Arising to Pfalling) + tpd (Pfalling to Brising) = 197.8 + T0 = 197.8 + 57 = 254.8 (ps) tpd (Afalling to Bfalling) = tpd (Arising to Prising) + tpd (Prising to Bfalling) = 303.4 + T0 = 303.4 + 68 = 371.4 (ps) 3. PATH A to C:tpd = t pd (IN1) + tpd (NA2) tpd (Arising to Crising) = tpd (Arising to Pfalling) + tpd (Pfalling to Crising) = 197.8 + T0 = 197.8 + 112 = 309.8 (ps) Table 7.3 Table of Characteristics (Power Supply Voltage = 5.0 V) Cell Input Output tpd (Typ.) Pin Fan-in Pin Fan-out From To Edge T0 (ps) K (ps/ Lu) IN1 A 1.0 X 23.8 A X 64 39.9 67 21.8 IN2 A 2.1 X 44.1 A X 57 21.5 68 11.8 NA2 A1 1.0 X 21.7 A X 112 43.0 101 33.0 NO2 A1 1.0 X 11.5 A X 135 76.1 97 22.3

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80 EPSON GATE ARRAY S1L30000 SERIES

tpd (Afalling to Cfalling) = tpd (Afalling to Prising) + tpd (Prising to Cfalling) = 303.4 + T0 = 303.4 + 101 = 404.4 (ps) 4. PATH A to D:tpd = tpd (IN1) + tpd (NO2) tpd (Arising to Drising) = tpd (Arising to Pfalling) + tpd (Pfalling to Drising) = 197.8 + T0 = 197.8 + 135 = 332.8 (ps) tpd (Afalling to Dfalling) = tpd (Afalling to Prising) + tpd (Prising to Dfalling) = 303.4 + T0 = 303.4 + 97 = 400.4 (ps)

7.5 Calculating Output Buffer Delay

As was discussed in Chapter 4, all of the output buffers are isolated from the pre-drivers in the S1L30000 Series. Because of this, the output buffer delay times are the sum of the output cell delay times and the pre-driver delay times. Assuming that the load capacitance connected to the output buffer is C L, the delay time tpd is calculated as follows: tpd = T0 (Output cell) + K (Output cell) x CL/10 + T0 (pre-driver) + K (pre-driver) x Output Cell Input Capacitance T0 (Output cell): The intrinsic delay of the output cell [ps] T0 (Pre-driver): The intrinsic delay of the pre-driver [ps] K (Output cell): The output cell load delay coefﬁcient [ps/10 pF] K (Pre-driver): The pre-driver load delay coefﬁcient [ps/Lu] C L: The attached load capacitance [pF] Please reference the “Gate Array S1L30000 Series MSI Cell Library” regarding the intrinsic delays and load delay coefﬁcients of the output cells and pre-drivers.

7.6 Sequential Cell Setup/Hold Time

A critical factor to analyze when designing an ASIC is sequential cell usage and operation. Data which is to be stored by sequential logic must arrive before the gating or clock signal to insure sufﬁcient data setup and proper operation. That same data must remain unchanged or held subsequent to the gating or clock signal. These timing rules and others (see below) must be taken into consideration when designing sequential logic. Sequential cell speciﬁc timing values can be found in the “Gate Array S1L30000 Series MSI Cell Library.” (1) Min. Pulse Width: TPWC, TPWS or TPWR The Min. pulse width refers to the Min. value of the time between a leading edge and a trailing edge of an input pulse waveform, as seen at the clock, set, preset or reset terminal of a sequential cell. Circuit malfunction may occur when a narrow pulse is applied which volates this constraint. The Min. pulse widths may be of the following three types:

Chapter 7: Propagation Delay and Timing GATE ARRAY S1L30000 SERIES EPSON 81 DESIGN GUIDE TPWC: Clock signal Min. pulse width violation. TPWS: Set signal Min. pulse width violation. TPWR: Reset signal Min. pulse width violation. (2) Setup Time: TEROR/SETUP “Setup time” refers to the required time interval in which the data state must be set before the active edge transition of the gate or clock signal in order to correctly store the data in a sequential cell or an MSI function which is made up of sequential cells. (3) Hold Time: TEROR/HOLD “Hold time” refers to the required time interval in which the data state must be held after the active edge of the gate or clock signal in order to correctly store the data in a sequen- tial cell or an MSI function which is made up of sequential cells. (4) Release Time (Setup): CSERO, CRERO/SETUP “Release time” (setup) refers to the required time interval between a set/reset signal tran- sition to inactive and the active edge of the gate or clock signal in a sequential cell of an MSI function which is made up of sequential cells. (5) Release Time (Hold): CSERO, CRERO/HOLD “Release time” (Hold) refers to the required time interval between a set/reset signal transi- tion to active and the active edge of the gate or clock signal in a sequential cell or an MSI function which is made up of sequential cells. (6) Set/Reset (Setup): RSERO/SETUP “Set/Reset” (Setup) refers to the required time interval after a set input state is released until it is possible to have a rising edge on a reset input in a sequential cell or MSI function which is made up of sequential cells. (7) Set/Reset (Hold): RSERO/HOLD The “Set/Reset” (Hold) refers to the required time interval after a reset input state is released until it is possible to have a rising edge on a set input in a sequential cell or MSI function which is made up of sequential cells. Figure 7.3: DFSR (Example) Figure 7.3 DFSR D C S R Q XQ DATA CLOCK RESET SET Q XQ

Chapter 7: Propagation Delay and Timing

82 EPSON GATE ARRAY S1L30000 SERIES

Figure 7.4 Timing Wave Form (Explanatory Diagram for Numbers 1-5) Figure 7.5 Timing Wave Form (Explanatory Diagram for Numbers 6-7) The setup and hold times for ﬂip-ﬂop circuits of the S1L30000 Series are listed in the cell library in the format shown in Table 7.4. When actually using these ﬂip-ﬂop circuits, refer to the characteristics of each cell. TPWC TPWC SETUP (TEROR) HOLD (TEROR) RELEASE (HOLD) (CRERO) TPWS (TPWR) RELEASE (SETUP) (CRERO) TPWS (TPWR) CLOCK DATA SET (RESET) SET (RESET) RELEASE (HOLD) (RSERO) RELEASE (SETUP) (RSERO) SET SET RESET

Chapter 7: Propagation Delay and Timing GATE ARRAY S1L30000 SERIES EPSON 83 DESIGN GUIDE NOTE: P=transition from 0 to 1 level or Positive pulse N=transition from 0 to 1 level or Negative pulse

7.7 Chip Internal Skew

Because of transistor characteristic variance within an ASIC, the tpd of similar gates within an ASIC may vary. Skew is a term used to describe this variance. Skew must be taken into account so as to provide margin in timing critical portions of logic to insure proper operation. Table 7.4 DFSR Timing Characteristics (Example) Pin Setup time1 tsu(ps) Hold time, th(ps) Pulsewidth, tw (ps) Setup time, tsu(ps) Hold time, th(ps) Pulsewidth, tw (ps) C(P) to D 924 508 - 1318 738 - C(P) to S 610 751 - 872 1049 - C(P) to R 699 733 - 1013 1028 - R(P) to S(P) 884 673 - 1207 934 - Table 7.5 Skew Within the Chip Cell Layout Area Skew Internal cells All regions 5% I/O cell All regions 5%

Chapter 8: Test Pattern Generation

84 EPSON GATE ARRAY S1L30000 SERIES

Chapter 8 Test Pattern Generation Test patterns must be generated once the logical design has been completed. Test patterns are used to simulate and verify circuit functionality. Test patterns are also used for product inspection prior to shipment. Please keep the following guidelines in mind when generating test patterns, thereby improving manufacturability and insuring product quality.

8.1 Testability Considerations

Because the test pattern is used in the ﬁnal inspection of the product before it is shipped, it must be able to test all circuits within the LSI. If there are areas within the circuits of the LSI which are untested, it will not be possible to test those areas before the product is shipped, and thus there will be the danger of shipping defective product. It is difﬁcult to test all of the circuits within the LSI, so it is important to consider testability during the process of designing the circuit. If the Epson-recommended test circuit is included in your system, the DC test and various other conditions required for test patterns can be set easily. For details, refer to Chapter 6, “Circuit Conﬁguration for Facilitating DC and AC Tests.”

8.2 Waveform Types

Although the test pattern is normally a series of “0” and “1” when a simulation is performed or the LSI tests are run, the input wave forms can be delayed, and the wave forms can be changed. The wave forms which can be used when the test pattern is generated include the following two types: Figure 8.1 Constraints on Timing Settings NRZ wave RZ wave Output wave Strobe Test cycle Input delay Pulse width

Chapter 8: Test Pattern Generation GATE ARRAY S1L30000 SERIES EPSON 85 DESIGN GUIDE NRZ (Non Return to Zero) A signal whose state changes no more than once per test pattern cycle is deﬁned as being an NRZ type waveform. This waveform type can be delayed by a constant offset from the beginning of the test pattern cycle boundary. RZ (Return to Zero) A signal whose state may change twice per test pattern cycle is deﬁned as being an RZ type waveform. This waveform type can be delayed by a constant offset from the beginning of the test pattern cycle boundary. This waveform type is useful for deﬁning clock signals using positive or negative pulse deﬁnitions.

8.3 Constraints on the Types of Test Patterns

During design veriﬁcation, test patterns can be set to accurately reﬂect actual operating frequency, yet in order to be used in ﬁnal device inspection, the test patterns must adhere to constraints of the LSI tester. These constraints are explained below and should be kept in mind during test pattern development.

8.3.1 Test Period

The test period must be 100 nsec or longer in duration and is deﬁned in 1 nsec intervals. (Recommended test period: 200nsec.) In addition, deﬁne the test period in accordance with the limitations speciﬁed in Section 8.3.5, “Strobe”. Also, for the number of events, follow Section 6.2, “Considerations Regarding Compressing the Test Patterns” on page 62 in the creation of a test pattern.

8.3.2 Input Delay

(a) Range of Input Delays 0 nsec < input delay value < strobe point. The input delay is deﬁned in 1 nsec intervals within the range above. See Section 8.3.5 below regarding constraints on the strobe point. (b) Input delay values must have a minimum of 3 nsec resolution from one another. 3 nsec or above. (c) Types of input delays No more than 8 types of input delays can be used in a single test pattern. A 0nS delay is also counted as 1 type. When there are identical delays on an RZ wave form as on an NRZ wave form, these are counted as different delay types. When 2 RZ wave forms have identical delay values or 2 NRZ wave forms have identical delay values, these are counted as identical delay types.

Chapter 8: Test Pattern Generation

86 EPSON GATE ARRAY S1L30000 SERIES

8.3.3 Pulse Width

Pulse widths for RZ wave forms must be 15 nsec or more.

8.3.4 Input Waveform Format

The input wave form must assume a value of “0”, “1”, “P”, or “N”. “P” and “N” indicate RZ positive pulse and negative pulse type. Use state “0” to disable positive pulse RZ waveform, and state “1” to disable negative pulse RZ waveform (i.e. RZ type state combinations of (0,P) and (1,N) are valid, while state combinations of (0,N) and (1,P) are invalid). Do not use a bi-directional pin as the clock.

8.3.5 Strobe

The constraints on the strobe are as follows. (a) Only a single strobe may be used within a single test pattern event. (b) The smallest value for a strobe should be at least 30 nsec after the completion of all out- put signal changes, where the change results from input signals state change applied dur- ing that event. (c) The maximum value for the strobe should be the test period minus 15 nsec. (d) The strobe is deﬁned in 1 nsec intervals.

8.4 Notes Regarding DC Testing

The test pattern is used for functional testing and DC testing of the LSI. Please generate the test patterns so that the following DC tests can be performed. DC tests are performed to verify the DC parameters of the LSI. Because the DC tests perform measurements on the trailing edge of the measurement events, those terminals which are measured must not have state changes after the strobe during the measurement events. The DC parameters measured are as described below: (a) Output Driver Test (V OH , VOL ) The output buffer current driving capabilities are tested. The terminals which are to be tested are caused to enter the output level through the operation of the device, the speci- ﬁed current load is applied, and the level of the voltage drop is measured. In order to perform the output driver tests, it is necessary for the test pattern to cause all of the terminals to enter all of the states which are obtained when the device is operating. Also, the states must be such that they do not change even if the measurement event extends the test period indeﬁnitely.

Chapter 8: Test Pattern Generation GATE ARRAY S1L30000 SERIES EPSON 87 DESIGN GUIDE (b) Quiescent Current Test (IDDS ) The quiescent current is the leakage current which ﬂows to the LSI power supply when the input is in an ﬁxed state. While generally this current is extremely small, this measure- ment must be done in a state where there are no other currents ﬂowing aside from the leakage current. To do this, all of the following conditions must be fulﬁlled, and there must be two or more places wherein there are events which can measure the quiescent cur- rent. (1) The input terminals are all in a ﬁxed state. (2) The bi-directional terminals are given High level or Low level inputs or are in an out- put state. (3) There are no oscillators or operating functions within the circuit. (4) None of the internal 3-state buffers (internal bus) are in a ﬂoating or a contention state. (5) The RAM, the ROM, and the megacells are not in states wherein current is ﬂowing. (6) An High level input is applied to input terminals which have pull-up resistors. (7) Bi-directional terminals with pull-up resistors attached are either given High level inputs or are producing High level outputs. (8) Bi-directional terminals with pull-down resistors are either in an input state or are producing Low level outputs. (c) The Input Current Test The input current test measures the inputs to the input buffer. The test items include measurements of input leakage current and of pull-up/pull-down currents. The tests for these measurement items are performed by applying a V DD level or VSS level voltage to the terminal being measured, and measuring the current which ﬂows. In other words, the test is performed by applying either an High level or a Low level voltage to the terminal being measured. For example, when a V DD (High level) signal is applied during the test to a terminal being measured and which is in a state having an Low level, then there is the potential for this to cause the state to change from Low to High in the terminal being measured, and the potential that this will cause the LSI to function incorrectly. In order to measure the input current tests, a test where a V DD level is applied at an event where there is an High input to the terminal being measured in the test pattern, and a test is performed where a VSS level is applied in the event where a Low is applied. Because of this, it is not possible to perform these tests when the terminals being measured are not in these states in the test pattern. The input current tests are further broken down into the following classiﬁcations. (1) Input Leakage Current Test (I LH . ILL) Measurements are performed regarding the input current of the input buffers which have no pull-up/pull-down resistors. The current which ﬂows when an High level voltage is applied to the input buffer is called ILH , and its maximum current value is guaranteed. In order to perform this test there must be an event in the test pattern which causes the input terminal to be mea- sured to have an High level input. Bi-directional terminals must have High level inputs in the input state. The current which ﬂows when a Low level voltage is applied to the input buffer is called I LL, and its maximum value is guaranteed. In order to perform this test there must be an event in the test pattern which causes the input terminal to be measured

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88 EPSON GATE ARRAY S1L30000 SERIES

to have a Low level input. Bi-directional terminals must have Low level inputs in the input state. (2) Pull-up Current Tests (IPU ) This test measures the current which ﬂows when an Low level voltage is applied to an input buffer having a pull-up resistance. In order to perform this test there must be an event in the test pattern which causes the input terminal to be measured to have an Low level input. Bi-directional terminals must have Low level inputs in the input state. (3) Pull-down Current Tests (I PD ) This test measures the current which ﬂows when an High level voltage is applied to an input buffer having a pull-down resistance. In order to perform this test there must be an event in the test pattern which causes the input terminal to be measured to have an High level input. Bi-directional terminals must have High level inputs in the input state. (4) Off State Leakage Current (I OZH , IOZL ) This measures the leakage current which ﬂows when the output is a high-impedance state in output buffers which have open drains or which are 3-state output buffers. The actual measurement is the measurement of the currents when a V DD level volt- age is applied, and when a VSS level voltage is applied to the terminal being mea- sured when the terminal is in a high-impedance state. Because of this, the terminal being measured must enter into a high impedance state in the test pattern.

8.5 Notes Regarding the Use of Oscillation Circuits

An example of an oscillation circuit (oscillator, interval oscillator) is shown below. Figure 8.2 Example of Oscillator Circuits Generally when oscillator circuits are used, the driving power of the oscillator inverter is small and the output wave form of the oscillator circuit is inﬂuenced by the load of the measurement environment. Thus the oscillator circuit is unable to transmit precise wave forms to the next- stage gates. LIN LOT or LOT2 Gate side signal Drain side signal Clock signal Oscillation cell LIN LOT or LOT2 Enable signal Drain side signal Clock signal Oscillation cell Gate side signal IN1 IN1

Chapter 8: Test Pattern Generation GATE ARRAY S1L30000 SERIES EPSON 89 DESIGN GUIDE Because of this, in order to reproduce the conditions of the simulation in the tests, a procedure known as “reverse drive” (i.e. a procedure wherein a signal having the same wave form as the output from the drain is input to the drain terminal) is used. When the oscillator inverter is structured as an inverter, it is possible to generate a reverse drive signal if the signal input from the drain is simply a reverse-phase input of the signal applied to the gate; however, in the case of NAND gate structures (known as interval oscillators or gated-OSC), then decisions cannot be made simply based on the gate signal alone, but rather the reverse drive wave form must be determined by looking at the expected. values of the drain terminal. In this method, if the input wave form is the NRZ wave form and the strobe is at the end of the test period, then the input wave form is put to the drain terminal expected value directly and a reverse drive wave form can be generated. However, in the case of the RZ wave form, then the expected value of the drain terminal is ﬁxed to either an High or an Low whether or oscillator is in a oscillating state or an oscillation stop state, so it is not possible to determine a reverse drive wave form by examining the expected state of the drain terminal. Because of this, please keep the following cautions and notes in mind when a circuit having a interval oscillator is used: (1) An RZ wave form cannot be used as the input signal. (2) Do not cause transitions in the clock signal by transitions in the enable signal.

8.6 Regarding AC Testing

AC testing measures the time it takes for a signal to propagate to the output terminal when there has been a transition at the input terminal during a single event. The AC testing can be performed on a measurement path selected by the customer.

8.6.1 Constraints Regarding Measurement Events

Because this test is done using a testing method known as the “normal binary search method,” the terminal being measured (i.e. the output terminal wherein there is a transition) must have only a single transition point within a measurement event. (Measurements cannot be performed on terminals having an RZ wave form output, nor can they be performed in situations where a hazard is output during the measurement event.) Also, the state transitions of the signal being measure must be either High to Low or Low to High. (Transitions involving a high-impedance state cannot be measured.) Other cautions and notes include the necessity for selecting events so that there are no signal contentions between the bi-directional terminals and the LSI tester, and that there are no situations where many output terminals have simultaneous transitions at the measurement event. This is because the LSI power source is overwhelmed when there are simultaneous transitions or signal contentions, affecting the output wave form of the terminals being measured and making it impossible to get an accurate measurement.

8.6.2 Constraints on the Measurement Locations for AC Testing

Please use only 4 or less measurement locations in the AC testing.

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8.6.3 Constraints Regarding the Path Delay Which is Tested

The longer the delay in the AC measurement, the more accurate the measurement. The measurement path delay time should be recorded using maximum delay simulation conditions targeting a path delay value of 30 nsec or more, and less than the strobe point.

8.6.4 Other Constraints

(1) Do not designate a path from the oscillator circuit. (2) Designate a path which does not pass through a circuit having an internal 3-state unit (i.e. the internal bus). (3) Do not designate a path passing through other bi-directional cells between the input cell and the output cell of the measurement path. (4) When there are two or more voltage ranges used, reconcile these to a single AC test measurement voltages.

8.7 Test Pattern Constraints for Bi-directional Terminals

By the constraints of testing, the bi-directional terminals cannot switch between input mode and output mode more than once within a single event. Because of this, the test pattern generated should not use an RZ wave form for controlling the bi-directional cell input/output mode switching. Also, an RZ wave form cannot be used as an input to the bi-directional terminal.

Chapter 9: Estimating the Power Consumption GATE ARRAY S1L30000 SERIES EPSON 91 DESIGN GUIDE Chapter 9 Estimating the Power Consumption CMOS LSIs consume very little current when they are not operating. However, when they are operating, the power they consume depends on the operating frequency. When the power consumed is large, then the temperature of the LSI chip increases, and the quality of the LSI can be negatively affected if the temperature of the chip gets too high. Because of this, it is necessary to calculate the power consumption and to check whether or not the power consumption is within allowable tolerances.

9.1 Calculating the Power Consumption

The power consumption of a CMOS circuit is generally dependent on the operating frequency, the capacitance, and the power supply voltage. (This excludes those special situations where there is a normal current through RAM/ROM, etc.) Here the CMOS gate array power consumption can be calculated easily if the operating frequencies and load captaincies of the various cells used within the circuit are known. However, because it is difﬁcult to calculate the load captaincies for each internal cell, use the rough calculations described below. After the power consumption for the input cells, the output cells and the internal cells are calculated, and these values are summed to produce the total power consumption. (1) The Input Cell Power Consumption (P The input cell power consumption is the sum of the products of the signal frequencies (MHz) input into each cell, and the input buffer power coefﬁcient Kpi (µW/MHz) for each cell Kpi: Input Buffer Power Coefﬁcient (Reference Table 9.1 below) fi: The operating frequency of the ith input cell (MHz) Table 9.1 Kpi of input cells in the S1L30000 Series. VDD (Typ.) Kpi

5.0 V 25 µW/MHz

3.3 V 9.7 µW/MHz 3.0 V 7.7 µW/MHz Pi = Σ i=1 K (Kpi X fi) (W)

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(2) Output Cell Power Consumption (Po) The output cell power consumption differs depending on whether the load is a direct cur- rent load (such as resistive loads, TTL device connections, etc.) or whether the loads are alternating current loads (such as capacitance loads, CMOS device connections, etc.). In the case of alternating current loads, the output cell power consumption is calculated from the load capacitance C L as follows:

Alternating current power consumption PAC = f x CL x (VDD )2 (W) f: Output cell operating frequency (Hz) C L: Load capacitance (F) VDD : Power supply voltage (V) In the case of the direct current load, the power consumed in the direct current load is added to the power consumed in the alternating current load.
Direct current power consumption PDC = PDCH + PDCL Where, PDCH = |IOH | x (VDD - VOH ) (W) PDCL = IOL x VOL (W) The ratio of PDCH and PDCL is determined by the output signal duty cycle. Figure 9.1 Example of the Duty Cycle Duty H = (T1 + T2) / T Duty L = (T - T1 - T2) / T Because of this, PDC = PDCH + PDCL T T1 T2 = Σ i=1 K {(VDD -VOHi) x IOHi x Duty H} + Σ {VOLi x IOLi x Duty L} K i=1

Chapter 9: Estimating the Power Consumption GATE ARRAY S1L30000 SERIES EPSON 93 DESIGN GUIDE Consequently, the power consumption P0 of the output cell is calculated by: (3) Internal Cell Power Consumption (Pint) The internal cell power consumption depends on the type of device used, the cell use efﬁ- ciency, the operating frequency, and the ratio of cells operating at the operating frequency. It is calculated as follows: Nb: Total number of BCs in the device type used. U: Cell use ratio (Use 40% - 50% for DLM, use 70% - 88% for TLM) ﬁ: Operating frequency of the ith group (MHz) S pi: Percentage of cells operating at frequency ﬁ. (20% - 30% depending on the system) kpint: Internal cell power coefﬁcient (Please reference Table 9.2 below.) Because of this, the total power consumption Ptotal is calculated as follows: Ptotal = Pi + PO + Pint (4) Please see Chapter 11 regarding power consumption calculations for dual power sup- plies. Table 9.2 Kpint of Internal Cells in the S1L30000 Series VDD (Typ.) Kpi 5.0 V 3.4 µW/MHz 3.3 V 1.3 µW/MHz 3.0 V 1.1 µW/MHz Po = Σ (P AC + P DC ) = Σ {fi x CLi x (VDD ) 2} + Σ {(VDD - VOHi) x IOHi x Duty H} K i=1 K i=1 + Σ {VOLi x IOLi x Duty L} K i=1 Pint = Σ { (Nb X U) x fi x Spi x (kpint) } (W) K i=1

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9.2 Constraints on Power Consumption

The LSI chip heats up according to the power consumption within the LSI. The temperature of the LSI chip when it is mounted in a package can be calculated from the ambient temperature Ta, the thermal resistor(θ j-a) of the of the package, and the power consumption PD. The chip temperature (Tj) = Ta + (PD × θj-a) (°C) In normal use, the chip temperature (Tj) should be less than about 125°C. Please refer to table 9.3 for the thermal resistors of each of the various packages. Because the thermal resistors listed in Table 9.3 are thermal resistors in a situation where there is no air circulation, these values will change substantially depending on the mounting of the packages on the circuit board and depending on whether or not there is forced air cooling. Table 9.3 Thermal Resistors of Various Packages (Without Air Circulation) QFP5 QFP5 100 128 110( C/W) 110 ALLOY42 θj-a θj-a θj-a 0 m/sec 1 m/sec 2 m/sec 3 m/sec QFP8 128 65 ––– QFP8 QFP12 QFP13 QFP14 QFP15 208 100 230 170 110 115 TQFP14 TQFP14 TQFP15 100 100 100 100 110 QFP5 QFP5 QFP5 QFP8 QFP8 QFP10 100 128 160 256 304 85( C/W) Cu-L/F 0 m/sec 1 m/sec 2 m/sec 3 m/sec QFP12 QFP13 QFP14 QFP15 QFP20 QFP21 QFP21 QFP22 QFP22 QFP23 QFP23 TQFP12 TQFP13 TQFP15 TQFP24 100 184 176 216 208 256 184 240 128 144 175 130 110 165 140 105 120 H2QFP8 HQFP8 HQFP5 H2QFP23 H3QFP15 160 128 240 128 208 34 –– – PBGA PBGA PBGA 225 256 388 72( C/W) PBGA 0 m/sec 1 m/sec 2 m/sec 3 m/sec θj-a θj-a θj-a θj-a θj-a θj-a θj-a θj-a θj-a CFLGA424 CFLGA307 CFLGA239 CFLGA152 CFLGA104 75mm 50mm 30mm 75mm 50mm 30mm 75mm 50mm 30mm 75mm 50mm 30mm 75mm 50mm 30mm CFLGA (Board installation under th windless condition) 3.82 mm X 3.82 mm 5.73 mm X 5.73 mm Chip Size 44.0( C/W) 46.9 61.1 44.0 47.1 61.7 44.0 47.3 62.2 44.8 48.8 63.3 45.5 50.3 64.3 32.9 36.4 50.1 33.1 37.4 51.5 33.1 38.3 52.9 34.4 39.7 53.9 35.6 41.1 54.9 24.6 27.8 42.1 24.9 28.5 43.1 25.1 29.2 43.9 9.55 mm X 9.55 mm PINPKG Package type Customer's board size PINPKG PINPKG

Chapter 10: Pin Layout Considerations GATE ARRAY S1L30000 SERIES EPSON 95 DESIGN GUIDE Chapter 10 Pin Layout Considerations

10.1 Estimating the Number of Power Supply Terminals

It is necessary to estimate the number of power supply terminals required based on the power consumed by the LSI and on the number of output buffers. The output buffers use a large current when switching. This current increases with larger output buffer drive capabilities, and the current may exceed 100 mA in buffers with I OL = 24 mA. The number of power supply terminals required by the LSI can be estimated by its relationship with the current consumed as shown below. If the current consumed is IDD (mA), then the number of power supply terminals required (NIDD) to supply the consumption current IDD is as follows: N IDD ≥ IDD /50 (pairs) NOTE: Insert a minimum of 2 pairs of power terminals NIDD. IDD : Calculate IDD by dividing the power consumption calculated in Chapter 9 by the operating voltage. See Chapter 11 regarding the estimation of the number of power terminals for dual power supplies. NOTE: If the output buffer has a DC load connected with a constant current flowing through it, power-supply pins must be added. For details, contact Epson or its distributor.

10.2 Number of Simultaneous Operations and Adding Power

In the S1L30000 Series, the output drive capability is extremely large at a maximum of 24 mA, and thus the noise generated by the output buffers when they are operating is also extremely large. V SS power supplies need to be added, as shown in Table 10.1 to prevent malfunction from the noise when multiple output buffers operate at the same time. Moreover, VDD terminals need to be added in a ratio of 1 VDD per every two additional VSS terminals when using 24 mA drivers. In other cases, add VDD terminals at 1-to-1 ratio with additional VSS terminals. (See Table 10.2.)

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NOTE: When using power of 3.0 VDD or 3.3 VDD (Typ.), the number of output buffers should be about 60% of the number metioned above list. NOTE: When using power of 3.0 VDD or 3.3 VDD (Typ.), the number of output buffers should be about 60% of the number metioned above list. Table 10.1 Number of VSS Power Supplies to Add Depending on the Simultaneous Operation of Output Buffers (VDD =5 V) Output Drive Ability (IOL ) Number of Output Buffers Operating Simultaneously Number of Additional Power Supplies C L ≤ 50 pF C L ≤ 100 pF C L ≤ 200 pF 8 mA ≤80 1 2 ≤16 1 2 4 ≤24 1 3 6 ≤32 2 4 8 12 mA ≤81 2 3 ≤16 2 3 5 ≤24 2 5 7 ≤32 3 6 12 24 mA & PCI ≤81 2 4 ≤16 2 4 6 ≤24 3 6 8 ≤32 4 8 16 Table 10.2 Number of VDD Power Supplies to Add Depending on the Simultaneous Operation of Output Buffers (VDD =5 V) Output Drive Ability (IOH ) Number of Output Buffers Operating Simultaneously Number of Additional Power Supplies C L ≤ 50 pF C L ≤ 100 pF C L ≤ 200 pF 8 mA ≤80 1 1 ≤16 1 1 3 ≤24 1 2 4 ≤32 1 3 5 12 mA & PCI ≤81 2 3 ≤16 2 3 4 ≤24 2 4 5 ≤32 3 5 9

Chapter 10: Pin Layout Considerations GATE ARRAY S1L30000 SERIES EPSON 97 DESIGN GUIDE

10.3 Cautions and Notes Regarding the Layout of Terminals

Once the package to be used has been selected, then it is time to layout the pins. Please see the speciﬁc “Pin Layout Table” regarding the number of power supply pins and useable input/ output terminals in the various S1L30000 Series Packages. Once the pin layout has been established, submit to EPSON a pin assignment speciﬁcation which has been ﬁlled out with the pin layout. EPSON will layout the interconnections according to the speciﬁcation submitted by the customer, so we request that the customer carefully check this speciﬁcation. The pin layout is one of the critical speciﬁcations which controls the quality of the LSI. It is especially important in avoiding malfunctions due to noise. Moreover, problems with noise are difﬁcult to check for in simulations. So that there will be are no malfunctions with non- traceable causes in the customer’s LSI, we urge the customer to carefully study the guidelines detailed in this chapter before generating the pin layout.

10.3.1 Fixed Power Supply Pins

There are some pins which can only be used for power supply, depending on the combination of each device and package in this series. Because there are some pins which must be set to V DD pins and some pins which must be set to VSS pins please consult with EPSON when selecting a package.

10.3.2 Selecting I/O Cells

A wide variety of cells has been prepared by EPSON with differing input interface levels, with and without Schmitt trigger inputs, with and without pull-up/pull-down resistances, with different output drive capabilities, and with and without noise countermeasures. The following items should be referenced in selecting the optimal input/output cells. See Chapter 4 (“Notes and Cautions Regarding the Types of I/O Cells and Their Use”) regarding the methods of using the various I/O cells. (1) Selecting the Input Cell a) Is the required interface level a CMOS level or a TTL level? b) Is a Schmitt trigger input necessary? (Are hysteresis characteristics necessary?) c) Is it necessary to add pull-up/pull-down resistors? (2) Selecting the Output Cell a) How much output current must be driven? (I OL / IOH ) b) Are noise countermeasures necessary? c) Is a bus hold circuit necessary? (3) Selecting Bi-directional Cells Select the bi-directional cells by examining both sets of criteria for selecting the input cells and selecting the output cells.

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10.3.3 Cautions and Notes Regarding the Pin Layout

The pin layout inﬂuences the logical functioning and electrical characteristics of the LSI. Moreover, the pin layout may be constrained by the construction of the LSI, the structuring of the cells and the bulk, etc. Because of this, we will explain factors which must be researched when creating the pin layout, factors such as the power supply current, the input pin/output pin isolation, the critical signals, the pull-up/pull-down resistor inputs, simultaneous output, current drivers, etc. (1) Power Supply Current (I DD , ISS ) When it comes to the power supply current (IDD , ISS ) there are limitations on the tolerable levels for current from the power supply through the power supply pins when in an operat- ing state. When the tolerable levels are exceeded, the current density within the power supply interconnects within the LSI becomes too high, and the voltage generated by the current and the resistance within the interconnects increases or decreases. This may lead to malfunctioning and may have an impact on DC or AC characteristics. In order to avoid these types of problems, it is necessary to reduce the current density and the power supply interconnect line impedance. To do this, it is necessary to estimate the power consumption during the design of the gate array, and to make sure that there are enough power supply pins so that the current through each of the power supply pins does not exceed tolerances. Moreover, the layout should be such that the power supply pins are not concentrated all in one location, but rather are spread out. However, the ﬁnal power supply pin count may require the addition of power supply pins according to the above, and the power supply pin count must include additional power supply pins for the purpose of reducing noise, etc. See Section 10.2, “Number of Simulta- neous Operations and Adding Power Supplies,” regarding additional the number of addi- tional power supply pins. (2) Noise Resulting from the Operation of Output Cells The noise resulting from the operation of the output cells can be broadly divided into two categories. To reduce this noise as many power supplies should be added as possible as the countermeasure. a) Noise Generated in the Power Supply Lines When many outputs switch simultaneously, there will be problems with noise gener- ated in the power supply line. This can change the LSI input threshold levels, causing malfunctions. This power supply line noise is a result of the large current which is caused to ﬂow in the power supply lines when output cells switch simultaneously. The power supply noise exerts an especially large impact on the interface components. Because of this, the LSI equivalent circuits can be represented as shown in Figure 10.1. The output of this circuit diagram shows that when there is an High to Low tran- sition, the current from the output pin ﬂows through the components within the LSI, and ﬂows through the equivalent inductance L 2 of the LSI package, etc. At this time, the voltage in the VSS power supply line within the LSI is distorted by the equivalent inductance L2. This voltage distortion in the VSS power supply line is the noise that is generated within the power supply line. The noise which is generated within the power supply lines is primarily a result of the equivalent inductance L2, so a large amount of noise is generated when power supply currents change rapidly.

Chapter 10: Pin Layout Considerations GATE ARRAY S1L30000 SERIES EPSON 99 DESIGN GUIDE Figure 10.1 An LSI Equivalent Circuit b) The equivalent inductance in the output pins causes noises known as “overshoot,” “undershoot” and “ringing.” This equivalent inductance is marked by L3 in Figure 10.1. Because inductance has the property of storing energy, this overshoot, undershoot or ringing is the result of the output becoming either low or high. When there is a transi- tion, the overshoot and undershoot is proportional to the size of the current to the rate of change of the current. The most effective way to reduce overshoot and undershoot is to use output cells with relatively small drive current, and there is a tendency for the overshoot and under- shoot to be reduced when there is a relatively large load capacitance. Because of this, there is a need for caution when using cells with especially large current driving capa- bilities. (3) Isolating Input Pins and Output Pins Separating the input pin group from the output pin group in the pin layout is an important technique for reducing the impact of noise. Because input pins and bi-directional pins in the input state are especially susceptible to noise, one should avoid mixing these pins with output pins whenever possible, and the input pin group, the output pin group, and the bi-directional pin group should be separated from each other by the power supply pins (V DD , VSS ). VDD Input pin VDD (internal) VSS (internal) Output pin

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Figure 10.2 Example of Separating Input Pins and Output Pins (4) Critical Signals The following cautions and notes should be kept in mind when laying out the pins for criti- cal signals such as clock input pins and high-speed output pins. a) Pins for which it is necessary to reduce the noise, such as clock and reset pins, should be placed near the power supply pins and far from the output pins. (See Figure 10.3) b) Oscillator circuit pins should be placed near one another, sandwiched between power supply pins (VDD , VSS ). Moreover, they should not be placed near output pins. (See Figure 10.4) c) High-speed input and output pins should be placed near the center of the edge of the chip (of the package). (See Figure 10.3) d) When there is little margin in the customer speciﬁcations for delays between the input pins and the output pins, these input and output pins should be placed near to one another. (See Figure 10.3) Figure 10.3 Example 1 of a Layout for Critical Signals VDD VSS VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS Output pins Output pins Input pins Bid pins RST CLK VSS VSS High speed input Through input Through output High speed output

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(6) Simultaneous Switching of Outputs Noise is generated when multiple output pins change at the same time, which may cause malfunctioning of the LSI. In order to reduce the risk of malfunction due to noise when multiple output pins change at the same time, a power supply pin should be added to the group of output pins which are changing simultaneously. See section 10.2 regarding the number of power supply pins which must be added and the method for laying out these power supply pins. In order to reduce this noise, one may alternatively add a cell to delay the previous stage of these output cell groups, thereby reducing the amount of simultane- ous changes of the output cells, thereby reducing noise as well. (See Figure 10.8) Figure 10.7 Example of Adding Power Supply Pins Figure 10.8 Example of Adding Delay Cells (7) Large Current Drivers When outputs are used which drive large currents (IOL = 12 mA, 24 mA), pin layout should be performed following the constraints below: a) Constraints on Strengthening the Power Supplies Power supply pins should be located near the large-current driver pins to minimize switching niose. (See Figure 10.9.) b) Low-Noise Pre-drivers Low-noise output cells and low-noise pre-drivers have been prepared in order to reduce the noise generated by the operation of output cells with large current drivers. See Chapter 4 regarding recommended combinations of pre-drivers and output cells. VDD VSS VDD VSS VDD VSS VSS VSS Simultaneously changing output pins. A TD TS P N PDV1T UO4 A TD TS P N PDV1T DL1 UO4 OUT1 OUT2

Chapter 10: Pin Layout Considerations GATE ARRAY S1L30000 SERIES EPSON 103 DESIGN GUIDE Figure 10.9 Example of Strengthening Power Supplies (8) Other Cautions and Notes The relationship between the package pins and the LSI pads is already established by the combination of each series device type and package type. Because of this, there may be constraints on the use of pins because of the package, and constraints on the pin layout due to the I/O cell types. Notes and cautions regarding these restraints are described below; these should be kept in mind when determining the pin layouts. a) NC Pins (non-connection) A pin might be unavailable for use when the number of pads on the LSI is less than the number of pins on the package, or when the LSI pad cannot be connected to one of the package pins. Mark these with a double asterisk (**) on the pin layout table. b) Tab Hanger Pins Tab hanger pins are package pins which are connected directly the LSI substrate. For reasons discussed above, these pins are at a V SS (GND) level even if they are not externally connected to the power supply. Normally these pins should be left open on the circuit board. These pins should be marked with double pound signs (“##”) on the pin layout table form. VSS VSS High drive output

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10.3.4 Examples of Recommended Pin Connections

The pin layout is a critical point in ensuring that the LSI operates correctly. Determine pin layouts after referencing the example pin layout (Figure 10.10) which takes into consideration the entire content explained in this chapter. Figure 10.10 Example of Recommended Pin Layout Input pins are located on the upper and left hand edges of the package, output pins which change simultaneously are located on the right hand side of the package, and bi-directional pins and other output pins are located on the bottom edge of the package. VDD VSS Input pins Output pins Input pins PLUP INP9 INP10 INP11 INP14 INP15 INP16 INP17 INP18 INP19 V DD INP12 INP13 CLK VDD VSS SOUT0 SOUT1 SOUT2 SOUT5 SOUT6 SOUT7 SOUT8 SOUT9 SOUT3 SOUT4 V SS VSS VSS VSS INP8 VSS VSS VDD VSS VSS INP7 INP6 INP5 INP4 INP3 INP2 INP1 INP0 OSCIN OSCOUT VDD VDD VSS VSS BID0 HOUT VSS BID1 BID2 BID3 BID4 V SS VSS OUT0 OUT1 MOSC Output pinsBid pins

Chapter 10: Pin Layout Considerations GATE ARRAY S1L30000 SERIES EPSON 105 DESIGN GUIDE Table 10.3 Pin Layout Example Location Pin Name Explanation of Pin Name Detailed Explanation of the Position of Each Pin Upper Edge PULP CLK Input pins with pull-ups Input pins for the clock Located where the impact of noise is the least. Located near the center of the package, and near power supply pins. Left Edge OSCIN, OSCOUT INP0 to19 Oscillator pins Input pins Located near the center of the package, and near power supply pins. Located with power supply pins, away from other pins. Right-hand Edge SOUT0 to 9 Simultaneously changing output pins Located near power supply pins and separated from other pins with additional power supply pins. Bottom Edge BID0 to 4 MOSC HOUT OUT01 Bi-directional pins Oscillator monitor output pins High-drive output pins Output pins Located near power supply pins and separated from other pins. Located separated from oscillator pins and near power supply pins. Located near power supply pins. Located near power supply pins and separated from other pins. All Edges V DD VSS VDD power supply pins VSS (GND) power supply pins

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Chapter 11 Dual Power Supplies Guidelines By using dual power supplies (5.0 V/3.0 V systems) the S1L30000 Series is able to interface with either 5.0 V system signals or 3.0 V system signals for each I/O cell. The internal cell region operates on only the single 3.0 V system power supply.

11.1 The Method of Adapting to Dual Power Supplies

The S1L30000 Series is of capable of interfacing with signals of a voltage which is different than the internal operating voltage. There are two methods by which to interface with systems of different voltages.

The Single Power Supply Method With a single power supply, it is possible to input signals with operating voltages that are higher than the supply voltage, by using an Nch open-drain buffer. However, it is not possible to output signals with operating voltages that are higher than the supply volt- age, unless an Nch open-drain buffer and an external pull-up resistor are combined.
The Dual Power Supply Method It is possible to input a signal of a higher voltage than the internal operating voltage through the use of special dual power supply compatible input cells. Also, the use of a combination of pre-drivers with level shifters and dual power supply output cells makes it possible to output signals of voltages higher than internal operating voltage.

11.2 Power Supplies for Dual Power Operation

When two power supplies are applied, use the unique power supply identiﬁers, HVDD and LVDD . HVDD is used to supply power for HVDD ’ I/O cells and level shifter cells. LVDD is used to supply power for LVDD ’ I/O cells and all internal cells. The power supply voltages must always fulﬁll the following inequality: HV DD ≥ LVDD Caution is necessary because operation cannot be assured if HVDD is less than LVDD . The following two conditions are recommended operating conditions.

H VDD = 5.0 V, LVDD = 3.3 V
H VDD = 5.0 V, LVDD = 3.0 V Below is an example of use in a situation where a dual power supply is supplied to the S1L30000 Series.

Chapter 11: Dual Power Supplies Guidelines GATE ARRAY S1L30000 SERIES EPSON 107 DESIGN GUIDE Figure 11.1 Example of Use Where a Dual Power Supply is Supplied to the S1L30000 Series

11.3 I/O Buffers Compatible with Dual Power Supplies

When a dual power supply is used, dual power supply-compatibility I/O cells should be used as well. Care must be taken so that I/O cells for single power supply are not used. Because of this, I/O cells for single power supplies and I/O cells for dual power supplies cannot be mixed. However, cells for testing (ITST1) are cells for both dual power supplies and signal power supplies.

11.3.1 I/O Buffers for the LVDD System

LVDD system I/O cells include input cells which input 3.0 V (or 3.3 V) signals, output cells which output 3.0 V (or 3.3 V) amplitude signals, and bi-directional cells which can input 3.0 V (or 3.3 V) signals and which can output 3.0 V (or 3.3 V) amplitude signals. The output cells and bi-directional cells are combined with pre-drivers just as they are when using single power supplies. When HV DD system signals are input into LVDD system input cells, a very large current ﬂows through the guard diode within the LVDD system cell, damaging the quality of the cell; thus voltages of more than the LVDD voltage should not be applied.

11.3.1.1 Input Buffers for the LVDD System

The input buffer is comprised of only input cells. The LVDD system input signals include those shown in Table 11.1. S1L30000 series Core voltage = 3.0 V 5.0 V 3.0 V IC VDD =5.0 V IC V DD =3.0 V

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NOTE: When ∗ value is 1 or 2, the pull-up/pull-down resistance values correspond to 1:90 kΩ , 2:180 kΩ respectively. NOTE: When ∗ value is 1 or 2, the pull-up/pull-down resistance values correspond to 1:90 kΩ , 2:180 kΩ respectively.

11.3.1.2 Output Buffers for the LVDD System

Use a combination of internal cell pre-drivers (PDV1T, PDV1AT, PDV2T, PDV2AT, etc.) and output cells (LU01 - LU04, etc.) when structuring the LVDD system output buffers. See Table 11.3, below, regarding the combinations. Use only PDV1AAT or PDV2AAT for PCI speciﬁcation output buffer pre-drivers. Table 11.1 Table of LVDD System Input Cells Cell Name Input Level Function Pull-up/Pull-down Resistors LIBC LIBCP∗ LIBCD ∗ CMOS CMOS CMOS Buffer Buffer Buffer None Pull-up Resistor (90 kΩ , 180 kΩ ) Pull-down Resistor (90 kΩ , 180 kΩ ) LIBH LIBHP LIBHD ∗ CMOS Schmitt CMOS Schmitt CMOS Schmitt Buffer Buffer Buffer None Pull-up Resistor (90 kΩ , 180 kΩ ) Pull-down Resistor (90 kΩ , 180 kΩ ) LIBPB LIBPBP LIBPBD ∗ PCI PCI PCI Buffer Buffer Buffer None Pull-up Resistor (90 kΩ , 180 kΩ ) Pull-down Resistor (90 kΩ , 180 kΩ ) Table 11.2 Table of LVDD Input Level Shifters Cell Name Input Level Function Pull-up/Pull-down Resistors LIDC LIDCD ∗ CMOS CMOS Buffer Buffer None Pull-down Resistor (90 kΩ , 180 kΩ ) LIDH LIDHD ∗ CMOS Schmitt CMOS Schmitt Buffer Buffer None Pull-down Resistor (90 kΩ , 180 kΩ )

Chapter 11: Dual Power Supplies Guidelines GATE ARRAY S1L30000 SERIES EPSON 109 DESIGN GUIDE Table 11.3 Combinations of Pre-drivers and LVDD System Output Cells Function IOL * / IOH Cell Structure * Normal output for low noise 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA LUOS + PDV1T LUOM + PDV1T LUO1 + PDV1T LUO2 + PDV1T LUO3 + PDV1T LUO4 + PDV1T Normal output for high speed 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA PCI LUOS + PDV1AT LUOM + PDV1AT LUO1 + PDV1AT LUO2 + PDV1AT LUO3 + PDV1AAT LUO4 + PDV1AAT LUOPB + PDV1AAT Normal output with low slew rate control 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA LUOS + PDV1BT LUOM + PDV1BT LUOH + PDV1BT LUO2 + PDV1BT LUO3 + PDV1BT LUO4 + PDV1BT Normal output with slew rate control 6 mA / -6 mA 12 mA / -6 mA LUO3L + PDV3T LUO4L + PDV3T 3-state output for low noise 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA LUOS + PDV2T LUOM + PDV2T LUO1 + PDV2T LUO2 + PDV2T LUO3 + PDV2T LUO4 + PDV2T 3-state output for high speed 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA PCI LUOS + PDV2AT LUOM + PDV2AT LUO1 + PDV2AT LUO2 + PDV2AT LUO3 + PDV2AAT LUO4 + PDV2AAT LUOPB + PDV2AAT 3-state output with low slew rate control 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA LUOS + PDV2BT LUOM + PDV2BT LUO1 + PDV2BT LUO2 + PDV2BT LUO3 + PDV2BT LUO4 + PDV2BT 3-state output with slew rate control 6 mA / -6 mA 12 mA / -6 mA LUO3L + PDV4T LUO4L + PDV4T 3-state output for low noise (Bus hold circuit) 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA LUOSH + PDV2T LUOMH + PDV2T LUO1H + PDV2T LUO2H + PDV2T LUO3H + PDV2T LUO4H + PDV2T

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NOTE: * V OL = 0.3 V (LVDD = 3.3 V, 3.0 V) VOH = LVDD - 0.3 V (LVDD = 3.3 V, 3.0 V) * Along with the structuring method shown in Table 11.3, the pre-driver structure may include structures which have no test terminals. Those customers wishing to use such structures should direct their inquiries to EPSON. NOTE: * V OL = 0.3 V (LVDD = 3.3 V, 3.0 V) ** Along with the structuring method shown in Table 11.4, the pre-driver structure may include structures which have no test terminals. Those customers wishing to use such structures should direct their inquiries to EPSON.

11.3.1.3 Bi-directional Buffers for the LVDD System

When a dual power supply is used, the bi-directional buffer is structured from a combination of pre-driver with an enable terminal and an LVDD system bi-directional cell. See Table 11.5 regarding these combinations. Use only the PDV2AAT pre-driver for the PCI speciﬁcation bi-directional buffer. 3-state output for high speed (Bus hold circuit) 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA LUOSH + PDV2AT LUOMH + PDV2AT LUO1H + PDV2AT LUO2H + PDV2AT LUO3H + PDV2AAT LUO4H + PDV2AAT 3-state output with low slew rate control (Bus hold circuit) 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA LUOSH + PDV2BT LUOMH + PDV2BT LUO1H + PDV2BT LUO2H + PDV2BT LUO3H + PDV2BT LUO4H + PDV2BT 3-state output with slew rate control (Bus hold circuit) 6 mA / -6 mA 12 mA / -6 mA LUO3HL + PDV4T LUO4HL + PDV4T Table 11.4 Combinations of Pre-drivers and LVDD System ODN System Cells Function IOL * / IOH Cell Structure * Normal output for low noise 0.05 mA 0.5 mA 2 mA 4 mA 6 mA 12 mA LODNS + PDV1T LODNM + PDV1T LODN1 + PDV1T LODN2 + PDV1T LODN3 + PDV1T LODN4 + PDV1T Normal output for high speed 0.05 mA 0.5 mA 2 mA 4 mA 6 mA 12 mA LODNS + PDV1AT LODNM + PDV1AT LODN1 + PDV1AT LODN2 + PDV1AT LODN3 + PDV1AAT LODN4 + PDV1AAT Normal output with low slew rate control 6 mA 12 mA LODN3L + PDV3T LODN4L + PDV3T Table 11.3 Combinations of Pre-drivers and LVDD System Output Cells (Continued) Function IOL * / IOH Cell Structure *

Chapter 11: Dual Power Supplies Guidelines GATE ARRAY S1L30000 SERIES EPSON 111 DESIGN GUIDE Table 11.5 Combinations of Pre-drivers and LVDD System Bi-directional Cells Input Level Function IOL * / IOH Cell Structure* CMOS Bi-directional for low noise output 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA LUCS + PDV2T LUCM + PDV2T LUC1 + PDV2T LUC2 + PDV2T LUC3 + PDV2T LUC4 + PDV2T CMOS Bi-directional for high speed output 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA LUCS + PDV2AT LUCM + PDV2AT LUC1 + PDV2AT LUC2 + PDV2AT LUC3 + PDV2AAT LUC4 + PDV2AAT CMOS Bi-directional with low slew rate control output 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA LUCS + PDV2BT LUCM + PDV2BT LUC1 + PDV2BT LUC2 + PDV2BT LUC3 + PDV2BT LUC4 + PDV2BT CMOS Bi-directional with slew rate control output 6 mA / -6 mA 12 mA / -6 mA LUC3L + PDV4T LUC4L + PDV4T PCI Bi-directional for high speed output PCI LUBPB + PDV2AAT CMOS Schmitt Bi-directional for low noise output 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA LUHS + PDV2T LUHM + PDV2T LUH1 + PDV2T LUH2 + PDV2T LUH3 + PDV2T LUH4 + PDV2T CMOS Schmitt Bi-directional for high speed output 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA LUHS + PDV2AT LUHM + PDV2AT LUH1 + PDV2AT LUH2 + PDV2AT LUH3 + PDV2AAT LUH4 + PDV2AAT CMOS Schmitt Bi-directional with low slew rate control output 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA LUHS + PDV2BT LUHM + PDV2BT LUH1 + PDV2BT LUH2 + PDV2BT LUH3 + PDV2BT LUH4 + PDV2BT CMOS Schmitt Bi-directional with slew rate control output 6 mA / -6 mA 12 mA / -6 mA LUH3L + PDV4T LUH4L + PDV4T CMOS Bi-directional for low noise output (Bus hold circuit) 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA LUCSH + PDV2T LUCMH + PDV2T LUC1H + PDV2T LUC2H + PDV2T LUC3H + PDV2T LUC4H + PDV2T CMOS Bi-directional for high speed output (Bus hold circuit) 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA LUCSH + PDV2AT LUCMH + PDV2AT LUC1H + PDV2AT LUC2H + PDV2AT LUC3H + PDV2AAT LUC4H + PDV2AAT

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NOTE: * VOL = 0.3 V (LVDD = 3.3 V, 3.0 V) VOH = LVDD - 0.3 V (LVDD = 3.3 V, 3.0 V) * Along with the structuring method shown in Table 11.5, the bi-directional buffer may be structured with pull-up or pull-down resistors, or the pre-driver may be structured without test terminals. Those customers wishing to use a structure without test terminals should direct their inquiries to EPSON. CMOS Bi-directional with low slew rate control output (Bus hold circuit) 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA LUCSH + PDV2BT LUCMH + PDV2BT LUC1H + PDV2BT LUC2H + PDV2BT LUC3H + PDV2BT LUC4H + PDV2BT CMOS Bi-directional with slew rate control output (Bus hold circuit) 6 mA / -6 mA 12 mA / -6 mA LUC3HL + PDV4T LUC4HL + PDV4T CMOS Schmitt Bi-directional for high speed output (Bus hold circuit) 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA LUHSH + PDV2T LUHMH + PDV2T LUH1H + PDV2T LUH2H + PDV2T LUH3H + PDV2T LUH4H + PDV2T CMOS Schmitt Bi-directional for high speed output (Bus hold circuit) 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA LUHSH + PDV2AT LUHMH + PDV2AT LUH1H + PDV2AT LUH2H + PDV2AT LUH3H + PDV2AAT LUH4H + PDV2AAT CMOS Schmitt Bi-directional with low slew rate control output (Bus hold circuit) 0.05 mA / -0.05 mA 0.5 mA / -0.5 mA 2 mA / -2 mA 4 mA / -4 mA 6 mA / -6 mA 12 mA / -6 mA LUHSH + PDV2BT LUHMH + PDV2BT LUH1H + PDV2BT LUH2H + PDV2BT LUH3H + PDV2BT LUH4H + PDV2BT CMOS Schmitt Bi-directional with slew rate control output (Bus hold circuit) 6 mA / -6 mA 12 mA / -6 mA LUH3HL + PDV4T LUH4HL + PDV4T Table 11.5 Combinations of Pre-drivers and LVDD System Bi-directional Cells (Continued) Input Level Function IOL * / IOH Cell Structure*

Chapter 11: Dual Power Supplies Guidelines GATE ARRAY S1L30000 SERIES EPSON 113 DESIGN GUIDE NOTE: * V OL = 0.3 V (LVDD = 3.3 V, 3.0 V) ** Along with the structuring method shown in Table 11.6, the bi-directional buffer may be structured with pull-up or pull-down resistors, or the pre-driver may be structured without test terminals. Those customers wishing to use a structure without test terminals should direct their inquiries to EPSON.

11.3.2 I/O Buffers for the HVDD System

The HVDD system I/O cells include input cells which input 5.0 V signals, output cells which output 5.0 V amplitude signals, and bi-directional cells which input 5.0 V signals and output 5.0 V amplitude signals. Output cells and bi-directional cells are used in combination with pre- drivers with level shifters. Table 11.6 Combinations of Pre-drivers and LVDD System BDC and BDH System Cells Input Level Function IOL * Cell Structure*** CMOS Bi-directional for low noise out- put 0.05 mA 0.5 mA 2 mA 4 mA 6 mA 12 mA LBDCS + PDV2T LBDCM + PDV2T LBDC1 + PDV2T LBDC2 + PDV2T LBDC3 + PDV2T LBDC4 + PDV2T CMOS Bi-directional for high speed output 0.05 mA 0.5 mA 2 mA 4 mA 6 mA 12 mA LBDCS + PDV2AT LBDCM + PDV2AT LBDC1 + PDV2AT LBDC2 + PDV2AT LBDC3 + PDV2AAT LBDC4 + PDV2AAT CMOS Bi-directional with low slew rate control output 0.05 mA 0.5 mA 2 mA 4 mA 6 mA 12 mA LBDCS + PDV2BT LBDCM + PDV2BT LBDC1 + PDV2BT LBDC2 + PDV2BT LBDC3 + PDV2BT LBDC4 + PDV2BT CMOS Bi-directional with slew rate control output 6 mA 12 mA LBDC3L + PDV4T LBDC4L + PDV4T CMOS Schmitt Bi-directional for low noise out- put 0.05 mA 0.5 mA 2 mA 4 mA 6 mA 12 mA LBDHS + PDV2T LBDHM + PDV2T LBDH1 + PDV2T LBDH2 + PDV2T LBDH3 + PDV2T LBDH4 + PDV2T CMOS Schmitt Bi-directional for high speed output 0.05 mA 0.5 mA 2 mA 4 mA 6 mA 12 mA LBDHS + PDV2AT LBDHM + PDV2AT LBDH1 + PDV2AT LBDH2 + PDV2AT LBDH3 + PDV2AAT LBDH4 + PDV2AAT CMOS Schmitt Bi-directional with low slew rate control output 0.05 mA 0.5 mA 2 mA 4 mA 6 mA 12 mA LBDHS + PDV2BT LBDHM + PDV2BT LBDH1 + PDV2BT LBDH2 + PDV2BT LBDH3 + PDV2BT LBDH4 + PDV2BT CMOS Schmitt Bi-directional with slew rate control output 6 mA 12 mA LBDH3L + PDV4T LBDH4L + PDV4T

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11.3.2.1 Input Buffers for the HVDD System

Inputs are structured from input cells alone. The HVDD input cells are comprised of the HVDD system circuits for the initial-stage input, and the next-stage is comprised of LVDD system circuits. The HVDD system signals are converted to LVDD system signals after which these signals are supplied to the MSI cells (internal cell region). The HVDD system input cells are as shown in Table 11.7. NOTE: When ∗ value is 1 or 2, the pull-up/pull-down resistance values correspond to 1:50 kΩ , 2:100 kΩ respectively.

11.3.2.2 Output Buffers for the HVDD System

The HVDD system output buffer is structured from a combination of pre-drivers with level shifters comprised of internal cells (such as LSP1T, LSP1AT, LSP1BT, LSP2T, LSP2AT, LSP2BT, etc.) and output cells (HU01 to HU04, etc.). See Table 11.8 regarding these combinations. PCI speciﬁcation output buffers should use only the LSP1AAT and LSP2AAT pre-drivers. Table 11.7 Table of HVDD System Input Cells Cell Name Input Level Function Pull-up/Pull-down Resistors HIBT HIBTP ∗ HIBTD ∗ TTL TTL TTL Buffer Buffer Buffer None Pull-up Resistor (50 kΩ , 100 kΩ ) Pull-down Resistor (50 kΩ , 100 kΩ ) HIBC HIBCP HIBCD ∗ CMOS CMOS CMOS Buffer Buffer Buffer None Pull-up Resistor (50 kΩ , 100 kΩ ) Pull-down Resistor (50 kΩ , 100 kΩ ) HIBS HIBSP HIBSD ∗ TTL Schmitt TTL Schmitt TTL Schmitt Buffer Buffer Buffer None Pull-up Resistor (50 kΩ , 100 kΩ ) Pull-down Resistor (50 kΩ , 100 kΩ ) HIBH HIBHP HIBHD ∗ CMOS Schmitt CMOS Schmitt CMOS Schmitt Buffer Buffer Buffer None Pull-up Resistor (50 kΩ , 100 kΩ ) Pull-down Resistor (50 kΩ , 100 kΩ ) HIBPA HIBPAP HIBPAD ∗ PCI PCI PCI Buffer Buffer Buffer None Pull-up Resistor (50 kΩ , 100 kΩ ) Pull-down Resistor (50 kΩ , 100 kΩ )

Chapter 11: Dual Power Supplies Guidelines GATE ARRAY S1L30000 SERIES EPSON 115 DESIGN GUIDE Table 11.8 Combinations of Pre-drivers with Level Shifters and HV DD System Output Cells Function IOL * / IOH Cell Structure * Normal output for low noise 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA HUOS + LSP1T HUOM + LSP1T HUO1 + LSP1T HUO2 + LSP1T HUO3 + LSP1T HUO4 + LSP1T Normal output for high speed 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA PCI HUOS + LSP1AT HUOM + LSP1AT HUO1 + LSP1AT HUO2 + LSP1AT HUO3 + LSP1AAT HUO4 + LSP1AAT HUOPA + LSP1AAT Normal output with low slew rate control 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA HUOS + LSP1BT HUOM + LSP1BT HUO1 + LSP1BT HUO2 + LSP1BT HUO3 + LSP1BT HUO4 + LSP1BT Normal output with slew rate control 12 mA / -12 mA 24 mA / -12 mA HUO3L + LSP3T HUO4L + LSP3T 3-state output for low noise 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA HUOS + LSP2T HUOM + LSP2T HUO1 + LSP2T HUO2 + LSP2T HUO3 + LSP2T HUO4 + LSP2T 3-state output for high speed 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA PCI HUOS + LSP2AT HUOM + LSP2AT HUO1 + LSP2AT HUO2 + LSP2AT HUO3 + LSP2AAT HUO4 + LSP2AAT HUOPA + LSP2AAT 3-state output with low slew rate control 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA HUOS + LSP2BT HUOM + LSP2BT HUO1 + LSP2BT HUO2 + LSP2BT HUO3 + LSP2BT HUO4 + LSP2BT 3-state output with slew rate control 12 mA / -12 mA 24 mA / -12 mA HUO3L + LSP4T HUO4L + LSP4T 3-state output for low noise (Bus hold circuit) 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA HUOSH + LSP2T HUOMH + LSP2T HUO1H + LSP2T HUO2H + LSP2T HUO3H + LSP2T HUO4H + LSP2T

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NOTE: * VOL = 0.4 V (HVDD = 5.0 V) VOH = HVDD - 0.4 V (HVDD = 5.0 V) * Along with the structuring method shown in Table 11.8, the pre-driver structure may include structures which have no test terminals. Those customers wishing to use such structures should direct their inquiries to EPSON.

11.3.2.3 Bi-directional Buffers for the HVDD System

Even when dual power supplies are used, the bi-directional buffers are structured from combinations of pre-drivers equipped with level shifters and enable terminals and from HVDD bi-directional cells. Only the LSP2AAT is to be used as the pre-driver for PCI speciﬁcation bi- directional buffers. 3-state output for high speed (Bus hold circuit) 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA HUOSH + LSP2AT HUOMH + LSP2AT HUO1H + LSP2AT HUO2H + LSP2AT HUO3H + LSP2AAT HUO4H + LSP2AAT 3-state output with low slew rate control (Bus hold circuit) 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA HUOSH + LSP2BT HUOMH + LSP2BT HUO1H + LSP2BT HUO2H + LSP2BT HUO3H + LSP2BT HUO4H + LSP2BT 3-state output with slew rate control (Bus hold circuit) 12 mA / -12 mA 24 mA / -12 mA HUO3HL + LSP4T HUO4HL + LSP4T Table 11.8 Combinations of Pre-drivers with Level Shifters and HV DD System Output Cells (Continued) Function IOL * / IOH Cell Structure *

Chapter 11: Dual Power Supplies Guidelines GATE ARRAY S1L30000 SERIES EPSON 117 DESIGN GUIDE Table 11.9 Combinations of Pre-drivers (With Level Shifters) and HV DD Bi-directional Cells Input Level Function IOL * / IOH Cell Structure* TTL Bi-directional for low noise output 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA HUTS + LSP2T HUTM + LSP2T HUT1 + LSP2T HUT2 + LSP2T HUT3 + LSP2T HUT4 + LSP2T TTL Bi-directional for high speed output 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA HUTS + LSP2AT HUTM + LSP2AT HUT1 + LSP2AT HUT2 + LSP2AT HUT3 + LSP2AAT HUT4 + LSP2AAT TTL Bi-directional with low slew rate control output 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA HUTS + LSP2BT HUTM + LSP2BT HUT1 + LSP2BT HUT2 + LSP2BT HUT3 + LSP2BT HUT4 + LSP2BT TTL Bi-directional with slew rate control output 12 mA / -12 mA 24 mA / -12 mA HUT3L + LSP4T HUT4L + LSP4T CMOS Bi-directional for low noise output 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA HUCS + LSP2T HUCM + LSP2T HUC1 + LSP2T HUC2 + LSP2T HUC3 + LSP2T HUC4 + LSP2T CMOS Bi-directional for high speed output 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA HUCS + LSP2AT HUCM + LSP2AT HUC1 + LSP2AT HUC2 + LSP2AT HUC3 + LSP2AAT HUC4 + LSP2AAT CMOS Bi-directional with low slew rate control output 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA HUCS + LSP2BT HUCM + LSP2BT HUC1 + LSP2BT HUC2 + LSP2BT HUC3 + LSP2BT HUC4 + LSP2BT CMOS Bi-directional with slew rate control output 12 mA / -12 mA 24 mA / -12 mA HUC3 + LSP4T HUC4 + LSP4T PCI Bi-directional for high speed output PCI HUBPA + LSP2AAT TTL Schmitt Bi-directional for low noise output 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA HUSS + LSP2T HUSM + LSP2T HUS1 + LSP2T HUS2 + LSP2T HUS3 + LSP2T HUS4 + LSP2T

Chapter 11: Dual Power Supplies Guidelines

118 EPSON GATE ARRAY S1L30000 SERIES

TTL Schmitt Bi-directional for high speed output 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA HUSS + LSP2AT HUSM + LSP2AT HUS1 + LSP2AT HUS2 + LSP2AT HUS3 + LSP2AAT HUS4 + LSP2AAT TTL Schmitt Bi-directional with low slew rate control output 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA HUSS + LSP2BT HUSM + LSP2BT HUS1 + LSP2BT HUS2 + LSP2BT HUS3 + LSP2BT HUS4 + LSP2BT TTL Schmitt Bi-directional with slew rate control output 12 mA / -12 mA 24 mA / -12 mA HUS3L + LSP4T HUS4L + LSP4T TTL Bi-directional for low noise output (Bus hold circuit) 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA HUTS + LSP2T HUTM + LSP2T HUT1 + LSP2T HUT2 + LSP2T HUT3 + LSP2T HUT4 + LSP2T TTL Bi-directional for high speed output (Bus hold circuit) 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA HUTSH + LSP2AT HUTMH + LSP2AT HUT1H + LSP2AT HUT2H + LSP2AT HUT3H + LSP2AAT HUT4H + LSP2AAT TTL Bi-directional with low slew rate control output (Bus hold circuit) 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA HUTSH + LSP2BT HUTMH + LSP2BT HUT1H + LSP2BT HUT2H + LSP2BT HUT3H + LSP2BT HUT4H + LSP2BT TTL Bi-directional with slew rate control output (Bus hold circuit) 12 mA / -12 mA 24 mA / -12 mA HUT3HL + LSP4T HUT4HL + LSP4T CMOS Bi-directional for low noise output (Bus hold circuit) 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA HUCSH + LSP2T HUCMH + LSP2T HUC1H + LSP2T HUC2H + LSP2T HUC3H + LSP2T HUC4H + LSP2T CMOS Bi-directional for high speed output (Bus hold circuit) 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA HUCSH + LSP2AT HUCMH + LSP2AT HUC1H + LSP2AT HUC2H + LSP2AT HUC3H + LSP2AAT HUC4H + LSP2AAT CMOS Bi-directional with low slew rate control output (Bus hold circuit) 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA HUCSH + LSP2BT HUCMH + LSP2BT HUC1H + LSP2BT HUC2H + LSP2BT HUC3H + LSP2BT HUC4H + LSP2BT Table 11.9 Combinations of Pre-drivers (With Level Shifters) and HV DD Bi-directional Cells (Continued) Input Level Function IOL * / IOH Cell Structure*

Chapter 11: Dual Power Supplies Guidelines GATE ARRAY S1L30000 SERIES EPSON 119 DESIGN GUIDE NOTE: * V OL = 0.4 V (HVDD = 5.0 V) VOH = HVDD - 0.4 V (HVDD = 5.0 V) * Along with the structuring method shown in Table 11.9, the bi-directional buffer structure may include structures which have no test terminals and the bi-directional cell structure may be one without pull-up or pull-down resistors. Those customers wishing to use a structure without test terminals should direct their inquiries to EPSON. CMOS Bi-directional with slew rate control output (Bus hold circuit) 12 mA / -12 mA 24 mA / -12 mA HUC3HL + LSP4T HUC4HL + LSP4T TTL Schmitt Bi-directional for low noise output (Bus hold circuit) 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA HUSSH + LSP2T HUSMH + LSP2T HUS1H + LSP2T HUS2H + LSP2T HUS3H + LSP2T HUS4H + LSP2T TTL Schmitt Bi-directional for high speed output (Bus hold circuit) 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA HUSSH + LSP2AT HUSMH + LSP2AT HUS1H + LSP2AT HUS2H + LSP2AT HUS3H + LSP2AAT HUS4H + LSP2AAT TTL Schmitt Bi-directional with low slew rate control output (Bus hold circuit) 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA HUSSH + LSP2BT HUSMH + LSP2BT HUS1H + LSP2BT HUS2H + LSP2BT HUS3H + LSP2BT HUS4H + LSP2BT TTL Schmitt Bi-directional with slew rate control output (Bus hold circuit) 12 mA / -12 mA 24 mA / -12 mA HUS3HL + LSP4T HUS4HL + LSP4T CMOS Schmitt Bi-directional for high speed output (Bus hold circuit) 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA HUHSH + LSP2T HUHMH + LSP2T HUH1H + LSP2T HUH2H + LSP2T HUH3H + LSP2T HUH4H + LSP2T CMOS Schmitt Bi-directional for high speed output (Bus hold circuit) 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA HUHSH + LSP2AT HUHMH + LSP2AT HUH1H + LSP2AT HUH2H + LSP2AT HUH3H + LSP2AAT HUH4H + LSP2AAT CMOS Schmitt Bi-directional with low slew rate control output (Bus hold circuit) 0.1 mA / -0.1 mA 1 mA / -1 mA 4 mA / -4 mA 8 mA / -8 mA 12 mA / -12 mA 24 mA / -12 mA HUHSH + LSP2BT HUHMH + LSP2BT HUH1H + LSP2BT HUH2H + LSP2BT HUH3H + LSP2BT HUH4H + LSP2BT CMOS Schmitt Bi-directional with slew rate control output (Bus hold circuit) 12 mA / -12 mA 24 mA / -12 mA HUH3HL + LSP4T HUH4HL + LSP4T Table 11.9 Combinations of Pre-drivers (With Level Shifters) and HV DD Bi-directional Cells (Continued) Input Level Function IOL * / IOH Cell Structure*

Chapter 11: Dual Power Supplies Guidelines

120 EPSON GATE ARRAY S1L30000 SERIES

11.4 Calculating Delay Times in Dual Power Supply Systems

When dual power supplies are used, there will be cells wherein the delay coefﬁcient variability M of Table 7.1 (Chapter 7) cannot be used in situations such as shown below: Cells where the “Delay Coefﬁcient Variability M” of Table 7.1 cannot be used

H VDD system input cells (such as HIBC, HIBT, etc.)
H VDD system bi-directional cells (such as HUC∗, HUT∗, etc.)
Pre-drivers with level shifters (LSP∗) T0 and K Min., Typ., and Max. values for these cells are listed in the “Gate Array S1L30000 Series MSI Cell Library.” Calculate the delay times using these values of T0 and K. (1) The Delay Time (Typ. Value) Calculation The method for calculating the delay time (Typ. value) for dual power supplies is the same as the method for calculating the delay time (Typ. value) for a single power supply. Because a high-precision delay calculation environment is provided, one must note that the calculated delay times do not match those delay times which are calculated by using the values listed in the “Gate Array S1L30000 MSI Cell Library.” For input cells, use the values of T 0 (Typ.) and K (Typ.) corresponding to the appropriate operating voltage of the HV DD and the LVDD system cells. When calculating the delay time (Typ. value) of the internal cells, use the T0 (Typ.) and K (Typ.) values for the power supply voltage of the LVDD system. When calculating the output buffer delay time (Typ. value), the HVDD system delay time is the sum of the output cell delay time (Typ. value) and the pre-driver (with level shifter) delay time (Typ. value). (2) Delay Time (Min., Max. values) Calculation and Variability in the Delay Coefﬁcient In the case of single power supplies, the typical value is multiplied by the delay variability coefﬁcient M (Table 7.1) to obtain the Max. and Min. values of the delay times. In con- trast, when dual power supplies are used, the delay variability coefﬁcients for the LV DD system and the HVDD system are different, so the Min. values and Max. values of the delay time for each cell are calculated separately. Min. value and Max. value of the delay time for a circuit is obtained by adding the delay times calculated for each cell. However, when dual power supplies are used, the delay coefﬁcient variability M listed in Table 7.1 cannot be used for cells such as HIBC, HUB1, LSP1, etc. For these type of cells, the Min. value of the delay time, for example, would be calculated by using the Min. values of T 0 and K in the cell library. Also, when calculating the Max. value for the delay time, the Max. values of T0 and K from the cell library are used in the calculation.

Chapter 11: Dual Power Supplies Guidelines GATE ARRAY S1L30000 SERIES EPSON 121 DESIGN GUIDE

11.5 Cautions and Notes Regarding Power Consumption

Calculations When Using Dual Power Supplies The power consumption calculations compatible with dual power supplies require the calculation of power consumption to be split into HVDD and LVDD systems. (1) Input Cell Power Consumption (Pi [HVDD ] and Pi [LVDD ]) The formula is not different from the formula for single power supply. If we deﬁne the power consumption for the HVDD system as Pi (HVDD ) and the power consumption for the LVDD system as Pi (LVDD ) then: The sum of Pi (HVDD ) and Pi (LVDD ) from the formulas above is the power consumption of the input cell. For input cells in HVDD systems, replace the 5.0 V Kpi when performing cal- culations with a 3.3 V/3.0 V Kpi in the case of the LVDD system. See Table 9.1 of Chapter 9 for Kpi values. (2) Output Cell Power Consumption (Po (HVDD ) and Po(LVDD )) The formula is not different from the formula for single power supply. If we deﬁne the power consumption for the HVDD system as Po (HVDD ) and the power consumption for the LVDD system as Po(LVDD ) then The output cell power consumption is the sum of Po (HVDD ) and Po (LVDD ) of the formulas above. When performing these calculations, be aware that the VDD values in the HVDD and LVDD systems are different. NOTE: Be aware that the value for VOHi is different in the HVDD system than it is in the LVDD system. Pi (HVDD ) = Σ (Kpi X fi) (W) K i=1 K i=1 Pi (LVDD ) = Σ (Kpi X fi) (W) Po (HVDD ) = Σ (PAC + PDC ) = Σ {fi X CLi X (HVDD ) 2} + Σ {(HVDD - VOH i) X |IOH i| X Duty H} K i=1 K i=1 + Σ {VOL i X IOL i X Duty L} K i=1 Po (LVDD ) = Σ (PAC + PDC ) = Σ {fi X CLi X (LVDD ) 2} + Σ {(LVDD - VOH i) X |IOH i| X Duty H} K i=1 K i=1 + Σ {VOL i X IOL i X Duty L} K i=1

Chapter 11: Dual Power Supplies Guidelines

122 EPSON GATE ARRAY S1L30000 SERIES

(3) Internal Cell Power Consumption (Pint) This formula is not different from the formula for the single power supply. The power consumed in the internal cells is calculated using the above formula. Replace Kpint with the appropriate LVDD Kpint when performing the calculation. See Table 9.2 of Chapter 9 for the Kpint values. Using the above, the Ptotal total power consumed is cal- culated as follows. Ptotal = Pi (HVDD ) + Pi (LVDD ) + Po (HVDD ) + Po (LVDD ) + Pint NOTE: When calculating the power consumption of a pre-driver with a level shifter, calculate using the LVDD system as the operating voltage

11.6 Estimating the Number of Power Supply Terminals When

Even when using a dual power supply system, the magnitude of the allowable current per pair of power supplies (for both the HVDD and the LVDD system) is the same as for the single power supply case. Calculate the required number of power supplies separately for the HVDD system and the LVDD system. * Assuming the current consumption of the HVDD system to be IDD (HVDD ) [mA], the number of pairs of power supply terminals NIDD (HVDD ) for the current consumed IDD (HVDD ) is given by: N IDD (HVDD ) ≥ IDD (HVDD ) / 50 (pairs) * Assuming the current consumption of the LVDD system to be IDD (LVDD ) [mA], the number of pairs of power supply terminals NIDD (LVDD ) for the current consumed IDD (LVDD ) is given by: N IDD (LVDD ) ≥ IDD (LVDD ) / 50 (pairs) In this case, there must be a Min. of two pairs of power supply terminals for the HVDD system and a Min. of two pairs for the LVDD system. NOTE: When adding power supplies in response to the simultaneous switching of outputs, distinctions should be drawn between the HVDD system output cells and the LVDD system output cells. Reference Chapter 10 when adding power supply systems to each. = Σ {(Nb X U) X fi X Spi X Kpint} (W) Κ i=1 Pint

GATE ARRAY S1L30000 SERIES EPSON 123 DESIGN GUIDE Simulation Input Timing Waveforms *The about timing might change with the limitation of the measuring system including a tester. A FILE NAME TYPEWAVEFORMINPUT PIN NAME NRZ B NRZ C NRZ D NRZ NRZ STROBE * SYSTEM CLOCK STROBE POINT RATE A.PA.P A.P=ACTIVE POINT A B C D E RATE (ns) COMMENTDELAY (ns) (SYSTEM CLOCK) Duty

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First issue February,1996 D Printed March, 2001 in Japan C A EPSON Electronic Devices Website ELECTRONIC DEVICES MARKETING DIVISION http://www.epsondevice.com Document code: 404566403 This manual was made with recycle papaer, and printed using soy-based inks.

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S1L30000 specifications and overview.

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GATE ARRAY

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GATE ARRAY

Source title S1L30000 Datasheet(PDF) - Epson Company

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