STS1HNK60 STMICROELECTRONICS | Alldatasheet

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Technical content

N-CHANNEL 600V - 8Ω -0 . 3 AS O - 8 SuperMESH™Power MOSFET ■ TYPICAL R DS (on) = 8Ω ■ EXTREMELY HIGH dv/dt CAPABILITY ■ 100% AVALANCHE TESTED ■ GATE CHARGE MINIMIZED ■ NEW HIGH VOLTAGE BENCHMARK

DESCRIPTION

The SuperMESH™ series is obtained through an extreme optimization of ST’s well established strip- based PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is tak- en to ensure a very good dv/dt capability for the most demanding applications. Such series comple- ments ST full range of high voltage MOSFETs in- cluding revolutionary MDmesh™ products.

APPLICATIONS

■ SWITCH MODE LOW POWER SUPPLIES (SMPS) ■ LOW POWER, LOW COST CFL (COMPACT FLUORESCENT LAMPS) ■ LOW POWER BATTERY CHARGERS

ORDERING INFORMATION

TYPE V DSS R DS(on) ID Pw STS1HNK60 600 V < 8.5 Ω 0.3 A 2 W SALES TYPE MARKING PACKAGE PACKAGING STS1HNK60 S1HNK60 SO-8 TAPE & REEL SO-8 INTERNAL SCHEMATIC DIAGRAM

(/circle6 ) Pulse width limited by safe operating area (1) ISD ≤0.3A, di/dt≤100A/µs, VDD ≤ V(BR)DSS ,Tj≤ TJMAX. THERMAL DATA ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) ON/OFF Symbol Parameter Value Unit VDS Drain-source Voltage (VGS =0 ) 600 V VDGR Drain-gate Voltage (RGS =2 0kΩ ) 600 V VGS Gate- source Voltage ± 30 V ID Drain Current (continuous) at TC = 25°C 0.3 A ID Drain Current (continuous) at TC = 100°C 0.19 A IDM (/circle6 ) Drain Current (pulsed) 1.2 A PTOT Total Dissipation at TC = 25°C 2W Derating Factor 0.016 W/°C dv/dt (1) Peak Diode Recovery voltage slope 3 V/ns Tj Tstg Operating Junction Temperature Storage Temperature -65 to 150 °C Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W Symbol Parameter Test Conditions Min. Typ. Max. Unit V(BR)DSS Drain-source Breakdown Voltage ID =1m A ,VGS = 0 600 V IDSS Zero Gate Voltage Drain Current (VGS =0 ) VDS = Max Rating VDS = Max Rating, TC = 125 °C µA µA IGSS Gate-body Leakage Current (VDS =0 ) VGS = ± 30 V ±100 nA VGS(th) Gate Threshold Voltage VDS =V GS ,ID = 250 µA 2.25 3 3.7 V R DS(on) Static Drain-source On Resistance VGS =1 0V ,ID = 0.5 A 8 8.5 Ω

ELECTRICAL CHARACTERISTICS (CONTINUED) DYNAMIC SWITCHING ON SWITCHING OFF SOURCE DRAIN DIODE Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Symbol Parameter Test Conditions Min. Typ. Max. Unit gfs(1) Forward Transconductance V DS >ID(on)xR DS(on)max, ID = 0.5 A C iss C oss C rss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS =2 5 V ,f=1M H z ,VGS = 0 156 23.5 3.8 pF pF pF Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tr Turn-on Delay Time Rise Time VDD =3 0 0V ,ID = 0.5 A R G = 4.7Ω VGS =1 0V (Resistive Load see, Figure 3) 6.5 ns ns Q g Q gs Q gd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD =4 8 0V ,ID =1A , VGS =1 0 V ,RG = 4.7Ω 1.1 3.4 10 nC nC nC Symbol Parameter Test Conditions Min. Typ. Max. Unit td(off) tf Turn-off Delay Time Fall Time VDD = 300 V, ID = 0.5 A R G =4 . 7Ω VGS =1 0V (Resistive Load see, Figure 3) ns ns tr(Voff) tf tc Off-voltage Rise Time Fall Time Cross-over Time VDD = 480V, ID = 1.0 A, R G =4 . 7Ω, VGS = 10V (Inductive Load see, Figure 5) ns ns ns Symbol Parameter Test Conditions Min. Typ. Max. Unit ISD ISDM (2) Source-drain Current Source-drain Current (pulsed) 0.3 1.2 A A VSD (1) Forward On Voltage ISD = 0.3 A, VGS =0 1.6 V trr Q rr IRRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 0.3 A, di/dt = 100 A/µs VDD =2 5V ,Tj= 150°C (see test circuit, Figure 5) 229 377 3.3 ns µC A

Static Drain-source On ResistanceTransconductance Output Characteristics Safe Operating Area Transfer Characteristics

Normalized BVDSS vs Temperature Normalized On Resistance vs TemperatureNormalized Gate Threshold Voltage vs Temp. Gate Charge vs Gate-source Voltage Capacitance Variations Source-drain Diode Forward Characteristics

Fig. 5:Test Circuit For Inductive Load Switching And Diode Recovery Times Fig. 4:Gate Charge test Circuit Fig. 2:Unclamped Inductive WaveformFig. 1:Unclamped Inductive Load Test Circuit Fig. 3:Switching Times Test Circuit For Resistive Load

DIM. mm inch A1 . 7 5 0 . 0 6 8 a1 0.1 0.25 0.003 0.009 a2 1.65 0.064 a3 0.65 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.019 c1 45 (typ.) D 4.8 5.0 0.188 0.196 E 5.8 6.2 0.228 0.244 e1 . 2 7 0 . 0 5 0 e3 3.81 0.150 F 3.8 4.0 0.14 0.157 L 0.4 1.27 0.015 0.050 M0 . 6 0 . 0 2 3 S 8 (max.) 0016023 SO-8 MECHANICAL DATA

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