S1D13704F00A

S1D13305 EPSON | Alldatasheet

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Datasheet sections

• 8.5.2 MREAD

Datasheet sections

• 16.3 System Interconnection

No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no represen- tation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. ] In this manual, Zilog's Z80-CPU or its equivalent shall be called Z80, Intel's 8085A or its equivalent shall be called 8085 and Motorola's MC6809 and MC6802 or their equivalents shall be called 6809 and 6802, respectively. ® stands for registered trade mark. All other product names mentioned herein are trademarks and/or registered trademarks of their respec- tive owners. © Seiko Epson Corporation 2001 All rights reserved.

Comparison table between new and previous number of Evaluation Boards S5U 13705 P00C Specification Corresponding model number (13705: for S1D13705) Product classification (S5U: development tool for semiconductor) S1 D 13706 F 00A0 00 The information of the product number change Starting April 1, 2001, the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales representative. Devices Configuration of product number Comparison table between new and previous number Packing specification Specification Package (B: CSP, F: QFP) Corresponding model number Model name (D: driver, digital products) Product classification (S1: semiconductor) Evaluation Board Previous No. SED1335 Series SED1335D0A SED1335F0A SED1335F0B S1D13305 Series S1D13305D00A S1D13305F00A S1D13305F00B New No. Previous No. SED135x Series SED1353D0A SED1353F0A SED1353F1A SED1354F0A SED1354F1A SED1354F2A SED1355F0A SED1356F0A S1D1350x Series S1D13503D00A S1D13503F00A S1D13503F01A S1D13504F00A S1D13504F01A S1D13504F02A S1D13505F00A S1D13506F00A New No. Previous No. SED137x Series SED1374F0A SED1375F0A SED1376B0A SED1376F0A SED1378 Series S1D1370x Series S1D13704F00A S1D13705F00A S1D13706B00A S1D13706F00A S1D13708 Series New No. Previous No. SED13Ax Series SED13A3F0A SED13A3B0B SED13A4B0B S1D13A0x Series S1D13A03F00A S1D13A03B00B S1D13A04B00B New No. Previous No. SED138x Series SED1386F0A S1D1380x Series S1D13806F00A New No.

• S1D1350x Series
• S1D13305 Series • S1D1370x Series
• S1D13A0x Series
• S1D1380x Series
• S1D1350x Series
• S1D1370x Series • S1D1380x Series
• S1D13A0x Series Previous No. SDU1353#0C SDU1354#0C SDU1355#0C SDU1356#0C S5U13503P00C S5U13504P00C S5U13505P00C S5U13506P00C New No. Previous No. SDU1374#0C SDU1375#0C SDU1376#0C SDU1376BVR SDU1378#0C S5U13704P00C S5U13705P00C S5U13706P00C S5U13706B32R S5U13708P00C New No. Previous No. SDU1386#0C S5U13806P00C New No. Previous No. SDU13A3#0C SDU13A4#0C S5U13A03P00C S5U13A04P00C New No.

1. OVERVIEW The S1D13305 series is a controller IC that can display text and graphics on LCD panel. The S1D13305 series can display layered text and graph- ics, scroll the display in any direction and partition the display into multiple screens. The S1D13305 series stores text, character codes and bit- mapped graphics data in external frame buffer memory. Display controller functions include transferring data from the controlling microprocessor to the buffer memory, reading memory data, converting data to display pixels and generating timing signals for the buffer memory, LCD panel. The S1D13305 series has an internal character generator with 160, 5 × 7 pixel characters in internal mask ROM. The character generators support up to 64, 8 × 16 pixel characters in external character generator RAM and up to 256, 8 × 16 pixel characters in external character genera- tor ROM. 2. FEATURES

• Text, graphics and combined text/graphics display modes
• Three overlapping screens in graphics mode
• Up to 640 × 256 pixel LCD panel display resolution
• Programmable cursor control
• Smooth horizontal and vertical scrolling of all or part of the display
• 1/2-duty to 1/256-duty LCD drive
• Up to 640 × 256 pixel LCD panel display resolution memory
• 160, 5 × 7 pixel characters in internal mask-program- med character generator ROM
• Up to 64, 8 × 16 pixel characters in external character generator RAM
• Up to 256, 8 × 16 pixel characters in external character generator ROM
• 6800 and 8080 family microprocessor interfaces
• Low power consumption—3.5 mA operating current DD = 3.5V), 0.05 µA standby current
• Package line-up Package S1D13305F00A QFP5-60 pin S1D13305F00B QFP6-60 pin
• 2.7 to 5.5 V (S1D13305F) OVERVIEW/FEATURES

2 EPSON S1D13305 Series

1. BLOCK DIAGRAM Video RAM Character Generator RAM Character Generator ROM LCD ControllerVideo RAM Interface Display Address Controller Cursor Address Controller Refresh Counter Dot Counter Character Generator ROM Layered Controller Oscillator YSCL, YD, YDIS LP, WF XSCL XD0 to XD3 VD0 to VD7 VA0 to VA15 VCEVRD, VWR (S1D13305F) SEL0 SEL1 RES RD, WR A0, CS D0 to D7 XG XD Input/Output Register LCD Microprocessor Interface BLOCK DIAGRAM

1. PINOUTS ◊S1D13305F00A ◊S1D13305F00B Index 11 5 3145 60 16

30 XD3

V DD CS XD XG SEL1 VD3 VD2 VD1 VD0 VA15 VA14 VA13 VA12 VA11 VA10 VA9 VA8 VA7 VA6 NC VD4 VD5 VD6 VD7 YSCL YD YDIS WF LP V SS XSCL XECL XD0 XD1 XD2 VA5 VA4 VA3 VA2 VA1 VA0 VWR VCE VRD RES NC NC RD WR SEL 2 Index1 3060 404550 201510 VA8 VA9 VA10 VA11 VA12 VA13 NC VA14 VA15 VD0 VD1 VD2 XD CS V DD XD3 XD2 XD1 XD0 XECL XSCL V SS LP WF YDIS YD YSCL VD7 VD6 VD5 VD4 VD3 XG SEL1 SEL2 WR RD NC NC RES VRD VCE VWR VA0 VA1 VA2 VA3 VA4 VA5 VA6 VA7 S1D13305F00BS1D13305F00A PINOUTS

4 EPSON S1D13305 Series

1. PIN DESCRIPTION 5.1. S1D13305F00A/00B Pin Summary Name Number Type Description VA0 to VA15 27 to 28 1 to 6 Output VRAM address bus30 to 43 50 to 59 VWR 44 7 Output VRAM write signal VCE 45 8 Output Memory control signal VRD 46 9 Output VRAM read signal RES 47 10 Input Reset NC 28, 48, 49 11, 12, 60 — No connection RD 50 13 Input 8080 family: Read signal 6800 family: Enable clock (E) WR 51 14 Input 8080 family: Write signal 6800 family: R/W signal SEL2 52 15 Input 8080 or 6800 family interface select SEL1 53 16 Input 8080 or 6800 family interface select XG 54 17 Input Oscillator connection XD 55 18 Output Oscillator connection CS 56 19 Input Chip select A0 57 20 Input Data type select V DD 58 21 Supply 2.7 to 5.5V supply D0 to D7 59 to 60 22 to 29 Input/output Data bus1 to 6 XD0 to XD3 7 to 10 30 to 33 Output X-driver data XECL 11 34 Output X-driver enable chain clock XSCL 12 35 Output X-driver data shift clock V SS 13 36 Supply Ground LP 14 37 Output Latch pulse WF 15 38 Output Frame signal YDIS 16 39 Output Power-down signal when display is blanked YD 17 40 Output Scan start pulse YSCL 18 41 Output Y-driver shift clock VD0 to VD7 19 to 26 42 to 49 Input/output VRAM data bus S1D13305F00A S1D13305F00B PIN DESCRIPTION

5.2. Pin Functions 5.2.1. Power supply 5.2.3. Microprocessor interface 5.2.2. Oscillator Pin Name Function VDD 2.7 to 5.5V supply. This may be the same supply as the controlling microprocessor. VSS Ground Note: The peak supply current drawn by the S1D13305 series may be up to ten times the average supply current. The power supply impedance must be kept as low as possible by ensuring that supply lines are sufficiently wide and by placing 0.47 µF decoupling capacitors that have good high-frequency response near the device’s supply pins. Pin Name Function XG Crystal connection for internal oscillator (See section 13). This pin can be driven by an external clock source that satisfies the timing specifications of the EXT φ0 signal (See section 6.3.6). XD Crystal connection for internal oscillator. Leave this pin open when using an external clock source. Pin Name Function D0 to D7 Tristate input/output pins. Connect these pins to an 8- or 16-bit microprocessor bus. Microprocessor interface select pin. The S1D13305 series supports both 8080 family processors (such as the 8085 and Z80®) and 6800 family processors (such as the 6802 and 6809). SEL1 SEL2* Interface A0 RD WR CS 0 0 8080 family A0 RD WR CS 1 0 6800 family A0 E R/W CS Note: SEL1 should be tied directly to VDD or VSS to prevent noise. If noise does appear on SEL1, decouple it to ground using a capacitor placed as close to the pin as possible. SEL1, SEL2 PIN DESCRIPTION

6 EPSON S1D13305 Series

5.2.4. Display memory control The S1D13305 series can directly access static RAM and PROM. The designer may use a mixture of these two types of memory to achieve an optimum trade-off be- tween low cost and low power consumption. Pin Name Function 8080 family interface A0 RD WR Function 0 0 1 Status flag read 1 0 1 Display data and cursor address read 0 1 0 Display data and parameter write 1 1 0 Command write 6800 family interface A0 R/W E Function 0 1 1 Status flag read 1 1 1 Display data and cursor address read 0 0 1 Display data and parameter write 1 0 1 Command write When the 8080 family interface is selected, this signal acts as the active-LOW read strobe. The S1D13305 series output buffers are enabled when this signal is active. When the 6800 family interface is selected, this signal acts as the active-HIGH enable clock. Data is read from or written to the S1D13305 series when this clock goes HIGH. When the 8080 family interface is selected, this signal acts as the active-LOW write strobe. The bus data is latched on the rising edge of this signal. When the 6800 family interface is selected, this signal acts as the read/write control signal. Data is read from the S1D13305 series if this signal is HIGH, and written to the S1D13305 series if it is LOW. Chip select. This active-LOW input enables the S1D13305 series. It is usually connected to the output of an address decoder device that maps the S1D13305 series into the memory space of the controlling microprocessor. This active-LOW input performs a hardware reset on the S1D13305 series. It is a Schmitt-trigger input for enhanced noise immunity; however, care should be taken to ensure that it is not triggered if the supply voltage is lowered. WR or R/W CS RES RD or E VA0 to VA15 16-bit display memory address. When accessing character generator RAM or ROM, VA0 to VA3, reflect the lower 4 bits of the S1D13305 series’s row counter. VD0 to VD7 8-bit tristate display memory data bus. These pins are enabled when VR/W is LOW. VCE Active-LOW static memory standby control signal. VCE can be used with CS. VWR Active-LOW display memory write control output. Pin Name Function VRD Active-LOW display memory read control output. PIN DESCRIPTION

5.2.5. LCD drive signals In order to provide effective low-power drive for LCD matrixes, the S1D13305 series can directly control both the X- and Y-drivers using an enable chain. Pin Name Function XD0 to XD3 4-bit X-driver (column drive) data outputs. Connect these outputs to the inputs of the X-driver chips. The falling edge of XSCL latches the data on XD0 to XD3 into the input shift registers of the X-drivers. To conserve power, this clock halts between LP and the start of the following display line (See section 6.3.7). XECL The falling edge of XECL triggers the enable chain cascade for the X-drivers. Every 16th clock pulse is output to the next X-driver. LP latches the signal in the X-driver shift registers into the output data latches. LP is a falling- edge triggered signal, and pulses once every display line. Connect LP to the Y-driver shift clock on modules. WF LCD panel AC drive output. The WF period is selected to be one of two values with SYSTEM SET command. The falling edge of YSCL latches the data on YD into the input shift registers of the Y-drivers. YSCL is not used with driver ICs which use LP as the Y-driver shift clock. YD is the data pulse output for the Y drivers. It is active during the last line of each frame, and is shifted through the Y drivers one by one (by YSCL), to scan the display’s common connections. Power-down output signal. YDIS is HIGH while the display drive outputs are active. YDIS goes LOW one or two frames after the sleep command is written to the S1D13305 series. All Y-driver outputs are forced to an intermediate level (de-selecting the display segments) to blank the display. In order to implement power-down operation in the LCD unit, the LCD power drive supplies must also be disabled when the display is disabled by YDIS. XSCL LP YSCL YD YDIS PIN DESCRIPTION/SPECIFICATIONS 6. SPECIFICATIONS 6.1. Absolute Maximum Ratings Parameter Symbol Rating Unit Supply voltage range V DD –0.3 to 7.0 Input voltage range V IN –0.3 to VDD + 0.3 V V Power dissipation P D 300 mW Operating temperature range T opg –20 to 75 °C Storage temperature range T stg –65 to 150 °C Soldering temperature (10 seconds). See note 1. Tsolder 260 °C Notes: 1. The humidity resistance of the flat package may be reduced if the package is immersed in solder. Use a soldering technique that does not heatstress the package. 2. If the power supply has a high impedance, a large voltage differential can occur between the input and supply voltages. Take appropriate care with the power supply and the layout of the supply lines. (See section 6.2.) 3. All supply voltages are referenced to VSS = 0V.

8 EPSON S1D13305 Series

6.2. S1D13305 Notes: Parameter Symbol Condition Rating UnitMin. Typ. Max. Supply voltage V DD 4.5 5.0 5.5 V Register data retention voltage VOH 2.0 — 6.0 V Input leakage current I LI VI = VDD . See note 5. — 0.05 2.0 µA Output leakage current I LO VI = VSS . See note 5. — 0.10 5.0 µA Operating supply current I opr See note 4. — 11 15 mA Quiescent supply current I Q Sleep mode, — 0.05 20.0 µAVOSC1 = VCS = VRD = VDD Oscillator frequency f OSC 1.0 — 10.0 MHz External clock frequency f CL 1.0 — 10.0 MHz Oscillator feedback resistance Rf 0.5 1.0 3.0 M Ω TTL HIGH-level input voltage V IHT See note 1. 0.5V DD —V DD V LOW-level input voltage V ILT See note 1. V SS — 0.2V DD V HIGH-level output voltage V OHT IOH = –5.0 mA. 2.4 — — VSee note 1. LOW-level output voltage V OLT IOL = 5.0 mA. See note 1. — — V SS + 0.4 V CMOS HIGH-level input voltage V IHC See note 2. 0.8V DD —V DD V LOW-level input voltage V ILC See note 2. V SS — 0.2V DD V HIGH-level output voltage V OHC IOH = –2.0 mA. See note 2.VDD – 0.4 — — V LOW-level output voltage V OLC IOH = 1.6 mA. See note 2.—— V SS + 0.4 V Open-drain LOW-level output voltage V OLN IOL = 6.0 mA. SS + 0.4 V Schmitt-trigger Rising-edge threshold voltage V T+ See note 3. 0.5V DD 0.7VDD 0.8VDD V Falling-edge threshold voltage VT– See note 3. 0.2V DD 0.3VDD 0.5VDD V VDD = 4.5 to 5.5V, VSS = 0V, Ta = –20 to 75°C Measured at crystal, 47.5% duty cycle. See note 6. 1. D0 to D7, A0, CS, RD, WR, VD0 to VD7, VA0 to VA15, VRD, VWR and VCE are TTL-level inputs. 2. SEL1 is CMOS-level inputs. YD, XD0 to XD3, XSCL, LP, WF, YDIS are CMOS-level outputs. 3. RES is a Schmitt-trigger input. The pulsewidth on RES must be at least 200 µs. Note that pulses of more than a few seconds will cause DC voltages to be applied to the LCD panel. 4. f OSC = 10 MHz, no load (no display memory), internal character generator, 256 × 200 pixel display. The operating supply current can be reduced by approximately 1 mA by setting both CLO and the display OFF. 5. VD0 to VD7 and D0 to D7 have internal feedback circuits so that if the inputs become high-impedance, the input state immediately prior to that is held. Because of the feedback circuit, input current flow occurs when the inputs are in an intermediate state. 6. Because the oscillator circuit input bias current is in the order of µA, design the printed circuit board so as to reduce leakage currents. —— V SPECIFICATIONS

1. D0 to D7, A0, CS, RD, WR, VD0 to VD7, VA0 to VA15, VRD, VWR and VCE are TTL-level inputs. 2. SEL1 is CMOS-level inputs. YD, XD0 to XD3, XSCL, LP, WF, YDIS are CMOS-level outputs. 3. RES is a Schmitt-trigger input. The pulsewidth on RES must be at least 200 µs. Note that pulses of more than a few seconds will cause DC voltages to be applied to the LCD panel. 4. fOSC = 10 MHz, no load (no display memory), internal character generator, 256 × 200 pixel display. The operating supply current can be reduced by approximately 1 mA by setting both CLO and the display OFF. 5. VD0 to VD7 and D0 to D7 have internal feedback circuits so that if the inputs become high-impedance, the input state immediately prior to that is held. Because of the feedback circuit, input current flow occurs when the inputs are in an intermediate state. 6. Because the oscillator circuit input bias current is in the order of µA, design the printed circuit board so as to reduce leakage currents. V DD = 2.7 to 4.5 V, VSS = 0 V, Ta = –20 to 75˚C unless otherwise noted Parameter Symbol Condition Rating Unit Min. Typ. Max. Supply voltage V DD 2.7 3.5 4.5 V Register data retention voltage V OH 2.0 — 6.0 V Input leakage current I LI VI = VDD . See note 5. — 0.05 2.0 µA Output leakage current I LO VI = VSS . See note 5. — 0.10 5.0 µA Operating supply current Iopr VDD = 3.5 V. See note 4. — 3.5 — mA See note 4. — — 7.0 Quiescent supply current I Q Sleep mode, — 0.05 20.0 µAVOSC1 = VCS = VRD = VDD Oscillator frequency f OSC Measured at crystal, 1.0 — 8.0 MHz External clock frequency f CL 47.5% duty cycle. 1.0 — 8.0 MHz Oscillator feedback resistance Rf See note 6. 0.7 — 3.0 M Ω TTL HIGH-level input voltage V IHT See note 1. 0.5 V DD —V DD V LOW-level input voltage V ILT See note 1. V SS — 0.2 V DD V HIGH-level output voltage V OHT IOH = –3.0 mA. See note 1.2.4 — — V LOW-level output voltage V OLT IOL = 3.0 mA. See note 1. — — V SS + 0.4 V CMOS HIGH-level input voltage V IHC See note 2. 0.8 V DD —V DD V LOW-level input voltage V ILC See note 2. V SS — 0.2 V DD V HIGH-level output voltage V OHC IOH = –2.0 mA. See note 2.VDD – 0.4 — — V LOW-level output voltage V OLC IOH = 1.6 mA. See note 2. — — V SS + 0.4 V Open-drain LOW-level output voltage V OLN IOL = 6.0 mA. — — V SS + 0.4 V Schmitt-trigger Rising-edge threshold voltage V T+ See note 3. 0.5 V DD 0.7 VDD 0.8 VDD V Falling-edge threshold voltage V T– See note 3. 0.2 V DD 0.3 VDD 0.5 VDD V SPECIFICATIONS

10 EPSON S1D13305 Series

6.3. S1D13305F Timing Diagrams 6.3.1. 8080 family interface timing tCYC8 tOH8 tAH8tAW8 tCC tDS8 tDH8 tACC8 AO, CS WR, RD D0 to D7 (Write) D0 to D7 (Read) A0, CS tAH8 Address hold time 10 — 10 — ns tAW8 Address setup time 0 — 0 — ns WR, RD tCYC8 System cycle time See note. — See note. —n s tCC Strobe pulsewidth 120 — 150 — ns CL = 100pF tDS8 Data setup time 120 — 120 — ns D0 to D7 tDH8 Data hold time 5 — 5 — ns tACC8 RD access time — 50 — 80 ns tOH8 Output disable time 10 50 10 55 ns Note: For memory control and system control commands: tCYC8 = 2tC + tCC + tCEA + 75 > tACV + 245 For all other commands: tCYC8 = 4tC + tCC + 30 Ta = –20 to 75°C SPECIFICATIONS

6.3.2. 6800 family interface timing Note: tCYC6 indicates the interval during which CS is LOW and E is HIGH. E R/W A0, CS D0 to D7 (Write) D0 to D7 (Read) tCYC6 tAW6 tEW tAH6 tDH6 tDS6 tOH6tACC6 SPECIFICATIONS A0, CS, R/W tCYC6 System cycle time See note. — See note. —n s tAW6 Address setup time 0 — 10 — ns tAH6 Address hold time 0 — 0 — ns tDS6 Data setup time 100 — 120 — ns CL = D0 to D7 tDH6 Data hold time 0 — 0 — ns 100 pF tOH6 Output disable time 10 50 10 75 ns tACC6 Access time — 85 — 130 ns Et EW Enable pulsewidth 120 — 150 — ns Note: For memory control and system control commands: tCYC6 = 2tC + tEW + tCEA + 75 > tACV + 245 For all other commands: tCYC6 = 4tC + tEW + 30 Ta = –20 to 75°C

12 EPSON S1D13305 Series

6.3.3. Display memory read timing EXT Φ 0 VCE VA0 to VA15 VR/W VD0 to VD7 tC tW tCE tW tAHCtASC tCYR tRCS tCEA tRCH tCE3 tOH2tACV EXT φ0t C Clock period 100 — 125 — ns tW VCE HIGH-level pulsewidth tC – 50 — t C – 50 — ns VCE tCE VCE LOW-level pulsewidth 2tC – 30 — 2t C – 30 — ns tCYR Read cycle time 3t C —3 t C —n s tASC Address setup time to tC – 70 — t C – 100 — nsfalling edge of VCE tAHC Address hold time from2tC – 30 — 2t C – 40 — nsfalling edge of VCE tRCS Read cycle setup time totC – 45 — t C – 60 — ns VRD falling edge of VCE tRCH Read cycle hold time 0.5tC — 0.5t C —n sfrom rising edge of VCE tACV Address access time — 3t C – 100 — 3t C – 115 ns VD0 to tCEA VCE access time — 2t C – 80 — 2t C – 90 ns VD7 tOH2 Output data hold time 0 — 0 — ns tCE3 VCE to data off time 0 — 0 — ns VA0 to VA15 CL = 100 pF Ta = –20 to 75°C SPECIFICATIONS

6.3.4. Display memory write timing tWSC tC tCE tAH2 tCA tDH2 tASC tWHC tAS tDHC tDSC tAHC tW EXT φ O VCE VA0 to VA15 VR/W VD0 to VD7 SPECIFICATIONS

14 EPSON S1D13305 Series

EXT φ0t C Clock period 100 — 125 — ns tW VCE HIGH-level pulsewidth tC – 50 — t C – 50 — ns VCE tCE VCE LOW-level pulsewidth 2tC – 30 — 2t C – 30 — ns tCYW Write cycle time 3t C —3 t C —n s tAHC Address hold time from2tC – 30 — 2t C – 40 — nsfalling edge of VCE tASC Address setup time to tC – 70 — t C – 110 — nsfalling edge of VCE VA0 to tCA Address hold time from 0—0— n sVA15 rising edge of VCE tAS Address setup time to 0—0— n sfalling edge of VWR tAH2 Address hold time from 10 — 10 — nsrising edge of VWR tWSC Write setup time to tC – 80 — t C – 115 — ns VWR falling edge of VCE tWHC Write hold time from 2tC – 20 — 2t C – 20 — nsfalling edge of VCE tDSC Data input setup time totC – 85 — t C – 125 — nsfalling edge of VCE VD0 to tDHC Data input hold time 2tC – 30 — 2t C – 30 — nsVD7 from falling edge of VCE tDH2 Data hold time from 55 055 0 n srising edge of VWR Note: VD0 to VD7 are latching input/outputs. While the bus is high impedance, VD0 to VD7 retain the write data until the data read from the memory is placed on the bus. Ta = –20 to 75°C CL = 100 pF SPECIFICATIONS

6.3.5. SLEEP IN command timing VCE WR (Command input) YDIS tWRL tWRD SYSTEM SET writeSLEEP IN write tWRD VCE falling-edge delaySee note 1. — See note 1. —n s WR time tWRL YDIS falling-edge delay — See note 2. — See note 2. nstime Notes: 1. tWRD = 18tC + tOSS + 40 (tOSS is the time delay from the sleep state until stable operation) 2. tWRL = 36tC × [TC/R] × [L/F] + 70 Ta = –20 to 75°C CL = 100 pF SPECIFICATIONS

16 EPSON S1D13305 Series

6.3.6. External oscillator signal timing EXT φ0 tWL tWH tC tRCL tFCL See note 1. See note 2. See note 1. See note 2. tRCL External clock rise time — 15 — 15 ns tFCL External clock fall time — 15 — 15 ns tWH External clock See note 1. See note 2. See note 1. See note 2.nsHIGH-level pulsewidth tWL External clock nsLOW-level pulsewidth tC External clock period 100 — 125 — ns Notes: 1. (tC – tRCL – tFCL ) × 475 < tWH , tWL 1000 2. (tC – tRCL – tFCL ) × 525 > tWH , tWL 1000 Ta = –20 to 75°C EXT φ0 SPECIFICATIONS

6.3.7. LCD output timing The following characteristics are for a 1/64 duty cycle. Row LP LP XSCL tr tftWX tCX tDS tDH tLS tWL tDF tLD tDHY LP YD XD0 to XD3 WF(B) XSCL XD0 to XD3 YD WF WF Row 64 Row 1 1 line time 1 frame time 62 63 64 1 2 3 4 60 61 62 63 64 Row 2 SPECIFICATIONS

18 EPSON S1D13305 Series

tr Rise time — 30 — 40 ns tf Fall time — 30 — 40 ns XSCL tCX Shift clock cycle time 4tC —4 t C —n s tWX XSCL clock pulsewidth 2tC – 60 — 2t C – 60 — ns XD0 to tDH X data hold time 2t C – 50 — 2t C – 50 — ns XD3 tDS X data setup time 2t C – 100 — 2t C – 105 — ns tLS Latch data setup time 2tC – 50 — 2t C – 50 — ns LP t WL LP pulsewidth 4t C – 80 — 4t C – 120 — ns tLD LP delay time from XSCL 0 — 0 — ns WF t DF Permitted WF delay — 50 — 50 ns YD t DHY Y data hold time 2t C – 20 — 2t C – 20 — ns Ta = –20 to 75°C CL = 100 pF SPECIFICATIONS

1. PACKAGE DIMENSIONS Unit: mm 7.1. S1D13305F00A ◊QFP5-60 pin 7.2. S1D13305F00B ◊QFP6-60 pin 0 to 12° 2.8 2.7 ± 0.1 1.5 ± 0.3 0.15 ± 0.05 Index 62 3 0.35 ± 0.1 19.6 ± 0.4 14.0 ± 0.1 25.6 ± 0.4 20.0 ± 0.1 1.0 ± 0.1 Index 11 5 0 to 12° 1.8 2.7 ± 0.1 0.8 ± 0.3 17.6 ± 0.4 14.0 ± 0.2 17.6 ± 0.4 14.0 ± 0.2 PACKAGE DIMENSIONS

20 EPSON S1D13305 Series

Table 1. Command set

1. In general, the internal registers of the S1D13305 series are modified as each command parameter is input. However,

parameter registers are unchanged. half of the parameter has been input, the single byte is ignored.

1. APL and APH are 2-byte parameters, but are treated as two 1-byte parameters.

commands to operate incorrectly.

1. Resets the internal timing generator

Selects the internal or external character generator ROM. ters are fixed at fabrication by the metallization mask. hand, can contain up to 256 user-defined characters. memory cannot be written to. space is treated as character generator ROM. Figure 1. SYSTEM SET instruction

22 EPSON S1D13305 Series

S1D13305 series graphics mode to reposition them. Selects the LCD drive method. Figure 2. Single-panel display Figure 3. Above and below two-panel display

Figure 4. Left-and-right two-panel display There are no Seiko Epson LCD units in the configuration shown in Figure 4. Table 2. LCD parameters

1. See table 26 for further details on setting the C/R and TC/R parameters when using the HDOT SCR command.
2. The value of SL when IV = 0 is equal to the value of SL when IV = 1, plus one.

24 EPSON S1D13305 Series

See Section 10.5 for information on scrolling. Figure 5. IV and HDOT SCR adjustment Table 3. Horizontal character size selection applies to the second screen layer. the second eight bits is not displayed. Figure 6. FX and FY display addresses

In 16-line AC drive, WF inverts every 16 lines. voltages or at high viewing angles. FY can range from 00 to 0FH inclusive. Table 4. Vertical character size selection

0 E 1110 1 5

0 F 1111 1 6

number of horizontal bytes per character. C/R can range from 0 to 239. less 2. See Section 16.1.1 for the calculation of C/R. number of excess pixels must not exceed 64. Table 5. Display line address range

4 F 01001111 8 0

26 EPSON S1D13305 Series

Table 6. Line length selection equal to L/F + 1, where L/F can range from 0 to 255. Table 7. Frame height selection

7 F 01111111 1 2 8

28 EPSON S1D13305 Series

be set to flash over one character or over a whole line. Figure 10. DISP ON/OFF parameters dence over the FP bits in the parameter. cursor flashes with a 70% duty cycle (ON/OFF). Table 9. Cursor flash rate selection Table 10. Screen block attribute selection SAD2 and SAD4 cannot be set independently.

10 Flash at f

11 Flash at fFR /64 Hz

11 Flash at fFR /4 Hz

Figure 11. SCROLL instruction parameters

30 EPSON S1D13305 Series

SL1 and SL2 set the number of lines per scrolling screen. Table 11. Screen block start address selection Table 12. Text display mode if not using a partitioned screen.

Table 12. Text display mode (continued) Set both SL1 and SL2 to ((L/F) / 2 + 1).

1. SAD3 has the same value as either SAD1 or SAD2, whichever has the least number of lines (set by SL1 and SL2).
2. Since the parameters corresponding to SL3 and SL4 are fixed by L/F, they do not have to be set in this mode.

32 EPSON S1D13305 Series

Table 13. Graphics display mode

Table 13. Graphics display mode (continued)

1. SAD3 has the same value as either SAD1 or SAD2, whichever has the least number of lines (set by SL1 and SL2).
2. Since the parameters corresponding to SL3 and SL4 are fixed by L/F, they do not have to be set.
3. If, and only if, W/S = 1, the differences between SL1 and (L/F + 1) / 2, and between SL2 and (L/F + 1) / 2, are blanked.

Set both SL1 and SL2 to ((L/F) / 2 + 1). Figure 12. Two-panel display height

34 EPSON S1D13305 Series

graphics displays when displaying special characters. Figure 13. CSRFORM parameter bytes be less than or equal to FX. Table 14. Horizontal cursor size selection the vertical size of the cursor from the character origin. CRY is equal to the number of lines less one. Table 15. Cursor height selection Figure 14. Cursor size and position by the number of bytes specified by the address pitch, AP. address increment on each read or write. Figure 15. CSRDIR parameters Figure 16. Cursor direction

Table 16. Cursor shift direction Figure 17. OVLAY parameters be specified for the individual screen blocks. flashing of individual screens is used. ment in character units. See Section 9.3. Table 17. Composition method selection L1: First layer (text or graphics). If text is selected, layer L3 cannot be used.

36 EPSON S1D13305 Series

Note 1: Screen blocks 2 and 4 can only display graphics. Figure 18. Combined layer display Set OV to 0 for mixed text and graphics mode. Specifies the CG RAM start address. Figure 19. CGRAM ADR parameters See section 10 for information on the SAG parameters.

38 EPSON S1D13305 Series

byte and then the high byte of the register. Figure 23. CSRR parameters Figure 24. MWRITE parameters P1, P2, ..., Pn: display data.

Puts the S1D13305 series into the data output state. mands or by updating the cursor address register. positions ahead of the cursor. Figure 25. MREAD parameters

40 EPSON S1D13305 Series

1. DISPLAY CONTROL FUNCTIONS

can be varied in both dimensions. Figure 26. Example of character display ([FX] ≤ 8) and generator bitmap extra space between displayed characters is blank.

Figure 27. Character width greater than one byte wide ([FX] = 9) even though the character image requires only one.

42 EPSON S1D13305 Series

display memory as the text screen. screens and the physical screen. C/R. Rows are scanned from top to bottom. next line of text is displayed. Figure 28. Virtual and physical screen relationship

44 EPSON S1D13305 Series

Figure 31. Two-panel display address indexing are thus read alternately, one line at a time.

46 EPSON S1D13305 Series

memory and restored after memory access is complete. Figure 34. Cursor addressing memory for more than a few hundred milliseconds. automatically moving the cursor to the desired location. Figure 35. Cursor display layers set to an address within the blank text screen block. over the graphical characters.

displayed at the cursor address. graphics screen, a bar cursor. Figure 36. Cursor movement

48 EPSON S1D13305 Series

message display area. See Figure 37 and 38. Figure 37. Display layers and memory

Figure 38. Display window and memory

50 EPSON S1D13305 Series

Figure 39. Memory map and magnified characters

52 EPSON S1D13305 Series

units, regardless of the display memory capacity. Figure 42. Horizontal wraparound scrolling

command can be used to scroll horizontally in pixel units. Figure 43. Bidirectional scrolling dently scrolled horizontally in pixel units.

54 EPSON S1D13305 Series

1. CHARACTER GENERATOR 10.1. CG Characteristics 10.1.1. Internal character generator The internal character generator is recommended for minimum system configurations containing a S1D13305 series, display RAM, LCD panel, single-chip micropro- cessor and power supply. Since the internal character generator uses a CMOS mask ROM, it is also recom- mended for low-power applications.

• 5 × 7-pixel font (See Section 17.)
• 160 JIS standard characters
• Can be mixed with character generator RAM (maxi- mum of 64 CG RAM characters)
• Can be automatically spaced out up to 8 × 16 pixels 10.1.2. External character generator ROM The external CG ROM can be used when fonts other than those in the internal ROM are needed. Data is stored in the external ROM in the same format used in the internal ROM. (See Section 10.3.)
• Up to 8 × 8-pixel characters (M2 = 0) or 8 × 16-pixel characters (M2 = 1)
• Up to 256 characters (192 if used together with the internal ROM)
• Mapped into the display memory address space at F000H to F7FFH (M2 = 0) or F000H to FFFFH (M2 = 1)
• Characters can be up to 8 × 16-pixels; however, excess bits must be set to zero. 10.1.3. Character generator RAM The user can freely use the character generator RAM for storing graphics characters. The character generator RAM can be mapped by the microprocessor anywhere in dis- play memory, allowing effective use of unused address space.
• Up to 8 × 8-pixel characters (M2 = 0) or 8 × 16 characters (M2 = 1)
• Up to 256 characters if mapped at F000H to FFFFH (64 if used together with character generator ROM)
• Can be mapped anywhere in display memory address space if used with the character generator ROM
• Mapped into the display memory address space at F000H to F7FFH if not used with the character gen- erator ROM (more than 64 characters are in the CG RAM). Set SAG0 to F000H and M1 to zero when defining characters number 193 upwards. CHARACTER GENERATOR

Figure 44. Internal and external character mapping Note that there can be no more than 64 characters per bank. Table 20. Character mapping

56 EPSON S1D13305 Series

address. This mapping is shown in Table 21 and 22. Table 21. Character fonts, number of lines ≤ 8 (M2 = 0, M1 = 0) Table 22. Character fonts, 9 ≤ number of lines ≤ 16 (M2 = 1, M1 = 0) Figure 45. Row select address not mapped directly from the address in the SAG register.

• Calculate the address as for M1 = 0.
• Change bit 6 of the character code from “1” to “0”. CHARACTER GENERATOR

• Define a pattern for the “A” in Figure 26.
• The CG RAM table start address is 4800H.
• The character code for the defined pattern is 80H (the first character code in the CG RAM area). As the character code table in Figure 46 shows, codes 80H to 9FH and E0H to FFH are allocated to the CG RAM and can be used as desired. 80H is thus the first code for CG RAM. As characters cannot be used if only using graphics mode, there is no need to set the CG RAM data.

Table 23. Character data example

58 EPSON S1D13305 Series

CG RAM if not using the internal ROM. Figure 46. On-chip character codes

9 A B C D E F

1. MICROPROCESSOR INTERFACE

connected to the lowest bit of the system address bus. bus, and should have a pull-up or pull-down resistor. Table 24. 8080 series interface signals Table 25. 6800 series interface signals when accessing the S1D13305 series. consecutive access that cannot be ignored within a frame. the display can be updated without causing screen flicker. the microprocessor first issues the MWRITE command. access times. See Figure 47. for the next read access. See Figure 48.

101 Display data and cursor address

111 Display data and cursor address

60 EPSON S1D13305 Series

Figure 47. Display memory write cycle Figure 48. Display memory read cycle in the program loop. tACC , tACV and tCYC limits are given in section 6.2.

62 EPSON S1D13305 Series

1. DISPLAY MEMORY INTERFACE

buffers are required if the bus is heavily loaded.

• S1D13305F

Figure 51. Static RAM interface Note: If the bus load is too much, use a bus buffer.

64 EPSON S1D13305 Series

Figure 55. Flowchart for busy flag checking

• Precaution on the write timing to VRAM The allowable writing duration is since “5 × 9 × tOSC ” has elapsed (tOSC = 1/fOSC : a cycle of the oscillation frequency) from the positive going edge of LP up to {(TCR) – (C/R) – 7} × 9 × tOSC . Currently employed D6 status flag reading method does not identify the timing when the read D6 = Low took place. Thus, negative going edge of LP should be used as the interrupt signal when implementing the writing in above timing. If you try to access the display memory in other timing than the above, flickering of the display screen will result.

number of characters per line [VC]. C/R can be determined from VC and FX. not the number of characters. TC/R must satisfy the condition [TC/R] ≥ [C/R] + 4. the value of TC/R revised using the above equation. R and modify it if necessary.

• Vertical scanning halts and a high-contrast hori- zontal line appears.
• All pixels are on or off.
• The LP output signal is absent or corrupted.
• The display is unstable. RESET/APPLICATION NOTES The S1D13305 series requires a reset pulse at least 1 ms long after power-on in order to re-initialize its internal state. For maximum reliability, it is not recommended to apply a DC voltage to the LCD panel while the S1D13305 series is reset. Turn off the LCD power supplies for at least one frame period after the start of the reset pulse. The S1D13305 series cannot receive commands while it is reset. Commands to initialize the internal registers should be issued soon after a reset. During reset, the LCD drive signals XD, LP and FR are halted. A delay of 3 ms (maximum) is required following the rising edges of both RES and V DD to allow for system stabilization. 15. RESET

Figure 56. Reset timing

66 EPSON S1D13305 Series

Figure 57. Initialization procedure Table 26. Epson LCD unit example parameters

1. The remainder pixels on the right-hand side of the display are automatically blanked by the S1D13305F. There is no need to

zero the display memory corresponding to these pixels.

1. Assuming a frame frequency of 60 Hz.

Table 27. Initialization procedure

1 Power-up

2 Supply

3 SYSTEM SET

4 SCROLL

68 EPSON S1D13305 Series

Table 27. Initialization procedure (continued)

5 HDOT SCR

6 OVLAY

7 DISP ON/OFF

8 Clear data in first layer Fill first screen layer memory with 20H (space character)

13 CSR DIR

9 Clear data in second layer Fill second screen layer memory with 00H (blank data)

10 CSRW

11 CSR FORM

12 DISP ON/OFF

70 EPSON S1D13305 Series

18 CSRW

19 MWRITE

14 MWRITE

15 CSRW

16 CSR DIR

17 MWRITE

30 CSRW

31 CSR DIR

32 MWRITE

20 CSRW Repeat operations 18 and 19 to fill in the background under

29 MWRITE

72 EPSON S1D13305 Series

• 320 × 200 pixels, single-panel drive (1/200 duty cycle)
• First layer: text display
• Second layer: graphics display
• 8 × 8-pixel character font
• CG RAM not required r Display memory allocation
• First layer (text): 320/8 = 40 characters per line, 200/8 = 25 lines. Required memory size = 40 × 25 = 1000 bytes.
• Second layer (graphics): 320/8 = 40 characters per line, 200/1 = 200 lines. Required memory size = 40 × 200 = 8000 bytes.

Figure 58. Character over graphics layers

• 320 × 200 pixels, single-panel drive (1/ 200 duty cycle)
• First layer: graphics display
• Second layer: graphics display r Display memory allocation
• First layer (graphics): 320/8 = 40 characters per line, 200/1 = 200 lines. Required memory size = 40 × 200 = 8000 bytes.
• Second layer (graphics): 320/8 = 40 characters per line, 200/1 = 200 lines. Required memory size = 8000 bytes.

Figure 59. Two-layer graphics

74 EPSON S1D13305 Series

r Register setup procedure SYSTEM SET TC/R calculation C = 40H P1 = 30H fOSC = 6 MHz P2 = 87H fFR = 70 Hz P3 = 07H P5 = 2FH [TC/R] = 48, so TC/R = 2FH P6 = C7H P7 = 28H P8 = 00H SCROLL C = 44H P1 = 00H P2 = 00H P3 = C8H P4 = 40H P5 = 1FH P6 = C8H P7 = XH P8 = XH P9 = XH P10 = XH CSR FORM C = 5DH P1 = 07H P2 = 87H HDOT SCR C = 5AH P1 = 00H OVLAY C = 5BH P1 = 0CH DISP ON/OFF C = 59H P1 = 16H X = Don’t care APPLICATION NOTES

• 320 × 200 pixels, single-panel drive (1/200 duty cycle)
• First layer: graphics display
• Second layer: graphics display
• Third layer: graphics display r Display memory allocation
• All layers (graphics): 320/8 = 40 characters per line, 200/1 = 200 lines. Required memory size = 40 × 200 = 8000 bytes.

Figure 60. Three-layer graphics

76 EPSON S1D13305 Series

Figure 61 shows the S1D13305 series in a typical system. a complete medium- resolution liquid crystal display. Figure 61. System block diagram

Figure 62. System interconnection diagram

78 EPSON S1D13305 Series

The S1D13305 series layered screens and flexible scroll- ing facilities support a range of display functions and reduces the load on the controlling microprocessor when displaying underlining, inverse display, text overlaid on graphics or simple animation. These facilities are supported by the S1D13305 series ability to divide display memory into up to four different areas. r Character code table

• Contains character codes for text display
• Each character requires 8 bits
• Table mapping can be changed by using the scroll start function r Graphics data table
• Contains graphics bitmaps
• Word length is 8 bits
• Table mapping can be changed r CG RAM table
• Character generator memory can be modified by the external microprocessor
• Character sizes up to 8 × 16-pixels (16 bytes per character)
• Maximum of 64 characters
• Table mapping can be changed r CG ROM table
• Used when the internal character generator is not adequate
• Can be used in conjunction with the internal char- acter generator and external character generator RAM
• Character sizes up to 8 × 16-pixels (16 bytes per character)
• Maximum of 256 characters
• Fixed mapping at F000H to FFFFH APPLICATION NOTES

80 EPSON S1D13305 Series

Figure 64. Layer synthesis the one layer at the same time. The first layer is text, the second layer is graphics. Figure 65. Half-tone character and graphics

16.5.3.1 Small area

ters at intervals of 0.5 to 1.0 seconds. layers using the OR function. CSRW Set the cursor address. CSRDIR Set the cursor auto-increment direction. MWRITE Write to the display memory.

1. The microprocessor reads the character data from its
2. The microprocessor sets the display address and

Figure 66. Localized flashing

82 EPSON S1D13305 Series

Figure 67. Graphics address indexing

8 O7 O6 O5 O4 O3 O2 O1 O 8 O7 O6 O5 O4 O3 O2 O1

84 EPSON S1D13305 Series

1. INTERNAL CHARACTER GENERATOR FONT

Figure 70. On-chip character set The shaded positions indicate characters that have the whole 6 × 8 bitmap blackened.

1. GLOSSARY OF TERMS A Address AP Address pitch parameter C Character display mode CD Cursor direction of movement parameter CG Character generator CGRAM ADR Character generator memory address CM Cursor display shape parameter C/R Characters per row parameter CRX Horizontal cursor size parameter CRY Vertical cursor size parameter CSR DIR Cursor direction of movement instruction CSR FORM Cursor size, position and type instruction CSRR Read cursor address register instruction CSRW Write cursor address register instruction DM Display mode parameter FC Flashing cursor parameter f FR Frame frequency fOSC Oscillator frequency FP Screen flashing parameter FX Horizontal character size parameter FY Vertical character size parameter G Graphics display mode GLC Graphic line control unit HDOT SCR Horizontal scrolling by pixels instruction IV Screen origin compensation for inverse display L/F Lines per frame instruction MREAD Display memory read instruction MWRITE Display memory write instruction MX Screen composition mode OV Graphics layer select parameter OVLAY Screen layer mode instruction P Parameter R Row RAM Random access memory ROM Read only memory SAD Display scrolling start address parameter SL Display scrolling length parameter TC/R Length, including horizontal blanking, of one screen line VRAM Display memory WF Display drive waveform parameter W/S Windows per screen parameter GLOSSARY OF TERMS

86 EPSON S1D13305 Series

Request for Information on S1D13305 Series Company: Name of the inquiring person: The phenomenon occurred on: Desired date of receiving the reply: ______________ Device name: S1D13305F00A/ S1D13305F00B (Lot No. ) Number of units of the device causing the phenomenon: __units Applications: (Scope of occurrence: ___ / ___) Your address: Documents in your current possession: Your phone number: - - FAX: - - Image plane size: ____ dots × ____ dots (single-plane drive/2-plane drive) Using LCD module (manufacturer): Frame frequency: Hz. Display mode (circle either one) (1) First layer: Characters Two-part plane, Second layer: Graphics Single plane (2) First layer: Characters Single plane, Second layer: Graphics Single plane < (1)' > (3) First layer: Characters Two-part plane, Second layer: Graphics Two-part plane (4) First layer: Graphics Two-part plane, Second layer: Graphics Single plane (5) First layer: Graphics Single plane, Second layer: Graphics Single plane < (4)' > (6) First layer: Graphics Single plane, Second layer: Graphics Single plane, Third layer: Graphics Single plane (7) First layer: Graphics Two-part plane, Second layer: Graphics Two-part plane Initialization parameter: Give in decimals or duodecimals. System setting Scroll HDOT SCR CSRFORM P1(IV, W/S, M2, M1, M0) = P1(SADIL) = P1 = P1 = P2(W/F, FX) = P2(SADIH) = OVLAY P2 = P3(FY) = P3(SL1) = P1 = P4(C/R) = P4(SAD2L) = DISP ON/OFF P5(TC/R) = P5(SAD2H) = P1 = P6(L/F) = P6(SL2) = CSRW P7(APL) = P7(SAD3L) = P1 = P8(APH) = P8(SAD3H) = P2 = P9(SAD4L) = CSR DIR P10(SAD4H) = C = Oscillation frequency: MHz. (internal/external) CPU: CPU clock: MHz. Frame memory capacity: Kb. (using memory IC: , access time: nsec.) Descriptions of your inquiry (Give details such as what type of display is being sought for and which phenomenon is occurring.) Attached documents (circuit diagram, timing chart, program list, or others)

EPSON Electronic Devices Website ELECTRONIC DEVICES MARKETING DIVISION http://www.epson.co.jp/device/ First issue April,1998 D Printed March, 2001 in Japan C A This manual was made with recycle papaer, and printed using soy-based inks.