S1C60A08

Epson Company

4-bit Single Chip Microcomputer

Manufacturer: Epson Company

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4-bit Single Chip Microcomputer G S1C6200C Core CPU G Built-in LCD Driver G Serial Interface I DESCRIPTION The S1C60N08 Series is a single-chip microcomputer made up of the 4-bit core CPU S1C6200C, ROM (4,096 words × 12 bits), RAM (832 words × 4 bits), LCD driver, serial interface, event counter with dial input function, watchdog timer, and two types of time base counter. Because of its low-voltage operation and low power consump- tion, this series is ideal for a wide range of applications, and is especially suitable for battery-driven systems. The S1C60R08 is a microcomputer with a CMOS 4-bit core CPU S1C6200C as main component, and a built-in programmable RAM (ROM emulator). The S1C60R08 has almost the same functions as the S1C60N08/60A08. The mask ROM in the S1C60N08/60A08 has been changed to a ROM emulator that allows the user to rewrite programs using a Serial EEPROM. I CONFIGULATION The S1C60N08 Series is configured as follows, depending on supply voltage and oscillation circuits. Model Supply voltage Oscillation circuit Evaluation tool S1C60N08 3.0 V OSC1 only (Single clock) S1C60R08 S1C60A08 3.0 V OSC1 and OSC3 (Twin clock) S1C60L08 1.5 V OSC1 only (Single clock) I FEATURES ...S1C60A08/60R08 only (differs depending on instruction) CLK = 38.400 kHz: 130 µsec, 182 µsec, 313 µsec (CLK: CPU operation frequency) CLK = 500 kHz: 10 µsec, 14 µsec, 24 µsec...S1C60A08/60R08 only ...S1C60R08 only V-3 V 1/4, 1/3 or 1/2 duty (voltage regulator and booster circuits built-in) Low Voltage Operation Products

Digital envelope built-in (∗1) G Battery low detection circuit (BLD).. Dual system (programmable in 8 values and a fixed value) Serial interface interrupt: 1 system Halt state: 1.0 µA when CLK = 32.768 kHz (Typ.) Run state: 2.2 µA when CLK = 32.768 kHz (Typ.) S1C60L08 Halt state: 1.0 µA when CLK = 32.768 kHz (Typ.) Run state: 2.2 µA when CLK = 32.768 kHz (Typ.) S1C60A08 Halt state: 1.1 µA when CLK = 32.768 kHz (Typ.) Run state: 3.0 µA when CLK = 32.768 kHz (Typ.) Run state: 50 µA when CLK = 500 kHz (Typ.) S1C60R08 Halt state: 1.0 µA when CLK = 32.768 kHz (Typ.) ...Target for S1C60N08 Run state:115 µA when CLK = 500 kHz (Typ.)...Target for S1C60A08 only ∗1: Can be selected with mask option

COM0–3 SEG0–47 VDD VL1 VL2 VL3 CA CB VS1 VSS K00–K03, K10 K20–K23 TEST P00–P03 P10–P13 R00–R03 R10–R13 OTPRST RESET SIN SOUT SCLK ERROUTSDA SCL Core CPU S1C6200C ROM Emulator 4,096 words × 12 bits Interrupt Generator RAM 832 words × 4 bits LCD Driver

48 SEG × 4 COM

∗ OSC3 ∗ OSC4 AMPP AMPM COM0–3 SEG0–47 VDD VL1 VL2 VL3 CA CB VS1 VSS K00–K03, K10 K20–K23 TEST RESET P00–P03 P10–P13 R00–R03 R10–R13 SIN SOUT SCLK Core CPU S1C6200C ROM 4,096 words × 12 bits System Reset Control Interrupt Generator RAM 832 words × 4 bits LCD Driver ∗: S1C60A08 only

G S1C60N08/60L08/60A08 Pin Configuration COM1 COM0 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 No. Pin name SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 AMPP AMPM K23 K22 K21 K20 K10 K03 K02 No. Pin name SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 TEST SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 No. Pin name K01 K00 SIN SOUT N.C. SCLK P03 P02 P01 P00 N.C. N.C. P13 P12 P11 P10 R03 R02 R01 R00 N.C. = No Connection No. Pin name 100 R12 R11 R10 R13 V SS RESET OSC4 OSC3 V OSC2 OSC1 V DD VL3 VL2 VL1 CA CB N.C. COM3 COM2 No. Pin name 5180 INDEX 301 100 S1C60N08/60L08/60A08 QFP5-100pin 5175 INDEX 251 100 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 No. Pin name SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 AMPP AMPM K23 K22 K21 K20 K10 K03 K02 K01 No. Pin name SEG27 SEG26 SEG25 SEG24 TEST SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 N.C. SEG11 SEG10 No. Pin name K00 SIN SOUT N.C. SCLK N.C. P03 P02 P01 P00 P13 P12 P11 P10 R03 R02 R01 R00 R12 R11 N.C. = No Connection No. Pin name 100 R10 R13 V SS RESET OSC4 OSC3 V OSC2 OSC1 V DD VL3 VL2 VL1 CA CB N.C. COM3 COM2 COM1 COM0 No. Pin name S1C60N08/60L08/60A08 QFP15-100pin

G S1C60N08/60L08/60A08 Pin Description Pin name VDD VSS VS1 VL1 VL2 VL3 CA, CB OSC1 OSC2 OSC3 OSC4 K00–K03 K10 K20–K23 P00–P03 P10–P13 R00–R03 R10 R13 R11 R12 SIN SOUT SCLK AMPP AMPM SEG0–47 COM0–3 RESET TEST Pin No. Function Power supply pin (+) Power supply pin (-) Oscillation and internal logic system voltage output pin LCD drive voltage output pin (approx. -1.05 V or 1/2·V L2) LCD drive voltage output pin (2·VL1 or approx. -2.10 V) LCD drive voltage output pin (3·VL1 or 3/2·VL2) Boost capacitor connecting pin Cryctal oscillation input pin Crystal oscillation output pin CR or ceramic oscillation input pin ∗ (N.C. for S1C60N08 and S1C60L08) CR or ceramic oscillation output pin ∗ (N.C. for S1C60N08 and S1C60L08) Input port pin Input port pin Input port pin I/O port pin I/O port pin Output port pin Output port pin or BZ output pin ∗ Output port pin or BZ output pin ∗ Output port pin or SIOF output pin ∗ Output port pin or FOUT output pin ∗ Serial interface data input pin Serial interface data output pin Serial interface clock input/output pin Analog comparator non-inverted input pin Analog comparator inverted input pin LCD segment output pin or DC output pin ∗ LCD common output pin (1/2, 1/3 or 1/4 duty are selectable ∗) Initial reset input pin Input pin for test QFP5-100 96, 97 62–59 57–54 70–67 76–73 80–77 51–28, 26–3 2, 1, 100, 99 QFP15-100 94, 95 61–58 56–53 70–67 74–71 78–75 50–39, 37–26, 24–1 100–97 I/O (I) (I) I O I O I I I I/O I/O O O O O O I O I/O I I O O I I ∗ Can be selected by mask option

G S1C60R08 Pin Configuration COM1 COM0 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 No. Pin name SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 AMPP AMPM K23 K22 K21 K20 K10 K03 K02 No. Pin name SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 TEST SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 No. Pin name K01 K00 SIN SOUT OTPRST SCLK P03 P02 P01 P00 SCL SDA P13 P12 P11 P10 R03 R02 R01 R00 No. Pin name 100 R12 R11 R10 R13 V SS RESET OSC4 OSC3 V OSC2 OSC1 V DD VL3 VL2 VL1 CA CB ERROUT COM3 COM2 No. Pin name 5180 INDEX 301 100 S1C60R08 QFP5-100pin 5175 INDEX 251 100 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 No. Pin name SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 AMPP AMPM K23 K22 K21 K20 K10 K03 K02 K01 K00 No. Pin name SEG27 SEG26 SEG25 SEG24 TEST SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 No. Pin name SIN SOUT OTPRST SCLK P03 P02 P01 P00 SCL SDA P13 P12 P11 P10 R03 R02 R01 R00 R12 R11 No. Pin name 100 R10 R13 V SS RESET OSC4 OSC3 V OSC2 OSC1 V DD VL3 VL2 VL1 CA CB ERROUT COM3 COM2 COM1 COM0 No. Pin name S1C60R08 QFP15-100pin

G S1C60R08 Pin Description Pin name VDD VSS VS1 VL1 VL2 VL3 CA, CB OSC1 OSC2 OSC3 OSC4 K00–K03 K10 K20–K23 P00–P03 P10–P13 R00–R03 R10 R11 R12 R13 SIN SOUT SCLK AMPP AMPM SEG0–47 COM0–3 RESET TEST SCL SDA ERROUT OTPRST Pin No. Function Power supply pin (+) Power supply pin (-) Oscillation and internal logic system voltage output pin LCD drive voltage output pin (approx. -1.05 V or 1/2·V L2) LCD drive voltage output pin (2·VL1 or approx. -2.10 V) LCD drive voltage output pin (3·VL1 or 3/2·VL2) Boost capacitor connecting pin Crystal oscillation input pin Crystal oscillation output pin CR or ceramic oscillation input pin * CR or ceramic oscillation output pin * Input port pin Input port pin Input port pin I/O port pin I/O port pin Output port pin Output port pin or BZ output pin * Output port pin or SIOF output pin * Output port pin or FOUT output pin * Output port pin or BZ output pin * Serial interface data input pin Serial interface data output pin Serial interface clock input/output pin Analog comparator non-inverted input pin Analog comparator inverted input pin LCD segment output pin or DC output pin * LCD common output pin (1/2, 1/3 or 1/4 duty are selectable *) Initial reset input pin Input pin for test Serial EEPROM clock output pin Serial EEPROM data input/output pin Errout detecting singnal output for download program Cold reset pin for re-start download program from EEPROM QFP5-100 96, 97 62–59 57–54 70–67 76–73 80–77 51–28, 26–3 2, 1, 100, 99 QFP15-100 94, 95 60–57 55–52 68–65 74–71 78–75 49–26, 24–1 100–97 I/O (I) (I) I O I O I I I I/O I/O O O O O O I O I/O I I O O I I O I/O O I ∗ Can be selected by mask option

DEVICE TYPE II 2. S1C60L08 (Low Power Type) (Note) II 3. S1C60A08 (Twin Clock Type)

CLOCK TYPE (for Evaluation board) II 1. 32 kHz II 2. 38 kHz 2. OSC3 SYSTEM CLOCK (only for S1C60A08) II 1. CR II 2. Ceramic 3. MULTIPLE KEY ENTRY RESET II 2. Use K00, K01 II 3. Use K00, K01, K02 II 4. Use K00, K01, K02, K03 4. WATCHDOG TIMER II 1. Use II 2. Not Use 5. INPUT INTERRUPT NOISE REJECTOR 6. INPUT PORT PULL DOWN RESISTOR 7. OUTPUT PORT SPECIFICATION (R00–R03) 8. R10 SPECIFICATION 9. R11 SPECIFICATION 10. R12 SPECIFICATION II 2. FOUT 32768 or 38400 [Hz] II 3. FOUT 16384 or 19200 [Hz] II 4. FOUT 8192 or 9600 [Hz] II 5. FOUT 4096 or 4800 [Hz] II 6. FOUT 2048 or 2400 [Hz] II 7. FOUT 1024 or 1200 [Hz] II 8. FOUT 512 or 600 [Hz] II 9. FOUT 256 or 300 [Hz]

R13 SPECIFICATION II 2. Buzzer Inverted Output (R13 Control) II 3. Buzzer Inverted Output (R10 Control) 12. I/O PORT SPECIFICATION 13. SIN PULL DOWN RESISTOR II 1. With Resistor II 2. Gate Direct 14. SOUT SPECIFICATION II 1. Complementary II 2. Pch-OpenDrain 15. SCLK SPECIFICATION 16. SIO DATA PERMUTATION II 1. MSB First II 2. LSB First 17. EVENT COUNTER NOISE REJECTOR II 1. 2048 or 2400 [Hz] II 2. 256 or 300 [Hz] 18. LCD SPECIFICATION

BIAS SELECTION II 2. 1/3 Bias, Regulator Not Used, LCD 3 V II 3. 1/2 Bias, Regulator Not Used, LCD 3 V II 4. 1/3 Bias, Regulator Not Used, LCD 4.5 V II 2. 1/2 Bias, Regulator Not Used, LCD 3 V II 3. 1/3 Bias, Regulator Not Used, LCD 4.5 V II 2. 1/3 Bias, Regulator Not Used, LCD 3 V II 3. 1/2 Bias, Regulator Not Used, LCD 3 V II 4. 1/3 Bias, Regulator Not Used, LCD 4.5 V II 2. 1/3 Duty II 3. 1/2 Duty 19. SEGMENT MEMORY ADDRESS II 1. 0 Page (040–06F) II 2. 2 Page (240–26F) Note: The S1C60R08 does not support the S1C60L08.

I S1C60R08 ROM EMULATOR/ROM EMULATOR PROGRAMMER The S1C60R08 has a built-in ROM emulator, which is constructed by RAM, to emulate mask ROM. The ROM emulator is programmed from outside through the serial interface (programmer) circuit and then its data is read by the CPU. This chapter explain the ROM emulator and the Programmer circuit. G Configuration of ROM Emulator The built-in ROM emulator is the same structure with the mask ROM built-in S1C60N08. And used for loading the user-program. That has a capacity of 4,096 steps × 12 bits. The program area consists of 16 (0–15) pages × 256 (00H–FFH) steps. After initial reset, the program beginning address is set to bank 0, page 1, step 00H. The interrupt vector is allocated to page 1, steps 01H–0FH. Step 00H Step 0FH Step 10H Step FFH 12 bits Program start address Interrupt vector area Bank 0 Page 0 Page 1 Page 2 Page 3 Page 15 Step 01H The ROM emulator data is downloaded from an external Serial EEPROM through the Programmer circuit. After power on or a HIGH pulse is input to the OTPRST pin, the ROM emulator data is initialized and downloading will be started. G Configuration of ROM Emulator Programmer The ROM emulator data is written through the Programmer. The Programmer supports data transmit/receive communication with Serial EEPROM, interface data error check and system reset signal generation. VSS CPU VDD OTPRST SDA SCL ERROUT Error Detect Circuit OSC1 RESET S1C60R08 System reset Configuration flag CPU and peripheral circuit ROM Emulator 4,096 × 12 bits EEPROM Interface Circuit Serial EEPROM Terminals The Programmer uses the following input/output terminals. SCL: Serial EEPROM control clock output terminal SDA: Serial EEPROM data transmit/receive terminal ERROUT: Data check result output terminal OTPRST: Data re-loading start input terminal

The S1C60R08 has two operation modes,

Programming mode: Load the data from the Serial EEPROM
Normal mode: Work as if the mask ROM type The following describes how to operate the S1C60R08. 1) Make an application software. 2) Convert the software to the Serial EEPROM format with winedg in the S1C60R08 package. 3) Write the program which is converted to the Serial EEPROM format to the Serial EEPROM. 4) Set up the S1C60R08, the Serial EEPROM and the other peripheral components on the user target application. (The example is described in "BASIC EXTERNAL CONNECTION DIAGRAM".) 5) The application power on. 6) The S1C60R08 enters to the Programming mode, and starts data loading from the Serial EEPROM to the built-in ROM emulator automatically. In the loading, internal circuit is kept as system reset condition ex- cept the Programmer. And data error checking is done at the same time. 7) If the data error happens, the ERROUT pin goes HIGH level and data loading is terminated. 8) If the data has loaded without any error, the S1C60R08 enters to the Normal mode automatically. Then the CPU read the ROM emulator data as the instruction and start to run as if the mask ROM type. 9) If you want to re-load the data, input a HIGH pulse to the OTPRST pin. Then the S1C60R08 enters to Programming mode and starts re-loading. I SUMMARY OF NOTES G Target Type for S1C60N08 Series The S1C60N08 has 3 types (S1C60N08, S1C60A08 and S1C60L08). In these models, the S1C60R08 supports the following 2 types as the ROM emulator model. S1C60N08 V DD = 3.0 V (Typ.), OSC1 S1C60A08 V DD = 3.0 V (Typ.), OSC1/OSC3 Refer the "S1C60N08/60R08 Technical Manual". G Mask/Segment Option The S1C60R08 can load ROM emulator data. But cannot load the mask option and segment option. Therefore customer must make the function option data and segment option data by the S1C60R08 development tool at first. Then send the data to SEIKO EPSON and order the mask. SEIKO EPSON makes the S1C60R08 with a customized option according to this request. G Serial EEPROM The external Serial EEPROM is necessary for programming the ROM emulator data, and this component is recommended. Recommended component: AK6010A/12A (AKM) M24C64/32 (SGS-THOMSON) BR24C64 (ROHM) 24AA64 (Microchip) Note: Use larger EEPROM than program memory size.

I ELECTRICAL CHARACTERISTICS G Absolute Maximum Ratings S1C60N08/60A08/60R08 Rating Supply voltage Input voltage (1) Input voltage (2) Permissible total output current ∗1 Operating temperature Storage temperature Soldering temperature / time Permissible dissipation ∗ (VDD =0V ) Symbol VSS VI VIOSC ΣIVSS Topr Tstg Tsol P D Value -5.0 to 0.5 VSS -0.3 to 0.5 VS1-0.3 to 0.5 -20 to 70 -65 to 150 260°C, 10sec (lead section) 250 Unit V V V mA mW ∗1: ∗2: The permissible total output current is the sum total of the current (average current) that simultaneously flows from the output pins (or is draw in). In case of plastic package. S1C60L08 Rating Supply voltage Input voltage (1) Input voltage (2) Permissible total output current ∗1 Operating temperature Storage temperature Soldering temperature / time Permissible dissipation ∗ (VDD =0V ) Symbol VSS VI VIOSC ΣIVSS Topr Tstg Tsol P D Value -2.0 to 0.5 VSS -0.3 to 0.5 VS1-0.3 to 0.5 -20 to 70 -65 to 150 260°C, 10sec (lead section) 250 Unit V V V mA mW ∗1: ∗2: The permissible total output current is the sum total of the current (average current) that simultaneously flows from the output pins (or is draw in). In case of plastic package. G Recommended Operating Conditions S1C60N08 Condition Supply voltage Oscillation frequency (Ta=-20 to 70°C ) Symbol V SS fOSC1 Unit V kHz kHz Max. -1.8 Typ. -3.0 32.768 38.400 Min. -3.5 Remark V DD =0V Either one is selected S1C60L08 Condition Supply voltage Oscillation frequency ∗1: ∗2: (Ta=-20 to 70°C ) Symbol VSS fOSC1 Unit V V V kHz kHz Max. -1.1 -0.9 -1.2 Typ. -1.5 -1.5 -1.5 32.768 38.400 Min. -1.7 -1.7 -1.7 When switching to heavy load protection mode. The possibility of LCD panel display differs depending on the characteristics of the LCD panel. Remark V DD =0V VDD =0V, with software control ∗1 VDD =0V, when analog comparator is used Either one is selected S1C60A08/60R08 Condition Supply voltage Oscillation frequency (1) Oscillation frequency (2) (Ta=-20 to 70°C ) Symbol V SS fOSC1 fOSC3 Unit V kHz kHz kHz Max. -2.2 600 Typ. -3.0 32.768 38.400 500 Min. -3.5 Remark V DD =0V Either one is selected duty 50±5%, VSS =-2.2 to -3.5V ∗1: -1.8V when the S1C60R08 is used as the S1C60N08.

High level input voltage (1) High level input voltage (2) Low level input voltage (1) Low level input voltage (2) High level input current (1) High level input current (2) High level input current (3) Low level input current High level output current (1) High level output current (2) Low level output current (1) Low level output current (2) Common output current Segment output current (during LCD output) Segment output current (during DC output) (Unless otherwise specified: V DD =0V, VSS =-3.0V, fOSC1 =32.768kHz, Ta=25°C, VS1/VL1–VL3 are internal voltage, C1–C 5=0.1µF) Symbol VIH1 VIH2 VIL1 VIL2 IIH1 IIH2 IIH3 IIL IOH1 IOH2 IOL1 IOL2 IOH3 IOL3 IOH4 IOL4 IOH5 IOL5 Unit V V V V µA µA µA µA mA mA mA mA µA µA µA µA µA µA Max. 0.8·VSS 0.9·VSS 0.5 100 -1.8 -0.9 -200 Typ.Min. 0.2·VSS 0.1·VSS VSS VSS -0.5 6.0 3.0 200 Condition K00–03, K10, K20–23, P00–03, P10–13 SIN, (SDA) ∗ SCLK, RESET, TEST, (OTPRST) ∗1 K00–03, K10, K20–23, P00–03, P10–13 SIN, (SDA) ∗1 SCLK, RESET, TEST, (OTPRST) ∗1 VIH1=0V K00–03, K10, K20–23, P00–03, P10–13 No pull-down SIN, SCLK, AMPP, AMPM (SDA) ∗1 VIH2=0V K00–03, K10, K20–23 With pull-down SIN, SCLK V IH3=0V P00–03, P10–13, RESET, TEST With pull-down (OTPRST) ∗1 VIL=VSS K00–03, K10, K20–23, P00–03, P10–13 SIN, SCLK, AMPP, AMPM, RESET, TEST (OTPRST), (SDA) ∗ VOH1 =0.1·VSS R10, R11, R13 VOH2 =0.1·VSS R00–03, R12, P00–03, P10–13, SOUT SCLK, (SDA), (ERROUT), (SCL) ∗ VOL1 =0.9·VSS R10, R11, R13 VOL2 =0.9·VSS R00–03, R12, P00–03, P10–13, SOUT SCLK, (SDA), (ERROUT), (SCL) ∗ VOH3 =-0.05V COM0–3 VOL3 =VL3+0.05V VOH4 =-0.05V SEG0–47 VOL4 =VL3+0.05V VOH5 =0.1·VSS SEG0–47 VOL5 =0.9·VSS ∗1: ( ) indicate the S1C60R08 pins. S1C60L08 Characteristic High level input voltage (1) High level input voltage (2) Low level input voltage (1) Low level input voltage (2) High level input current (1) High level input current (2) High level input current (3) Low level input current High level output current (1) High level output current (2) Low level output current (1) Low level output current (2) Common output current Segment output current (during LCD output) Segment output current (during DC output) (Unless otherwise specified: V DD =0V, VSS =-1.5V, fOSC1 =32.768kHz, Ta=25°C, VS1/VL1–VL3 are internal voltage, C1–C 5=0.1µF) Symbol VIH1 VIH2 VIL1 VIL2 IIH1 IIH2 IIH3 IIL IOH1 IOH2 IOL1 IOL2 IOH3 IOL3 IOH4 IOL4 IOH5 IOL5 Unit V V V V µA µA µA µA µA µA µA µA µA µA µA µA µA µA Max. 0.8·VSS 0.9·VSS 0.5 -300 -150 -100 Typ.Min. 0.2·VSS 0.1·VSS VSS VSS -0.5 1400 700 100 Condition K00–03, K10, K20–23, P00–03, P10–13 SIN SCLK, RESET, TEST K00–03, K10, K20–23, P00–03, P10–13 SIN SCLK, RESET, TEST V IH1=0V K00–03, K10, K20–23, P00–03, P10–13 No pull-down SIN, SCLK AMPP, AMPM VIH2=0V K00–03, K10, K20–23 With pull-down SIN, SCLK V IH3=0V P00–03, P10–13 With pull-down RESET, TEST V IL=VSS K00–03, K10, K20–23, P00–03, P10–13 SIN, SCLK, AMPP, AMPM RESET, TEST V OH1 =0.1·VSS R10, R11, R13 VOH2 =0.1·VSS R00–03, R12, P00–03, P10–13 SOUT, SCLK V OL1 =0.9·VSS R10, R11, R13 VOL2 =0.9·VSS R00–03, R12, P00–03, P10–13 SOUT, SCLK V OH3 =-0.05V COM0–3 VOL3 =VL3+0.05V VOH4 =-0.05V SEG0–47 VOL4 =VL3+0.05V VOH5 =0.1·VSS SEG0–47 VOL5 =0.9·VSS

G Analog Circuit Characteristics and Current Consumption S1C60N08 (Normal Operating Mode) Characteristic LCD drive voltage BLD voltage ∗1 BLD circuit response time Sub-BLD voltage Sub-BLD circuit response time Analog comparator input voltage Analog comparator offset voltage Analog comparator response time Current consumption ∗1: ∗2: (Unless otherwise specified: V DD =0V, VSS =-3.0V, fOSC1 =32.768kHz, Ta=25°C, CG =25pF, VS1/VL1–VL3 are internal voltage, C1–C 5=0.1µF) Symbol VL1 VL2 VL3 VB0 VB1 VB2 VB3 VB4 VB5 VB6 VB7 tB VBS tBS VIP VIM VOF tAMP IOP Unit V V V V V V V V V V V µsec V µsec V mV msec µA µA Max. 1/2·V ×0.9 -1.90 3/2·VL2 ×0.9 -2.05 -2.10 -2.15 -2.20 -2.25 -2.30 -2.35 -2.40 100 -2.25 100 V DD -0.9 2.0 4.0 Typ. -2.10 -2.20 -2.25 -2.30 -2.35 -2.40 -2.45 -2.50 -2.55 -2.40 1.0 2.2 Min. 1/2·V - 0.1 -2.30 3/2·VL2 - 0.1 -2.35 -2.40 -2.45 -2.50 -2.55 -2.60 -2.65 -2.70 -2.55 V SS +0.3 The relationships among VB0–VB7 are VB0>VB1>VB2>...VB5>VB6>VB7. The BLD circuit, sub-BLD circuit and analog comparator are in the OFF status. Condition Connect 1 MΩ load resistor between VDD and VL1 (without panel load) Connect 1 MΩ load resistor between VDD and VL2 (without panel load) Connect 1 MΩ load resistor between VDD and VL3 (without panel load) BLC="0" BLC="1" BLC="2" BLC="3" BLC="4" BLC="5" BLC="6" BLC="7" Non-inverted input (AMPP) Inverted input (AMPM) V IP=-1.5V VIM=VIP±15mV During HALT Without During operation ∗2 panel load S1C60N08 (Heavy Load Protection Mode) Characteristic LCD drive voltage BLD voltage ∗1 BLD circuit response time Sub-BLD voltage Sub-BLD circuit response time Analog comparator input voltage Analog comparator offset voltage Analog comparator response time Current consumption ∗1: ∗2: (Unless otherwise specified: V DD =0V, VSS =-3.0V, fOSC1 =32.768kHz, Ta=25°C, CG =25pF, VS1/VL1–VL3 are internal voltage, C1–C 5=0.1µF) Symbol VL1 VL2 VL3 VB0 VB1 VB2 VB3 VB4 VB5 VB6 VB7 tB VBS tBS VIP VIM VOF tAMP IOP Unit V V V V V V V V V V V µsec V µsec V mV msec µA µA Max. 1/2·V ×0.9 -1.90 3/2·VL2 ×0.9 -2.05 -2.10 -2.15 -2.20 -2.25 -2.30 -2.35 -2.40 100 -2.25 100 V DD -0.9 Typ. -2.10 -2.20 -2.25 -2.30 -2.35 -2.40 -2.45 -2.50 -2.55 -2.40 Min. 1/2·V - 0.1 -2.30 3/2·VL2 - 0.1 -2.35 -2.40 -2.45 -2.50 -2.55 -2.60 -2.65 -2.70 -2.55 V SS +0.3 The relationships among VB0–VB7 are VB0>VB1>VB2>...VB5>VB6>VB7. The BLD circuit and sub-BLD circuit are in the ON status (HLMOD="1", BLS="0"). The analog comparator is in the OFF status. Condition Connect 1 MΩ load resistor between V DD and VL1 (without panel load) Connect 1 MΩ load resistor between VDD and VL2 (without panel load) Connect 1 MΩ load resistor between VDD and VL3 (without panel load) BLC="0" BLC="1" BLC="2" BLC="3" BLC="4" BLC="5" BLC="6" BLC="7" Non-inverted input (AMPP) Inverted input (AMPM) V IP=-1.5V VIM=VIP±15mV During HALT Without During operation ∗2 panel load

S1C60L08 (Normal Operating Mode) Characteristic LCD drive voltage BLD voltage ∗1 BLD circuit response time Sub-BLD voltage Sub-BLD circuit response time Analog comparator input voltage Analog comparator offset voltage Analog comparator response time Current consumption ∗1: ∗2: (Unless otherwise specified: V DD =0V, VSS =-1.5V, fOSC1 =32.768kHz, Ta=25°C, CG =25pF, VS1/VL1–VL3 are internal voltage, C1–C 5=0.1µF) Symbol VL1 VL2 VL3 VB0 VB1 VB2 VB3 VB4 VB5 VB6 VB7 tB VBS tBS VIP VIM VOF tAMP IOP Unit V V V V V V V V V V V µsec V µsec V mV msec µA µA Max. -0.95 2·V ×0.9 3·VL1 ×0.9 -0.95 -1.00 -1.05 -1.10 -1.15 -1.20 -1.25 -1.30 100 -1.10 100 V DD -0.9 2.0 4.0 Typ. -1.05 -1.05 -1.10 -1.15 -1.20 -1.25 -1.30 -1.35 -1.40 -1.20 1.0 2.2 Min. -1.15 2·V - 0.1 3·VL1 - 0.1 -1.15 -1.20 -1.25 -1.30 -1.35 -1.40 -1.45 -1.50 -1.30 V SS +0.3 The relationships among VB0–VB7 are VB0>VB1>VB2>...VB5>VB6>VB7. The BLD circuit, sub-BLD circuit and analog comparator are in the OFF status. Condition Connect 1 MΩ load resistor between VDD and VL1 (without panel load) Connect 1 MΩ load resistor between VDD and VL2 (without panel load) Connect 1 MΩ load resistor between VDD and VL3 (without panel load) BLC="0" BLC="1" BLC="2" BLC="3" BLC="4" BLC="5" BLC="6" BLC="7" Non-inverted input (AMPP) Inverted input (AMPM) V IP=-1.1V VIM=VIP±30mV During HALT Without During operation ∗2 panel load S1C60L08 (Heavy Load Protection Mode) Max. -0.95 2·VL1 ×0.85 3·VL1 ×0.85 -0.95 -1.00 -1.05 -1.10 -1.15 -1.20 -1.25 -1.30 100 -1.10 100 V DD -0.9 Typ. -1.05 -1.05 -1.10 -1.15 -1.20 -1.25 -1.30 -1.35 -1.40 -1.20 6.5 8.5 Min. -1.15 2·V - 0.1 3·VL1 - 0.1 -1.15 -1.20 -1.25 -1.30 -1.35 -1.40 -1.45 -1.50 -1.30 V SS +0.3 Characteristic LCD drive voltage BLD voltage ∗1 BLD circuit response time Sub-BLD voltage Sub-BLD circuit response time Analog comparator input voltage Analog comparator offset voltage Analog comparator response time Current consumption ∗1: ∗2: (Unless otherwise specified: V DD =0V, VSS =-1.5V, fOSC1 =32.768kHz, Ta=25°C, CG =25pF, VS1/VL1–VL3 are internal voltage, C1–C 5=0.1µF) Symbol VL1 VL2 VL3 VB0 VB1 VB2 VB3 VB4 VB5 VB6 VB7 tB VBS tBS VIP VIM VOF tAMP IOP Unit V V V V V V V V V V V µsec V µsec V mV msec µA µA The relationships among V B0–VB7 are VB0>VB1>VB2>...VB5>VB6>VB7. The BLD circuit and sub-BLD circuit are in the ON status (HLMOD="1", BLS="0"). The analog comparator is in the OFF status. Condition Connect 1 MΩ load resistor between V DD and VL1 (without panel load) Connect 1 MΩ load resistor between VDD and VL2 (without panel load) Connect 1 MΩ load resistor between VDD and VL3 (without panel load) BLC="0" BLC="1" BLC="2" BLC="3" BLC="4" BLC="5" BLC="6" BLC="7" Non-inverted input (AMPP) Inverted input (AMPM) V IP=-1.1V VIM=VIP±30mV During HALT Without During operation ∗2 panel load

S1C60A08 (Normal Operating Mode) Characteristic LCD drive voltage BLD voltage ∗1 BLD circuit response time Sub-BLD voltage Sub-BLD circuit response time Analog comparator input voltage Analog comparator offset voltage Analog comparator response time Current consumption ∗1: ∗2: (Unless otherwise specified: V DD =0V, VSS =-3.0V, fOSC1 =32.768kHz, Ta=25°C, CG =25pF, VS1/VL1–VL3 are internal voltage, C1–C 5=0.1µF) Symbol VL1 VL2 VL3 VB0 VB1 VB2 VB3 VB4 VB5 VB6 VB7 tB VBS tBS VIP VIM VOF tAMP IOP Unit V V V V V V V V V V V µsec V µsec V mV msec µA µA µA Max. -0.95 2·V ×0.9 3·VL1 ×0.9 -2.05 -2.10 -2.15 -2.20 -2.25 -2.30 -2.35 -2.40 100 -2.25 100 V DD -0.9 2.0 5.0 Typ. -1.05 -2.20 -2.25 -2.30 -2.35 -2.40 -2.45 -2.50 -2.55 -2.40 1.1 3.0 Min. -1.15 2·V - 0.1 3·VL1 - 0.1 -2.35 -2.40 -2.45 -2.50 -2.55 -2.60 -2.65 -2.70 -2.55 V SS +0.3 The relationships among VB0–VB7 are VB0>VB1>VB2>...VB5>VB6>VB7. The BLD circuit, sub-BLD circuit and analog comparator are in the OFF status. Condition Connect 1 MΩ load resistor between VDD and VL1 (without panel load) Connect 1 MΩ load resistor between VDD and VL2 (without panel load) Connect 1 MΩ load resistor between VDD and VL3 (without panel load) BLC="0" BLC="1" BLC="2" BLC="3" BLC="4" BLC="5" BLC="6" BLC="7" Non-inverted input (AMPP) Inverted input (AMPM) V IP=-1.5V VIM=VIP±15mV During HALT Without During operation ∗2 panel load During operation at 500kHz ∗2 S1C60A08 (Heavy Load Protection Mode) Characteristic LCD drive voltage BLD voltage ∗1 BLD circuit response time Sub-BLD voltage Sub-BLD circuit response time Analog comparator input voltage Analog comparator offset voltage Analog comparator response time Current consumption ∗1: ∗2: (Unless otherwise specified: V DD =0V, VSS =-3.0V, fOSC1 =32.768kHz, Ta=25°C, CG =25pF, VS1/VL1–VL3 are internal voltage, C1–C 5=0.1µF) Symbol VL1 VL2 VL3 VB0 VB1 VB2 VB3 VB4 VB5 VB6 VB7 tB VBS tBS VIP VIM VOF tAMP IOP Unit V V V V V V V V V V V µsec V µsec V mV msec µA µA µA Max. -0.95 2·V ×0.9 3·VL1 ×0.9 -2.05 -2.10 -2.15 -2.20 -2.25 -2.30 -2.35 -2.40 100 -2.25 100 V DD -0.9 Typ. -1.05 -2.20 -2.25 -2.30 -2.35 -2.40 -2.45 -2.50 -2.55 -2.40 6.5 8.5 Min. -1.15 2·V - 0.1 3·VL1 - 0.1 -2.35 -2.40 -2.45 -2.50 -2.55 -2.60 -2.65 -2.70 -2.55 V SS +0.3 The relationships among VB0–VB7 are VB0>VB1>VB2>...VB5>VB6>VB7. The BLD circuit and sub-BLD circuit are in the ON status (HLMOD="1", BLS="0"). The analog comparator is in the OFF status. Condition Connect 1 MΩ load resistor between V DD and VL1 (without panel load) Connect 1 MΩ load resistor between VDD and VL2 (without panel load) Connect 1 MΩ load resistor between VDD and VL3 (without panel load) BLC="0" BLC="1" BLC="2" BLC="3" BLC="4" BLC="5" BLC="6" BLC="7" Non-inverted input (AMPP) Inverted input (AMPM) V IP=-1.5V VIM=VIP±15mV During HALT Without During operation ∗2 panel load During operation at 500kHz ∗2

S1C60R08 (Normal Operating Mode) Target: S1C60N08 Characteristic LCD drive voltage BLD voltage ∗1 BLD circuit response time Sub-BLD voltage Sub-BLD circuit response time Analog comparator input voltage Analog comparator offset voltage Analog comparator response time Current consumption ∗1: ∗2: (Unless otherwise specified: V DD =0V, VSS =-3.0V, fOSC1 =32.768kHz, Ta=25°C, CG =25pF, VS1/VL1–VL3 are internal voltage, C1–C 5=0.1µF) Symbol VL1 VL2 VL3 VB0 VB1 VB2 VB3 VB4 VB5 VB6 VB7 tB VBS tBS VIP VIM VOF tAMP IOP Unit V V V V V V V V V V V µsec V µsec V mV msec µA µA Max. 1/2·V ×0.9 -1.90 3/2·VL2 ×0.9 -2.05 -2.10 -2.15 -2.20 -2.25 -2.30 -2.35 -2.40 100 -2.25 100 V DD -0.9 2.0 9.0 Typ. -2.10 -2.20 -2.25 -2.30 -2.35 -2.40 -2.45 -2.50 -2.55 -2.40 1.0 6.5 Min. 1/2·V - 0.1 -2.30 3/2·VL2 - 0.1 -2.35 -2.40 -2.45 -2.50 -2.55 -2.60 -2.65 -2.70 -2.55 V SS +0.3 The relationships among VB0–VB7 are VB0>VB1>VB2>...VB5>VB6>VB7. The BLD circuit, sub-BLD circuit and analog comparator are in the OFF status. Condition Connect 1 MΩ load resistor between VDD and VL1 (without panel load) Connect 1 MΩ load resistor between VDD and VL2 (without panel load) Connect 1 MΩ load resistor between VDD and VL3 (without panel load) BLC="0" BLC="1" BLC="2" BLC="3" BLC="4" BLC="5" BLC="6" BLC="7" Non-inverted input (AMPP) Inverted input (AMPM) V IP=-1.5V VIM=VIP±15mV During HALT Without During operation ∗2 panel load S1C60R08 (Heavy Load Protection Mode) Target: S1C60N08 Characteristic LCD drive voltage BLD voltage ∗1 BLD circuit response time Sub-BLD voltage Sub-BLD circuit response time Analog comparator input voltage Analog comparator offset voltage Analog comparator response time Current consumption ∗1: ∗2: (Unless otherwise specified: V DD =0V, VSS =-3.0V, fOSC1 =32.768kHz, Ta=25°C, CG =25pF, VS1/VL1–VL3 are internal voltage, C1–C 5=0.1µF) Symbol VL1 VL2 VL3 VB0 VB1 VB2 VB3 VB4 VB5 VB6 VB7 tB VBS tBS VIP VIM VOF tAMP IOP Unit V V V V V V V V V V V µsec V µsec V mV msec µA µA Max. 1/2·V ×0.9 -1.90 3/2·VL2 ×0.9 -2.05 -2.10 -2.15 -2.20 -2.25 -2.30 -2.35 -2.40 100 -2.25 100 V DD -0.9 Typ. -2.10 -2.20 -2.25 -2.30 -2.35 -2.40 -2.45 -2.50 -2.55 -2.40 6.5 11.5 Min. 1/2·V - 0.1 -2.30 3/2·VL2 - 0.1 -2.35 -2.40 -2.45 -2.50 -2.55 -2.60 -2.65 -2.70 -2.55 V SS +0.3 The relationships among VB0–VB7 are VB0>VB1>VB2>...VB5>VB6>VB7. The BLD circuit and sub-BLD circuit are in the ON status (HLMOD="1", BLS="0"). The analog comparator is in the OFF status. Condition Connect 1 MΩ load resistor between V DD and VL1 (without panel load) Connect 1 MΩ load resistor between VDD and VL2 (without panel load) Connect 1 MΩ load resistor between VDD and VL3 (without panel load) BLC="0" BLC="1" BLC="2" BLC="3" BLC="4" BLC="5" BLC="6" BLC="7" Non-inverted input (AMPP) Inverted input (AMPM) V IP=-1.5V VIM=VIP±15mV During HALT Without During operation ∗2 panel load

S1C60R08 (Normal Operating Mode) Target: S1C60A08 Characteristic LCD drive voltage BLD voltage ∗1 BLD circuit response time Sub-BLD voltage Sub-BLD circuit response time Analog comparator input voltage Analog comparator offset voltage Analog comparator response time Current consumption ∗1: ∗2: (Unless otherwise specified: V DD =0V, VSS =-3.0V, fOSC1 =32.768kHz, Ta=25°C, CG =25pF, VS1/VL1–VL3 are internal voltage, C1–C 5=0.1µF) Symbol VL1 VL2 VL3 VB0 VB1 VB2 VB3 VB4 VB5 VB6 VB7 tB VBS tBS VIP VIM VOF tAMP IOP Unit V V V V V V V V V V V µsec V µsec V mV msec µA µA µA Max. -0.95 2·V ×0.9 3·VL1 ×0.9 -2.05 -2.10 -2.15 -2.20 -2.25 -2.30 -2.35 -2.40 100 -2.25 100 V DD -0.9 2.0 150 Typ. -1.05 -2.20 -2.25 -2.30 -2.35 -2.40 -2.45 -2.50 -2.55 -2.40 1.1 7.5 115 Min. -1.15 2·V - 0.1 3·VL1 - 0.1 -2.35 -2.40 -2.45 -2.50 -2.55 -2.60 -2.65 -2.70 -2.55 V SS +0.3 The relationships among VB0–VB7 are VB0>VB1>VB2>...VB5>VB6>VB7. The BLD circuit, sub-BLD circuit and analog comparator are in the OFF status. Condition Connect 1 MΩ load resistor between VDD and VL1 (without panel load) Connect 1 MΩ load resistor between VDD and VL2 (without panel load) Connect 1 MΩ load resistor between VDD and VL3 (without panel load) BLC="0" BLC="1" BLC="2" BLC="3" BLC="4" BLC="5" BLC="6" BLC="7" Non-inverted input (AMPP) Inverted input (AMPM) V IP=-1.5V VIM=VIP±15mV During HALT Without During operation ∗2 panel load During operation at 500kHz ∗2 S1C60R08 (Heavy Load Protection Mode) Target: S1C60A08 Characteristic LCD drive voltage BLD voltage ∗1 BLD circuit response time Sub-BLD voltage Sub-BLD circuit response time Analog comparator input voltage Analog comparator offset voltage Analog comparator response time Current consumption ∗1: ∗2: (Unless otherwise specified: V DD =0V, VSS =-3.0V, fOSC1 =32.768kHz, Ta=25°C, CG =25pF, VS1/VL1–VL3 are internal voltage, C1–C 5=0.1µF) Symbol VL1 VL2 VL3 VB0 VB1 VB2 VB3 VB4 VB5 VB6 VB7 tB VBS tBS VIP VIM VOF tAMP IOP Unit V V V V V V V V V V V µsec V µsec V mV msec µA µA µA Max. -0.95 2·V ×0.9 3·VL1 ×0.9 -2.05 -2.10 -2.15 -2.20 -2.25 -2.30 -2.35 -2.40 100 -2.25 100 V DD -0.9 160 Typ. -1.05 -2.20 -2.25 -2.30 -2.35 -2.40 -2.45 -2.50 -2.55 -2.40 6.5 12.5 120 Min. -1.15 2·V - 0.1 3·VL1 - 0.1 -2.35 -2.40 -2.45 -2.50 -2.55 -2.60 -2.65 -2.70 -2.55 V SS +0.3 The relationships among VB0–VB7 are VB0>VB1>VB2>...VB5>VB6>VB7. The BLD circuit and sub-BLD circuit are in the ON status (HLMOD="1", BLS="0"). The analog comparator is in the OFF status. Condition Connect 1 MΩ load resistor between V DD and VL1 (without panel load) Connect 1 MΩ load resistor between VDD and VL2 (without panel load) Connect 1 MΩ load resistor between VDD and VL3 (without panel load) BLC="0" BLC="1" BLC="2" BLC="3" BLC="4" BLC="5" BLC="6" BLC="7" Non-inverted input (AMPP) Inverted input (AMPM) V IP=-1.5V VIM=VIP±15mV During HALT Without During operation ∗2 panel load During operation at 500kHz ∗2

G Oscillation Characteristics Oscillation characteristics will vary according to different conditions (elements used, boad pattern). Use the following char- acteristics are as reference values. S1C60N08/60R08 (OSC1 Crystal Oscillation) Characteristic Oscillation start voltage Oscillation stop voltage Built-in capacitance (drain) Frequency/voltage deviation Frequency/IC deviation Frequency adjustment range Harmonic oscillation start voltage Permitted leak resistance Symbol Vsta Vstp C D ∆f/∆V ∆f/∆IC ∆f/∆C G Vhho R leak Unit V V pF ppm ppm ppm V M Ω Max. -3.5 Typ. Min. -1.8 -1.8 -10 200 Condition tsta≤5sec (VSS ) tstp≤10sec (VSS ) Including the parasitic capacitance inside the chip VSS =-1.8 to -3.5V C G =5 to 25pF (VSS ) Between OSC1 and VDD (Unless otherwise specified: VDD =0V, VSS =-3.0V, Crystal: Q13MC146, CG =25pF, CD =built-in, Ta=25°C) S1C60L08 (OSC1 Crystal Oscillation) Characteristic Oscillation start voltage Oscillation stop voltage Built-in capacitance (drain) Frequency/voltage deviation Frequency/IC deviation Frequency adjustment range Harmonic oscillation start voltage Permitted leak resistance ∗1: Symbol Vsta Vstp C D ∆f/∆V ∆f/∆IC ∆f/∆C G Vhho R leak Unit V V pF ppm ppm ppm V M Ω Max. -1.7 Typ. Min. -1.1 -1.1 (-0.9) -10 200 Parentheses indicate value for operation in heavy load protection mode. Condition tsta≤5sec (VSS ) tstp≤10sec (VSS ) Including the parasitic capacitance inside the chip C G =5 to 25pF (VSS ) Between OSC1 and VDD (Unless otherwise specified: VDD =0V, VSS =-1.5V, Crystal: Q13MC146, CG =25pF, CD =built-in, Ta=25°C) S1C60A08 (OSC1 Crystal Oscillation) Characteristic Oscillation start voltage Oscillation stop voltage Built-in capacitance (drain) Frequency/voltage deviation Frequency/IC deviation Frequency adjustment range Harmonic oscillation start voltage Permitted leak resistance Symbol Vsta Vstp C D ∆f/∆V ∆f/∆IC ∆f/∆C G Vhho R leak Unit V V pF ppm ppm ppm V M Ω Max. -3.5 Typ. Min. -2.2 -2.2 -10 200 Condition tsta≤5sec (VSS ) tstp≤10sec (VSS ) Including the parasitic capacitance inside the chip VSS =-2.2 to -3.5V C G =5 to 25pF (VSS ) Between OSC1 and VDD (Unless otherwise specified: VDD =0V, VSS =-3.0V, Crystal: Q13MC146, CG =25pF, CD =built-in, Ta=25°C) S1C60A08/60R08 (OSC3 CR Oscillation) Characteristic Oscillation frequency dispersion Oscillation start voltage Oscillation start time Oscillation stop voltage Symbol f OSC3 Vsta tsta Vstp Unit V msec V Max. Typ. 480kHz Min. -30 -2.2 -2.2 Condition (VSS ) VSS =-2.2 to -3.5V (VSS ) (Unless otherwise specified: VDD =0V, VSS =-3.0V, RCR =82kΩ , Ta=25°C) S1C60A08/60R08 (OSC3 Ceramic Oscillation) Characteristic Oscillation start voltage Oscillation start time Oscillation stop voltage Symbol Vsta tsta Vstp Unit V msec V Max. Typ.Min. -2.2 -2.2 Condition (VSS ) VSS =-2.2 to -3.5V (VSS ) (Unless otherwise specified: VDD =0V, VSS =-3.0V, Ceramic oscillator: 500kHz, CGC =C DC =100pF, Ta=25°C)

I BASIC EXTERNAL CONNECTION DIAGRAM S1C60N08 and S1C60L08 K00 K03 K10 K20 K23 P00 P03 P10 P13 SIN SOUT SCLK AMPM AMPP R00 R03 R11 (LAMP) R12 (FOUT) SEG0 SEG47 COM0 COM3 R10 (BZ) R13 (BZ) CB CA VL1 VL2 VL3 VDD OSC1 OSC2 VS1 OSC3 OSC4 RESET TEST VSS Lamp Piezo C 1 C 5 N.C. 3.0 V (S1C60N08) or

1.5 V (S1C60L08)

N.C. C P C GX X'talS1C60N08 S1C60L08 LCD panel I/O SIO O I X'tal C GX C 1 C 2 C 3 C 4 C 5 C P R A1 R A2 Crystal oscillator Trimmer capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Protection resistor Protection resistor 32.768 kHz or 38.400 kHz, C I = 35 kΩ 5–25 pF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 3.3 µF 100 Ω 100 Ω R13 (BZ) R10 (BZ) R A2 When the piezoelectric buzzer is driven directly R A1 Piezo [The potential of the substrate (back of the chip) is VDD .] Capacitors (C2–C 4) are connected. Connection depending on power supply and LCD panel specification. Note: The above tables are simply an example, and are not guaranteed to work.

R11 (LAMP) R12 (FOUT) SEG0 SEG47 COM0 COM3 R10 (BZ) R13 (BZ) CB CA VL1 VL2 VL3 VDD OSC1 OSC2 VS1 OSC3 OSC4 RESET TEST VSS Lamp Piezo C 1 C 5 CR C GC R CR C DC 3.0 V C P C GX X'tal S1C60A08 LCD panel I/O SIO O I X'tal C GX CR C GC C DC R CR C 1 C 2 C 3 C 4 C 5 C P R A1 R A2 Crystal oscillator Trimmer capacitor Ceramic oscillator Gate capacitor Drain capacitor Resistor for CR oscillation Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Protection resistor Protection resistor 32.768 kHz or 38.400 kHz, C I = 35 kΩ 5–25 pF 500 kHz 100 pF 100 pF 82 kΩ 0.1 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 3.3 µF 100 Ω 100 Ω R13 (BZ) R10 (BZ) R A2 When the piezoelectric buzzer is driven directly R A1 Piezo ∗1 Ceramic oscillation ∗2 CR oscillation [The potential of the substrate (back of the chip) is VDD.] Capacitors (C2–C 4) are connected. Connection depending on power supply and LCD panel specification. Note: The above tables are simply an example, and are not guaranteed to work.

S1C60R08 (Target for S1C60N08) K00 K03 K10 K20 K23 P00 P03 P10 P13 SIN SOUT SCLK OTPRST AMPM AMPP R11 (LAMP) R12 (FOUT) SEG0 SEG47 COM0 COM3 R10 (BZ) R13 (BZ) CB CA VL1 VL2 VL3 VDD OSC1 OSC2 VS1 OSC3 OSC4 RESET TEST VSS Lamp Piezo C 1 C 5 N.C. N.C. C P C GX X'talS1C60R08 LCD panel 3.0 V I/O SIO I X'tal C GX C 1 C 2 C 3 C 4 C 5 C P R A1 R A2 IC1 Crystal oscillator Trimmer capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Protection resistor Protection resistor Serial EEPROM 32.768 kHz or 38.400 kHz 5–25 pF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 3.3 µF 100 Ω 100 Ω R13 (BZ) R10 (BZ) R A2R A1 Piezo ERROUT SCL SDA V SS VCC NC SCL SDA IC1 When the piezoelectric buzzer is driven directly ∗: See "Serial EEPROM" [The potential of the substrate (back of the chip) is VDD.] Capacitors (C2–C 4) are connected. Connection depending on power supply and LCD panel specification. Note: The above tables are simply an example, and are not guaranteed to work.

S1C60R08 (Target for S1C60A08) K00 K03 K10 K20 K23 P00 P03 P10 P13 SIN SOUT SCLK OTPRST AMPM AMPP SEG0 SEG47 COM0 COM3 CB CA VL1 VL2 VL3 VDD OSC1 OSC2 VS1 OSC3 OSC4 RESET TEST VSS C 1 C 5 CR C GC R CR C DC 3.0 V C P C GX X'tal S1C60R08 LCD panel I/O SIO I R13 (BZ) R10 (BZ) R A2R A1 Piezo ∗1 Ceramic oscillation ∗2 CR oscillation R11 (LAMP) R12 (FOUT) R10 (BZ) R13 (BZ) Lamp Piezo ERROUT SCL SDA V SS VCC NC SCL SDA IC1 X'tal C GX CR C GC C DC R CR C 1 C 2 C 3 C 4 C 5 C P R A1 R A2 IC1 Crystal oscillator Trimmer capacitor Ceramic oscillator Gate capacitor Drain capacitor Resistor for CR oscillation Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Protection resistor Protection resistor Serial EEPROM 32.768 kHz or 38.400 kHz 5–25 pF 500 kHz 100 pF 100 pF 82 kΩ 0.1 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 3.3 µF 100 Ω 100 Ω When the piezoelectric buzzer is driven directly ∗: See "Serial EEPROM" [The potential of the substrate (back of the chip) is VDD.] Capacitors (C2–C 4) are connected. Connection depending on power supply and LCD panel specification. Note: The above tables are simply an example, and are not guaranteed to work.

20±0.1 25.6±0.4 5180 14±0.1 19.6±0.4 INDEX 0.3±0.1 301 100 812.7±0.10.26 3.4max 2.8 1.5 12° 0.15±0.05 0.65 Plastic QFP15-100pin 14±0.1 16±0.4 5175 14±0.1 16±0.4 INDEX 0.18 251 100 1.4±0.10.1 1.7max 0.5±0.2 10° 0.125 0.5 +0.1 –0.05 +0.05 –0.025 Unit: mm

G S1C60N08/60L08/60A08 Diagram of Pad Layout X(0, 0) Die No. Y 3.73 mm 3.74 mm 15101520 50 55 60 65 70 Chip thickness: 400 µm Pad opening: 95 µm G S1C60N08/60L08/60A08 Pad Coordinates No. Pad name AMPP AMPM K23 K22 K21 K20 K10 K03 K02 K01 K00 SIN SOUT SCLK P03 P02 P01 P00 P13 P12 P11 P10 R03 R02 R01 R00 R12 R11 R10 R13 V SS RESET X 1,294 1,164 1,034 904 774 644 514 384 254 124 -137 -267 -397 -527 -657 -787 -917 -1,048 -1,178 -1,308 -1,438 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 Y 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,686 1,556 1,426 1,296 1,166 1,036 812 682 457 327 No. Pad name OSC4 * OSC3 * V OSC2 OSC1 V DD VL3 VL2 VL1 CA CB COM3 COM2 COM1 COM0 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 X -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,415 -1,285 -1,155 -1,025 -895 -765 -635 -505 -375 -245 -115 145 275 405 535 665 Y 176 -84 -214 -344 -503 -633 -763 -893 -1,022 -1,153 -1,283 -1,413 -1,543 -1,673 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 No. Pad name SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 TEST SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 X 795 925 1,055 1,185 1,315 1,445 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 Y -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,621 -1,465 -1,310 -1,180 -1,050 -920 -790 -660 -530 -400 -270 -140 -10 120 250 380 510 640 770 900 1,030 1,160 1,290 1,420 1,550 1,680 Unit: µm ∗: S1C60A08 only

G S1C60R08 Diagram of Pad Layout Y X (0, 0) 7.00 mm 8.35 mm 1510152025 Die No. 55 60 65 70 75 100 Chip thickness: 400 µm Pad opening: 95 µm G S1C60R08 Pad Coordinates No. Pad name AMPP AMPM K23 K22 K21 K20 K10 K03 K02 K01 K00 SIN SOUT OTPRST SCLK P03 P02 P01 P00 SCL SDA P13 P12 P11 P10 R03 R02 R01 R00 R12 R11 R10 R13 V SS X 2,893 2,638 2,382 2,127 1,871 1,616 1,360 1,105 849 594 339 -85 -260 -438 -683 -863 -1,064 -1,275 -1,566 -1,821 -2,126 -2,405 -2,685 -2,978 -3,686 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 Y 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,090 2,787 2,657 2,527 2,288 2,064 1,599 1,470 No. Pad name REST OSC4 OSC3 V OSC2 OSC1 V DD VL3 VL2 VL1 CA CB ERROUT COM3 COM2 COM1 COM0 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 X -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -3,420 -3,116 -2,811 -2,507 -2,203 -1,899 -1,595 -1,290 -986 -682 -378 -74 230 534 838 1,142 1,446 Y 1,340 733 517 300 -576 -793 -958 -1,174 -1,391 -1,607 -1,824 -2,040 -2,241 -2,429 -2,645 -2,862 -3,088 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 No. 100 Pad name SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 TEST SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 X 1,751 2,055 2,359 2,663 2,967 3,272 3,661 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 Y -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,049 -2,590 -2,355 -2,119 -1,883 -1,647 -1,411 -1,175 -939 -703 -467 -231 240 476 712 948 1,184 1,420 1,656 1,892 2,128 2,364 2,600 2,836 Unit: µm

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NOTICE: No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. © Seiko Epson Corporation 2001 All right reserved. SEIKO EPSON CORPORATION ELECTRONIC DEVICES MARKETING DIVISION IC Marketing & Engineering Group ED International Marketing Department Europe & U.S.A. 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone : 042-587-5812 FAX : 042-587-5564 ED International Marketing Department Asia 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone : 042-587-5814 FAX : 042-587-5110 http://www.epson.co.jp/device/ I EPSON Electronic Devices Website Issue August, 2001 Printed in Japan L

Product Information

S1C60A08 specifications and overview.

Summary

4-bit Single Chip Microcomputer

Description

4-bit Single Chip Microcomputer

Source title S1C60A08 Datasheet(PDF) - Epson Company

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