S12744EJ4V0DS00

S12744EJ4V0DS00_15 RENESAS | Alldatasheet

Document overview

• Manufacturer or author: NEC Electronics Corporation/NEC Electronics Corporation
• PDF pages: 26

Technical content

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μPD3739

5000 PIXELS CCD LINEAR IMAGE SENSOR

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S12744EJ4V0DS00 (4th edition) Date Published October 2006 NS CP (K) Printed in Japan The mark '' <R>" shows major revised points. The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field. 1997

DESCRIPTION

The μ PD3739 is a CCD (Charge Coupled Device) linear image sens or which changes optical images to electrical signal. The μ PD3739 is a 2-output type CCD sensor with 2 rows of high-speed charge transfer register, which transfers the photo signal electrons of 5000 pixels separately in odd and ev en pixels. It is suitable for 400 dpi/A3 high-speed digital copiers, OCRs and high-end business facsimiles.

FEATURES

• Valid photocell : 5000 pixels
• Photocell’s pitch : 7 μ m
• High sensitivity : 9.0 V/lx •s TYP. (Light source: Daylight color fluorescent lamp)
• Low image lag : 1 % MAX.
• Peak response wavelength : 550 nm (green)
• Resolution : 16 dot/mm (400 dpi) A3 (297 × 420 mm) size (shorter side)
• Data rate : 40 MHz MAX. (20 MHz/1 output)
• Output type : 2 outputs out of phase (2 outputs in phase also supported)
• Power supply : +12 V
• Drive clock level : CMOS output under 5 V operation
• On-chip circuit : Automatic φ R level adjuster

ORDERING INFORMATION

μ PD3739D-A CCD linear image sensor 22-pin ceramic DIP (CERDIP) (10.16 mm (400)) Remark The μ PD3739D-A is a lead-free product. <R>

2 Data Sheet S12744EJ4V0DS

μ PD3739 BLOCK DIAGRAM 14 13 22 12 18 17 VOD 20VOUT2 (Even) 12 TG VOUT1 (Odd) GND 1L2 Automatic R level adjuster CCD analog shift register Transfer gate Photocell D32 S4999 S5000 D33 D34 Transfer gate CCD analog shift register 2L1 φφ φ φφ φφ φ φ

μ PD3739 PIN CONFIGURATION (Top View) CCD linear image sensor 22-pin ceramic DIP (CERDIP) (10.16 mm (400 mil)) μ PD3739D-A VOUT2 12 2 22 1 32 0 41 9 51 8 61 7 71 6 81 5 91 4 10 13 11 12 No connection No connection Output drain voltage Reset gate clock 2 Last stage shift register clock 1 No connection No connection Shift register clock 2 Shift register clock 1 Transfer gate clock Ground No connection Output signal 1 (Odd) No connection Reset gate clock 1 Last stage shift register clock 2 No connection No connection Shift register clock 2 Shift register clock 1 No connection GND VOUT1 NC NC NC NC TG NC NC 1L2 VOD Output signal 2 (Even) NC φ NC 22φ NC φR1φ 2L1φ 11φ φ φ φ Caution Connect the No connection pins (NC) to GND. PHOTOCELL STRUCTURE DIAGRAM 5 mμ 2 mμ 7 m μ Channel stopper Aluminum shield

4 Data Sheet S12744EJ4V0DS

μ PD3739 ABSOLUTE MAXIMUM RATINGS (TA = +25°C) Parameter Symbol Ratings Unit Output drain voltage V OD –0.3 to +15 V Shift register clock voltage V φ 1, Vφ 2 –0.3 to +15 V Reset gate clock voltage V φ R1, Vφ R2 –0.3 to +15 V Transfer gate clock voltage V φ TG –0.3 to +15 V Operating ambient temperature Note T A –25 to +55 ˚C Storage temperature T stg –40 to +100 ˚C Note Use at the condition wi thout dew condensation. Caution Product quality may suffer if the absolute m aximum rating is exceeded ev en momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. RECOMMENDED OPERATING CONDITIONS (TA = –25 to +55°C) Parameter Symbol Conditions MIN. TYP. MAX. Unit Output drain voltage V OD 11.4 12.0 12.6 V Shift register clock high level V φ 1H, Vφ 2H 4.5 5.0 5.5 V Shift register clock low level V φ 1L, Vφ 2L –0.3 0 +0.5 V Reset gate clock high level V φ R1H, Vφ R2H Note 4.5 5.0 5.5 V Reset gate clock low level V φ R1L, Vφ R2L Note –0.3 0 +0.5 V Capacitance of reset gate clock pin external capacitor CEXTφ R Non-polar type 800 1000 1200 pF Transfer gate clock high level V φ TGH 4.5 5.0 5.5 V Transfer gate clock low level V φ TGL –0.3 0 +0.5 V Data rate 2f φ R1, 2fφ R2 0.5 2 40 MHz Note Input the reset gate clocks 1 and 2 ( φ R1, φ R2) to pins 5 and 18, respectively, via an input resistor and a capacitor. Use of a capacitor is indispensable. Refer to APPLICATION CIRCUIT EXAMPLE for the connection method. The reset gate clock high level and low level at the IC pins (after passing through the external capacitor) varies according to the IC, due to the on-chip automatic φ R level adjuster. The recommended operating conditions of reset gate clocks 1, 2 ( φ R1, φ R2) in the table above are for signals applied to the external capacitor. Remark φ 1 in the above tables represents φ 11, φ 12 and φ 1L2. φ 2 represents φ 21, φ 22 and φ 2L1.

μ PD3739

ELECTRICAL CHARACTERISTICS

TA = +25°C, VOD = 12 V, fφ 1 = 1 MHz, data rate = 2 MHz, storage time = 10 ms light source: 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm), input signal clock = 5 Vp-p Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Saturation voltage V sat 1.0 1.5 — V Saturation exposure SE Daylight colo r fluorescent lamp — 0.17 — lx•s Photo response non-uniformity PRNU V OUT = 500 mV — 4 10 % Average dark signal ADS Light shielding — 0.3 3.0 mV Dark signal non-uniformity DSNU Light shielding 0 4.0 6.0 mV Power consumption P W — 200 400 mW Output impedance Z O — 0.2 0.5 k Ω Response R F Daylight color fluorescent lamp 7.2 9.0 10.8 V/Ix•s Response peak — 550 — nm Image lag IL V OUT = 1 V — 0.3 1.0 % Offset level Note 1 V OS 2.0 3.5 5.0 V Output fall delay time Note 2 t d V OUT = 1 V — 20 — ns Register imbalance RI V OUT = 500 mV 0 — 4.0 % Total transfer efficiency TTE V OUT = 500 mV, data rate = 40 MHz 92 98 — % Dynamic range DR1 V sat/DSNU — 375 — times DR2 V sat/σ — 2143 — times Reset feed-through noise Note 1 RFTN Light shielding 0 400 600 mV Random noise σ Light shielding — 0.7 — mV Notes 1. Refer to TIMING CHART 2, 5. 2. Typical value when the respective fall times of φ 1L2 and φ 2L1 are t11’, t41’ and t2’, t32’ (refer to TIMING CHART 2, 5 ). Note that V OUT1 and V OUT2 are the outputs of the two step s of emitter-follower shown in APPLICATION CIRCUIT EXAMPLE.

6 Data Sheet S12744EJ4V0DS

μ PD3739 INPUT PIN CAPACITANCE (TA = +25°C, VOD = 12 V) Parameter Symbol Pin name Pin No. MIN. TYP. MAX. Unit φ 11 10 250 350 500 pF Shift register clock pin capacitance 1 C φ 1 φ 12 13 250 350 500 pF φ 21 9 250 350 500 pF Shift register clock pin capacitance 2 C φ 2 φ 22 14 250 350 500 pF φ 1L2 17 40 50 100 pF Last stage shift register clock pin capacitance C φ L φ 2L1 6 40 50 100 pF φ R1 5 8 10 15 pF Reset gate clock pin capacitance C φ R φ R2 18 8 10 15 pF Transfer gate clock pin capacitance C φ TG φ TG 12 100 150 200 pF

μ PD3739 TIMING CHART 1 (Out of phase operation) TG 2L1 VOUT1 1L2 VOUT2 Note 5029 5031 5033 5035 5037 5030 5032 5034 5036 5038 Optical black (22 pixels) Invalid photocell (2 pixels) Invalid photocell (2 pixels) Valid photocell (5000 pixels) φ φ φφ φ φ φφ φ Note Input the φ R1 and φ R2 pulses continuously during this period, too.

8 Data Sheet S12744EJ4V0DS

μ PD3739 TIMING CHART 2 (Out of phase operation) 2L1 VOUT1 1L2 VOUT2 RFTN VOS 10 % 10 % 90 % 10 % 90 % 10 % 90 % 10 % 90 % 50 % 50 % t7 t1 t2 10 % 90 % 10 % 90 % 10 % 90 % 10 % 90 % 10 % td t14 t11’ t12’ t15 t16 t13 t17’ t12 t1’ t2’ t6 t4 t11 50 % 50 % 50 % 50 % 50 % 50 % t17 VOS RFTN t7’ td φφ φ φφ φφ φ

μ PD3739 TIMING CHART 3 (Out of phase operation) t21 t24 t23 t25 t22 90 % 50 % 50 %11, 12, 1L2 21, 22, 2L1 TG 10 % φ φφφ φφφ φ 11, φ 21 cross points φ 12, φ 22 cross points

2 V or more 2 V or more

φ φ φ φ φ 11, φ 2L1 cross points φ 1L2, φ 22 cross points

0.5 V or more

2 V or more

φ φ φ φ Remark Adjust cross points of ( φ 11, φ 21), (φ 12, φ 22), (φ 11, φ 2L1) and (φ 1L2, φ 22) with input resistance of each pin. Symbol MIN. TYP. MAX. Unit t1, t2, t11, t12 0 50 — ns t3, t13 15 50 — ns t4, t14 5 20 — ns t5, t6, t15, t16 0 20 — ns t7, t7’, t17, t17’ 25 — — ns t21, t22 0 50 — ns t23 1000 2000 5000 ns t24, t25 10 100 — ns

10 Data Sheet S12744EJ4V0DS

μ PD3739 TIMING CHART 4 (In phase operation) TG 2L1 VOUT1 1L2 5029 5031 5033 5035 5037 5030 5032 5034 5036 5038VOUT2 Note Optical black (22 pixels) Valid photocell (5000 pixels) Invalid photocell (2 pixels) Invalid photocell (2 pixels) φ φ φφ φφ φφ φ Note Input the φ R1 and φ R2 pulses continuously during this period, too.

11Data Sheet S12744EJ4V0DS μ PD3739 TIMING CHART 5 (In phase operation) 2L1 VOUT1 12 50 % 50 % 50 % 50 % 50 % 50 % 10 % 10 % 90 % 90 % 10 % 90 % 90 % 10 % 50 % 50 % 90 % 10 % 90 % 10 % 10 % 10 % 90 % 10 % 10 % 90 %22 1L2 VOUT2 t47 t42 t41’ t42’ t44 t47’ t43 t46t45 t41 td td RFTN VOS RFTN VOS t35 t34 t32’ t36 t33 t37’ t31’ t37 t31 t32 φφ φφ φφ φφ

12 Data Sheet S12744EJ4V0DS

μ PD3739 TIMING CHART 6 (In phase operation) TG 21, 2L1 12, 1L2 t51 t54 t53 t55 t52 90 % 50 % 50 % 50 % 10 % φ φ φ φ φ φ φ φ 11, φ 21 cross points φ 12, φ 22 cross points φ φ φ φ φ 11, φ 2L1 cross points φ 1L2, φ 22 cross points φ φ 2 V or more 0.5 V or more 1L2 φ φ Remark Adjust cross points of ( φ 11, φ 21), (φ 12, φ 22), (φ 11, φ 2L1) and (φ 1L2, φ 22) with input resistance of each pin. Symbol MIN. TYP. MAX. Unit t31, t32, t41, t42 0 50 — ns t33, t43 15 50 — ns t34, t44 5 20 — ns t35, t36, t45, t46 0 20 — ns t37, t37’, t47, t47’ 25 — — ns t51, t52 0 50 — ns t53 1000 2000 5000 ns t54, t55 10 100 — ns

13Data Sheet S12744EJ4V0DS μ PD3739 DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage: Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure: SE Product of intensity of illumination (IX) and storage time(s) when saturation of output voltage occurs. 3. Photo response non-uniformity: PRNU The output signal non-uniformity of all the valid pixels w hen the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula. x ΔxPRNU (%) = × 100 Δx : maximum of | xj − x¯ | x = j = 1 5000 xj 5000 xj : Output voltage of valid pixel number j Δx VOUT Register Dark DC level x 4. Average dark signal: ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula. ADS (mV) = j = 1 5000 dj 5000 dj : Dark signal of valid pixel number j

14 Data Sheet S12744EJ4V0DS

μ PD3739 5. Dark signal non-uniformity: DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV): maximum of | dj – ADS | j = 1 to 5000 dj : Dark signal of valid pixel number j ADS DSNU Register Dark DC level VOUT 6. Output impedance: ZO Impedance of the output pins viewed from outside. 7. Response: R Output voltage divided by exposure (Ix•s). Note that the response varies with a light source (spectral characteristic). 8. Image lag: IL The rate between the last output voltage and the next one after read out the data of a line. TG Light ON OFF VOUT VOUT φ IL (%) = × 100V1 VOUT

15Data Sheet S12744EJ4V0DS μ PD3739 9. Register imbalance: RI The rate of the difference between the averages of the out put voltage of Odd and Ev en pixels, against the average output voltage of all the valid pixels. RI (%) = n j = 1 n (V2j – 1 – V2j) n j = 1 n Vj × 100 n : Number of valid pixels Vj : Output voltage of each pixel 10. Random noise: σ Random noise σ is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding). σ (mV) = i=1 100 (Vi – V) V 100 , = 100 i=1 100 Vi Vi : A valid pixel output signal among all of the valid pixels VOUT V100 line 1 line 2 line 100 This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling).

16 Data Sheet S12744EJ4V0DS

μ PD3739 STANDARD CHARACTERISTIC CURVES (Reference Value) 01 0 2 0 3 04 0 5 0 0.1 0.25 0.5 51 01 0.1 0.2 1200600400 1000 800 100 TOTAL SPECTRAL RESPONSE CHARACTERISTIC (without infrared cut filter) (TA = +25°C) STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (T A = +25°C) DARK OUTPUT TEMPERATURE CHARACTERISTIC Operating Ambient Temperature T A (°C) Relative Output Voltage Relative Output Voltage Storage Time (ms) Wavelength (nm) Response Ratio (%)

17Data Sheet S12744EJ4V0DS μ PD3739 APPLICATION CIRCUIT EXAMPLE (Out of phase operation) PD3739 GND NC VOUT1 NC 200 Ω 200 Ω

0.1 F10 F/16 V

0.1 F 10 F/16 V

0.1 F 47 F/25 V

47 Ω 2 Ω 2 Ω 47 Ω 2 Ω 2 Ω 2 Ω 2L1 NC NC NC NC NC VOUT2 VOD 1L2 NC TG NC B1 B2 +5 V TG +5 V 10 Ω +12 V μ μ μμ μμμ φ φφ φ φ φ φφ φ φ φ φ φ φ Caution Connect the No connection pins (NC) to GND.

18 Data Sheet S12744EJ4V0DS

μ PD3739 Remarks 1. The μ PD3739 can be operated leaving pin 2 (NC) unconnec ted, and connecting pin 4 (NC) and pin 11 (NC) to a +12 V power supply. 2. It is recommended that pins 6 ( φ 2L1) and 17 (φ 1L2) each is separately driven a driver other than that of pins 10, 13 (φ 11, φ 12) and pins 9, 14 (φ 21, φ 22). 3. The inverters shown in the above applicat ion circuit example are the 74AC04. +12 V 110 Ω 4.7 kΩ

47 F/25V

1 kΩ 47 Ω CCD VOUT B1, B2 EQUIVALENT CIRCUIT μ

19Data Sheet S12744EJ4V0DS μ PD3739 PACKAGE DRAWING Name Refractive index ±0.3 42.2± 0.25 4.0 ± 0.3 1bit 9.65±0.3 10.16 2.54 0.46 ± 0.06 1.02 ± 0.15 4.33±0.5 4.68±0.5 (5.27) Glass cap 1.5 (1.95) 0∼10° 22D-1CCD-PKG8-1 48.6 ±0.5 47.5×9.25×0.7 1.60±0.25 25.4 0.25±0.05 2.38 Dimensions CCD LINEAR IMAGE SENSOR 22-PIN CERAMIC DIP (CERDIP) (10.16 mm (400) ) PD3739Dμ (Unit : mm)

20 Data Sheet S12744EJ4V0DS

μ PD3739 RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. Type of Through-hole Device μ PD3739D-A: CCD linear image sensor 22-pin ceramic DIP (CERDIP) (10.16 mm (400)) Process Conditions Partial heating method Pin temperature: 380°C or bel ow, Heat time: 3 seconds or less (per pin). Cautions 1. During assembly care should be taken to pr event solder or flux fr om contacting the glass cap. The optical characteristics could be degraded by such contact. 2. Soldering by the solder flow method may ha ve deleterious effects on prevention of glass cap soiling and heat resistance. So the method cannot be guaranteed. <R>

21Data Sheet S12744EJ4V0DS μ PD3739 NOTES ON HANDLING THE PACKAGES MOUNTING OF THE PACKAGE The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't have any object come in contact with glass cap. You should not reform the lead frame. We recommended to use a IC-inserter when you assemble to PCB. Also, be care that the any of the following can cause the package to crack or dust to be generated. 1. Applying heat to the external leads for an extended period of time with soldering iron. 2. Applying repetitive bending stress to the external leads. 3. Rapid cooling or heating GLASS CAP Don’t either touch glass cap surface by hand or have any object come in contact with glass cap surface. Care should be taken to avoid mechanical or thermal shock because the glass cap is easily to damage. For dirt stuck through electricity ionized air is recommended. OPERATE AND STORAGE ENVIRONMENTS3 Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid storage or usage in such conditions. Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the devices are transported from a low-temperature environment to a high-temperature environment. Avoid such rapid temperature changes. For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E) ELECTROSTATIC BREAKDOWN CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes detected. Before handling be sure to take the following protective measures. 1. Ground the tools such as soldering iron, radio cutting pliers of or pincer. 2. Install a conductive mat or on the floor or working table to prevent the generation of static electricity. 3. Either handle bare handed or use non-chargeable gloves, clothes or material. 4. Ionized air is recommended for discharge when handling CCD image sensor. 5. For the shipment of mounted substrates, use box treated for prevention of static charges. 6. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 M Ω.

22 Data Sheet S12744EJ4V0DS

μ PD3739 [MEMO]

23Data Sheet S12744EJ4V0DS μ PD3739 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V IL (MAX) and V IH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between V IL (MAX) and VIH (MIN). HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. NOTES FOR CMOS DEVICES

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