S124

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■ ARM Cortex-M0+ Core  ARMv6-M architecture  Maximum operating frequency: 32 MHz  Debug and Trace: DWT, BPU, CoreSight™ MTB-M0+  CoreSight Debug Port: SW-DP ■ Memory  Up to 128-KB code flash memory  4-KB data flash memory (up to 100,000 erase/write cycles)  Up to 16-KB SRAM  128-bit unique ID ■ Connectivity  USB 2.0 Full-Speed Module (USBFS) - On-chip transceiver with voltage regulator - Compliant with USB Battery Charging Specification 1.2  Serial Communications Interface (SCI) × 3 - UART - Simple IIC - Simple SPI  Serial Peripheral Interface (SPI) × 2  I 2C bus interface (IIC) × 2  CAN module (CAN) ■ Analog  14-Bit A/D Converter (ADC14)  12-Bit D/A Converter (DAC12)  Low-Power Analog Comparator (ACMPLP) × 2  Temperature Sensor (TSN) ■ Timers  General PWM Timer 32-Bit (GPT32)  General PWM Timer 16-Bit (GPT16) × 6  Asynchronous General-Purpose Timer (AGT) × 2  Watchdog Timer (WDT) ■ Safety  SRAM Parity Error Check  Flash Area Protection  ADC self-diagnosis function  Clock Frequency Accuracy Measurement Circuit (CAC)  Cyclic Redundancy Check (CRC) Calculator  Data Operation Circuit (DOC)  Port Output Enable for GPT (POEG)  Independent Watchdog Timer (IWDT)  GPIO Readback Level Detection  Register Write Protection  Main Oscillator Stop Detection ■ System and Power Management  Low-power modes  RealTime Clock (RTC)  Event Link Controller (ELC)  Data Transfer Controller (DTC)  Key Interrupt Function (KINT)  Power-on reset  Low Voltage Detection with voltage settings ■ Security and Encryption  AES128/256  True Random Number Generator (TRNG) ■ Human Machine Interface (HMI)  Capacitive Touch Sensing Unit (CTSU) ■ Multiple Clock Sources  Main clock oscillator (MOSC) (1 to 20 MHz when VCC = 2.4 to 5.5 V) (1 to 8 MHz when VCC = 1.8 to 5.5 V) (1 to 4 MHz when VCC = 1.6 to 5.5 V)  Sub-clock oscillator (SOSC) (32.768 kHz)  High-speed on-chip oscillator (HOCO) (24, 32, 48, 64 MHz when VCC = 2.4 to 5.5 V) (24, 32, 48 MHz when VCC = 1.8 to 5.5 V) (24, 32 MHz when VCC = 1.6 to 5.5 V)  Middle-speed on-chip oscillator (MOCO) (8 MHz)  Low-speed on-chip oscillator (LOCO) (32.768 kHz)  Independent watchdog timer OCO (15 kHz)  Clock trim function for HOCO/MOCO/LOCO  Clock out support ■ General Purpose I/O Ports  Up to 51 input/output pins - Up to 3 CMOS input - Up to 48 CMOS input/output - Up to 6 5-V tolerant input/output (when VCC = 3.6 V) - Up to 16 pins high current (20 mA) ■ Operating Voltage  VCC: 1.6 to 5.5 V ■ Operating Temperature and Packages  Ta = –40°C to +85°C - 36-pin LGA (4 mm × 4 mm, 0.5 mm pitch)  Ta = –40°C to +105°C - 64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch) - 48-pin LQFP (7 mm × 7 mm, 0.5 mm pitch) - 64-pin QFN (8 mm × 8 mm, 0.4 mm pitch) - 48-pin QFN (7 mm × 7 mm, 0.5 mm pitch) - 40-pin QFN (6 mm × 6 mm, 0.5 mm pitch) Ultra-low power 32-MHz ARM® Cortex®-M0+ microcontroller, up to 128-KB code flash memory, 16-KB SRAM, Capacitive Touch Sensing Unit, 14-bit A/D Converter, 12-bit D/A Converter, security and safety features. S124 MCU (Ultra-Low-Power MCU) 32-bit ARM® Cortex®-M0+ microcontroller

R01DS0264EU0100 Rev.1.00 Page 2 of 95 Feb 23, 2016 S124 1. Overview 1. Overview The S124 MCU comprises multiple series of software- and pin-compatible ARM-based 32-bit MCUs that share a common set of Renesas peripherals to facilitate design scalability and efficient platform-based product development. Based on the energy-efficient ARM® Cortex®-M0+ 32-bit core, this MCU is particularly well suited for cost-sensitive and low-power applications. The MCU in this series feature:  Up to 128 KB code flash memory  16-KB SRAM  Capacitive Touch Sensing Unit (CTSU)  14-bit ADC  12-bit DAC  Security features.

1.1 Function Outline

Table 1.1 ARM core Feature Functional description ARM Cortex-M0+  Maximum operating frequency: up to 32 MHz  ARM Cortex-M0+: - Revision: r0p1-00rel0 - ARMv6-M architecture profile - Single-cycle integer multiplier.  SysTick timer - Driven by LOCO clock. Table 1.2 Memory Feature Functional description Code flash memory Maximum 128 KB code flash memory. See section 37, Flash Memory in User's Manual. Data flash memory 4 KB data flash memory. See section 37, Flash Memory in User's Manual. Option-Setting Memory The option-setting memory determines t he state of the MCU after a reset. See section 6, Option-Setting Memory and Information Memory in User's Manual. SRAM The MCU has an on-chip high-speed SRAM with even parity bit. See section 36, SRAM in User's Manual. Table 1.3 System (1/2) Feature Functional description Operating mode Two operating modes:  Single-chip mode  SCI boot mode. See section 3, Operating Modes in User's Manual. Reset The MCU has 9 types of resets:  RES pin reset  Power-on reset  Independent watchdog timer reset  Watchdog timer reset  Voltage monitor 0 reset  Voltage monitor 1 reset  Voltage monitor 2 reset  SRAM parity error reset  Software reset. See section 5, Resets in User's Manual.

R01DS0264EU0100 Rev.1.00 Page 3 of 95 Feb 23, 2016 S124 1. Overview Low Voltage Detection (LVD) The Low Voltage Detection (LVD) monitors the voltage level input to the VCC pin and the detection level can be selected using a software program. See section 7, Low Voltage Detection (LVD) in User's Manual. Clock  Main clock oscillator (MOSC)  Sub-clock oscillator (SOSC)  High-speed on-chip oscillator (HOCO)  Middle-speed on-chip oscillator (MOCO)  Low-speed on-chip oscillator (LOCO)  Independent Watchdog Timer on-chip oscillator  Clock out support. See section 8, Clock Generation Circuit in User's Manual. Clock Frequency Accuracy Measurement Circuit (CAC) The clock frequency accuracy measurement circuit (CAC) is used to check the system clock frequency with a reference clock signal by counting the number of pulses of the system clock to be measured. The reference clock can be provided externally through a CACREF pin or internally from various on-chip oscillators. Event signals can be generated when the clock does not match or measurement ends. This feature is particularly useful in implementing a fail-safe mechanism for home and industrial automation applications. See section 9, Clock Frequency Accuracy Measurement Circuit (CAC) in User's Manual. Low Power Mode The MCU has several functions for r educing power consumption, such as setting clock dividers, stopping modules, selecting power control mode in normal operation, and transitioning to low power modes. See section 10, Low Power Modes in User's Manual. Register Write Protection The Register Write Protection func tion protects important registers from being overwritten due to software errors. See section 11, Register Write Protection in User's Manual. Watchdog Timer (WDT) The Watchdog Timer (WDT) is a 14-bi t down-counter. It can be used to reset the MCU when the counter underflows because the system has run out of control and is unable to refresh the WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow. The refresh-permitted period can be set to refresh the counter and used as the condition to detect when the system runs out of control. See section 22, Watchdog Timer (WDT) in User's Manual. Independent Watchdog Timer (IWDT) The Independent Watchdog Timer (IWDT) consists of a 14-bit down-counter that must be serviced periodically to prevent counter underflow. The IWDT provides functionality to reset the MCU or to generate a non-maskable interrupt/interrupt for a timer underflow. Because the timer operates with an independent, dedicated clock source, it is particularly useful in returning the MCU to a known state as a fail safe mechanism when the system runs out of control. The watchdog timer can be triggered automatically on reset, underflow, or refresh error, or by a refresh of the count value in the registers. See section 23, Independent Watchdog Timer (IWDT) in User's Manual. Table 1.4 Interrupt Control Feature Functional description Interrupt Controller Unit (ICU) The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC/DTC module. The ICU also controls NMI interrupts. See section 12, Interrupt Controller Unit (ICU) in User's Manual. Table 1.5 Event Link Feature Functional description Event Link Controller (ELC) The Event Link Controller (ELC) uses the interrupt requests generated by various peripheral modules as event signals to connect them to different modules, enabling direct interaction between the modules without CPU intervention. See section 15, Event Link Controller (ELC) in User's Manual. Table 1.6 Direct memory access Feature Functional description Data Transfer Controller (DTC) The MCU incorporates a Data Transfer Controller (DTC) that performs data transfers when activated by an interrupt request. See section 14, Data Transfer Controller (DTC) in User's Manual. Table 1.3 System (2/2) Feature Functional description

R01DS0264EU0100 Rev.1.00 Page 4 of 95 Feb 23, 2016 S124 1. Overview Table 1.7 Timers Feature Functional description General PWM Timer (GPT) The General PWM Timer (GPT) is a 32-bit timer with 1 channel and a 16-bit timer with 6 channels. PWM waveforms can be generated by controlling the up-counter, down-counter, or the up- and down-counter. In addition, PWM waveforms for controlling brushless DC motors can be generated. The GPT can also be used as a general-purpose timer. See section 19, General PWM Timer (GPT) in User's Manual. Port Output Enable for GPT (POEG) Use the Port Output Enable for GPT (POEG) function to place the General PWM Timer (GPT) output pins in the output disable state. See section 18, Port Output Enable for GPT (POEG) in User’s Manual. Asynchronous General Purpose Timer (AGT) The Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used for pulse output, external pulse width or period measurement, and counting external events. This 16-bit timer consists of a reload register and a down-counter. The reload register and the down-counter are allocated to the same address, and they can be accessed with the AGT register. See section 20, Asynchronous General Purpose Timer (AGT) in User's Manual. Realtime Clock (RTC) The Realtime Clock (RTC) has two counting modes, calendar count mode and binary count mode, that are used by switching register settings. For calendar count mode, the RTC has a 100-year calendar from 2000 to 2099 and automatically adjusts dates for leap years. For binary count mode, the RTC counts seconds and retains the information as a serial value. Binary count mode can be used for calendars other than the Gregorian (Western) calendar. See section 21, Realtime Clock (RTC) in User's Manual. Table 1.8 Communication interfaces (1/2) Feature Functional description Serial Communications Interface (SCI) The Serial Communication Interface (SCI) is configurable to five asynchronous and synchronous serial interfaces:  Asynchronous interfaces (UART and asynchronous communications interface adapter (ACIA))  8-bit clock synchronous interface  Simple IIC (master-only)  Simple SPI  Smart card interface The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and transmission protocol. SCI0 has FIFO buffers to enable continuous and full-duplex communication, and the data transfer speed can be configured independently using an on-chip baud rate generator. See section 25, Serial Communications Interface (SCI) in User's Manual. I 2C Bus interface (IIC) The MCU has a two-channel I 2C bus interface (IIC). The IIC module conforms with and provides a subset of the NXP I2C bus (Inter-Integrated Circuit bus) interface functions. See section 26, I2C Bus Interface (IIC) in User's Manual. Serial Peripheral Interface (SPI) The MCU includes two independent channels of the Serial Peripheral Interface (SPI). The SPI channels are capable of high-speed, full-duplex synchronous serial communications with multiple processors and peripheral devices. See section 28, Serial Peripheral Interface (SPI) in User's Manual. Controller Area Network (CAN) Module The Controller Area Network (CAN) module provides functionality to receive and transmit data using a message-based protocol between multiple slaves and masters in electromagnetically noisy applications. The CAN module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports up to 32 mailboxes, which can be configured for transmission or reception in normal mailbox and FIFO modes. Both standard (11-bit) and extended (29-bit) messaging formats are supported. See section 27, Controller Area Network (CAN) Module in User's Manual.

R01DS0264EU0100 Rev.1.00 Page 5 of 95 Feb 23, 2016 S124 1. Overview USB 2.0 Full-Speed Module (USBFS) The MCU incorporates a USB 2.0 Full-Speed module (USBFS). The USBFS is a USB controller that is equipped to operate as a device controller. The module supports full-speed and low-speed transfer as defined in the Universal Serial Bus Specification 2.0. The module has an internal USB transceiver and supports all of the transfer types defined in the Universal Serial Bus Specification 2.0. The USB has buffer memory for data transfer, providing a maximum of 5 pipes. PIPE0 and PIPE4 to PIPE7 can be assigned any endpoint number based on the peripheral devices used for communication or based on the user system. The MCU supports revision 1.2 of the battery charging specification. Because the MCU can be powered at 5 V, the USB LDO regulator provides the internal USB transceiver power supply 3.3 V. See section 24, USB 2.0 Full-Speed Module (USBFS) in User's Manual. Table 1.9 Analog Feature Functional description 14-bit A/D Converter (ADC14) The MCU incorporates up to one uni t of a 14-bit successive approximation A/D converter. Up to 18 analog input channels are selectable. Temperature sensor output and internal reference voltage are selectable for conversion. The A/D conversion accuracy is selectable from 12-bit and 14-bit conversion making it possible to optimize the tradeoff between speed and resolution in generating a digital value. See section 30, 14-Bit A/D Converter (ADC14) in User's Manual. 12-bit D/A Converter (DAC12) The MCU includes a 12-bit D/A conv erter with an output amplifier. See section 31, 12-Bit D/A Converter (DAC12) in User's Manual. Temperature Sensor (TSN) The on-chip Temperature Sensor can be used to determine and monitor the die temperature for reliable operation of the device. The sensor outputs a voltage directly proportional to the die temperature, and the relationship between the die temperature and the output voltage is linear. The output voltage is provided to the ADC for conversion and can be further used by the end application. See section 32, Temperature Sensor (TSN) in User's Manual. Low-Power Analog Comparator (ACMPLP) Analog comparators can be used to compare a reference input voltage and analog input voltage. The comparison result can be read by software and also be output externally. The reference input voltage can be selected from either an input to the CMPREFi (i = 0, 1) pin or from the internal reference voltage (Vref) generated internally in this MCU. The ACMPLP response speed can be set before starting an operation. Setting high-speed mode decreases the response delay time, but increases current consumption. Setting low- speed mode increases the response delay time, but decreases current consumption. See section 33, Low-Power Analog Comparator (ACMPLP) in User's Manual. Table 1.10 Human machine interfaces Feature Functional description Key Interrupt Function (KINT) A key interrupt can be generated by setting the Key Return Mode register (KRM) and inputting a rising/falling edge to the key interrupt input pins. See section 17, Key Interrupt Function (KINT) in User's Manual. Capacitive Touch Sensing Unit (CTSU) The Capacitive Touch Sensing Unit (CTSU) measures the electrostatic capacitance of the touch sensor. Changes in the electrostatic capacitance are determined by software, which enables the CTSU to detect whether a finger is in contact with the touch sensor. The electrode surface of the touch sensor is usually enclosed with an electrical conductor so that a finger does not come into direct contact with the electrode. See section 34, Capacitive Touch Sensing Unit (CTSU) in User's Manual. Table 1.11 Data processing Feature Functional description Cyclic Redundancy Check (CRC) Calculator The Cyclic Redundancy Check (CRC) generates CRC codes to detect errors in the data. The bit order of CRC calculation results can be switched for LSB first or MSB first communication. Additionally, various CRC generation polynomials are available. The snoop function allows monitoring reads from and writes to specific addresses. This function is useful in applications that require CRC code to be generated automatically in certain events, such as monitoring writes to the serial transmit buffer and reads from the serial receive buffer. See section 29, Cyclic Redundancy Check (CRC) Calculator in User's Manual. Table 1.8 Communication interfaces (2/2) Feature Functional description

R01DS0264EU0100 Rev.1.00 Page 6 of 95 Feb 23, 2016 S124 1. Overview Data Operation Circuit (DOC) The Data O peration Circuit (DOC) is used to compare, add, and subtract 16-bit data. See section 35, Data Operation Circuit (DOC) in User's Manual. Table 1.12 Security Feature Functional description AES See the AES Engine chapter. True Random Number Generator (TRNG) See True Random Number Generator chapter. Table 1.11 Data processing Feature Functional description

R01DS0264EU0100 Rev.1.00 Page 7 of 95 Feb 23, 2016 S124 1. Overview

1.2 Block Diagram

Figure 1.1 shows the block diagram of this MCU superset. Individual devices within the group may have a subset of the features. Figure 1.1 Block diagram Memories

128 KB Code Flash

4 KB Data Flash

16 KB SRAM

(H/M/L) OCO GPT32 × 1 GPT16 × 6 Timers AGT × 2 RTC CTSU KINT ARM Cortex-M0+ NVIC System Timer Test and DBG I/F DTC WDT/IWDT CAC POR/LVD Reset Human Machine Interfaces ELC Event Link AES + TRNG Security Analogs CRC Data Processing DOC Communication Interfaces IIC × 2 SPI × 2 CAN × 1 USBFS with BC1.2 SCI × 3 TSN DAC12 ACMPLP × 2 ADC14

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1.3 Part Numbering

Figure 1.2 Part numbering scheme 7 3 A 0 1 C F M Package type FM: LQFP 64 pins FL: LQFP 48 pins LM: LGA 36 pins NB: QFN 64 pins NE: QFN 48 pins NF: QFN 40 pins Quality ID Software ID Operating temperature 2: -40 ° C to 85° C 3: -40° C to 105° C Code flash memory size 6: 64 KB 7: 128 KB Feature set 7: Superset Group name 4: S124 Core 2: ARM Cortex-M0+ Series name 1: Ultra low power Renesas Synergy family Flash memory Renesas microcontroller Renesas R 7 F S 1 2 4 7

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1.4 Function Comparison

Table 1.13 Function comparison Parts number R7FS124773A01CFM/ R7FS124763A01CFM/ R7FS124773A01CNB/ R7FS124763A01CNB R7FS124773A01CFL/ R7FS124763A01CFL/ R7FS124773A01CNE/ R7FS124763A01CNE R7FS124773A01CNF/ R7FS124763A01CNF R7FS124772A01CLM/ R7FS124762A01CLM Pin count 64 48 40 36 Package LQFP/QFN LQFP/QFN QFN LGA Code flash memory 128/64 KB Data flash memory 4 KB SRAM 16 KB Parity 4 KB System CPU clock 32 MHz Interrupt control ICU Yes Event control ELC 8 8 7 6 DMA DTC Yes Timers GPT32 1 G P T 1 6 6 644 A G T2 222 RTC Yes WDT/IWDT Yes Communication SCI 3 IIC 2 SPI 2 CAN Yes USBFS Yes Analog ADC14 18 14 12 11 DAC12 1 ACMPLP 2 TSN Yes H M I C T S U 3 1 2 31 71 3 K I N T 8 554 Data processing CRC Yes DOC Yes Security AES and TRNG

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1.5 Pin Functions

Table 1.14 Pin functions (1/3) Function Signal I/O Description Power supply VCC Input Power supply pin. Connect it to the system power supply. Connect this pin to VSS by a 0.1-μF capacitor. The capacitor should be placed close to the pin. VCL Input Connect this pin to the VSS pin by the smoothing capacitor used to stabilize the internal power supply. Place the capacitor close to the pin. VSS Input Ground pin. Connect it to the system power supply (0 V). Clock XTAL Output Pins for a crystal resonator. An external clock signal can be input through the EXTAL pin.EXTAL Input XCIN Input Input/output pins for the sub-clo ck oscillator. Connect a crystal resonator between XCOUT and XCIN.XCOUT Output CLKOUT Output Clock output pin. Operating mode control MD Input Pins for setting the oper ating mode. The signal levels on these pins must not be changed during operation mode transition at the time of release from the reset state. System control RES Input Reset signal input pin. The MCU enters the reset state when this signal goes low. CAC CACREF Input Measurement reference clock input pin. On-chip debug SWDIO I/O Serial Wire debug Data Input/Output pin. SWCLK Input Serial Wire Clock pin. Interrupt NMI Input Non-maskable interrupt request pin. IRQ0 to IRQ7 Input Maskable interrupt request pins. GPT GTETRGA, GTETRGB Input External trigger input pin. GTIOC0A to GTIOC6A, GTIOC0B to GTIOC6B I/O Input capture, Output Compare, or PWM output pin. GTIU Input Hall sensor input pin U. GTIV Input Hall sensor input pin V. GTIW Input Hall sensor input pin W. GTOUUP Output Three-phase PWM output for BLDC motor control (positive U phase). GTOULO Output Three-phase PWM output for BLDC motor control (negative U phase). GTOVUP Output Three-phase PWM output for BLDC motor control (positive V phase). GTOVLO Output Three-phase PWM output for BLDC motor control (negative V phase). GTOWUP Output Three-phase PWM output for BLDC motor control (positive W phase). GTOWLO Output Three-phase PWM output for BLDC motor control (negative W phase). AGT AGTEE0, AGTEE1 Input External event input enable. AGTIO0, AGTIO1 I/O External event input and pulse output. AGTO0, AGTO1 Output Pulse output. AGTOA0, AGTOA1 Output Output compare match A output. AGTOB0, AGTOB1 Output Output compare match B output. RTC RTCOUT Output Output pin for 1-Hz/64-Hz clock.

R01DS0264EU0100 Rev.1.00 Page 11 of 95 Feb 23, 2016 S124 1. Overview SCI SCK0, SCK1, SCK9 I/O Input/output pins for the cl ock (clock synchronous mode). RXD0, RXD1, RXD9 Input Input pins for received data (a synchronous mode/clock synchronous mode). TXD0, TXD1, TXD9 Output Output pins for transmitted dat a (asynchronous mode/clock synchronous mode). CTS0_RTS0, CTS1_RTS1, CTS9_RTS9 I/O Input/Output pins for controlling t he start of transmission and reception (asynchronous mode/clock synchronous mode), active LOW. SCL0, SCL1, SCL9 I/O Input/output pins for the IIC clock (simple IIC). SDA0, SDA1, SDA9 I/O Input/output pins for the IIC data (simple IIC). SCK0, SCK1, SCK9 I/O Input/output pins for the clock (simple SPI). MISO0, MISO1, MISO9 I/O Input/output pins for slave tr ansmission of data (simple SPI). MOSI0, MOSI1, MOSI9 I/O Input/output pins for master transmission of data (simple SPI). SS0, SS1, SS9 Input Slave-select input pins (simple SPI), active LOW. IIC SCL0, SCL1 I/O Input/output pins for clock. SDA0, SDA1 I/O Input/output pins for data. SPI RSPCKA, RSPCKB I/O Clock input/output pin. MOSIA, MOSIB I/O Inputs or outputs data output from the master. MISOA, MISOB I/O Inputs or outputs data output from the slave. SSLA0, SSLB0 I/O Input or output pin for slave selection. SSLA1 to SSLA3, SSLB1 to SSLB3 Output Output pin for slave selection. CAN CRX0 Input Receive data. CTX0 Output Transmit data. USBFS VSS_USB Input Ground pins. VCC_USB_LDO Input Power supply pin for USB LDO regulator. VCC_USB I/O Input: Power supply pin for USB transceiver. Output: USB LDO regulator output pin. This pin should be connected to an external capacitor. USB_DP I/O D+ I/O pin of the USB on-chip tr ansceiver. This pin should be connected to the D+ pin of the USB bus. USB_DM I/O D– I/O pin of the USB on-chip tr ansceiver. This pin should be connected to the D– pin of the USB bus. USB_VBUS Input USB cable connection monitor pin. This pin should be connected to VBUS of the USB bus. The VBUS pin status (connected or disconnected) can be detected when the USB module is operating as a function controller. Analog power supply AVCC0 Input Analog voltage supply pin for the analog. Connect this pin to VCC. AVSS0 Input Analog ground pin. Connect this pin to VSS. VREFH0 Input Analog reference voltage supply pi n for the A/D converter. Connect this pin to VCC when not using the A/D converter. VREFL0 Input Analog reference ground pin for the A/D converter. Connect this pin to VSS when not using the A/D converter. Table 1.14 Pin functions (2/3) Function Signal I/O Description

R01DS0264EU0100 Rev.1.00 Page 12 of 95 Feb 23, 2016 S124 1. Overview ADC14 AN000 to AN010, AN016 to AN022 Input Input pins for the analog signals to be processed by the A/D converter. ADTRG0 Input Input pins for the external trig ger signals that start the A/D conversion, active LOW. DAC12 DA0 Output Output pins for the analog sign als to be processed by the D/A converter. ACMPLP VCOUT Output Comparator output pin. CMPREF0, CMPREF1 Input Reference voltage input pins. CMPIN0, CMPIN1 Input Analog voltage input pins. CTSU TS00 to TS28, TS30, TS31 Input Capacitive touch det ection pins (touch pins). TSCAP - Secondary power supply pin for the touch driver. KINT KR00 to KR07 Input Key interrupt input pins. I/O ports P000 to P004, P010 to P015 I/O General-purpose input/output pins. P100 to P113 I/O General-purpose input/output pins. P200 Input General-purpose input pin. P201, P204 to P206, P212, P213 I/O General-purpose input/output pins. P214, P215 Input General-purpose input pins. P300 to P304 I/O General-purpose input/output pins. P400 to P403, P407 to P411 I/O General-purpose input/output pins. P500 to P502 I/O General-purpose input/output pins. Table 1.14 Pin functions (3/3) Function Signal I/O Description

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1.6 Pin Assignments

Figure 1.3 to Figure 1.8 show the pin assignments. Figure 1.3 Pin assignment for LQFP 64-pin (Top view) P501 P502 P015 P014 P012 AVCC0 AVSS0 P011/VREFL0 P010/VREFH0 P004 P003 P002 P001 P013 P300/SWCLK P301 P302 P303 P304 P201/MD RES P204 P205 P206 VCC_USB_LDO VCC_USB USB_DP USB_DM VSS_USB P200 P100 P102 P103 P104 P105 P106 P107 VSS VCC P113 P112 P111 P110 P108/SWDIO P101 P109 P400 P402 P403 VCL P215/XCIN P214/XCOUT VSS P213/XTAL P212/EXTAL VCC P411 P410 P408 P407 P401 P409 P000 R7FS1247x3A01CFM P500

R01DS0264EU0100 Rev.1.00 Page 14 of 95 Feb 23, 2016 S124 1. Overview Figure 1.4 Pin assignment for QFN 64-pin (Top view) P300/SWCLK P301 P302 P303 P304 P201/MD RES P204 P205 P206 VCC_USB_LDO VCC_USB USB_DP USB_DM VSS_USB P200 P100 P102 P103 P104 P105 P106 P107 VSS VCC P113 P112 P111 P110 P108/SWDIO P101 P109 P400 P402 P403 VCL P215/XCIN P214/XCOUT VSS P213/XTAL P212/EXTAL VCC P411 P410 P408 P407 P401 P409 R7FS1247x3A01CNB 49P500 P501 P502 P015 P014 P012 AVCC0 AVSS0 P011/VREFL0 P010/VREFH0 P004 P003 P002 P001 P000 P013

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1.7 Pin Lists

Power, System, Clock, Debug, CAC I/O ports Timers Communication Interfaces Analogs HMI LQFP64 LQFP48 QFN48 QFN40 LGA36 AGT GPT_OPS, POEG GPT RTC USBFS,CAN SCI IIC SPI ADC14 DAC12, ACMPLP CTSU Interrupt

1111 C 2 C A C R E F _

C P400 AGTIO1_ D GTIOC6A SCK0_B/ SCK1_B SCL0_A TS20 IRQ0 222- - P 4 0 1 G T E T R G A_B GTIOC6B CTX0_B CTS0_RT S0_B/ SS0_B/ TXD1_B/ MOSI1_B/ SDA1_B SDA0_A TS19 IRQ5 3 - - - - P402 CRX0_B RXD1_B/ MISO1_B/ SCL1_B TS18 IRQ4 4---- P 4 0 3 G T I O C 3 A CTS1_RT S1_B/ SS1_B TS17

5332 A 1 V C L

6443 B 1 X C I N P 2 1 5

8665 D 1 V S S

9776 D 3 X T A L P 2 1 3 G T E T R G

A_D TXD1_A/ MOSI1_A/ SDA1_A IRQ2 10 8 8 7 D2 EXTAL P212 AGTEE1 GTETRG B_D RXD1_A/ MISO1_A/ SCL1_A IRQ3 11 9 9 8 E1 VCC 12 - - - - P411 AGTOA1 GTOVUP GTIOC6A TXD0_B/ MOSI0_B/ SDA0_B MOSIA_B TS07 IRQ4 13 - - - - P410 AGTOB1 GTOVLO GTIOC6B RXD0_B/ MISO0_B/ SCL0_B MISOA_B TS06 IRQ5 14 10 10 - - P409 GTOWUP GTIOC5A TXD9_A/ MOSI9_A/ SDA9_A TS05 IRQ6 15 11 11 9 - P408 GTOWLO GTIOC5B RXD9_A/ MISO9_A/ SCL9_A TS04 IRQ7 16 12 12 10 E2 P407 RTCOUT USB_VBU S CTS0_RT S0_D/ SS0_D SDA0_B SSLB3_A ADTRG0_ B TS03 17 13 13 11 F1 VSS_USB 18 14 14 12 F2 USB_DM 19 15 15 13 F3 USB_DP 20 16 16 14 F4 VCC_US B 21 17 17 15 F5 VCC_US B_LDO 22 18 18 - - P206 GTIU_A RXD0_D/ MISO0_D/ SCL0_D SDA1_A SSLB1_A TS01 IRQ0 23 - - - - CLKOUT_ A P205 AGTO1 GTIV_A GTIOC4A TXD0_D/ MOSI0_D/ SDA0_D/ CTS9_RT S9_A/ SS9_A SCL1_A SSLB0_A TSCAP_A IRQ1 2 4 ---- C A C R E F _ A P204 AGTIO1_ A GTIW_A GTIOC4B SCK0_D/ SCK9_A SCL0_B RSPCKB_ A TS00 25 19 19 16 E3 RES 26 20 20 17 E4 MD P201 27 21 21 18 E5 P200 NMI 28 - - - - P304 GTIOC1A 29 - - - - P303 GTIOC1B TS02 30 22 22 - - P302 GTOUUP GTIOC4A SSLB3_B TS08 IRQ5 31 23 23 19 - P301 GTOULO GTIOC4B SSLB2_B TS09 IRQ6 32 24 24 20 F6 SWCLK P300 GTOUUP GTIOC0A SSLB1_B 33 25 25 21 E6 SWDIO P108 GTOULO GTIOC0B CTS9_RT S9_B/ SS9_B SSLB0_B 34 26 26 22 D4 CLKOUT_ B P109 GTOVUP GTIOC1A CTX0_A TXD9_B/ MOSI9_B/ SDA9_B MOSIB_B TS10

R01DS0264EU0100 Rev.1.00 Page 18 of 95 Feb 23, 2016 S124 1. Overview Note: Several pin names have the added suffix of _A, _B, _C, and _D. The suffix can be ignored when assigning functionality. 35 27 27 23 D5 P110 GTOVLO GTIOC1B CRX0_A CTS0_RT S0_C/ SS0_C/ RXD9_B/ MISO9_B/ SCL9_B MISOB_B VCOUT TS11 IRQ3 36 28 28 24 D6 P111 GTIOC3A SCK0_C/ SCK9_B RSPCKB_ B TS12 IRQ4 37 29 29 25 C6 P112 GTIOC3B TXD0_C/ MOSI0_C/ SDA0_C TSCAP_C 3 8 ---- P 1 1 3 39 30 30 - - VCC 40 31 31 - - VSS 41 - - - - P107 GTIOC0A KR07 42 - - - - P106 GTIOC0B SSLA3_A KR06 43 - - - - P105 GTETRG A_C SSLA2_A KR05/ IRQ0 44 32 32 26 - P104 GTETRG B_B RXD0_C/ MISO0_C/ SCL0_C SSLA1_A TS13 KR04/ IRQ1 45 33 33 27 C3 P103 GTOWUP GTIOC2A CTX0_C CTS0_RT S0_A/ SS0_A SSLA0_A AN019 CMPREF TS14 KR03 46 34 34 28 C4 P102 AGTO0 GTOWLO GTIOC2B CRX0_C SCK0_A RSPCKA_ A AN020/ ADTRG0_ A CMPIN1 TS15 KR02 47 35 35 29 C5 P101 AGTEE0 GTETRG B_A GTIOC5A TXD0_A/ MOSI0_A/ SDA0_A/ CTS1_RT S1_A/ SS1_A SDA1_B MOSIA_A AN021 CMPREF TS16 KR01/ IRQ1 48 36 36 30 B6 P100 AGTIO0_ A GTETRG A_A GTIOC5B RXD0_A/ MISO0_A/ SCL0_A/ SCK1_A SCL1_B MISOA_A AN022 CMPIN0 TS26 KR00/ IRQ2 49 37 37 - - P500 AGTOA0 GTIU_B GTIOC2A AN016 TS27 50 - - - - P501 AGTOB0 GTIV_B GTIOC2B AN017 51 - - - - P502 GTIW_B GTIOC3B AN018 52 38 38 31 A6 P015 AN010 TS28 IRQ7 53 39 39 32 A5 P014 AN009 DA0 54 40 40 33 B5 P013 AN008 55 41 41 34 B4 P012 AN007 56 42 42 35 A4 AVCC0 57 43 43 36 A3 AVSS0 58 44 44 37 B3 VREFL0 P011 AN006 TS31 59 45 45 38 A2 VREFH0 P010 AN005 TS30 60 - - - - P004 AN004 TS25 IRQ3 61 - - - - P003 AN003 TS24 62 46 46 - - P002 AN002 TS23 IRQ2 63 47 47 39 - P001 AN001 TS22 IRQ7 64 48 48 40 B2 P000 AN000 TS21 IRQ6 Pin number Power, System, Clock, Debug, CAC I/O ports Timers Communication Interfaces Analogs HMI LQFP64 LQFP48 QFN48 QFN40 LGA36 AGT GPT_OPS, POEG GPT RTC USBFS,CAN SCI IIC SPI ADC14 DAC12, ACMPLP CTSU Interrupt

R01DS0264EU0100 Rev.1.00 Page 20 of 95 Feb 23, 2016 S124 2. Electrical Characteristics

2.1 Absolute Maximum Ratings

Caution: Permanent damage to the MCU may result if absolute maximum ratings are exceeded. To preclude any malfunctions due to noise interference, insert capacitors of high frequency characteristics between the VCC and VSS pins, between the AVCC0 and AVSS0 pins, between the VCC_USB and VSS_USB pins, and between the VREFH0 and VREFL0 pins. Place capacitors of about 0.1 μF as close as possible to every power supply pin and use the shortest and heaviest possible traces. Also, connect capacitors as stabilization capacitance. Connect the VCL pin to a VSS pin by a 4.7-µF capacitor. The capacitor must be placed close to the pin. Note 1. Ports P205, P206, P400, P401, and P407 are 5V-tolerant. Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up might cause malfunction and the abnormal current that passes in the device at this time might cause degradation of internal elements. Note 2. See section 2.2.1, Tj/Ta Definition. Note 3. Contact Renesas Electronics sales office for information on derating operation under Ta = +85°C to +105°C. Derating is the systematic reduction of load for improved reliability. Table 2.1 Absolute maximum ratings Item Symbol Value Unit Power supply voltage VCC –0.5 to +6.5 V Input voltage 5V-tolerant ports* 1 Vin –0.3 to +6.5 V P000 to P004 P010 to P015 Vin –0.3 to AVCC0 + 0.3 V Others V in –0.3 to VCC + 0.3 V Reference power supply voltage VREFH0 –0.3 to +6.5 V Analog power supply voltage AVCC0 –0.5 to +6.5 V USB power supply voltage VCC_USB –0.5 to +6.5 V VCC_USB_LDO –0.5 to +6.5 V Analog input voltage When AN000 to AN010 are used VAN –0.3 to AVCC0 + 0.3 V When AN016 to AN022 are used –0.3 to VCC + 0.3 V Operating temperature*2 *3 Topr –40 to +105 °C Storage temperature T stg –55 to +125 °C

R01DS0264EU0100 Rev.1.00 Page 21 of 95 Feb 23, 2016 S124 2. Electrical Characteristics Note 1. Use AVCC0 and VCC under the following conditions: AVCC0 and VCC can be set individually within the operating range when VCC ≥ 2.0 V AVCC0 = VCC when VCC < 2.0 V. Note 2. When powering on the VCC and AVCC0 pins, power them on at the same time or the VCC pin first and then the AVCC0 pin. Table 2.2 Recommended operating conditions Item Symbol Value Min Typ Max Unit Power supply voltages VCC *1, *2 When USBFS is not used 1.6 - 5.5 V When USBFS is used USB Regulator Disable VCC_USB - 3.6 V When USBFS is used USB Regulator Enable VCC_USB _LDO -5 . 5 V V S S -0 -V USB power supply voltages VCC_USB When USBFS is not used -V C C -V When USBFS is used USB Regulator Disable (Input) 3.0 3.3 3.6 V VCC_USB_LDO When USBFS is not used -V C C -V When USBFS is used USB Regulator Enable 3.8 - 5.5 V VSS_USB - 0 - V Analog power supply voltages AVCC0 *1, *2 1.6 - 5.5 V AVSS0 - 0 - V VREFH0 When used as ADC14 Reference 1.6 - AVCC0 V VREFL0 - 0 - V

R01DS0264EU0100 Rev.1.00 Page 22 of 95 Feb 23, 2016 S124 2. Electrical Characteristics

2.2 DC Characteristics

2.2.1 Tj/Ta Definition

Note: Make sure that Tj = T a + θja × total power consumption (W), where total power consumption = (VCC – VOH) × ΣIOH + VOL × ΣIOL + ICCmax × VCC.

2.2.2 I/O V IH, VIL

Note 1. SCL0_A, SDA0_A, SDA0_B, SCL1_A, SDA1_A (total 5 pins) Note 2. SCL0_A, SDA0_A, SCL0_B, SDA0_B, SCL1_ A, SDA1_A, SCL1_B, SDA1_B (total 8 pins) Note 3. P205, P206, P400, P401, P407 (total 5pins) Table 2.3 DC characteristics Conditions: Products with operating temperature (Ta) –40 to +105°C Item Symbol Typ Max Unit Test conditions Permissible junction temperature Tj - 125 °C High-speed mode Middle-speed mode Low-voltage mode Low-speed mode SubOSC-speed mode Table 2.4 I/O V IH, VIL (1) Conditions: VCC = AVCC0 = 2.7 to 5.5 V Item Symbol Min Typ Max Unit Test Conditions Schmitt trigger input voltage IIC (except for SMBus)*1 VIH VCC × 0.7 - 5.8 V - VIL –0.3 - VCC × 0.3 ∆VT VCC × 0.05 - - RES, NMI Other peripheral input pins excluding IIC V IH VCC × 0.8 - VCC + 0.3 VIL –0.3 - VCC × 0.2 ∆VT VCC × 0.1 - - Input voltage (except for Schmitt trigger input pin) IIC (SMBus)* 2 VIH 2.2 - VCC + 0.3 VCC = 3.6 to 5.5 V VIH 2.0 - VCC + 0.3 VCC =2.7 to 3.6 V VIL –0.3 - 0.8 - 5V-tolerant ports*3 VIH VCC × 0.8 - 5.8 VIL –0.3 - VCC × 0.2 P000 to P004 P010 to P015 VIH AVCC0 × 0.8 - AVCC0 + 0.3 VIL –0.3 - AVCC0 × 0.2 EXTAL Input ports pins except for P000 to P004, P010 to P015 VIH VCC × 0.8 - VCC + 0.3 VIL –0.3 - VCC × 0.2

R01DS0264EU0100 Rev.1.00 Page 23 of 95 Feb 23, 2016 S124 2. Electrical Characteristics Note 1. P205, P206, P400, P401, P407 (total 5pins) Table 2.5 I/O V IH, VIL (2) Conditions: VCC = AVCC0 = 1.6 to 2.7 V Item Symbol Min Typ Max Unit Test Conditions Schmitt trigger input voltage RES, NMI Peripheral input pins VIH VCC × 0.8 - VCC + 0.3 V - VIL –0.3 - VCC × 0.2 ∆VT VCC × 0.01 - - Input voltage (except for Schmitt trigger input pin) 5V-tolerant ports*1 VIH VCC × 0.8 - 5.8 VIL –0.3 - VCC × 0.2 P000 to P004 P010 to P015 VIH AVCC0 × 0.8 - AVCC0 + 0.3 VIL –0.3 - AVCC0 × 0.2 EXTAL Input ports pins except for P000 to P004, P010 to P015 V IH VCC × 0.8 - VCC + 0.3 VIL –0.3 - VCC × 0.2

R01DS0264EU0100 Rev.1.00 Page 24 of 95 Feb 23, 2016 S124 2. Electrical Characteristics

2.2.3 I/O I OH, IOL

Caution: To protect the reliability of the MCU, the outp ut current values should not exceed the values in this table. The average output current indicates the average value of current measured during 100 μs. Note 1. This is the value when low driving ability is select ed with the port drive capability bit in the PmnPFS register. Note 2. This is the value when middle driving ability is sele cted with the port drive capability bit in the PmnPFS register. Note 3. Except for Ports P200, P2 14, P215, which are input ports. Table 2.6 I/O I OH, IOL Conditions: VCC = AVCC0 = 1.6 to 5.5 V Item Symbol Min Typ Max Unit Permissible output current (average value per pin) Ports P000 to P004, P010 to P015, P212, P213 - IOH --– 4 . 0 m A IOL --4 . 0 m A Ports P408, P409 Low drive* 1 IOH --– 4 . 0 m A IOL --4 . 0 m A Middle drive*2 VCC = 2.7 to 3.0 V IOH --– 8 . 0 m A IOL --8 . 0 m A Middle drive*2 VCC = 3.0 to 5.5 V IOH --– 2 0 . 0 m A IOL --2 0 . 0 m A Other output pins*3 Low drive* 1 IOH --– 4 . 0 m A IOL --4 . 0 m A Middle drive*2 IOH --– 8 . 0 m A IOL --8 . 0 m A Permissible output current (max value per pin) Ports P000 to P004, P010 to P015, P212, P213 - IOH --– 4 . 0 m A IOL --4 . 0 m A Ports P408, P409 Low drive* 1 IOH --– 4 . 0 m A IOL --4 . 0 m A Middle drive*2 VCC = 2.7 to 3.0 V IOH --– 8 . 0 m A IOL --8 . 0 m A Middle drive*2 VCC = 3.0 to 5.5 V IOH --– 2 0 . 0 m A IOL --2 0 . 0 m A Other output pins*3 Low drive* 1 IOH --– 4 . 0 m A IOL --4 . 0 m A Middle drive*2 IOH --– 8 . 0 m A IOL --8 . 0 m A Permissible output current (max value total pins) Total of ports P000 to P004, P010 to P015 ΣIOH (max) --– 3 0 m A ΣIOL (max) --3 0m A Total of all output pin ΣIOH (max) --– 6 0 m A ΣIOL (max) --6 0m A

R01DS0264EU0100 Rev.1.00 Page 25 of 95 Feb 23, 2016 S124 2. Electrical Characteristics

2.2.4 I/O V OH, VOL, and Other Characteristics

Note 1. SCL0_A, SDA0_A, SCL0_B, SDA0_B, SCL1_ A, SDA1_A, SCL1_B, SDA1_B (total 8 pins). Note 2. This is the value when middle driving ability is sele cted with the port drive capability bit in the PmnPFS register. Note 3. Based on characterization data, not tested in production. Note 4. Except for Ports P200, P2 14, P215, which are input ports. Note 1. SCL0_A, SDA0_A, SCL0_B, SDA0_B, SCL1_ A, SDA1_A, SCL1_B, SDA1_B (total 8 pins). Note 2. This is the value when middle driving ability is sele cted with the port drive capability bit in the PmnPFS register. Note 3. Based on characterization data, not tested in production. Note 4. Except for Ports P200, P2 14, P215, which are input ports. Table 2.7 I/O V OH, VOL (1) Conditions: VCC = AVCC0 = 4.0 to 5.5 V Item Symbol Min Typ Max Unit Test conditions Output voltage IIC* 1, *2 VOL -- 0 . 4 V I OL = 3.0 mA VOL -- 0 . 6 I OL = 6.0 mA Ports P408, P409*2, *3 VOH VCC – 1.0 - - I OH = –20 mA VOL -- 1 . 0 I OL = 20 mA Ports P000 to P004 P010 to P015 Low drive V OH AVCC0 – 0.8 -I OH = –2.0 mA VOL -- 0 . 8 I OL = 2.0 mA Middle drive V OH AVCC0 – 0.8 -I OH = –4.0 mA VOL -- 0 . 8 I OL = 4.0 mA Other output pins*4 Low drive V OH VCC – 0.8 - - I OH = –2.0 mA VOL -- 0 . 8 I OL = 2.0 mA Middle drive V OH VCC – 0.8 - - I OH = –4.0 mA VOL -- 0 . 8 I OL = 4.0 mA Table 2.8 I/O V OH, VOL (2) Conditions: VCC = AVCC0 = 2.7 to 4.0 V Item Symbol Min Typ Max Unit Test conditions Output voltage IIC* 1, *2 VOL -- 0 . 4 V I OL = 3.0 mA VOL -- 0 . 6 I OL = 6.0 mA Ports P408, P409*2, *3 VOH VCC – 1.0 - - I OH = –20 mA VCC = 3.3 V VOL -- 1 . 0 I OL = 20 mA VCC = 3.3 V Ports P000 to P004 P010 to P015 Low drive V OH AVCC0 – 0.5 -- I OH = –1.0 mA VOL -- 0 . 5 I OL = 1.0 mA Middle drive V OH AVCC0 – 0.5 -- I OH = –2.0 mA VOL -- 0 . 5 I OL = 2.0 mA Other output pins*4 Low drive V OH VCC – 0.5 - - I OH = –1.0 mA VOL -- 0 . 5 I OL = 1.0 mA Middle drive V OH VCC – 0.5 - - I OH = –2.0 mA VOL -- 0 . 5 I OL = 2.0 mA

R01DS0264EU0100 Rev.1.00 Page 26 of 95 Feb 23, 2016 S124 2. Electrical Characteristics Note 1. Except for Ports P200, P2 14, P215, which are input ports. Table 2.9 I/O V OH, VOL (3) Conditions: VCC = AVCC0 = 1.6 to 2.7 V Item Symbol Min Typ Max Unit Test conditions Output voltage Ports P000 to P004 P010 to P015 Low drive V OH AVCC0 – 0.3 -- I OH = –0.5 mA VOL -- 0 . 3 I OL = 0.5 mA Middle drive V OH AVCC0 – 0.3 -- I OH = –1.0 mA VOL -- 0 . 3 I OL = 1.0 mA Other output pins*1 Low drive V OH VCC – 0.3 - - V I OH = –0.5 mA VOL -- 0 . 3 I OL = 0.5 mA Middle drive V OH VCC – 0.3 - - I OH = –1.0 mA VOL -- 0 . 3 I OL = 1.0 mA Table 2.10 I/O other characteristics Conditions: VCC = AVCC0 = 1.6 to 5.5 V Item Symbol Min Typ Max Unit Test conditions Input leakage current RES, Ports P200, P214, P215 | I in | - - 1.0 μAV in = 0 V Vin = VCC Three-state leakage current (off state) 5V-tolerant ports | I TSI | - - 1.0 μAV in = 0 V Vin = 5.8 V Other ports - - 1.0 V in = 0 V Vin = VCC Input pull-up resistor All ports (except for P200, P214, P215) RU 10 20 50 k Ω Vin = 0 V Input capacitance USB_DP , USB_DM, P200 C in - - 30 pF V in = 0 V f = 1 MHz Ta = 25°COther input pins - - 15

R01DS0264EU0100 Rev.1.00 Page 27 of 95 Feb 23, 2016 S124 2. Electrical Characteristics

2.2.5 I/O Pin Output Characte ristics of Low Drive Capacity

Figure 2.2 V OH/VOL and IOH/IOL Voltage Characteristics at Ta = 25°C When Low drive output is Selected (Reference Data) Figure 2.3 V OH/VOL and IOH/IOL Temperature Characteristics at VCC = 1.6 V When Low drive output is Selected (Reference Data) 0123456 -60 -50 -40 -30 -20 -10 I OH/IOL vs VOH/VOL VOH/VOL [V] IOH/IOL [mA] VCC = 5.5 V VCC = 3.3 V VCC = 2.7 V VCC = 1.6 V VCC = 1.6 V VCC = 2.7 V VCC = 3.3 V VCC = 5.5 V IOH/IOL vs VOH/VOL VOH/VOL [V] IOH/IOL [mA] Ta = -40°C Ta = 105°C Ta = 25°C Ta = 105°C Ta = -40°C Ta = 25°C

R01DS0264EU0100 Rev.1.00 Page 29 of 95 Feb 23, 2016 S124 2. Electrical Characteristics Figure 2.6 V OH/VOL and IOH/IOL Temperature Characteristics at VCC = 5.5 V When Low drive output is Selected (Reference Data)

2.2.6 I/O Pin Output Characteri stics of Middle Drive Capacity

Figure 2.7 V OH/VOL and IOH/IOL Voltage Characteristics at Ta = 25°C When Middle drive output is Selected (Reference Data) 0123456 -60 -40 -20 I OH/IOL vs VOH/VOL VOH/VOL [V] IOH/IOL [mA] Ta = -40°C Ta = 105°C Ta = 25°C Ta = 105°C Ta = -40°C Ta = 25°C 0123456 -140 -120 -100 -80 -60 -40 -20 100 120 140 I OH/IOL vs VOH/VOL VOH/VOL [V] IOH/IOL [mA] VCC = 5.5 V VCC = 3.3 V VCC = 2.7 V VCC = 1.6 V VCC = 1.6 V VCC = 2.7 V VCC = 3.3 V VCC = 5.5 V

R01DS0264EU0100 Rev.1.00 Page 32 of 95 Feb 23, 2016 S124 2. Electrical Characteristics

2.2.7 P408, P409 I/O Pin Ou tput Characteristics of Middle Drive Capacity

Figure 2.12 V OH/VOL and IOH/IOL Voltage Characteristics at Ta = 25°C When Middle drive output is Selected (Reference Data) Figure 2.13 V OH/VOL and IOH/IOL Temperature Characteristics at VCC = 2.7 V When Low drive output is Selected (Reference Data) 0123456 IOH/IOL vs VOH/VOL VOH/VOL [V] IOH/IOL [mA] VCC = 5.5 V VCC = 3.3 V VCC = 2.7 V VCC = 2.7 V VCC = 3.3 V VCC = 5.5 V -140 -120 -100 -80 -60 -40 -20 100 120 140 200 180 160 -160 -180 -200 0 0.5 1 1.5 2 2.5 3 -60 -40 -20 IOH/IOL vs VOH/VOL VOH/VOL [V] IOH/IOL [mA] Ta = -40°C Ta = 105°C Ta = 25°C Ta = 105°C Ta = -40°C Ta = 25°C

R01DS0264EU0100 Rev.1.00 Page 34 of 95 Feb 23, 2016 S124 2. Electrical Characteristics

2.2.8 IIC I/O Pin Out put Characteristics

Figure 2.16 V OH/VOL and IOH/IOL Voltage Characteristics at Ta = 25°C 0123456 100 110 120 IOL vs VOL VOL [V] IOL [mA] VCC = 2.7V (Low drive) VCC = 3.3V (Low drive) VCC = 5.5V (Low drive) VCC = 5.5 V (Middle drive) VCC = 3.3V (Middle drive) VCC = 2.7V (Middle drive)

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2.2.9 Operating and Standby Current

Table 2.11 Operating and standby current (1) (1/2) Conditions: VCC = AVCC0 = 1.6 to 5.5 V Item Symbol Typ* 9 Max Unit Test Conditions Supply current*1 High-speed mode* Normal mode All peripheral clock disabled, code executing from flash*5 ICLK = 32 MHz I CC 3.6 - mA * 7 ICLK = 16 MHz 2.4 - ICLK = 8 MHz 1.7 - All peripheral clock disabled, CoreMark code executing from flash*5 ICLK = 32 MHz 5.6 - ICLK = 16 MHz 3.5 - ICLK = 8 MHz 2.4 - All peripheral clock enabled, code executing from flash*5 ICLK = 32 MHz 9.5 - * 8 ICLK = 16 MHz 5.4 - ICLK = 8 MHz 3.3 - All peripheral clock enabled, code executing from flash*5 ICLK = 32 MHz - 21.0 Sleep mode All peripheral clock disabled*5 ICLK = 32 MHz 1.5 - * 7 ICLK = 16 MHz 1.1 - ICLK = 8 MHz 0.9 - All peripheral clock enabled*5 ICLK = 32 MHz 7.2 - * 8 ICLK = 16 MHz 4.0 - ICLK = 8 MHz 2.4 - Increase during BGO operation*6 2.5 - - Middle-speed mode*2 Normal mode All peripheral clock disabled, code executing from flash* ICLK = 12 MHz I CC 1.7 - mA * 7 ICLK = 8 MHz 1.5 - All peripheral clock disabled, CoreMark code executing from flash* ICLK = 12 MHz 2.7 - ICLK = 8 MHz 1.9 - All peripheral clock enabled, code executing from flash* ICLK = 12 MHz 3.9 - * 8 ICLK = 8 MHz 3.0 - All peripheral clock enabled, code executing from flash* ICLK = 12 MHz - 8.0 Sleep mode All peripheral clock disabled*5 ICLK = 12 MHz 0.8 - * 7 ICLK = 8 MHz 0.8 - All peripheral clock enabled*5 ICLK = 12 MHz 2.9 - * 8 ICLK = 8 MHz 2.2 - Increase during BGO operation*6 2.5 - - Low-speed mode*3 Normal mode All peripheral clock disabled, code executing from flash*5 ICLK = 1 MHz I CC 0.2 - mA * 7 All peripheral clock disabled, CoreMark code executing from flash*5 ICLK = 1 MHz 0.3 - All peripheral clock enabled, code executing from flash*5 ICLK = 1 MHz 0.4 - * 8 All peripheral clock enabled, code executing from flash*5 ICLK = 1 MHz - 2.0 Sleep mode All peripheral clock disabled*5 ICLK = 1 MHz 0.2 - * 7 All peripheral clock enabled*5 ICLK = 1 MHz 0.3 - * 8

R01DS0264EU0100 Rev.1.00 Page 36 of 95 Feb 23, 2016 S124 2. Electrical Characteristics Note 1. Supply current values do not include output ch arge/discharge current from all pins. The values apply when internal pull-up MOSs are in the off state. Note 2. The clock source is HOCO. Note 3. The clock source is MOCO. Note 4. The clock source is the sub-clock oscillator. Note 5. This does not include BGO operation. Note 6. This is the increase for programming or erasure of the ROM or flash memory for data storage during program execution. Note 7. PCLKB and PCLKD are set to divided by 64. Note 8. PCLKB and PCLKD are the same frequency as that of ICLK. Note 9. VCC = 3.3 V. Note 1. Supply current values do not include output ch arge/discharge current from all pins. The values apply when internal pull-up MOS transistors are in the off state. Note 2. The IWDT and LVD are not operating. Supply current*1 Low-voltage mode* Normal mode All peripheral clock disabled, code executing from flash*5 ICLK = 4 MHz I CC 1.4 - mA * 7 All peripheral clock disabled, CoreMark code executing from flash*5 ICLK = 4 MHz 1.4 - All peripheral clock enabled, code executing from flash*5 ICLK = 4 MHz 2.1 - * 8 All peripheral clock enabled, code executing from flash*5 ICLK = 4 MHz - 4.0 Sleep mode All peripheral clock disabled*5 ICLK = 4 MHz 0.9 - * 7 All peripheral clock enabled* ICLK = 4 MHz 1.6 - * 8 Subosc- speed mode*4 Normal mode All peripheral clock disabled, code executing from flash*5 ICLK = 32.768 kHz I CC 5.9 - μA* 7 All peripheral clock enabled, code executing from flash*5 ICLK = 32.768 kHz 13.0 - * 8 All peripheral clock enabled, code executing from flash*5 ICLK = 32.768 kHz - 55.0 Sleep mode All peripheral clock disabled*5 ICLK = 32.768 kHz 3.2 - * 7 All peripheral clock enabled* ICLK = 32.768 kHz 10.0 - * 8 Table 2.12 Operating and standby current (2) Conditions: VCC = AVCC0 = 1.6 to 5.5 V Item Symbol Typ* 3 Max Unit Test conditions Supply current*1 Software Standby mode* Ta = 25°C I CC 0.4 1.5 μA- Ta = 55°C 0.6 5.5 Ta = 85°C 1.2 10.0 Ta = 105°C 2.6 40.0 Increment for RTC operation with low-speed on-chip oscillator*4 0.4 - - Increment for RTC operation with sub-clock oscillator*4 0.5 - SOMCR.SODRV[1:0] are 11b (Low power mode 3) 1.3 - SOMCR.SODRV[1:0] are 00b (Normal mode) Table 2.11 Operating and standby current (1) (2/2) Conditions: VCC = AVCC0 = 1.6 to 5.5 V Item Symbol Typ* 9 Max Unit Test Conditions

R01DS0264EU0100 Rev.1.00 Page 37 of 95 Feb 23, 2016 S124 2. Electrical Characteristics Note 3. VCC = 3.3 V. Note 4. Includes the current of low-speed on -chip oscillator or sub-oscillation circuit. Note 1. The reference power supply current is included in the power supply current value for D/A conversion. Note 2. Current is consumed only by the USBFS. Note 3. Includes the current supplied from the pull-up resistor of the USB_DP pin to the pull-down resistor of the host device, in addition to the current consumed by the MCU in the suspended state. Note 4. When VCC = VCC_USB = 3.3 V. Table 2.13 Operating and standby current (3) Conditions: VCC = AVCC0 = 1.6 to 5.5 V Item Symbol Min Typ Max Unit Test conditions Analog power supply current During A/D conversion (at high-speed conversion) I AVCC -- 3 . 0 m A - During A/D conversion (at low-power conversion) - - 1.0 mA - During D/A conversion* 1 -0 . 4 0 . 8 m A - Waiting for A/D and D/A conversion (all units) - - 1.0 μA- Reference power supply current During A/D conversion (at high-speed conversion) I REFH0 - - 150 μA- Waiting for A/D conversion (all units) - - 60 nA - Temperature sensor I TNS -7 5 - μA- Low-power analog comparator (ACMPLP) operating current Window mode I CMPLP -1 5 - μA- Comparator high-speed mode - 10 - μA- Comparator low-speed mode - 2 - μA- USB operating current During USB communication under the following settings and conditions:  Function controller is in Full-Speed mode and - Bulk OUT transfer is (64 bytes) × 1 - Bulk IN transfer is (64 bytes) × 1  Host device is connected by a 1-meter USB cable from the USB port. IUSBF*2 - 3.6 (VCC) 1.1 (VCC_USB)*4 -m A - During suspended state under the following setting and conditions:  Function controller is in Full-Speed mode (the USB_DP pin is pulled up)  Software Standby mode  Host device is connected by a 1-meter USB cable from the USB port. ISUSP*3 - 0.35 (VCC) 170 (VCC_USB)*4 - μA-

R01DS0264EU0100 Rev.1.00 Page 38 of 95 Feb 23, 2016 S124 2. Electrical Characteristics

2.2.10 VCC Rise and Fall Gr adient and Ripple Frequency

Note 1. When OFS1.LVDAS = 0. Note 2. Turn the power supply voltage on according to the normal startup rising gradient because the register settings set by OFS1 are not read in boot mode. Figure 2.17 Ripple waveform Table 2.14 Rise and fall gradient characteristics Conditions: VCC = AVCC0 = 0 to 5.5 V Item Symbol Min Typ Max Unit Test conditions Power-on VCC rising gradient Voltage monitor 0 reset disabled at startup SrVCC 0.02 - 2m s / V - Voltage monitor 0 reset enabled at startup*1, *2 0.02 - - Table 2.15 Rising and falling gradient and ripple frequency characteristics Conditions: VCC = AVCC0 = 1.6 to 5.5 V The ripple voltage must meet the allowable ripple frequency fr(VCC) within the range between the VCC upper limit (5.5 V) and lower limit (1.6 V). When the VCC change exceeds VCC ±10%, the allowable voltage change rising and falling gradient dt/dVCC must be met. Item Symbol Min Typ Max Unit Test conditions Allowable ripple frequency f r (VCC) -- 10 kHz Figure 2.17 Vr (VCC) ≤ VCC × 0.2 -- 1 MHz Figure 2.17 Vr (VCC) ≤ VCC × 0.08 -- 10 MHz Figure 2.17 Vr (VCC) ≤ VCC × 0.06 Allowable voltage change rising and falling gradient dt/dVCC 1.0 - - ms/V When VCC change exceeds VCC ±10% Vr(VCC)VCC 1/fr(VCC)

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2.3 AC Characteristics

2.3.1 Frequency

Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory. When using ICLK for programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note 2. The frequency accuracy of ICLK must be ±3.5% while programming or erasing the flash memory. Confirm the frequency accuracy of the clock source. Note 3. The lower-limit frequency of PCLKD is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D converter is in use. Note 4. See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK, PCLKB, and PCLKD. Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory. When using ICLK for programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note 2. The frequency accuracy of ICLK must be ±3.5% while programming or erasing the flash memory. Confirm the frequency accuracy of the clock source. Note 3. The lower-limit frequency of PCLKD is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D converter is in use. Note 4. See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK, PCLKB, and PCLKD. Table 2.16 Operation frequency in high-speed operating mode Conditions: VCC = AVCC0 = 2.4 to 5.5 V Item Symbol Min Typ Max Unit Operation frequency System clock (ICLK)*1, *2, *4 2.7 to 5.5 V f 0.032768 - 32 MHz 2.4 to 2.7 V 0.032768 - 16 Peripheral module clock (PCLKB)*4 2.7 to 5.5 V - - 32 2.4 to 2.7 V - - 16 Peripheral module clock (PCLKD)* 2.7 to 5.5 V - - 64 2.4 to 2.7 V - - 16 Table 2.17 Operation frequency in middle-speed mode Conditions: VCC = AVCC0 = 1.8 to 5.5 V Item Symbol Min Typ Max Unit Operation frequency System clock (ICLK)*1, *2, *4 2.7 to 5.5 V f 0.032768 - 12 MHz 2.4 to 2.7 V 0.032768 - 12 1.8 to 2.4 V 0.032768 - 8 Peripheral module clock (PCLKB)* 4 2.7 to 5.5 V - - 12 2.4 to 2.7 V - - 12 1.8 to 2.4 V - - 8 Peripheral module clock (PCLKD)* 3, *4 2.7 to 5.5 V - - 12 2.4 to 2.7 V - - 12 1.8 to 2.4 V - - 8

R01DS0264EU0100 Rev.1.00 Page 40 of 95 Feb 23, 2016 S124 2. Electrical Characteristics Note 1. The lower-limit frequency of ICLK is 1 MH z while programming or erasing the flash memory. Note 2. The frequency accuracy of ICLK must be ±3.5% while programming or erasing the flash memory. Confirm the frequency accuracy of the clock source. Note 3. The lower-limit frequency of PCLKD is 1 MHz when the A/D converter is in use. Note 4. See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK, PCLKB, and PCLKD. Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory. When using ICLK for programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note 2. The frequency accuracy of ICLK must be ±3.5% while programming or erasing the flash memory. Confirm the frequency accuracy of the clock source. Note 3. The lower-limit frequency of PCLKD is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D converter is in use. Note 4. See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK, PCLKB, and PCLKD. Note 1. Programming and erasing the flash memory is not possible. Note 2. The 14-bit A/D converter cannot be used. Note 3. See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK, PCLKB, and PCLKD. Table 2.18 Operation frequency in low-speed mode Conditions: VCC = AVCC0 = 1.8 to 5.5 V Item Symbol Min Typ Max Unit Operation frequency System clock (ICLK)*1, *2, *4 1.8 to 5.5 V f 0.032768 - 1 MHz Peripheral module clock (PCLKB)*4 1.8 to 5.5 V - - 1 Peripheral module clock (PCLKD)*3, *4 1.8 to 5.5 V - - 1 Table 2.19 Operation frequency in low-voltage mode Conditions: VCC = AVCC0 = 1.6 to 5.5 V Item Symbol Min Typ Max Unit Operation frequency System clock (ICLK)*1, *2, *4 1.6 to 5.5 V f 0.032768 - 4 MHz Peripheral module clock (PCLKB)*4 1.6 to 5.5 V - - 4 Peripheral module clock (PCLKD)*3, *4 1.6 to 5.5 V - - 4 Table 2.20 Operation frequency in Subosc-speed mode Conditions: VCC = AVCC0 = 1.8 to 5.5 V Item Symbol Min Typ Max Unit Operation frequency Peripheral module clock (PCLKB)*3 1.8 to 5.5 V - - 37.6832 Peripheral module clock (PCLKD)*2, *3 1.8 to 5.5 V - - 37.6832

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2.3.2 Clock Timing

Table 2.21 Clock timing (1/2) Item Symbol Min Typ Max Unit Test conditions EXTAL external clock input cycle time t Xcyc 50 - - ns Figure 2.18 EXTAL external clock input high pulse width t XH 20 - - ns EXTAL external clock input low pulse width t XL 20 - - ns EXTAL external clock rising time t Xr --5 n s EXTAL external clock falling time t Xf --5 n s EXTAL external clock input wait time*1 tEXWT 0.3 - - μs- EXTAL external clock input frequency f EXTAL --2 0 M H z 2 . 4 ≤ VCC ≤ 5.5 Main clock oscillator oscillation frequency f MAIN 1- 2 0 M H z 2.4 ≤ VCC ≤ 5.5 1- 8 1.8 ≤ VCC < 2.4 1- 4 1.6 ≤ VCC < 1.8 LOCO clock oscillation frequency f LOCO 27.8528 32.768 37.6832 kHz - LOCO clock oscillation stabilization time t LOCO - - 100 μs Figure 2.19 IWDT-dedicated clock oscillation frequency f ILOCO 12.75 15 17.25 kHz - MOCO clock oscillation frequency f MOCO 6.8 8 9.2 MHz - MOCO clock oscillation stabilization time t MOCO --1 μs- HOCO clock oscillation frequency f HOCO24 23.64 24 24.36 MHz Ta = –40 to –20°C 1.8 ≤ VCC ≤ 5.5 22.68 24 25.32 Ta = –40 to 85°C 1.6 ≤ VCC < 1.8 23.76 24 24.24 Ta = –20 to 85°C 1.8 ≤ VCC ≤ 5.5 23.52 24 24.48 Ta = 85 to 105°C 2.4 ≤ VCC ≤ 5.5 fHOCO32 31.52 32 32.48 Ta = –40 to –20°C 1.8 ≤ VCC ≤ 5.5 30.24 32 33.76 Ta = –40 to 85°C 1.6 ≤ VCC < 1.8 31.68 32 32.32 Ta = –20 to 85°C 1.8 ≤ VCC ≤ 5.5 31.36 32 32.64 Ta = 85 to 105°C 2.4 ≤ VCC ≤ 5.5 fHOCO48*3 47.28 48 48.72 Ta = –40 to –20°C 1.8 ≤ VCC ≤ 5.5 47.52 48 48.48 Ta = –20 to 85°C 1.8 ≤ VCC ≤ 5.5 47.04 48 48.96 Ta = –40 to 105°C 2.4 ≤ VCC ≤ 5.5 fHOCO64*4 63.04 64 64.96 Ta = –40 to –20°C 2.4 ≤ VCC ≤ 5.5 63.36 64 64.64 Ta = –20 to 85°C 2.4 ≤ VCC ≤ 5.5 62.72 64 65.28 Ta = 85 to 105°C 2.4 ≤ VCC ≤ 5.5 HOCO clock oscillation stabilization time*5, *6 Except low- voltage mode tHOCO24 tHOCO32 - - 37.1 μs Figure 2.20 tHOCO48 - - 43.3 tHOCO64 - - 80.6 Low-voltage mode tHOCO24 tHOCO32 tHOCO48 tHOCO64 - - 100.9 Sub-clock oscillator oscillation frequency f SUB - 32.768 - kHz -

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2.3.3 Reset Timing

Note 1. When OFS1.LVDAS = 0. Note 2. When OFS1.LVDAS = 1. Note 3. When IWDTCR.CKS[3:0] = 0000b. Figure 2.22 Reset input timing at power-on Figure 2.23 Reset input timing (1) Table 2.22 Reset timing Item Symbol Min Typ Max Unit Test conditions RES pulse width At power-on t RESWP 3- - m s Figure 2.22 Not at power-on t RESW 30 - - μs Figure 2.23 Wait time after RES cancellation (at power-on) LVD0 enabled*1 tRESWT -0 . 7 -m s Figure 2.22 LVD0 disabled*2 -0 . 3 - Wait time after RES cancellation (during powered-on state) LVD0 enabled*1 tRESWT2 -0 . 5 - μs Figure 2.23 LVD0 disabled*2 -0 . 0 5 - Reset period IWDT* 3 tRESWIW -1 -I W D T clock cycle Figure 2.24 Internal reset (except IWDT) t RESWIR -1 -I C L K cycle Wait time after internal reset cancellation LVD0 enabled* 1 tRESWT3 -0 . 5 - μs LVD0 disabled*2 -0 . 0 5 - VCC RES tRESWP Internal reset tRESWT RES Internal reset tRESWT2 tRESW

R01DS0264EU0100 Rev.1.00 Page 44 of 95 Feb 23, 2016 S124 2. Electrical Characteristics Figure 2.24 Reset input timing (2) Independent watchdog timer reset Software reset Internal reset tRESWT3 tRESWIW, tRESWIR

R01DS0264EU0100 Rev.1.00 Page 45 of 95 Feb 23, 2016 S124 2. Electrical Characteristics

2.3.4 Wakeup Time

Note 1. The division ratio of ICLK and PCLKx is 1. The recovery time is determined by the system clock source. Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h. Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h. Note 4. The HOCO clock wait control register (HOCOWTCR) is set to 05h. Note 5. The HOCO clock wait control register (HOCOWTCR) is set to 06h. Note 1. The division ratio of ICLK and PCLKx is 1. The recovery time is determined by the system clock source. Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h. Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h. Note 4. The system clock is 12 MHz. Table 2.23 Timing of recovery from low power modes (1) Item Symbol Min Typ Max Unit Test conditions Recovery time from Software Standby mode*1 High-speed mode Crystal resonator connected to main clock oscillator System clock source is main clock oscillator (20 MHz) tSBYMC -2 3m s Figure 2.25 External clock input to main clock oscillator System clock source is main clock oscillator (20 MHz) tSBYEX -1 4 25 μs System clock source is HOCO*4 (HOCO clock is 32 MHz) tSBYHO - 43 52 μs System clock source is HOCO*4 (HOCO clock is 48 MHz) tSBYHO - 44 52 μs System clock source is HOCO*5 (HOCO clock is 64 MHz) tSBYHO - 82 110 μs System clock source is MOCO t SBYMO - 16 25 μs Table 2.24 Timing of recovery from low power modes (2) Item Symbol Min Typ Max Unit Test conditions Recovery time from Software Standby mode*1 Middle-speed mode Crystal resonator connected to main clock oscillator System clock source is main clock oscillator (12 MHz) tSBYMC - 23 m s Figure 2.25 External clock input to main clock oscillator System clock source is main clock oscillator (12 MHz)*3 tSBYEX - 2.9 10 μs System clock source is HOCO*4 tSBYHO - 38 50 μs System clock source is MOCO (8 MHz) t SBYMO - 3.5 5.5 μs

R01DS0264EU0100 Rev.1.00 Page 46 of 95 Feb 23, 2016 S124 2. Electrical Characteristics Note 1. The division ratio of ICLK and PCLKx is 1. The recovery time is determined by the system clock source. Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h. Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h. Note 1. The division ratio of ICLK and PCLKx is 1. The recovery time is determined by the system clock source. Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h. Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h. Note 1. The sub-clock oscillator or LOCO itself continues oscillating in Software Standby mode during Subosc-speed mode. Table 2.25 Timing of recovery from low power modes (3) Item Symbol Min Typ Max Unit Test conditions Recovery time from Software Standby mode*1 Low-speed mode Crystal resonator connected to main clock oscillator System clock source is main clock oscillator (1 MHz) tSBYMC - 23m s Figure 2.25 External clock input to main clock oscillator System clock source is main clock oscillator (1 MHz)*3 tSBYEX - 28 50 μs System clock source is MOCO (1 MHz) t SBYMO - 25 35 μs Table 2.26 Timing of recovery from low power modes (4) Item Symbol Min Typ Max Unit Test conditions Recovery time from Software Standby mode*1 Low-voltage mode Crystal resonator connected to main clock oscillator System clock source is main clock oscillator (4 MHz)*2 tSBYMC - 23m s Figure 2.25 External clock input to main clock oscillator System clock source is main clock oscillator (4 MHz)*3 tSBYEX - 108 130 μs System clock source is HOCO (4 MHz) tSBYHO - 108 130 μs Table 2.27 Timing of recovery from low power modes (5) Item Symbol Min Typ Max Unit Test conditions Recovery time from Software Standby mode* SubOSC-speed mode System clock source is sub-clock oscillator (32.768 kHz) tSBYSC -0 . 8 5 1m s Figure 2.25 System clock source is LOCO (32.768 kHz) tSBYLO - 0.85 1.2 ms

R01DS0264EU0100 Rev.1.00 Page 47 of 95 Feb 23, 2016 S124 2. Electrical Characteristics Figure 2.25 Software Standby mode cancellation timing Table 2.28 Timing of recovery from low power modes (6) Item Symbol Min Typ Max Unit Test conditions Recovery time from Software Standby mode to Snooze High-speed mode System clock source is HOCO tSNZ -3 6 4 5 μs- Middle-speed mode System clock source is MOCO (8 MHz) tSNZ -1 . 3 3 . 6 μs Low-speed mode System clock source is MOCO (1 MHz) tSNZ -1 0 1 3 μs Low-voltage mode System clock source is HOCO (4 MHz) t SNZ -8 7 1 1 0 μs Oscillator ICLK IRQ Software Standby mode tSBYSC, tSBYLO Oscillator ICLK IRQ Software Standby mode tSBYMC, tSBYEX, tSBYMO, tSBYHO

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2.3.5 NMI and IRQ Noise Filter

Note: 200 ns minimum in Software Standby mode. Note 1. t Pcyc indicates the PCLKB cycle. Note 2. t NMICK indicates the cycle of the NMI digital filter sampling clock. Note 3. t IRQCK indicates the cycle of the IRQi digital filter sampling clock (i = 0 to 7). Figure 2.26 NMI interrupt input timing Figure 2.27 IRQ interrupt input timing Table 2.29 NMI and IRQ noise filter Item Symbol Min Typ Max Unit Test conditions NMI pulse width t NMIW 200 -- ns NMI digital filter disabled t Pcyc × 2 ≤ 200 ns tPcyc × 2*1 -- tPcyc × 2 > 200 ns 200 -- NMI digital filter enabled t NMICK × 3 ≤ 200 ns tNMICK × 3.5*2 -- tNMICK × 3 > 200 ns IRQ pulse width t IRQW 200 -- ns IRQ digital filter disabled t Pcyc × 2 ≤ 200 ns tPcyc × 2*1 -- tPcyc × 2 > 200 ns 200 -- IRQ digital filter enabled t IRQCK × 3 ≤ 200 ns tIRQCK × 3.5*3 -- tIRQCK × 3 > 200 ns tNMIW NMI tIRQW IRQ

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2.3.6 I/O Ports, POEG , GPT, AGT, KINT, and ADC14 Trigger Timing

Note 1. Constraints on AGTIO input: t Pcyc × 2 (tPcyc: PCLKB cycle) < tACYC. Figure 2.28 I/O ports input timing Figure 2.29 POEG in put trigger timing Figure 2.30 GPT input capture timing Table 2.30 I/O Ports, PO EG, GPT, AGT, KINT, and ADC14 trigger timing Item Symbol Min Max Unit Test conditions I/O Ports Input data pulse width t PRW 1.5 - tPcyc Figure 2.28 POEG POEG input trigger pulse width t POEW 3 - tPcyc Figure 2.29 GPT Input capture pulse width Single edge t GTICW 1.5 - tPDcyc Figure 2.30 Dual edge 2.5 - AGT AGTIO, AGTEE input cycle 2.7 V ≤ VCC ≤ 5.5 V t ACYC*1 250 - ns Figure 2.31 2.4 V ≤ VCC < 2.7 V 500 - ns 1.8 V ≤ VCC < 2.4 V 1000 - ns 1.6 V ≤ VCC < 1.8 V 2000 - ns AGTIO, AGTEE input high level width, low-level width 2.7 V ≤ VCC ≤ 5.5 V t ACKWH, tACKWL 100 - ns 2.4 V ≤ VCC < 2.7 V 200 - ns 1.8 V ≤ VCC < 2.4 V 400 - ns 1.6 V ≤ VCC < 1.8 V 800 - ns AGTIO, AGTO, AGTOA, AGTOB output frequency 2.7 V ≤ VCC ≤ 5.5 V t ACYC2 62.5 - ns Figure 2.31 2.4 V ≤ VCC < 2.7 V 125 - ns 1.8 V ≤ VCC < 2.4 V 250 - ns 1.6 V ≤ VCC < 1.8 V 500 - ns ADC14 14-bit A/D converter trigger input pulse width t TRGW 1.5 - tPcyc Figure 2.32 KINT Key interrupt input low-level width t KR 250 - ns Figure 2.33 Port tPRW POEG input trigger tPOEW Input capture tGTICW

R01DS0264EU0100 Rev.1.00 Page 50 of 95 Feb 23, 2016 S124 2. Electrical Characteristics Figure 2.31 AGT I/O timing Figure 2.32 ADC14 trigger input timing Figure 2.33 Key inte rrupt input timing

2.3.7 CAC Timing

Note 1. t PBcyc: PCLKB cycle. Note 2. t cac: CAC count clock source cycle. Table 2.31 CAC timing Item Symbol Min Typ Max Unit Test conditions CAC CACREF input pulse width t PBcyc ≤ tcac*2 tCACREF 4.5 × tcac + 3 × tPBcyc -- ns - tPBcyc > tcac*2 5 × tcac + 6.5 × tPBcyc -- ns tACYC2 AGTIO, AGTEE (input) tACYC tACKWL tACKWH AGTIO, AGTO, AGTOA, AGTOB (output) ADTRG0 tTRGW KR00 to KR07 tKR

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2.3.8 SCI Timing

Note 1. t Pcyc: PCLKB cycle. Table 2.32 SCI timing (1) Conditions: VCC = AVCC0 = 1.6 to 5.5 V Item Symbol Min Max Unit *1 Test conditions SCI Input clock cycle Asynchronous t Scyc 4 - tPcyc Figure 2.34 Clock synchronous 6 - Input clock pulse width t SCKW 0.4 0.6 t Scyc Input clock rise time t SCKr -2 0 n s Input clock fall time t SCKf -2 0 n s Output clock cycle Asynchronous t Scyc 6 - tPcyc Clock synchronous 4 - Output clock pulse width t SCKW 0.4 0.6 t Scyc Output clock rise time 1.8V or above t SCKr -2 0 n s 1.6V or above - 30 Output clock fall time 1.8V or above t SCKf -2 0 n s 1.6V or above - 30 Transmit data delay (master) Clock synchro nous 1.8V or above t TXD -4 0 n s Figure 2.35 1.6V or above - 45 Transmit data delay (slave) Clock synchro nous 2.7V or above - 55 ns 2.4V or above - 60 1.8V or above - 100 1.6V or above - 125 Receive data setup time (master) Clock synchro nous 2.7V or above t RXS 45 - ns 2.4V or above 55 - 1.8V or above 90 - 1.6V or above 110 - Receive data setup time (slave) Clock synchro nous 2.7V or above 40 - ns 1.6V or above 45 - Receive data hold time (master) Clock synchronous t RXH 5 - ns Receive data hold time (slave) Clock synchronous t RXH 40 - ns

R01DS0264EU0100 Rev.1.00 Page 53 of 95 Feb 23, 2016 S124 2. Electrical Characteristics Note 1. t Pcyc: PCLKB cycle Table 2.33 SCI timing (2) Conditions: VCC = AVCC0 = 1.6 to 5.5 V Item Symbol Min Max Unit* 1 Test conditions Simple SPI SCK clock cycle output (master) t SPcyc 4 65536 t Pcyc Figure 2.36 SCK clock cycle input (slave) 6 65536 SCK clock high pulse width t SPCKWH 0.4 0.6 t SPcyc SCK clock low pulse width t SPCKWL 0.4 0.6 t SPcyc SCK clock rise and fall time 1.8V or above tSPCKr, tSPCKf -2 0 n s 1.6V or above -3 0 Data input setup time Master 2.7V or above t SU 45 - ns Figure 2.37 to Figure 2.402.4V or above 55 - 1.8V or above 80 - 1.6V or above 110 - Slave 2.7V or above 40 - 1.6V or above 45 - Data input hold time Master t H 33.3 - ns Slave 40 - SS input setup time t LEAD 1- t SPcyc SS input hold time t LAG 1- t SPcyc Data output delay Master 1.8V or above t OD -4 0 n s 1.6V or above - 50 Slave 2.4V or above - 65 1.8V or above - 100 1.6V or above - 125 Data output hold time Master 2.7V or above t OH –10 - ns 2.4V or above –20 - 1.8V or above –30 - 1.6V or above –40 - Slave –10 - Data rise and fall time Master t Dr, tDf -2 0 n s Slave 1.8V or above - 20 1.6V or above - 30 Simple SPI Slave access time t SA -6t Pcyc Figure 2.40 Slave output release time t REL -6t Pcyc

R01DS0264EU0100 Rev.1.00 Page 56 of 95 Feb 23, 2016 S124 2. Electrical Characteristics Figure 2.40 SCI simple SPI mode timing (slave, CKPH = 0) Note: t IICcyc: IIC internal reference clock (IICφ) cycle. Note 1. Cb indicates the total capacity of the bus line. Table 2.34 SCI timing (3) Conditions: VCC = AVCC0 = 2.7 to 5.5 V Item Symbol Min Max Unit Test conditions Simple IIC (Standard mode) SDA input rise time t Sr - 1000 ns Figure 2.41 SDA input fall time t Sf - 300 ns SDA input spike pulse removal time t SP 04 × t IICcyc ns Data input setup time t SDAS 250 - ns Data input hold time t SDAH 0 - ns SCL, SDA capacitive load C b*1 - 400 pF Simple IIC (Fast mode) SCL, SDA input rise time t Sr - 300 ns Figure 2.41 SCL, SDA input fall time t Sf - 300 ns SCL, SDA input spike pulse removal time t SP 04 × t IICcyc ns Data input setup time t SDAS 100 - ns Data input hold time t SDAH 0 - ns SCL, SDA capacitive load C b*1 - 400 pF tDr, tDf tSA tOH tLEAD tTD tLAG tH LSB OUT (Last data) DATA MSB OUT MSB IN DATA LSB IN MSB IN LSB OUT tSU tOD tREL MSB OUT SSn input SCKn CKPOL = 1 input SCKn CKPOL = 0 input MISOn output MOSIn input (n = 0, 1, 9)

R01DS0264EU0100 Rev.1.00 Page 57 of 95 Feb 23, 2016 S124 2. Electrical Characteristics Figure 2.41 SCI simple IIC mode timing SDAn SCLn VIH VIL tSTAH tSCLH tSCLL P*1 S*1 tSf tSr tSCL tSDAH tSDAS tSTAS tSP tSTOS P*1 tBUF Sr*1 Note 1. S, P, and Sr indicate the following conditions: S: Start condition P: Stop condition Sr: Restart condition (n = 0, 1, 9)

R01DS0264EU0100 Rev.1.00 Page 58 of 95 Feb 23, 2016 S124 2. Electrical Characteristics

2.3.9 SPI Timing

Table 2.35 SPI timing (1/2) Conditions: Middle drive output is selected in the Drive Strength Control bit in the PmnPFS register. Item Symbol Min Max Unit *1 Test conditions SPI RSPCK clock cycle Master t SPcyc 2 4096 t Pcyc Figure 2.42 C = 30PFSlave 6 4096 RSPCK clock high pulse width Master t SPCKWH (tSPcyc – tSPCKR – tSPCKF) / 2 – 3 - ns Slave 3 × t Pcyc - RSPCK clock low pulse width Master t SPCKWL (tSPcyc – tSPCKR – tSPCKF) / 2 – 3 - ns Slave 3 × t Pcyc - RSPCK clock rise and fall time Output 2.7V or above t SPCKr, tSPCKf -1 0 n s 2.4V or above - 15 1.8V or above - 20 1.6V or above - 30 Input - 1 µs Data input setup time Master t SU 10 - ns Figure 2.43 to Figure 2.48 C = 30PFSlave 2.4V or above 10 - 1.8V or above 15 - 1.6V or above 20 - Data input hold time Master (RSPCK is PCLKB/2) t HF 0 - ns Master (RSPCK is not PCLKB/2) tH tPcyc - Slave t H 20 - SSL setup time Master t LEAD – 30 + N x tSpcyc*2 -n s Slave 6 x t Pcyc -n s SSL hold time Master t LAG – 30 + N x tSpcyc*3 -n s Slave 6 x t Pcyc -n s

R01DS0264EU0100 Rev.1.00 Page 63 of 95 Feb 23, 2016 S124 2. Electrical Characteristics Figure 2.48 SPI timing (slave, CPHA = 1) SSLA0 input RSPCKA CPOL = 0 input RSPCKA CPOL = 1 input MISOA output MOSIA input tDr, tDf tSA tOH tLEAD tTD tLAG tH LSB OUT (Last data) DATA MSB OUT MSB IN DATA LSB IN MSB IN LSB OUT tSU tOD tREL MSB OUT

R01DS0264EU0100 Rev.1.00 Page 64 of 95 Feb 23, 2016 S124 2. Electrical Characteristics

2.3.10 IIC Timing

Note: t IICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle Note 1. Values in parentheses apply when ICMR3.NF[1:0] is se t to 11b while the digital filter is enabled with ICFER.NFE Table 2.36 IIC timing Conditions: VCC = AVCC0 = 2.7 to 5.5 V Item Symbol Min* 1, *2 Max Unit Test conditions IIC (standard mode, SMBus) SCL input cycle time t SCL 6 (12) × tIICcyc + 1300 - ns Figure 2.49 SCL input high pulse width t SCLH 3 (6) × tIICcyc + 300 - ns SCL input low pulse width t SCLL 3 (6) × tIICcyc + 300 - ns SCL, SDA input rise time t Sr - 1000 ns SCL, SDA input fall time t Sf - 300 ns SCL, SDA input spike pulse removal time tSP 0 1 (4) × t IICcyc ns SDA input bus free time (When wakeup function is disabled) tBUF 3 (6) × tIICcyc + 300 - ns SDA input bus free time (When wakeup function is enabled) tBUF 3 (6) × tIICcyc + 4 × tPcyc + 300 - ns START condition input hold time (When wakeup function is disabled) tSTAH tIICcyc + 300 - ns START condition input hold time (When wakeup function is enabled) tSTAH 1 (5) × tIICcyc + tPcyc + 300 - ns Repeated START condition input setup time tSTAS 1000 - ns STOP condition input setup time t STOS 1000 - ns Data input setup time t SDAS tIICcyc + 50 - ns Data input hold time t SDAH 0 - ns SCL, SDA capacitive load C b - 400 pF IIC (Fast mode) SCL input cycle time t SCL 6 (12) × tIICcyc + 600 - ns Figure 2.49 SCL input high pulse width t SCLH 3 (6) × tIICcyc + 300 - ns SCL input low pulse width t SCLL 3 (6) × tIICcyc + 300 - ns SCL, SDA input rise time t Sr 20 × (external pullup voltage/5.5V)*2 300 ns SCL, SDA input fall time t Sf 20 × (external pullup voltage/5.5V)*2 300 ns SCL, SDA input spike pulse removal time tSP 0 1 (4) × t IICcyc ns SDA input bus free time (When wakeup function is disabled) tBUF 3 (6) × tIICcyc + 300 - ns SDA input bus free time (When wakeup function is enabled) tBUF 3 (6) × tIICcyc + 4 × tPcyc + 300 - ns START condition input hold time (When wakeup function is disabled) tSTAH tIICcyc + 300 - ns START condition input hold time (When wakeup function is enabled) tSTAH 1(5) × tIICcyc + tPcyc + 300 - ns Repeated START condition input setup time tSTAS 300 - ns STOP condition input setup time t STOS 300 - ns Data input setup time t SDAS tIICcyc + 50 - ns Data input hold time t SDAH 0 - ns SCL, SDA capacitive load C b - 400 pF

R01DS0264EU0100 Rev.1.00 Page 65 of 95 Feb 23, 2016 S124 2. Electrical Characteristics set to 1. Note 2. Only supported for SCL0_A and SDA0_A. Figure 2.49 I 2C bus interface input/output timing SDA0 and SDA1 SCL0 and SCL1 VIH VIL tSTAH tSCLH tSCLL P*1 S*1 tSf tSr tSCL tSDAH tSDAS tSTAS tSP tSTOS P*1 tBUF Sr*1 Note 1. S, P, and Sr indica te the following conditions. S: Start condition P: Stop condition Sr: Restart condition

R01DS0264EU0100 Rev.1.00 Page 66 of 95 Feb 23, 2016 S124 2. Electrical Characteristics

2.3.11 CLKOUT Timing

Note 1. When the EXTAL external clock input or an oscillator is used with division by 1 (the CKOCR.CKOSEL[2:0] bits are 011b and the CKOCR.CKODIV[2:0] bits are 000b) to output from CLKOUT, the above should be satisfied with an input duty cycle of 45 to 55%. Note 2. When the MOCO is selected as the clock output source (t he CKOCR.CKOSEL[2:0] bits are 001b), set the clock output division ratio selection to be divided by 2 (the CKOCR.CKODIV[2:0] bits are 001b). Figure 2.50 CLKOUT output timing Table 2.37 CLKOUT timing Item Symbol Min Max Unit* 1 Test conditions CLKOUT CLKOUT pin output cycle* 1 VCC = 2.7 V or above t Ccyc 62.5 - ns Figure 2.50 VCC = 1.8 V or above 125 - VCC = 1.6 V or above 250 - CLKOUT pin high pulse width* 2 VCC = 2.7 V or above t CH 15 - ns VCC = 1.8 V or above 30 - VCC = 1.6 V or above 150 - CLKOUT pin low pulse width* 2 VCC = 2.7 V or above t CL 15 - ns VCC = 1.8 V or above 30 - VCC = 1.6 V or above 150 - CLKOUT pin output rise time VCC = 2.7 V or above t Cr -1 2 n s VCC = 1.8 V or above - 25 VCC = 1.6 V or above - 50 CLKOUT pin output fall time VCC = 2.7 V or above t Cf -1 2 n s VCC = 1.8 V or above - 25 VCC = 1.6 V or above - 50 tCf tCH tCcyc tCr tCL CLKOUT pin output Test conditions: VOH = VCC × 0.7, VOL = VCC × 0.3, IOH = -1.0 mA, IOL = 1.0 mA, C = 30 pF

R01DS0264EU0100 Rev.1.00 Page 67 of 95 Feb 23, 2016 S124 2. Electrical Characteristics

2.4 USB Characteristics

2.4.1 USBFS Timing

Figure 2.51 USB_DP and USB_DM output timing Table 2.38 USB characteristics Conditions: VCC = AVCC0 = VCC_USB = 3.0 to 5.5, Ta = –20 to +85°C Item Symbol Min Max Unit Test conditions Input characteristics Input high level voltage V IH 2.0 - V - Input low level voltage V IL -0 . 8 V - Differential input sensitivity V DI 0.2 - V | USB_DP – USB_DM | Differential common mode range VCM 0.8 2.5 V - Output characteristics Output high level voltage V OH 2.8 VCC_USB V I OH = –200 μA Output low level voltage V OL 0.0 0.3 V I OL= 2 mA Cross-over voltage V CRS 1.3 2.0 V Figure 2.51, Figure 2.52, Figure 2.53Rise time FS t r 42 0 n s LS 75 300 Fall time FS t f 42 0 n s LS 75 300 Rise/fall time ratio FS t r/tf 90 111.11 % LS 80 125 Output resistance Z DRV 28 44 Ω (Adjusting the resistance of external elements is not necessary.) VBUS characteristics VBUS input voltage V IH VCC × 0.8 - V - VIL -V C C × 0 . 2 V - Pull-up, pull-down Pull-down resistor R PD 14.25 24.80 k Ω - Pull-up resistor R PUI 0.9 1.575 k Ω During idle state RPUA 1.425 3.09 k Ω During reception Battery Charging Specification Ver 1.2 D + sink current I DP_SINK 25 175 μA- D – sink current I DM_SINK 25 175 μA- DCD source current I DP_SRC 71 3 μA- Data detection voltage V DAT_REF 0.25 0.4 V - D + source voltage V DP_SRC 0.5 0.7 V Output current = 250 μA D – source voltage V DM_SRC 0.5 0.7 V Output current = 250 μA USB_DP, USB_DM tftr 90% 10%10% 90%VCRS

R01DS0264EU0100 Rev.1.00 Page 68 of 95 Feb 23, 2016 S124 2. Electrical Characteristics Figure 2.52 Test circuit for Full-Speed (FS) connection Figure 2.53 Test circuit for Low-Speed (LS) connection

2.4.2 USB External Supply

Table 2.39 USB regulator Item Min Typ Max Unit Test conditions VCC_USB supply current VCC_USB_LDO ≥ 3.8V -- 50 mA - VCC_USB_LDO ≥ 4.5V -- 100 mA - VCC_USB supply voltage 3.0 - 3.6 V - Observation point 50 pF USB_DP USB_DM 50 pF Observation point 200 pF to 600 pF USB_DP USB_DM 200 pF to 600 pF 1.5 K 3.6 V Observation point

R01DS0264EU0100 Rev.1.00 Page 69 of 95 Feb 23, 2016 S124 2. Electrical Characteristics

2.5 ADC14 Characteristics

Figure 2.54 AVCC0 to VREFH0 voltage range Table 2.40 A/D conversion characteristics (1) in high-speed mode (1/2) Conditions: VCC = AVCC0 = 4.5 to 5.5 V, VREFH0 = 4.5 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V Reference voltage range applied to the VREFH0 and VREFL0. Item Min Typ Max Unit Test Conditions Frequency 1 - 64 MHz - Analog input capacitance Cs - - 15 pF High-precision channel - - 30 pF Normal-precision channel Analog input resistance Rs - - 2.5 k Ω - Analog input voltage range Ain 0 - VREFH0 V - 12-bit mode Resolution - - 12 Bit - Conversion time* (Operation at PCLKD = 64 MHz) Permissible signal source impedance Max. = 0.3 kΩ 0.70 - - μs High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 1.13 - - μs Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h Offset error - ±0.5 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Full-scale error - ±0.75 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±1.25 ±5.0 LSB High-precision channel ±8.0 LSB Other than above DNL differential nonlinearity error - ±1.0 - LSB - INL integral nonlinearity error - ±1.0 ±3.0 LSB - 14-bit mode Resolution - - 14 Bit - Conversion time* (Operation at PCLKD = 64 MHz) Permissible signal source impedance Max. = 0.3 kΩ 0.80 - - μs High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 1.22 - - μs Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h VREFH0 5.0 4.0 3.0 2.0 1.0 A/D Conversion Characteristics (2) ADCSR.ADHSC = 0 5.5 2.7 2.4 2.4 2.7 5.5 AVCC0 VREFH0 5.0 4.0 3.0 2.0 1.0 ADCSR.ADHSC = 1 5.5 2.7 2.4 2.4 2.7 5.5 AVCC0 1.8 1.8 A/D Conversion Characteristics (1) A/D Conversion Characteristics (3) A/D Conversion Characteristics (4) A/D Conversion Characteristics (5) A/D Conversion Characteristics (6)

R01DS0264EU0100 Rev.1.00 Page 70 of 95 Feb 23, 2016 S124 2. Electrical Characteristics Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Offset error - ±2.0 ±18 LSB High-precision channel ±24.0 LSB Other than above Full-scale error - ±3.0 ±18 LSB High-precision channel ±24.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±5.0 ±20 LSB High-precision channel ±32.0 LSB Other than above DNL differential nonlinearity error - ±4.0 - LSB - INL integral nonlinearity error - ±4.0 ±12.0 LSB - Table 2.41 A/D conversion characteristics (2) in high-speed mode (1/2) Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V Reference voltage range applied to the VREFH0 and VREFL0. Item Min Typ Max Unit Test Conditions Frequency 1 - 48 MHz - Analog input capacitance Cs - - 15 pF High-precision channel - - 30 pF Normal-precision channel Analog input resistance Rs - - 2.5 k Ω - Analog input voltage range Ain 0 - VREFH0 V - 12-bit mode Resolution - - 12 Bit - Conversion time* (Operation at PCLKD = 48 MHz) Permissible signal source impedance Max. = 0.3 kΩ 0.94 - - μs High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 1.50 - - μs Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h Offset error - ±0.5 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Full-scale error - ±0.75 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±1.25 ±5.0 LSB High-precision channel ±8.0 LSB Other than above DNL differential nonlinearity error - ±1.0 - LSB - INL integral nonlinearity error - ±1.0 ±3.0 LSB - 14-bit mode Resolution - - 14 Bit - Conversion time* (Operation at PCLKD = 48 MHz) Permissible signal source impedance Max. = 0.3 kΩ 1.06 - - μs High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 1.63 - - μs Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h Table 2.40 A/D conversion characteristics (1) in high-speed mode (2/2) Conditions: VCC = AVCC0 = 4.5 to 5.5 V, VREFH0 = 4.5 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V Reference voltage range applied to the VREFH0 and VREFL0. Item Min Typ Max Unit Test Conditions

R01DS0264EU0100 Rev.1.00 Page 71 of 95 Feb 23, 2016 S124 2. Electrical Characteristics Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Offset error - ±2.0 ±18 LSB High-precision channel ±24.0 LSB Other than above Full-scale error - ±3.0 ±18 LSB High-precision channel ±24.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±5.0 ±20 LSB High-precision channel ±32.0 LSB Other than above DNL differential nonlinearity error - ±4.0 - LSB - INL integral nonlinearity error - ±4.0 ±12.0 LSB - Table 2.42 A/D conversion characteristics (3) in high-speed mode (1/2) Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V Reference voltage range applied to the VREFH0 and VREFL0. Item Min Typ Max Unit Test Conditions Frequency 1 - 32 MHz - Analog input capacitance Cs - - 15 pF High-precision channel - - 30 pF Normal-precision channel Analog input resistance Rs - - 2.5 k Ω - Analog input voltage range Ain 0 - VREFH0 V - 12-bit mode Resolution - - 12 Bit - Conversion time* (Operation at PCLKD = 32 MHz) Permissible signal source impedance Max. = 1.3 kΩ 1.41 - - μs High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 2.25 - - μs Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h Offset error - ±0.5 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Full-scale error - ±0.75 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±1.25 ±5.0 LSB High-precision channel ±8.0 LSB Other than above DNL differential nonlinearity error - ±1.0 - LSB - INL integral nonlinearity error - ±1.0 ±3.0 LSB - 14-bit mode Resolution - - 14 Bit - Conversion time* (Operation at PCLKD = 32 MHz) Permissible signal source impedance Max. = 1.3 kΩ 1.59 - - μs High-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 0Dh 2.44 - - μs Normal-precision channel ADCSR.ADHSC = 0 ADSSTRn.SST[7:0] = 28h Table 2.41 A/D conversion characteristics (2) in high-speed mode (2/2) Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V Reference voltage range applied to the VREFH0 and VREFL0. Item Min Typ Max Unit Test Conditions

R01DS0264EU0100 Rev.1.00 Page 72 of 95 Feb 23, 2016 S124 2. Electrical Characteristics Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Offset error - ±2.0 ±18 LSB High-precision channel ±24.0 LSB Other than above Full-scale error - ±3.0 ±18 LSB High-precision channel ±24.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±5.0 ±20 LSB High-precision channel ±32.0 LSB Other than above DNL differential nonlinearity error - ±4.0 - LSB - INL integral nonlinearity error - ±4.0 ±12.0 LSB - Table 2.43 A/D conversion characteristics (4) in low power mode (1/2) Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V Reference voltage range applied to the VREFH0 and VREFL0. Item Min Typ Max Unit Test Conditions Frequency 1 - 24 MHz - Analog input capacitance Cs - - 15 pF High-precision channel - - 30 pF Normal-precision channel Analog input resistance Rs - - 2.5 k Ω - Analog input voltage range Ain 0 - VREFH0 V - 12-bit mode Resolution - - 12 Bit - Conversion time* (Operation at PCLKD = 24 MHz) Permissible signal source impedance Max. = 1.1 kΩ 2.25 - - μs High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 3.38 - - μs Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h Offset error - ±0.5 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Full-scale error - ±0.75 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±1.25 ±5.0 LSB High-precision channel ±8.0 LSB Other than above DNL differential nonlinearity error - ±1.0 - LSB - INL integral nonlinearity error - ±1.0 ±3.0 LSB - 14-bit mode Resolution - - 14 Bit - Conversion time* (Operation at PCLKD = 24 MHz) Permissible signal source impedance Max. = 1.1 kΩ 2.50 - - μs High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 3.63 - - μs Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h Table 2.42 A/D conversion characteristics (3) in high-speed mode (2/2) Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V Reference voltage range applied to the VREFH0 and VREFL0. Item Min Typ Max Unit Test Conditions

R01DS0264EU0100 Rev.1.00 Page 73 of 95 Feb 23, 2016 S124 2. Electrical Characteristics Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Offset error - ±2.0 ±18 LSB High-precision channel ±24.0 LSB Other than above Full-scale error - ±3.0 ±18 LSB High-precision channel ±24.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±5.0 ±20 LSB High-precision channel ±32.0 LSB Other than above DNL differential nonlinearity error - ±4.0 - LSB - INL integral nonlinearity error - ±4.0 ±12.0 LSB - Table 2.44 A/D conversion characteristics (5) in low power mode (1/2) Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V Reference voltage range applied to the VREFH0 and VREFL0. Item Min Typ Max Unit Test Conditions Frequency 1 - 16 MHz - Analog input capacitance Cs - - 15 pF High-precision channel - - 30 pF Normal-precision channel Analog input resistance Rs - - 2.5 k Ω - Analog input voltage range Ain 0 - VREFH0 V - 12-bit mode Resolution - - 12 Bit - Conversion time* (Operation at PCLKD = 16 MHz) Permissible signal source impedance Max. = 2.2 kΩ 3.38 - - μs High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 5.06 - - μs Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h Offset error - ±0.5 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Full-scale error - ±0.75 ±4.5 LSB High-precision channel ±6.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±1.25 ±5.0 LSB High-precision channel ±8.0 LSB Other than above DNL differential nonlinearity error - ±1.0 - LSB - INL integral nonlinearity error - ±1.0 ±3.0 LSB - 14-bit mode Resolution - - 14 Bit - Conversion time* (Operation at PCLKD = 16 MHz) Permissible signal source impedance Max. = 2.2 kΩ 3.75 - - μs High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 5.44 - - μs Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h Table 2.43 A/D conversion characteristics (4) in low power mode (2/2) Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V Reference voltage range applied to the VREFH0 and VREFL0. Item Min Typ Max Unit Test Conditions

R01DS0264EU0100 Rev.1.00 Page 74 of 95 Feb 23, 2016 S124 2. Electrical Characteristics Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Offset error - ±2.0 ±18 LSB High-precision channel ±24.0 LSB Other than above Full-scale error - ±3.0 ±18 LSB High-precision channel ±24.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±5.0 ±20 LSB High-precision channel ±32.0 LSB Other than above DNL differential nonlinearity error - ±4.0 - LSB - INL integral nonlinearity error - ±4.0 ±12.0 LSB - Table 2.45 A/D conversion characteristics (6) in low power mode (1/2) Reference voltage range applied to the VREFH0 and VREFL0. Item Min Typ Max Unit Test Conditions Frequency 1 - 8 MHz - Analog input capacitance Cs - - 15 pF High-precision channel - - 30 pF Normal-precision channel Analog input resistance Rs - - 2.5 k Ω - Analog input voltage range Ain 0 - VREFH0 V - 12-bit mode Resolution - - 12 Bit - Conversion time* (Operation at PCLKD = 8 MHz) Permissible signal source impedance Max. = 5 kΩ 6.75 - - μs High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 10.13 - - μs Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h Offset error - ±1.0 ±7.5 LSB High-precision channel ±10.0 LSB Other than above Full-scale error - ±1.5 ±7.5 LSB High-precision channel ±10.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±3.0 ±8.0 LSB High-precision channel ±12.0 LSB Other than above DNL differential nonlinearity error - ±1.0 - LSB - INL integral nonlinearity error - ±1.0 ±3.0 LSB - 14-bit mode Resolution - - 14 Bit - Conversion time* (Operation at PCLKD = 8 MHz) Permissible signal source impedance Max. = 5 kΩ 7.50 - - μs High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 10.88 - - μs Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h Table 2.44 A/D conversion characteristics (5) in low power mode (2/2) Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V Reference voltage range applied to the VREFH0 and VREFL0. Item Min Typ Max Unit Test Conditions

R01DS0264EU0100 Rev.1.00 Page 75 of 95 Feb 23, 2016 S124 2. Electrical Characteristics Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Offset error - ±4.0 ±30.0 LSB High-precision channel ±40.0 LSB Other than above Full-scale error - ±6.0 ±30.0 LSB High-precision channel ±40.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±12.0 ±32.0 LSB High-precision channel ±48.0 LSB Other than above DNL differential nonlinearity error - ±4.0 - LSB - INL integral nonlinearity error - ±4.0 ±12.0 LSB - Table 2.46 A/D conversion characteristics (7) in low power mode (1/2) Reference voltage range applied to the VREFH0 and VREFL0. Item Min Typ Max Unit Test Conditions Frequency 1 - 4 MHz - Analog input capacitance Cs - - 15 pF High-precision channel - - 30 pF Normal-precision channel Analog input resistance Rs - - 2.5 k Ω - Analog input voltage range Ain 0 - VREFH0 V - 12-bit mode Resolution - - 12 Bit - Conversion time* (Operation at PCLKD = 4 MHz) Permissible signal source impedance Max. = 9.9 kΩ 13.5 - - μs High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 20.25 - - μs Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h Offset error - ±1.0 ±7.5 LSB High-precision channel ±10.0 LSB Other than above Full-scale error - ±1.5 ±7.5 LSB High-precision channel ±10.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±3.0 ±8.0 LSB High-precision channel ±12.0 LSB Other than above DNL differential nonlinearity error - ±1.0 - LSB - INL integral nonlinearity error - ±1.0 ±3.0 LSB - 14-bit mode Resolution - - 14 Bit - Conversion time* (Operation at PCLKD = 4 MHz) Permissible signal source impedance Max. = 9.9 kΩ 15.0 - - μs High-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 0Dh 21.75 - - μs Normal-precision channel ADCSR.ADHSC = 1 ADSSTRn.SST[7:0] = 28h Table 2.45 A/D conversion characteristics (6) in low power mode (2/2) Reference voltage range applied to the VREFH0 and VREFL0. Item Min Typ Max Unit Test Conditions

R01DS0264EU0100 Rev.1.00 Page 76 of 95 Feb 23, 2016 S124 2. Electrical Characteristics Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not include quantization errors. Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is indicated for the test conditions. Note 1. The internal reference voltage cannot be selected for input channels when AVCC0 < 2.0 V. Note 2. The 14-bit A/D internal reference voltage indicates the voltage when the internal reference voltage is input to the 14-bit A/D converter. Offset error - ±4.0 ±30.0 LSB High-precision channel ±40.0 LSB Other than above Full-scale error - ±6.0 ±30.0 LSB High-precision channel ±40.0 LSB Other than above Quantization error - ±0.5 - LSB - Absolute accuracy - ±12.0 ±32.0 LSB High-precision channel ±48.0 LSB Other than above DNL differential nonlinearity error - ±4.0 - LSB - INL integral nonlinearity error - ±4.0 ±12.0 LSB - Table 2.47 14-bit A/D converter channel classification Classification Channel Conditions Remarks High-precision channel AN000 to AN010 AVCC0 = 1.6 to 5.5 V Pins AN000 to AN010 cannot be used as general I/O, TS transmission, when the A/D converter is in use.Normal-precision channel AN016 to AN022 Internal reference voltage input channel Internal reference voltage AVCC0 = 2.0 to 5.5 V - Temperature sensor input channel Temperature sensor output AVCC0 = 2.0 to 5.5 V - Table 2.48 A/D internal reference voltage characteristics Conditions: VCC = AVCC0 = VREFH0 = 2.0 to 5.5 V*1 Item Min Typ Max Unit Test conditions Internal reference voltage input channel*2 1.36 1.43 1.50 V - Table 2.46 A/D conversion characteristics (7) in low power mode (2/2) Reference voltage range applied to the VREFH0 and VREFL0. Item Min Typ Max Unit Test Conditions

R01DS0264EU0100 Rev.1.00 Page 77 of 95 Feb 23, 2016 S124 2. Electrical Characteristics Figure 2.55 Illustration of 14-bit A/D converter characteristic terms Absolute accuracy Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of the analog input voltage (1-LSB width), which can meet the expectation of outputting an equal code based on the theoretical A/D conversion characteristics, is used as the analog input voltage. For example, if 12-bit resolution is used and the reference voltage VREFH0 = 3.072 V , then 1-LSB width becomes 0.75 mV, and 0 mV , 0.75 mV , and 1.5 mV are used as the analog input voltages. If analog input voltage is 6 mV , an absolute accuracy of ±5 LSB means that the actual A/D conversion result is in the range of 003h to 00Dh, though an output code of 008h can be expected from the theoretical A/D conversion characteristics. Integral nonlinearity error (INL) Integral nonlinearity error is the maximum deviation between the ideal line when the measured offset and full-scale errors are zeroed, and the actual output code. Differential nonlinearity error (DNL) Differential nonlinearity error is the difference between 1-LSB width based on the ideal A/D conversion characteristics and the width of the actual output code. Offset error Offset error is the difference between the transition point of the ideal first output code and the actual first output code. Full-scale error Full-scale error is the difference between the transition point of the ideal last output code and the actual last output code. Integral nonlinearity error (INL) Actual A/D conversion characteristic Ideal A/D conversion characteristic Analog input voltage Offset error Absolute accuracy Differential nonlinearity error (DNL) Full-scale error FFFh 000h Ideal line of actual A/D conversion characteristic 1-LSB width for ideal A/D conversion characteristic Differential nonlinearity error (DNL) 1-LSB width for ideal A/D conversion characteristic VREFH0 (full-scale) A/D converter output code

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2.6 DAC12 Characteristics

Figure 2.56 Illustration of D/A converter characteristic terms Integral nonlinearity error (INL) Integral nonlinearity error is the maximum deviation between the ideal output voltage based on the ideal conversion characteristic when the measured offset and full-scale errors are zeroed, and the actual output voltage. Differential nonlinearity error (DNL) Differential nonlinearity error is the difference between 1-LSB voltage width based on the ideal D/A conversion characteristics and the width of the actual output voltage. Table 2.49 D/A conversion characteristics Conditions: VCC = AVCC0 = 1.8 to 5.5 V Reference voltage = AVCC0 or AVSS0 selected Item Min Typ Max Unit Test conditions Resolution - - 12 bit - Resistive load 30 - - k Ω - Capacitive load - - 50 pF - Output voltage range 0.35 - AVCC0 – 0.47 V - DNL differential nonlinearity error - ±0.5 ±2.0 LSB - INL integral nonlinearity error - ±2.0 ±8.0 LSB - Offset error - -± 3 0 m V - Full-scale error - -± 3 0 m V - Output impedance - 5- Ω - Conversion time - -3 0 μs- 000h D/A converter input code FFFh Output analog voltage Upper output limit Lower output limit Offset error Ideal output voltage 1-LSB width for ideal D/A conversion characteristic Differential nonlinearity error (DNL) Actual D/A conversion characteristic Integral nonlinearity error (INL) Full-scale error Gain error Offset error Ideal output voltage Note 1. Ideal D/A conversion output voltage that is adjusted so that offset and full scale errors are zeroed .

R01DS0264EU0100 Rev.1.00 Page 79 of 95 Feb 23, 2016 S124 2. Electrical Characteristics Offset error Offset error is the difference between the highest actual output voltage that falls below the lower output limit and the ideal output voltage based on the input code. Full-scale error Full-scale error is the difference between the lowest actual output voltage that exceeds the upper output limit and the ideal output voltage based on the input code.

2.7 TSN Characteristics

2.8 OSC Stop Detect Characteristics

Figure 2.57 Oscillation stop detection timing Table 2.50 TSN characteristics Conditions: VCC = AVCC0 = 2.0 to 5.5 V Item Symbol Min Typ Max Unit Test conditions Relative accuracy - - ±1.5 - °C 2.4 V or above - ±2.0 - °C Below 2.4 V Temperature slope -- –3.65 - mV/°C - Output voltage (at 25°C) -- 1.05 - V VCC = 3.3 V Temperature sensor start time t START -- 5 μs- Sampling time - 5 - - μs Table 2.51 Oscillation stop detection circuit characteristics Item Symbol Min Typ Max Unit Test conditions Detection time t dr --1 m s Figure 2.57 tdr Main clock OSTDSR.OSTDF MOCO clock ICLK

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2.9 POR and LVD Characteristics

Note 1. These characteristics apply when noise is not super imposed on the power supply. When a setting causes this voltage detection level to overlap with that of the voltage detection circuit (LVD2), it cannot be specified whether LVD1 or LVD2 is used for voltage detection. Note 2. # in the symbol V det0_# denotes the value of the OFS1.VDSEL1[2:0] bits. Note 3. # in the symbol V det1_# denotes the value of the LVDLVLR.LVD1LVL[4:0] bits. Note 4. # in the symbol V det2_# denotes the value of the LVDLVLR.LVD2LVL[2:0] bits. Table 2.52 Power-on reset circuit and voltag e detection circuit characteristics (1) Conditions: VCC = AVCC0 Item Symbol Min Typ Max Unit Test Conditions Voltage detection level*1 Power-on reset (POR) V POR 1.27 1.42 1.57 V Figure 2.58, Figure 2.59 Voltage detection circuit (LVD0)*2 Vdet0_0 3.68 3.85 4.00 V Figure 2.60 At falling edge VCCVdet0_1 2.68 2.85 2.96 Vdet0_2 2.38 2.53 2.64 Vdet0_3 1.78 1.90 2.02 Vdet0_4 1.60 1.69 1.82 Voltage detection circuit (LVD1)*3 Vdet1_0 4.13 4.29 4.45 V Figure 2.61 At falling edge VCCVdet1_1 3.98 4.16 4.30 Vdet1_2 3.86 4.03 4.18 Vdet1_3 3.68 3.86 4.00 Vdet1_4 2.98 3.10 3.22 Vdet1_5 2.89 3.00 3.11 Vdet1_6 2.79 2.90 3.01 Vdet1_7 2.68 2.79 2.90 Vdet1_8 2.58 2.68 2.78 Vdet1_9 2.48 2.58 2.68 Vdet1_A 2.38 2.48 2.58 Vdet1_B 2.10 2.20 2.30 Vdet1_C 1.84 1.96 2.05 Vdet1_D 1.74 1.86 1.95 Vdet1_E 1.63 1.75 1.84 Vdet1_F 1.60 1.65 1.73 Voltage detection circuit (LVD2)*4 Vdet2_0 4.11 4.31 4.48 V Figure 2.62 At falling edge VCCV det2_1 3.97 4.17 4.34 Vdet2_2 3.83 4.03 4.20 Vdet2_3 3.64 3.84 4.01 Table 2.53 Power-on reset circuit and voltage detection circuit characteristics (2) (1/2) Conditions: VCC = AVCC0 Item Symbol Min Typ Max Unit Test Conditions Wait time after voltage monitoring 0,1,2 reset cancellation LVD0:enable*1 tLVD0,1,2 -0 . 6 - μs- LVD0:disable*2 tLVD1,2 -0 . 2 - μs- Response delay*3 tdet - - 350 μs Figure 2.58, Figure 2.59 Minimum VCC down time t VOFF 450 - - μs Figure 2.58, VCC = 1.0 V or above Power-on reset enable time t W (POR) 1- - m s Figure 2.59, VCC = below 1.0 V

R01DS0264EU0100 Rev.1.00 Page 83 of 95 Feb 23, 2016 S124 2. Electrical Characteristics Figure 2.62 Voltage detection circuit timing (V det2)

2.10 CTSU Characteristics

Table 2.54 CTSU characteristics Conditions: VCC = AVCC0 = 1.8 to 5.5 V Item Symbol Min Typ Max Unit Test conditions External capacitance connected to TSCAP pin C tscap 91 0 1 1 n F - TS pin capacitive load C base --5 0 p F - Permissible output high current ΣIoH - - -24 mA When the mutual capacitance method is applied tVOFF Vdet2VCC tdettdet tLVD2 Td(E-A) LVCMPCR.LVD2E LVD2 Comparator output LVD2CR0.CMPE LVD2SR.MON Internal reset signal (active-low) When LVD2CR0.RN = 0 When LVD2CR0.RN = 1 VLVH tLVD2

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2.11 Comparator Characteristics

Table 2.55 ACMPLP characteristics Conditions: VCC = AVCC0 = 1.8 to 5.5 V, VSS = AVSS0 = 0 V Item Symbol Min Typ Max Unit Test conditions Reference voltage range V REF 0- V C C –1.4 Input voltage range V I 0 - VCC V - Output delay High-speed mode T d -- 1.2 μs VCC = 3.0 Slew rate of input signal > 50 mV/μsLow-speed mode -- 5 μs Window mode - - 2 μs Offset voltage High-speed mode - - - 50 mV - Low-speed mode - - - 40 mV - Window mode - - - 60 mV - Internal reference voltage for window mode V RFH - 0.76 × VCC - V- VRFL - 0.24 × VCC - V- Operation stabilization wait time T cmp 100 - - μs-

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2.12 Flash Memory Characteristics

2.12.1 Code Flash Memory Characteristics

Note 1. The reprogram/erase cycle is th e number of erasures for each block. When the reprogram/erase cycle is n times (n = 1,000), erasing can be performed n times for each block. For instance, when 4-byte programming is performed 256 times for different addresses in 1-KB blocks, and then the entire block is erased, the reprogram/ erase cycle is counted as one. However, programming the same address for several times as one erasure is not enabled. (overwriting is prohibited.) Note 2. Characteristic when using the flash memory progra mmer and the self-programming library provided by Renesas Electronics. Note 3. This result is obtained from reliability testing. Note 1. Does not include the time until each operation of the flash memory is started after instructions are executed by the software. Note 2. The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note 3. The frequency accuracy of ICLK must be ±3.5% while programming or erasing the flash memory. Confirm the frequency accuracy of the clock source. Table 2.56 Code flash characteristics (1) Item Symbol Min Typ Max Unit Conditions Reprogramming/erasure cycle*1 NPEC 1000 -- Times - Data hold time After 1000 times N PEC tDRP 20*2, *3 -- Year T a = +85°C Table 2.57 Code flash characteristics (2) High-speed operating mode Conditions: VCC = AVCC0 = 2.7 to 5.5 V Item Symbol ICLK = 1 MHz ICLK = 32 MHz UnitMin Typ Max Min Typ Max Programming time 4-byte t P4 - 116 998 - 54 506 μs Erasure time 1-KB t E1K - 9.03 287 - 5.67 222 ms Blank check time 4-byte t BC4 -- 56.8 -- 16.6 μs 1-KB t BC1K -- 1899 -- 140 μs Erase suspended time t SED -- 22.5 -- 10.7 μs Startup area switching setting time t SAS - 21.9 585 - 12.1 447 ms Access window time t AWS - 21.9 585 - 12.1 447 ms OCD/serial programmer ID setting time t OSIS - 21.9 585 - 12.1 447 ms Flash memory mode transition wait time 1 tDIS 2 -- 2 -- μs Flash memory mode transition wait time 2 tMS 5 -- 5 -- μs

R01DS0264EU0100 Rev.1.00 Page 86 of 95 Feb 23, 2016 S124 2. Electrical Characteristics Note 1. Does not include the time until each operation of the flash memory is started after instructions are executed by the software. Note 2. The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note 3. The frequency accuracy of ICLK must be ±3.5% while programming or erasing the flash memory. Confirm the frequency accuracy of the clock source.

2.12.2 Data Flash Memory Characteristics

Note 1. The reprogram/erase cycle is the number of erasure for each block. When the reprogram/erase cycle is n times (n = 100,000), erasing can be performed n times for each block. For instance, when 1-byte programming is performed 1,000 times for different addresses in 1-byte blocks, and then the entire block is erased, the reprogram/erase cycle is counted as one. However, programming the same address for several times as one erasure is not enabled. (overwriting is prohibited.) Note 2. Characteristics when using the flash memory program mer and the self-programming library provided by Renesas Electronics. Note 3. These results are obt ained from reliability testing. Table 2.58 Code flash characteristics (3) Middle-speed operating mode Conditions: VCC = AVCC0 = 1.8 to 5.5 V, Ta = -40 to +85°C Item Symbol ICLK = 1 MHz ICLK = 8 MHz UnitMin Typ Max Min Typ Max Programming time 4-byte t P4 - 157 1411 - 101 966 μs Erasure time 1-KB t E1K - 9.10 289 - 6.10 228 ms Blank check time 2-byte t BC4 -- 87.7 -- 52.5 μs 1-KB t BC1K -- 1930 -- 414 μs Erase suspended time t SED -- 32.7 -- 21.6 μs Startup area switching setting time t SAS - 22.8 592 - 14.2 465 ms Access window time t AWS - 22.8 592 - 14.2 465 ms OCD/serial programmer ID setting time t OSIS - 22.8 592 - 14.2 465 ms Flash memory mode transition wait time 1 tDIS 2 -- 2 -- μs Flash memory mode transition wait time 2 tMS 720 -- 720 -- ns Table 2.59 Data flash characteristics (1) Item Symbol Min Typ Max Unit Conditions Reprogramming/erasure cycle*1 NDPEC 100000 1000000 - Times - Data hold time After 10000 times of N DPEC tDDRP 20*2, *3 -- Year Ta = +85°C After 100000 times of NDPEC 5*2, *3 -- Year After 1000000 times of NDPEC -1 * 2, *3 - Year Ta = +25°C

R01DS0264EU0100 Rev.1.00 Page 87 of 95 Feb 23, 2016 S124 2. Electrical Characteristics Note 1. Does not include the time until each operation of the flash memory is started after instructions are executed by the software. Note 2. The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note 3. The frequency accuracy of ICLK must be ±3.5% while programming or erasing the flash memory. Confirm the frequency accuracy of the clock source. Note 1. Does not include the time until each operation of the flash memory is started after instructions are executed by the software. Note 2. The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz cannot be set. Note 3. The frequency accuracy of ICLK must be ±3.5% while programming or erasing the flash memory. Confirm the frequency accuracy of the clock source. Table 2.60 Data flash characteristics (2) High-speed operating mode Conditions: VCC = AVCC0 = 2.7 to 5.5 V Item Symbol ICLK = 4 MHz ICLK = 32 MHz UnitMin Typ Max Min Typ Max Programming time 1-byte t DP1 - 52.4 463 - 42.1 387 μs Erasure time 1-KB t DE1K - 8.98 286 - 6.42 237 ms Blank check time 1-byte t DBC1 -- 24.3 -- 16.6 μs 1-KB t DBC1K -- 1872 -- 512 μs Suspended time during erasing t DSED -- 13.0 -- 10.7 μs Data flash STOP recovery time t DSTOP 5 - -5 - - μs Table 2.61 Data flash characteristics (3) Middle-speed operating mode Conditions: VCC = AVCC0 = 1.8 to 5.5 V, Ta = -40 to +85°C Item Symbol ICLK = 4 MHz ICLK = 32 MHz UnitMin Typ Max Min Typ Max Programming time 1-byte t DP1 - 94.7 886 - 87.0 837 μs Erasure time 1-KB t DE1K - 9.59 299 - 7.82 266 ms Blank check time 1-byte t DBC1 -- 56.2 -- 50.9 μs 1-KB t DBC1K -- 2.17 -- 1.21 ms Suspended time during erasing t DSED -- 23.0 -- 21.0 μs Data flash STOP recovery time t DSTOP 720 - -7 2 0 - -n s

R01DS0264EU0100 Rev.1.00 Page 88 of 95 Feb 23, 2016 S124 2. Electrical Characteristics

2.12.3 Serial Wire Debug (SWD)

Figure 2.63 SWD SWCLK timing Table 2.62 SWD characteristics (1) Conditions: VCC = AVCC0 = 2.4 to 5.5 V Item Symbol Min Typ Max Unit Test conditions SWCLK clock cycle time t SWCKcyc 80 - - ns Figure 2.63 SWCLK clock high pulse width t SWCKH 35 - - ns SWCLK clock low pulse width t SWCKL 35 - - ns SWCLK clock rise time t SWCKr -- 5 n s SWCLK clock fall time t SWCKf -- 5 n s SWDIO setup time t SWDS 16 - - ns Figure 2.64 SWDIO hold time t SWDH 16 - - ns SWDIO data delay time t SWDD 2 - 70 ns Table 2.63 SWD characteristics (2) Conditions: VCC = AVCC0 = 1.6 to 2.4 V Item Symbol Min Typ Max Unit Test conditions SWCLK clock cycle time t SWCKcyc 250 - - ns Figure 2.63 SWCLK clock high pulse width t SWCKH 120 - - ns SWCLK clock low pulse width t SWCKL 120 - - ns SWCLK clock rise time t SWCKr -- 5 n s SWCLK clock fall time t SWCKf -- 5 n s SWDIO setup time t SWDS 50 - - ns Figure 2.64 SWDIO hold time t SWDH 50 - - ns SWDIO data delay time t SWDD 2 - 150 ns SWCLK tSWCKcyc tSWCKH tSWCKf tSWCKr tSWCKL

R01DS0264EU0100 Rev.1.00 Page 89 of 95 Feb 23, 2016 S124 2. Electrical Characteristics Figure 2.64 SWD input output timing SWCLK SWDIO (Input) tSWDS tSWDH SWDIO (Output) SWDIO (Output) SWDIO (Output) tSWDD tSWDD tSWDD

R01DS0264EU0100 Rev.1.00 Page 90 of 95 Feb 23, 2016 S124 Appendix 1. Package Dimensions Appendix 1. Package Dimensions Information on the latest version of the package dimensions or mountings is displayed in “Packages” on the Renesas Electronics Corporation website. Figure 1.1 LQFP 64-pin MASS (Typ) [g] 0.3 Unit: mm Previous CodeRENESAS Code PLQP0064KB-C — P-LFQFP64-10x10-0.50 © 2015 Renesas Electronics Corporation. All rights reserved. D E HD HE A bp c T e x y L p 9.9 9.9 11.8 11.8 0.05 0.15 0.09 0.45 Min Nom Dimensions in millimetersReference Symbol Max 10.0 10.0 1.4 12.0 12.0 0.20 3.5q 0.5 0.6 1.0 10.1 10.1 12.2 12.2 1.7 0.15 0.27 0.20 0.08 0.08 0.75 NOTE) 1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH. 2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET. 3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE LOCATED WITHIN THE HATCHED AREA. 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY. HD A2A1 Lp Detail F A c 0.25 D 48 33 3249 161 F NOTE 4 NOTE 3 Index area HE E*2 bpe yS S M T

R01DS0264EU0100 Rev.1.00 Page 91 of 95 Feb 23, 2016 S124 Appendix 1. Package Dimensions Figure 1.2 LQFP 48-pin MASS (Typ) [g] 0.2 Unit: mm Previous CodeRENESAS Code PLQP0048KB-B — P-LFQFP48-7x7-0.50 © 2015 Renesas Electronics Corporation. All rights reserved. D E HD HE A bp c T e x y L p 6.9 6.9 8.8 8.8 0.05 0.17 0.09 0.45 Min Nom Dimensions in millimetersReference Symbol Max 7.0 7.0 1.4 9.0 9.0 0.20 3.5q 0.5 0.6 1.0 7.1 7.1 9.2 9.2 1.7 0.15 0.27 0.20 0.08 0.08 0.75 NOTE) 1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH. 2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET. 3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE LOCATED WITHIN THE HATCHED AREA. 4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY. HD A2A1 Lp Detail F A c 0.25 HE D E 36 25 25 11 2 F NOTE 4 NOTE 3 Index area bpe yS S M T

R01DS0264EU0100 Rev.1.00 Page 92 of 95 Feb 23, 2016 S124 Appendix 1. Package Dimensions Figure 1.3 LGA 36-pin P-WFLGA36-4x4-0.50 PWLG0036KA-A P36FC-50-AA4-2 0.023 ITEM DIMENSIONS D E w e A b x y ZD ZE 4.00 ±0.10 4.00 ±0.10 0.05 0.20 0.69 ±0.07 0.08 0.50 0.24 ±0.05 (UNIT:mm) 0.20 0.75 0.75 S y1 S A Sy Sx32x b A B M e SwB ZD ZE INDEX MARK B C A SwAD E E EF DC B A C DDETAIL DETAIL EDETAIL b 0.34±0.05 0.55 0.70 ±0.05 0.55±0.05 0.70 ±0.05 0.55±0.05 0.75 φ φ 0.75 0.55 0.55 R0.275±0.05 R0.35±0.05 0.75 0.55±0.05 0.70± 0.05 0.55 0.75 0.55±0.05 0.70±0.05 (LAND PAD) (APERTURE OF SOLDER RESIST) D 2.90 2.90 2012 Renesas Electronics Corporation. All rights reserved.

R01DS0264EU0100 Rev.1.00 Page 93 of 95 Feb 23, 2016 S124 Appendix 1. Package Dimensions Figure 1.4 QFN 64-pin 2013 Renesas Electronics Corporation. All rights reserved. Sy e Lp SxbA B M A D E A S B A D E DETAIL OF A PART EXPOSED DIE PAD P-HWQFN64-8x8-0.40 PWQN0064LA-A 0.16 161 3249 INDEX AREA D A Lp 0.20 6.50 0.40 8.00 8.00 6.50 Referance Symbol Min Nom Max Dimension in Millimeters 0.23 0.30 0.50 b 0.17 x A 0.80 y 0.05 0.00 0.20 e Z Z c D E D E E 0.40 0.05 1.00 1.00 0.15 0.25 A1 c 2 8.057.95 8.057.95 Z Z D E 3348 P64K8-40-9B5-3

R01DS0264EU0100 Rev.1.00 Page 94 of 95 Feb 23, 2016 S124 Appendix 1. Package Dimensions Figure 1.5 QFN 48-pin 2013 Renesas Electronics Corporation. All rights reserved. Sy e Lp SxbA B M A D E A S B A D E DETAIL OF A PART EXPOSED DIE PAD P-HWQFN48-7x7-0.50 PWQN0048KB-A 48PJN-A 0.13 121 2437 INDEX AREA D A Lp 0.20 5.50 0.40 7.00 7.00 5.50 Referance Symbol Min Nom Max Dimension in Millimeters 0.30 0.30 0.50 b 0.18 x A 0.80 y 0.05 0.00 0.25 e Z Z c D E D E E 0.50 0.05 0.75 0.75 0.15 0.25 A1 c 2 7.056.95 7.056.95 Z Z D E 2536 P48K8-50-5B4-6

R01DS0264EU0100 Rev.1.00 Page 95 of 95 Feb 23, 2016 S124 Appendix 1. Package Dimensions Figure 1.6 QFN 40-pin Sy e Lp SxbA B M A D E A S B A D E DETAIL OF A PART EXPOSED DIE PAD P-HWQFN40-6x6-0.50 PWQN0040KC-A P40K8-50-4B4-5 0.09 101 2031 INDEX AREA D A Lp 0.20 4.50 0.40 6.00 6.00 4.50 Referance Symbol Min Nom Max Dimension in Millimeters 0.30 0.30 0.50 b 0.18 x A 0.80 y 0.05 0.00 0.25 e Z Z c D E D E E 0.50 0.05 0.75 0.75 0.15 0.25 A1 c 2 6.055.95 6.055.95 Z Z D E 2130

Rev. Date Chapter Summary 1.00 Feb. 23, 2016 — First Edition issued All trademarks and registered trademarks are the property of their respective owners.

Revision History

General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products 1. Precaution against Electrostatic Discharge (ESD) A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices. 2. Processing at power-on The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the level at which resetting is specified. 3. Input of signal during power-off state Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Follow the guideline for input signal during power-off state as described in your product documentation. 4. Handling of unused pins Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. 5. Clock signals After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable. 6. Voltage application waveform at input pin Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.). 7. Prohibition of access to reserved addresses Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these addresses as the correct operation of the LSI is not guaranteed. 8. Differences between products Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system-evaluation test for the given product.

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