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Mar. 2014 Specifications subject to change without notice Confidential Proprietary Rev0.1 Data Sheet of RL508 FM Tuner RTC6218(RL508)
Mar. 2014 Specifications subject to change without notice Confidential Proprietary Rev0.1
Revision History
0.1 Initial version 2014/03/11
RTC6218(RL508)
T-ST508-DST-001 Data Sheet Mar. 2014 General Description The RL508 is a single-chip broadcast FM stereo ra dio tuner with fully integrated building blocks as LNA, VCO with digital synthesizer, digital channel selection filter, digital FM demodulator and MPX decoder. The RL508 integrates the tuner function from antenna input to stereo audio output for worldwide European, US, Japanese and China FM bands. The FM tuner only requires a minimum amount of small and low cost external co mponents to be a very attractive solution for portable devices. With a powerful audio engine , the RL508 is able to deliver optimum sound quality under hostile channel conditions.
Features
Worldwide FM band support (64–108 MHz) Digital frequency synthesizer On-chip VCO On-chip loop filter Autonomous search tuning Automatic frequency control (AFC) Automatic gain control (AGC) Signal strength measurement Programmable de-emphasis (50/75 μs) Digital adaptive noise suppression Volume control 32.768 kHz, 12M, 24M, 13M, 26M, 19.2M, 38.4MHz reference clock 2-wire control interface 2.0 V to 3.6 V supply voltage Integrated LDO regulator SOP-8 package Pb-free / RoHS compliant Integrated crystal oscillator Built in audio amp for 32ohm load
Applications
Headphones MP3, MP4 players Portable radios PDA Notebook PC Gift Reference RL508 EVB Quick Start Guide RL508 Programming Guide RL508 EVB User’s Guide Specifications subject to change without notice Confidential Proprietary Rev0.1 RTC6218(RL508)
Mar. 2014 Specifications subject to change without notice Confidential Proprietary Rev0.1 F UNCTIONAL D ESCRIPTION 1.1. O VERVIEW 1.2. FM R ECEIVER 1.3. A UDIO P ROCESSING 1.4. T UNING AND S EEKING 1.5. R ESET AND P OWER UP 1.5.1. R ESET 1.5.2. P OWER 1.6. I NITIALIZATION S EQUENCE 1.6.1. T O INITIALIZE THE DEVICE 1.6.2. T O POWER DOWN THE DEVICE 1.7. C ONTROL I NTERFACE 1.7.1 WIRE C ONTROL I NTERFACE E LECTRICAL C HARACTERISTIC R EGISTERS S UMMARY R EGISTER D ESCRIPTIONS P IN D ESCRIPTION P ACKAGE O UTLINE PCB L AND P ATTERN A PPLICATION S CHEMATIC 8.1 A PPLICATION C IRCUIT FOR RCLK AND HEADPHONE 8.1.1 B ILL O F M ATERIALS RTC6218(RL508)
Figure 1. RL508 FM receiver block diagram design easily for the miniature application. allowed to directly supply 2.0 to 3.6 V from battery. power consumption and to eliminate environmental noise with audio algorithm such as soft-mute and stereo-blending. source or build-in clock oscillator with off-chip crystal.
Mar. 2014 Specifications subject to change without notice Confidential Proprietary Rev0.1 1.3. Audio Processing Switching from stereo to mono to limit the output noise is automatically performed by MPX decoder. The blending process from stereo to mono occurs when signal level reaches the threshold which is defined in register bits CSR0_BLNDADJUST[1:0] +CSR0_BLNDOFS[3:0]. Stereo/mono status is shown in the register bit ST. Mono operation can be forced by register bit CSR0_MONO. A 19 kHz pilot notch filter is implemented to eliminate the distortion from 19 kHz pilot tone for some audio analyzer. High-frequency interferences and noise can be reduced by pre-emphasis and de-emphasis technology to improve SNR. Since the high audio frequency is accentuated by pre-emphasis universally when FM signal is transmitted, the received FM signal is applied to attenuate high audio frequenc y using a de-emphasis filter. The CSR0_DEEM bit can be programmed for either 50 or 75us for de-emphasis time constant. The audio output may be muted by CSR0_DIS_MUTE bit. Volume can be adjusted digitally through CSR0_VOLUME[3:0] bits. Audio output can be attenuated and audible noise can be minimized during weak-signal level by the software mute function. Four levels of soft-mute tuning (fastest, fast, slow and slowest) are defined in register bits CSR0_SMUTERATE[1:0]. In addition, 4 levels of attenuation (16,14,12 and 10dB) are defined in register bits CSR0_SMUTEATT[1:0]. The soft-mute function can be disabled by register CSR0_DIS_SMUTE. 1.4. Tuning and Seeking The tuning frequency is defined as: Frequency (MHz) = Channel Spacing (200kHz or 100kHz or 50kHz) * Channel Number + Band Selection (87.5MHz, 76MHz or 64MHz) The Channel Spacing is selected by CSR0_CHSPACE[1:0]. The Channel Number is defined by CSR0_CH[9:0]. The CSR0_BAND is used for Band Selection such as Japan, Europe/U.S./Asia or China band. Setting CSR0_TUNE bit is to enable tuning operation. The seek/tune done (STD) bit set when tuning process is done and RSSI level is available. When seeking process is initiated by setting CSR0_SEEK, the tuning frequency will be seek up or seek down depending on the setting of CSR0_SEEKUP. The RSSI and tuned channel are readable in RSSI[7:0] and READCH[9:0] respectively when the STD bit is set to high to indicate the completion of seek operation. The SF bit is set to high to indicate that the tuned channel is seek failure when the number of RSSI of all seeking channel is less than or equal to the threshold number defined in CSR0_SEEKRSSITH[7:0]. Seek channel can be read by READCH[9:0] during the entire seek operation. The seek operation can always be deactivated by setting CSR0_SEEK bit to low. RTC6218(RL508)
cycle before the next falling SCLK edge. edge. To acknowledge (ACK) each data word, SDIO is driv en low for one cycle before the next falling SCLK edge. counter automatically wraps around to the first register. condition. The internal address counter is reset to 0 when STOP condition happen. Table 1. 2-Wire control interface characteristics
- Electrical Characteristic
Table 2. Recommended operating conditions Table 3. Absolute maximum ratings
- For input pins SCLK, SDIO, RCLK.
Table 4. DC electrical characteristics
- Refer to Register 02h, for the description of CSR0_ENABLE bit.
- For input pins SCLK, SDIO, RCLK.
Mar. 2014 Specifications subject to change without notice Confidential Proprietary Rev0.1 Table5. FM receiver characteristics (VDD = 2 to 3.6V, T A = –20 to 85 °C) PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT Input Frequency --- 108 MHz Usable Sensitivity (S+N)/N=26dB --- 1.6 2.0 μV EMF Adjacent Channel Selectivity ± 200kHz --- dB Alternate Channel Selectivity ± 400kHz --- dB IIP3 f1=200 kHz, f2=400 kHz --- --- dBuV EMF IIP3 f1=400 kHz, f2=800 kHz --- --- dBuV EMF Audio Output Voltage Load 10KΩ 1∥ 0pF --- 151 --- mVrms Audio Frequency Response 0 to –3dB --- 15K Hz Audio (S+N)/N --- dB Stereo Separation --- 42.3 --- dB Audio Total Harmonic Distortion (THD) Stereo --- 0.1 0.5 Power-up Time From Power-off to audio out --- 150 --- ms Tuning/Seeking Time --- --- ms RTC6218(RL508)
Mar. 2014 Specifications subject to change without notice Confidential Proprietary Rev0.1 3. Registers Summary Table 6. Registers summary
Description
MPX configuration register 02H 0000H CHANNEL Tuning channel setting 03H 0000H SYSCONFIG System configuration register 04H 0000H SEEKCONFIG1 Seek configuration register1 05H 0000H POWERCONFIG Power configuration register 06H 0000H PADCONFIG PAD configuration register 07H 7000H Reserved Reserved 08H 0000H SEEKCONFIG2 Seek configuration register2 09H 4010H STATUS Status register and work channel 0AH 0000H RSSI RSSI 0BH 0000H Reserved Reserved 0CH 0000H Reserved Reserved 0DH 0000H Reserved Reserved 0EH 0000H Reserved Reserved 0FH 0000H RTC6218(RL508)
Mar. 2014 Specifications subject to change without notice Confidential Proprietary Rev0.1 4. Register Descriptions DEVICEID (Device ID code), 00H Field Bits Type PART_NUMBER 15:12 R Part number MFGID 11:0 R Manufacture ID CHIPID (Chip ID code), 01H Field Bits Type REVISION_NO 15:10 R Reserved 9:0 R Reserved MPXCONFRG (MPX configuration register), 02H Field Bits Type CSR0_DIS_SMUTE R/W Disable Softmute 0 = Enable Softmute 1 = Disable Softmute(default) CSR0_DIS_MUTE R/W Disable Mute 0 = Enable Mute(default) 1 = Disable Mute CSR0_MONO R/W Force Mono or Auto Detect 0 = Auto detect Mono or Stereo(default) 1 = Force mono CSR0_DEEM R/W De-emphasis 0 = 75us(default) 1 = 50us Reserved 11:10 R Reserved CSR0_BLNDADJUST 9:8 R/W Stereo/Mono Blend Level Adjustment Set the RSSI range for stereo/mono blend 00 = 31~49 dBuv(default) 01 = 37~55 dBuv 10 = 19~37 dBuv 11 = 25~43 dBuv CSR0_SMUTERATE 7:6 R/W Softmute Enter/Recover Rate 00 = fastest(default) 01 = fast 10 = slow 11 = slowest CSR0_SMUTEATT 5:4 R/W Softmute Attenuation value 00 = 16dB(default) 01 = 14dB 10 = 12dB 11 = 10dB CSR0_VOLUME 3:0 R/W Volume 0000 = mute(default). 0001 = -28dBFS 1110 = -2dBFS 1111 = 0dBFS RTC6218(RL508)
Mar. 2014 Specifications subject to change without notice Confidential Proprietary Rev0.1 CHANNEL (Tuning channel setting), 03H Field Bits Type CSR0_TUNE R/W Enable Tune function 0 = Disable(default) 1 = Enable Reserved R Reserved CSR0_BAND 13:12 R/W Band Select 00 = 87.5~108MHz(default) 01 = 76~108MHz 10 = 76~91MHz 11 = 64~76MHz CSR0_CHSPACE 11:10 R/W Channel spacing 00 = 200kHz(default) 01 = 100kHz 10 = 50kHz CSR0_CH 9:0 R/W Tuning Channel Channel for tune operation SYSCONFIG (System configuration register), 04H Field Bits Type 15:14 R Reserved CSR0_DIS_AGC R/W Disable AGC 0 = Enable AGC (default) 1 = Disable AGC Reserved R Reserved Reserved 11:10 R Reserved Reserved 9:8 R Reserved Reserved 7:0 R Reserved SEEKCONFIG1 (Seek configuration register1), 05H Field Bits Type CSR0_SEEK R/W Enable Seek function 0 = Disable(default) 1 = Enable CSR0_SEEKUP R/W Seek Direction 0 = Seek down(default) 1 = Seek up CSR0_SKMODE R/W Seek Mode. 0 = Wrap at the upper or lower band limit and continue seeking (default). 1 = Stop seeking at the upper or lower band limit. Reserved 12:8 R Reserved CSR0_SEEKRSSITH 7:0 R/W RSSI Seek Threshold 0x00 = min RSSI(default) 0x7F = max RSSI RTC6218(RL508)
Mar. 2014 Specifications subject to change without notice Confidential Proprietary Rev0.1 POWERCONFIG (Power configuration register), 06H Field Bits Type CSR0_ENABLE R/W Power-up Enable Default = 0 CSR0_DISABLE R/W Power-up Disable Default = 0 Reserved 13:12 R Reserved CSR0_BLNDOFS 11:8 R/W Blending offset value, 2dB per step 0000 = 0 dB (default) 0001 = 2 dB 1111 = 30 dB Reserved 7:4 R Reserved CSR0_VOLEXT R/W 0: Volume attenuate 0dB more 1: Volume attenuate 15dB more CSR0_CLK_TYPE 2:0 R/W 000: 32.768KHz 001: 12MHz 010: 13MHz 011: 19.2MHz 100: 32.768KHz 101: 24MHz 110: 26MHz 111: 38.4MHz PADCONFIG (PAD configuration register), 07H Field Bits Type 15:0 R Reserved RESERVED1 (Reserved register1), 08H Field Bits Type 15:0 R Reserved RESERVED2 (Reserved register2), 09H Field Bits Type CSR0_OFSTH 15:8 R/W Seek DC offset fail threshold for 100k/200k spacing 0x00 = min DC value (default: 0x40) 0xFF = max DC value CSR0_QLTTH 7:0 R/W Seek audio quality fail threshold 0x00 = best quality (default: 0x10) 0xFF = worst quality RTC6218(RL508)
Mar. 2014 Specifications subject to change without notice Confidential Proprietary Rev0.1 STATUS (Status register and work channel), 0AH Field Bits Type R Reserved STD R Seek/Tune Done 0 = Not complete 1 = Done SF R Seek Fail 0 = Seek successful 1 = Seek failure Reserved R Reserved Reserved R Reserved SI R Stereo Indicator 0 = Mono 1 = Stereo READCH 9:0 R Read Channel RSSI (RSSI), 0BH Field Bits Type 15:8 R Reserved RSSI 7:0 R RSSI RSSI unit is dBuv RESERVED3 (Reserved register3), 0CH Field Bits Type 15:0 R Reserved RESERVED4 (Reserved register4), 0DH Field Bits Type 15:0 R Reserved. RESERVED5 (Reserved register5), 0EH Field Bits Type 15:0 R Reserved. RESERVED6 (Reserved register6), 0FH Field Bits Type 15:0 R Reserved. RTC6218(RL508)
T-ST508-DST-001 Data Sheet Mar. 2014 5. Pin Description Figure 5. Top View Table 7. Pin definition FM RF input. For single-ended operation GND Chip RF ground. Connect to ground plane on PCB. SCLK 2-wire serial clock input. SDIO 2-wire serial data input/output. RCLK External reference clock input. VDD Power supply voltage. ROUT Right audio output. LOUT Left audio output. Specifications subject to change without notice Confidential Proprietary Rev0.1 RTC6218(RL508)
Figure 7. Package outline Table 8. Package dimensions
Figure 8. PCB land pattern
T-ST508-DST-001 Data Sheet Mar. 2014
8 Application Schematic
8.1 Application Circuit for RCLK and headphone
Notes: 1. Place C4 closed to VDD pin 2. Options: the antenna matching network is kept for high sensitivity mode. 3. Strongly recommended to keep L5, L6, L7 and C9 when applying earphone antennas.
8.1.1 Bill Of Materials
C1, C2 Audio AC couple capacitors BLM15HD182SN1D L5, L6, L7 Ferrite bead keep high-impedance for RF path 100nF Supply bypass capacitor 100nF ,±20%,Z5U/X7R 4.7K R5, R6 I2C pull-up resistors 6.8pF C10 Antenna matching 220nH Antenna matching 1nF DC-blocking capacitor Specifications subject to change without notice Confidential Proprietary Rev0.1 RTC6218(RL508)