RTC-58321 EPSON | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 12
Technical content
Datasheet sections
http://www.spezial.cz - - - spezial@ spezial.cz - - - Hotlines: Tel (02) 2434 2200 - - - Fax (02) 2434 3200
4BIT REAL TIME CLOCK MODULE with I/O CONNECTIONS RTC-58321/58323 n Overview The RTC-58321/58323 is a CMOS real time clock modules with perpetual calendar function developed for microcomputer applications. It has a built-in 32.768 kHz quartz resonator, and provides clock and calendar registers for year, month, day, day-of-week, hours, minutes and seconds, with 12-hour/24-hour selection, plus automatic leap-year correction with software selection for local calendars, and an additional periodic reference signal output. Being a CMOS device, it has a very low power consumption for battery back-up purposes. n Features l Adjustment- free built-in quartz resonator keeps component count low. l Built-in clock and calendar registers for year, month, day, day-of-week, hours, minutes and seconds. l 12-hour/24-hour selection. l Automatic leap-year correction, with software selection for loca l calendars. l Counter start, stop and reset functions. l Periodic reference signal output selectable: 1024 Hz, or 1 second, 1 minute or 1 hour intervals. l Data bus is 4-bit bidirectional, with memory-type reads and writes. l CMOS device, for very low pow er consumption, and long battery back-up period. l Compatible at pin and function levels with the MSM58321 RS. n Pin connections 1. CS 2 2. WRITE 3. READ 4. D 0 5. D 1 6. D 2 7. D 3 8. GND 14 to 16. V DD 13. CS 12. TEST 11. STOP
10 BUSY
- ADDRESS WRITE * Connect power supply positive side to pin 16. 1 to 4. NC 5. CS 2 6. WRITE 7. READ 8. D 0 9. D 1 10. D 2 11. D 3 18 to 24. V DD 17. CS 1 16. TEST 15. STOP 14. BUSY 13. ADDRESS WRITE 12. GND NC: Pins are fixed low. * Connect power supply positive side to pin 24.
Pin numbers Pin symbol Input/output Function RTC-58321 RTC-58323 1 5 CS 2 Input Chip select. When high, device can be accessed. 2 6 WRITE Input Set high to write. 3 7 READ Input Set high to read. 4 to 7 8 to 11 D 0 to D 3 Both Address/data bus. 8 12 GND Negative power supply. 9 13 ADDRESS WRITE Input Address latch. Set high to latch address from D 0 to D 3 . 10 14 BUSY Output 1 Hz output pin. 11 15 STOP Input 1 Hz on/off control pin. When high, the 1 Hz signal is disabled, and the counter stopped. 12 16 TEST Input Increment pin for the counter. Normally this pin should be fixed low. 13 17 CS 1 Input Connect to power down detection circuit. (Fix high if there is no power down detection circuit.) When CS 1 is low, chip cannot be accessed, regardless of state of CS 2 . * 1 to 4 NC Fix low. 14 to 16 18 to 24 V DD Positive power supply (normally +5 V). * A bypass capacitor (minimum 0.01 µF) must be connected between V DD and V SS , as close as possible. Y10Y1 Day-of week 1/7 1/10|1/10 Year Month 1/10|1/3 Day or 1/12|1/24 Hours 1/10|1/6 Minutes 1/10|1/6 Seconds TEST DATA BUS ADDRESS WRITE D 2 D 3 D 1 D 0 CS2 CS1 READ WRITE TEST STOP 1'A BUSY OSC 32.768 kHz quarts oscillator 1Hz 1024Hz BUSY R 1/2 15 R MO10MO1D10D1WH10H1M110M11 S10 R 1 ’ R 1 ’ R 1 ’ R 1 ’ R 1 ’ R 1 ’ R 1 ’ N D S1 S10 M11 M110 H10 W D10 M01 M010 Y10 D E-F A B C D E-F D 10 ’ D 11 ’ D 12 ’ D 13 ’ u Rp = 200K Ω TYP TRI-STATE CONTROL ADDRESS LATCHE, FSWITCH 1024H z 1/3600Hz 1/60Hz1Hz
- Absolute maximum ratings Item Symbol Conditions (Pins) Rated Value Unit Power supply voltage V DD Ta = 25 °C, V DD -V SS -0.3 to +7.0 V Input voltages V I Ta = 25 °C input pins -0.3 to V DD +0.3 V Output voltages V O D 0 to D 3 -0.3 to V DD +0.3 V Storage temperature T STG Temperature stored as separate item. RTC-58321 -55 to +85 °C RTC-58323 -55 to +125 °C Soldering temperature T SOL RTC-58321 Maximum 260 °C for up to 10 seconds (pins); package maximum 150 °C. RTC-58323 Maximum 260 °C for up to 10 seconds (twice maximum), or maximum 230 °C for up to three minutes. 2. Operating Conditions Item Symbol Min. Typ. Max. Unit Notes Power supply V DD 4.5 5.0 5.5 V V DD -V SS Data hold voltage *1 V DH 2.2 − 5.5 Operating RTC-58321 T OP -10 − 70 ° C temperature RTC-58323 -30 − 85 *1 Data hold voltage: This is the range of power supply voltage for which the internal operation of the clock is guaranteed. I/O operations are not guaranteed. 3. Frequency characteristics Item Symbol Conditions Max. Unit RTC-58321 A Ta = 25 °C ± 10 Frequency RTC-58321 B Δf/ f O V DD = 5.0V ± 50 ppm tolerance RTC-58323 5 ± 20 Aging fa Ta = 25 °C :V DD = 5.0V ; first year ± 5 ppm/y Temperature characteristics *2 tOP V DD = 5.0V ; Ta = -10 to 70 °C + 10/-120 ppm Voltage characteristics f V V DD = 2.2 to 5.5V Ta fixed, 5V reference ± 2 ppm *2 Deviation from the frequency at 25 °C. Notes 1. Frequency tolerance based on V DD = 5.0 V. 2. Frequency tolerance is value guaranteed on factory shipment.
- DC characteristics RTC-58321 (V DD = 5V ± 0.5V, Ta = -10 to 70 °C) RTC-58323 (V DD = 5V ± 0.5V, Ta = -30 to 85 °C) Item Symbol Conditions Min. Typ. Max. Unit High input voltage V IH1 *1 3.6 V V IH2 *2 V DD - 0.5 V Low input voltage V IL 0.8 V Low output voltage V OL IOL = 1.6mA 0.4 V Low output current IOL V OL = 0.4V 1.6 mA High input current IIH *3 V IH = 5V 10 30 80 µA Low input current IIL *3 V IL = 0V -1 µA Input leakage current ILIH V IH = 5V 1 µA Input off-state leakage current ILIL V IL = 0V -1 Input capacity C I f = 1MHz 5 pF Current consumption IOP V DD = 5V *4 100 500 µA *5 20 40 V DD = 3V *4 15 30 *5 7 20 Oscillation start time *6 tOSC V DD = 5V 1.5 3.0 sec. Ta = 25 °C *1 Pins CS 2 , WRITE, READ, ADDRESS WRITE, STOP, TEST and D 0 to D 3 *2 CS 1 *3 Pins CS 1 , CS 2 , WRITE, READ, ADDRESS WRITE, STOP and TEST *4 CS 1 and CS 2 high, BUSY Open-circuit *5 CS 1 , CS 2 and BUSY Open-circuit *6 Confirmed by BUSY 5. AC characteristics RTC-58321 (V DD = 5V ± 0.5V, Ta = -10 to 70 °C) RTC-58323 (V DD = 5V ± 0.5V, Ta = -30 to 85 °C) Item Symbol Conditions Min. Typ. Max. Unit Chip select set-up time tCS − 0 − − µS Address set-up time tAS − 0 − − µS Address write pulse width tAW − 0.5 − − µS Address hold time tAH − 0.1 − − µS Data set-up time tDS − 0 − − µS Write pulse width tW W − 2 − − µS Data hold time tDH − 0 − − µS Read inhibit time tRI − 0 − − µS Read access time tRA − − − Q µS Read delay time tDD − − − 1 µS Chip select hold time tCH − 0 − − µS Q tRA = 1 µS + C × R × ln V V V DD DD H− min C : capacitance of data lin e R : pull-up resistance V H min : high voltage level of IC connected to data line ln : natural logarithm
- Timing chart 7. Data hold timing V DD CS2 or WR must not be activated. Data hold mode CS 1 ≤ 0.8V 2.2 to 4.5V 4.5V VI LVI L V IH2V IH2 tRtCDR 4.5V IC can interact with external circuit IC can interact with external circuit CS 1 CS 1 Address bus in IC Data bus in IC Address write Read Write D 0 to D 3 CS 2 Data-writeAddress High impedance Data invalid Data valid tCHtDDtRAtRItDHtWWtDStAHtAWtAStCS Data-read
- Register table Address D3 D2 D1 D0 Register DATA Count value Notes (hexadecimal) (A3) (A2) (A1) (A0) name D3 D2 D1 D0 0 0 0 0 0 S 1 s 8 s 4 s 2 s 1 0 to 9 Seconds units register 1 0 0 0 1 S 0 * s 40 s 20 s 10 0 to 5 Seconds tens register 2 0 0 1 0 MI 1 mi 8 mi 4 mi 2 mi 1 0 to 9 Minutes units register 3 0 0 1 1 MI 10 * mi 40 mi 20 mi 10 0 to 5 Minutes tens register 4 0 1 0 0 H 1 h 8 h 4 h 2 h 1 0 to 9 Hours units register 5 0 1 0 1 H 10 24/12 pm/am h 20 h 10 0 to 1 or 0 to 2 Hours tens register 6 0 1 1 0 W * w 4 w 2 w 1 0 to 6 Day-of-week register 7 0 1 1 1 D 1 d 8 d 4 d 2 d 1 0 to 9 Day units register 8 1 0 0 0 D 10 Leap year select d 20 d 10 0 to 3 Day tens register 9 1 0 0 1 MO 1 mo 8 mo 4 mo 2 mo 1 0 to 9 Month units register A 1 0 1 0 MO 10 * * * mo 10 0 to 1 Month tens register B 1 0 1 1 Y 1 y 8 y 4 y 2 y 1 0 to 9 Year units register C 1 1 0 0 Y 10 y 80 y 40 y 20 y 10 0 to 9 Year tens register D 1 1 0 1 * * * * Reset register E 1 1 1 0 1hour 1minute 1second 1024Hz Reference signal registers F 1 1 1 1 2. Notes (1) The device uses positive logic, and a logic high vo ltage corresponds to a 1 in a register bit. (2) Do not set the clock to impossible dates (17:34 pm on February 30th, for example). The results are unpredictable. (3) When the device is powered on, the initial settings of all bits are undefined. n Register functions 1. Date and time registers (1) The register values are in BCD, and used positive logic. (2) Day-of-week register The value is coded as 0 to 6, with Sunday = 0. Code 0 1 2 3 4 5 6 (3) pm/am, h 20 and h 10 registers The range of these values depends on whether the 12-hour or 24-hour clock is being used. The pm/am bit is used only when the 12-hour clock is selected. Set D 3 to 1 for the 24-hour, and to 0 for the 12-hour clock. Set D 2 to 1 for pm and to 0 for am. Writing a 1 to bit D 3 automatically resets bit D 2 to 0. Selection Value range 12-hour clock 12:00 to 11:59 am and pm * 24-hour clock 00:00 to 23:59 * Note: 12:00 am represents 12:00 midnight , and 12:00 pm represents 12:00 noon. (4) Y 1 and Y 10 Leap year selection Bits D 3 and D 2 of the day tens register select the year value module 4 to be used for leap years. Calendar D3 D2 Value module 4 for leap year Standard calendar 0 0 0 0 1 3 1 0 2 1 1 1 (5) Do not set the clock to impossible dates (17:34 pm on February 30th, for example). The results are unpredictable.
- Reset register (Control register D) Select this register to reset the last five stages of the 1/2 15 divider, and the busy circuit. Latch the hexadecimal value D using the ADDRESS LATCH pin, and set WRITE high to carry out the reset. 3. Reference signal (Control registers E and F) Latch the hexadecimal value E or F using the ADDRESS LATCH pin, and set WRITE high to obtain t he reference signal values on D 0 to D 3 . n Package dimensions (1) RTC-58321 ( Unit:mm) (2) RTC-58323
Note: The illustration is a general representation of the content and the location of information on the label, and is not a detailed specification of the typeface, size or positioning of printing used on the label. n Application notes (1) In order to realize low-power operation, the device has a high impedance; the shaded portion in the figure bel ow is highly susceptible to inductance effects, and should be kept clear of signal lines. (2) Power supply filter capacitor To ensure stable operation against transients and noise, connect a bypass capacitor of at least 0.01 µF (ceramic) across the power supply, close to the device. (3) This device passes a drop test (from 75 cm onto a hard board), but it is possible for the crystal resonator to be damaged by the shocks produced by some mounting equipment. It is important to confirm that the mounting conditions for the equipment being used do not adversely affect performance. Re-check if any of the mounting conditions change. (4) There is a possibility of damage to the crystal resonator during ultrasonic cleaning. Because of the wide variation of conditions in ultrasonic cleaning equipment, the performance of this device is not guaranteed if it is subject to ultrasonic cleaning. (5) This is a CMOS device, and the standard precautions against static electricity should be taken. RTC-58321 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 RTC-58323 24 23 22 21 20 19 18 1 7 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12