RTC4543 ETC | Alldatasheet

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Technical content

Absolute Max. rating Specifications (characteristics) Operating range Frequency characteristics DC characteristics External dimensions (Unit: mm) R4543 B 607 6AE 7.4–0.23.2–0.1 5.03.1 10.1–0.2 Terminal connection 0.150.6 0.05 min. No. 4543SA GND N.C CE FSEL WR FOE N.C N.C V DD CLK DATA N.C N.C F OUT 4543SB N.C N.C N.C N.C F OE WR FSEL CE GND FOUT DATA CLK N.C VDD N.C N.C N.C N.C 1234567 14 13 12 11 10 9 8 123456 18 17 16 15 14 13 0˚ to 10˚ RTC-4543SA RTC-4543SA(SOP 14-pin) RTC-4543SB RTC-4543SB(SOP 18-pin) 0.41.27 7.8–0.22.0 max. 5.41.8 11.4–0.2 0.150.6 0.05 min. 0˚ to 10˚ R4543 B 607 6AE

  • Builtin crystal unit allows adjustment-free efficient operation.
  • Automatic leap year correction.
  • Output selectable between 32.768 KHz/1 Hz.
  • Operating voltage range: 2.5V to 5.5V.
  • Supply voltage detection voltage: 1.7±0.3V.
  • Low current consumption: 1.0 µA/2.0V (Max.) SERIAL-INTERFACE REAL TIME CLOCK MODULE RTC-4543SA/SB Item Power source voltage Input voltage Output voltage Storage temperature Symbol V DD VIN VOUT TSTG Condition VDD-GND Min. -0.3 -55 Max. 7.0 VDD+0.3 +125 Unit V Item Operating voltage Date holding voltage Operating temperature Symbol VDD VCLK TOPR Condition Min. 2.5 1.4 -40 Max. 5.5 +85 Unit V Item Frequency tolerance Frequency temperature characteristics Frequency voltage characteristics Oscillation start time Aging Symbol Df/fo Top fV tOSC fa Condition Ta=25˚C, VDD=5V -10 to +70˚C Ta=25˚C, VDD=2.0 to 5.5V Ta=25˚C, VDD=2.5V First year Ta=25˚C, VDD=5V Range 5±23 +10/-120 Unit ppm ppm/V s ppm/year Item “H” input voltage “L” input voltage Input off-leak current “H” output voltage “L” output voltage Output leak current Supply detection voltage Output load conditions Current consumption Symbol VIH VIL IOFF VOH1 VOH2 VOL1 VOL2 IOZH IOZL VDT CL N IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 Condition Min. Typ. Max. Unit VDD=5.0V VDD=3.0V VDD=5.0V VDD=3.0V VOUT=5.5V VOUT=0V IOH=-1.0 mA DATA, FOUT pins IOH=1.0 mA DATA, FOUT pins CE="L", FOE="L" FSEL="H" CE="L", FOE="H" FSEL="L" No load on the FOUT pin DATA, FOUT pins FOUT pin 30 pF(max.) 2LS-TTL 1.7 VDD=5.0V VDD=3.0V VDD=2.0V VDD=5.0V VDD=3.0V VDD=2.0V 1.5 1.0 0.5 4.0 2.5 1.5 3.0 2.0 1.0 10.0 6.5 4.0 WR, DATA, CE, CLK, FOE,FSEL pins WR, CE, CLK, FOE,FSEL pins 0.8VDD 4.5 2.5 -1.0 1.4 0.2VDD 0.5 0.5 0.8 1.0 2.0 V mA mA mA V V (VDD=5V±0.5V, Ta=-40 to 85˚C) Actual size

Seconds (0 to 59) s 40 s 20 s 10 s 8 s 4 s 2 s 1 ∗Minutes (0 to 59) mi 40 mi 20 mi 10 mi 8 mi 4 mi 2 mi 1 ∗Hour (0 to 23) ∗ h 20 h 10 h 8 h 4 h 2 h 1 Day of the week (1 to 7) ∗ w 4 w 2 w 1 ∗Day (1 to 31) ∗ d 20 d 10 d 8 d 4 d 2 d 1 TMMonth (1 to 12) ∗ ∗ mo 10 mo 8 mo 4 mo 2 mo 1 y 80year (0 to 99) y 40 y 20 y 10 y 8 y 4 y 2 y 1 FDT bit: Supply voltage detection bit. TM bit: Test bit always set this bit to "0". Switching characteristics Block diagram Register table Timing chart 32.768 kHz FOUT CLK WR CE F SEL FOE DATA (Ta=-40 to +85˚C, CL=30 pF) Output controller I/O controller Control circuit Voltage detecter DividerOscillator Clock and calendar Shift register FOE FOUT FOUT DATA CLK CE WR DATA CLK CE WR VIL VIH Enabled High impedance Disabled tXZ tf 2 tSD tHD tDATA tCLKH tCLKH tCES tCES tCLK tCLK tWRS tWRS tr1 tCE tCE tf1 tr1 tf1 tCEH tOZ tCEH tRCV tRCV tWRH tWRH tCLKL tCLKL tr2 t tH tZX Duty= x 100 t tH [%] Data read Data write FOUT Disabled and Enabled Item CLK clock cycle CLK high pulse width CLK low pulse width CE setup time CE hold time CE enable time Write data setup time Write data hold time WR setup time WR hold time DATA output delay time DATA output floating time Clock input rise time Clock input fall time F OUT rise time FOUT fall time Disable time Enable time F OUT duty ratio Wait time Symbol t CLK t CLKH t CLKL t CES t CEH t CE t SD t HD t WRS t WRH t DATA t DZ t r1 t f1 t r2 t f2 t XZ t ZX Duty t rcv Min. 0.75 0.375 0.1 100 0.95 Max. 7800 3900 0.9 0.2 0.1 100 Min. 1.5 0.75 0.2 0.1 100 1.9 Max. 7800 3900 0.9 0.4 0.2 100 200 Unit ms s ms ns ms ns ms CL= 30pF VDD= 5V± 10% V DD= 3V± 10%