L6919C STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 32
Technical content
■ 2 PHASE OPERATION WITH SYNCRHONOUS RECTIFIER CONTROL ■ ULTRA FAST LOAD TRANSIENT RESPONSE ■ INTEGRATED HIGH CURRENT GATE DRIVERS: UP TO 2A GATE CURRENT ■ TTL-COMPATIBLE 5 BIT PROGRAMMABLE OUTPUT FROM 0.800V TO 1.550V WITH 25mV STEPS ■ DYNAMIC VID MANAGEMENT ■ 0.6% OUTPUT VOLTAGE ACCURACY ■ 10% ACTIVE CURRENT SHARING ACCURACY ■ DIGITAL 2048 STEP SOFT-START ■ OVERVOLTAGE PROTECTION ■ OVERCURRENT PROTECTION REALIZED USING THE LOWER MOSFET'S R dsON OR A SENSE RESISTOR ■ OSCILLATOR EXTERNALLY ADJUSTABLE AND INTERNALLY FIXED AT 200kHz ■ POWER GOOD OUTPUT AND INHIBIT FUNCTION ■ REMOTE SENSE BUFFER ■ PACKAGE: SO-28
APPLICATIONS
■ POWER SUPPLY FOR SERVERS AND WORKSTATIONS ■ POWER SUPPLY FOR HIGH CURRENT MICROPROCESSORS ■ DISTRIBUTED POWER SUPPLY
DESCRIPTION
The device is a power supply controller specifically de- signed to provide a high performance DC/DC conver- sion for high current microprocessors. The device implements a dual-phase step-down controller with a 180° phase-shift between each phase. A precise 5-bit digital to analog converter (DAC) allows adjusting the output voltage from 0.800V to 1.550V with 25mV binary steps managing On-The-Fly VID code changes. The high precision internal reference assures the se- lected output voltage to be within ±0.6%. The high peak current gate drive affords to have fast switching to the external power mos providing low switching losses. The device assures a fast protection against load over current and load over/under voltage. An internal crowbar is provided turning on the low side mosfet if an over-voltage is detected. In case of over-current, the system works in Constant Current mode. SO-28 ORDERING NUMBERS:L6919CD L6919CDTR
5 BIT PROGRAMMABLE DUAL-PHASE CONTROLLER
WITH DYNAMIC VID MANAGEMENT BLOCK DIAGRAM CURRE NT REA DING IFB TO TA L CURRE NT CURRE NT AVG CH1 OCP DAC DI GITAL SO F T- S T ART LOGI C PW M ADA P TI VE ANTI CRO SS CO ND UCT IO N CH1 O CP
2 PHASE
Symbol Parameter Value Unit Vcc, VCCDR to PGND 15 V VBOOT -VPHASE Boot Voltage 15 V VUGA TE1-VPHASE1 VUGA TE2-VPHASE2 15 V LGA TE1, PHASE1, LGATE2, PHASE2 to PGND -0.3 to Vcc+0.3 V VID0 to VID4 -0.3 to 5 V All other pins to PGND -0.3 to 7 V Vphase Sustainable Peak Voltage t < 20ns @ 600kHz 26 V Symbol Parameter Value Unit R th j-amb Thermal Resistance Junction to Ambient 60 °C/W Tmax Maximum junction temperature 150 °C Tstorage Storage temperature range -40 to 150 °C Tj Junction T emperature Range 0 to 125 °C PMAX Max power dissipation at Tamb = 25°C 2 W 28LGATE1 VCCDR PHASE1 FB BOOT1 UGATE1 VSEN VCC SGND COMP ISEN1 PGNDS1 FBR FBG VID3 VID2 VID1 VID4 BOOT2 PGOOD UGATE2 PHASE2 LGATE2 PGND OSC / INH / FAULT ISEN2 PGNDS2 VID0 L6919C
ELECTRICAL CHARACTERISTICS
VCC = 12V ±10% , TJ = 0 to 70°C unless otherwise specified Symbol Parameter Test Condition Min Typ Max Unit Vcc SUPPL Y CURRENT ICC Vcc supply current HGA TEx and LGATEx open VCCDR =VBOOT =12V 7.5 10 12.5 mA ICCDR VCCDR supply current LGA TEx open; V CCDR =12V 2 3 4 mA IBOOTx Boot supply current HGA TEx open; PHASEx to PGND VCC =VBOOT =12V 0.5 1 1.5 mA POWER-ON Turn-On VCC threshold V CC Rising; VCCDR =5V 8 9.2 10.4 V Turn-Off VCC threshold V CC Falling; VCCDR =5V 6.5 7.5 8.5 V Turn-On VCCDR Threshold VCCDR Rising VCC =12V 4.2 4.4 4.6 V Turn-Off VCCDR Threshold VCCDR Falling VCC =12V 4.0 4.2 4.4 V OSCILLATOR/INHIBIT/FAULT fOSC Initial Accuracy OSC = OPEN OSC = OPEN; Tj=0°C to 125°C 185 180 200 215 220 kHz kHz fOSC,Rosc Total Accuracy R T to GND=74kΩ 360 400 440 kHz INH Inhibit threshold I SINK=5mA 0.5 V dMAX Maximum duty cycle OSC = OPEN; I FB = 0 75 80 % OSC = OPEN; IFB = 60µA3 8 4 6 % ΔVosc Ramp Amplitude 1.8 2 2.2 V FAULT Voltage at pin OSC OVP or UVP Active 4.75 5.0 5.25 V REFERENCE AND DAC Output Voltage Accuracy VID0, VID1, VID2, VID3, VID4 see T able1; FBR = VOUT ; FBG = GND -0.6 - 0.6 % IDAC VID pull-up Current VIDx = GND 4 5 6 µA VID pull-up Voltage VIDx = OPEN 3.2 - 3.5 V ERROR AMPLIFIER DC Gain 80 dB SR Slew-Rate COMP=10pF 15 V/ µs DIFFERENTIAL AMPLIFIER (REMOTE BUFFER) DC Gain 1 V/V CMRR Common Mode Rejection Ratio 40 dB SR Slew Rate VSEN=10pF 15 V/ µs
DIFFERENTIAL CURRENT SENSING IISEN1, IISEN2 Bias Current I LOAD = 0 45 50 55 µA IPGNDSx Bias Current 45 50 55 µA IISEN1, IISEN2 Bias Current at Over Current Threshold 80 85 90 µA IFB Active Droop Current I LOAD ≤ 0% ILOAD = 100% 47.5 52.5 µA µA GATE DRIVERS tRISE HGA TE High Side Rise Time VBOOTx -VPHASEx =10V; C HGATEx to PHASEx=3.3nF 15 30 ns IHGA TEx High Side Source Current VBOOTx -VPHASEx =10V 2 A R HGA TEx High Side Sink Resistance VBOOTx -VPHASEx =12V; 1.5 2 2.5 Ω tRISE LGATE Low Side Rise Time VCCDR =10V; C LGATEx to PGNDx=5.6nF 30 55 ns ILGA TEx Low Side Source Current VCCDR =10V 1.8 A R LGA TEx Low Side Sink Resistance VCCDR =12V 0.7 1.1 1.5 Ω PROTECTIONS PGOOD Upper Threshold (VSEN /DAC Output) VSEN Rising 108 112 116 % PGOOD Lower Threshold (VSEN /DAC Output) VSEN Falling 84 88 92 % OVP Over Voltage Threshold (VSEN ) VSEN Rising 1.915 2.05 V UVP Under Voltage T rip (VSEN /DAC Output) VSEN Falling 65 70 75 % VPGOOD PGOOD Voltage Low I PGOOD = -4mA 0.3 0.4 0.5 V ELECTRICAL CHARACTERISTICS (continued) VCC = 12V ±10% , TJ = 0 to 70°C unless otherwise specified Symbol Parameter Test Condition Min Typ Max Unit
Table 1. Voltage Identification (VID) Codes
1 LGA TE1 Channel 1 low side gate driver output. 2 VCCDR LS Mosfet driver supply. It can be varied from 5V to 12V . 3 PHASE1 This pin is connected to the source of the upper mosfet and provides the return path for the high side driver of channel 1. 4 UGA TE1 Channel 1 high side gate driver output. 5 BOOT1 Channel 1 bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper mosfet. Connect through a capacitor to the PHASE1 pin and through a diode to Vcc (cathode vs. boot). 6 VCC Device supply voltage. The operative supply voltage is 12V . 7 GND All the internal references are referred to this pin. Connect it to the PCB signal ground.
8 COMP This pin is connected to the error amplifier output and is used to compensate the control
feedback loop.
9 FB This pin is connected to the error amplifier inverting input and is used to compensate the voltage
control feedback loop. A current proportional to the sum of the current sensed in both channel is sourced from this pin (50µA at full load, 70µA at the 140% Constant Current threshold). Connecting a resistor between this pin and VSEN pin allows programming the droop effect.
10 VSEN Connected to the output voltage it is able to manage Over&Under-voltage conditions and the
PGOOD signal. It is internally connected with the output of the Remote Sense Buffer for Remote Sense of the regulated voltage. If no Remote Sense is implemented, connect it directly to the regulated voltage in order to manage OVP , UVP and PGOOD. 11 FBR Remote sense buffer non-inverting input. It has to be connected to the positive side of the load to perform a remote sense. If no remote sense is implemented, connect directly to the output voltage (in this case connect also the VSEN pin directly to the output regulated voltage). 12 FBG Remote sense buffer inverting input. It has to be connected to the negative side of the load to perform a remote sense. Pull-down to ground if no remote sense is implemented. 13 ISEN1 Channel 1 current sense pin. The output current may be sensed across a sense resistor or across the low-side mosfet R dsON. This pin has to be connected to the low-side mosfet drain or to the sense resistor through a resistor Rg in order to program the over current intervention for this phase at 140% as follow: Where 35µA is the current offset information relative to the Over Current condition (offset at OC threshold minus offset at zero load). The net connecting the pin to the sense point must be routed as close as possible to the PGNDS1 net in order to couple in common mode any picked-up noise. 14 PGNDS1 Channel 1 Power Ground sense pin. The net connecting the pin to the sense point must be routed as close as possible to the ISEN1 net in order to couple in common mode any picked-up noise. PGNDS2 Channel 2 Power Ground sense pin. The net connecting the pin to the sense point must be routed as close as possible to the ISEN2 net in order to couple in common mode any picked-up noise. IOCPx 35µ AR g⋅
16 ISEN2 Channel 2 current sense pin. The output current may be sensed across a sense resistor or across the low-side mosfet RdsON. This pin has to be connected to the low-side mosfet drain or to the sense resistor through a resistor Rg in order to program the over current intervention for this phase at 140% as follow: Where 35µA is the current offset information relative to the Over Current condition (offset at OC threshold minus offset at zero load). The net connecting the pin to the sense point must be routed as close as possible to the PGNDS2 net in order to couple in common mode any picked-up noise.
17 OSC/
Oscillator switching frequency pin. Connecting an external resistor from this pin to GND, the external frequency is increased according to the equation: Connecting a resistor from this pin to Vcc (12V), the switching frequency is reduced according to the equation: If the pin is not connected, the switching frequency is 200KHz. Forcing the pin to a voltage lower than 0.6V , the device stop operation and enter the inhibit state. The pin is forced high when an Over/Under Voltage is detected. This condition is latched; to recover it is necessary turn off and on VCC. 18-22 VID4-0 Voltage IDentification pins. These input are internally pulled-up and TTL compatible. They are used to program the output voltage as specified in T able 1 and to set the power good thresholds. Connect to GND to program a ‘0’ while leave floating to program a ‘1’. 23 PGOOD This pin is an open collector output and is pulled low if the output voltage is not within the above specified thresholds. If not used may be left floating. 24 BOOT2 Channel 2 bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper mosfet. Connect through a capacitor to the PHASE2 pin and through a diode to Vcc (cathode vs. boot). 25 UGA TE2 Channel 2 high side gate driver output. 26 PHASE2 This pin is connected to the source of the upper mosfet and provides the return path for the high side driver of channel 2. 27 LGA TE2 Channel 2 low side gate driver output. 28 PGND Power ground pin. This pin is common to both sections and it must be connected through the closest path to the low side mosfets source pins in order to reduce the noise injection into the device. PIN FUNCTION (continued) N Name Description IOCPx 35µ AR g⋅ fS 200kHz 14.82 106⋅ fS 200kHz 12.91 107⋅
triangular waveform. When an under voltage is detected the device latches and the FAULT pin is driven high. driver and driving high the FAULT pin. the current sunk (forced) from (into) the pin considering the internal gain of 12KHz/µA. Figure 1. ROSC vs. Switching Frequency
/ Under Voltage protection (OVP/UVP) thresholds. ing the transition and it is re-activated after the transition has finished while OVP / UVP are still active. Figure 2. Dynamic VID transition 2048 clock periods as shown in figure 3. mode: all the power mosfets are turned off and protections are disabled. Setting the INH pin free, causes the device to restart.
1 Clock Cycle Blanking Time
Figure 3. Soft Start Figure 4. Drivers peak current: High Side (left) and Low Side (right) R dsON ), maintaining fast switching transition. CDRV pin is required to start operations of the device. than 240ns, the low side mosfet is switched on so allowing the negative current of the inductor to recirculate. This mechanism allows the system to regulate even if the current is negative.
2048 Clock Cycles
is also flexible; 5V or 12V bus can be chosen freely. by the external resistor Rg placed outside the chip between ISENx and PGNDSx pins toward the reading points. sense is implemented to avoid absolute maximum rating overcome on ISENx pin). Figure 5. Current Reading Timing (Left) and Circuit (Right)
pared to IAVG to give the correction to the PWM output in order to equalize the current carried by the two phases.
- TON Limited Output Voltage.
age follows the resulting characteristic (dotted in Figure 6b) until UVP is detected or anyway until IFB = 70µA. Figure 6. TON Limited Operation
0.80 T IFB⋅ 0µ A =
0.40 T IFB⋅ 70 µ A=
(2048 clock cycles after start-up). (set at 1.976V) and the reference programmed by VID. more than one clock period the device turns off and the FAULT is driven high. en by the 2048 soft start digital counter. pin with unity gain eliminating the errors. voltage. In this case the FBG and FBR pins must be connected anyway to the regulated voltage. with a single phase operation. Figure 10. Input RMS Current vs. Duty Cycle (D) and Driving Relationships
It can be observed that the input rms value is one half of the single-phase equivalent input current in the worst case condition that happens for D = 0.25 and D = 0.75. The power dissipated by the input capacitance is then equal to: Input capacitor is designed in order to sustain the ripple relative to the maximum load duty cycle. To reach the high RMS value needed by the CPU power supply application and also to minimize components cost, the input capacitance is realized by more than one physical capacitor. The equivalent RMS current is simply the sum of the single capacitor's RMS current. Input bulk capacitor must be equally divided between high-side drain mosfets and placed as close as possible to reduce switching noise above all during load transient. Ceramic capacitor can also introduce benefits in high frequency noise decoupling, noise generated by parasitic components along power path. OUTPUT CAPACITOR Since the microprocessors require a current variation beyond 50A doing load transients, with a slope in the range of tenth A/µs, the output capacitor is a basic component for the fast response of the power supply. Dual phase topology reduces the amount of output capacitance needed because of faster load transient response (switching frequency is doubled at the load connections). Current ripple cancellation due to the 180° phase shift between the two phases also reduces requirements on the output ESR to sustain a specified voltage ripple. When a load transient is applied to the converter's output, for first few microseconds the current to the load is supplied by the output capacitors. The controller recognizes immediately the load transient and increases the duty cycle, but the current slope is limited by the inductor value. The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the ESL): ΔVOUT = ΔIOUT · ESR A minimum capacitor value is required to sustain the current during the load transient without discharge it. The voltage drop due to the output capacitor discharge is given by the following equation: Where DMAX is the maximum duty cycle value. The lower is the ESR, the lower is the output drop during load transient and the lower is the output voltage static ripple. INDUCTOR DESIGN The inductance value is defined by a compromise between the transient response time, the efficiency, the cost and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain the ripple current ΔIL between 20% and 30% of the maximum output current. The inductance value can be cal- culated with this relationship: Where fSW is the switching frequency, VIN is the input voltage and VOUT is the output voltage. Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter response time to a load transient. The response time is the time required by the inductor to change its current from initial to final value. Since the inductor has not finished its charging time, the output current is supplied by the output capacitors. Minimizing the response time can minimize the output capacitance required. The response time to a load transient is different for the application or the removal of the load: if during the ap- P RMS ESR I RMS() 2⋅= V OUTΔ IOUT 2Δ L⋅ L V IN V OUT– V OUT V IN
and it is used to adjust the duty cycle whose dominant value is set by the error amplifier at COMP pin (See fig. 13). The current sharing control is a high bandwidth control loop allowing current sharing even during load transients. Δ IREAD is the difference between one phase current and the ideal current (IMAX /2). Figure 13. Current Sharing Control Loop pin flows into RFB implementing the dependence of the output voltage from the read current.
Figure 14. ACM Control Loop Gain Block Diagram (left) and Bode Diagram (right)
to consider when designing such high current applications. These are the connections where switching and continuous current flows from the input supply towards the load. each connection as much as possible. nection is suggested to minimize effects due to multiple connections. Figure 15. Power connections and related connections layout guidelines (same for both phases)
eliminate the stray inductance generated by the copper traces. Low ESR and ESL capacitors are required. ■ Power Connections Related. losses for the high side mosfet are significantly increased. Figure 16. Device orientation (left) and sense nets routing (right) mize the loop that is created. – Decoupling capacitor from Vcc and SGND placed as close as possible to the involved pins. sustains the peak currents requested by the low-side mosfet drivers. the optional resistor from FB to GND used to give the positive droop effect. and to ensure the right precision to the regulation when the remote sense buffer is not used.
low side mosfets, to a value lower than 26V, for 20nSec, at FSW of 600kHz max. ■ Current Sense Connections. ulation, increasing output tolerance. this case the device won't work properly. Route anyway to the LS mosfet source (together with ISENx net). Right and wrong connections are reported in Figure 17. Symmetrical layout is also suggested to avoid any unbalance between the two phases of the converter. Figure 17. PCB layout connections for sense nets Wrong (left) and correct (right) connections for the current reading sensing nets.
Figure 22. PCB and Components Layouts (Dimensions: 10.8mm x 8.2mm)
CPU Power Supply: 5 to 12VIN; 1.2VOUT ; 45ADC Considering the high slope for the load transient, a high switching frequency has to be used. In addition to fast reaction, this helps in reducing output and input capacitor. Inductance value is also reduced. A switching frequency of 200kHz for each phase is then considered allowing large bandwidth for the compen- sation network. Considering the high output current, power conversion will start from the 12V bus. – Current Reading Network and Over Current: Since the maximum output current is IMAX = 45A, the over current threshold has been set to 45A (22.5A x 2)in the worst case (max mosfet temperature). Since the device limits the valley of the triangular ripple across the inductors, the current ripple must be considered too. Considering the inductor core satura- tion, a current ripple of 10A has to be considered so that the OCP threshold in worst case becomes OCPx=17A (22.5A-5A). Considering to sense the output current across the low-side mosfet RdsON, SUB85N03L-04P has 4.3mΩ max at 25°C that becomes 5.6mΩ at 100ºC considering the temperature variation; the resulting transconductance resistor Rg has to be: – Droop function Design: Considering a voltage drop of 70mV at full load, the feedback resistor R FB has to be: – Inductor design: Transient response performance needs a compromise in the inductor choice value: the biggest the in- ductor, the highest the efficient but the worse the transient response and vice versa. Considering then an inductor value of 0.8µH, the current ripple becomes: – Output Capacitor: Five Rubycon MBZ (2200µF / 6.3V / 12mΩ max ESR) has been used implementing a resulting ESR of 2.4mΩ resulting in an ESR voltage drop of 45A · 2.4mΩ = 108mV after a 45A load transient. – Compensation Network: A voltage loop bandwidth of 20kHz is considered to let the device fast react after load transient. The R F CF network results: (R8) (C2) Further adjustments can be done on the work bench to fit the requirements and to compensate layout parasitic components. Rg I OCPx R dsON R FB 70mV IΔ Vin Vout– R F R FB V OSΔ⋅ VIN 4--- ω T L 4---20K 2 Π 0.8µ 2 5.6m ⋅ C F Co L 2---⋅ R F 62 2 0 0µ 1µ
DIM. mm inch A 2.65 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 C 0.5 0.020 c1 45 ° (typ.) D 17.7 18.1 0.697 0.713 E 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 F 7.4 7.6 0.291 0.299 L 0.4 1.27 0.016 0.050 S8 ° (max.) OUTLINE AND MECHANICAL DATA
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com L6919C