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www.onsemi.com © Semiconductor Components Industries, LLC, 2019 May, 2022 − Rev. 1
1 Publication Order Number:
Bluetooth/C0041 5.2 Wireless MCU RSL15 Introduction RSL15 is an ultra −low power secure Arm ® Cortex ®−M33 processor−based Bluetooth Low Energy 5.2 wireless MCU designed for connected smart devices in industrial and medical applications. The comprehensive, yet easy −to−use Software Development Kit (SDK) provides sample applications that demonstrate the hardware capabilities to enable security with the Cybersecurity Platform, acquire sensor data in Smart Sense mode, configure the built−in power management and utilize Bluetooth Low Energy features. Key Features
- Bluetooth Low Energy 5.2 Certified with Key Features: ♦ Up to 10 simultaneous connections ♦ Long Range (Coded PHY) ♦ 2 Mbit PHY (High Speed) ♦ Angle of Arrival (AoA) and Angle of Departure (AoD) ♦ Extended Advertising ♦ Backwards compatibility and support for earlier Bluetooth Low
- Ultra−low Power Operation: ♦ Sleep Mode (GPIO Wakeup) @ 3 V VBAT: 36 nA ♦ Sleep Mode (Crystal Oscillator, RTC Timer Wakeup) @ 3 V VBA T: 81 nA ♦ Smart Sense Mode allows some digital and analog peripherals to remain active to monitor and acquire data from external sensors at a very low system−level power consumption ♦ Continuous ADC operation in Smart Sense Mode with wakeup on ADC threshold @ 3 V VBAT: 186 nA ♦ Peak Rx Current 1 Mbps @ 3V VBAT: 2.7 mA ♦ Peak Tx Current 0 dBm Output Power @ 3 V VBAT: 4.3 mA ♦ Non−Connectable Advertising at 5 s Intervals @ 3 V VBAT: 1.1 /C0109A (Average) ♦ Connectable Advertising at 5 s Intervals @ 3 V VBAT: 1.3 /C0109A (Average)
- Rx Sensitivity (BLE Mode, 1 Mbps): −96 dBm
- Rx Sensitivity (BLE Mode, 2 Mbps): −94 dBm
- Configurable Tx Power: −17 dBm to +6 dBm
- Data Rate of 62.5 kbps to 2000 kpbs
- Arm Cortex−M33 processor clocked up to 48 MHz
- Cybersecurity Platform with Arm CryptoCell™−312 for End−to−end Product Security with Secure Boot, Root of Trust, Lifecycle Management, Secure Key Management, and Application and Data Security
- Arm TrustZone® to enable secure execution zones QFN40 5x5, 0.4P CASE 485CR See detailed ordering and shipping information on page 2 of this data sheet.
ORDERING INFORMATION
Key Features (continued)
- Two Flash Memory Sizes Available, 284 kB Flash (NCH−RSL15−284−101Q40−ACG) or 512 kB Flash (NCH−RSL15−512−101Q40−ACG)
- 80 kB RAM (64 kB user RAM, 16 kB RAM for Baseband)
- Flexible Power Management: 1.2 V – 3.6 V VBAT. Directly connect 1.5 V Silver−oxide or 3 V Coin Cells without any external active components
- Two SPI ports with QSPI capability 401 RSL15 AWLYYWW/C0071 /C0071 RSL15 = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week /C0071= Pb−Free Package (Note: Microdot may be in either location) MARKING DIAGRAM
www.onsemi.com NCH−RSL15−284−101Q40−ACG QFN40 1500 Tape/Reel NCH−RSL15−512−101Q40−ACG QFN40 1500 Tape/Reel
APPLICATIONS
- Drug Injection Pens
- Blood Glucose Meters
- Wearable Bracelets
- Blood Analyzers
- Virus Detectors
- Smart Toothbrushes
- Heart Rate Monitors
- Bottle Caps
- Sleep Monitors
- Avalanche Detectors
- Electronic Pens
- Electronic Bikes
- Bicycle Computers
- Pet Trackers
- E−Stethoscopes
- Shavers
- Vacuum Cleaners
- SpO2 Monitors
- Wearable Head Bands Smart Building
- Electronic Access Badges
- Air Filter Sensors
- Windows Surveillance
- Smoke Alarms
- Key Pads
- Energy Harvesting Switches
- HV AC Systems
- Vending Machines
- Lighting Mesh Control Smart Industry
- Electronic Tags
- Power Tools
- Shopping Cart Trackers
- Coldchain Monitors
- Electronic Labels
- Beverage Dispensers
- Charge Control Systems
- Worker Safety Applications
- Battery Management Systems
- Machine Monitors
- Data Loggers
- Helmets
- Pellet Tracking
- Electronic Wheel Nuts
- Food Tracking Sensors Smart Home
- Smart Circuit Breakers
- Smart Thermometers
- Smart Light Switches
- Smart Meters
- Coffee Makers
- Smart Refrigerators
- Air Purifiers
- Garage Door Controls
- Sprinkler Control Systems Smart City
- People and Asset Tracking
- Door Access Control
- Fleet Management Systems
- Outdoor Robots
- Bioprocessing Equipment
- Educational Robots
Figure 1. High−Level Block Diagram
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FEATURES
Arm Cortex−M33 Processor The Cortex−M33 32−bit Armv8−M processor is designed for IoT and deeply embedded applications that require high performance, power efficiency and security. The processor has many features to execute high performance applications such a Floating −Point Unit (FPU), DSP extensions and Memory Protection Unit (MPU). Secure debug is done through the SWJ −DP which combines JTAG −DP and SW−DP for either JTAG probe or Serial Wire Debug (SWD) connection. Cybersecurity Platform The Cortex−M33 processor with TrustZone Armv8 −M security extensions forms the basis of the security platform. The Arm CryptoCell−312 allows for end −to−end product security with Secure Boot with Root of Trust, secure lifecycle management, secure key management, and application and data encryption using symmetric or asymmetric cryptography. Arm TrustZone enables secure software access control. User available cryptographic services such as SHA1, SHA256, keyed −hash message authentication code (HMAC) and True Random Number Generator (TRNG) allow for development of custom proprietary security solutions. The TRNG conforms to NIST SP800−90B, NIST SP800−22, FIPS 140−2, and BSI AIS−31. Please note that this mobile telecommunications Radio Access Network (RAN) equipment is designed for civil use, which also meet the provisions of paragraphs a.2 to a.4 of the Cryptography Note (Note 3 in Category 5—Part 2), having an RF output power limited to 0.1 W (20 dBm) or less, and supporting 16 or fewer concurrent users. RF Subsystem The RF architecture is based on a 2.4 GHz RF Front End that implements the physical layer of the BLE 5.2 standard as well as other proprietary or custom protocols. The modem is of the FSK type with a single −ended RF Port, which alleviates the need for an external balun. RF Operation Bluetooth 5.2 certified baseband and protocol stack has features such as 2 Mbps RF link, Angle −Of−Arrival, Angle−Of−Departure, and Coded PHY (“Long Range”). The hardware enables implementation of custom protocols. Localization RSL15 supports Angle −of−Arrival (AoA) and Angle−of−Departure (AoD) as defined by the Bluetooth Low Energy standard along with RSSI for enhanced localization capabilities. Flexible Power Management Built−in DC−DC converter with buck and LDO modes requiring few external passive components allows for a broad voltage supply range. Any voltage in the range of 1.2 V to 3.6 V can be used directly without the need for external power conversion allowing for simple use of common coin cell batteries such as 3 V coins cells and 1.5 V silver oxide cells. Power Modes Several power modes are available to reduce power consumption while still maintaining system responsiveness. Each mode is configurable with RAM retention and wakeup sources. Smart Sense mode allows some digital and analog peripherals to remain active to monitor and acquire data from external sensors at a very low system −level power consumption. Flexible Clocking Two crystal oscillators and two internal RC oscillators are available on RSL15 to offer many clocking configurations. The primary oscillator is based on a 48 MHz crystal, which is necessary for any connected RF operation. The secondary oscillator is based on a 32 kHz crystal, which can be used for precision timing even in low power modes. When precision timing is not required, the internal fast RC oscillator can be used in place of the 48 MHz crystal oscillator for general non−RF processing. Likewise, the internal 32 kHz RC oscillator can be used in place of the 32 kHz crystal oscillator for certain use cases. Additionally, 48 MHz and 32 kHz external clocks can be driven into RSL15 from external clock sources. Analog to Digital Converters (ADCs) RSL15 has two ADCs, a high−speed 12−bit SAR ADC for fast conversion of analog inputs up to 2 Msps and Low Speed ADC for slower conversion up to 50 ksps. There is also an integrated temperature sensor that can be read by the Low Speed ADC. Flexible I/O General purpose I/O can be mapped to GPIO, SPI, QSPI, I2C, UART, PWM, PCM, pulse counter, clock input/output and analog functions. RSL15 facilitates an analog comparator, as well as a DAC for generating bias voltages for external components, and a current source output. Memory Architecture The memory architecture is centered around the Arm Cortex−M33. The flash memory contains application code as well as the protocol stack. The RAM architecture is flexible allowing for powering only the amount of memory needed for the application. A total of 64 kB user RAM is available, implemented as 8 times 8 kB. An additional 16 kB is available for the digital baseband hardware. A DMA controller is available for easy data streaming between a peripheral/interface and memories.
www.onsemi.com Software Development Kit Contains Eclipse −based ON Semiconductor IDE plus support for other industry standard development environments, Bluetooth protocol stack, sample applications, libraries and many other software components and tools to enable rapid application development. RoHS Compliant Device RSL15 is RoHS compliant.
Figure 2. RSL15 Detailed Block Diagram
www.onsemi.com Cybersecurity Platform The Cortex−M33 processor with TrustZone Armv8 −M security extensions forms the basis of the security platform that is extended with Arm CryptoCell−312. Secure Boot with Root of Trust The secure boot ROM authenticates firmware in flash with a certificate−based mechanism using a private−public key scheme. This is the basis of the hardware Root of Trust. This same mechanism ensures continuity of the hardware Root of Trust after secure Firmware −Over−The−Air (FOTA) update. Data and Application Encryption User available cryptographic services including AES−128, AES −256, SHA −256, Hash Message Authentication Code (HMAC), PKA (Public Key Accelerator), ChaCha and AIS−31 compliant True Random Number Generator (TRNG) allow for development of custom proprietary security solutions. TrustZone Enables secure software access control to protect critical software and hardware resources. Secure Lifecycle State Management Lifecycle states refers to the multiple states RSL15 could go through during its lifetime. The first lifecycle state is the Chip Manufacture (CM) Lifecycle State. The device manufacture transitions to the Device Manufacture (DM) Lifecycle State. At field deployment, it is transitioned to the Secure (SE) Lifecycle State. A Return to Manufacturer (RMA) State is also available. Lifecycle state management ensures the authenticity, integrity and confidentiality of code and data belonging to different stakeholders at each lifecycle. In addition to the Secure Lifecycle States, an Energy Harvesting (EH) Mode is available for applications that require fast cold startup (initial application of VBAT) but do not require secure boot with Root of Trust. This mode is especially useful when RSL15 is used in energy harvesting systems. RF Subsystem The RSL15 2.4 GHz radio front −end implements the physical layer for the Bluetooth Low Energy standard and other standard, proprietary, or custom protocols. It operates in the worldwide deployable 2.4 GHz ISM band (2.4000 to 2.4835 GHz). RF Architecture The 2.4 GHz radio front −end is based on a low −IF architecture and comprises the following building blocks:
- High performance single−ended RF port which alleviates the need for an external balun
- On−chip matching network with 50 /C0087 RF input
- Low power LNA (low noise amplifier), and mixer
- PA (Power Amplifier) with up to +6 dBm output power for Bluetooth
- RSSI (Received Signal Strength Indication) with 60 dB nominal range with 1 dB steps (not considering AGC)
- Fully integrated ultra−low power frequency synthesis with fast settling time, with direct digital modulation in transmission (pulse shape programmable)
- 48 MHz XTAL reference
- Fully−integrated FSK−based modem with programmable pulse shape, data rate, and modulation index
- Digital baseband (DBB) with link layer functionalities, including automatic packet handling with preamble & sync, CRC, and separate Rx and Tx 128−bytes FIFOs
- The 2.4 GHz radio front−end contains also a highly−flexible digital baseband − in terms of modulation schemes, configurability and programmability – in order to support Bluetooth Low Energy technology and proprietary protocols. It allows for programmable data rates from 62.5 kbps up to 2 Mbps, FSK with programmable pulse shape and modulation index.
- The 2.4 GHz radio front−end also includes Manchester encoding and Data whitening. The packet handling includes: ♦ Automatic preamble and sync word insertion ♦ Automatic packet length handler ♦ Basic address check ♦ Automatic CRC calculation and verification with a programmable CRC polynomial ♦ Multi−frame support
- Coexistence signals to identify the RF front−end is busy for Bluetooth or other traffic Bluetooth Low Energy RSL15 is Bluetooth 5.2 certified with the following Bluetooth LE features:
- Angle of Arrival (AoA) and Angle of Departure (AoD)
- LE Long Range (Coded PHY)
- 2 Mbit PHY (High Speed)
- LE Extended Advertising
- High Duty Cycle Non−Connectable Advertising
- LE Channel Selection Algorithm #2
- Advertising Channel Index
- GATT Caching
- HCI support for debug keys in LE Secure Connections
- Sleep clock accuracy update mechanism
- ADI field in scan response data
- Host channel classification for secondary advertising
- Periodic Advertising Sync Transfer
- Backwards compatibility and support for earlier Bluetooth Low Energy specifications including 5.1, 5.0, 4.2, 4.1 and 4.0
The power management unit is shown in Figure 3. Figure 3. Power Management Unit BUCK Mode can be used for battery voltages above 1.4 V. used to power the analog blocks (excluding the RF Blocks). between the VCC and VDC pins. and below (but can be used for the entire operating voltage). In this case a linear LDO generates a voltage VCC of 1.2 V . of the device manufacturing process. A separate supply exists for powering the flash, i.e.
- VDDC is the voltage for the internal digital blocks – excluding digital RAM and GPIOs. VDDC is trimmed by ON Semiconductor as part of the device manufacturing process
- VDDM is the voltage for the RAM blocks. VDDM is trimmed by ON Semiconductor as part of the device manufacturing process
- VDDPA is the voltage used to supply the RF power amplifier (used in RF Tx mode). The VDDPA setting depends on the output power level selected VDDO is an input to the RSL15 and constitutes the logical high level for the digital I/Os, i.e. if VDDO is connected to VBA T the GPIO signal swing will be between GND and VBA T. The RSL15 power management unit allows for operation across wide temperature and voltages ranges at low power consumption and monitors the battery voltage to ensure reliable operation. If the battery voltage dips below the Power−On Reset (POR) voltage, a POR is asserted to the system. This also prevents possible damage to RSL15 when the battery is inserted or removed.
detector, or by asserting the nRESET pin. consumption while still maintaining system responsiveness. system−level power consumption. wakeup time through disabling of internal clocks. retained) and allow for configurable wakeup sources. Table 1. POWER MODES OVERVIEW Sleep Mode The lowest power mode. Processor and RF subsystem powered down and not clocked. system before program execution begins. some digital and analog peripherals to remain active with minimal processor intervention. monitor and acquire data from external sensors at a very low system−level power consumption. powered with lower voltage and not clocked. Only selected wakeup sources are powered. available in Standby Mode. On wakeup, the program is executed directly out of retained RAM. RF subsystem and memory powered as in Run Mode but not clocked.
to use the VDDA voltage for this purpose. Table 2. POWER MODE PERIPHERAL AVAILABILITY rudimentary data processing and decision making. Available in all power modes. Sense mode, for the lowest power operation. Figure 4. ULP Data Acquisition Subsystem.
www.onsemi.com The ULP Data Acquisition Subsystem has various features to further reduce power consumption such as Burst Sampling Mode, which allows for bursts of high speed sampling followed by an adjustable delay between sampling bursts. The pulse counter can be configured to accept inputs from any of GPIO[3:0]. It counts pulses from these GPIOs during a set window ranging from 1 to 1024 clock cycles (based on a 32 kHz clock). Overall, the ULP Data Acquisition Subsystem operation can be summarized as follows: Accumulation
- An accumulation can be done with a configured number of samples ranging from 1 to 16 samples
- This mode is enabled when SUM_EN is set on Figure 4
- The accumulated value is stored in the FIFO Threshold Detection
- Two thresholds can be configured: one when the input value goes higher than the threshold, and one when the input value goes lower than the threshold
- This mode allows the system to wake up after a configured number of consecutive samples generated are greater than or lower than the configurable threshold. Acquisition
- Acquired samples are stored in the FIFO. FIFO size can be 1 to 16 samples Clocking Oscillators The following oscillators are available:
- 48 MHz crystal oscillator (RFCLK) typically used in RUN Mode when RF operation is required. Prescalers exist to provide divided clocks (including system clock) to other parts of the system
- A fast RC oscillator (RCCLK) can provide an alternative to the 48 MHz crystal oscillator. However, RF operation is not possible using the fast RC Oscillator
- A 32 kHz crystal oscillator (XTAL32K) typically used in Sleep and Standby Modes for precision timing and to maintain the real−time clock (RTC)
- A slow RC oscillator (RC32) that can be an alternative to the 32 kHz crystal oscillator for certain use cases. Clock Management Flexible clock management allows the different clock sources to be used in power−efficient ways and to minimize external components. Internal RC oscillators can be used for fast startup and then easily switched to crystal oscillators when precision timing is required. Additionally, clocks can be sourced externally with the 48 MHz and 32 kHz clock inputs. A built−in clock detector ensures a proper system reset in case the system clock goes below 2 kHz. General Purpose Input/Output (GPIO) RSL15 contains highly flexible general purpose input/output (GPIO) pins that can be configured as digital input or output, communication interfaces, clocks, wakeup sources or analog functions. Communication interfaces can be routed to any GPIO. Other functions are available on select GPIO, see section Pin Definition and Multiplexing. Each GPIO has a software configurable pull up/down resistor, debounce LPF for I2C and four drive strengths options. Analog Successive Approximation ADC (SAR ADC) The Successive Approximation ADC (SAR ADC) generates 12−bit samples up to 2 Msps sample frequency. The SAR ADC is auto calibrated during operation for optimal INL/DNL performance. Low Speed ADC Converter (LSAD) This is a combined integrating and algorithmic ADC that has a resolution varying from 8 to 14 bits depending on configuration. While converting, the input signal can be integrated across one or more clock cycles (depending on configuration). ADC sampling rate can be up to 50 ksps. This ADC converter is also used to monitor the VBAT input voltage. It can also be configured to measure single ended or differential input voltages. Pulse Counter A pulse counter can be driven by one of GPIO[3:0]. It counts pulses from these GPIOs during a set interval. Analog Comparator RSL15 contains a low −power comparator that can be active in Standby, Sleep and Smart Sense mode. It has 3 different settings to trade off response time with power consumption, Low Power, Normal and High Speed, see section Analog Comparator Specifications (ACOMP). DAC RSL15 contains a low−power DAC that can be used for sensor biasing purposes. To optimize power consumption there is also a buffer that can be disabled if the load is high impedance. Current Source A built −in current source with adjustable output from 1/C8201 /C0109A to 16 /C0109A. The current source may be applied for temperature measurements using an external thermistor connected to a GPIO.
www.onsemi.com Peripherals Timers There are 4 independent 24−bit timers that can operate as single−shot, multi−shot or free −run. An interrupt can be generated on timer expiration. Also, a GPIO interrupt can capture and store the current timer value. Watchdog The independent watchdog timer cannot be disabled. It must be reloaded at regular intervals. At the first timer expiration, an interrupt is generated and the timer is reloaded. At the second timer expiration, a reset is issued to the system. PWM The PWM (Pulse Width Modulation) controller can output on 5 independent channels with configurable period, duty cycle and offset. The PWM has 12−bit resolution with an optional 8 −bit dithering per channel for lighting applications. Additionally, one 8 −bit ACS −PWM channel fixed on GPIO[4] can be operational in low power modes. I2C The I2C controller consists of 2 independent channels of the two−wire interface including a bidirectional clock line (SCL) and bidirectional data line (SDA). The I2C interface supports both master and slave mode operation. 100 kHz, 400 kHz and 1 MHz modes are supported. SPI The SPI controller consists of 2 independent channels with the standard 4−wire interface of SCLK, MOSI, MISO and CS supporting master and slave mode. Each channel also supports dual (DSPI) and quad (QSPI) modes in half or full duplex mode. UART The general −purpose Universal Asynchronous Receiver−Transmitter (UART) uses a standard data format with one start bit, eight data bits and one stop bit. PCM The highly configurable PCM (Pulse Code Modulation) interface can be used to stream data in and out of RSL15. RTC The RTC timer consists of a 32 −bit free −running up−counter, clocked by the 32 kHz clock. Activity Counter The activity counters help to analyze how long the system has been running, and how much the CPU and the flash have been used by the application in a period of time. This is useful information to estimate and optimize the power consumption of the application. Asynchronous Clock Counter The asynchronous clock counter measure the timing of a clock signal, such as STANDBYCLK or a clock provided on a GPIO input, relative to the system clock. CRC This block provides an implementation of two standard cyclic redundancy code (CRC) algorithms (CRC −CCITT and CRC−32) which, if used, can ensure data integrity of a user application’s code and data.
Figure 5. RSL15 Memory Map
128 B + 128 B(duplicated )
Table 3. ABSOLUTE MAXIMUM RATINGS Stresses exceeding those listed in the Absolute Maximum Ratings table may damage the device.
- Storage temperature applies after soldering to PCB.
Table 4. GENERAL OPERATING CONDITIONS
48 MHz
operating conditions for extended periods may affect device reliability.
- VCC, VDDA, VDDFLASH and VDDRF Outputs are for connections to external filtering capacitors only. These regulated voltages are used
internally and are not intended for powering external devices.
- Minimum SYS_CLK required for BLE Operation.
internal supplies trimmed to factory defaults. Table 5. RF CURRENT CONSUMPTION
8 MHz system clock
1.25 V LDO Mode 6
3.0 V BUCK Mode 8 mA
48 MHz (RFCLK) active, Radio OFF and internal supplies
trimmed to factory defaults. Table 6. RUN MODE CURRENT CONSUMPTION
3.0 V BUCK Mode 49 /C0109A/MHz
1.8 V BUCK Mode 76
1.25 V LDO Mode 106
16 MHz system clock
3.0 V BUCK Mode 39 /C0109A/MHz
1.8 V BUCK Mode 58
1.25 V LDO Mode 84
24 MHz system clock
3.0 V BUCK Mode 34 /C0109A/MHz
1.8 V BUCK Mode 54
1.25 V LDO Mode 77
48 MHz system clock
3.0 V BUCK Mode 30 /C0109A/MHz
1.8 V BUCK Mode 46
1.25 V LDO Mode 65
3.0 V BUCK Mode 33 /C0109A/MHz
1.8 V BUCK Mode 50
1.25 V LDO Mode 71
3.0 V BUCK Mode 26 /C0109A/MHz
1.8 V BUCK Mode 39
1.25 V LDO Mode 55
3.0 V BUCK Mode 20 /C0109A/MHz
1.8 V BUCK Mode 31
1.25 V LDO Mode 51
3.0 V BUCK Mode 21 /C0109A/MHz
1.8 V BUCK Mode 34
1.25 V LDO Mode 50
trimmed to factory defaults. Table 7. IDLE MODE CURRENT CONSUMPTION
1.8 V BUCK Mode 103
1.25 V LDO Mode 156
internal power supplies trimmed to factory defaults. Table 8. STANDBY MODE CURRENT CONSUMPTION
1.8 V BUCK Mode 20
1.25 V LDO Mode 26
1.8 V BUCK Mode 21
3.0 V BUCK Mode 21 /C0109A
1.8 V BUCK Mode 22
1.25 V LDO Mode 29
3.0 V BUCK Mode 19 /C0109A
1.25 V LDO Mode 28
48 MHz (RFCLK) inactive, Radio OFF and internal
supplies trimmed to factory defaults. Table 9. SLEEP MODE CURRENT CONSUMPTION
1.8 V BUCK Mode 37
1.25 V LDO Mode 60
1.8 V BUCK Mode 184
1.25 V LDO Mode 299
1.8 V BUCK Mode 253
1.25 V LDO Mode 420
1.8 V BUCK Mode 407
1.25 V LDO Mode 659
1.8 V BUCK Mode 696
1.25 V LDO Mode 1135
1.8 V BUCK Mode 98
1.25 V LDO Mode 147
1.8 V BUCK Mode 66
1.25 V LDO Mode 97
1.8 V BUCK Mode 244
1.25 V LDO Mode 382
1.8 V BUCK Mode 213
1.25 V LDO Mode 335
1.8 V BUCK Mode 311
1.25 V LDO Mode 502
1.8 V BUCK Mode 283
1.25 V LDO Mode 453
1.8 V BUCK Mode 464
1.25 V LDO Mode 729
1.8 V BUCK Mode 428
1.25 V LDO Mode 681
obtain a more accurate measurement with the measurement device.
trimmed to factory defaults. Table 10. ULP DATA ACQUISITION SUBSYSTEM PERFORMANCE Table 11. WAKEUP TIMING SPECIFICATIONS in RAM (startup code is not executed).
- Wakeup times may vary due to system capacitance and sleep period.
Table 12. EEMBC BENCHMARK SCORES (All RSL15 benchmark scores have been certified by EEMBC)
3 V 1070
VBA T > 1.4 V , LDO mode for VBAT ≤ 1.4 V). Table 13. RF SPECIFICATIONS
Table 13. RF SPECIFICATIONS (continued)
- At +6 dBm Tx power, an antenna gain of +2.2 dBi or less must be used to ensure out−of−band regulatory emissions compliance.
Table 14. FLASH SPECIFICATIONS Table 15. 32 kHz CRYSTAL OSCILLATOR (XTAL32K)
Table 16. SLOW RC OSCILLATOR (RC32)
- temperature constant within ± 0.5°C
- calibrating at least every 10 seconds
- averaging window > 7.8 ms
- defined as 3 sigma 500 ppm Startup time After VBAT applied 2 ms Current consumption Temperature comp enabled 120 nA
Table 17. 48 MHz CRYSTAL OSCILLATOR (RFCLK) Table 18. FAST RC OSCILLATOR (RCCLK)
12 MHz Output 12
24 MHz Output 24
48 MHz Output 48
12 MHz Output 18 /C0109A
24 MHz Output 38 /C0109A
48 MHz Output 78 /C0109A
Table 19. ANALOG COMPARATOR SPECIFICATIONS (ACOMP) Table 20. CURRENT SOURCE (CSRC) SPECIFICATIONS
Table 21. SUCCESSIVE APPROXIMATION ADC (SAR ADC) SPECIFICATIONS Table 22. LOW SPEED ADC CONVERTER (LSAD) SPECIFICATIONS Table 23. DAC SPECIFICATIONS
Table 24. TEMPERATURE SENSOR SPECIFICATIONS Table 25. PULSE COUNTER SPECIFICATIONS
Table 26. GPIO INTERFACE SPECIFICATIONS
- For VDDO < 1.8 V, VIL Max is 0.23 x VDDO.
Table 27. RECOMMENDED EXTERNAL COMPONENTS NOTE: All capacitors used must have good RF performance.
- The recommended decoupling capacitance uses 2 capacitors with the values specified.
- Example: GRM155R61A225KE95D or GRM155R61A475MEAAD, Murata, AMK105BJ225_P, Taiyo Yuden.
- For improved harmonic performance in environments where RSL15 is operating in close proximity to smartphones or base stations, FBAR
filters such as the Broadcom ACPF− 7924 can be applied instead of the suggested discrete harmonic filter. Table 28. RECOMMENDED DC−DC CONVERTER INDUCTANCE TABLE Default inductor used on evaluation board. in Buck mode versus LDO mode operation. A low−profile, AEC−Q200 option.
Figure 8. QFN40 Pin Out
RSL15 has very flexible pad multiplexing capabilities. functions available on the GPIO. Table 29. PIN DEFINITION AND MULTIPLEXING
Table 30. GPIO MULTIPLEXING
0 RTC_CLK_OUTPUT (Note 5) RTC clock output
2 JTAG_TDO JTAG Test Data Out
3 JTAG_TDI JTAG Test Data In
4 JTAG_TRST JTAG Test Reset
4 ACS−PWM (Note 4) Always On PWM in the Analog Control Subsystem (ACS)
7 SDAC_OUTPUT SDAC output
9 SAR_ADC SUPPLY & REFERNCE SAR ADC voltage supply and reference (VREF)
- ACS −PWM has an equivalent 500 Ohm series resistor at the output.
- RTC_CLK_OUTPUT output level is at VCC in Sleep Mode.
- Decoupling capacitors should be placed as close to
- Differential output signals should be routed as
- Analog input signals should be shielded as well as
- Pay close attention to the parasitic coupling
- Special care should be made for PCB design in
- Multi−layer PCB should be used with a keep−out
- All the supply voltages should be decoupled as
- Digital signals should not be routed close to the
- Proper DC−DC component placement and layout
www.onsemi.com DC−DC mode. Minimize parasitic capacitance and inductance on the VDC node as much as possible. 10. [QFN only]: Ground EP by vias to a ground plane and/or through at least two VSS pins to PCB surface ground. 11. [QFN only]: Connect SHLD pin to EP, and connect SHLD to an external ground trace shielding XTAL48M_IN from SWCLK. PACKAGE MARKING INFORMATION Chip Identification System identification is used to identify different system components. For the RSL15 chip, the key identifier components and values are as follows: Chip Family: 0x0B Chip Version: 0x02 Chip Major Revision: 0x02 ELECTROSTATIC DISCHARGE (ESD) SENSITIVE DEVICE CAUTION:ESD sensitive device. Permanent damage may occur on devices subjected to high −energy electrostatic discharges. Proper ESD precautions in handling, packaging and testing are recommended to avoid performance degradation or loss of functionality. SOLDER INFORMATION The RSL15 QFN package is constructed with all RoHS compliant material and should be reflowed accordingly. This device is Moisture Sensitive Class MSL3 and must be stored and handled accordingly. Re−flow according to IPC/JEDEC standard J −STD−020C, Joint Industry Standard: Re −flow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. Hand soldering is not recommended for this part. For more information, see SOLDERRM/D available from http://onsemi.com EXPORT CONTROL CLASSIFICATION NUMBER (ECCN) The ECCN designation for RSL15 is 5a991.g . Arm, Cortex and TrustZone are registered trademarks and CryptoCell is a trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. ULPMark is a trademark of EEMBC in the US and/or elsewhere.
www.onsemi.com PACKAGE DIMENSIONS QFN40 5x5, 0.4P CASE 485CR ISSUE C SEATINGNOTE 4 0.15 C (A3) A b 40XL40X BOTTOM VIEW TOP VIEW SIDE VIEW D A B E 0.15 C ÉÉÉ ÉÉÉ ÉÉÉ PIN ONE LOCATION 0.10 C 0.08 C C e PLANE NOTE 3 DETAIL A L ALTERNATE TERMINAL CONSTRUCTIONS L ÉÉ ÉÉÉÉ DETAIL B MOLD CMPDEXPOSED Cu ALTERNATE CONSTRUCTION DETAIL B DETAIL A A0.10 B C 0.05 C A0.10 B C M M M SOLDERING FOOTPRINT DIMENSIONS: MILLIMETERS 3.64 5.30 5.30 0.40 0.63 0.25 40X 40X PITCH PKG OUTLINE 3.64 RECOMMENDED NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM THE TERMINAL TIP . 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM MIN MAX MILLIMETERS A 0.80 1.00 A1 −−− 0.05 A3 0.20 REF b 0.15 0.25 D 5.00 BSC D2 3.40 3.60 E 5.00 BSC 3.60E2 3.40 e 0.40 BSC L 0.30 0.50 L1 −−− 0.15 A0.10 B CM e/2 DETAIL A L2 0.12 REF onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION TECHNICAL SUPPORT North American Technical Support: Voice Mail: 1 800−282−9855 Toll Free USA/Canada Phone: 011 421 33 790 2910 LITERATURE FULFILLMENT: Email Requests to: orderlit@onsemi.com onsemi Website: www.onsemi.com Europe, Middle East and Africa Technical Support: Phone: 00421 33 790 2910 For additional information, please contact your local Sales Representative