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© Semiconductor Components Industries, LLC, 2016 May, 2018 − Rev. 3

1 Publication Order Number:

System-on-Chip (SoC) Introduction RSL10 is an ultra−low−power, highly flexible multi−protocol

2.4 GHz radio specifically designed for use in high−performance

wearable and medical applications. With its Arm ® Cortex ®−M3 Processor and LPDSP32 DSP core, RSL10 supports Bluetooth low energy technology and 2.4 GHz proprietary protocol stacks, without sacrificing power consumption. Key Features

  • Rx Sensitivity (Bluetooth Low Energy Mode, 1 Mbps): −94 dBm
  • Data Rate: 62.5 to 2000 kbps
  • Transmitting Power: −17 to +6 dBm
  • Peak Rx Current = 5.6 mA (1.25 V VBAT)
  • Peak Rx Current = 3.0 mA (3 V VBAT)
  • Peak Tx Current (0 dBm) = 8.9 mA (1.25 V VBAT)
  • Peak Tx Current (0 dBm) = 4.6 mA (3 V VBAT)
  • Bluetooth 5 Certified with LE 2M PHY Support
  • Arm Cortex−M3 Processor Clocked at up to 48 MHz
  • LPDSP32 for Audio Codec
  • Supply V oltage Range: 1.1 − 3.3 V
  • Current Consumption (1.25 V VBAT): ♦ Deep Sleep, IO Wake−up: 50 nA ♦ Deep Sleep, 8 kB RAM Retention: 300 nA ♦ Audio Streaming at 7 kHz Audio BW: 1.8 mA RX, 1.8 mA TX
  • Current Consumption (3 V VBAT): ♦ Deep Sleep, IO Wake−up: 25 nA ♦ Deep Sleep, 8 kB RAM Retention: 100 nA ♦ Audio Streaming at 7 kHz Audio BW: 0.9 mA RX, 0.9 mA TX
  • 384 kB of Flash Memory
  • Highly−integrated System−on−Chip (SoC)
  • Supports FOTA (Firmware Over−The−Air) Updates WLCSP51 CASE 567MT www.onsemi.com XXXXXX = Specific Device Code A = Assembly Location WL = Wafer Lot Y or YY = Year WW = Work Week G or /C0071= Pb−Free Package RSL10 AWLYYWWG Device Package Shipping †

ORDERING INFORMATION

NCH−RSL10− 101WC51−ABG WLCSP51 (Pb−Free) 5000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. NCH−RSL10− 101Q48−ABG QFN48 (Pb−Free) 3000 / Tape & Reel 481 QFN48 CASE 485BA (QFN48) (WLCSP51) RSL10 AWLYWW /C0071

www.onsemi.com

FEATURES

  • Arm Cortex−M3 Processor: A 32−bit core for real−time applications, specifically developed to enable high−performance low−cost platforms for a broad range of low−power applications.
  • LPDSP32: A 32−bit Dual Harvard DSP core that efficiently supports audio codecs required for wireless audio communication. Various codecs are available to customers through libraries that are included in RSL10’s development tools.
  • Radio Frequency Front−End: Based on a 2.4 GHz RF transceiver, the RFFE implements the physical layer of the Bluetooth low energy technology standard and other proprietary or custom protocols.
  • Protocol Baseband Hardware: Bluetooth 5 certified and includes support for a 2 Mbps RF link and custom protocol options. The RSL10 baseband stack is supplemented by support structures that enable implementation of ON Semiconductor and customer designed custom protocols.
  • Highly−Integrated SoC: The dual−core architecture is complemented by high−efficiency power management units, oscillators, flash and RAM memories, a DMA controller, along with a full complement of peripherals and interfaces.
  • Deep Sleep Mode: RSL10 can be put into a Deep Sleep Mode when no operations are required. Various Deep Sleep Mode configurations are available, including: ♦ “IO wake−up” configuration. The power consumption in deep sleep mode is 50 nA (1.25 V VBA T). ♦ Embedded 32 kHz oscillator running with interrupts from timer or external pin. The total current drain is 90 nA (1.25 V VBAT). ♦ As above with 8 kB RAM data retention. The total current drain is 300 nA (1.25 V VBAT). ♦ With the exception of IO wake up only configuration, the on−chip buck converter can also be enabled to reduce current consumption in Deep Sleep Mode (at higher VBAT voltages).
  • Standby Mode: Can be used to reduce the average power consumption for off−duty cycle operation, ranging typically from a few ms to a few hundreds of ms. The typical chip power consumption is 30 /C0109A in Standby Mode.
  • Multi−Protocol Support: Using the flexibility provided by LPDSP32, the Arm Cortex−M3 processor, and the RF front−end; proprietary protocols and other custom protocols are supported.
  • Flexible Supply Voltage: RSL10 integrates high− efficiency power regulators and has a VBAT range of 1.1 to 3.3 V . See Table 2. RECOMMENDED OPERA TING CONDITIONS.
  • Highly Configurable Interfaces: I2C, UART, two SPI interfaces, PCM interface, multiple GPIOs. It also supports a digital microphone interface (DMIC) and an output driver (OD).
  • The Asynchronous Sample Rate Converter (ASRC) Block and Audio Sink Clock Blocks Provides a means of synchronizing the audio sample rate between an audio source and an audio sink. The audio sink clock also provides a high accuracy mechanism to measure an input clock used for the RTC or protocol timing.
  • Flexible Clocking Scheme: RSL10 must be clocked from the XTAL/PLL of the radio front−end at 48 MHz when transmitting or receiving RF traffic. When RSL10 is not transmitting/receiving RF traffic, it can run off the 48 MHz XTAL, the internal RC oscillators, the 32 kHz oscillator, or an external clock. A low frequency RTC clock at 32 kHz can also be used in Deep Sleep Mode. It can be sourced from either the internal XTAL, the RC oscillator, or a digital input pad.
  • Diverse Memory Architecture: 76 kB of SRAM program memory and 88 kB of SRAM data memory are available. A total of 384 kB of flash is available to store the Bluetooth stack and other applications. The Arm Cortex−M3 processor can execute from SRAM and/or flash.
  • IP Protection Feature: Ensures that the customer’s flash contents cannot be copied by a third party. It prevents any core or memory from being accessed externally after the chip has booted.
  • Ultra−Low Power Consumption Application Examples: ♦ Audio Signal Streaming: IDD = 1.8 mA @ VBAT

1.25 V in Rx Mode for receiving, decoding and

sending an 7 kHz bandwidth audio signal to the SPI interface using a proprietary custom audio protocol from ON Semiconductor. ♦ Low Duty Cycle Advertising: IDD 1.1 /C0109A for advertising at all three channels at 5 second intervals @ VBAT 3 V , DCDC converter enabled.

  • RoHS Compliant Device

The block diagram of the RSL10 chip is shown in Figure 1. Figure 1. RSL10 Block Diagram Table 1. ABSOLUTE MAXIMUM RATINGS should not be assumed, damage may occur and reliability may be affected.

Table 2. RECOMMENDED OPERATING CONDITIONS the Recommended Operating Ranges limits may affect device reliability.

  1. In order to be able to use a VBAT Min of 1.1 V, the following reduced operating conditions should be observed:

the restricted operating conditions described above. Table 3. ELECTRICAL PERFORMANCE SPECIFICATIONS Unless otherwise noted, the specifications mentioned in the table below are valid at 25°C at VBAT = VDDO = 1.25 V. 7 kHz audio BW, 5.5 ms delay. 7 kHz audio BW, 37 ms delay. with interrupts from timer or external pin. 7 kHz audio BW, 5.5 ms delay. with interrupts from timer or external pin.

Table 3. ELECTRICAL PERFORMANCE SPECIFICATIONS (continued) Unless otherwise noted, the specifications mentioned in the table below are valid at 25°C at VBAT = VDDO = 1.25 V.

8.10.1 C compiler, certified

Unless otherwise noted, the specifications mentioned in the table below are valid at 25°C at VBAT = VDDO = 1.25 V.

Unless otherwise noted, the specifications mentioned in the table below are valid at 25°C at VBAT = VDDO = 1.25 V. Power in 2nd harmonic 0 dBm mode. 50 /C0087 for “Typ” value. Power in 3rd harmonic 0 dBm mode. 50 /C0087 for “Typ” value. Power in 4th harmonic 0 dBm mode. 50 /C0087 for “Typ” value.

3 MHz ON−CHIP RC OSCILLATOR

Load Capacitance No external load capacitors required.

Unless otherwise noted, the specifications mentioned in the table below are valid at 25°C at VBAT = VDDO = 1.25 V. performance may not be indicated by the Electrical Characteristics if operated under different conditions.

  1. The maximum VDDC voltage cannot exceed the VBAT input voltage or the VCC output from the buck converter.
  2. The maximum VDDM voltage cannot exceed the VBAT input voltage or the VCC output from the buck converter.
  3. The maximum VDDRF voltage cannot exceed the VBAT input voltage or the VCC output from the buck converter.
  4. The VDDRF calibrated targets are:
  5. The LDO can be used to regulate down from VBAT and generate VCC. For VBAT values higher than 1.5 V, the LDO is less efficient and it

is possible to save power by activating the DC−DC converter to generate VCC.

  1. Signal generated by RF tester.
  2. 0.5 to 1.0 dB degradation in the RX sensitivity is present on the QFN package vs WLCSP. This is attributed to the presence of the metal slug

of the QFN package which is in close proximity to on−chip inductors.

  1. All values are based on evaluation board performance at the antenna connector, including the harmonic filter loss

10.The values shown here are without RF filter. Harmonics need to be filtered with an external filter (See “RF Filter” on T able 6).

  1. These specifications have been validated with the Epson Toyocom MC – 306 crystal

Table 4. VDDM Target Trimming Voltage in Function of VDDO Voltage NOTE: These are trimming targets at room/ATE temperature 25 /C008830°C. Table 5. VDDC Target Trimming Voltage in Function of SYSCLK Frequency mode and between 0 and 85°C only. NOTE: These are trimming targets at room/ATE temperature 25 /C008830°C.

Table 6. RECOMMENDED EXTERNAL COMPONENTS: NOTE: All capacitors used must have good RF performance. 12.The recommended decoupling capacitance uses 2 capacitors with the values specified. 13.Example: AMK105BJ225_P, Taiyo Yuden. filters such as the Broadcom ACPF−7924 can be applied instead of the suggested discrete harmonic filter. Table 7. RECOMMENDED DC−DC CONVERTER INDUCTANCE TABLE (Vbat = 3.3 V) versus LDO mode operation. depending on operation mode and settings. NOTE: Values have been measured on the QFN version of the RSL10 development board.

  1. Decoupling capacitors should be placed as close to the related balls as possible.
  2. Differential output signals should be routed as symmetrically as possible.
  3. Analog input signals should be shielded as well as possible.
  4. Pay close attention to the parasitic coupling capacitors.
  5. Special care should be made for PCB design in order to obtain good RF performance.
  6. Multi−layer PCB should be used with a keep−out area on the inner layers directly below the antenna matching

circuitry in order to reduce the stray capacitances that influence RF performance.

  1. All the supply voltages should be decoupled as close as possible to their respective pin with high performance RF

lines on the PCB from the chip’s pin to the supply source.

  1. Digital signals shouldn’t be routed close to the crystal or the power supply lines.
  2. Proper DC−DC component placement and layout is critical to RX sensitivity performance in DC−DC mode.

Table 9. CHIP INTERFACE SPECIFICATIONS

Table 9. CHIP INTERFACE SPECIFICATIONS (continued) *VSS should be connected to VSSRF at the PCB level. Pull up: selectable between 10 k/C0087 and 250 k/C0087. U1 = pull up, 200 k/C0087. All digital pads have a Schmitt trigger input. All DIO pads have a programmable I2C low pass filter. All DIOs can be configured to no pull.

The architecture of the RSL10 chip is shown in Figure 4. Figure 4. RSL10 Architecture

www.onsemi.com Power Management Unit The RSL10 power management unit prevents system brown−outs in case the battery voltage dips below the specified minimum voltage required for reliable operation. It does this by: 1. Monitoring the power supply and safely shutting down the system if needed. 2. Preventing possible damage to RSL10 when the battery is inserted or removed. 3. Allowing operation across wide temperature and voltage ranges at low power consumption. RSL10 allows the use of either the DC−DC converter for a better efficiency when the battery voltage is higher than 1.4 V or the internal LDO when VBAT is lower than 1.4 V . The output of the DC−DC converter or the LDO regulator is used to supply other voltage regulator blocks of RSL10. These blocks are:

  • A programmable voltage regulator to supply the digital cores (VDDC)
  • A programmable voltage regulator to supply the memories (VDDM)
  • A charge pump supplying the analog blocks and the flash memory (VDDA)
  • A programmable voltage regulator to supply the radio front−end (VDDRF)
  • A programmable voltage regulator to supply the power amplifier of the radio (VDDPA): This regulator is used only for the +6 dBm output power case or if we want to transmit at +3 dBm output power with a battery level less than 1.4 V . The VDDPA regulator can be disabled if RSL10 doesn’t have to transmit at high power, and VDDRF only should be used. Clock and Clocking Options RSL10’s system clock (SYSCLK) can come from various sources:
  • A 48 MHz crystal oscillator, used in normal operation mode
  • An internal trimmable RC oscillator that supplies a

3 MHz – 12 MHz clock used at system startup

  • A Real Time Clock, used in stand−by mode, generated from one of: ♦ A 32 kHz RC oscillator ♦ A 32 kHz crystal oscillator ♦ An external input on one of DIO0 to DIO3
  • A JTAG clock, used in debug mode, coming from the JTCK pad
  • An external clock source, coming from the EXTCLK pad Every clock generated in the system can be disabled when they are not needed. Also, every clock has an associated configurable prescaler to minimize the power dissipated on the clock tree. A clock detector unit can be used to monitor the system clock and/or the RTC clock in sleep and standby modes. In the event the clock frequency goes below a certain threshold, the RSL10 IC will be reset. The clock detector threshold is nominally 2 kHz. This block and the reset it triggers is enabled by default, but both can be disabled. Radio Front−End RSL10 2.4 GHz radio front−end implements the physical layer for the Bluetooth low energy technology standard and other standard, proprietary, and custom protocols. It operates in the worldwide deployable 2.4 GHz ISM band (2.4000 to 2.4835 GHz) and supports:
  • Bluetooth 5 certified with LE 2M PHY support
  • ON Semiconductor’s custom audio protocol and other custom protocols The RSL10 Radio Front End includes the necessary hardware to support the following protocols:
  • The IEEE 802.15.4 standard, used as the physical layer for many standard and proprietary protocols including ZigBee and Thread
  • Proprietary protocols or proprietary audio protocols The 2.4 GHz radio front−end is based on a low−IF architecture and comprises the following building blocks:
  • High performance single−ended RF port
  • On−chip matching network with 50 ohm RF input
  • High gain, low power LNA (low noise amplifier), and mixer
  • PA (Power Amplifier) with +3 dBm output power for Bluetooth and 802.15.4 OQPSK applications, and up to +6 dBm with dedicated PA voltage supply
  • ADC converter
  • RSSI (Received Signal Strength Indication) with 60 dB nominal range with 2.4 dB steps (not considering AGC)
  • Fully integrated ultra−low power frequency synthesis with fast settling time, with direct digital modulation in transmission (pulse shape programmable)
  • 48 MHz XTAL reference (finely trimmable)
  • Fully−integrated FSK−based modem with programmable pulse shape, data rate, and modulation index
  • Digital baseband (DBB) with Link layer functionalities, including automatic packet handling with preamble & sync, CRC, and separate Rx and Tx 128−bytes FIFOs
  • Serial and parallel digital interfaces The 2.4 GHz radio front−end contains a full transceiver with the following features:
  • IEEE 802.15.4 chip encoding & decoding
  • Manchester encoding
  • Data whitening
  • Automatic preamble and sync word insertion
  • Automatic packet length handler
  • Basic address check
  • Automatic CRC calculation and verification with a programmable CRC polynomial
  • Multi−frame support
  • 2x128 byte FIFOs Baseband Controller and Software Stack The RSL10 Bluetooth baseband controller is connected to the radio front−end. It configures the physical layer of the RSL10 for use as a Bluetooth low energy technology device. It provides access and support for the Direct−Test Mode (DTM) layer for RF testing, and it implements portions of the link layer and other controller level components from the Bluetooth stack. It is dedicated to low level bitwise operations and data packet processing. RSL10 is Bluetooth 5 certified and includes LE 2 Mbps support and all optional features from earlier versions of Bluetooth low energy technology. The RSL10 device also supports custom software stacks for:
  • Custom audio protocol to support low−latency audio streaming
  • Custom audio protocol to support low−power audio streaming from a remote dongle Also, the coexistence between Bluetooth and a custom protocol is supported. For example, when streaming audio from a remote dongle, it is possible to also use the phone to control the audio device using the standard Bluetooth low energy technology protocol. The software stack, including the profiles and the application, handles the protocol functions and is executed on the Arm Cortex−M3 processor. The Bluetooth IP implementation is split among software and hardware as shown in Figure 5.

Figure 5. Bluetooth Protocol Implementation RSL10 development tools kit.

  • Find Me
  • Proximity
  • Health Thermometer
  • Heart Rate
  • Time
  • Blood Pressure
  • Glucose Monitor
  • HID over GATT (HOG)
  • Alert Notification
  • Phone Alert Status
  • Running Speed
  • Cycling Speed
  • Cycling Power
  • Location and Navigation
  • Rezence (custom protocol defined by AirFuel/C0116 Alliance to support wireless battery charging)

www.onsemi.com Arm Cortex−M3 Processor Subsystem The Arm Cortex−M3 processor subsystem includes the Arm Cortex−M3 processor, which is the master processor of the RSL10 chip. It also contains the Bluetooth baseband controller, and all interfaces and other peripherals. Arm Cortex−M3 Processor The Arm Cortex−M3 processor is a state−of−the−art 32−bit core with embedded multiplier and ALU for handling typical control functions. Software development is done in C. It features a low gate count, low interrupt latency, and low−cost debug functionality. It is primarily intended for deeply embedded applications that require low power consumption with fast interrupt response. The processor implements the Arm architecture v7−M. For power management, the processor can be placed under firmware control, into a Standby mode, in which the processor clock is disabled. The Nested Vectored Interrupt Controller (NVIC) will continue to run to enable exiting Standby mode on an interrupt. LPDSP32 LPDSP32 is a C−programmable, 32−bit DSP developed by ON Semiconductor. LPDSP32 is a high efficiency, dual Harvard DSP that supports both single (32−bit) and double precision (64−bit) arithmetic. LPDSP32’s dual MAC unit, load store architecture is specifically optimized to support audio processing tasks. The advanced architecture also provides:

  • Two 72−bit ALUs capable of doing single and double precision arithmetic and logical operations
  • Two 32−bit integer/fractional multipliers
  • Four 64−bit accumulators with 8−bit overflow (extension bits) LPDSP32 can typically support the audio codecs needed to deploy audio device communication use cases. This includes (but is not limited to) codecs to support:
  • A 16 kHz sample rate, producing a signal with a 7 kHz bandwidth (E.g.; G.722 and mSBC codec)
  • A 24 kHz sample rate, producing a signal with an 11 kHz bandwidth (E.g.: G.722, CELT codec from the OPUS standard) Communications to the Arm Cortex−M3 processor are completed via interrupts and shared memories. Software development is done in C, and the development tools are provided upon request from Synopsys. Interfaces RSL10 includes:
  • Two independent SPI interfaces that can be configured in master and slave mode
  • A fully configurable PCM interface
  • A standard general purpose I2C interface
  • A standard general purpose UART interface
  • Two PWM (Pulse Width Modulation) drivers that can generate a single bit output signal at a given frequency
  • A two−channel digital microphone (DMIC) input
  • An output driver (OD) to allow direct connection to high impedance speakers
  • SWJ−DP interface for the Arm Cortex−M3 processor
  • JTAG interface for LPDSP32 RSL10 includes 16 DIO pads (Digital Input/Output) that all can be assigned to any of the interfaces above, or used as general purpose DIOs. Peripherals RSL10 includes:
  • Four general purpose timers
  • A DMA (Direct Memory Access) controller to transfer data between peripherals and memories without any core intervention
  • A flash copier to initialize SRAM memories and that can be used with the CRC blocks to validate flash memory contents
  • An Analog to Digital converter (ADC), accessed by the Arm Cortex−M3 processor. The ADC can read 4 external values (DIO[0]−DIO[3]), AOUT, VDDC, VBA T/2 and the ADC offset value.
  • Two standard Cyclic Redundancy Code (CRC) blocks to ensure data integrity of the user application code and data
  • An Asynchronous Sample Rate Converter (ASRC) and Audio Sink Clock Counters blocks to provide a means of synchronizing the audio sample rate between the radio link and the host device
  • A Watchdog timer to detect and recover from RSL10 malfunctions.
  • Four autonomous 32−bit Activity Counters. These counters help analyze how long the system has been running and how much the Arm Cortex−M3 processor, LPDSP32, and the flash memory have been used by the application. This is useful information to estimate and optimize the power consumption of the application.
  • An IP protection system to ensure that the flash content cannot be copied by a third party. It can be used to prevent any core or memory of the RSL10 from being accessed externally after the RSL10 has booted.
  • Program memory loop caches for each processor to reduce the RSL10 power consumption. This reduces the number of flash and RAM memory accesses by caching the program words that are read in these loops. RSL10 Memory Structure Table 10 lists the memory structures attached to RSL10, and the size and width of each memory structure.

Table 10. RSL10 MEMORY STRUCTURES

  • Chip Family: 0x09
  • Chip Version: 0x01
  • Chip Revision: 0x01 Electrostatic Discharge (ESD) Sensitive Device CAUTION: ESD sensitive device. Permanent damage may occur on devices subjected to high−energy electrostatic discharges. Proper ESD precautions in handling, packaging and testing are recommended to avoid performance degradation or loss of functionality. Solder Information The RSL10 QFN package is constructed with all RoHS compliant material and should be reflowed accordingly. This device is Moisture Sensitive Class MSL3 and must be stored and handled accordingly. Re−flow according to IPC/JEDEC standard J−STD−020C, Joint Industry Standard: Re−flow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. Hand soldering is not recommended for this part. For more information, see SOLDERRM/D available from http://onsemi.com. Development Tools RSL10 is supported by a full suite of comprehensive tools including:
  • An easy−to−use development board
  • Software Development Kit (SDK) including an Oxygen Eclipse−based development environment, Bluetooth protocol stacks, sample code, libraries, and documentation Company or Product Inquiries For more information about ON Semiconductor products or services visit our Web site at http://onsemi.com. For sales or technical support, contact your local representative or authorized distributor.

www.onsemi.com PACKAGE DIMENSIONS QFN48 6x6, 0.4P CASE 485BA ISSUE A SEATINGNOTE 4 K 0.10 C (A3) A b 48X L BOTTOM VIEW DETAIL A TOP VIEW SIDE VIEW D A B E 0.10 C ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ PIN ONE LOCATION 0.10 C 0.08 C C e A0.07 BC 0.05 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM MIN MAX MILLIMETERS A 0.80 1.00 A1 0.00 0.05 A3 0.20 REF b 0.15 0.25 D 6.00 BSC D2 4.40 4.60 E 6.00 BSC 4.60E2 4.40 e 0.40 BSC L 0.30 0.50 L1 0.00 0.15 NOTE 3 PLANE DIMENSIONS: MILLIMETERS 0.25 4.66 0.40 4.66 48X 0.68 48X 6.40 6.40 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* e/2 DETAIL B DETAIL A L ALTERNATE TERMINAL CONSTRUCTIONS L ÉÉÉ ÉÉÉÉÉÉ DETAIL B MOLD CMPDEXPOSED Cu ALTERNATE CONSTRUCTION K 0.20 MIN PITCH 48X PKG OUTLINE

www.onsemi.com PACKAGE DIMENSIONS WLCSP51, 2.364x2.325 CASE 567MT ISSUE A SEATING PLANE 0.05 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. 4. PACKAGE CENTER AND FOOTPRINT CENTER ARE NOT COINCIDENT. REFER TO DIMENSION F FOR OFFSETS. DIM A MIN NOM 0.319 MILLIMETERS D 2.325 BSC E b 0.09 0.10 e 0.252 BSC 0.350 ÈÈ ÈÈ E D A B PIN A1 REFERENCE 0.03 C

0.08 C A1

A C 0.060 0.075

2.364 BSC

F 0.0198 BSC *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT*

0.05 C2X TOP VIEW

0.10 51X DIMENSIONS: MILLIMETERS 0.252 0.126 PITCH 0.252 e A0.05 BC 0.03 C 51X b 123 J H F BOTTOM VIEW 4689 1 0 1 1 D C B A L K G E e/2 e e/2 F NOTE 4 MAX A2 0.237 0.250 A3 0.022 0.025 0.12 0.381 0.090 0.263 0.028 0.0198 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries i n the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . A listing of ON Semiconductor’s product/patent ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the right s of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 RSL10/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative ON Semiconductor is licensed by the Philips Corporation to carry the I2C bus protocol. AirFuel is a trademark of Air Routing International Corporation. Bluetooth is a registered trademark of Bluetooth SIG. Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries).