RPT7050J RAKON | Alldatasheet

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PLUTO+™ ULTRA STABLE SMD TCXO | STRATUM 3 / IEEE 1588 / SYNCE Issue: B, 16 October 2024 Specifications are subject to change without notice. Copyright © 2014 to 2024 Rakon Limited. All rights reserved Page 1 of 2 RPT7050J The RPT7050J uses Rakon's new patented, Pluto+™ ASIC. The 7 x 5 mm footprint TCXO advances on the world famous Pluto™ ASIC technology by providing enhanced frequency versus temperature stability. It also delivers to the industry the lowest jitter achievable from an ultra-stable Standard Specifications Parameter Min. Typ. Max. Unit Test Condition / Description Nominal frequency (Fn) 10 – 40 MHz Standard frequencies: 10, 12.8, 16.384, 19.44, 20, 20.48, 24.576, 25, 30.72, 38.88 and 40MHz Operating temperature range -55 105 °C Holdover stability, variable temperature ±100 – ±280 ppb The default reference for holdover stability, variable temperature is (Fmax + Fmin)/2 Holdover stability, constant temperature ±10 – ±40 ppb ±10ppb after 10 days of continuous operation, ±40ppb after 48 hours of continuous operation Slope over temperature (ΔF/ΔT) ±20 – ±100 ppb/°C Free-run accuracy ±4.6 ppm Inclusive of calibration tolerance at 25°C, temperature, supply voltage variation ±5%, load variation ±5pF, reflow soldering and 20 years ageing reference to the nominal frequency Wander generation TDEV / MTIE TDEV compliant with GR-1244 fig 5-4, G.812 types II & III fig 2, G.813, G.8262 MTIE compliant with GR-1244 Fig 5-5, G.812 types II & III fig 1, G.813, G.8262 Supply voltage stability ±0.025 ppm ±5% variation, reference to frequency at nominal supply voltage Acceleration stability < 2 ppb/g Gamma vector, 3 axes, 30 – 1500Hz Start-up time 5 – 15 ms 90% amplitude Root Allan Variance 5 10-11 tau = 1.0s Supply voltage, VCC 3.3 V ±5% Supply current 3 6 mA Depending on the nominal frequency Oscillator output – HCMOS Output voltage level high (VOH) Output voltage level low (VOL) Duty cycle Rise & fall time Load 0.9VCC 0.1V CC V V ns pF LVCMOS & LVTTL compatible as per JESD8C At 50% level Between 10% and 90% Tri-state control Input level low (pin 6) Input level high (pin 6) 0.6VCC 0.2VCC V V Device disabled, output in high impedance state Device enabled and operating Features Applications 7.0 x 5.0 x 1.5 mm  Best-in-class frequency versus temperature  RMS phase jitter down to 0.13ps  Phase noise <-160dBc/Hz floor  Excellent holdover stability  Stratum 3 / IEEE 1588 / SyncE  SONET / SDH / WDM / OTN  Carrier Ethernet / Microwave  Backhaul / Transport Equipment

PLUTO+™ ULTRA STABLE SMD TCXO | STRATUM 3 / IEEE 1588 / SYNCE Issue: B, 16 October 2024 Specifications are subject to change without notice. Copyright © 2014 to 2024 Rakon Limited. All rights reserved Page 2 of 2 SSB Phase Noise (Typical value at 25°C) Model Outline and Recommended Pad Layout Test Circuit RMS Jitter = 290 fs (12 kHz ~ 5 MHz) RMS Jitter = 190 fs (12 kHz ~ 5 MHz)