RPC564L60L5BFQR

RPC56EL60L5 STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1 Introduction
• 1.1 Document overview
• 1.2 Description
• 1.3 Device comparison
• 1.4 Block diagram
• 1.5 Feature details
• 1.5.1 High-performance e200z4d core
• 1.5.2 Crossbar switch (XBAR)
• 1.5.3 Memory Protection Unit (MPU)
• 1.5.4 Enhanced Direct Memory Access (eDMA)
• 1.5.5 On-chip flash memory with ECC
• 1.5.6 On-chip SRAM with ECC
• 1.5.7 Platform flash memory controller
• 1.5.8 Platform Static RAM Controller (SRAMC)
• 1.5.9 Memory subsystem access time
• 1.5.10 Error Correction Status Module (ECSM)
• 1.5.11 Peripheral bridge (PBRIDGE)
• 1.5.12 Interrupt Controller (I NTC)
• 1.5.13 System clocks and clock generation
• 1.5.14 Frequency-Modulated Phase-Locked Loop (FMPLL)
• 1.5.15 Main oscillator
• 1.5.16 Internal Reference Clock ( RC) oscillator
• 1.5.17 Clock, reset, power, mode and test control modules (MC_CGM,
• 1.5.18 Periodic Interrupt Timer Mo dule (PIT)
• 1.5.19 System Timer Module (STM)
• 1.5.20 Software Watchdog Timer (SWT)
• 1.5.21 Fault Collection and Control Unit (FCCU)
• 1.5.22 System Integration Unit Lite (SIUL)
• 1.5.23 Non-Maskable Interrupt (NMI)
• 1.5.24 Boot Assist Module (BAM)
• 1.5.25 System Status and Configuration Module (SSCM)
• 1.5.26 FlexCAN
• 1.5.27 FlexRay

Datasheet sections

• 3.13 FMPLL electrical characteristics
• 3.15 ADC electrical characteristics
• 3.15.1 Input Impedance and ADC Accuracy
• 3.16 Flash memory electrical characteristics
• 3.17 SWG electrical characteristics
• 3.18 AC specifications
• 3.18.1 Pad AC specifications
• 3.19 Reset sequence
• 3.19.1 Reset sequence duration
• 3.19.2 Reset sequence description
• 3.19.3 Reset sequence trigger mapping
• 3.19.4 Reset sequence — start condition
• 3.19.5 External watchdog window
• 3.20 AC timing characteristics
• 3.20.1 RESET pin characteristics
• 3.20.2 WKUP/NMI timing
• 3.20.4 Nexus timing
• 3.20.5 External interrupt timing (I RQ pin)
• 3.20.6 DSPI timing
• 4 Package characteristics
• 4.1 ECOPACK®
• 4.2 Package mechanical data
• 5 Ordering information
• 6 Revision history

Features

 High-performance e200z4d dual core  32-bit Power Architecture® technology CPU  Core frequency as high as 120 MHz  Dual issue five-stage pipeline core  Variable Length Encoding (VLE)  Memory Management Unit (MMU)  4 KB instruction cache with error detection code  Signal processing engine (SPE)  Memory available – 1 MB flash memory with ECC – 128 KB on-chip SRAM with ECC – Built-in RWW capabilities for EEPROM emulation  SIL3/ASILD innovative safety concept: LockStep mode and Fail-safe protection – Sphere of replication (SoR) for key components (such as CPU core, eDMA, crossbar switch) – FCCU, interrupt controller – Redundancy control and checker unit (RCCU) on outputs of the SoR connected to FCCU – Boot-time Built-In Self-Test for Memory (MBIST) and Logic (LBIST) triggered by hardware – Boot-time Built-In Self-Test for ADC and flash memory triggered by software – Replicated safety enhanced watchdog – Replicated junction temperature sensor – Non-maskable interrupt (NMI) – 16-region memory protection unit (MPU) – Clock monitoring units (CMU) – Power management unit (PMU) – Cyclic redundancy check (CRC) unit  Decoupled Parallel mode for high-performance use of replicated cores  Nexus Class 3+ interface  GPIOs individually programmable as input, output or special function  Three 6-channel general-purpose eTimer units  2 FlexPWM units: 4 16-bit channels per module  Communications interfaces – 2 LINFlexD channels – 3 DSPI channels – 2 FlexCAN interfac es (2.0B Active) – FlexRay module (V2.1 Rev. A)  Two 12-bit analog-to-digital converters (ADCs) – 16 input channels – Programmable CTU to synchronize ADCs conversion with timer and PWM  Sine wave generator (D/A with low pass filter)  Single 3.0 V to 3.6 V voltage supply  Ambient temperature range –40 °C to 125 °C  Junction temperature range –40 °C to 150 °C  Aerospace and Defense features – Dedicated traceabilit y and part marking – Production parts approval documents available – Adapted Extended life time and obsolescence management – Extended Product Change Notification process – Designed and manufactured to meet sub ppm quality goals – Advanced mold and frame designs for Superior resilience to harsh environment (acceleration, EMI, thermal, humidity) – Single Fabrication, Assembly and Test site – Dual internal producti on source capability LQFP144 (20 x 20 x 1.4 mm)

1 Introduction

1.1 Document overview

This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the devices. This document provides electrical specifications, pin assignments, and package diagrams for the RPC56EL60L5 series of microcontroller units (MCUs). Microcontroller Reference Manual and Safety Application Guide are available on request.

1.2 Description

The RPC56EL60L5 series microcontrollers are system-on-chip devices that are built on Power Architecture technology and contain enhancements that improve the architecture’s fit in embedded applications, include additional instruction support for digital signal processing (DSP) and integrate technologies such as an enhanced time processor unit, enhanced queued analog-to-digital converter, Controller Area Network, and an enhanced modular input-output system. The RPC56EL60L5 family of 32-bit microcontrollers is designed to address electrical hydraulic power steering (EHPS), electric power steering (EPS) and airbag applications. The advanced and cost-efficient host processor core of the RPC56EL60L5 controller family complies with the Power Architecture embedded category. It operates at speeds as high as 120 MHz and offers high-performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users’ implementations.

1.3 Device comparison

Table 1. RPC56EL60L5 device summary

3.3 V with integrated bypassable ballast

1. The third eTimer (eTimer_2) is avail able with external I/O access only in the BGA package, on the LQFP package eTimer_2

is available internally only without any external I/O access.

1. The second FlexPWM module is av ailable only in the BGA package.
2. LBGA257 available only as development package.

Table 1. RPC56EL60L5 device summary (continued)

1.4 Block diagram

Figure 1 shows a top-level block diagram of the RPC56EL60L5 device. Figure 1. RPC56EL60L5 block diagram

 High-performance e200z4d dual core – 32-bit Power Architecture ® technology CPU – Core frequency as high as 120 MHz – Dual issue five-stage pipeline core – Variable Length Encoding (VLE) – Memory Management Unit (MMU) – 4 KB instruction cache with error detection code – Signal processing engine (SPE)  Memory available – 1 MB flash memory with ECC – 128 KB on-chip SRAM with ECC – Built-in RWW capabilitie s for EEPROM emulation  SIL3/ASILD innovative safety concept: LockStep mode and Fail-safe protection – Sphere of replication (SoR) for key components (such as CPU core, eDMA, crossbar switch) – Fault collection and control unit (FCCU) – Redundancy control and checker unit (RCCU) on outputs of the SoR connected to FCCU – Boot-time Built-In Self-Test for Memory (MBIST) and Logic (LBIST) triggered by hardware – Boot-time Built-In Self-Test for ADC and flash memory triggered by software – Replicated safety enhanced watchdog – Replicated junction temperature sensor – Non-maskable interrupt (NMI) – 16-region memory protection unit (MPU) – Clock monitoring units (CMU) – Power management unit (PMU) – Cyclic redundancy check (CRC) unit  Decoupled Parallel mode for high-performance use of replicated cores  Nexus Class 3+ interface  Interrupts – Replicated 16-priority controller – Replicated 16-channel eDMA controller  GPIOs individually programmable as input, output or special function  Three 6-channel general-purpose eTimer units  2 FlexPWM units – Four 16-bit channels per module  Communications interfaces – 2 LINFlexD channels – 3 DSPI channels with automatic chip select generation – 2 FlexCAN interfaces (2.0B Active) with 32 message objects

– FlexRay module (V2.1 Rev. A) with 2 channels, 64 message buffers and data rates up to 10 Mbit/s  Two 12-bit analog-to-digital converters (ADCs) – 16 input channels – Programmable cross triggering unit (CTU) to synchronize ADCs conversion with timer and PWM  Sine wave generator (D/A with low pass filter)  On-chip CAN/UART bootstrap loader  Single 3.0 V to 3.6 V voltage supply  Ambient temperature range –40 °C to 125 °C  Junction temperature range –40 °C to 150 °C

1.5 Feature details

1.5.1 High-performance e200z4d core

The e200z4d Power Architecture® core provides the following features:  2 independent execution units, both supporting fixed-point and floating-point operations  Dual issue 32-bit Power Architecture technology compliant – 5-stage pipeline (IF, DEC, EX1, EX2, WB) – In-order execution and instruction retirement  Full support for Power Architecture instruction set and Variable Length Encoding (VLE) – Mix of classic 32-bit and 16-bit instruction allowed – Optimization of code size possible  Thirty-two 64-bit general purpose registers (GPRs)  Harvard bus (32-bit address, 64-bit data) – I-Bus interface capable of one outstanding transaction plus one piped with no wait- on-data return – D-Bus interface capable of two transa ctions outstanding to fill AHB pipe  I-cache and I-cache controller – 4 KB, 256-bit cache line (programmable for 2- or 4-way)  No data cache  16-entry MMU  8-entry branch table buffer  Branch look-ahead instruction buffer to accelerate branching  Dedicated branch address calculator  3 cycles worst case for missed branch  Load/store unit – Fully pipelined – Single-cycle load latency – Big- and little-endian modes supported – Misaligned access support – Single stall cycle on load to use  Single-cycle throughput (2-cycle latency) integer 32 × 32 multiplication  4 – 14 cycles integer 32 × 32 division (average division on various benchmark of nine cycles)  Single precision floating-point unit – 1 cycle throughput (2-cycle latency) floating-point 32 × 32 multiplication – Target 9 cycles (worst case acceptable is 12 cycles) throughput floating-point 32 × 32 division – Special square root and min/max function implemented  Signal processing support: APU-SPE 1.1 – Support for vectorized mode: as many as two floating-point instructions per clock  Vectored interrupt support  Reservation instruction to support read-modify-write constructs

 Extensive system development and tracing support via Nexus debug port

1.5.2 Crossbar switch (XBAR)

The XBAR multi-port crossbar switch supports simultaneous connections between four master ports and three slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width. The crossbar allows four concurrent transactions to occur from any master port to any slave port, although one of those transfers must be an instruction fetch from internal flash memory. If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher priority master and grants it ownership of the slave port. All other masters requesting that slave port are stalled until the higher priority master completes its transactions. The crossbar provides the following features:  4 masters and 3 slaves supported per each replicated crossbar – Masters allocation for each crossbar: e200z4d core with two independent bus interface units (BIU) for I and D access (2 masters), one eDMA, one FlexRay – Slaves allocation for each crossbar: a redundant flash-memory controller with 2 slave ports to guarantee maximum flexibility to handle Instruction and Data array, one redundant SRAM controller with 1 slave port each and 1 redundant peripheral bus bridge  32-bit address bus and 64-bit data bus  Programmable arbitration priority – Requesting masters can be treated with equal priority and are granted access to a slave port in round-robin method, based upon the ID of the last master to be granted access or a priority order can be assigned by software at application run time  Temporary dynamic priority elevation of masters The XBAR is replicated for each processing channel.

1.5.3 Memory Protection Unit (MPU)

The Memory Protection Unit splits the physical memory into 16 different regions. Each master (eDMA, FlexRay, CPU) can be assigned different access rights to each region.  16-region MPU with concurrent checks against each master access  32-byte granularity for protected address region The memory protection unit is replicated for each processing channel.

1.5.4 Enhanced Direct Memory Access (eDMA)

The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data movements via 16 programmable channels, with minimal intervention from the host processor. The hardware microarchitecture includes a DMA engine which performs source and destination address calculations, and the actual data movement operations, along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation is used to minimize the overall block size.

The eDMA module provides the following features:  16 channels supporting 8-, 16-, and 32-bit value single or block transfers  Support variable sized queues and circular buffered queue  Source and destination address registers independently configured to post-increment or stay constant  Support major and minor loop offset  Support minor and major loop done signals  DMA task initiated either by hardware requestor or by software  Each DMA task can optionally generate an interrupt at completion and retirement of the task  Signal to indicate closure of last minor loop  Transfer control descriptors mapped inside the SRAM The eDMA controller is replicated for each processing channel.

1.5.5 On-chip flash memory with ECC

This device includes programmable, non-volatile flash memory. The non-volatile memory (NVM) can be used for instruction storage or data storage, or both. The flash memory module interfaces with the system bus through a dedicated flash memory array controller. It supports a 64-bit data bus width at the system bus port, and a 128-bit read data interface to flash memory. The module contains four 128-bit prefetch buffers. Prefetch buffer hits allow no-wait responses. Buffer misses incur a 3 wait state response at 120 MHz. The flash memory module provides the following features  1 MB of flash memory in unique multi-partitioned hard macro  Sectorization: 16 KB + 2 × 48 KB + 16 KB + 2 × 64 KB + 2 × 128 KB + 2 × 256 KB  EEPROM emulation (in software) within same module but on different partition  16 KB test sector and 16 KB shadow block for test, censorship device and user option bits  Wait states: – 3 wait states for frequencies =< 120 MHz – 2 wait states for frequencies =< 80 MHz – 1 wait state for frequencies =< 60 MHz  Flash memory line 128-bit wide with 8-bit ECC on 64-bit word (total 144 bits)  Accessed via a 64-bit wide bus for write and a 128-bit wide array for read operations  1-bit error correction, 2-bit error detection

1.5.6 On-chip SRAM with ECC

The RPC56EL60L5 SRAM provides a general-purpose single port memory. ECC handling is done on a 32-bit boundary for data and it is extended to the address to have the highest possible diagnostic coverage including the array internal address decoder.

The SRAM module provides the following features:  System SRAM: 128 KB  ECC on 32-bit word (syndrome of 7 bits) – ECC covers SRAM bus address  1-bit error correction, 2-bit error detection  Wait states: – 1 wait state for frequencies =< 120 MHz – 0 wait states for frequencies =< 80 MHz

1.5.7 Platform flash memory controller

The following list summarizes the key features of the flash memory controller:  Single AHB port interface supports a 64-bit data bus. All AHB aligned and unaligned reads within the 32-bit container are supported. Only aligned word writes are supported.  Array interfaces support a 128-bit read data bus and a 64-bit write data bus for each bank.  Code flash (bank0) interface provides configurable read buffering and page prefetch support. – Four page-read buffers (each 128 bits wide) and a prefetch controller support speculative reading and optimized flash access.  Single-cycle read responses (0 AHB data-phase wait states) for hits in the buffers. The buffers implement a least-recently-used replacement algorithm to maximize performance.  Programmable response for read-while-write sequences including support for stall- while-write, optional stall notification interrupt, optional flash operation abort , and optional abort notification interrupt.  Separate and independent configurable access timing (on a per bank basis) to support use across a wide range of platforms and frequencies.  Support of address-based read access timing for emulation of other memory types.  Support for reporting of single- and multi-bit error events.  Typical operating configuration loaded into programming model by system reset. The platform flash controller is replicated for each processor.

1.5.8 Platform Static RAM Controller (SRAMC)

The SRAMC module is the platform SRAM array controller, with integrated error detection and correction. The main features of the SRAMC provide connectivity for the following interfaces:  XBAR Slave Port (64-bit data path)  ECSM (ECC Error Reporting, error injection and configuration)  SRAM array

The platform SRAM controller is replicated for each processor.

1.5.9 Memory subsystem access time

accessed is not parked on the requesting master in the crossbar.

1.5.10 Error Correction Status Module (ECSM)

Table 2. Platform memory access time summary

1.5.11 Peripheral bridge (PBRIDGE)

The PBRIDGE implements the following features:  Duplicated periphery  Master access privilege level per peripheral (per master: read access enable; write access enable)  Checker applied on PBRIDGE output toward periphery  Byte endianess swap capability

1.5.12 Interrupt Controller (INTC)

The INTC provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time systems. For high-priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of interrupt request, the priority of each interrupt request is software configurable. The INTC supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource can not preempt each other. The INTC provides the following features:  Duplicated periphery  Unique 9-bit vector per interrupt source  16 priority levels with fixed hardware arbitration within priority levels for each interrupt source  Priority elevation for shared resource The INTC is replicated for each processor.

1.5.13 System clocks and clock generation

The following list summarizes the system clock and clock generation on this device:  Lock status continuously monitored by lock detect circuitry  Loss-of-clock (LOC) detection for reference and feedback clocks  On-chip loop filter (for improved electromagnetic interference performance and fewer external components required)  Programmable output clock divider of system clock (1, 2, 4, 8)  FlexPWM module and as many as three eTimer modules running on an auxiliary clock independent from system clock (with max frequency 120 MHz)  On-chip crystal oscillator with automatic level control  Dedicated internal 16 MHz internal RC oscillator for rapid start-up – Supports automated frequency trimming by hardware during device startup and by user application  Auxiliary clock domain for motor control periphery (FlexPWM, eTimer, CTU, ADC, and SWG)

1.5.14 Frequency-Modulated Phase-Locked Loop (FMPLL)

Each device has two FMPLLs. Each FMPLL allows the user to generate high speed system clocks starting from a minimum reference of 4 MHz input clock. Further, the FMPLL supports programmable frequency modulation of the system clock. The FMPLL multiplication factor, output clock divider ratio are all software configurable. The FMPLLs have the following major features:  Input frequency: 4–40 MHz continuous range (limited by the crystal oscillator)  Voltage controlled oscillator (VCO) range: 256–512 MHz  Frequency modulation via software control to reduce and control emission peaks – Modulation depth ±2% if centered or 0% to –4% if downshifted via software control register – Modulation frequency: triangular modulation with 25 kHz nominal rate  Option to switch modulation on and off via software interface  Output divider (ODF) for reduced frequency operation without re-lock  3 modes of operation – Bypass mode – Normal FMPLL mode with crystal reference (default) – Normal FMPLL mode with external reference  Lock monitor circuitry with lock status  Loss-of-lock detection for reference and feedback clocks  Self-clocked mode (SCM) operation  On-chip loop filter  Auxiliary FMPLL – Used for FlexRay due to precise sym bol rate requirement by the protocol – Used for motor control periphery and connected IP (A/D digital interface CTU) to allow independent frequencies of operation for PWM and timers and jitter-free control – Option to enable/disable mo dulation to avoid protocol violation on jitter and/or potential unadjusted error in electric motor control loop – Allows to run motor control periphery at different (precisely lower, equal or higher as required) frequency than the system to ensure higher resolution

1.5.15 Main oscillator

The main oscillator provides these features:  Input frequency range 4–40 MHz  Crystal input mode  External reference clock (3.3 V) input mode  FMPLL reference

1.5.16 Internal Referen ce Clock (RC) oscillator

The architecture uses constant current charging of a capacitor. The voltage at the capacitor is compared to the stable bandgap reference voltage. The RC oscillator is the device safe clock.

The RC oscillator provides these features:  Nominal frequency 16 MHz  ±5% variation over voltage and temperature after process trim  Clock output of the RC oscillator serves as system clock source in case loss of lock or loss of clock is detected by the FMPLL  RC oscillator is used as the default system clock during startup and can be used as back-up input source of FMPLL(s) in case XOSC fails

1.5.17 Clock, reset, pow er, mode and test control modules (MC_CGM,

MC_RGM, MC_PCU, and MC_ME) These modules provide the following:  Clock gating and clock distribution control  Halt, stop mode control  Flexible configurable system and auxiliary clock dividers  Various execution modes – HALT and STOP mode as reduced activity low power mode – Reset, Idle, Test, Safe – Various RUN modes with software selectable powered modules – No stand-by mode implemented (no internal switchable power domains)

1.5.18 Periodic Interrupt Timer Module (PIT)

The PIT module implements the following features:  4 general purpose interrupt timers  32-bit counter resolution  Can be used for software tick or DMA trigger operation

1.5.19 System Timer Module (STM)

The STM implements the following features:  Up-counter with 4 output compare registers  OS task protection and hardware tick implementation per AUTOSAR(a) requirement The STM is replicated for each processor.

1.5.20 Software Watchdog Timer (SWT)

This module implements the following features:  Fault tolerant output  Safe internal RC oscillator as reference clock  Windowed watchdog  Program flow control monitor with 16-bit pseudorandom key generation  Allows a high level of safety (SIL3 monitor) a. Automotive Open System Architecture

The SWT module is replicated for each processor.

1.5.21 Fault Collection and Control Unit (FCCU)

The FCCU module has the following features:  Redundant collection of hardware checker results  Redundant collection of error information and latch of faults from critical modules on the device  Collection of self-test results  Configurable and graded fault control – Internal reactions (no internal reaction, IRQ, Functional Reset, Destructive Reset, or Safe mode entered) – External reaction (failure is reported to the external/surrounding system via configurable output pins)

1.5.22 System Integrat ion Unit Lite (SIUL)

The SIUL controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO), internal peripheral multiplexing, and system reset operation. The reset configuration block contains the external pin boot configuration logic. The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU. The SIU provides the following features:  Centralized pad control on a per-pin basis – Pin function selection – Configurable weak pull-up/down – Configurable slew rate control (slow/medium/fast) – Hysteresis on GPIO pins – Configurable automatic safe mode pad control  Input filtering for external interrupts

1.5.23 Non-Maskable Interrupt (NMI)

The non-maskable interrupt with de-glitching filter supports high-priority core exceptions.

1.5.24 Boot Assist Module (BAM)

The BAM is a block of read-only memory with hard-coded content. The BAM program is executed only if serial booting mode is selected via boot configuration pins. The BAM provides the following features:  Enables booting via serial mode (FlexCAN or LINFlex-UART)  Supports programmable 64-bit password protection for serial boot mode  Supports serial bootloading of either Power Architecture code (default) or VLE code  Automatic switch to serial boot mode if internal flash memory is blank or invalid

1.5.25 System Status and Configuration Module (SSCM)

The SSCM on this device features the following:  System configuration and status  Debug port status and debug port enable  Multiple boot code starting locations out of reset through implementation of search for valid Reset Configuration Half Word  Sets up the MMU to allow user boot code to execute as either Power Architecture code (default) or as VLE code out of flash memory  Triggering of device self-tests during reset phase of device boot

1.5.26 FlexCAN

The FlexCAN module is a communication controller implementing the CAN protocol according to Bosch Specification version 2.0B. The CAN protocol was designed to be used primarily as a vehicle serial data bus, meeting the specific requirements of this field: real- time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness and required bandwidth. The FlexCAN module provides the following features:  Full implementation of the CAN protocol specification, version 2.0B – Standard data and remote frames – Extended data and remote frames – 0 to 8 bytes data length – Programmable bit rate as fast as 1Mbit/s  32 message buffers of 0 to 8 bytes data length  Each message buffer configurable as receive or transmit buffer, all supporting standard and extended messages  Programmable loop-back mode supporting self-test operation  3 programmable mask registers  Programmable transmit-first scheme: lowest ID or lowest buffer number  Time stamp based on 16-bit free-running timer  Global network time, synchronized by a specific message  Maskable interrupts  Independent of the transmission medium (an external transceiver is assumed)  High immunity to EMI  Short latency time due to an arbitration scheme for high-priority messages  Transmit features – Supports configuration of multiple mailboxes to form message queues of scalable depth – Arbitration scheme according to mess age ID or message buffer number – Internal arbitration to guarantee no inner or outer priority inversion – Transmit abort procedure and notification

 Receive features – Individual programmable filters for each mailbox – 8 mailboxes configurable as a 6-entry receive FIFO – 8 programmable acceptance filters for receive FIFO  Programmable clock source – System clock – Direct oscillator clock to avoid FMPLL jitter

1.5.27 FlexRay

The FlexRay module provides the following features:  Full implementation of FlexRay Protocol Specification 2.1 Rev. A  64 configurable message buffers can be handled  Dual channel or single channel mode of operation, each as fast as 10 Mbit/s data rate  Message buffers configurable as transmit or receive  Message buffer size configurable  Message filtering for all message buffers based on Frame ID, cycle count, and message ID  Programmable acceptance filters for receive FIFO  Message buffer header, status, and payload data stored in system memory (SRAM)  Internal FlexRay memories have error detection and correction

1.5.28 Serial communication interface module (LINFlexD)

The LINFlexD module (LINFlex with DMA support) on this device features the following:  Supports LIN Master mode, LIN Slave mode and UART mode  LIN state machine compliant to LIN1.3, 2.0, and 2.1 specifications  Manages LIN frame transmission and reception without CPU intervention  LIN features – Autonomous LIN frame handling – Message buffer to store as many as 8 data bytes – Supports messages as long as 64 bytes – Detection and flagging of LIN errors (Sync field, delimiter, ID parity, bit framing, checksum and Time-out errors) – Classic or extended checksum calculation – Configurable break duration of up to 50-bit times – Programmable baud rate prescalers (13-bit mantissa, 4-bit fractional) – Diagnostic features (Loop back, LIN bus stuck dominant detection) – Interrupt driven operation with 16 interrupt sources  LIN slave mode features – Autonomous LIN header handling – Autonomous LIN response handling  UART mode – Full-duplex operation – Standard non return-to-zero (NRZ) mark/space format – Data buffers with 4-byte receive, 4-byte transmit – Configurable word length (8-bit, 9-bit, 16-bit, or 17-bit words) – Configurable parity scheme: none, odd, even, always 0 – Speed as fast as 2 Mbit/s – Error detection and flagging (Parity, Noise and Framing errors) – Interrupt driven operation with four interrupt sources – Separate transmitter and receiver CPU interrupt sources – 16-bit programmable baud-rate modulus counter and 16-bit fractional – Two receiver wake-up methods  Support for DMA enabled transfers

1.5.29 Deserial Serial Peripheral Interface (DSPI)

The DSPI modules provide a synchronous serial interface for communication between the RPC56EL60L5 and external devices. A DSPI module provides these features:  Full duplex, synchronous transfers  Master or slave operation  Programmable master bit rates  Programmable clock polarity and phase

 End-of-transmission interrupt flag  Programmable transfer baud rate  Programmable data frames from 4 to 16 bits  As many as 8 chip select lines available, depending on package and pin multiplexing  4 clock and transfer attributes registers  Chip select strobe available as alternate function on one of the chip select pins for de- glitching  FIFOs for buffering as many as 5 transfers on the transmit and receive side  Queueing operation possible through use of the eDMA  General purpose I/O functionality on pins when not used for SPI

1.5.30 FlexPWM

The pulse width modulator module (FlexPWM) contains four PWM channels, each of which is configured to control a single half-bridge power stage. Two modules are included on LFBGA257 devices; on the LQFP144 package, only one module is present. Additionally, four fault input channels are provided per FlexPWM module. This PWM is capable of controlling most motor types, including:  AC induction motors (ACIM)  Permanent Magnet AC motors (PMAC)  Brushless (BLDC) and brush DC motors (BDC)  Switched (SRM) and variable reluctance motors (VRM)  Stepper motors A FlexPWM module implements the following features:  16 bits of resolution for center, edge aligned, and asymmetrical PWMs  Maximum operating frequency as high as 120 MHz – Clock source not modulated and independe nt from system clock (generated via secondary FMPLL)  Fine granularity control for enhanced resolution of the PWM period  PWM outputs can operate as complementary pairs or independent channels  Ability to accept signed numbers for PWM generation  Independent control of both edges of each PWM output  Synchronization to external hardware or other PWM supported  Double buffered PWM registers – Integral reload rates from 1 to 16 – Half cycle reload capability  Multiple ADC trigger events can be generated per PWM cycle via hardware  Fault inputs can be assigned to control multiple PWM outputs  Programmable filters for fault inputs  Independently programmable PWM output polarity  Independent top and bottom deadtime insertion  Each complementary pair can operate with its own PWM frequency and deadtime values

 Individual software control for each PWM output  All outputs can be forced to a value simultaneously  PWMX pin can optionally output a third signal from each channel  Channels not used for PWM generation can be used for buffered output compare functions  Channels not used for PWM generation can be used for input capture functions  Enhanced dual edge capture functionality  Option to supply the source for each complementary PWM signal pair from any of the following: – External digital pin – Internal timer channel – External ADC input, taking into account values set in ADC high- and low-limit registers  DMA support 1.5.31 eTimer module The MPC5643L provides three eTimer modules (on the LQFP package eTimer_2 is available internally only without any external I/O access). Six 16-bit general purpose up/down timer/counters per module are implemented with the following features:  Maximum clock frequency of 120 MHz  Individual channel capability – Input capture trigger – Output compare – Double buffer (to capture rising edge and falling edge) – Separate prescaler for each counter – Selectable clock source – 0–100% pulse measurement – Rotation direction flag (Quad decoder mode)  Maximum count rate – Equals peripheral clock divided by 2 for external event counting – Equals peripheral clock for internal clock counting  Cascadeable counters  Programmable count modulo  Quadrature decode capabilities  Counters can share available input pins  Count once or repeatedly  Preloadable counters  Pins available as GPIO when timer functionality not in use  DMA support

1.5.32 Sine Wave Generator (SWG)

A digital-to-analog converter is available to generate a sine wave based on 32 stored values for external devices (ex: resolver).

1.5.33 Analog-to-Digital Converter module (ADC)

The ADC module features include: Analog part:  2 on-chip ADCs – 12-bit resolution SAR architecture – Same digital interface as in the SPC560P family – A/D Channels: 9 external, 3 internal and 4 shared with other A/D (total 16 channels) – One channel dedicated to each T-sensor to enable temperature reading during application – Separated reference for each ADC – Shared analog supply voltage for both ADCs – One sample and hold unit per ADC – Adjustable sampling and conversion time Digital part:  4 analog watchdogs comparing ADC results against predefined levels (low, high, range) before results are stored in the appropriate ADC result location  2 modes of operation: CPU Mode or CTU Mode  CPU mode features – Register based interface with the CP U: one result register per channel – ADC state machine managing three request flows: regular command, hardware injected command, software injected command – Selectable priority between software and hardware injected commands – 4 analog watchdogs comparing ADC results against predefined levels (low, high, range) –D M A c o m p a t i ble interface  CTU mode features – Triggered mode only – 4 independent result queues (1 16 entries, 28 entries, 14 entries) – Result alignment circuitry (left justified; right justified) – 32-bit read mode allows to have channel ID on one of the 16-bit parts –D M A c o m p a t i ble interfaces  Built-in self-test features triggered by software

1.5.34 Cross Triggering Unit (CTU)

The ADC cross triggering unit allows automatic generation of ADC conversion requests on user selected conditions without CPU load during the PWM period and with minimized CPU load for dynamic configuration.

The CTU implements the following features:  Cross triggering between ADC, FlexPWM, eTimer, and external pins  Double buffered trigger generation unit with as many as 8 independent triggers generated from external triggers  Maximum operating frequency less than or equal to 120 MHz  Trigger generation unit configurable in sequential mode or in triggered mode  Trigger delay unit to compensate the delay of external low pass filter  Double buffered global trigger unit allowing eTimer synchronization and/or ADC command generation  Double buffered ADC command list pointers to minimize ADC-trigger unit update  Double buffered ADC conversion command list with as many as 24 ADC commands  Each trigger capable of generating consecutive commands  ADC conversion command allows control of ADC channel from each ADC, single or synchronous sampling, independent result queue selection  DMA support with safety features

1.5.35 Cyclic Redundancy Checker (CRC) Unit

The CRC module is a configurable multiple data flow unit to compute CRC signatures on data written to its input register. The CRC unit has the following features:  3 sets of registers to allow 3 concurrent contexts with possibly different CRC computations, each with a selectable polynomial and seed  Computes 16- or 32-bit wide CRC on the fly (single-cycle computation) and stores result in internal register.  The following standard CRC polynomials are implemented: – x8 + x4 + x3 + x2 + 1 [8-bit CRC] – x16 + x12 + x5 + 1 [16-bit CRC-CCITT] – x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1  [32-bit CRC-ethernet(32)]  Key engine to be coupled with communication periphery where CRC application is added to allow implementation of safe communication protocol  Offloads core from cycle-consuming CRC and helps checking configuration signature for safe start-up or periodic procedures  CRC unit connected as peripheral bus on internal peripheral bus  DMA support

1.5.36 Redundancy Contro l and Checker Unit (RCCU)

The RCCU checks all outputs of the sphere of replication (addresses, data, control signals). It has the following features:  Duplicated module to guarantee highest possible diagnostic coverage (check of checker)  Multiple times replicated IPs are used as checkers on the SoR outputs

1.5.37 Junction temperature sensor

The junction temperature sensor provides a value via an ADC channel that can be used by software to calculate the device junction temperature. The key parameters of the junction temperature sensor include:  Nominal temperature range from –40 to 150 °C  Software temperature alarm via analog ADC comparator possible

1.5.38 Nexus Port Controller (NPC)

The NPC module provides real-time development support capabilities for this device in compliance with the IEEE-ISTO 5001-2003. This development support is supplied for MCUs without requiring external address and data pins for internal visibility. The NPC block interfaces to the host processor and internal buses to provide development support as per the IEEE-ISTO 5001-2003 Class 3+, including selected features from Class 4 standard. The development support provided includes program trace, data trace, watchpoint trace, ownership trace, run-time access to the MCUs internal memory map and access to the Power Architecture internal registers during halt. The Nexus interface also supports a JTAG only mode using only the JTAG pins. The following features are implemented:  Full and reduced port modes  MCKO (message clock out) pin  4 or 12 MDO (message data out) pins (b)  2 MSEO (message start/end out) pins  EVTO (event out) pin – Auxiliary input port  EVTI (event in) pin  5-pin JTAG port (JCOMP, TDI, TDO, TMS, and TCK) – Supports JTAG mode  Host processor (e200) development support features – Data trace via data write messaging (DWM) and data read messaging (DRM). This allows the development tool to trace reads or writes, or both, to selected internal memory resources. – Ownership trace via ownership trac e messaging (OTM). OTM facilitates ownership trace by providing visibility of which process ID or operating system task is activated. An ownership trace message is transmitted when a new process/task is activated, allowing development tools to trace ownership flow. – Program trace via branch trace messagi ng (BTM). Branch trace messaging displays program flow discontinuities (direct branches, indirect branches, b. 4 MDO pins on LQFP144 package, 12 MDO pins on LFBGA257 package.

exceptions, etc.), allowing the development tool to interpolate what transpires between the discontinuities. Thus, static code may be traced. – Watchpoint messaging (WPM) via the auxiliary port – Watchpoint trigger enable of program and/or data trace messaging – Data tracing of instruction fetches via private opcodes 1.5.39 IEEE 1149.1 JTAG Controller (JTAGC) The JTAGC block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. All data input to and output from the JTAGC block is communicated in serial format. The JTAGC block is compliant with the IEEE standard. The JTAG controller provides the following features:  IEEE Test Access Port (TAP) interface with 5 pins: –T D I –T M S –T C K –T D O –J C O M P  Selectable modes of operation include JTAGC/debug or normal system operation  5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions: –B Y P A S S – IDCODE –E X T E S T –S A M P L E – SAMPLE/PRELOAD  3 test data registers: a bypass register, a boundary scan register, and a device identification register. The size of the boundary scan register is parameterized to support a variety of boundary scan chain lengths.  TAP controller state machine that controls the operation of the data registers, instruction register and associated circuitry

1.5.40 Voltage regulator / Power Management Unit (PMU)

The on-chip voltage regulator module provides the following features:  Single external rail required  Single high supply required: nominal 3.3 V both for packaged and Known Good Die option – Packaged option requires external balla st transistor due to reduced dissipation capacity at high temperature but can use embedded transistor if power dissipation is maintained within package dissipation capacity (lower frequency of operation) – Known Good Die option uses embedded balla st transistor as dissipation capacity is increased to reduce system cost  All I/Os are at same voltage as external supply (3.3 V nominal)  Duplicated Low-Voltage Detectors (LVD) to guarantee proper operation at all stages (reset, configuration, normal operation) and, to maximize safety coverage, one LVD can be tested while the other operates (on-line self-testing feature)

1.5.41 Built-In Self-Test (BIST) capability

This device includes the following protection against latent faults:  Boot-time Memory Built-In Self-Test (MBIST)  Boot-time scan-based Logic Built-In Self-Test (LBIST)  Run-time ADC Built-In Self-Test (BIST)  Run-time Built-In Self Test of LVDs

2 Package pinouts and signal descriptions

2.1 Package pinouts

Figure 2 shows the RPC56EL60L5 in the LQFP144 package. Figure 2. RPC56EL60L5 LQFP144 pinout (top view) Figure 3 shows the RPC56EL60L5 in the LFBGA257 package.

Figure 3. RPC56EL60L5 LFBGA257 pinout (top view) packages, respectively, listing all the signals multiplexed to each pin.

1. NC = Not connected (the pin is physical ly not connected to anything on the device)

Table 3. LQFP144 pin function summary

10 A[7]

11 C[4]

12 A[8]

13 C[5]

Table 3. LQFP144 pin function summary (continued)

14 A[5]

15 C[7]

16 V DD_HV_REG_0 —

17 V SS_LV_COR —

18 V DD_LV_COR —

19 F[7]

20 F[8]

21 V DD_HV_IO —

22 V SS_HV_IO —

23 F[9]

24 F[10]

25 F[11]

26 D[9]

27 V DD_HV_OSC —

28 V SS_HV_OSC —

29 XTAL —

30 EXTAL —

31 RESET —

32 D[8]

33 D[5]

34 D[6]

35 V SS_LV_PLL0_PLL1 —

36 V DD_LV_PLL0_PLL1 —

37 D[7]

38 FCCU_F[0] FCCU F[0] F[0]

39 V DD_LV_COR —

40 V SS_LV_COR —

41 C[1]

42 E[4]

43 B[7]

44 E[5]

45 C[2]

46 E[6]

47 B[8]

48 E[7]

49 E[2]

50 V DD_HV_ADR0 —

51 V SS_HV_ADR0 —

52 B[9]

53 B[10]

54 B[11]

55 B[12]

56 V DD_HV_ADR1 —

57 V SS_HV_ADR1 —

58 V DD_HV_ADV —

59 V SS_HV_ADV —

60 B[13]

61 E[9]

62 B[15]

63 E[10]

64 B[14]

65 E[11]

66 C[0]

67 E[12]

68 E[0]

69 BCTRL —

70 V DD_LV_COR —

71 V SS_LV_COR —

72 V DD_HV_PMU —

73 A[0]

74 A[1]

75 G[11]

76 D[10]

77 G[10]

78 D[11]

79 G[9]

80 C[11]

81 G[8]

82 C[12]

83 G[7]

84 A[2]

85 G[5]

86 B[5]

87 TMS —

88 TCK —

89 B[4]

90 V SS_HV_IO —

91 V DD_HV_IO —

92 A[3]

93 V DD_LV_COR —

94 V SS_LV_COR —

95 V DD_HV_REG_1 —

96 V SS_HV_FLA —

97 V DD_HV_FLA —

98 G[6]

99 D[12]

100 G[4]

101 C[13]

102 G[2]

103 C[14]

104 G[3]

105 D[14]

106 F[12]

107 V PP_TEST

108 A[4]

109 B[0]

110 B[1]

111 C[10]

112 F[13]

113 F[15]

114 B[2]

115 F[14]

116 B[3]

117 E[13]

118 A[10]

119 E[14]

120 A[11]

121 E[15]

122 A[12]

123 JCOMP — — JCOMP

124 C[15]

125 D[0]

127 V SS_HV_IO —

128 D[3]

129 D[4]

130 V DD_HV_REG_2 —

131 V DD_LV_COR —

132 V SS_LV_COR —

133 F[0]

134 A[9]

136 A[13]

137 V SS_LV_COR —

138 B[6]

139 F[3]

140 D[2]

141 FCCU_F[1] FCCU F[1] F[1]

142 C[6]

143 A[14]

144 A[15]

1. V PP_TEST should always be tied to ground (VSS) for normal operations.

Table 4. LFBGA257 pin function summary

Table 4. LFBGA257 pin function summary (continued)

1. V PP_TEST should always be tied to ground (VSS) for normal operations.

2.2 Supply pins

Table 5. Supply pins between these pins and the nearest VDD_LV_COR pin.

17 VSS_HV (2)

18 VDD_LV (1)

39 VDD_LV (1)

between these pins and the nearest VDD_LV_COR pin.

40 VSS_LV (2)

capacitor must be connected between this pins and VSS_LV_REGCOR.

70 VDD_LV (1)

capacitor must be connected between this pins and VDD_LV_REGCOR.

71 VSS_LV (2)

between these pins and the nearest VSS_LV_COR pin.

93 VDD_LV (1)

connected between these pins and the nearest VDD_LV_COR pin.

94 VSS_LV (2)

between these pins and the nearest VDD_LV_COR pin.

131 VDD_LV (1)

between these pins and the nearest VDD_LV_COR pin.

132 VSS_LV (2)

between these pins and the nearest VDD_LV_COR pin.

135 VDD_LV (1)

between these pins and the nearest VDD_LV_COR pin.

137 VSS_LV (2)

1. VDD_LV balls are tied together on the LFBGA257 substrate.
2. VSS_LV balls are tied together on the LFBGA257 substrate.
3. VDD_HV balls are tied together on the LFBGA257 substrate.
4. VSS_HV balls are tied together on the LFBGA257 substrate.

Table 5. Supply pins (continued)

2.3 System pins

Note: None of system pins (except R ESET) provides an open drain output.

2.4 Pin muxing

Table 7 defines the pin list and muxing for this device. functions. The default function assigned to each pin after reset is indicated by ALT0. voltage may cause unpredictable device behavior or damage. Table 6. System pins

1. This pad is configured for Fast (F) pad speed.
2. This pad contai ns a weak pull-up.
3. EXTAL is an "Output" in "crystal" mode, and is an "Input" in "ext clock" mode.
4. In XOSC Bypass Mode, the analog portion of crystal oscillator (amplifier) is disabled. An external clock can be applied at
5. This pad contains a weak pull-down.
6. RESET output shall be considered valid only af ter the 3.3V supply reaches its stable value.

Table 7. Pin muxing

Table 7. Pin muxing (continued)

1. Programmable via the SRC (Slew Rate Control) bit in the re spective Pad Configuration Register; S = Slow, M = Medium,
2. The default function of this pin out of reset is ALT1 (TDO).

3 Electrical characteristics

3.1 Introduction

characteristics, and AC timing specifications for this device. normal device operation. An example is the input voltage of a voltage regulator. the signals that the chip provides. normal device operation. They specify how each characteristic is guaranteed. – P: parameter is guaranteed by production testing of each individual device. from a statistically relevant sample size across process variations. are shown in the typical (“typ”) column are within this category. – D: parameters are derived mainly from simulations.

3.2 Absolute maximum ratings

Table 8. Absolute maximum ratings(1)

3.3 Recommended operating conditions

0.5 V/s V/

1. Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress ratings

extended periods may affect device reliability or cause permanent damage to the device.

1. Any voltage between operating condition and absolute max rati ng can be sustained for maximum cumulative time of 10
2. Voltage overshoots during a high-to-low or low-to-hi gh transition must not exceed 10 seconds per instance.
3. Internal structures hold the input voltage less than the ma ximum voltage on all pads powered by VDDE supplies, if the

maximum injection current specification is met and VDDE is within the operating voltage specifications.

1. V DD has to be considered equal to to VDD_HV_ADRx in case of ADC pins, whilst it is VDD_HV_IOx for any other pin.

Table 8. Absolute maximum ratings(1) (continued) Table 9. Recommended operating conditions (3.3 V)

3.4 Thermal characteristics

1. Full functionality cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics and

I/Os DC electrical specification may not be guaranteed.

1. V DD_HV_ADR0 and VDD_HV_ADR1 cannot be operated at different voltages, and need to be supplied by the same voltage
2. VDD_HV_ADRx must always be applied and should be stable before LBIST starts. If this supply is not above its absolute

minimum level, LBIST operations can fail.

1. Can be connected to emitter of external NPN. Low voltage supp lies are not under user control. They are produced by an on-
2. For the device to function properly, the low voltage grounds (V SS_LV_xxx) must be shorted to high voltage grounds

(VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected to the external ballast emitter, if one is used. Table 9. Recommended operating conditions (3.3 V) (continued) Table 10. Thermal characteristics for LQFP144 package(1)

3.4.1 General notes for sp ecifications at maximum junction temperature

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
2. Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets

JEDEC specification for this package.

1. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification
2. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is

used for the case temperature. Reported value includes the thermal resistance of the interface layer.

1. Thermal characterization parameter indicating the temper ature difference between the package top and the junction

Table 11. Thermal characteristics for LFBGA257 package(1)

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
2. Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets

JEDEC specification for this package.

1. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification
2. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is

used for the case temperature. Reported value includes the thermal resistance of the interface layer.

1. Thermal characterization parameter indicating the temper ature difference between the package top and the junction

common usage: the value determined on a single layer board and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed in Equation 2 as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: Equation 2 : RJA = RJC + RCA where: RJA = junction to ambient thermal resistance (°C/W) RJC= junction to case thermal resistance (°C/W) RCA= case to ambient thermal resistance (°C/W) RJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal Characterization Parameter ( JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using Equation 3: Equation 3 TJ = TT + (JT × PD) where: T T= thermocouple temperature on top of the package (°C) JT= thermal characterization parameter (°C/W) PD= power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. References Semiconductor Equipment and Materials International

3081 Zanker Road

San Jose, CA 95134 USA (408) 943-6900 MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC specifications are available on the WEB at http://www.jedec.org.

1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an
2. G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled

Applications,” Electronic Packaging and Production, pp. 53–58, March 1998.

1. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal

3.5 Electromagnetic Interfer ence (EMI) characteristics

The configuration information referenced in Table 13 is explained in Table 12. Table 12. EMI configuration summary

• High emission = all pads have max slew rate, LVDS pads running at 40 MHz
• Oscillator frequency = 40 MHz
• System bus frequency = 80 MHz
• No PLL frequency modulation
• IEC level I ( 36 dBV) Configuration B
• Reference emission = pads use min, mid and max slew rates, LVDS pads disabled
• Oscillator frequency = 40 MHz
• System bus frequency = 80 MHz
• 2% PLL frequency modulation
• IEC level K( 30 dBV)

3.6 Electrostatic discharg e (ESD) characteristics

Electrostatic Discharge Sensitivity Measurement is available on request. Table 13. EMI emission testing specifications

150 MHz —1 6—

500 MHz —3 2—

1000 MHz —2 5—

150 MHz —1 5—

150 MHz —2 1—

500 MHz —3 0—

1000 MHz —2 4—

Table 14. ESD ratings(1), (2)

3.7 Static latch-up (LU)

 A supply overvoltage is applied to each power supply pin.  A current injection is applied to each input, output and configurable I/O pin. These tests are compliant with the EIA/JESD 78 IC latch-up standard.

3.8 Voltage regulator electrical characteristics

 High voltage detector (HVD_DIG_BKUP) for the self-test of HVD_DIG_MAIN. RPC56EL60L5 makes a transition from HPREG1 to HPREG2. This transition is dynamic. Once HPREG2 is fully operational, the controller part of HPREG1 is switched off.

1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification

room temperature followed by hot temperature, unless specified otherwise in the device specification.

1. Data based on characterization results, not tested in production.

Table 14. ESD ratings(1), (2) (continued) Table 15. Latch-up results

1 LU SR Static latch-up class T A = 125 °C conforming to JESD 78 II level A

vendors is the same, there are slight variations in the temperature coefficient parameter. temperature coefficient and against the specified gain range to have a robust design. Table 16. Characteristics

1. derating factor 12mW/degC
2. Adjust resistor at bipolar transisto r collector for 3.3V to avoid VCE<VCESAT

Table 17. Voltage regulator electrical specifications

1.2 V pins

Table 17. Voltage regulator electrical specifications (continued)

Figure 4. BCP68 board schematic example avoid the resonance and make the regulator stable.

3.9 DC electrical characteristics

Table 18 gives the DC electrical characteristics at 3.3 V (3.0 V < VDD_HV_IOx < 3.6 V). Table 18. DC electrical characteristics(1)

3.10 Supply current characteristics

are subject to change per device characterization.

1. These specifications are design targets and subject to change per device characterization.
2. “SR” parameter values must not exc eed the absolute maximum ratings shown in Table 8.
3. The max input voltage on the ADC pins is the ADC reference voltage VDD_HV_ADRx.
4. Measured values are applicable to all modes of the pad i.e. IBE = 0/1 and / or APC= 0/1.

Table 18. DC electrical characteristics(1) (continued) Table 19. Current consumption characteristics

1.2 V supplies

1.2 V supplies during

Table 19. Current consumption characteristics (continued)

120 MHz

60 MHz

3.3 V supplies

1. Devices configured for DPM mode, single core only with Core 0 executing typical code at 120 MHz from SRAM and Core 1
2. Enabled Modules in 'Typical mode': Flex PWM0, ETimer0/1/2, CTU, SWG, DMA, FlexCAN0/1, LINFlex, ADC1, DSPI0/1,
3. Internal structures hold the input voltage less than VDDA + 1.0 V on all pads powered by VDDA supplies, if the maximum

injection current specification is met and VDDA is within the operating voltage specifications.

1. This value is the total current for both ADCs.
2. VFLASH is only available in the calibration package.

3.11 Temperature sensor electrical characteristics

3.12 Main oscillator elec trical characteristics

Figure 5. Crystal oscillator and resonator connection scheme Note: XTAL/EXTAL must not be directly used to drive external circuits. Table 20. Temperature sensor electrical characteristics

Figure 6. Main oscillator electrical characteristics Table 21. Main oscillator electrical characteristics

1. V DD = 3.3 V ±10%, TJ = –40 to +150 °C, unless otherwise specified.
2. The recommended configuration for maximizing the oscillator margin are: 

3.13 FMPLL electrical characteristics

Table 22. FMPLL electrical characteristics

3.15 ADC electrical characteristics

1. Considering operation wi th FMPLL not bypassed.
2. With FM; the value does not include a possible +2% modulation
3. “Loss of Reference Frequency” window is the reference frequenc y range outside of which the FMPLL is in self clocked
4. Self clocked mode frequency is the frequency that the FMP LL operates at when the reference frequency falls outside the
5. f VCO is the frequency at the output of the VCO; its range is 256–512 MHz.
6. This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this

FMPLL, load capacitors should not exceed these limits.

1. This specification applies to the period required for the FMP LL to relock after changing the MFD frequency control bits in

the synthesizer control register (SYNCR).

1. This value is determined by the crystal manufacturer and board design.
2. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fSYS.

percentage for a given interval.

1. Proper PC board layout procedures must be followed to achieve specifications.
2. Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER and either

fCS or fDS (depending on whether center spread or down spread modulation is enabled).

1. Modulation depth is attenuated from depth setting wh en operating at modulation frequencies above 50 kHz.

Table 23. 16 MHz RC oscillator electrical characteristics

Figure 7. ADC characteristics and error definitions

3.15.1 Input Impedance and ADC Accuracy

input signal (bandwidth) and the equivalent input impedance of the ADC itself.

1 LSB (ideal)

1 LSB ideal =(VrefH-VrefL)/ 4096 =

Equation 4 generates a constraint for external network design, in particular on resistive path. Figure 8. Input Equivalent Circuit sampling phase is started (A/D switch close).

Figure 9. Transient Behavior during Sampling Phase

respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing. Figure 10. Spectral representation of input signal

during the time in which the sampling switch is closed. Table 24. ADC conversion characteristics R Sampling frequency — — — 983.

3.16 Flash memory elect rical characteristics

1. T J = –40 to +150 °C, unless otherwise specified and analog input voltage from VAGND to VAREF.
2. AD_CK clock is always half of the ADC module input cl ock defined via the auxiliary clock divider for the ADC.
3. This is the maximum frequency that the analog portion of the ADC can attain. A sustained conversion at this frequency is
4. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal

clock tsample depend on programming.

1. This parameter does not include the sample time Tsam ple, but only the time for determining the digital result.

Table 24. ADC conversion characteristics (continued) Table 25. Flash memory program and erase electrical specifications

1. Typical program and erase times represent the median perfor mance and assume nominal supply values and operation at
2. Initial Max program and erase times provide guidance for time-out limits used in the factory and apply for <100

program/erase cycles, nominal supply values and operation at 25C. These values are verified at production test.

1. Lifetime Max program and erase times apply across the vo ltage, temperature, and cycling range of product life. These

values are characterized, but not tested.

1. Program times are actual hardware programming times and do not include software overhead.

Table 26. Flash memory timing

1. Repeated suspends at a high frequency may result in t he operation timing out, and the flash module will respond by

Program operation). The minimum time between suspends to ensure this does not occur is TPSRT.

1. If Erase suspend rate is less than T ESRT, an increase of slope voltage ramp occurs during erase pulse. This improves erase

Table 27. Flash memory module life

48 KB, and 64 KB blocks over the operating temperature

3.17 SWG electrical characteristics

3 Retentio

1. Operating temperature range is T J from –40 °C to 150 °C. Typical endurance is evaluated at 25 C.
2. Typical P/E cycles is 100,000 cycles for 128 KB and 256 KB blocks.
3. Ambient temperature averaged over duration of applicati on, not to exceed product operating temperature range.

Table 27. Flash memory module life (continued) Table 28. RPC56EL60L5 SWG Specifications

1. Peak to Peak value is measured with no R or I load.
2. Peak to Peak excludes noise , SiNAD must be considered.
3. Common mode value is measured with no R or I load.
4. SiNAD is measured at Max Peak to Peak voltage.
5. Internal device routing resistance. ESD pad resistance is in series and must be considered for max Peak to Peak voltages,

depending on application I load and/or R load.

3.18 AC specifications

3.18.1 Pad AC specifications

Table 29. Pad AC specifications (3.3 V , IPP_HVE = 0 )(1)

4 Symmetric T 1 — 8 — — 5 — — 50 3 — 25 25

1. Propagation delay from V DD_HV_IOx/2 of internal signal to Pchannel/Nchannel switch-on condition.
2. Slope at rising/falling edge.
3. Data based on characterization re sults, not tested in production.

Figure 11. Pad output delay

3.19 Reset sequence

3.19.1 Reset sequence duration

different reset sequences described in Section 3.19.2. Table 30. RESET sequences

1. The maximum value is applicable only if the reset sequence duration is not prolonged by an extended assertion of RESET

by an external reset generator.

3.19.2 Reset sequence description

as the reset trigger mapping to the different reset sequences is specified in Section 3.19.3. application execution starts and the internal reset sequence is finished. reset generator keeping RESET asserted low beyond the last PHASE3. Figure 12. Destructive Reset Sequence, BIST enabled Figure 13. Destructive Reset Sequence, BIST disabled

low for the duration of the internal reset sequence(c).

3.19.3 Reset sequence trigger mapping

that are the basis for the timing data provided in Table 30. c. See RGM_FBRE register for more details. Table 31. Reset sequence trigger — reset sequence

1. Whether BIST is executed or not depends on the chip conf iguration data stored in the shadow sector of the NVM.
2. End of the internal reset sequence (as specified in Table 30) can only be observed by release of RESET if it is not held low
3. The assertion of RESET can only trigger a reset sequence if the device was running (RESET released) before. RESET

can prolong these sequences if RESET is held low externally beyond the end of the internal sequence (beyond PHASE3).

1. If RESET is configured for long reset (default) and if BIST is enabled via chip configuration data stored in the shadow sector
2. If RESET is configured for long reset (default) and if BIST is disabled via chip configuration data stored in the shadow

3.19.4 Reset sequence — start condition

compared to the overall reset sequence duration. Sequence, BIST enabled and the start for the Destructive Reset Sequence, BIST disabled. Figure 17. Reset sequence start for Destructive Resets initiated by the assertion of RESET as specified in Table 31.

1. If RESET is configured for short reset
2. Internal reset sequence can only be observed by state of RESET if bidirectional RESET functionality is enabled for the

functional reset source which triggered the reset sequence. Table 32. Voltage Thresholds

Figure 18. Reset sequence start via RESET assertion

3.19.5 External watchdog window

Figure 19. Reset sequence - External watchdog trigger window position

3.20 AC timing characteristics

3.20.1 RESET pin characteristics

The RPC56EL60L5 implements a dedicated bidirectional RESET pin. Figure 20. Start-up reset requirements Figure 21. Noise filtering on reset signal

3.20.2 WKUP/NMI timing

Table 33. RESET electrical characteristics

3 WNFRS

1. V DD = 3.3 V ± 10%, TJ = –40 to +150 °C, unless otherwise specified
2. C L includes device and package capacitance (CPKG < 5 pF).

Table 34. WKUP/NMI glitch filter Table 35. JTAG pin AC electrical characteristics

Figure 24. JTAG boundary scan timing

3.20.4 Nexus timing

Table 36. Nexus debug port timing(1)

Figure 27. Nexus Double Data Rate (DDR) Mode output timing

Figure 28. Nexus TDI, TMS, TDO timing

3.20.5 External interr upt timing (IRQ pin)

Table 37. External interrupt timing

1. Applies when IRQ pins are configured for rising edge or falling edge events, but not both.

Figure 29. External interrupt timing

3.20.6 DSPI timing

Table 38. DSPI timing

Figure 30. DSPI classic SPI timing — master, CPHA = 0

1. Slave Receive Only Mode can operate at a maximum frequency of 60 MHz. In this mode, the DSPI can receive data on

SIN, but no valid data is transmitted on SOUT. Table 38. DSPI timing (continued) Note: The numbers shown are referenced in Table 38.

4 Package characteristics

4.1 ECOPACK ®

specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.

4.2 Package mechanical data

Figure 39. LQFP144 package mechanical drawing

Table 39. LQFP144 mechanical data

1. Values in inches are converted fr om mm and rounded to four decimal digits.

Figure 40. LFBGA257 package mechanical drawing Table 40. LFBGA257 mechanical data

TITLE: LFBGA 14x14x1.7 257 F17x17 PITCH 0.8 BALL 0.4 PACKAGE CODE: JEDEC/EIAJ REFERENCE NUMBER: JEDEC STANDARD NO.95 SECTION 4.5 (Fine pitch, Square Ball Grid Array Package Design Guide) DIMENSIONS DATABOOK (mm) DRAWING (mm) A 1.70 1.45 (1) A1 0.21 0.25 0.30 0.35 A2 1.085 1.03 1.085 1.14 A3 0.30 0.26 0.30 0.34 A4 0.80 0.77 0.785 0.80 D1 12.80 12.80 E1 12.80 12.80 e 0.80 0.80 F 0.6 0.6 ddd 0.12 0.12 eee 0.15 0.15 (3) fff 0.08 0.08 (4) NOTES: (1) - LFBGA stands for Low profile Fine Pitch Ball Grid Array. - Low Profile: The total profile height (Dim A) is measured from the seating plane to the top of the component - The maximum total package height is calculated by the following methodology: A2 Typ+A1 Typ +¥ (A1²+A3²+A4² tolerance values) - Low profile: 1.20mm < A ” 1.70mm / Fine pitch: e < 1.00mm pitch. (2) – The typical ball diameter before mounting is 0.40mm. (3) - The tolerance of position that controls the location of the pattern of balls with respect to datums A and B. For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. (4) - The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each tolerance zone fff in the array is contained entirely in the respective zone eee above The axis of each ball must lie simultaneously in both tolerance zones. (5) - The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. - A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner is optional.

5 Ordering information

Figure 41. Commercial product code structure

6 Revision history

Table 41 summarizes revisions to this document. Table 41. Document revision history 23-Sep-2014 1 Initial release.