RP56D CONEXANT | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 18
Technical content
Features
- Downloadable MDP code from the host/DTE
- 2-wire full-duplex - V.90 and K56flex (RP56 models) - V.34 (33.6 kbps) (RP56 and RP336 models) - Bell 212 and 103
- 2-wire half-duplex - Bell 208 - Short train option in V.17 and V.27 ter
- Serial synchronous and asynchronous data
- Parallel synchronous and asynchronous data
- Parallel synchronous SDLC/HDLC support
- In-band secondary channel (V.34 and V.32 bis)
- Automatic mode selection (AMS)
- Automatic rate adaption (ARA)
- Digital near-end and far-end echo cancellation
- Bulk delay for satellite transmission
- ADPCM voice mode (7.2 kHz or 8.0 kHz)
- Voice pass-through mode (7.2 kHz, 8.0 kHz, or 11.025 kHz)
- Full-duplex speakerphone (SP models) - Acoustic and line echo cancellation - Programmable microphone AGC - Microphone volume selection and muting - Speaker volume control and muting; room monitor
- AudioSpan (SP models) - ITU-T V.61 modulation (4.8 kbps data plus audio) - Handset, headset, or half-duplex speakerphone
- TTL and CMOS compatible DTE interface - ITU-T V.24 (EIA/TIA-232-E) (data/control) - Microprocessor bus (data/configuration/control)
- Dynamic range: -9 dBm to -43 dBm
- Adjustable speaker output to monitor received signal
- DMA support interrupt lines
- Transmit and receive (16+128)-byte FIFO data buffers
- NRZI encoding/decoding
- 511 pattern generation/detection
- V.8 and V.8 bis signaling
- V.13 signaling
- Diagnostic capability - V.54 inter-DCE signaling - V.54 local analog and remote digital loopback
- +3.3V operation with +5V tolerant inputs - +5V analog operation
- Power consumption: - Normal Mode = 280 mW; Sleep Mode = 53 mW
- Low profile, small footprint package - 100-pin PQFP
53'53'DQG53' /RZ9ROWDJH9 .IOH[99ELV0RGHP'DWD3XPSV /G15 /G30/G27/G15/G14/G15 /G37/G44/G45/G4F/G48 /G14/G11 /G30/G52/G47/G48/G50 /G30/G52/G47/G48/G4F/G56 /G44/G51/G47 /G29/G58/G51/G46/G57/G4C/G52/G51/G56 /G30/G52/G47/G48/G50/G12/G33/G44/G55/G57 /G31/G58/G50/G45/G48/G55 /G14 /G33/G44/G46/G4E/G44/G4A/G48 /G44/G51/G47 /G33/G44/G46/G4E/G44/G4A/G48 /G32/G53/G57/G4C/G52/G51/G56 /G36/G58/G53/G53/G52/G55/G57/G48/G47 /G29/G58/G51/G46/G57/G4C/G52/G51/G56 /G15 /G30/G52/G47/G48/G4F /G31/G58/G50/G45/G48/G55 /G33/G44/G55/G57 /G31/G52/G11 /G33/G44/G46/G4E/G44/G4A/G48 /G26/G4F/G52/G46/G4E/G12/G26/G55/G5C/G56/G57/G44/G4F /G2C/G51/G53/G58/G57 /G24/G51/G44/G4F/G52/G4A /G2C/G51/G57/G48/G55/G49/G44/G46/G48 /G39/G52/G4F/G57/G44/G4A/G48 /G39/G11/G1C/G13/G12/G2E/G18/G19/G49/G4F/G48/G5B /G27/G44/G57/G44 /G39/G11/G16/G17 /G27/G44/G57/G44 /G39/G11/G16/G15 /G45/G4C/G56 /G27/G44/G57/G44/G0F /G39/G11/G16/G17 /G29/G44/G5B/G0F /G35/G48/G50/G52/G57/G48 /G39/G52/G4C/G46/G48 /G29/G27/G36/G33/G0F /G24/G58/G47/G4C/G52/G36/G53/G44/G51 /G39/G52/G4C/G46/G48 /G36/G48/G55/G4C/G44/G4F /G2C/G51/G57/G48/G55/G49/G44/G46/G48 /G35/G33/G18/G19/G27/G12/G36/G33 /G35/G19/G1A/G19/G17/G10/G19/G14 /G14/G13/G13/G10/G33/G4C/G51 /G33/G34/G29/G33 /G26/G4F/G52/G46/G4E /G0E/G18/G39 /G3C /G3C /G3C /G3C /GB1 /G35/G33/G18/G19/G27 /G35/G19/G1A/G19/G17/G10/G19/G16 /G14/G13/G13/G10/G33/G4C/G51 /G33/G34/G29/G33 /G26/G4F/G52/G46/G4E /G0E/G18/G39 /G3C /G3C /G3C /GB1 /GB1 /G35/G33/G16/G16/G19/G27/G12/G36/G33 /G35/G19/G1A/G19/G17/G10/G19/G18 /G14/G13/G13/G10/G33/G4C/G51 /G33/G34/G29/G33 /G26/G4F/G52/G46/G4E /G0E/G18/G39 /GB1 /G3C /G3C /G3C /GB1 /G35/G33/G16/G16/G19/G27 /G35/G19/G1A/G19/G17/G10/G19/G1A /G14/G13/G13/G10/G33/G4C/G51 /G33/G34/G29/G33 /G26/G4F/G52/G46/G4E /G0E/G18/G39 /GB1 /G3C /G3C /GB1 /GB1 /G35/G33/G14/G17/G17/G27/G12/G36/G33 /G35/G19/G1A/G19/G17/G10/G19/G1C /G14/G13/G13/G10/G33/G4C/G51 /G33/G34/G29/G33 /G26/G4F/G52/G46/G4E /G0E/G18/G39 /GB1 /GB1 /G3C /G3C /GB1 /G35/G33/G14/G17/G17/G27 /G35/G19/G1A/G19/G17/G10/G19/G1B /G14/G13/G13/G10/G33/G4C/G51 /G33/G34/G29/G33 /G26/G4F/G52/G46/G4E /G0E/G18/G39 /GB1 /GB1 /G3C /GB1 /GB1 /G31/G52/G57/G48/G56/G1D /G14/G11 /G30/G52/G47/G48/G4F/G12/G53/G44/G55/G57 /G51/G58/G50/G45/G48/G55 /G52/G53/G57/G4C/G52/G51/G56/G1D /G27 /G27/G52/G5A/G51/G4F/G52/G44/G47/G44/G45/G4F/G48 /G36/G33 /G36/G53/G48/G44/G4E/G48/G55/G53/G4B/G52/G51/G48/G11 /G15/G11 /G36/G58/G53/G53/G52/G55/G57/G48/G47 /G49/G58/G51/G46/G57/G4C/G52/G51/G56 /G0B/G3C /G20/G36/G58/G53/G53/G52/G55/G57/G48/G47/G1E /GB1 /G20/G31/G52/G57 /G56/G58/G53/G53/G52/G55/G57/G48/G47/G0C/G1D /G29/G27/G36/G33 /G29/G58/G4F/G4F/G10/G47/G58/G53/G4F/G48/G5B /G56/G53/G48/G44/G4E/G48/G55/G53/G4B/G52/G51/G48 /G35/G48/G50/G52/G57/G48 /G39/G52/G4C/G46/G48 /G35/G48/G50/G52/G57/G48 /G59/G52/G4C/G46/G48 /G55/G48/G46/G52/G55/G47 /G44/G51/G47 /G53/G4F/G44/G5C/G45/G44/G46/G4E /G24/G58/G47/G4C/G52/G36/G53/G44/G51 /G24/G51/G44/G4F/G52/G4A /G56/G4C/G50/G58/G4F/G57/G44/G51/G48/G52/G58/G56 /G59/G52/G4C/G46/G48 /G44/G51/G47 /G47/G44/G57/G44/G11 Information provided by CONEXANT SYSTEMS, INC. (CONEXANT) is believed to be accurate and reliable. However, no responsibility is assumed by CONEXANT for its use, nor any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of CONEXANT other than for circuitry embodied in CONEXANT products. CONEXANT reserves the right to change circuitry at any time without notice. This document is subject to change without notice. K56flex is a trademark of CONEXANT SYSTEMS, INC. and Lucent Technologies. CONEXANT and “What's Next in Communications Technologies” are trademarks of CONEXANT SYSTEMS, INC. ©1998, CONEXANT SYSTEMS, INC. Printed in U.S.A. All Rights Reserved
/RZ9ROWDJH9 .IOH[99ELV0RGHP'DWD3XPSV 53'53'DQG53' /G30/G27/G15/G14/G1B /G16 Technical Description The MDP functional interface is illustrated in Figure 1. Configurations and Rates The selectable MDP configurations, signaling rates, and data rates are listed in Table 2. MD218F1 FID RS0-RS4 TELEPHONE LINE/ TELEPHONE/ AUDIO INTERFACE INTERFACE TELEPHONE LINE ~RLYA ~RLYB RINGD RIN TXA1 TXA2 MICM SPK SPKMD MICV/NC* TELIN/NC* TELOUT/NC* RXA TXA VCC (+3.3V) AGND DGND POWER SUPPLY HOST PROCESSOR DECODER ~CS ~READ ~WRITE DATA BUS (8) D0-D7 ADDRESS BUS (5) A0-A4 ~RESET IRQ MIC/ SPEAKERSPKR MIC TELEPHONE LINETELOUT TELIN V.24 SERIAL DTE INTERFACE ~RDCLK TDCLK XTCLK TXD RXD ~RTS ~CTS ~DTR ~DSR ~RLSD ~RI MODEM DATA PUMP (MDP) R6764:100-PIN PQFP] VGG (+5V ) CLOCK CIRCUIT CLKIN VAA (+5V) * PINS ARE INTERNAL NO CONNECT (NC) ON NON-SP MODELS. /G29/G4C/G4A/G58/G55/G48 /G14/G11 /G30/G27/G33 /G29/G58/G51/G46/G57/G4C/G52/G51/G44/G4F /G2C/G51/G57/G48/G55/G49/G44/G46/G48
53'53'DQG53' /RZ9ROWDJH9 .IOH[99ELV0RGHP'DWD3XPSV /G17 /G30/G27/G15/G14/G1B /G37/G44/G45/G4F/G48 /G15/G11 /G26/G52/G51/G49/G4C/G4A/G58/G55/G44/G57/G4C/G52/G51/G56/G0F /G36/G4C/G4A/G51/G44/G4F/G4C/G51/G4A /G35/G44/G57/G48/G56/G0F /G44/G51/G47 /G27/G44/G57/G44 /G35/G44/G57/G48/G56 /G26/G52/G51/G49/G4C/G4A/G58/G55/G44/G57/G4C/G52/G51 /G30/G52/G47/G58/G4F/G44/G57/G4C/G52/G51 /G26/G44/G55/G55/G4C/G48/G55 /G29/G55/G48/G54/G58/G48/G51/G46/G5C /G0B/G2B/G5D/G0C /G93/G13/G11/G13/G14/G08 /G27/G44/G57/G44 /G35/G44/G57/G48 /G0B/G45/G53/G56/G0C /G93/G13/G11/G13/G14/G08 /G36/G5C/G50/G45/G52/G4F /G35/G44/G57/G48 /G0B/G36/G5C/G50/G45/G52/G4F/G56/G12/G36/G48/G46/G11/G0C /G25/G4C/G57/G56/G12/G36/G5C/G50/G45/G52/G4F /G10 /G27/G44/G57/G44 /G25/G4C/G57/G56/G12/G36/G5C/G50/G45/G52/G4F /G10 /G37/G26/G30 /G26/G52/G51/G56/G57/G48/G4F/G4F/G44/G57/G4C/G52/G51 /G33/G52/G4C/G51/G57/G56 V.90/K56flex PCM* PCM – 56000R/V.34ratesT4 8000 Dynamic – – V.34 33600 TCM TCM Note 2 33600 Note 2 Note 2 Note 2 Note 2 V.34 31200 TCM TCM Note 2 31200 Note 2 Note 2 Note 2 Note 2 V.34 28800 TCM TCM Note 2 28800 Note 2 Note 2 Note 2 Note 2 V.34 26400 TCM TCM Note 2 26400 Note 2 Note 2 Note 2 Note 2 V.34 24000 TCM TCM Note 2 24000 Note 2 Note 2 Note 2 Note 2 V.34 21600 TCM TCM Note 2 21600 Note 2 Note 2 Note 2 Note 2 V.34 19200 TCM TCM Note 2 19200 Note 2 Note 2 Note 2 Note 2 V.34 16800 TCM TCM Note 2 16800 Note 2 Note 2 Note 2 Note 2 V.34 14400 TCM TCM Note 2 14400 Note 2 Note 2 Note 2 Note 2 V.34 12000 TCM TCM Note 2 12000 Note 2 Note 2 Note 2 Note 2 V.34 9600 TCM TCM Note 2 9600 Note 2 Note 2 Note 2 Note 2 V.34 7200 TCM TCM Note 2 7200 Note 2 Note 2 Note 2 Note 2 V.34 4800 TCM TCM Note 2 4800 Note 2 Note 2 Note 2 Note 2 V.34 2400 TCM TCM Note 2 2400 Note 2 Note 2 Note 2 Note 2 V.32 bis 14400 TCM TCM 1800 14400 2400 6 1 128 V.32 bis 12000 TCM TCM 1800 12000 2400 5 1 64 V.32 bis 9600 TCM TCM 1800 9600 2400 4 1 32 V.32 bis 7200 TCM TCM 1800 7200 2400 3 1 16 V.32 bis 4800 QAM 1800 4800 2400 2 0 4 V.32 9600 TCM TCM 1800 9600 2400 4 1 32 V.32 9600 QAM 1800 9600 2400 4 0 16 V.32 4800 QAM 1800 4800 2400 2 0 4 V.22 bis 2400 QAM 1200/2400 2400 600 4 0 16 V.22 bis 1200 DPSK 1200/2400 1200 600 2 0 4 V.22 1200 DPSK 1200/2400 1200 600 2 0 4 V.22 600 DPSK 1200/2400 600 600 1 0 4 V.23 1200/75 FSK 1700/420 1200/75 1200 1 0 – V.21 FSK 1080/1750 0–300 300 1 0 – Bell 208 4800 DPSK 1800 4800 1600 3 0 8 Bell 212A DPSK 1200/2400 1200 600 2 0 4 Bell 103 FSK 1170/2125 0–300 300 1 0 – V.23 1200/75 FSK 1700/420 1200/75 1200 1 0 – V.21 FSK 1080/1750 0–300 300 1 0 – V.17 14400 TCM/V.333 TCM 1800 14400 2400 6 1 128 V.17 12000 TCM/V.333 TCM 1800 12000 2400 5 1 64 V.17 9600 TCM3 TCM 1800 9600 2400 4 1 32 V.17 7200 TCM3 TCM 1800 7200 2400 3 1 16 V.29 96003 QAM 1700 9600 2400 4 0 16 V.29 72003 QAM 1700 7200 2400 3 0 8 V.29 48003 QAM 1700 4800 2400 2 0 4 V.27 48003 DPSK 1800 4800 1600 3 0 8 V.27 24003 DPSK 1800 2400 1200 2 0 4 V.21 Channel 23 FSK 1750 300 300 1 0 – Notes: 1. Modulation legend: TCM: Trellis-Coded Modulation QAM: Quadrature Amplitude Modulation FSK: Frequency Shift Keying DPSK: Differential Phase Shift Keying 2. Adaptive; established during handshake: /G26/G44/G55/G55/G4C/G48/G55 /G29/G55/G48/G54/G58/G48/G51/G46/G5C /G0B/G2B/G5D/G0C /G36/G5C/G50/G45/G52/G4F /G35/G44/G57/G48 /G0B/G25/G44/G58/G47/G0C /G39/G11/G16/G17 /G2F/G52/G5A /G26/G44/G55/G55/G4C/G48/G55 /G39/G11/G16/G17 /G2B/G4C/G4A/G4B /G26/G44/G55/G55/G4C/G48/G55 /G15/G17/G13/G13 /G14/G19/G13/G13 /G14/G1B/G13/G13 /G15/G1B/G13/G13 /G14/G19/G1B/G13 /G14/G1B/G19/G1A /G16/G13/G13/G13 /G14/G1B/G13/G13 /G15/G13/G13/G13 /G16/G15/G13/G13 /G14/G1B/G15/G1C /G14/G1C/G15/G13 /G16/G17/G15/G1C /G14/G1C/G18/G1C /G14/G1C/G18/G1C 3. Models with fax support only. 4. Maximum data rate. * RP56 models only. ** RP56 and RP336 models only.
/RZ9ROWDJH9 .IOH[99ELV0RGHP'DWD3XPSV 53'53'DQG53' /G30/G27/G15/G14/G1B /G18 Automatic Mode Selection When automatic mode selection (AMS) is enabled, the MDP configures itself to the highest compatible data rate supported by the remote modem (AUTO bit). Automode operation is supported in V.90, K56flex, V.34, V.32 bis, modes. Automatic Rate Adaption (ARA) In V.90, K56flex, V.34, and V.32 bis modes, automatic rate adaption (ARA) can be enabled to select the highest data rate possible based on the measured eye quality monitor (EQM) (EARC bit). This selection occurs during handshake/retrain and rate renegotiation. Tone Generation The MDP can generate single or dual voice-band tones from 0 Hz to 3600 Hz with a resolution of 0.15 Hz and an accuracy of ± 0.01%. Tones over 3000 Hz are attenuated. DTMF tone generation allows the MDP to operate as a programmable DTMF dialer. Data Encoding The data encoding conforms to ITU-T recommendations V.22 bis, V.22, V.23, or V.21, and is compatible with Bell 208, 212A, or 103, depending on the model and selected configuration. RTS - CTS Response Time The response times of CTS relative to a corresponding transition of RTS are listed in Table 3. Transmit Level The transmitter output level is selectable from 0 dBm to -15 dBm (VAA = +5V) in 1 dB steps and is accurate to ±0.5 dB when used with an external hybrid. The output level can also be fine tuned by changing a gain constant in MDP DSP RAM. The maximum V.34/V.32 bis/V.32 transmit level for acceptable receive performance should not exceed -9 dBm. Note: In V.34 mode, the transmit level may be automatically changed during the handshake. This automatic adjustment of the transmit level may be disabled via a parameter in DSP RAM. Transmitter Timing Transmitter timing is selectable between internal (±0.01%), external, or slave. Scrambler/Descrambler A self-synchronizing scrambler/descrambler is used in accordance with the selected configuration. Answer Tone When the NV25 bit is a zero, the MDP generates a 2100 Hz answer tone at the beginning of the answer handshake bis, V.22, V.23, and V.21). The answer tone has 180° phase reversals every 0.45 second to disable network echo cancellers (V.8, V.32 bis, V.32). /G37/G44/G45/G4F/G48 /G16/G11 /G35/G37/G36/G10/G26/G37/G36 /G35/G48/G56/G53/G52/G51/G56/G48 /G37/G4C/G50/G48/G56 RTS-CTS Response 1 Configuration Constant Carrier Controlled Carrier Turn-Off Sequence 3 V.90, K56flex, V.34, V.32 bis, V.32 ± 2 ms N/A N/A V.33/V.17 Long N/A 1393 ms2 15 ms4 V.33/V.17 Short N/A 142 ms2 15 ms4 V.29 N/A 253 ms21 2 m s V.27 4800 Long N/A 708 ms2 7 ms4 V.27 4800 Short N/A 50 ms2 7 ms4 V.27 2400 Long N/A 943 ms2 10 ms4 V.27 2400 Short N/A 67 ms2 10 ms4 V.22 bis, V.22, Bell 212A ± 2 ms 270 ms N/A V.21 500 ms 500 ms N/A V.23, Bell 103 210 ms 210 ms N/A Notes: 1. Times listed are CTS turn-on. The CTS OFF-to-ON response time is host programmable in DSP RAM. (Full- duplex modes only.) 2. Add echo protector tone duration plus 20 ms when echo protector tone is used during turn-on. 3. Turn-off sequence consists of transmission of remaining data and scrambled ones for controlled carrier operation. CTS turn-off is less than 2 ms for all configurations. 4. Plus 20 ms of no transmitted energy. 5. N/A = not applicable. Receive Level The MDP satisfies performance requirements for received line signal levels from –9 dBm to –43 dBm measured at the Receiver Analog (RXA) (TIP and RING) input (-15 dBm at RIN). Note: A 6 dB pad is required between TIP and RING and the RIN input. Receiver Timing The timing recovery circuit can track a frequency error in the associated transmit timing source of ±0.035% (V.22 bis) or ±0.01% (other configurations). Carrier Recovery The carrier recovery circuit can track a ±7 Hz frequency offset in the received carrier. Clamping Received Data (RXD) is clamped to a constant mark whenever the Received Line Signal Detector (~RLSD) is off. ~RLSD can be clamped off (RLSDE bit).
53'53'DQG53' /RZ9ROWDJH9 .IOH[99ELV0RGHP'DWD3XPSV /G19 /G30/G27/G15/G14/G1B Echo Canceller A data echo canceller with near-end and far-end echo cancellation is included for 2-wire full-duplex V.34/V.32 bis/V.32 operation. The combined echo span of near and far cancellers can be up to 40 ms. The proportion allotted to each end is automatically determined by the MDP. The delay between near-end and far-end echoes can be up to 1.2 seconds. V.90 and K56flex echo cancellation is also provided. ADPCM Voice Mode The Adaptive Differential Pulse Code Modulation (ADPCM) voice coder and decoder (codec) compresses and decompresses voice signals for efficient digital storage of voice messages. The codec operates at 28.8k, 21.6k, or 14.4k bps (4-bit, 3-bit, or 2-bit quantization, respectively) with a 7.2 kHz or 8.0 kHz sample rate. Transmit Voice. 16-bit compressed transmit voice can be sent to the MDP ADPCM codec for decompression then to the digital-to-analog converter (DAC) by the host. Receive Voice. 16-bit received voice samples from the MDP analog-to-digital converter (ADC) can be sent to the ADPCM codec for compression, and then be read by the host. Voice Pass-Through Mode Voice pass-through mode allows the host to transmit and receive uncompressed voice samples in 16-bit linear form at 7.2 kHz, 8.0 kHz, or 11.025 kHz sample rate, or in 8-bit A-Law/µ-Law PCM form at 8.0 kHz sample rate. Transmit Voice. Transmit voice samples can be sent to the MDP DAC from the host. Receive Voice. Received voice samples from the MDP ADC can be read by the host. Speakerphone Voice/Audio Paths (SP Models) The MDP incorporates a dual integrated analog interface. The voice/audio transmit and receive signals can be routed through several paths. The voice/audio paths are available in the speakerphone mode configuration and are selected through DSP RAM. The voice/audio input can be taken from one of four different sources: telephone line input (RIN), handset (TELIN), microphone (MICM or MICV). The speaker output (SPK) can originate from one of five different sources: RIN, TELIN, MICM or MICV or from the MDP’s internal voice playback mode. The voice/audio output may be routed to the telephone line output (TXA1 and TXA2) or handset (TELOUT). The voice paths can be switched to allow an audio input to be routed to the telephone line output through a variable gain for applications such as music-on-hold. The “room monitor” mode allows the MDP to receive audio from its surroundings and concurrently transmit the audio to a remote site. AudioSpan Mode (SP Models) AudioSpan provides full-duplex analog simultaneous audio/voice and data over a single telephone line at a data rate with audio of 4800 bps using V.61 modulation. AudioSpan can send any type of audio waveform, including music. Data can be sent with or without error correction. The audio/voice interface can be in the form of a headset, handset, or a microphone and speaker (half- duplex speakerphone). Handset echo cancellation is provided. Data Formats Serial Synchronous Data Data rate: 300-56000 bps (RP56), 300-33600 bps (RP56 and RP336), or 300-14400 bps, ±0.01%. Selectable clock: Internal, external, or slave. Serial Asynchronous Data Data rate: 300-56000 bps (RP56), 300-33600 bps (RP56 and RP336), or 300-14400 bps, 0-300 bps (V.21 and Bell 103); Bits per character: 7, 8, 9, 10, or 11. Parallel Synchronous Data Normal sync: 8-bit data for transmit and receive Data rate: 300-56000 bps (RP56), 300-33600 bps (RP56 and RP336), or 300-14400 bps, ±0.01%. SDLC/HDLC support: Transmitter: Flag generation, 0 bit stuffing, CRC-16 or CRC-32 generation. Receiver: Flag detection, 0 bit deletion, CRC-16 or CRC-32 checking. Parallel Asynchronous Data Data rate: 300-56000 bps (RP56), 300-33600 bps (RP56 and RP336), or 300-14400 bps, 1200, 300, or 75 bps (FSK). Data bits per character: 5, 6, 7, or 8. Parity generation/checking: Odd, even, or 9th data bit. Async/Sync and Sync/Async Conversion An asynchronous-to-synchronous converter is provided in the transmitter and a synchronous-to-asynchronous converter is provided in the receiver. The converters operate in both serial and parallel modes. The asynchronous character format is 1 start bit, 5 to 8 data bits, an optional parity bit, and 1 or 2 stop bits. Valid character size, including all bits, is 7, 8, 9, 10, or 11 bits per character. Two ranges of signaling rates are provided:
- Basic range: +1% to –2.5%
- Extended overspeed range: +2.3% to –2.5%
/RZ9ROWDJH9 .IOH[99ELV0RGHP'DWD3XPSV 53'53'DQG53' /G30/G27/G15/G14/G1B /G1A When the transmitter's converter is operating at the basic signaling rate, no more than one stop bit will be deleted per 8 consecutive characters. When operating at the extended rate, no more than one stop bit will be deleted per 4 consecutive characters. Break handling is performed as described in V.14. Asynchronous characters are accepted on the TXD serial input and are issued on the RXD serial output. V.54 Inter-DCE Signaling The MDP supports V.54 inter-DCE signaling procedures in synchronous and asynchronous configurations. Transmission and detection of the preparatory, acknowledgment, and termination phases as defined in V.54 are provided. Three control bits in the transmitter allow the host to send the appropriate bit patterns (V54T, V54A, and V54P bits). Three control bits in the receiver are used to enable one of three bit pattern detectors (V54TE, V54AE, and V54PE bits). A status bit indicates when the selected pattern detector has found the corresponding bit pattern (V54DT bit). V.13 Remote RTS Signaling The MDP supports V.13 remote RTS signaling. Transmission and detection of signaling bit patterns in response to a change of state in the RTS bit or the ~RTS input signal are provided. The RRTSE bit enables V.13 signaling. The RTSDE bit enables detection of V.13 patterns. The RTSDT status bit indicates the state of the remote RTS signal. This feature may be used to clamp/unclamp the local ~RLSD and RXD signals in response to a change in the remote RTS signal in order to simulate controlled carrier operation in a constant carrier environment. The MDP automatically clamps and unclamps ~RLSD. Dialing and Answering The host can dial and answer using supported DTMF/pulse dialing and tone detection functions. The major parameters are host programmable. Supervisory Tone Detection Three parallel tone detectors (A, B, and C) are provided for supervisory tone detection. The signal path to these detectors is separate from the main received signal path. Each tone detector consists of two cascaded second order IIR biquad filters. The coefficients are host programmable. Each fourth order filter is followed by a level detector which has host programmable turn-on and turn-off thresholds allowing hysteresis. Tone detector C is preceded by a prefilter and squarer. This circuit is useful for detecting a tone with frequency equal to the difference between two tones that may be simultaneously present on the line. The squarer may be disabled by the SQDIS bit causing tone detector C to be an eighth order filter. The tone detectors are disabled in data mode. The tone detection sample rate is 9600 Hz in V.8 and V.34 modes and is 7200 Hz in non-V.34 modes. The default call progress filter coefficients are based on a 7200 Hz sampling rate and apply to non-V.34 modes only. The maximum detection bandwidth is equal to one-half the sample rate. The default bandwidths and thresholds of the tone detectors are: Tone Detector Bandwidth Turn-On Threshold Turn-Off Threshold A 245 – 650 Hz –25 dBm –31 dBm B 360 – 440 Hz –25 dBm –31 dBm C Prefilter 0 – 500 Hz N/A N/A C 50 – 110 Hz * * * Tone Detector C will detect a difference tone within its bandwidth when the two tones present are in the range –1 dBm to –26 dBm.
511 Pattern Generation/Detection
In synchronous mode, a 511 pattern can be generated and detected (control bit S511). Use of this bit pattern during self-test eliminates the need for external test equipment. In-Band Secondary Channel A full-duplex in-band secondary channel is provided in V.34 (all speeds) and V.32 bis/V.32 (7200 bps and above) modes. Control bit SECEN enables and disables the secondary channel operation. The secondary channel operates in parallel data mode with independent transmit and receive interrupts and data buffers. The main channel may operate in parallel or serial mode. In V.34 modes, the secondary channel rate is 200 bps. In V.32 bis/V.32 modes, the secondary channel rate is 150 bps. This rate is also host programmable in V.32 bis/V.32 modes. Transmit and Receive FIFO Data Buffers Two (16+128)-byte first-in first-out (FIFO) data buffers allow the DTE/host to rapidly output up to 144 bytes of transmit data and input up to 144 bytes of accumulated received data. The receiver FIFO is always enabled. The transmitter FIFO is enabled by the FIFOEN control bit. TXHF and RXHF bits operate off the lower 16 bits and indicate the corresponding FIFO buffer half full (8 or more bytes loaded) status. TXFNF and RXFNE bits indicate the TXFIFO buffer not full and RXFIFO buffer not empty status, respectively. An interrupt mask register allows an interrupt request to be generated whenever the TXFNF, RXFNE, RXHF, or TXHF status bit changes state. The 128-byte FIFO extensions are enabled by default and can be disabled by clearing a bit in RAM. DMA Support Interrupt Request Lines DMA support is available in synchronous, asynchronous, and HDLC parallel data modes. Control bit DMAE enables and disables DMA support. When DMA support is enabled, the MDP ~RI and ~DSR lines are assigned to Transmitter Request (TXRQ) and Receiver Request (RXRQ) hardware output interrupt request lines, respectively. The TXRQ and RXRQ signals follow the assertion of the TDBE and RDBF interrupt bits thus allowing the DTE/host to respond immediately to the
53'53'DQG53' /RZ9ROWDJH9 .IOH[99ELV0RGHP'DWD3XPSV /G1B /G30/G27/G15/G14/G1B interrupt request without masking out status bits to determine the interrupt source. NRZI Encoding/Decoding NRZI data encoding/decoding may be selected in synchronous and HDLC modes instead of the default NRZ (control bit NRZIEN). In NRZ encoding, a 1 is represented by a high level and a 0 is represented by a low level. In NRZI encoding, a 1 is represented by no change in level and a 0 is represented by a change in level. ITU-T CRC-32 Support ITU-T CRC-32 generation/checking may be selected instead of the default ITU-T CRC-16 in HDLC mode using DSP RAM access. Caller ID Demodulation Caller ID information can be demodulated in V.23 1200 receive configuration and presented to the host/DTE in serial (RXD) and parallel (RBUFFER) form. Telephone Line Interface Line Transformer Interface. V.90/K56flex/V.34/V.32 bis/V.32 places high requirements upon the Data Access Arrangement (DAA) to the telephone line. Any non-linear distortion generated by the DAA in the transmit direction cannot be canceled by the MDP's echo canceller and interferes with data reception. The designer must, therefore, ensure that the total harmonic distortion seen at the RXA input to the MDP be at least 65 dB below the minimum level of received signal. Due to the wider bandwidth requirements in V.90, K56flex, and V.34, the DAA must maintain linearity from 10 Hz to 4000 Hz. Relay Control. Direct control of the off-hook and talk/data relays is provided. Internal relay drivers allow direct connection to the off-hook (RLYA) and talk/data (RLYB) relays. The talk/data relay output can optionally be used for pulse dial. Speaker Interface An analog speaker output (SPK) is provided with on/off and volume control logic incorporated in the MDP. An external amplifier is recommended if driving non-amplified speakers. A digital speaker output (SPKMD) is provided which reflects the received analog input signal digitized to TTL high or low level by an internal comparator to create a PC Card (PCMCIA)-compatible signal. Additional Information Additional information is provided in the RP56D, RP336D, and RP144D Modem Designer's Guide (Order No. 1155). Hardware Interface Signals A functional interconnect diagram showing the typical MDP connection in a system is illustrated in Figure 2. Any point that is active low is represented by a small circle at the signal point. Edge triggered inputs are denoted by a small triangle (e.g., TDCLK). An active low signal is indicated by a tilde preceding the signal name (e.g., ~RESET). A clock intended to activate logic on its rising edge (low- to-high transition) is called active low (e.g., ~RDCLK), while a clock intended to activate logic on its falling edge (high-to-low transition) is called active high (e.g., TDCLK). When a clock input is associated with a small circle, the input activates on a falling edge. If no circle is shown, the input activates on a rising edge. The 100-pin PQFP MDP hardware interface signals are shown Figure 2. The 100-pin PQFP MDP signal pin assignments are shown Figure 3 and are listed in Table 4. The MDP hardware interface signals are described in Table 5. The digital interface characteristics are defined in Table 6. The analog interface characteristics are defined Table 7. The power requirements are defined in Table 8. The absolute maximum ratings are defined in Table 9.
/RZ9ROWDJH9 .IOH[99ELV0RGHP'DWD3XPSV 53'53'DQG53' /G30/G27/G15/G14/G1B /G1C ~RLYA RINGD RIN TXA1 TXA2 TELIN/NC* TELOUT/NC* MICV/NC* MICM SPK SPKMD NOTES: 1. TOLERANCES AND RATINGS (UNLESS OTHERWISE SPECIFIED): RESISTOR VALUES IN OHMS; 5%, 1/8W CAPACITOR VALUES IN MICROFARADS; 10%, 20V 2. DENOTES ANALOG GROUND. 3. DENOTES DIGITAL GROUND. TELEPHONE LINE/ TELEPHONE/ AUDIO INTERFACE AGND AGND AGND YCLK XCLK RS0 RS1 RS2 RS3 RS4 ~CS ~WRITE ~READ IRQ ~WKRES ~RES2 ~RES1 MCU: ~WKRESOUT MCU EXTERNAL BUS MCU: IRQ MCLKIN MTXSIN MRXOUT MSTROBE MSCLK MCNTRLSIN SR1IO IA1CLK SA1CLK SR4IN SR4OUT CLKOUT SR3OUT SR3IN SA2CLK SR2CLK SR2IO VCNTRLSIN/NC* VSCLK/NC* VSTROBE/NC* VRXOUT/NC* VTXSIN/NC* VCLKIN/NC* SLEEPO IASLEEP 10 0.1 CER VREF 32 10 0.1 CER VC 33 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED AVDD VDD VDD VDD GND GND GND GND GND +3.3V 0.1 0.022 10 10µH AVAA28 GPO0 ~RDCLK TDCLK XTCLK TXD RXD ~RLSD ~RI SERIAL DTE INTERFACE NC NC NC NC NC NC NC NC NC NC NC NC NC PLLVDD PLLGND 100 MD218F4-HIS-100PQFP +5V RESERVED VGG MCU: ~RESET CLKIN NC
28.224 MHz CLOCK
- PINS ARE INTERNAL NO CONNECT (NC) ON NON-SP MODELS. NC +5V PROVIDE DIRECT CONNECTION OR FERRITE BEAD BETWEEN GND AND AGND, WHICHEVER ACHIEVES LOWEST NOISE FLOOR. 0.1 +3.3V (VDD) DAA FOR EXTERNAL VC USE 10µH10µH10µH FERRITE BEADS (70 OHM @ 100 MHZ TYPE WITH A MAX DC RESISTANCE OF 0.5 OHM AND A RATED CURRENT OF 200 mA). FB FB FB /G29/G4C/G4A/G58/G55/G48 /G15/G11 /G30/G27/G33 /G2B/G44/G55/G47/G5A/G44/G55/G48 /G2C/G51/G57/G48/G55/G49/G44/G46/G48 /G36/G4C/G4A/G51/G44/G4F/G56/G10/G14/G13/G13/G10/G33/G4C/G51 /G33/G34/G29/G33
53'53'DQG53' /RZ9ROWDJH9 .IOH[99ELV0RGHP'DWD3XPSV /G14/G13 /G30/G27/G15/G14/G1B MD212F5 PO-R6764-100P 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PLLGNDGNDPLLVDDRS1RS0D7 D6 D5 D4 D3 D2 D1 D0 NC CLKINVDDRESERVEDRESERVEDGP00GND TXA2VREF VC MICV/NC* RIN ~RES2MICM SPKMDAGNDAVDD MCNTRLSIN MCLKINMTXSINMSCLK MRXOUTMSTROBE ~RLYAAGNDGND VSTROBE/NC* IRQ RINGD ~RI RESERVED XCLK YCLK RESERVED RESERVED RESERVED VGG RESERVED SLEEPO VDD RXD RESERVED GND XTCLK VDD SR1IO RESERVED SR2IO SA2CLK RESERVED RESERVED IASLEEP VCNTRLSIN/NC* VCLKIN/NC* VTXSIN/NC* VSCLK/NC* VRXOUT/NC* RESERVED RS2 RS3 RS4 ~CS ~WRITE ~READ ~RDCLK ~WKRES SR2CLK ~RLSD TDCLK TXD RESERVED RESERVED GND ~RES1 SR4OUT SR3OUT SR4IN SR3IN CLKOUT SA1CLK IA1CLK AGND TELIN/NC* TELOUT/NC* AVAA SPKR TXA1 * NC on non-SP models. /G29/G4C/G4A/G58/G55/G48 /G16/G11 /G30/G27/G33 /G33/G4C/G51 /G36/G4C/G4A/G51/G44/G4F/G56 /G10 /G14/G13/G13/G10/G33/G4C/G51 /G33/G34/G29/G33
/RZ9ROWDJH9 .IOH[99ELV0RGHP'DWD3XPSV 53'53'DQG53' /G30/G27/G15/G14/G1B /G14/G14 /G37/G44/G45/G4F/G48 /G17/G11 /G30/G27/G33 /G33/G4C/G51 /G36/G4C/G4A/G51/G44/G4F/G56 /G10 /G14/G13/G13/G10/G33/G4C/G51 /G33/G34/G29/G33 Pin Signal Label I/O Type Interface3 Pin Signal Label I/O Type Interface
1 RESERVED NC 51 VRXOUT/NC* DI To SR3IN (21)
2 RS2 IA Host Parallel Interface 52 VSCLK/NC* DI To SR2CLK (10)
3 RS3 IA Host Parallel Interface 53 VTXSIN/NC* DI To SR3OUT (19)
4 RS4 IA Host Parallel Interface 54 VCLKIN/NC* DI To CLKOUT (22)
5 ~CS IA Host Parallel Interface 55 VCNTRLSIN/NC* DI To SR2IO (60) 6 ~WRITE IA Host Parallel Interface 56 IASLEEP DI To SLEEPO (69) 7 ~READ IA Host Parallel Interface 57 RESERVED NC 8 ~RDCLK OA DTE Serial Interface 58 RESERVED NC 9 ~WKRES IA MCU: READY/~WKRESOUT 59 SA2CLK DI To VSTROBE (50)
10 SR2CLK DI To VSCLK (52) 60 SR2IO DI To VCNTRLSIN (55)
11 ~RLSD OA DTE Serial Interface 61 RESERVED NC
12 TDCLK OA DTE Serial Interface 62 SR1IO DI To MCNTRLSIN (41)
13 TXD IA DTE Serial Interface 63 VDD PWR +3.3V
14 RESERVED NC 64 XTCLK IA DTE Serial Interface
15 RESERVED NC 65 GND GND DGND
16 GND GND DGND 66 RESERVED NC
17 ~RES1 PIF: ~RESET SIF: Reset circuit
67 RXD OA DTE Serial Interface
18 SR4OUT DI To MTXSIN (43) 68 VDD PWR +3.3V
19 SR3OUT DI To VTXSIN (53) 69 SLEEPO DI To IASLEEP (56)
20 SR4IN DI To MRXOUT (45) 70 RESERVED NC
21 SR3IN DI To VRXOUT (51) 71 VGG REF +5V
22 CLKOUT DI To MCLKIN (42) & VCLKIN
(54)
72 RESERVED NC
23 SA1CLK DI To MSTROBE (46) 73 RESERVED NC
24 IA1CLK DI To MSCLK (44) 74 RESERVED NC
25 AGND GND Analog Ground 75 YCLK OA NC
26 TELIN/NC* I(DA) Line/Audio Interface 76 XCLK OA NC
27 TELOUT/NC* O(DD) Line/Audio Interface 77 RESERVED NC
28 AVAA PWR +5VA 78 ~RI OA DTE Serial Interface
29 SPK O(DF) Line/Audio Interface 79 RINGD IA Line/Audio Interface
30 TXA1 O(DD) Line/Audio Interface 80 IRQ IA Host Parallel Interface
31 TXA2 O(DD) Line/Audio Interface 81 GND GND DGND
32 VREF REF VC through capacitors 82 GP00 DI To ~RDCLK (8)
33 VC REF DAA through FB; GND
83 RESERVED NC
34 MICV/NC* I(DA) Line/Audio Interface 84 RESERVED NC
35 RIN I(DA) Line/Audio Interface 85 VDD PWR +3.3V 36 ~RES2 PIF: ~RESET SIF: Reset circuit
86 CLKIN I Clock Circuit
37 MICM I(DA) Line/Audio Interface 87 NC NC
38 SPKMD OA Line/Audio Interface 88 D0 IA/OB Host Parallel Interface
39 AGND GND Analog Ground 89 D1 IA/OB Host Parallel Interface
40 AVDD PWR +3.3V 90 D2 IA/OB Host Parallel Interface
41 MCNTRLSIN DI To SR1IO (62) 91 D3 IA/OB Host Parallel Interface
42 MCLKIN DI To CLKOUT (22) 92 D4 IA/OB Host Parallel Interface
43 MTXSIN DI To SR4OUT (18) 93 D5 IA/OB Host Parallel Interface
44 MSCLK DI To IA1CLK (24) 94 D6 IA/OB Host Parallel Interface
45 MRXOUT DI To SR4IN (20) 95 D7 IA/OB Host Parallel Interface
46 MSTROBE DI To SA1CLK (23) 96 RS0 IA Host Parallel Interface
47 ~RLYA OD NC 97 RS1 IA Host Parallel Interface 48 AGND GND AGND 98 PLLVDD PLL To +3.3 (VDD) through 10 W and to DGND through 10 mF.
49 GND GND DGND 99 GND GND DGND
50 VSTROBE/NC* DI To SA2CLK (59) 100 PLLGND PLL DGND
Notes: 1. I/O types: IA, IB = Digital input; OA, OB = Digital output. I(DA) = Analog input; O(DD), O(DF) = Analog output. DI = Device interconnect. 2. NC = No external connection allowed (may have internal connection). 3. Interface Legend: MDP = Modem Data Pump DTE = Data Terminal Equipment PIF = Parallel host interface SIF = Serial DTE interface. * NC on non-SP models.
53'53'DQG53' /RZ9ROWDJH9 .IOH[99ELV0RGHP'DWD3XPSV /G14/G15 /G30/G27/G15/G14/G1B /G37/G44/G45/G4F/G48 /G18/G11 /G30/G27/G33 /G36/G4C/G4A/G51/G44/G4F /G27/G48/G49/G4C/G51/G4C/G57/G4C/G52/G51/G56 Label I/O Type Signal/Definition OVERHEAD SIGNALS CLKIN I Clock In. Connect to an external 28.224 MHz clock circuit. ~RES1, ~RES2 IA Reset. ~RESET low holds the MDP in the reset state. ~RESET going high releases the MDP from the reset state and initiates normal operation using power turn-on (default) values. ~RESET must be held low for at least 3 µs. The MDP is ready to use 400 ms after the low-to-high transition of ~RESET. ~RES1 and ~RES2 are typically connected to the MCU ~RESET input and to the host bus ~RESET (or RESET through an inverter) line (parallel host) or reset circuit (serial DTE interface) which resets both the MCU and MDP upon power turn-on. ~RES1 and ~RES2 have active internal pull-up resistors. ~WKRES IA Wake-up Reset. ~WKRES is connected internally to ~RESET but will not drive the MDP ~RESET pins. Asserting ~WKRES performs the same reset function as the MDP ~RESET and typically used by the MCU to wake up the MDP from SLEEP Mode when the MDP ~RESET lines cannot be asserted (because they are also connected to the MCU ~RESET input). For a serial DTE or parallel host MCU configuration, connect ~WKRES to the MCU ~WKRESOUT output. ~WKRES has an active internal pull-up resistor. VDD PWR +3.3V Digital Circuit Power Supply. Connect to +3.3V through digital circuit power supply filter. AVDD PWR +3.3V Analog Circuit Digital Power Supply. Connect to +3.3V through digital circuit power supply filter. AVAA PWR Analog Circuit Analog Power Supply. Connect to +5V through analog circuit power supply filter. VGG REF Input Reference Voltage. Reference voltage for +5V tolerant input pins. Connect to +5V. GND GND Digital Ground. Connect to digital ground. AGND GND Analog Ground. Connect to analog ground. XCLK OA X Clock. Output clock at 56.448 MHz (PLL disabled) or 63.5045 (PLL enabled), which runs during MDP Normal Mode and is turned off during Sleep Mode. YCLK OA Y Clock. Output clock at 28.224 MHz, which runs during MDP Normal Mode and is turned off during Sleep Mode. SYCLK OA System Clock. Output clock at 28.224 MHz, which runs during MDP Normal Mode and during Sleep Mode. PLLVDD PLL PLLVDD Connection. Connect to +3.3V (VDD) through 10 W and to DGND through 10 (+) mF. PLLGND PLL PLLGND Connection. Connect to DGND. PARALLEL HOST INTERFACE Address, data, control, and interrupt hardware interface signals allow MDP connection to an 8086-compatible microprocessor bus. With the addition of external logic, the interface can be made compatible with a wide variety of other microprocessors such as the 6502, 8086 or 68000. The microprocessor interface allows a microprocessor to change MDP configuration, read or write channel and diagnostic data, and supervise MDP operation by writing control bits and reading status bits. D0–D7 IA/OB Data Lines. Eight bidirectional data lines (D0–D7) provide parallel transfer of data between the host and the MDP. The most significant bit is D7. Data direction is controlled by the Read Enable and Write Enable signals. RS0–RS4 IA Register Select Lines. The five active high register select lines (RS0–RS4) address interface memory registers within the MDP interface memory. These lines are typically connected to the five least significant lines (A0–A4) of the address bus. The MDP decodes RS0 through RS4 to address one of 32 internal interface memory registers (00–1F). The most significant address bit is RS4, while the least significant address bit is RS0. The selected register can be read from or written into via the 8-bit parallel data bus (D0–D7). The most significant data bit is D7, while the least significant data bit is D0. ~CS IA Chip Select. ~CS selects the MDP for microprocessor bus operation. ~CS is typically generated by decoding host address bus lines. ~READ IA Read Enable. During a read cycle (~READ asserted), data from the selected interface memory register is gated onto the data bus by means of three-state drivers in the MDP. These drivers force the data lines high for a one bit, or low for a zero bit. When not being read, the three-state drivers assume their high-impedance (off) state. ~WRITE IA Write Enable. During a write cycle (~WRITE asserted), data from the data bus is copied into the selected MDP interface memory register, with high and low bus levels representing one and zero bit states, respectively. IRQ OA Interrupt Request. The MDP IRQ output may be connected to the host processor interrupt request input in order to interrupt host program execution for immediate MDP service. The IRQ output can be enabled in the MDP interface memory to indicate immediate change of conditions. The use of IRQ is optional depending upon MDP application. The IRQ output is driven by a TTL-compatible CMOS driver.
/RZ9ROWDJH9 .IOH[99ELV0RGHP'DWD3XPSV 53'53'DQG53' /G30/G27/G15/G14/G1B /G14/G16 /G37/G44/G45/G4F/G48 /G18/G11 /G30/G27/G33 /G36/G4C/G4A/G51/G44/G4F /G27/G48/G49/G4C/G51/G4C/G57/G4C/G52/G51/G56 /G0B/G26/G52/G51/G57/G0A/G47/G0C Label I/O Type Signal Name/Description DTE SERIAL INTERFACE Timing, data, control, and status signals provide a V.24-compatible serial interface. These signals are TTL compatible in order to drive the short wire lengths and circuits normally found within a printed circuit board, stand-alone modem enclosures, or equipment cabinets. For driving longer cables, these signals can be easily converted to EIA/RS-232-D voltage levels. TXD IA Transmitted Data. The MDP obtains serial data to be transmitted from the local DTE on the Transmitted Data (TXD) input. RXD OA Received Data. The MDP presents received serial data to the local DTE on the Received Data (RXD) output. ~RTS IA Request to Send. Activating ~RTS causes the MDP to transmit data on TXD when ~CTS becomes active. The ~RTS pin is logically ORed with the RTS bit. ~CTS OA Clear To Send. ~CTS active indicates to the local DTE that the MDP will transmit any data present on TXD. CTS response times from an active condition of RTS are shown in Table 3. ~RLSD OA Received Line Signal Detector. ~RLSD active indicates to the local DTE that energy above the receive level threshold is present on the receiver input, and that the energy is not a training sequence. One of four ~RLSD receive level threshold options can be selected (RTH bits). A minimum hysteresis action of 2 dB exists between the actual off-to-on and on-to-off transition levels. The threshold level and hysteresis action are measured with a modulated signal applied to the Receiver Analog (RXA) input. Note that performance may be degraded when the received signal level is less than -43 dBm. The ~RLSD on and off thresholds are host programmable in DSP RAM. activating ~DTR initiates the handshake sequence. The DATA bit must be set to complete the handshake. In V.21, V.23, or Bell 103 configuration, activating ~DTR causes the MDP to enter the data state provided that the DATA bit is a 1. If in answer mode, the MDP immediately sends answer tone. In these modes, if controlled carrier is enabled, carrier is controlled by RTS. During the data mode, deactivating ~DTR causes the transmitter and receiver to turn off and return to the idle state. The ~DTR input and the DTR control bit are logically ORed. ~DSR OA Data Set Ready. ~DSR ON indicates that the MDP is in the data transfer state. ~DSR OFF indicates that the DTE is to disregard all signals appearing on the interchange circuits except Ring Indicator (~RI). ~DSR is OFF when the MDP is in a test mode (i.e., local analog or remote digital loopback). The DSR status bit reflects the state of the ~DSR output. ~RI OA Ring Indicator. ~RI output follows the ringing signal present on the line with a low level (0 V) during the ON time, and a high level during the OFF time coincident with the ringing signal. The RI status bit reflects the state of the ~RI output. TDCLK OA Transmit Data Clock. The MDP outputs a synchronous Transmit Data Clock (TDCLK) for USRT timing. The TDCLK frequency is the data rate (±0.01%) with a duty cycle of 50±1%. The TDCLK source can be internal, external (input on XTCLK), or slave (to ~RDCLK) as selected by TXCLK bits in interface memory. XTCLK IA External Transmit Clock. In synchronous communication, an external transmit data clock can be connected to the MDP XTCLK input. The clock supplied at XTCLK must exhibit the same characteristics as TDCLK. The XTCLK input is then reflected at the TDCLK output. ~RDCLK OA Receive Data Clock. The MDP outputs a synchronous Receive Data Clock (~RDCLK) for USRT timing. The ~RDCLK frequency is the data rate (±0.01%) with a duty cycle of 50±1%. The ~RDCLK low-to-high transitions coincide with the center of the received data bits.
53'53'DQG53' /RZ9ROWDJH9 .IOH[99ELV0RGHP'DWD3XPSV /G14/G17 /G30/G27/G15/G14/G1B /G37/G44/G45/G4F/G48 /G18/G11 /G30/G27/G33 /G36/G4C/G4A/G51/G44/G4F /G27/G48/G49/G4C/G51/G4C/G57/G4C/G52/G51/G56 /G0B/G26/G52/G51/G57/G0A/G47/G0C Label I/O Type Signal Name/Description TELEPHONE LINE/TELEPHONE/AUDIO INTERFACE SIGNALS AND REFERENCE VOLTAGE TXA1, TXA2 O(DF) Transmit Analog 1 and 2 Output. The TXA1 and TXA2 outputs are differential outputs 180 degrees out of phase with each other. Each output can drive a 300 W load. Typically, TXA1 and TXA2 are connected to the telephone line interface or an optional external hybrid circuit. RIN I(DA) Receive Analog Input. RIN is a single-ended input with 70K W input impedance. Typically, RIN is connected to telephone line interface or an optional external hybrid circuit. NOTE: If not used, do not tie directly to ground; this input has a bias voltage of +2.5V (VAA = +5V). RINGD IA Ring Detect. The RINGD input is monitored for pulses in the range of 15 Hz to 68 Hz. The frequency detection range may be changed by the host in DSP RAM. The circuit driving RINGD should be a 4N35 optoisolator or equivalent. The circuit driving RINGD should not respond to momentary bursts of ringing less than 125 ms in duration, or less than 40 VRMS (15 Hz to 68 Hz) across TIP and RING. Detected ring signals are reflected on the ~RI output signal as well as the RI bit. ~RLYA (~OHRC, ~CALLID) OD Relay A Control. The ~RLYA open drain output can directly drive a reed relay coil with a minimum resistance of An external transistor can be used to drive heavier loads (e.g., electro-mechanical relays). ~RLYA is controlled by host setting/resetting of the RA bit. In a typical application, ~RLYA is connected to the normally open Off-Hook relay (~OHRC). In this case, ~RLYA active closes the relay to connect the MDP to the telephone line. Alternatively, in a typical application, ~RLYA is connected to the normally open Caller ID relay (~CALLID). When the MDP detects a Calling Number Delivery (CND) message, the ~RLYA output is asserted to close the Caller ID relay in order to AC couple the CND information to the MDP RIN input (without closing the off-hook relay and allowing loop current flow which would indicate an off-hook condition). ~RLYB (~TALK) OD Relay B Control. The ~RLYB open drain output can directly drive a reed relay coil with a minimum resistance of external transistor can be used to drive heavier loads (e.g., electro-mechanical relays). ~RLYB is controlled by host setting/resetting of the RB bit. In a typical application, ~RLYB is connected to the normally closed Talk/Data relay (~TALK). In this case, ~RLYB active opens the relay to disconnect the handset from the telephone line. MICM I(DA) Modem Microphone Input. MICM is a single-ended microphone input. The input impedance is > 70k W . NOTE: If not used, do not tie directly to ground; this input has a bias voltage of +2.5V (VAA = +5V). SPK O(DF) Speaker Analog Output. The SPK analog output can originate from one of five different sources: RIN, TELIN, MICM or MICV or from the MDP’s internal voice playback mode. The SPK on/off and three levels of attenuation are controlled by bits in DSP RAM. When the speaker is turned off, the SPK output is clamped to the voltage at the VC pin. The SPK output can drive an impedance as low as 300 ohms. In a typical application, the SPK output is an input to an external LM386 audio power amplifier. SPKMD OA Modem Speaker Digital Output. The SPKMD digital output reflects the received analog input signal digitized to TTL high or low level by an internal comparator to create a PC Card (PCMCIA)-compatible signal. VREF REF High Voltage Reference. Connect to VC through 10 µF (polarized, + terminal to VREF) and 0.1 µF (ceramic) in parallel. VC REF Low Voltage Reference. Connect to a ferrite bead and connect the other end of the ferrite bead to DGND through 10 µF (polarized, + terminal to VC) and 0.1 µF (ceramic) in parallel. MICV/NC* I(DA) Voice Microphone Input. MICV is a single-ended microphone input. Typically, MICV is connected to a microphone output for recording voice e.g., in a speakerphone application. NOTE: If not used, do not tie directly to ground; this input has a bias voltage of +2.5V (VAA = +5V). TELIN/NC* I(DA) Telephone Analog Input. TELIN is a single-ended input with 70K W input impedance. Typically, TELIN is connected to a telephone handset microphone circuit. NOTE: If not used, do not tie directly to ground; this input has a bias voltage of +2.5V (VAA = +5V). TELOUT/NC* O(DF) Telephone Analog Output. TELOUT is a single-ended output that can drive a 300 W load. Typically, TELOUT is connected to a telephone handset speaker circuit. MICBIAS REF Microphone Bias. Microphone bias reference voltage.
/RZ9ROWDJH9 .IOH[99ELV0RGHP'DWD3XPSV 53'53'DQG53' /G30/G27/G15/G14/G1B /G14/G18 /G37/G44/G45/G4F/G48 /G18/G11 /G30/G27/G33 /G36/G4C/G4A/G51/G44/G4F /G27/G48/G49/G4C/G51/G4C/G57/G4C/G52/G51/G56 /G0B/G26/G52/G51/G57/G0A/G47/G0C Label I/O Type Signal Name/Description MISCELLANEOUS RESERVED Reserved Function. May be connected to internal circuit. Leave open. MDP INTERCONNECT GP00 DI To ~RDCLK. SLEEPO DI To IASLEEP. IASLEEP DI To SLEEPO. MSCLK DI To IA1CLK. CLKOUT DI To MCLKIN & VCLKIN. SR1IO DI To MCNTRLSIN. SR3IN DI To VRXOUT. IA1CLK DI To MSCLK. SA1CLK DI To MSTROBE. SR4OUT DI To MTXSIN. MCLKIN DI To CLKOUT. VCLKIN/NC* DI To CLKOUT. MSTROBE DI To SA1CLK. VSTROBE/NC* DI To SA2CLK. MCNTRLSIN DI To SR1IO. VSCLK/NC* DI To SR2CLK. VCNTRLSIN/NC* DI To SR2IO. MRXOUT DI To SR4IN. VTXSIN/NC* DI To SR3OUT. VRXOUT/NC* DI To SR3IN. MTXSIN DI To SR4OUT. SR2IO DI To VCNTRLSIN. SR4IN DI To MRXOUT. SR2CLK DI To VSCLK. SA2CLK DI To VSTROBE. SR3OUT DI To VTXSIN. * NC on non-SP models. External interconnects as described can made for the NC pins on non-SP models in case SP models are ever substituted in the application design and SP support is required.
53'53'DQG53' /RZ9ROWDJH9 .IOH[99ELV0RGHP'DWD3XPSV /G14/G19 /G30/G27/G15/G14/G1B /G37/G44/G45/G4F/G48 /G19/G11 /G27/G4C/G4A/G4C/G57/G44/G4F /G28/G4F/G48/G46/G57/G55/G4C/G46/G44/G4F /G26/G4B/G44/G55/G44/G46/G57/G48/G55/G4C/G56/G57/G4C/G46/G56 Parameter Symbol Min. Typ. Max. Units Test Conditions1 Input High Voltage V IH Vdc Type IA 2.0 – V CC Input High Current I IH – – 40 µA Input Low Voltage V IL 0.3 0.8 VDC Input Low Current I IL – – 40 µA Input Leakage Current I IN – – ±100 µADC V IN = 0 to +3.3V, VCC = 3.6V Output High Voltage V OH –– V D C Type OA 2.4 – V CC ILOAD = – 100 µA Type OD ILOAD = 0 mA Output Low Voltage V OL VDC Type OA – – 0.4 I LOAD = 1.6 mA Type OD – – 0.75 I LOAD = 15 mA Three-State (Off) Current ITSI ±10 µADC V IN = 0.4 to VCC -1 /G37/G44/G45/G4F/G48 /G1A/G11 /G24/G51/G44/G4F/G52/G4A /G28/G4F/G48/G46/G57/G55/G4C/G46/G44/G4F /G26/G4B/G44/G55/G44/G46/G57/G48/G55/G4C/G56/G57/G4C/G46/G56 Signal Name Type Characteristic Value RIN, TELIN, I (DA) Input Impedance > 70K W MICM, MICV AC Input Voltage Range 1.1 VP-P Reference Voltage +2.5 VDC (VAA = +5V) TXA1, TXA2, O (DD) Minimum Load 300 W TELOUT Maximum Capacitive Load 0 µF Output Impedance 10 W AC Output Voltage Range 2.2 VP-P (VAA = +5V) (with reference to ground and a 600 W load) Reference Voltage +2.5 VDC (VAA = +5V) DC Offset Voltage ± 200 mV SPK O (DF) Minimum Load 300 W Maximum Capacitive Load 0.01 µF Output Impedance 10 W AC Output Voltage Range 2.2 VP-P (VAA = +5V) Reference Voltage +2.5 VDC (VAA = +5V) DC Offset Voltage ± 20 mV
/RZ9ROWDJH9 .IOH[99ELV0RGHP'DWD3XPSV 53'53'DQG53' /G30/G27/G15/G14/G1B /G14/G1A /G37/G44/G45/G4F/G48 /G1B/G11 /G26/G58/G55/G55/G48/G51/G57 /G44/G51/G47 /G33/G52/G5A/G48/G55 /G35/G48/G54/G58/G4C/G55/G48/G50/G48/G51/G57/G56 Mode Typical Current (mA) Maximum Current (mA) Typical Power (mW) Maximum Power (mW) Notes Normal Mode 85 90 280 325 f = 28.224 MHz Sleep Mode 53 — 175 — f = 28.224 MHz Notes: 1. Operating voltage: VDD = +3.3V ± 0.3V. 2. Test conditions: VDD = +3.3V for typical values; VDD = +3.6V for maximum values. 3. Input Ripple £ 0.1 Vpeak-peak. 4. f = Internal frequency. /G37/G44/G45/G4F/G48 /G1C/G11 /G24/G45/G56/G52/G4F/G58/G57/G48 /G30/G44/G5B/G4C/G50/G58/G50 /G35/G44/G57/G4C/G51/G4A/G56 Parameter Symbol Limits Units Supply Voltage V DD -0.5 to +4.0 V Input Voltage V IN V Except XTLI -0.5 to (VGG +0.5)* XTLI -0.5 to 3.9V Operating Temperature Range T A -0 to +70 °C Storage Temperature Range T STG -55 to +125 °C Analog Inputs V IN -0.3 to (VAA + 0.5) V Voltage Applied to Outputs in High Impedance (Off) State VHZ -0.5 to (VGG +0.5)* V DC Input Clamp Current I IK ±20 mA DC Output Clamp Current I OK ±20 mA Static Discharge Voltage (25°C) V ESD ±2500 V Latch-up Current (25°C) I TRIG ±400 mA
53'53'DQG53' /RZ9ROWDJH9 .IOH[99ELV0RGHP'DWD3XPSV /G3A/G52/G55/G4F/G47/G5A/G4C/G47/G48 /G2B/G48/G44/G47/G54/G58/G44/G55/G57/G48/G55/G56 /G17/G16/G14/G14 /G2D/G44/G50/G45/G52/G55/G48/G48 /G35/G52/G44/G47/G0F /G33/G11/G32/G11 /G25/G52/G5B /G26 /G31/G48/G5A/G53/G52/G55/G57 /G25/G48/G44/G46/G4B/G0F /G26/G24 /G1C/G15/G19/G18/G1B/G10/G1B/G1C/G13/G15 /G33/G4B/G52/G51/G48/G1D /G0B/G1C/G17/G1C/G0C /G17/G1B/G16/G10/G17/G19/G13/G13 /G29/G44/G5B/G1D /G0B/G1C/G17/G1C/G0C /G17/G1B/G16/G10/G19/G16/G1A/G18 /G29/G52/G55 /G50/G52/G55/G48 /G4C/G51/G49/G52/G55/G50/G44/G57/G4C/G52/G51/G1D /G26/G44/G4F/G4F /G14/G10/G1B/G13/G13/G10/G1B/G18/G17/G10/G1B/G13/G1C/G1C /G2C/G51/G57/G48/G55/G51/G44/G57/G4C/G52/G51/G44/G4F /G4C/G51/G49/G52/G55/G50/G44/G57/G4C/G52/G51/G1D /G26/G44/G4F/G4F /G14/G10/G1C/G17/G1C/G10/G17/G1B/G16/G10/G19/G1C/G1C/G19 /G38/G35/G2F /G24/G47/G47/G55/G48/G56/G56/G1D /G4B/G57/G57/G53/G1D/G12/G12/G5A/G5A/G5A/G11/G46/G52/G51/G48/G5B/G44/G51/G57/G11/G46/G52/G50 /G28/G10/G30/G44/G4C/G4F /G24/G47/G47/G55/G48/G56/G56/G1D /G4F/G4C/G57/G48/G55/G44/G57/G58/G55/G48/G23/G46/G52/G51/G48/G5B/G44/G51/G57/G11/G46/G52/G50 /G35/G28/G2A/G2C/G32/G31/G24/G2F /G36/G24/G2F/G28/G36 /G32/G29/G29/G2C/G26/G28/G36 /G38/G36 /G31/G52/G55/G57/G4B/G5A/G48/G56/G57/G12/G33/G44/G46/G4C/G49/G4C/G46 /G31/G52/G55/G57/G4B/G5A/G48/G56/G57 /G16/G19/G13/G13 /G33/G55/G58/G51/G48/G55/G4C/G47/G4A/G48 /G24/G59/G48/G51/G58/G48 /G36/G58/G4C/G57/G48 /G14/G13/G13 /G36/G44/G51/G57/G44 /G26/G4F/G44/G55/G44/G0F /G26/G24 /G1C/G18/G13/G18/G14 /G33/G4B/G52/G51/G48/G1D /G0B/G17/G13/G1B/G0C /G15/G17/G1C/G10/G1C/G19/G1C/G19 /G29/G44/G5B/G1D /G0B/G17/G13/G1B/G0C /G15/G17/G1C/G10/G1A/G14/G14/G16 /G38/G36 /G2F/G52/G56 /G24/G51/G4A/G48/G4F/G48/G56 /G14/G13/G13/G13 /G25/G58/G56/G4C/G51/G48/G56/G56 /G26/G48/G51/G57/G48/G55 /G26/G4C/G55/G46/G4F/G48 /G36/G58/G4C/G57/G48 /G15/G14/G18 /G37/G4B/G52/G58/G56/G44/G51/G47 /G32/G44/G4E/G56/G0F /G26/G24 /G1C/G14/G16/G15/G13 /G33/G4B/G52/G51/G48/G1D /G0B/G1B/G13/G18/G0C /G16/G1A/G19/G10/G13/G18/G18/G1C /G29/G44/G5B/G1D /G0B/G1B/G13/G18/G0C /G16/G1A/G19/G10/G1B/G14/G1B/G13 /G38/G36 /G36/G52/G58/G57/G4B/G5A/G48/G56/G57 /G17/G16/G18/G13 /G39/G52/G51 /G2E/G44/G55/G50/G44/G51 /G24/G59/G48/G11 /G36/G58/G4C/G57/G48 /G17/G13/G13 /G31/G48/G5A/G53/G52/G55/G57 /G25/G48/G44/G46/G4B/G0F /G26/G24 /G1C/G15/G19/G19/G13 /G33/G4B/G52/G51/G48/G1D /G0B/G1C/G17/G1C/G0C /G17/G1B/G16/G10/G1C/G14/G14/G1C /G29/G44/G5B/G1D /G0B/G1C/G17/G1C/G0C /G17/G1B/G16/G10/G1C/G13/G1C/G13 /G38/G36 /G31/G52/G55/G57/G4B /G26/G48/G51/G57/G55/G44/G4F /G37/G5A/G52 /G33/G4C/G48/G55/G46/G48 /G33/G4F/G44/G46/G48 /G26/G4B/G44/G51/G46/G48/G4F/G4F/G52/G55/G5C /G33/G44/G55/G4E /G36/G58/G4C/G57/G48 /G1B/G14/G13 /G2C/G57/G44/G56/G46/G44/G0F /G2C/G2F /G19/G13/G14/G17/G16 /G33/G4B/G52/G51/G48/G1D /G0B/G19/G16/G13/G0C /G1A/G1A/G16/G10/G16/G17/G18/G17 /G29/G44/G5B/G1D /G0B/G19/G16/G13/G0C /G1A/G1A/G16/G10/G16/G1C/G13/G1A /G38/G36 /G36/G52/G58/G57/G4B /G26/G48/G51/G57/G55/G44/G4F /G14/G1A/G16/G13/G17 /G33/G55/G48/G56/G57/G52/G51 /G35/G52/G44/G47 /G36/G58/G4C/G57/G48 /G1C/G1A/G13 /G27/G44/G4F/G4F/G44/G56/G0F /G37/G3B /G1A/G18/G15/G18/G15 /G33/G4B/G52/G51/G48/G1D /G0B/G1C/G1A/G15/G0C /G1A/G16/G16/G10/G13/G1A/G15/G16 /G29/G44/G5B/G1D /G0B/G1C/G1A/G15/G0C /G17/G13/G1A/G10/G13/G19/G16/G1C /G38/G36 /G31/G52/G55/G57/G4B/G48/G44/G56/G57 /G15/G16/G1C /G2F/G4C/G57/G57/G4F/G48/G57/G52/G51 /G35/G52/G44/G47 /G36/G58/G4C/G57/G48 /G17/G24 /G3A/G48/G56/G57/G49/G52/G55/G47/G0F /G30/G24 /G13/G14/G1B/G1B/G19 /G33/G4B/G52/G51/G48/G1D /G0B/G18/G13/G1B/G0C /G19/G1C/G15/G10/G1A/G19/G19/G13 /G29/G44/G5B/G1D /G0B/G18/G13/G1B/G0C /G19/G1C/G15/G10/G1B/G14/G1B/G18 /G38/G36 /G36/G52/G58/G57/G4B/G48/G44/G56/G57 /G16/G18/G13/G13 /G33/G44/G55/G4E/G5A/G44/G5C /G2F/G44/G51/G48/G0F /G36/G58/G4C/G57/G48 /G17/G14/G18 /G31/G52/G55/G46/G55/G52/G56/G56/G0F /G2A/G24 /G16/G13/G13/G1C/G15 /G33/G4B/G52/G51/G48/G1D /G0B/G1A/G1A/G13/G0C /G15/G17/G19/G10/G1B/G15/G1B/G16 /G29/G44/G5B/G1D /G0B/G1A/G1A/G13/G0C /G15/G17/G19/G10/G13/G13/G14/G1B /G38/G36 /G29/G4F/G52/G55/G4C/G47/G44/G12/G36/G52/G58/G57/G4B /G24/G50/G48/G55/G4C/G46/G44 /G32/G51/G48 /G33/G55/G48/G56/G57/G4C/G4A/G48 /G33/G4F/G44/G46/G48 /G15/G19/G13/G13 /G30/G46/G26/G52/G55/G50/G4C/G46/G4E /G27/G55/G4C/G59/G48 /G36/G58/G4C/G57/G48 /G16/G18/G13 /G26/G4F/G48/G44/G55/G5A/G44/G57/G48/G55/G0F /G29/G2F /G16/G16/G1A/G18/G1C /G33/G4B/G52/G51/G48/G1D /G0B/G1B/G14/G16/G0C /G1A/G1C/G1C/G10/G1B/G17/G13/G19 /G29/G44/G5B/G1D /G0B/G1B/G14/G16/G0C /G1A/G1C/G1C/G10/G1B/G16/G13/G19 /G38/G36 /G30/G4C/G47/G10/G24/G57/G4F/G44/G51/G57/G4C/G46 /G33/G55/G4C/G51/G46/G48/G57/G52/G51 /G33/G4C/G4E/G48 /G26/G52/G55/G53/G52/G55/G44/G57/G48 /G26/G48/G51/G57/G48/G55 /G1C/G1C/G16 /G2F/G48/G51/G52/G5B /G27/G55/G4C/G59/G48/G0F /G36/G58/G4C/G57/G48 /G15/G13/G13 /G2F/G44/G5A/G55/G48/G51/G46/G48/G59/G4C/G4F/G4F/G48/G0F /G31/G2D /G13/G1B/G19/G17/G1B /G33/G4B/G52/G51/G48/G1D /G0B/G19/G13/G1C/G0C /G15/G14/G1C/G10/G1A/G17/G19/G15 /G29/G44/G5B/G1D /G0B/G19/G13/G1C/G0C /G1B/G1C/G18/G10/G15/G19/G19/G19 /G28/G58/G55/G52/G53/G48/G44/G51 /G2B/G48/G44/G47/G54/G58/G44/G55/G57/G48/G55/G56 /G2F/G48/G56 /G37/G44/G4C/G56/G56/G52/G58/G51/G4C/G48/G55/G48/G56 /G25/G14 /G14/G19/G1B/G13 /G35/G52/G58/G57/G48 /G47/G48/G56 /G27/G52/G4F/G4C/G51/G48/G56 /G25/G33 /G15/G1B/G16 /G13/G19/G1C/G13/G18 /G36/G52/G53/G4B/G4C/G44 /G24/G51/G57/G4C/G53/G52/G4F/G4C/G56 /G26/G48/G47/G48/G5B /G29/G55/G44/G51/G46/G48 /G33/G4B/G52/G51/G48/G1D /G0B/G16/G16/G0C /G17 /G1C/G16 /G13/G13 /G16/G16 /G16/G18 /G29/G44/G5B/G1D /G0B/G16/G16/G0C /G17 /G1C/G16 /G13/G13 /G16/G16 /G13/G16 /G28/G58/G55/G52/G53/G48 /G26/G48/G51/G57/G55/G44/G4F /G33/G44/G58/G4F/G10/G2A/G48/G55/G4B/G44/G55/G47/G57/G10/G24/G4F/G4F/G48/G48 /G18/G13 /G44 /G1B/G14/G15/G17/G18 /G30/G81/G51/G46/G4B/G48/G51 /G2A/G48/G55/G50/G44/G51/G5C /G33/G4B/G52/G51/G48/G1D /G0B/G17/G1C/G10/G1B/G1C/G0C /G1B/G15/G1C/G10/G14/G16/G15/G13 /G29/G44/G5B/G1D /G0B/G17/G1C/G10/G1B/G1C/G0C /G1B/G16/G17/G10/G15/G1A/G16/G17 /G28/G58/G55/G52/G53/G48 /G30/G48/G47/G4C/G57/G48/G55/G55/G44/G51/G48/G44/G51 /G39/G4C/G44 /G2A/G11 /G27/G4C /G39/G4C/G57/G57/G52/G55/G4C/G52/G0F /G14 /G15/G13/G13/G14/G1A /G30/G44/G5D/G5D/G52 /G27/G4C /G35/G4B/G52 /G0B/G30/G2C/G0C /G2C/G57/G44/G4F/G5C /G33/G4B/G52/G51/G48/G1D /G0B/G16/G1C /G15/G0C /G1C/G16/G14/G1A/G1C/G1C/G14/G14 /G29/G44/G5B /G0B/G16/G1C /G15/G0C /G1C/G16/G14/G1A/G1C/G1C/G14/G16 /G28/G58/G55/G52/G53/G48 /G31/G52/G55/G57/G4B /G25/G48/G55/G4E/G56/G4B/G4C/G55/G48 /G26/G52/G58/G55/G57 /G3A/G48/G56/G57/G48/G55/G51 /G35/G52/G44/G47 /G25/G55/G44/G46/G4E/G51/G48/G4F/G4F /G25/G48/G55/G4E/G56/G4B/G4C/G55/G48 /G35/G2A/G14/G15 /G14/G35/G28 /G28/G51/G4A/G4F/G44/G51/G47 /G33/G4B/G52/G51/G48/G1D /G17/G17 /G0B/G13/G0C /G14/G16/G17/G17 /G17/G1B/G19/G17/G17/G17 /G29/G44/G5B/G1D /G17/G17 /G0B/G13/G0C /G14/G16/G17/G17 /G17/G1B/G19/G18/G18/G18 /G28/G58/G55/G52/G53/G48 /G31/G52/G55/G57/G4B /G0B/G36/G44/G57/G48/G4F/G4F/G4C/G57/G48/G0C /G14/G14 /G2A/G44/G4F/G4A/G44/G4F/G48/G5C /G2B/G44/G53/G4F/G44/G47/G44 /G36/G57/G55/G48/G48/G57 /G33/G11/G32/G11 /G25/G52/G5B /G14/G15/G19/G19/G13 /G2B/G48/G55/G5D/G4F/G4C/G44 /G17/G19/G1A/G16/G16 /G2C/G56/G55/G44/G48/G4F /G33/G4B/G52/G51/G48/G1D /G0B/G1C/G1A/G15/G0C /G1C /G1C/G18/G15/G17/G13/G13/G13 /G29/G44/G5B/G1D /G0B/G1C/G1A/G15/G0C /G1C /G1C/G18/G1A/G16/G1A/G16/G15 /G28/G58/G55/G52/G53/G48 /G36/G52/G58/G57/G4B /G37/G52/G58/G55 /G2A/G24/G31 /G26/G48/G47/G48/G5B /G14/G16 /G1C/G15/G13/G1B/G15 /G33/G44/G55/G4C/G56 /G2F/G44 /G27/G70/G49/G48/G51/G56/G48 /G15 /G29/G55/G44/G51/G46/G48 /G33/G4B/G52/G51/G48/G1D /G0B/G16/G16/G0C /G14 /G17/G1C /G13/G19 /G16/G1C /G1B/G13 /G29/G44/G5B/G1D /G0B/G16/G16/G0C /G14 /G17/G1C /G13/G19 /G16/G1C /G1C/G13 /G24/G33/G24/G26 /G2B/G48/G44/G47/G54/G58/G44/G55/G57/G48/G55/G56 /G14 /G2E/G4C/G50 /G36/G48/G51/G4A /G33/G55/G52/G50/G48/G51/G44/G47/G48 /G06/G13/G1C/G10/G13/G14 /G28/G44/G56/G57 /G37/G52/G5A/G48/G55 /G2A/G55/G48/G44/G57 /G3A/G52/G55/G4F/G47 /G26/G4C/G57/G5C /G36/G4C/G51/G4A/G44/G53/G52/G55/G48 /G15/G16/G1A/G1C/G1C/G17 /G33/G4B/G52/G51/G48/G1D /G0B/G19/G18/G0C /G1A/G16/G1A/G10/G1A/G16/G18/G18 /G29/G44/G5B/G1D /G0B/G19/G18/G0C /G1A/G16/G1A/G10/G1C/G13/G1A/G1A /G24/G58/G56/G57/G55/G44/G4F/G4C/G44 /G36/G58/G4C/G57/G48 /G19/G13/G16/G0F /G18/G14 /G35/G44/G5A/G56/G52/G51 /G36/G57/G55/G48/G48/G57 /G28/G53/G53/G4C/G51/G4A/G0F /G31/G36/G3A /G15/G14/G15/G14 /G24/G58/G56/G57/G55/G44/G4F/G4C/G44 /G33/G4B/G52/G51/G48/G1D /G0B/G19/G14/G10/G15/G0C /G1C/G1B/G19/G1C /G17/G13/G1B/G1B /G29/G44/G5B/G1D /G0B/G19/G14/G10/G15/G0C /G1C/G1B/G19/G1C /G17/G13/G1A/G1A /G26/G4B/G4C/G51/G44 /G36/G4B/G44/G51/G4A/G4B/G44/G4C /G35/G48/G53/G55/G48/G56/G48/G51/G57/G44/G57/G4C/G59/G48 /G32/G49/G49/G4C/G46/G48 /G2F/G37 /G36/G54/G58/G44/G55/G48 /G25/G58/G4C/G4F/G47/G4C/G51/G4A/G0F /G36/G58/G4C/G57/G48 /G16/G13/G13/G15 /G18/G13/G13 /G26/G4B/G48/G51/G4A/G47/G58 /G31/G52/G55/G57/G4B /G35/G52/G44/G47 /G36/G4B/G44/G51/G4A/G4B/G44/G4C /G15/G13/G13/G13/G13/G16 /G33/G11/G35/G11/G26/G11 /G33/G4B/G52/G51/G48/G1D /G1B/G19/G10/G15/G14/G10/G19/G16/G19/G14/G10/G15/G18/G14/G18 /G29/G44/G5B/G1D /G1B/G19/G10/G15/G14/G10/G19/G16/G19/G14/G10/G15/G18/G14/G19 /G2B/G52/G51/G4A /G2E/G52/G51/G4A /G14/G16/G57/G4B /G29/G4F/G52/G52/G55/G0F /G36/G58/G4C/G57/G48/G56 /G1B/G10/G14/G13/G0F /G2B/G44/G55/G45/G52/G58/G55 /G26/G48/G51/G57/G55/G48 /G15/G18 /G2B/G44/G55/G45/G52/G58/G55 /G35/G52/G44/G47 /G3A/G44/G51/G46/G4B/G44/G4C/G0F /G2B/G52/G51/G4A /G2E/G52/G51/G4A /G33/G4B/G52/G51/G48/G1D /G0B/G1B/G18/G15/G0C /G15 /G1B/G15/G1A/G10/G13/G14/G1B/G14 /G29/G44/G5B/G1D /G0B/G1B/G18/G15/G0C /G15 /G1B/G15/G1A/G10/G19/G17/G1B/G1B /G2C/G51/G47/G4C/G44 /G35/G48/G4A/G4C/G52/G51/G44/G4F /G32/G49/G49/G4C/G46/G48 /G10 /G36/G52/G58/G57/G4B /G24/G56/G4C/G44 /G26/G44/G53/G4C/G57/G44/G4F /G37/G55/G58/G56/G57 /G2B/G52/G58/G56/G48 /G17/G1A /G26/G52/G50/G50/G58/G51/G4C/G57/G5C /G26/G48/G51/G57/G55/G48 /G29/G55/G4C/G48/G51/G47/G56 /G26/G52/G4F/G52/G51/G5C /G31/G48/G5A /G27/G48/G4F/G4B/G4C /G10 /G14/G14/G13 /G13/G19/G18 /G2C/G51/G47/G4C/G44 /G33/G4B/G52/G51/G48/G1D /G0B/G1C/G14/G10/G14/G14/G0C /G19/G1C/G15/G10/G17/G1A/G1B/G13 /G29/G44/G5B/G1D /G0B/G1C/G14/G10/G14/G14/G0C /G19/G1C/G15/G10/G17/G1A/G14/G15 /G2E/G52/G55/G48/G44 /G35/G52/G52/G50 /G31/G52/G11 /G14/G18/G13/G1B /G2E/G52/G55/G48/G44 /G37/G48/G5B/G57/G4C/G4F/G48 /G26/G48/G51/G57/G55/G48 /G25/G58/G4C/G4F/G47/G4C/G51/G4A /G1C/G17/G17/G10/G16/G14/G0F /G27/G44/G48/G46/G4B/G4C/G10/G16/G47/G52/G51/G4A /G2E/G44/G51/G4A/G51/G44/G50 /G33/G11/G32/G11 /G25/G52/G5B /G15/G13/G16/G1A /G2E/G44/G51/G4A/G51/G44/G50/G10/G4E/G58 /G36/G48/G52/G58/G4F /G2E/G52/G55/G48/G44 /G33/G4B/G52/G51/G48/G1D /G0B/G1B/G15/G10/G15/G0C /G18/G19/G18/G10/G15/G1B/G1B/G13 /G29/G44/G5B/G1D /G0B/G1B/G15/G10/G15/G0C /G18/G19/G18/G10/G14/G17/G17/G13 /G37/G44/G4C/G5A/G44/G51 /G2B/G48/G44/G47/G54/G58/G44/G55/G57/G48/G55/G56 /G35/G52/G52/G50 /G15/G1B/G13/G1B /G2C/G51/G57/G48/G55/G51/G44/G57/G4C/G52/G51/G44/G4F /G37/G55/G44/G47/G48 /G25/G4F/G47/G4A/G11 /G16/G16/G16/G0F /G2E/G48/G48/G4F/G58/G51/G4A /G35/G52/G44/G47/G0F /G36/G48/G46/G57/G4C/G52/G51 /G2C /G37/G44/G4C/G53/G48/G4C/G0F /G37/G44/G4C/G5A/G44/G51 /G14/G13/G18/G17/G1B /G35/G32/G26 /G33/G4B/G52/G51/G48/G1D /G0B/G1B/G1B/G19/G10/G15/G0C /G15/G1A/G15/G13/G10/G13/G15/G1B/G15 /G29/G44/G5B/G1D /G0B/G1B/G1B/G19/G10/G15/G0C /G15/G1A/G18/G1A/G10/G19/G1A/G19/G13 /G2D/G44/G53/G44/G51 /G2B/G48/G44/G47/G54/G58/G44/G55/G57/G48/G55/G56 /G36/G4B/G4C/G50/G52/G50/G52/G57/G52 /G25/G4F/G47/G4A/G11 /G14/G10/G17/G19/G10/G16 /G2B/G44/G57/G56/G58/G47/G44/G4C/G0F /G36/G4B/G4C/G45/G58/G5C/G44/G10/G4E/G58 /G37/G52/G4E/G5C/G52/G0F /G14/G18/G14 /G2D/G44/G53/G44/G51 /G33/G4B/G52/G51/G48/G1D /G0B/G1B/G14/G10/G16/G0C /G18/G16/G1A/G14 /G14/G18/G15/G13 /G29/G44/G5B/G1D /G0B/G1B/G14/G10/G16/G0C /G18/G16/G1A/G14 /G14/G18/G13/G14 /G36/G32/G38/G27/G1C/G1B/G14/G15/G14/G17