RMDA20420 FAIRCHILD | Alldatasheet
Document overview
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Technical content
Features
- Wideband 20–42GHz operation
- 22dB small signal gain (typ.)
- 23dBm saturated power output (typ.)
- Matched to 50 Ω
- Optional bonding configuration for multiplier applications
- Chip Size 1.720mm x 0.760mm Absolute Ratings Symbol Parameter Ratings Units Vd Positive DC Voltage (+3.5V Typical) +5 V Vg Negative DC Voltage -2 V Vdg Simultaneous (Vd - Vg) +7 V Id Positive DC Current 600 mA Pin RF Input Power (from 50 Ω source) 15 dBm Tc Operating Baseplate Temperature -40 to +85 °C T STG Storage Temperature Range -55 to +125 °C R JC Thermal Resistance (Channel to Backside) 57 °C/W Device
©2004 Fairchild Semiconductor Corporation RMDA20420 Rev. D RMDA20420
Electrical Characteristics
Notes: 1. Operated at 25°C, 50 Ω system, Vd = +3.5V, quiescent current (Idq) = 350mA. 2. Typical range of the negative gate voltage is -0.9 to -0.15V to set typical Idq of 350mA. 3. Production measurements for small signal gain are made over a frequency range of 20 to 40GHz. 4. Saturated power measurements are not 100% tested, but guaranteed by design. Figure 1. Functional Block Diagram
Figure 4. Recommended Assembly and Bonding Diagram
5 MIL THICK
- Die-attach with 80Au/20Sn.
- Use 0.003" x 0.0005" gold ribbon for bonding.
- RF input and output bonds should be less than 0.015" long with stress relief.
- For currents > 370 mA connect all drain pads (Vd1, Vd3, & Vd4) to the 100 pF capacitor.
- Back of chip is DC and RF ground.
- Do not use Vd2 pad for drain bias connection.
2 MIL GAP
(iii) Turn down and off gate bias voltage (Vg).
©2004 Fairchild Semiconductor Corporation RMDA20420 Rev. D RMDA20420
Application Information
CAUTION: THIS IS AN ESD SENSITIVE DEVICE Chip carrier material should be selected to have GaAs compatible thermal coefficient of expansion and high thermal conductivity such as copper molybdenum or copper tungsten. The chip carrier should be machined, finished flat, plated with gold over nickel and should be capable of withstanding 325°C for 15 minutes. Die attachment for power devices should utilize Gold/Tin (80/20) eutectic alloy solder and should avoid hydrogen environment for PHEMT devices. Note that the backside of the chip is gold plated and is used as RF and DC Ground. These GaAs devices should be handled with care and stored in dry nitrogen environment to prevent contamination of bonding surfaces. These are ESD sensitive devices and should be handled with appropriate precaution including the use of wrist-grounding straps. All die attach and wire/ribbon bond equipment must be well grounded to prevent static discharges through the device. Recommended wire bonding uses 3 mils wide and 0.5 mil thick gold ribbon with lengths as short as practical allowing for appropriate stress relief. The RF input and output bonds should be typically 0.012" long corresponding to a typical 2 mil gap between the chip and the substrate material.
©2004 Fairchild Semiconductor Corporation RMDA20420 Rev. D RMDA20420 Performance Data Normal Amplifier Configuration -10 -15 -20 -25 -30 -35 -40 -10 -20 -30 -40 -50 -60 01 0 2 0 3 0 4 0 5 0 FREQUENCY (GHz) 01 0 2 0 3 0 4 0 5 0 FREQUENCY (GHz) 01 0 2 0 3 0 4 0 5 0 FREQUENCY (GHz) 01 0 2 0 3 0 4 0 5 0 FREQUENCY (GHz) 01 0 2 0 3 0 4 0 5 0 FREQUENCY (GHz) FREQUENCY (GHz) Typical SS Gain vs. Frequency vs. Supply Current Bias Vd = 3.5 Typical Output Power @ 1dB Compression Bias Vd = 3.5V, Id = 350mA Typical Input Return Loss vs. Frequency Bias Vd = 3.5V, Id = 350mA Typical SS Gain vs. Frequency vs. Supply Voltage Supply Current = 350mA Typical SS Gain vs. Frequency vs. Base Plate Temperature Bias Vd = 3.5V, Id = 350mA Typical Output Return Loss vs. Frequency Bias Vd = 3.5V, Id = 350mA (dB) 200mA 300mA 350mA 400mA 20 22 24 26 28 30 32 34 36 38 40 42 P1dB (dBm) (dB)(dB) S21 (dB) -10 -15 -20 -25 -30 -35 (dB) -10 -20 -30 -40 -10 -20 -30 Vds = 5.0 90 C 20 C -40 CVds = 3.5Vds = 2.0
©2004 Fairchild Semiconductor Corporation RMDA20420 Rev. D RMDA20420 Performance Data (Continued) Normal Amplifier Configuration 20 22 24 26 28 30 32 34 36 38 40 FREQUENCY (GHz) 20 22 24 26 28 30 32 34 36 38 40 FREQUENCY (GHz) Noise Figure vs. Frequency vs. Supply Current Bias Vd = 3.5 Volts Noise Figure vs. Frequency vs. Supply Voltage Supply Current = 200mA NOISE FIGURE (dB) NOISE FIGURE (dB) Idq=100 mA Idq=350 mA Idq=200 mA Vd=5.0 Vd=4.5 Vd=3.5 Vd=2.0 15 17 19 21 23 OUTPUT POWER (dBm) GAIN (dB) 12% 16% 20% PAE (%) PAE PAE Gain Gain Gain Compression and PAE vs. Output Power Frequency = 40 GHz, Bias Vd = 3.5V, Id = 350mA 15 17 19 21 23 OUTPUT POWER (dBm) GAIN (dB) 12% 16% 20% PAE (%) Gain Compression and PAE vs. Output Power Frequency = 30 GHz, Bias Vd = 3.5V, Id = 350mA
©2004 Fairchild Semiconductor Corporation RMDA20420 Rev. D RMDA20420 The RMDA20420 can be used as an even harmonic multiplier or as an odd harmonic multiplier depending on the type of DC biasing arrangement being used. Optimum DC bias is applied to peak the desired harmonic which falls into the 20 to 42GHz passband. The following application information will detail the configuration and procedure for using the RMDA20420 as an even harmonic multiplier and as an odd harmonic multiplier. Typical measured data is provided at selected frequencies within the passband with the RMDA20420 configured as a doubler and as a tripler. Multiplier Operation The RMDA20420 is a four stage general purpose MMIC amplifier covering the 20-42GHz passband. The amplifier has a steep gain roll off at the band edges and the input return loss of the amplifier is better than 10dB from 42GHz down to DC. Any multiplier harmonics, which fall in the passband, will get amplified and any harmonics that fall below the passband will get suppressed. A deliberate design feature that makes the RMDA20420 an effective multiplier is the ability to independently bias the first stage. This feature allows freedom to determine the optimum DC bias condition required to peak the desired harmonic and suppressing the unwanted harmonics. Optimum DC bias conditions depend largely on factors such as fundamental frequency, desired harmonic frequency, input power level, output power level and suppression requirements. Test Set Up The basic test set uses a source to provide the input signal at the desired frequency and power level. The DUT was biased either as an even harmonic or odd harmonic operation and the output was observed on a spectrum analyzer. The power of the harmonics was measured using the spectrum analyzer with all the cable losses accounted. Figure 5 shows the basic test set used. Figure 5. Basic Test Set Up remaining stages of the amplifier. a linear amplifier. As an example, the RMDA20420 was evaluated as a doubler. three stages. Vg2 was adjusted until Idq = 330mA.
Figure 9. Measured Tripler Performance.
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