RM46L450PGET

RM46L450 TI1 | Alldatasheet

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 RM46Lx5016/32-BitRISCFlashMicrocontroller

1 RM46Lx50 16/32-BitRISC FlashMicrocontroller

1.1 Features

• High-PerformanceMicrocontrollerforSafety • Two High-End Timer Modules (N2HET) CriticalApplications – N2HET1: 32 programmable channels – Dual CPUs runninginlockstep – N2HET2: 18 programmable channels – ECC on flashand RAM interfaces – 160 Word InstructionRAM withparity – Built-InSelfTestforCPU and on-chipRAMs protectioneach – ErrorSignalingModule withErrorPin – Each includesHardware Angle Generator – Voltageand Clock Monitoring – DedicatedTransferUnits(HTU) on N2HETs
• ARM ® Cortex™ – R4F 32-bitRISC CPU • Two 10/12-bitMulti-BufferedADC Modules – 1.66DMIPS/MHz with8-stagepipeline – ADC1: 24 channels – FPU withSingle/DoublePrecision – ADC2: 16 channels – 12-RegionMemory ProtectionUnit – 16 shared channels – Open Architecturewith3rd PartySupport – 64 resultbufferswithparityprotectioneach
• OperatingConditions • MultipleCommunication Interfaces – 200MHz System Clock – 10/100Mbps EthernetMAC (EMAC) – Core Supply Voltage(VCC):1.14V-1.32V • IEEE 802.3compliant(3.3V-I/Oonly) – I/OSupply Voltage(VCCIO):3.0V-3.6V • Supports MII,RMII and MDIO
• IntegratedMemory – USB (revision2.0full-speed) – Up to1.25MB Program FlashwithECC • 2-portUSB Specification,revision2.0- compatiblehost controller,based on the– Up to192KB RAM withECC OHCI SpecificationforUSB, release1.0– 64KB Flashforemulated EEPROM withECC
• USB devicecompatiblewiththeUSB• 16-bitExternalMemory Interface(EMIF) Specification,revision2.0and USB• Common PlatformArchitecture Specification,revision1.1– Consistentmemory map across family – Three CAN Controllers(DCAN)– Real-TimeInterruptTimer (RTI)OS Timer • 64 mailboxes withparityprotectioneach– 128-channelVectoredInterruptModule (VIM) • Compliant toCAN protocolversion– 2-channelCyclicRedundancy Checker (CRC) 2.0A/B
• DirectMemory Access (DMA) Controller – Inter-IntegratedCircuit(I2C) – 16 Channels and 32 ControlPackets – Three Multi-bufferedSerialPeripheral – ParityprotectionforcontrolpacketRAM Interfaces(MibSPI) – DMA Accesses Protectedby DedicatedMPU • 128 Words withParityProtectioneach
• Frequency-ModulatedPhase-Locked-Loop • 8 Transfergroups (FMPLL) withBuilt-InSlipDetector – Up totwo Standard SerialPeripheral
• SeparateNon-ModulatingPLL Interfaces(SPI)
• IEEE 1149.1JTAG, Boundary Scan and ARM – Two UART (SCI)interfaces,one withLocal CoreSightComponents InterconnectNetwork Interface(LIN2.1)
• Advanced JTAG SecurityModule (AJSM) Support
• Trace and CalibrationCapabilities • Up to101 generalpurpose I/O(GIO)capable pins– Parameter OverlayModule (POM) – 16 dedicatedGIO pinswithinterrupt• Enhanced Timing PeripheralsforMotor Control generationcapability– 7 Enhanced Pulse Width Modulators(ePWM)
• Packages– 6 Enhanced Capture (eCAP) – 144-pinQuad Flatpack(PGE) [Green]– 2 Enhanced QuadratureEncoder Pulse – 337-BallGridArray(ZWT) Green Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCT PREVIEW informationconcernsproductsintheformativeordesignphase of Copyright© 2012,Texas InstrumentsIncorporateddevelopment.Characteristicdata and other specificationsare design goals.Texas Instrumentsreservestherighttochange ordiscontinuetheseproductswithoutnotice.

PRODUCT□PREVIEW RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com

1.2 Applications

• IndustrialSafetyApplications – IndustrialAutomation – Safe PLC ’s (Programmable Logic Controllers) – Power Generationand Distribution – Turbinesand Windmills – Elevatorsand Escalators
• MedicalApplications – Ventilators – Defibrillators – Infusionand Insulinpumps – Radiationtherapy – Roboticsurgery

2 RM46Lx50 16/32-BitRISC FlashMicrocontroller Copyright© 2012,Texas InstrumentsIncorporated

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1.3 Description

The RM46Lx50 isa highperformancemicrocontrollerfamilyforsafetysystems.The safetyarchitecture includesDual CPUs inlockstep,CPU and Memory Built-InSelfTest(BIST)logic,ECC on boththeFlash and thedataSRAM, parityon peripheralmemories,and loopback capabilityon peripheralIOs. The RM46Lx50 integratesthe ARM ® Cortex™ -R4F FloatingPoint CPU which offersan efficient 1.66DMIPS/MHz, and has configurationswhich can run up to200MHz providingup to332 DMIPS. The devicesupportsthelittle-endian[LE32]format. The RM46Lx50 has up to1.25MB integratedFlashand up to192KB dataRAM configurationswithsingle biterrorcorrectionand double biterrordetection.The flashmemory on thisdeviceisa nonvolatile, electricallyerasableand programmable,implementedwitha 64-bit-widedata bus interface.The flash operateson a 3.3V supplyinput(same levelas I/Osupply)forallread,program and eraseoperations. When inpipelinemode, theflashoperateswitha system clockfrequencyofup to200MHz. The SRAM supportssingle-cycleread/writeaccesses inbyte,halfword,and word modes throughoutthe supported frequencyrange.. The RM46Lx50 devicefeaturesperipheralsforreal-timecontrol-basedapplications,includingtwo Next GenerationHigh End Timer (N2HET) timingcoprocessorswith up to 44 totalIO terminals,seven Enhanced PWM (ePWM) modules withup to 14 outputs,sixEnhanced CaptureModules (eCAP),two Enhanced QuadratureEncoders (eQEP) and two 12-bitAnalog-to-Digitalconverterssupportingup to24 inputs. The N2HET isan advanced intelligenttimerthatprovidessophisticatedtimingfunctionsforreal-time applications.The timerissoftware-controlled,usinga reduced instructionset,witha specializedtimer micromachineand an attachedI/O port.The N2HET can be used forpulsewidthmodulated outputs, captureor compare inputs,or general-purposeI/O.Itisespeciallywellsuitedforapplicationsrequiring multiplesensorinformationand driveactuatorswithcomplex and accuratetimepulses.A High End Timer TransferUnit(HET-TU) can performDMA type transactionsto transferN2HET data to or from main memory. A Memory ProtectionUnit(MPU) isbuiltintotheHET-TU. The enhanced pulsewidthmodulator(ePWM) module isabletogeneratecomplex pulsewidthwaveforms withminimalCPU overheador intervention.Itiseasy touse and supportsbothhighsideand low side PWM and deadband generation.Withintegratedtripzone protectionand synchronizationwiththeon chip MibADC, theePWM module isidealfordigitalmotorcontrolapplications. The enhanced Capture (eCAP) module isessentialin systems where the accuratelytimed captureof externaleventsisimportant.The eCAP can alsobe used tomonitortheePWM outputsorforsimplePWM generationwhen notneeded forcaptureapplications. The enhanced quadratureencoderpulse(eQEP) module isused fordirectinterfacewitha linearorrotary incrementalencodertogetposition,direction,and speed informationfrom a rotatingmachine as used in high-performancemotionand position-controlsystems. The devicehas two 12-bit-resolutionMibADCs with24 totalchannelsand 64 words of parityprotected bufferRAM each.The MibADC channelscan be convertedindividuallyorcan be groupedby softwarefor sequentialconversionsequences.Sixteenchannelsare shared between the two MibADCs. There are threeseparategroups.Each group can be convertedonce when triggeredor configuredforcontinuous conversionmode. The devicehas multiplecommunicationinterfaces:threeMibSPIs,two SPIs,one LIN,one SCI, three DCANs ,one I2C, one Ethernet,and one USB module..The SPI providesa convenientmethod ofserial interactionforhigh-speedcommunicationsbetween similarshift-registertypedevices.The LIN supports theLocalInterconnectstandard2.0and can be used as a UART infull-duplexmode usingthestandard Non-Return-to-Zero(NRZ) format.The DCAN supportstheCAN 2.0B protocolstandardand uses a serial, Copyright© 2012,Texas InstrumentsIncorporated RM46Lx50 16/32-BitRISC FlashMicrocontroller 3 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com multimastercommunicationprotocolthatefficientlysupportsdistributedreal-timecontrolwith robust communicationratesofup to1 megabitpersecond (Mbps).The DCAN isidealforapplicationsoperating in noisy and harsh environments(e.g.,automotiveand industrialfields)thatrequirereliableserial communicationor multiplexedwiring.The Ethernetmodule supportsMII,RMII and MDIO interfaces.The USB module includesa 2-portUSB hostcontrollerand a USB devicecontroller The I2C module is a multi-mastercommunication module providingan interfacebetween the microcontrollerand an I2C compatibledeviceviatheI2C serialbus.The I2C supportsboth100 Kbps and 400 Kbps speeds. A frequency-modulatedphase-lockedloop (FMPLL) clock module is used to multiplythe external frequencyreferencetoa higherfrequencyforinternaluse.The FMPLL providesone oftheseven possible clocksourceinputstotheglobalclockmodule (GCM). The GCM module manages themapping between theavailableclocksourcesand thedeviceclockdomains. The devicealsohas an externalclockprescaler(ECP) module thatwhen enabled,outputsa continuous externalclockon theECLK terminal.The ECLK frequencyisa user-programmableratiooftheperipheral interfaceclock(VCLK) frequency.Thislowfrequencyoutputcan be monitoredexternallyas an indicatorof thedeviceoperatingfrequency. The DirectMemory Access Controller(DMA) has 16 channels,32 controlpacketsand parityprotectionon itsmemory. A Memory ProtectionUnit(MPU) isbuiltintotheDMA toprotectmemory againsterroneous transfers. The ErrorSignalingModule (ESM) monitorsalldeviceerrorsand determineswhether an interruptor externalErrorpin/ballistriggeredwhen a faultisdetected.The nERROR terminalcan be monitored externallyas an indicatorofa faultconditioninthemicrocontroller. The ExternalMemory Interface(EMIF)providesa memory extensiontoasynchronousand synchronous memories orotherslavedevices. A ParameterOverlayModule (POM) isincludedtoenhance thecalibrationcapabilitiesofapplicationcode. The POM can re-routeFlash accesses to internalmemory or to the EMIF, thus avoidingthe re- programmingstepsnecessaryforparameterupdatesinFlash. With integratedsafetyfeaturesand a wide choice of communication and controlperipherals,the RM46Lx50 isan idealsolutionforhigh performancerealtime controlapplicationswithsafetycritical requirements.

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PRODUCT□PREVIEW HTU1 HTU2 Switched Central Resource Main Cross Bar: Arbitration and Prioritization Control CRC Switched Central Resource Peripheral Central Resource Bridge Dual Cortex-R4F CPUs in Lockstep DCAN1 DCAN2 DCAN3 LIN SCI SPI4

64 KB Flash

CAN1_RX CAN1_TX CAN2_RX CAN2_TX CAN3_RX CAN3_TX MIBSPI1_CLK MIBSPI1_SIMO[1:0] MIBSPI1_SOMI[1:0] MIBSPI1_nCS[5:0] MIBSPI1_nENA SPI2 SPI2_CLK SPI2_SIMO SPI2_SOMI SPI2_nCS[1:0] SPI2_nENA MibSPI3 MIBSPI3_CLK MIBSPI3_SIMO MIBSPI3_SOMI MIBSPI3_nCS[5:0] MIBSPI3_nENA SPI4_CLK SPI4_SIMO SPI4_SOMI SPI4_nCS0 SPI4_nENA MibSPI5 MIBSPI5_SIMO[3:0] MIBSPI5_SOMI[3:0] MIBSPI5_nCS[3:0] MIBSPI5_nENA LIN_RX LIN_TX SCI_RX SCI_TX IOMM PMM VIM RTI DCC1 DCC2 32K 32K 32K 192kB RAM with ECC DMA POM # 2 # 3 # 5 # 1 # 2 # 1always on Core/RAM RAM Core Color Legend for Power Domains SYS nPORRST nRST ECLK ESM nERROR 1.25MB Flash with ECC 32K 32K 32K Switched Central Resource Switched Central Resource I2CN2HET1 GIO I2C_SCLI2C_SDAGIOB[7:0]GIOA[7:0] N2HET2[18,16]N2HET2[15:0]N2HET1[31:0] N2HET1_PIN_nDISN2HET2_PIN_nDIS N2HET2MibADC1 MibADC2 AD1EVT AD1IN[7:0] AD2EVT VSSADVCCAD ADREFHIADREFLO AD1IN[15:8] \\AD2IN[15:8] AD1IN[23:16] \\ AD2IN[7:0] MDIO MII MDCLK MDIO MII_RXD[3:0] MII_RXER MII_TXD[3:0] MII_TXEN MII_TXCLK MII_RXCLK MII_CRS MII_RXDV MII_COL EMIF EMIF_CLK EMIF_CKE EMIF_nCS[4:2] EMIF_nCS[0] EMIF_ADDR[12:0] EMIF_BA[1:0] EMIF_DATA[15:0] EMIF_nDQM[1:0] EMIF_nOE EMIF_nWE EMIF_nRAS EMIF_nCAS EMIF_nRW EMIF_nWAIT eQEP 1,2 eQEPxA eQEPxB eQEPxS eQEPxI eCAP 1..6 eCAP[6:1] ePWM 1..7 nTZ[3:1] SYNCO SYNCI ePWMxA ePWMxB Device Host USB1.OverCurrent USB1.RCV USB1.VM USB1.VP USB1.PortPower USB1.SPEED USB1.SUSPEND USB1.TXDAT USB1.TXEN USB1.TXSE0 USB2.OverCurrent USB2.RCV USB2.VM USB2.VP USB2.PortPower USB2.SPEED USB2.SUSPEND USB2.TXDAT USB2.TXEN USB2.TXSE0 USB_FUNC.GZO USB_FUNC.PUENO USB_FUNC.PUENON USB_FUNC.RXDI USB_FUNC.RXDMI USB_FUNC.RXDPI USB_FUNC.SE0O USB_FUNC.SUSPENDO USB_FUNC.TXDO USB_FUNC.VBUSI USB Slaves Switched Central Resource Switched Central Resource EMAC OHCI EMAC Slaves RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012

1.4 FunctionalBlock Diagram

The blockdiagramreflectsthe337BGA package.Some pinsaremultiplexedornotavailable inthe144QFP. Pleasesee theTerminalfunctionstablefordetails. Figure1-1.FunctionalBlock Diagram Copyright© 2012,Texas InstrumentsIncorporated RM46Lx50 16/32-BitRISC FlashMicrocontroller 5 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com Table1-1.Device Comparison Table OrderablePart# Part# Flash RAM EMAC USB Package RM46L450PGET RM46L450 1MB 128kB 10/100 Host+ Device 144-PinQFP RM46L450ZWTT RM46L450 1MB 128kB 10/100 Host+ Device 337-BallGridArray RM46L850PGET RM46L850 1.25MB 192kB 10/100 Host+ Device 144-PinQFP RM46L850ZWTT RM46L850 1.25MB 192kB 10/100 Host+ Device 337-BallGridArray

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5.11 Multi-Buffered/StandardSerialPeripheralInterface4 System Informationand ElectricalSpecifications

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PRODUCT□PREVIEW 108 2 3 4 5 GIOA[1] nTRST 109 144 110 111 112 113 114 115 116 117 118 119 120 121 AD1IN[10]□/ AD2IN[10] 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 23 24 25 26 27 27 28 29 30 31 32 33 34 35 36 10710610510410310210110099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 GIOB[3]GIOA[0] MIBSPI3NCS[3] MIBSPI3NCS[2] N2HET1[11] FLTP1FLTP2GIOA[2]VCCIO VSS CAN3RXCAN3TXGIOA[5] N2HET1[22] GIOA[6] VCC OSCIN Kelvin_GND OSCOUT VSS GIOA[7] N2HET1[01]N2HET1[03]N2HET1[0] VCCIO VSS VSSVCC N2HET1[02]N2HET1[05] MIBSPI5NCS[0] N2HET1[07] TEST N2HET1[09]N2HET1[4] MIBSPI3NCS[1] N2HET1[06] N2HET1[13] MIBSPI1NCS[2] N2HET1[15] VCCIO VSS VSS VCC nPORRST VSS VCC VCC VSS MIBSPI3SOMI MIBSPI3SIMO MIBSPI3CLK MIBSPI3NENA MIBSPI3NCS[0] VSS VCC AD1IN[16]□/ AD2IN[0] AD1IN[17]□/ AD2IN[01] AD1IN[0] AD1IN[07] AD1IN[18]□/ AD2IN[02] AD1IN[19]□/ AD2IN[03] AD1IN[20]□/ AD2IN[04] AD1IN[21]□/ AD2IN[05] ADREFHI ADREFLO VSSAD VCCAD AD1IN[09]□/ AD2IN[09] AD1IN[01] AD1IN[02]AD1IN[03]AD1IN[11]□/ AD2IN[11]AD1IN[04]AD1IN[12]□/ AD2IN[12]AD1IN[05]AD1IN[13]□/ AD2IN[13]AD1IN[06]AD1IN[22]□/ AD2IN[06]AD1IN[14]□/ AD2IN[14]AD1IN[08]□/ AD2IN[08]AD1IN[23]□/ AD2IN[07]AD1IN[15]□/ AD2IN[15]AD1EVTVCCVSSCAN1TXCAN1RXN2HET1[24]N2HET1[26]MIBSPI1SIMOMIBSPI1SOMIMIBSPI1CLKMIBSPI1NENAMIBSPI5NENAMIBSPI5SOMI[0]MIBSPI5SIMO[0]MIBSPI5CLKVCCVSSVSSVCCION2HET1[08]N2HET1[28]TMS TDI TDO TCK RTCK VCC VSS nRST nERROR N2HET1[10] ECLK VCCIO VSS VSS VCC N2HET1[12] N2HET1[14] GIOB[0] N2HET1[30] CAN2TX CAN2RX MIBSPI1NCS[1] LINRX LINTX GIOB[1] VCCP VSS VCCIO VCC VSS N2HET1[16] N2HET1[18] N2HET1[20] GIOB[2] VCC VSS MIBSPI1NCS[0] RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com

2 Device Package and TerminalFunctions

2.1 PGE QFP Package Pinout(144-Pin)

Figure2-1.PGE QFP Package Pinout(144-Pin) Note:Pinscan have multiplexedfunctions.Onlythedefaultfunctionisdepictedinabove diagram.

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PRODUCT□PREVIEW A B C D E F G H J K L M N P R T U V W

19 VSS VSS TMS N2HET1

[10] MIBSPI5 NCS[0] MIBSPI1 SIMO MIBSPI1 NENA MIBSPI5 CLK MIBSPI5 SIMO[0] N2HET1 [28] NC CAN3RX AD1EVT AD1IN[15] AD2IN[15] AD1IN[22] AD2IN[06] AD1IN [06] AD1IN[11] AD2IN[11] VSSAD VSSAD 19

18 VSS TCK TDO nTRST N2HET1

[08] MIBSPI1 CLK MIBSPI1 SOMI MIBSPI5 NENA MIBSPI5 SOMI[0] N2HET1 [0] NC CAN3TX NC AD1IN[08] AD2IN[08] AD1IN[14] AD2IN[14] AD1IN[13] AD2IN[13] AD1IN [04] AD1IN [02] VSSAD 18

17 TDI nRST NC EMIF_

SOMI[1] NC MIBSPI5 SIMO[3] MIBSPI5 SIMO[2] N2HET1 [31] EMIF_ nCS[3] EMIF_ nCS[2] EMIF_ nCS[4] EMIF_ nCS[0] NC AD1IN [05] AD1IN [03] AD1IN[10] AD2IN[10] AD1IN [01] AD1IN[09] AD2IN[09]

16 RTCK NC NC EMIF_

BA[1] MIBSPI5 SIMO[1] NC MIBSPI5 SOMI[3] MIBSPI5 SOMI[2] NC NC NC NC NC NC AD1IN[23] AD2IN[07] AD1IN[12] AD2IN[12] AD1IN[19] AD2IN[03] ADREFLO VSSAD 16

15 NC NC NC NC NC NC NC NC NC EMIF_

DATA[0] EMIF_ DATA[1] EMIF_ DATA[2] EMIF_ DATA[3] NC NC AD1IN[21] AD2IN[05] AD1IN[20] AD2IN[04] ADREFHI VCCAD 15

14 N2HET1

[26] nERROR NC NC NC VCCIO VCCIO VCCIO VCC VCC VCCIO VCCIO VCCIO VCCIO NC NC AD1IN[18] AD2IN[02] AD1IN [07] AD1IN [0] 14

13 N2HET1

[17] N2HET1 [19] NC NC EMIF_BA[0] VCCIO VCCIO NC NC AD1IN[17] AD2IN[01] AD1IN[16] AD2IN[0] NC 13

12 ECLK N2HET1

[04] NC NC EMIF_nOE VCCIO VSS VSS VCC VSS VSS VCCIO NC MIBSPI5 NCS[3] NC NC NC 12

11 N2HET1

[14] N2HET1 [30] NC NC EMIF_ nDQM[1] VCCIO VSS VSS VSS VSS VSS VCCPLL NC NC NC NC NC 11

10 CAN1TX CAN1RX EMIF_

ADDR[12] NC EMIF_ nDQM[0] VCC VCC VSS VSS VSS VCC VCC NC NC NC MIBSPI3 NCS[0] GIOB[3] 10

9 N2HET1

[27] NC EMIF_ ADDR[11] NC EMIF_ ADDR[5] VCC VSS VSS VSS VSS VSS VCCIO EXTCLKI N2 NC NC MIBSPI3 CLK MIBSPI3 NENA 9

8 NC NC EMIF_

ADDR[10] NC EMIF_ ADDR[4] VCCP VSS VSS VCC VSS VSS VCCIO EMIF_ DATA[15] NC NC MIBSPI3 SOMI MIBSPI3 SIMO 8

7 LINRX LINTX EMIF_

ADDR[9] NC EMIF_ ADDR[3] VCCIO VCCIO EMIF_ DATA[14] NC NC N2HET1 [09] nPORRST 7

6 GIOA[4] MIBSPI5

NCS[1] EMIF_ ADDR[8] NC EMIF_ ADDR[2] VCCIO VCCIO VCCIO VCCIO VCC VCC VCCIO VCCIO VCCIO EMIF_ DATA[13] NC NC N2HET1 [05] MIBSPI5 NCS[2] 6

5 GIOA[0] GIOA[5] EMIF_

ADDR[7] EMIF_ ADDR[1] EMIF_ DATA[4] EMIF_ DATA[5] EMIF_ DATA[6] FLTP2 FLTP1 EMIF_ DATA[7] EMIF_ DATA[8] EMIF_ DATA[9] EMIF_ DATA[10] EMIF_ DATA[11] EMIF_ DATA[12] NC NC MIBSPI3 NCS[1] N2HET1 [02] 5

4 N2HET1

[16] N2HET1 [12] EMIF_ ADDR[6] EMIF_ ADDR[0] NC NC NC N2HET1 [21] N2HET1 [23] NC NC NC NC NC EMIF_ nCAS NC NC NC NC 4

3 N2HET1

[29] N2HET1 [22] MIBSPI3 NCS[3] SPI2 NENA N2HET1 [11] MIBSPI1 NCS[1] MIBSPI1 NCS[2] GIOA[6] MIBSPI1 NCS[3] EMIF_ CLK EMIF_ CKE N2HET1 [25] SPI2 NCS[0] EMIF_ nWAIT EMIF_ nRAS NC NC NC N2HET1 [06] 3

2 VSS MIBSPI3

NCS[2] GIOA[1] SPI2 SOMI SPI2□CLK GIOB[2] GIOB[5] CAN2TX GIOB[6] GIOB[1] KELVIN_ GND GIOB[0] N2HET1 [13] N2HET1 [20] MIBSPI1 NCS[0] NC TEST N2HET1 [01] VSS 2

1 VSS VSS GIOA[2] SPI2

SIMO GIOA[3] GIOB[7] GIOB[4] CAN2RX N2HET1 [18] OSCIN OSCOUT GIOA[7] N2HET1 [15] N2HET1 [24] NC N2HET1 [07] N2HET1 [03] VSS VSS 1 A B C D E F G H J K L M N P R T U V W RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012

2.2 ZWT BGA Package Ball-Map(337BallGridArray)

Figure2-2.ZWT Package Pinout.Top View Note:Ballscan have multiplexedfunctions.Onlythedefaultfunctionisdepictedinabove diagram. Copyright© 2012,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 9 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

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2.3 TerminalFunctions

Section2.3.1and Section2.3.2identifytheexternalsignalnames, theassociatedpin/ballnumbers along withthemechanicalpackage designator,thepin/balltype(Input,Output,IO,Power or Ground),whether the pin/ballhas any internalpullup/pulldown,whether the pin/ballcan be configuredas a GIO, and a functionalpin/balldescription.The firstsignalname listedisthe primaryfunctionforthatterminal.The signalname inBold isthe functionbeingdescribed.Referto the I/OMultiplexingModule (IOMM) User Guide forinformationon how toselectbetween differentmultiplexedfunctions. NOTE AllI/OsignalsexceptnRST areconfiguredas inputswhilenPORRST islowand immediately afternPORRST goes High. Alloutput-onlysignalsare configuredas inputswhilenPORRST islow,and are configured as outputsimmediatelyafternPORRST goes High. WhilenPORRST islow,theinputbuffersaredisabled,and theoutputbuffersaretri-stated.

2.3.1 PGE Package

2.3.1.1 Multi-BufferedAnalog-to-DigitalConverters(MibADC)

Table2-1.PGE Multi-BufferedAnalog-to-DigitalConverters(MibADC1, MibADC2) Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE ADREFHI (1) 66 Power - - ADC highreference supply ADREFLO (1) 67 Power ADC lowreferencesupply VCCAD (1) 69 Power OperatingsupplyforADC VSSAD (1) 68 Ground AD1EVT /MII_RX_ER/RMII_RX_ER 86 Input PullDown Programmable, ADC1 eventtriggerinput, 20uA orGIO MIBSPI3NCS[0]/AD2EVT /GIOB[2]/ 55 I/O PullUp Programmable, ADC2 eventtriggerinput, EQEP1I/N2HET2_PIN_nDIS 20uA orGIO AD1IN[0] 60 Input - - ADC1 analoginput AD1IN[01] 71 AD1IN[02] 73 AD1IN[03] 74 AD1IN[04] 76 AD1IN[05] 78 AD1IN[06] 80 AD1IN[07] 61 (1) The ADREFHI, ADREFLO, VCCAD and VSSAD connectionsarecommon forbothADC cores.

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Table2-1.PGE Multi-BufferedAnalog-to-DigitalConverters(MibADC1, MibADC2) (continued) Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE AD1IN[08]/AD2IN[08] 83 Input - - ADC1/ADC2 shared analoginputsAD1IN[09]/AD2IN[09] 70 AD1IN[10]/AD2IN[10] 72 AD1IN[11]/AD2IN[11] 75 AD1IN[12]/AD2IN[12] 77 AD1IN[13]/AD2IN[13] 79 AD1IN[14]/AD2IN[14] 82 AD1IN[15]/AD2IN[15] 85 AD1IN[16]/AD2IN[0] 58 AD1IN[17]/AD2IN[01] 59 AD1IN[18]/AD2IN[02] 62 AD1IN[19]/AD2IN[03] 63 AD1IN[20]/AD2IN[04] 64 AD1IN[21]/AD2IN[05] 65 AD1IN[22]/AD2IN[06] 81 AD1IN[23]/AD2IN[07] 84 MIBSPI3SOMI/AWM1_EXT_ENA /ECAP2 51 Output PullUp - AWM1 externalanalog mux enable MIBSPI3SIMO/AWM1_EXT_SEL[0] /ECAP3 52 Output PullUp - AWM1 externalanalog mux selectline0 MIBSPI3CLK/AWM1_EXT_SEL[1] /EQEP1A 53 Output PullUp - AWM1 externalanalog mux selectline0 Copyright© 2012,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 11 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

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2.3.1.2 Enhanced High-End Timer Modules (N2HET)

Table2-2.PGE Enhanced High-End Timer Modules (N2HET) Terminal Signal DefaultPull PullType Description Type StateSignalName 144 PGE N2HET1[0]/SPI4CLK/EPWM2B 25 I/O PullDown Programmable, N2HET1 time input20uAN2HET1[01]/SPI4NENA /USB2.TXEN/ 23 capture or output USB_FUNC.PUENO/N2HET2[8]/EQEP2A compare,orGIO. N2HET1[02]/SPI4SIMO/EPWM3A 30 Each terminal has a suppression filterthatN2HET1[03]/SPI4NCS[0]/USB2.SPEED/ 24 ignores input pulsesUSB_FUNC.PUENON/N2HET2[10]/EQEP2B smaller than aN2HET1[04]/EPWM4B 36 programmableduration. N2HET1[05]/SPI4SOMI/N2HET2[12]/EPWM3B 31 N2HET1[06]/SCIRX/EPWM5A 38 N2HET1[07]/USB2.PortPower/USB_FUNC.GZO/ 33 N2HET2[14]/EPWM7B N2HET1[08]/MIBSPI1SIMO[1]/MII_TXD[3]/ 106 USB1.OverCurrent N2HET1[09]/N2HET2[16]/USB2.SUSPEND/ 35 USB_FUNC.SUSPENDO/EPWM7A N2HET1[10]/MII_TX_CLK/USB1.TXEN 118 /MII_TX_AVCLK4/nTZ3 N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ 6 USB2.OverCurrent/USB_FUNC.VBUSI/EPWM1SYNCO N2HET1[12]/MII_CRS/RMII_CRS_DV 124 N2HET1[13]/SCITX/EPWM5B 39 N2HET1[14]/USB1.TXSE0 125 N2HET1[15]/MIBSPI1NCS[4]/ECAP1 41 N2HET1[16]/EPWM1SYNCI/EPWM1SYNCO 139 MIBSPI1NCS[1]/N2HET1[17]/MII_COL/ 130 PullUp USB1.SUSPEND/EQEP1S N2HET1[18]/EPWM6A 140 PullDown MIBSPI1NCS[2]/N2HET1[19]/MDIO 40 PullUp N2HET1[20]/EPWM6B 141 PullDown N2HET1[22]/USB2.TXSE0/USB_FUNC.SE0O 15 MIBSPI1NENA/ N2HET1[23]/MII_RXD[2]/ 96 PullUp USB1.VP/ECAP4 N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] 91 PullDown MIBSPI3NCS[1]/N2HET1[25]/MDCLK 37 PullUp N2HET1[26]/MII_RXD[1]/RMII_RXD[1] 92 PullDown MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] 4 PullUp N2HET1[28]/MII_RXCLK/RMII_REFCLK/MII_RX_AVCLK4 107 PullDown MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 3 PullUp N2HET1[30]/MII_RX_DV/USB1.SPEED/EQEP2S 127 PullDown MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31] 54 PullUp GIOA[5]/EXTCLKIN/EPWM1A/ N2HET1_PIN_nDIS 14 PullDown

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Table2-2.PGE Enhanced High-End Timer Modules (N2HET) (continued) Terminal Signal DefaultPull PullType Description Type StateSignalName 144 PGE GIOA[2]/USB2.TXDAT/USB_FUNC.TXDO/ N2HET2[0]/EQE 9 I/O PullDown Programmable, N2HET2 time inputP2I 20uA capture or output GIOA[6]/N2HET2[4]/EPWM1B 16 compare,orGIO GIOA[7]/N2HET2[6]EPWM2A 22 Each terminal has a suppression filterthatN2HET1[01]/SPI4NENA/USB2.TXEN/ 23 ignores input pulsesUSB_FUNC.PUENO// N2HET2[8] smaller than aN2HET1[03]/SPI4NCS[0]/USB2.SPEED/ 24 programmableduration.USB_FUNC.PUENON/ N2HET2[10]/EQEP2B N2HET1[05]/SPI4SOMI/N2HET2[12] 31 N2HET1[07]/USB2.PortPower/USB_FUNC.GZO/ 33 N2HET2[14]/EPWM7B N2HET1[09]/N2HET2[16]/USB2.SUSPEND/ 35 USB_FUNC.SUSPENDO N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ 6 USB2.OverCurrent/USB_FUNC.VBUSI/EPWM1SYNCO MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I/N2HET2_PIN_n 55 PullUp DIS

2.3.1.3 Enhanced Capture Modules (eCAP)

Table2-3.PGE Enhanced Capture Modules (eCAP)(1) Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE NHET1[15]/MIBSPI1NCS[4]/ECAP1 41 I/O PullDown Fixed,20uA Enhanced Capture Module 1 I/O MIBSPI3SOMI/AWM1_EXT_ENA/ ECAP2 51 PullUp Enhanced Capture Module 2 I/O MIBSPI3SIMO/AWM1_EXT_SEL[0]/ ECAP3 52 Enhanced Capture Module 3 I/O MIBSPI1NENA/N2HET1[23] /MII_RXD[2]/ 96 Enhanced Capture USB1.VP/ECAP4 Module 4 I/O MIBSPI5NENA /MII_RXD[3]/USB1.VM/MIBSPI5SOMI[1]/ECA 97 Enhanced Capture P5 Module 5 I/O MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ 105 Enhanced Capture USB1.RCV/ ECAP6 Module 6 I/O (1) These signals,when used as inputs,aredouble-synchronizedand thenoptionallyfilteredwitha 6-cycleVCLK4-based counter. Copyright© 2012,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 13 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

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2.3.1.4 Enhanced QuadratureEncoder Pulse Modules (eQEP)

Table2-4.PGE Enhanced QuadratureEncoder Pulse Modules (eQEP)(1) Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE MIBSPI3CLK/AWM1_EXT_SEL[1]/ EQEP1A 53 Input PullUp Fixed,20uA Enhanced QEP1 InputA MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B 54 Input Enhanced QEP1 InputB MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I /N2HET2_PIN_nDI 55 I/O Enhanced QEP1 Index S MIBSPI1NCS[1]/N2HET1[17]/MII_COL 130 I/O Enhanced QEP1 Strobe /USB1.SUSPEND /EQEP1S N2HET1[01]/SPI4NENA /USB2.TXEN/ 23 Input PullDown Enhanced QEP2 InputA USB_FUNC.PUENO/N2HET2[8]/ EQEP2A N2HET1[03]/SPI4NCS[0]/USB2.SPEED/ 24 Input Enhanced QEP2 InputB USB_FUNC.PUENON/N2HET2[10]/ EQEP2B GIOA[2]/USB2.TXDAT/USB_FUNC.TXDO/N2HET2[0]/ EQEP 9 I/O Enhanced QEP2 Index N2HET1[30]/MII_RX_DV/USB1.SPEED/ EQEP2S 127 I/O Enhanced QEP2 Strobe (1) These signalsaredouble-synchronizedand thenoptionallyfilteredwitha 6-cycleVCLK4-based counter.

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2.3.1.5 Enhanced Pulse-WidthModulatorModules (ePWM)

Table2-5.PGE Enhanced Pulse-WidthModulatorModules (ePWM) Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE GIOA[5]/EXTCLKIN/EPWM1A /N2HET1_PIN_nDIS 14 Output PullDown - Enhanced PWM1 Output A GIOA[6]/N2HET2[4]/EPWM1B 16 Enhanced PWM1 Output B N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ 6 ExternalePWM Sync USB2.OverCurrent/USB_FUNC.VBUSI/EPWM1SYNCO PulseOutput N2HET1[16]/EPWM1SYNCI /EPWM1SYNCO 139 ExternalePWM Sync PulseOutput GIOA[7]/N2HET2[6]/EPWM2A 22 Enhanced PWM2 Output A N2HET1[0]/SPI4CLK/EPWM2B 25 Enhanced PWM2 Output B N2HET1[02]/SPI4SIMO/EPWM3A 30 Enhanced PWM3 Output A N2HET1[05]/SPI4SOMI/N2HET2[12]/EPWM3B 31 Enhanced PWM3 Output B MIBSPI5NCS[0]/EPWM4A 32 PullUp Enhanced PWM4 Output A N2HET1[04]/EPWM4B 36 PullDown Enhanced PWM4 Output B N2HET1[06]/SCIRX/EPWM5A 38 Enhanced PWM5 Output A N2HET1[13]/SCITX/EPWM5B 39 Enhanced PWM5 Output B N2HET1[18]/EPWM6A 140 Enhanced PWM6 Output A N2HET1[20]/EPWM6B 141 Enhanced PWM6 Output B N2HET1[09]/N2HET2[16]/USB2.SUSPEND/ 35 Enhanced PWM7 Output USB_FUNC.SUSPENDO/ EPWM7A A N2HET1[07]/USB2.PortPower/USB_FUNC.GZO/ 33 Enhanced PWM7 Output N2HET2[14]/EPWM7B B MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 3 Input PullUp Fixed,20uA TripZone Inputs1,2 and 3.These signalsareMIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 4 eitherconnected N2HET1[10]/MII_TX_CLK/USB1.TXEN 118 PullDown asynchronouslytothe /MII_TX_AVCLK4/nTZ3 ePWMx tripzone inputs, ordouble-synchronized withVCLK4, ordouble- synchronizedand then filteredwitha 6-cycle VCLK4-based counter beforeconnectingtothe ePWMx tripzone inputs. Copyright© 2012,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 15 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

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2.3.1.6 General-PurposeInput/Output (GIO)

Table2-6.PGE General-PurposeInput/Output (GIO) Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE GIOA[0]/USB2.VP/USB_FUNC.RXDPI 2 I/O PullDown Programmable, General-purposeI/O. 20uA AllGIO terminalsareGIOA[1]/USB2.VM/USB_FUNC.RXDMI 5 capableofgenerating GIOA[2]/USB2.TXDAT/USB_FUNC.TXDO/N2HET2[0]/EQEP 9 interruptstotheCPU on 2II rising/falling/both edges.GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS 14 GIOA[6]/N2HET2[4]/EPWM1B 16 GIOA[7]/N2HET2[6]/EPWM2A 22 GIOB[0]/USB1.TXDAT 126 GIOB[1]/USB1.PortPower 133 GIOB[2] 142 MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I/N2HET2_PIN_nD 55(1) PullUp IS GIOB[3]USB2.RCV/USB_FUNC.RXDI 1 PullDown (1) GIOB[2]cannotoutputa levelon topin55.Onlytheinputfunctionalityissupportedso thattheapplicationcan generatean interrupt whenever theN2HET2_PIN_nDIS isasserted(drivenlow).Also,a pullup isenabledon theinput.Thisisnotprogrammableusingthe GIO module controlregisters.

2.3.1.7 ControllerArea Network Controllers(DCAN)

Table2-7.PGE ControllerArea Network Controllers(DCAN) Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE CAN1RX 90 I/O PullUp Programmable, CAN1 receive,orGIO 20uACAN1TX 89 CAN1 transmit,orGIO CAN2RX 129 CAN2 receive,orGIO CAN2TX 128 CAN2 transmit,orGIO CAN3RX 12 CAN3 receive,orGIO CAN3TX 13 CAN3 transmit,orGIO

2.3.1.8 LocalInterconnectNetwork InterfaceModule (LIN)

Table2-8.PGE LocalInterconnectNetwork InterfaceModule (LIN) Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE LINRX 131 I/O PullUp Programmable, LIN receive,orGIO 20uALINTX 132 LIN transmit,orGIO

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2.3.1.9 Standard SerialCommunication Interface(SCI)

Table2-9.PGE Standard SerialCommunication Interface(SCI) Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE N2HET1[06]/SCIRX /EPWM5A 38 I/O PullDown Programmable, SCI receive,orGIO 20uAN2HET1[13]/SCITX /EPWM5B 39 SCI transmit,orGIO 2.3.1.10Inter-IntegratedCircuitInterfaceModule (I2C) Table2-10.PGE Inter-IntegratedCircuitInterfaceModule (I2C) Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE MIBSPI3NCS[2]/I2C_SDA /N2HET1[27]/nTZ2 4 I/O PullUp Programmable, I2C serialdata,orGIO 20uAMIBSPI3NCS[3]/I2C_SCL /N2HET1[29]/nTZ1 3 I2C serialclock,orGIO 2.3.1.11Standard SerialPeripheralInterface(SPI) Table2-11.PGE Standard SerialPeripheralInterface(SPI) Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE N2HET1[0]/SPI4CLK /EPWM2B 25 I/O PullDown Programmable, SPI4 clock,orGIO 20uAN2HET1[03]/SPI4NCS[0]/USB2.SPEED/ 24 SPI4 chipselect,orGIO USB_FUNC.PUENON/N2HET2[10]/EQEP2B N2HET1[01]/SPI4NENA /USB2.TXEN/ 23 SPI4 enable,orGIO USB_FUNC.PUENO/N2HET2[8]/EQEP2A N2HET1[02]/SPI4SIMO /EPWM3A 30 SPI4 slave-inputmaster- output,orGIO N2HET1[05]/SPI4SOMI /N2HET2[12]/EPWM3B 31 SPI4 slave-outputmaster- input,orGIO Copyright© 2012,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 17 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com 2.3.1.12Multi-BufferedSerialPeripheralInterfaceModules (MibSPI) Table2-12.PGE Multi-BufferedSerialPeripheralInterfaceModules (MibSPI) Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE MIBSPI1CLK 95 I/O PullUp Programmable, MibSPI1 clock,orGIO 20uAMIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ 105 MibSPI1 chipselect,or USB1.RCV/ECAP6 GIO MIBSPI1NCS[1]/N2HET1[17]/MII_COL 130 /USB1.SUSPEND /EQEP1S MIBSPI1NCS[2]/N2HET1[19]/MDIO 40 N2HET1[15]/MIBSPI1NCS[4]/ECAP1 41 PullDown Programmable, MibSPI1 chipselect,or 20uA GION2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] 91 MIBSPI1NENA /N2HET1[23]/MII_RXD[2]/ 96 PullUp Programmable, MibSPI1 enable,orGIO USB1.VP/ECAP4 20uA MIBSPI1SIMO 93 MibSPI1 slave-inmaster- out,orGIO N2HET1[08]/MIBSPI1SIMO[1]/MII_TXD[3]/ 106 PullDown Programmable, MibSPI1 slave-inmaster- USB1.OverCurrent 20uA out,orGIO MIBSPI1SOMI 94 PullUp Programmable, MibSPI1 slave-outmaster- 20uA in,orGIOMIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ 105 USB1.RCV/ECAP6 MIBSPI3CLK /AWM1_EXT_SEL[1]/EQEP1A 53 I/O PullUp Programmable, MibSPI3 clock,orGIO 20uAMIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I/N2HET2_PIN_nD 55 MibSPI3 chipselect,or IS GIO MIBSPI3NCS[1]/N2HET1[25]/MDCLK 37 MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 4 MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 3 N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ 6 PullDown Programmable, MibSPI3 chipselect,or USB2.OverCurrent/USB_FUNC.VBUSI/EPWM1SYNCO 20uA GIO MIBSPI3NENA /MIBSPI3NCS[5]/N2HET1[31]/EQEP1B 54 PullUp Programmable, MibSPI3 chipselect,or 20uA GIO MIBSPI3NENA /MIBSPI3NCS[5]/N2HET1[31]/EQEP1B 54 MibSPI3 enable,orGIO MIBSPI3SIMO /AWM1_EXT_SEL[0]/ECAP3 52 MibSPI3 slave-inmaster- out,orGIO MIBSPI3SOMI /AWM1_EXT_ENA/ECAP2 51 MibSPI3 slave-outmaster- in,orGIO MIBSPI5CLK /MII_TXEN/RMII_TXEN 100 I/O PullUp Programmable, MibSPI5 clock,orGIO 20uAMIBSPI5NCS[0]/EPWM4A 32 MibSPI5 chipselect,or GIO MIBSPI5NENA /MII_RXD[3]/USB1.VM/MIBSPI5SOMI[1]/ECA 97 MibSPI5 enable,orGIO MIBSPI5SIMO[0]/MII_TXD[1]/RMII_TXD[1]/MIBSPI5SOMI[2] 99 MibSPI5 slave-inmaster- out,orGIO MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0] 98 MibSPI5 slave-outmaster- in,orGIO MIBSPI5NENA /MII_RXD[3]/USB1.VM/MIBSPI5SOMI[1]/ECA 97 MibSPI5 SOMI, orGIO MIBSPI5SIMO[0]/MII_TXD[1]/RMII_TXD[1]/MIBSPI5SOMI[2] 99 MibSPI5 SOMI, orGIO

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 2.3.1.13EthernetController Table2-13.PGE EthernetController:MDIO Interface Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE MIBSPI3NCS[1]/N2HET1[25]/MDCLK 37 Output PullUp - Serialclockoutput MIBSPI1NCS[2]/N2HET1[19]/MDIO 40 I/O PullUp Fixed,20uA Serialdatainput/output Table2-14.PGE EthernetController:Reduced Media IndependentInterface(RMII) Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE N2HET1[12]/MII_CRS/RMII_CRS_DV 124 Input PullDown Fixed,20uA RMII carriersense and datavalid N2HET1[28]/MII_RXCLK/RMII_REFCLK /MII_RX_AVCLK4 107 RMII synchronous referenceclockfor receive,transmitand controlinterface AD1EVT/MII_RX_ER/ RMII_RX_ER 86 RMII receiveerror N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] 91 RMII receivedata N2HET1[26]/MII_RXD[1]/RMII_RXD[1] 92 MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0] 98 Output PullUp - RMII transmitdata MIBSPI5SIMO[0]/MII_TXD[1]/RMII_TXD[1]/MIBSPI5SOMI[2] 99 MIBSPI5CLK/MII_TXEN/RMII_TXEN 100 RMII transmitenable Table2-15.PGE EthernetController:Media IndependentInterface(MII) Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE MIBSPI1NCS[1]/N2HET1[17]/MII_COL / 130 Input PullUp - Collisiondetect USB1.SUSPEND/EQEP1S N2HET1[12]/MII_CRS /RMII_CRS_DV 124 PullDown Fixed,20uA Carriersense and receive valid N2HET1[28]/MII_RXCLK/RMII_REFCLK/MII_RX_AVCLK4 107 I/O PullDown - MIIoutputreceiveclock N2HET1[30]/MII_RX_DV /USB1.SPEED/EQEP2S/EQEP2S 127 Input PullDown Fixed,20uA Receiveddatavalid AD1EVT/ MII_RX_ER /RMII_RX_ER 86 Receiveerror N2HET1[28]/MII_RX_CLK /RMII_REFCLK/MII_RX_AVCLK4 107 I/O Receiveclock N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] 91 Input Receivedata N2HET1[26]/MII_RXD[1]/RMII_RXD[1] 92 MIBSPI1NENA/N2HET1[23]/MII_RXD[2]/ 96 PullUp Fixed,20uA USB1.VP/ECAP4 MIBSPI5NENA/ MII_RXD[3]/USB1.VM/ECAP5/ECAP5 97 N2HET1[10]/MII_TX_CLK/USB1.TXEN/ 118 I/O PullDown - MIIoutputtransmitclock MII_TX_AVCLK4 /nTZ3 N2HET1[10]/MII_TX_CLK /USB1.TXEN 118 Transmitclock /MII_TX_AVCLK4/nTZ3 Copyright© 2012,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 19 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com Table2-15.PGE EthernetController:Media IndependentInterface(MII)(continued) Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0] 98 Output PullUp - Transmitdata MIBSPI5SIMO[0]/MII_TXD[1] 99 MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ 105 USB1.RCV/ECAP6 N2HET1[08]/MIBSPI1SIMO[1]/MII_TXD[3]/ 106 PullDown - USB1.OverCurrent MIBSPI5CLK/MII_TXEN /RMII_TXEN 100 PullUp - Transmitenable 2.3.1.14USB Host PortControllerInterface Table2-16.PGE USB Host PortControllerInterface(USB1, USB2) Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE N2HET1[08]/MIBSPI1SIMO[1]/MII_TXD[3] 106 Input PullDown Fixed,20uA Overcurrentindication /USB1.OverCurrent fromUSB power switch MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ 105 PullUp Fixed,20uA ReceivedatafromUSB USB1.RCV /ECAP6 porttransceiver MIBSPI5NENA /MII_RXD[3]/USB1.VM 97 NRZI encoded D-minus fromUSB porttransceiver MIBSPI1NENA/N2HET1[23] /MII_RXD[2]/ 96 NRZI encoded D-plus USB1.VP /ECAP4 fromUSB porttransceiver GIOB[1]/USB1.PortPower 133 Output PullDown - N2HET1[30]/MII_RX_DV/USB1.SPEED 127 Transmitspeed indication MIBSPI1NCS[1]/N2HET1[17]/MII_COL/ 130 PullUp - USB1.SUSPEND /EQEP1S GIOB[0]/USB1.TXDAT 126 PullDown - N2HET1[10]/MII_TX_CLK/USB1.TXEN 118 Transmitenabletoport /MII_TX_AVCLK4 transceiver N2HET1[14]/USB1.TXSE0 125 Single-endedzerotoport transceiver N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ 6 Input PullDown Fixed,20uA USB2.OverCurrent/USB_FUNC.VBUSI/EPWM1SYNCO GIOB[3]/USB2.RCV /USB_FUNC.RXDI 1 PullDown Fixed,20uA GIOA[1]/USB2.VM /USB_FUNC.RXDMI 5 NRZI encoded D-minus fromUSB porttransceiver GIOA[0]/USB2.VP /USB_FUNC.RXDPI 2 NRZI encoded D-plus fromUSB porttransceiver N2HET1[07]/USB2.PortPower / 33 Output PullDown - USB_FUNC.GZO/N2HET2[14]/EPWM7B N2HET1[03]/SPI4NCS[0]/USB2.SPEED / 24 Transmitspeed indication USB_FUNC.PUENON/N2HET2[10] N2HET1[09]/N2HET2[16]/USB2.SUSPEND / 35 Portsuspend indication USB_FUNC.SUSPENDO GIOA[2]/USB2.TXDAT /USB_FUNC.TXDO/N2HET2[0]/EQEP 9 NRZI encoded D-plusto 2I porttransceiver N2HET1[01]/SPI4NENA/USB2.TXEN / 23 Transmitenabletoport USB_FUNC.PUENO/N2HET2[8] transceiver N2HET1[22]/USB2.TXSE0 /USB_FUNC.SE0O 15 Single-endedzerotoport transceiver

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Table2-17.PGE USB Device PortControllerInterface(USB_FUNC) Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE N2HET1[07]/USB2.PortPower/USB_FUNC.GZO /N2HET2[14] 33 Output PullDown - PullUp enable,allowsfor software-programmable USB device connect/disconnect N2HET1[01]/SPI4NENA/USB2.TXEN/ USB_FUNC.PUENO / 23 PUENO inverted N2HET2[8] N2HET1[03]/SPI4NCS[0]/USB2.SPEED/USB_FUNC.PUENO 24 N / N2HET2[10]/EQEP2B GIOB[3]/USB2.RCV/USB_FUNC.RXDI 1 Input PullDown Fixed,20uA USB devicesingle-ended datainput GIOA[1]/USB2.VM/USB_FUNC.RXDMI 5 USB devicelogicvalueof D-minus GIOA[0]/USB2.VP/USB_FUNC.RXDPI 2 USB devicelogicvalueof D-plus N2HET1[22]/USB2.TXSE0/USB_FUNC.SE0O 15 Output PullDown - USB devicesingle-ended zero N2HET1[09]/N2HET2[16]/USB2.SUSPEND/ 35 USB devicesuspend USB_FUNC.SUSPENDO output GIOA[2]/USB2.TXDAT/USB_FUNC.TXDO /N2HET2[0] 9 USB devicetransmitdata N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ 6 Input PullDown Fixed,20uA USB devicepower USB2.OverCurrent/USB_FUNC.VBUSI /EPWM1SYNCO connected 2.3.1.15System Module Interface Table2-18.PGE System Module Interface Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE nPORRST 46 Input PullDown 100uA Power-onreset,coldreset Externalpower supply monitorcircuitrymust drivenPORRST lowwhen any ofthesuppliestothe microcontrollerfalloutof thespecifiedrange.This terminalhas a glitchfilter. See Section4.8. nRST 116 I/O PullUp 100uA System reset,warm reset, bidirectional. The internalcircuitry indicatesany reset conditionby drivingnRST low. The externalcircuitrycan asserta systemresetby drivingnRST low.To ensurethatan external resetisnotarbitrarily generated,TI recommends thatan externalpull-upresistoris connectedtothisterminal. Thisterminalhas a glitch filter.See Section4.8. Copyright© 2012,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 21 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com Table2-18.PGE System Module Interface(continued) Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE nERROR 117 I/O PullDown 20uA ESM ErrorSignal Indicateserrorofhigh severity.See Section4.18. 2.3.1.16Clock Inputsand Outputs Table2-19.PGE Clock Inputsand Outputs Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE OSCIN 18 Input - - From external crystal/resonator,or externalclockinput KELVIN_GND 19 Input Kelvingroundforoscillator OSCOUT 20 Output To external crystal/resonator ECLK 119 I/O PullDown Programmable, Externalprescaledclock 20uA output,orGIO. GIOA[5]/EXTCLKIN /EPWM1A /N2HET1_PIN_nDIS 14 Input PullDown 20uA Externalclockinput#1 2.3.1.17Testand Debug Modules Interface Table2-20.PGE Testand Debug Modules Interface Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE TEST 34 Input PullDown Fixed,100uA Testenable nTRST 109 Input JTAG testhardwarereset RTCK 113 Output - - JTAG returntestclock TCK 112 Input PullDown Fixed,100uA JTAG testclock TDI 110 Input PullUp JTAG testdatain TDO 111 Output PullDown JTAG testdataout TMS 108 Input PullUp JTAG testselect 2.3.1.18FlashSupply and TestPads Table2-21.PGE FlashSupply and TestPads Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE VCCP 134 3.3V - - Flashpump supply Power FLTP1 7 - - - Flashtestpads.These terminalsarereservedforFLTP2 8 TIuse only.Forproper operationtheseterminals must connectonlytoa testpad ornotbe connectedatall[no connect(NC)].

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 2.3.1.19Supply forCore Logic:1.2Vnominal Table2-22.PGE Supply forCore Logic:1.2Vnominal Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE VCC 17 1.2V - - Core supply PowerVCC 29 VCC 45 VCC 48 VCC 49 VCC 57 VCC 87 VCC 101 VCC 114 VCC 123 VCC 137 VCC 143 2.3.1.20Supply forI/OCells:3.3Vnominal Table2-23.PGE Supply forI/OCells:3.3Vnominal Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE VCCIO 10 3.3V - - OperatingsupplyforI/Os PowerVCCIO 26 VCCIO 42 VCCIO 104 VCCIO 120 VCCIO 136 Copyright© 2012,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 23 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com 2.3.1.21Ground ReferenceforAllSuppliesExcept VCCAD Table2-24.PGE Ground ReferenceforAllSuppliesExcept VCCAD Terminal Signal Default PullType Description Type PullStateSignalName 144 PGE VSS 11 Ground - - Ground reference VSS 21 VSS 27 VSS 28 VSS 43 VSS 44 VSS 47 VSS 50 VSS 56 VSS 88 VSS 102 VSS 103 VSS 115 VSS 121 VSS 122 VSS 135 VSS 138 VSS 144

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2.3.2 ZWT Package

2.3.2.1 Multi-BufferedAnalog-to-DigitalConverters(MibADC)

Table2-25.ZWT Multi-BufferedAnalog-to-DigitalConverters(MibADC1, MibADC2) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT ADREFHI (1) V15 Power - - ADC highreference supply ADREFLO (1) V16 Power ADC lowreferencesupply VCCAD (1) W15 Power OperatingsupplyforADC VSSAD V19 Ground - - ADC supplypower W16 W18 W19 AD1EVT /MII_RX_ER/RMII_RX_ER N19 Input PullDown Programmable, ADC1 eventtriggerinput, 20uA orGIO MIBSPI3NCS[0]/AD2EVT /GIOB[2]/EQEP1I/N2HET2_PIN_nD V10 I/O PullUp Programmable, ADC2 eventtriggerinput, IS 20uA orGIO AD1IN[0] W14 Input - - ADC1 analoginput AD1IN[01] V17 AD1IN[02] V18 AD1IN[03] T17 AD1IN[04] U18 AD1IN[05] R17 AD1IN[06] T19 AD1IN[07] V14 AD1IN[08]/AD2IN[08] P18 Input - - ADC1/ADC2 shared analoginputsAD1IN[09]/AD2IN[09] W17 AD1IN[10]/AD2IN[10] U17 AD1IN[11]/AD2IN[11] U19 AD1IN[12]/AD2IN[12] T16 AD1IN[13]/AD2IN[13] T18 AD1IN[14]/AD2IN[14] R18 AD1IN[15]/AD2IN[15] P19 AD1IN[16]/AD2IN[0] V13 AD1IN[17]/AD2IN[01] U13 AD1IN[18]/AD2IN[02] U14 AD1IN[19]/AD2IN[03] U16 AD1IN[20]/AD2IN[04] U15 AD1IN[21]/AD2IN[05] T15 AD1IN[22]/AD2IN[06] R19 AD1IN[23]/AD2IN[07] R16 MIBSPI3SOMI/AWM1_EXT_ENA /ECAP2 V8 Output PullUp - AWM1 externalanalog mux enable MIBSPI3SIMO/AWM1_EXT_SEL[0] /ECAP3 W8 AWM1 externalanalog mux selectline0 MIBSPI3CLK/AWM1_EXT_SEL[1] /EQEP1A V9 AWM1 externalanalog mux selectline0 (1) The ADREFHI, ADREFLO, VCCAD and VSSAD connectionsarecommon forbothADC cores. Copyright© 2012,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 25 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

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2.3.2.2 Enhanced High-End Timer Modules (N2HET)

Table2-26.ZWT Enhanced High-End Timer Modules (N2HET) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT N2HET1[0]/SPI4CLK/EPWM2B K18 I/O PullDown Programmable, N2HET1 time input20uAN2HET1[01]/SPI4NENA/N2HET2[8] V2 capture or output compare,orGIO.N2HET1[02]/SPI4SIMO/EPWM3A W5 Each terminal has aN2HET1[03]/SPI4NCS[0]/USB2.SPEED/ U1 suppression filterthatUSB_FUNC.PUENON/N2HET2[10]/EQEP2B ignores input pulsesN2HET1[04]/EPWM4B B12 smaller than a N2HET1[05]/SPI4SOMI/N2HET2[12]/EPWM3B V6 programmableduration. N2HET1[06]/SCIRX/EPWM5A W3 N2HET1[07]/EPWM7B /USB2.PortPower/ T1 USB_FUNC.GZO/N2HET2[14]/EPWM7B N2HET1[08]/MIBSPI1SIMO[1]/MII_TXD[3]/ E18 USB1.OverCurrent N2HET1[09]/N2HET2[16]/ V7 USB2.SUSPEND/USB_FUNC.SUSPENDO/EPWM7A N2HET1[10]/MII_TX_CLK/ D19 USB1.TXEN/MII_TX_AVCLK4/nTZ3 N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ E3 USB2.OverCurrent/USB_FUNC.VBUSI/EPWM1SYNCO N2HET1[12]/MII_CRS/RMII_CRS_DV B4 N2HET1[13]/SCITX/EPWM5B N2 N2HET1[14]/USB1.TXSE0 A11 N2HET1[15]/MIBSPI1NCS[4]/ECAP1 N1 N2HET1[16]/EPWM1SYNCI/EPWM1SYNCO A4 N2HET1[17] A13 N2HET1[18]/EPWM6A J1 N2HET1[19] B13 N2HET1[20]/EPWM6B P2 N2HET1[21] H4 N2HET1[22]/USB2.TXSE0/USB_FUNC.SE0O B3 N2HET1[23] J4 N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] P1 N2HET1[25] M3 N2HET1[26]/MII_RXD[1]/RMII_RXD[1] A14 N2HET1[27] A9 N2HET1[28]/MII_RX_CLK/RMII_REFCLK/MII_RX_AVCLK4 K19 N2HET1[29] A3 N2HET1[30]/MII_RX_DV/USB1.SPEED/EQEP2S B11 N2HET1[31] J17 GIOA[5]/EXTCLKIN/EPWM1A /N2HET1_PIN_nDIS B5 input PullDown Fixed,20uA

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Table2-26.ZWT Enhanced High-End Timer Modules (N2HET) (continued) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT GIOA[2]/USB2.TXDAT/USB_FUNC.TXDO/ N2HET2[0]/EQEP C1 I/O PullDown Programmable, N2HET2 time input2I 20uA capture or output EMIF_ADDR[0]/N2HET2[1] D4 compare,orGIO. GIOA[3]/N2HET2[2] E1 Each terminal has a suppression filterthatEMIF_ADDR[1]/N2HET2[3] D5 ignores input pulsesGIOA[6]/N2HET2[4]/EPWM1B H3 smaller than a EMIF_BA[1]/N2HET2[5] D16 programmableduration. GIOA[7]/N2HET2[6]/EPWM2A M1 EMIF_nCS[0]/N2HET2[7] N17 N2HET1[01]/SPI4NENA/USB2.TXEN/ V2 USB_FUNC.PUENO/ N2HET2[8] EMIF_nCS[3]/N2HET2[9] K17 N2HET1[03]/SPI4NCS[0]/USB2.SPEED/ U1 USB_FUNC.PUENON/ N2HET2[10]/EQEP2B EMIF_ADDR[6]/N2HET2[11] C4 N2HET1[05]/SPI4SOMI/N2HET2[12]/EPWM3B V6 EMIF_ADDR[7]/N2HET2[13] C5 N2HET1[07]/USB2.PortPower/ T1 USB_FUNC.GZO/ N2HET2[14]/EPWM7B EMIF_ADDR[8]/N2HET2[15] C6 N2HET1[09]/N2HET2[16]/USB2.SUSPEND/ V7 USB_FUNC.SUSPENDO/EPWM7A N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ E3 USB2.OverCurrent/USB_FUNC.VBUSI/EPWM1SYNCO MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I/N2HET2_PIN_nD V10 PullUp IS

2.3.2.3 Enhanced Capture Modules (eCAP)

Table2-27.ZWT Enhanced Capture Modules (eCAP)(1) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT N2HET1[15]/MIBSPI1NCS[4]/ECAP1 N1 I/O PullDown Fixed,20uA Enhanced Capture Module 1 I/O MIBSPI3SOMI/AWM1_EXT_ENA/ ECAP2 V8 std PullUp Enhanced Capture buffer Module 2 I/O MIBSPI3SIMO/AWM1_EXT_SEL[0]/ ECAP3 W8 std Enhanced Capture buffer Module 3 I/O MIBSPI1NENA/N2HET1[23]/MII_RXD[2]/USB1.VP/ECAP4 G19 std Enhanced Capture buffer Module 4 I/O MIBSPI5NENA/ MII_RXD[3]/USB1.VM/MIBSPI5SOMI[1]/ECA H18 std Enhanced Capture P5 buffer Module 5 I/O MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/USB1.RCV/EC R2 std Enhanced Capture AP6 buffer Module 6 I/O (1) These signals,when used as inputs,aredouble-synchronizedand thenoptionallyfilteredwitha 6-cycleVCLK4-based counter. Copyright© 2012,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 27 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

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2.3.2.4 Enhanced QuadratureEncoder Pulse Modules (eQEP)

Table2-28.ZWT Enhanced QuadratureEncoder Pulse Modules (eQEP)(1) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT MIBSPI3CLK/AWM1_EXT_SEL[1]/ EQEP1A V9 Input PullUp Fixed,20uA Enhanced QEP1 InputA MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B W9 Input Enhanced QEP1 InputB MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I /N2HET2_PIN_nDI V10 I/O Enhanced QEP1 Index S MIBSPI1NCS[1]/N2HET1[17]/MII_COL/USB1.SUSPEND/ EQ F3 I/O Enhanced QEP1 Strobe EP1S N2HET1[01]/SPI4NENA/USB2.TXEN/USB_FUNC.PUENO/N V2 Input PullDown Enhanced QEP2 InputA 2HET2[8]/EQEP2A N2HET1[03]/SPI4NCS[0]/USB2.SPEED/USB_FUNC.PUENO U1 Input PullDown Enhanced QEP2 InputB N/N2HET2[10]/EQEP2B GIOA[2]/USB2.TXDAT/USB_FUNC.TXDO/N2HET2[0]/ EQEP C1 I/O PullDown Enhanced QEP2 Index N2HET1[30]/MII_RX_DV/USB1.SPEED/ EQEP2S B11 I/O PullDown Enhanced QEP2 Strobe (1) These signalsaredouble-synchronizedand thenoptionallyfilteredwitha 6-cycleVCLK4-based counter.

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2.3.2.5 Enhanced Pulse-WidthModulatorModules (ePWM)

Table2-29.ZWT Enhanced Pulse-WidthModulatorModules (ePWM) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT GIOA[5]/EXTCLKIN/EPWM1A /N2HET1_PIN_nDIS B5 Output PullDown - Enhanced PWM1 Output A GIOA[6]/N2HET2[4]/EPWM1B H3 Enhanced PWM1 Output B N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/USB2.OverCurrent E3 ExternalePWM Sync /USB_FUNC.VBUSI/ EPWM1SYNCO PulseOutput N2HET1[16]/EPWM1SYNCI /EPWM1SYNCO A4 ExternalePWM Sync PulseOutput GIOA[7]/N2HET2[6]/EPWM2A M1 Enhanced PWM2 Output A N2HET1[0]/SPI4CLK/EPWM2B K18 Enhanced PWM2 Output B N2HET1[02]/SPI4SIMO/EPWM3A W5 Enhanced PWM3 Output A N2HET1[05]/SPI4SOMI/N2HET2[12]/EPWM3B V6 Enhanced PWM3 Output B MIBSPI5NCS[0]/EPWM4A E19 PullUp Enhanced PWM4 Output A N2HET1[04]/EPWM4B B12 PullDown Enhanced PWM4 Output B N2HET1[06]/SCIRX/EPWM5A W3 Enhanced PWM5 Output A N2HET1[13]/SCITX/EPWM5B N2 Enhanced PWM5 Output B N2HET1[18]/EPWM6A J1 Enhanced PWM6 Output A N2HET1[20]/EPWM6B P2 Enhanced PWM6 Output B N2HET1[09]/N2HET2[16]/USB2.SUSPEND/USB_FUNC.SUS V7 Enhanced PWM7 Output PENDO/ EPWM7A A N2HET1[07]/USB2.PortPower/USB_FUNC.GZO/N2HET2[14]/ T1 Enhanced PWM7 Output EPWM7B B MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 C3 Input PullUp Fixed,20uA TripZone Inputs1,2 and 3These signalsareeitherMIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 B2 connected N2HET1[10]/MII_TX_CLK/USB1.TXEN//MII_TX_AVCLK4/nT D19 PullDown asynchronouslytothe Z3 ePWMx tripzone inputs, ordouble-synchronized withVCLK4, ordouble- synchronizedand then filteredwitha 6-cycle VCLK4-based counter beforeconnectingtothe ePWMx tripzone inputs. Copyright© 2012,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 29 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

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2.3.2.6 General-PurposeInput/Output (GIO)

Table2-30.ZWT General-PurposeInput/Output (GIO) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT GIOA[0]/USB2.VP/USB_FUNC.RXDPI A5 I/O PullDown Programmable, General-purposeI/O. 20uA AllGIO terminalsareGIOA[1]/USB2.VM/USB_FUNC.RXDMI C2 capableofgenerating GIOA[2]/USB2.TXDAT/USB_FUNC.TXDO/N2HET2[0] C1 interruptstotheCPU on /EQEP2I rising/falling/both edges.GIOA[3]/N2HET2[2] E1 GIOA[4] A6 GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS B5 GIOA[6]/N2HET2[4]/EPWM1B H3 GIOA[7]/N2HET2[6]/EPWM2A M1 GIOB[0]/USB1.TXDAT M2 GIOB[1]/USB1.PortPower K2 GIOB[2] F2 / V10 (1) GIOB[3]/USB2.RCV W10 GIOB[4] G1 GIOB[5] G2 GIOB[6] J2 GIOB[7] F1 (1) GIOB[2]cannotoutputa levelon toterminalV10.Onlytheinputfunctionalityissupportedso thattheapplicationcan generatean interruptwhenever theN2HET2_PIN_nDIS isasserted(drivenlow).Also,a pullup isenabledon theinput.Thisisnotprogrammable usingtheGIO module controlregisters.

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2.3.2.7 ControllerArea Network Controllers(DCAN)

Table2-31.ZWT ControllerArea Network Controllers(DCAN) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT CAN1RX B10 I/O PullUp Programmable, CAN1 receive,orGIO 20uACAN1TX A10 CAN1 transmit,orGIO CAN2RX H1 CAN2 receive,orGIO CAN2TX H2 CAN2 transmit,orGIO CAN3RX M19 CAN3 receive,orGIO CAN3TX M18 CAN3 transmit,orGIO

2.3.2.8 LocalInterconnectNetwork InterfaceModule (LIN)

Table2-32.ZWT LocalInterconnectNetwork InterfaceModule (LIN) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT LINRX A7 I/O PullUp Programmable, LIN receive,orGIO 20uALINTX B7 LIN transmit,orGIO

2.3.2.9 Standard SerialCommunication Interface(SCI)

Table2-33.ZWT Standard SerialCommunication Interface(SCI) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT N2HET1[06]/SCIRX /EPWM5A W3 I/O PullDown Programmable, SCI receive,orGIO 20uAN2HET1[13]/SCITX /EPWM5B N2 SCI transmit,orGIO Copyright© 2012,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 31 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com 2.3.2.10Inter-IntegratedCircuitInterfaceModule (I2C) Table2-34.ZWT Inter-IntegratedCircuitInterfaceModule (I2C) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT MIBSPI3NCS[2]/I2C_SDA /N2HET1[27]/nTZ2 B2 I/O PullUp Programmable, I2C serialdata,orGIO 20uAMIBSPI3NCS[3]/I2C_SCL /N2HET1[29]/nTZ1 C3 I2C serialclock,orGIO 2.3.2.11Standard SerialPeripheralInterface(SPI) Table2-35.ZWT Standard SerialPeripheralInterface(SPI) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT SPI2CLK E2 I/O PullUp Programmable, SPI2 clock,orGIO 20uASPI2NCS[0] N3 SPI2 chipselect,orGIO SPI2NENA/ SPI2NCS[1] D3 SPI2 chipselect,orGIO SPI2NENA /SPI2NCS[1] D3 SPI2 enable,orGIO SPI2SIMO D1 SPI2 slave-inputmaster- output,orGIO SPI2SOMI D2 SPI2 slave-outputmaster- input,orGIO N2HET1[0]/SPI4CLK /EPWM2B K18 I/O PullDown Programmable, SPI4 clock,orGIO 20uAN2HET1[03]/SPI4NCS[0]/USB2.SPEED/ U1 SPI4 chipselect,orGIO USB_FUNC.PUENON/N2HET2[10]/EQEP2B N2HET1[01]/SPI4NENA /USB2.TXEN/ V2 SPI4 enable,orGIO USB_FUNC.PUENO/N2HET2[8] N2HET1[02]/SPI4SIMO /EPWM3A W5 SPI4 slave-inputmaster- output,orGIO N2HET1[05]/SPI4SOMI /N2HET2[12]/EPWM3B V6 SPI4 slave-outputmaster- input,orGIO

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 2.3.2.12Multi-BufferedSerialPeripheralInterfaceModules (MibSPI) Table2-36.ZWT Multi-BufferedSerialPeripheralInterfaceModules (MibSPI) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT MIBSPI1CLK F18 I/O PullUp Programmable, MibSPI1 clock,orGIO 20uAMIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ R2 MibSPI1 chipselect,or USB1.RCV GIO MIBSPI1NCS[1]/N2HET1[17]/MII_COL/ F3 USB1.SUSPEND /EQEP1S MIBSPI1NCS[2]/N2HET1[19]/MDIO G3 MIBSPI1NCS[3]/N2HET1[21] J3 N2HET1[15]/MIBSPI1NCS[4] N1 PullDown Programmable, MibSPI1 chipselect,or 20uA GION2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] P1 MIBSPI1NENA /N2HET1[23]/MII_RXD[2]/ G19 PullUp Programmable, MibSPI1 enable,orGIO USB1.VP/ECAP4 20uA MIBSPI1SIMO F19 MibSPI1 slave-inmaster- out,orGIO N2HET1[08]/MIBSPI1SIMO[1]/MII_TXD[3]/USB1.OverCurrentE18 PullDown Programmable, MibSPI1 slave-inmaster- 20uA out,orGIO MIBSPI1SOMI G18 PullUp Programmable, MibSPI1 slave-outmaster- 20uA in,orGIOMIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ECAP6/ R2 USB1.RCV MIBSPI3CLK /AWM1_EXT_SEL[1]/EQEP1A V9 I/O PullUp Programmable, MibSPI3 clock,orGIO 20uAMIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I/N2HET2_PIN_nD V10 MibSPI3 chipselect,or IS GIO MIBSPI3NCS[1]/N2HET1[25]/MDCLK V5 MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2 B2 MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1 C3 N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ E3 PullDown Programmable, MibSPI3 chipselect,or USB2.OverCurrent/USB_FUNC.VBUSI/EPWM1SYNCO 20uA GIO MIBSPI3NENA/ MIBSPI3NCS[5]/N2HET1[31]/EQEP1B W9 PullUp Programmable, MibSPI3 chipselect,or 20uA GIO MIBSPI3NENA /MIBSPI3NCS[5]/N2HET1[31]/EQEP1B W9 MibSPI3 enable,orGIO MIBSPI3SIMO /AWM1_EXT_SEL[0]/ECAP3 W8 MibSPI3 slave-inmaster- out,orGIO MIBSPI3SOMI /AWM1_EXT_ENA/ECAP2 V8 MibSPI3 slave-outmaster- in,orGIO MIBSPI5CLK /MII_TXEN/RMII_TXEN H19 I/O PullUp Programmable, MibSPI5 clock,orGIO 20uAMIBSPI5NCS[0]/EPWM4A E19 MibSPI5 chipselect,or GIOMIBSPI5NCS[1] B6 MIBSPI5NCS[2] W6 MIBSPI5NCS[3] T12 MIBSPI5NENA MII_RXD[3]/ H18 MibSPI5 enable,orGIO USB1.VM/MIBSPI5SOMI[1]/ECAP5 MIBSPI5SIMO[0]/MII_TXD[1]/RMII_TXD[1] J19 MibSPI5 slave-inmaster- out,orGIOMIBSPI5SIMO[1] E16 MIBSPI5SIMO[2] H17 MIBSPI5SIMO[3] G17 MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0] J18 MIBSPI5SOMI[1] E17 MIBSPI5SOMI[2] H16 MIBSPI5SOMI[3] G16 Copyright© 2012,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 33 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com 2.3.2.13EthernetController Table2-37.ZWT EthernetController:MDIO Interface Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT MIBSPI3NCS[1]/N2HET1[25]/MDCLK V5 Output PullUp - Serialclockoutput MIBSPI1NCS[2]/N2HET1[19]/MDIO G3 I/O PullUp Fixed,20uA Serialdatainput/output Table2-38.ZWT EthernetController:Reduced Media IndependentInterface(RMII) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT N2HET1[12]/MII_CRS/RMII_CRS_DV B4 Input PullDown Fixed,20uA RMII carriersense and datavalid N2HET1[28]/MII_RX_CLK/RMII_REFCLK /MII_RX_AVCLK4 K19 RMII synchronous referenceclockfor receive,transmitand controlinterface AD1EVT/MII_RX_ER/ RMII_RX_ER N19 RMII receiveerror N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] P1 RMII receivedata N2HET1[26]/MII_RXD[1]/RMII_RXD[1] A14 MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0] J18 Output PullUp - RMII transmitdata MIBSPI5SIMO[0]/MII_TXD[1]/RMII_TXD[1] J19 MIBSPI5CLK//MII_TXEN/RMII_TXEN H19 RMII transmitenable Table2-39.ZWT EthernetController:Media IndependentInterface(MII) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT MIBSPI1NCS[1]/N2HET1[17]/MII_COL / F3 Input PullUp - Collisiondetect USB1.SUSPEND/EQEP1S N2HET1[12]/MII_CRS /RMII_CRS_DV B4 PullDown Fixed,20uA Carriersense and receive valid N2HET1[28]/MII_RXCLK/RMII_REFCLK/MII_RX_AVCLK4 K19 I/O PullDown - MIIoutputreceiveclock N2HET1[30]/MII_RX_DV /USB1.SPEED/EQEP2S B11 Input PullDown Fixed,20uA Receiveddatavalid AD1EVT/ MII_RX_ER /RMII_RX_ER N19 Receiveerror N2HET1[28]/MII_RX_CLK /RMII_REFCLK/MII_RX_AVCLK4 K19 I/O Receiveclock N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] P1 Input Receivedata N2HET1[26]/MII_RXD[1]/RMII_RXD[1] A14 MIBSPI1NENA/N2HET1[23]/MII_RXD[2]/ G19 PullUp Fixed,20uA USB1.VP/ECAP4 MIBSPI5NENA/ MII_RXD[3]/USB1.VM/MIBSPI5SOMI[1]/ECA H18 N2HET1[10]/MII_TX_CLK/USB1.TXEN/ D19 I/O PullDown - MIIoutputtransmitclock MII_TX_AVCLK4 /nTZ3 N2HET1[10]/MII_TX_CLK /USB1.TXEN D19 Transmitclock /MII_TX_AVCLK4/nTZ3

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Table2-39.ZWT EthernetController:Media IndependentInterface(MII)(continued) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0] J18 Output PullUp - Transmitdata MIBSPI5SIMO[0]/MII_TXD[1] J19 MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ R2 USB1.RCV N2HET1[08]/MIBSPI1SIMO[1]/MII_TXD[3]/ E18 PullDown - USB1.OverCurrent MIBSPI5CLK/MII_TXEN /RMII_TXEN H19 PullUp - Transmitenable Copyright© 2012,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 35 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com 2.3.2.14USB Host PortControllerInterface Table2-40.ZWT USB Host PortControllerInterface(USB1, USB2) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT N2HET1[08]/MIBSPI1SIMO[1]/MII_TXD[3]/ E18 Input PullDown Fixed,20uA Overcurrentindication USB1.OverCurrent fromUSB power switch MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ R2 PullUp Fixed,20uA ReceivedatafromUSB USB1.RCV porttransceiver MIBSPI5NENA/ MII_RXD[3]/USB1.VM /MIBSPI5SOMI[1]/ECA H18 NRZI encoded D-minus P5 fromUSB porttransceiver MIBSPI1NENA/N2HET1[23]/MII_RXD[2]/ G19 NRZI encoded D-plus USB1.VP /ECAP4 fromUSB porttransceiver GIOB[1]/USB1.PortPower K2 Output PullDown - N2HET1[30]/MII_RX_DV/USB1.SPEED /EQEP2S B11 Transmitspeed indication MIBSPI1NCS[1]/N2HET1[17]/MII_COL/ F3 PullUp - USB1.SUSPEND /EQEP1S GIOB[0]/USB1.TXDAT M2 PullDown - N2HET1[10]/MII_TX_CLK/USB1.TXEN / D19 Transmitenabletoport MII_TX_AVCLK4/nTZ3 transceiver N2HET1[14]/USB1.TXSE0 A11 Single-endedzerotoport transceiver N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ E3 Input PullDown Fixed,20uA USB2.OverCurrent/USB_FUNC.VBUSI/EPWM1SYNCO GIOB[3]/USB2.RCV /USB_FUNC.RXDI W10 PullDown Fixed,20uA GIOA[1]/USB2.VM /USB_FUNC.RXDMI C2 NRZI encoded D-minus fromUSB porttransceiver GIOA[0]/USB2.VP /USB_FUNC.RXDPI A5 NRZI encoded D-plus fromUSB porttransceiver N2HET1[07]/USB2.PortPower / T1 Output PullDown - USB_FUNC.GZO/N2HET2[14]/EPWM7B N2HET1[03]/SPI4NCS[0]/USB2.SPEED / U1 Transmitspeed indication USB_FUNC.PUENON/N2HET2[10]/EQEP2B N2HET1[09]/N2HET2[16]/USB2.SUSPEND / V7 Portsuspend indication USB_FUNC.SUSPENDO/EPWM7A GIOA[2]/USB2.TXDAT /USB_FUNC.TXDO/N2HET2[0]/EQEP C1 NRZI encoded D-plusto 2I porttransceiver N2HET1[01]/SPI4NENA/USB2.TXEN \\ V2 Transmitenabletoport USB_FUNC.PUENO/N2HET2[8] transceiver N2HET1[22]/USB2.TXSE0 /USB_FUNC.SE0O B3 Single-endedzerotoport transceiver Table2-41.ZWT USB Device PortControllerInterface(USB_FUNC) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT N2HET1[07]/USB2.PortPower/USB_FUNC.GZO /N2HET2[14]/ T1 Output PullDown - PullUp enable,allowsfor EPWM7B software-programmable USB device connect/disconnect N2HET1[01]/SPI4NENA/USB2.TXEN/ USB_FUNC.PUENO / V2 PUENO inverted N2HET2[8] N2HET1[03]/SPI4NCS[0]/USB2.SPEED/USB_FUNC.PUENO U1 N / N2HET2[10]/EQEP2B

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Table2-41.ZWT USB Device PortControllerInterface(USB_FUNC) (continued) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT GIOB[3]/USB2.RCV/USB_FUNC.RXDI W10 Input PullDown Fixed,20uA USB devicesingle-ended datainput GIOA[1]/USB2.VM/USB_FUNC.RXDMI C2 USB devicelogicvalueof D-minus GIOA[0]/USB2.VP/USB_FUNC.RXDPI A5 USB devicelogicvalueof D-plus N2HET1[22]/USB2.TXSE0/USB_FUNC.SE0O B3 Output PullDown - USB devicesingle-ended zero N2HET1[09]/N2HET2[16]/USB2.SUSPEND/USB_FUNC.SUS V7 USB devicesuspend PENDO /EPWM7A output GIOA[2]/USB2.TXDAT/USB_FUNC.TXDO /N2HET2[0]/EQEP C1 USB devicetransmitdata N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ E3 Input PullDown Fixed,20uA USB devicepower USB2.OverCurrent/USB_FUNC.VBUSI /EPWM1SYNCO connected Copyright© 2012,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 37 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com 2.3.2.15ExternalMemory Interface(EMIF) Table2-42.ExternalMemory Interface(EMIF) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT EMIF_CKE L3 Output PullDown - EMIF ClockEnable EMIF_CLK K3 I/O EMIF clock.Thisisan outputsignalinfunctional mode. Itisgatedoffby default,so thatthesignal istri-stated.PINMUX29[8] must be clearedtoenable thisoutput. EMIF_nWE/ EMIF_RNW D17 Output PullUp - EMIF Read-Not-Write EMIF_nOE E12 PullDown - EMIF Read Enable EMIF_nWAIT P3 I/O PullUp Fixed,20uA EMIF ExtendedWait Signal EMIF_nWE /EMIF_RNW D17 Output PullUp Programmable, EMIF WriteEnable. 20uAEMIF_nCAS R4 Output EMIF column address strobe EMIF_nRAS R3 Output EMIF row addressstrobe EMIF_nCS[0]/N2HET27 N17 Output PullDown EMIF chipselect, synchronous EMIF_nCS[2] L17 Output PullUp EMIF chipselects, asynchronousEMIF_nCS[3]/N2HET29 K17 Output PullDown Thisappliestochip EMIF_nCS[4] M17 Output PullUp selects2,3 and 4 EMIF_nDQM[0] E10 Output PullDown Programmable, EMIF Data Mask orWrite 20uA Strobe.EMIF_nDQM[1] E11 Output Data mask forSDRAM devices,writestrobefor connectedasynchronous devices. EMIF_BA[0] E13 Output EMIF bank addressor addressline EMIF_BA[1]/N2HET25 D16 Output EMIF bank addressor addressline EMIF_ADDR[0] /N2HET21 D4 Output EMIF address EMIF_ADDR[1] /N2HET23 D5 Output EMIF_ADDR[2] E6 Output EMIF_ADDR[3] E7 Output EMIF_ADDR[4] E8 Output EMIF_ADDR[5] E9 Output EMIF_ADDR[6] /NHET211 C4 Output EMIF_ADDR[7] /NHET213 C5 Output EMIF_ADDR[8] /NHET215 C6 Output EMIF_ADDR[9] C7 Output EMIF_ADDR[10] C8 Output EMIF_ADDR[11] C9 Output EMIF_ADDR[12] C10 Output (1) These signalsaretri-statedand pulleddown by defaultafterpower-up.Any applicationthatrequirestheEMIF must setthebit31 ofthe systemmodule general-purposeregisterGPREG1.

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Table2-42.ExternalMemory Interface(EMIF)(continued) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT EMIF_DATA[0] K15 I/O PullUp Fixed,20uA EMIF Data EMIF_DATA[1] L15 I/O EMIF_DATA[2] M15 I/O EMIF_DATA[3] N15 I/O EMIF_DATA[4] E5 I/O EMIF_DATA[5] F5 I/O EMIF_DATA[6] G5 I/O EMIF_DATA[7] K5 I/O EMIF_DATA[8] L5 I/O EMIF_DATA[9] M5 I/O EMIF_DATA[10] N5 I/O EMIF_DATA[11] P5 I/O EMIF_DATA[12] R5 I/O EMIF_DATA[13] R6 I/O EMIF_DATA[14] R7 I/O EMIF_DATA[15] R8 I/O Copyright© 2012,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 39 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com 2.3.2.16System Module Interface Table2-43.ZWT System Module Interface Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT nPORRST W7 Input PullDown 100uA Power-onreset,coldreset Externalpower supply monitorcircuitrymust drivenPORRST lowwhen any ofthesuppliestothe microcontrollerfalloutof thespecifiedrange.This terminalhas a glitchfilter. See Section4.8. nRST B17 I/O PullUp 100uA System reset,warm reset, bidirectional. The internalcircuitry indicatesany reset conditionby drivingnRST low. The externalcircuitrycan asserta systemresetby drivingnRST low.To ensurethatan external resetisnotarbitrarily generated,TI recommends thatan externalpull-upresistoris connectedtothisterminal. Thisterminalhas a glitch filter.See Section4.8. nERROR B14 I/O PullDown 20uA ESM ErrorSignal Indicateserrorofhigh severity.See Section4.18. 2.3.2.17Clock Inputsand Outputs Table2-44.ZWT Clock Inputsand Outputs Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT OSCIN K1 Input - - From external crystal/resonator,or externalclockinput KELVIN_GND L2 Input Kelvingroundforoscillator OSCOUT L1 Output To external crystal/resonator ECLK A12 I/O PullDown Programmable, Externalprescaledclock 20uA output,orGIO. GIOA[5]/EXTCLKIN /EPWM1A/N2HET1_PIN_nDIS B5 Input PullDown 20uA Externalclockinput#1 EXTCLKIN2 R9 Input Externalclockinput#2 VCCPLL P11 1.2V - Dedicatedcoresupplyfor Power PLL's

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 2.3.2.18Testand Debug Modules Interface Table2-45.ZWT Testand Debug Modules Interface Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT TEST U2 Input PullDown Fixed,100uA Testenable nTRST D18 Input JTAG testhardwarereset RTCK A16 Output - - JTAG returntestclock TCK B18 Input PullDown Fixed,100uA JTAG testclock TDI A17 Input PullUp JTAG testdatain TDO C18 Output PullDown JTAG testdataout TMS C19 Input PullUp JTAG testselect 2.3.2.19FlashSupply and TestPads Table2-46.ZWT FlashSupply and TestPads Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT VCCP F8 3.3V - - Flashpump supply Power FLTP1 J5 - - - Flashtestpads.These terminalsarereservedforFLTP2 H5 TIuse only.Forproper operationtheseterminals must connectonlytoa testpad ornotbe connectedatall[no connect(NC)]. 2.3.2.20No Connects Table2-47.No Connects Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT NC A8 - - - NC A15 - - - NC B8 - - - NC B9 - - - NC B15 - - - NC B16 - - - Copyright© 2012,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 41 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com Table2-47.No Connects (continued) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT NC C11 - - - No Connects.These balls arenotconnectedtoanyNC C12 - - - internallogicand can be NC C13 - - - connectedtothePCB groundwithoutaffectingNC C14 - - - thefunctionalityofthe NC C15 - - - device. NC C16 - - - NC C17 - - - NC D6 - - - NC D7 - - - NC D8 - - - NC D9 - - - NC D10 - - - NC D11 - - - NC D12 - - - NC D13 - - - NC D14 - - - NC D15 - - - NC E4 - - - NC F4 - - - NC F16 - - - NC F17 - - - NC G4 - - - NC K4 - - - NC K16 - - - NC L4 - - - NC L16 - - - NC M4 - - - NC M16 - - - NC N4 - - - NC N16 - - - NC N18 - - - NC P4 - NC P15 - - - NC P16 - - - NC P17 - - - NC R1 - - - NC R10 - - - NC R11 - - - NC R12 - - - NC R13 - - - NC R14 - - - NC R15 - - -

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Table2-47.No Connects (continued) Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT NC T2 - - - No Connects.These balls arenotconnectedtoanyNC T3 - - - internallogicand can be NC T4 - - - connectedtothePCB groundwithoutaffectingNC T5 - - - thefunctionalityofthe NC T6 - - - device. NC T7 - - - NC T8 - - - NC T9 - - - NC T10 - - - NC T11 - - - NC T13 - - - NC T14 - - - NC U3 - - - NC U4 - - - NC U5 - - - NC U6 - - - NC U7 - - - NC U8 - - - NC U9 - - - NC U10 - - - NC U11 - - - NC U12 - - - NC V3 - - - NC V4 - - - NC V11 - - - NC V12 - - - NC W4 - - - NC W13 - - - 2.3.2.21Supply forCore Logic:1.2Vnominal Table2-48.ZWT Supply forCore Logic:1.2Vnominal Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT VCC F9 1.2V - - Core supply PowerVCC F10 VCC H10 VCC J14 VCC K6 VCC K8 VCC K12 VCC K14 VCC L6 VCC M10 VCC P10 Copyright© 2012,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 43 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com 2.3.2.22Supply forI/OCells:3.3Vnominal Table2-49.ZWT Supply forI/OCells:3.3Vnominal Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT VCCIO F6 3.3V - - OperatingsupplyforI/Os PowerVCCIO F7 VCCIO F11 VCCIO F12 VCCIO F13 VCCIO F14 VCCIO G6 VCCIO G14 VCCIO H6 VCCIO H14 VCCIO J6 VCCIO L14 VCCIO M6 VCCIO M14 VCCIO N6 VCCIO N14 VCCIO P6 VCCIO P7 VCCIO P8 VCCIO P9 VCCIO P12 VCCIO P13 VCCIO P14

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 2.3.2.23Ground ReferenceforAllSuppliesExcept VCCAD Table2-50.ZWT Ground ReferenceforAllSuppliesExcept VCCAD Terminal Signal Default PullType Description Type PullStateSignalName 337 ZWT VSS A1 Ground - - Ground reference VSS A2 VSS A18 VSS A19 VSS B1 VSS B19 VSS H8 VSS H9 VSS H11 VSS H12 VSS J8 VSS J9 VSS J10 VSS J11 VSS J12 VSS K9 VSS K10 VSS K11 VSS L8 VSS L9 VSS L10 VSS L11 VSS L12 VSS M8 VSS M9 VSS M11 VSS M12 VSS V1 VSS W1 VSS W2 Copyright© 2012,Texas InstrumentsIncorporated DevicePackage and TerminalFunctions 45 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

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3 Device OperatingConditions

3.1 AbsoluteMaximum RatingsOver OperatingFree-AirTemperature Range, (1)

VCC (2) -0.3V to1.43V Supplyvoltagerange: VCCIO ,VCCP (2) -0.3V to4.1V VCCAD -0.3V to5.5V Allinputpins,withexceptionofADC pins -0.3V to4.1V Inputvoltagerange: ADC inputpins -0.3V to5.25V IIK (VI< 0 orVI> VCCIO ) ±20 mA Allpins,exceptAD1IN[23:0] Inputclamp current: IIK (VI< 0 orVI> VCCAD ) ±10 mA AD1IN[23:0] Total ±40 mA Operatingfree-airtemperaturerange,TA: -40°C to105°C Operatingjunctiontemperaturerange,TJ: -40°C to150°C Storagetemperaturerange,Tstg -65°C to150°C (1) Stressesbeyond thoselistedunder“absolutemaximum ratings”may cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunder“recommended operating conditions”isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) maximum-ratedconditionsforextendedperiodsmay affectdevicereliability.Allvoltagevaluesarewithrespecttotheirassociated grounds.

3.2 Device Recommended OperatingConditions(1)

VCC Digitallogicsupplyvoltage(Core) 1.14 1.2 1.32 V VCCPLL PLL SupplyVoltage 1.14 1.2 1.32 V VCCIO Digitallogicsupplyvoltage(I/O) 3 3.3 3.6 V VCCAD MibADC supplyvoltage 3 5.25 V VCCP Flashpump supplyvoltage 3 3.3 3.6 V VSS Digitallogicsupplyground 0 V VSSAD MibADC supplyground -0.1 0.1 V VADREFHI A-to-Dhigh-voltagereferencesource VSSAD VCCAD V VADREFLO A-to-Dlow-voltagereferencesource VSSAD VCCAD V TA Operatingfree-airtemperature -40 105 °C TJ Operatingjunctiontemperature -40 150 °C (1) AllvoltagesarewithrespecttoVSS ,exceptVCCAD ,whichiswithrespecttoVSSAD

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PRODUCT□PREVIEW Address□Waitstates Data□Waitstates RAM Address□Waitstates Data□Waitstates Flash 0MHz 0MHz 0MHz 0MHz 100MHz 0 1 3 150MHz 120MHz 200MHz 200MHz 200MHz 200MHz50MHz RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012

3.3 SwitchingCharacteristicsover Recommended OperatingConditionsforClock Domains

Table3-1.Clock Domain Timing Specifications Parameter Description Conditions Max Unit fHCLK HCLK -System clockfrequency Pipelinemode 200 MHz enabled Pipelinemode 50 MHz disabled fGCLK GCLK -CPU clockfrequency fHCLK MHz fVCLK VCLK -Primaryperipheralclockfrequency 100 MHz fVCLK2 VCLK2 -Secondaryperipheralclock 100 MHz frequency fVCLK3 VCLK3 -Secondaryperipheralclock 100 MHz frequency fVCLKA1 VCLKA1 -Primaryasynchronous 100 MHz peripheralclockfrequency fVCLKA2 VCLKA2 -Secondaryasynchronous 100 MHz peripheralclockfrequency fVCLKA3 VCLKA3 -Primaryasynchronous 100 MHz peripheralclockfrequency fVCLKA4 VCLKA4 -Secondaryasynchronous 100 MHz peripheralclockfrequency fRTICLK RTICLK -clockfrequency fVCLK MHz

3.4 Wait StatesRequired

Figure3-1.Wait StatesScheme As shown inthefigureabove,theTCM RAM can supportprogram and datafetchesatfullCPU speed without any addressordatawaitstatesrequired. The TCM flashcan supportzeroaddressand datawaitstatesup toa CPU speed of50MHz innon-pipelined mode. The flashsupportsa maximum CPU clockspeed of 200MHz inpipelinedmode withone addresswait stateand threedatawaitstates. The flashwrapperdefaultstonon-pipelinedmode withzeroaddresswaitstateand one random-readdatawait state. Copyright© 2012,Texas InstrumentsIncorporated DeviceOperatingConditions 47 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

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3.5 Power Consumption Over Recommended OperatingConditions

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fHCLK = 200MHz 350 forPGE PackageVCC digitalsupplycurrent(operatingmode) mAfVCLK = 100MHz, 375 forZWT Flash in pipelined Package400 mode, VCCmaxICC LBIST clock rate =VCC Digitalsupplycurrent(LBISTmode) mA 100MHz Peak PBIST ROM clock TBDVCC Digitalsupplycurrent mAfrequency= 100MHz(PBIST mode) RMS 240 ICCPLL VCCPLL digitalsupplycurrent(operatingmode) VCCPLL = VCCPLLmax 10 mA ICCIO VCCIO Digitalsupplycurrent(operatingmode. No DC load,VCCmax 15 mA SingleADC 15 operational, VCCADmax ICCAD VCCAD supplycurrent(operatingmode) mA BothADCs 30 operational, VCCADmax SingleADC 3 operational, AD REFHImax ICCREFHI AD REFHI supplycurrent(operatingmode) mA BothADCs 6 operational, AD REFHImax readoperation 34 VCCPmax program,VCCPmax 37 readfrom1 bank 55ICCP VCCP supplycurrent mA and program anotherbank, VCCPmax erase,VCCPmax 27

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3.6 Input/OutputElectricalCharacteristicsOver Recommended OperatingConditions(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vhys Inputhysteresis Allinputs 180 mV VIL Low-levelinputvoltage Allinputs -0.3 0.8 V VIH High-levelinputvoltage Allinputs 2 VCCIO + 0.3 V IOL = IOLmax 0.2VCCIO IOL = 50 µA,standard 0.2 outputmodeVOL Low-leveloutputvoltage V IOL = 50 µA,low-EMI 0.2VCCIO outputmode (see Section3.10) IOH = IOHmax 0.8VCCIO IOH = 50 µA,standard VCCIO -0.2 outputmodeVOH High-leveloutputvoltage V IOH = 50 µA,low-EMI 0.8VCCIO outputmode (see Section3.10) VI< VSSIO -0.3orVI -2 2IIC Inputclamp current(I/Opins) mA> VCCIO + 0.3 IIH Pulldown20µA VI= VCCIO 5 40 IIH Pulldown100µA VI= VCCIO 40 195 II Inputcurrent(I/Opins) IILPullup20µA VI= VSS -40 -5 µA IILPullup100µA VI= VSS -195 -40 Allotherpins No pulluporpulldown -1 1 C I Inputcapacitance 2 pF C O Outputcapacitance 3 pF (1) Sourcecurrents(outofthedevice)arenegativewhilesinkcurrents(intothedevice)arepositive. Copyright© 2012,Texas InstrumentsIncorporated DeviceOperatingConditions 49 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

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3.7 Output BufferDriveStrengths

Table3-2.Output BufferDriveStrengths Low-levelOutput Current, IOL forVI=VOLmax or Signals High-levelOutput Current, IOH forVI=VOHmin MIBSPI5CLK, MIBSPI5SOMI[0], MIBSPI5SOMI[1], MIBSPI5SOMI[2], MIBSPI5SOMI[3], MIBSPI5SIMO[0],MIBSPI5SIMO[1],MIBSPI5SIMO[2],MIBSPI5SIMO[3], TMS, TDI,TDO, RTCK, SPI4CLK, SPI4SIMO, SPI4SOMI, nERROR, N2HET2[1], N2HET2[3], N2HET2[5], N2HET2[7], N2HET2[9], N2HET2[11], N2HET2[13], N2HET2[15] ECAP1, ECAP4, ECAP5, ECAP6 EQEP1I, EQEP1S, EQEP2I, EQEP2S 8mA EPWM1A, EPWM1B, EPWM1SYNCO, ETPW2A, EPWM2B, EPWM3A, EPWM3B, EPWM4A, EPWM4B, EPWM5A, EPWM5B, EPWM6A, EPWM6B, EPWM7A, EPWM7B EMIF_ADDR[0:12],EMIF_BA[0:1],EMIF_CKE, EMIF_CLK, EMIF_DATA[0:15],EMIF_nCAS, EMIF_nCS[0:4],EMIF_nDQM[0:1], EMIF_nOE, EMIF_nRAS, EMIF_nWAIT, EMIF_nWE, EMIF_RNW MDCLK, MDIO, MII_RX_VCLKA4, MII_TX_VCLKA4, MII_TXD[0:3], MII_TXEN, RMII_REFCLK, RMII_TXD[0:1],RMII_TXEN USB_FUNC.SE0O, USB_FUNC.SUSPENDO, USB_FUNC.TXDO TEST, MIBSPI3SOMI, MIBSPI3SIMO, MIBSPI3CLK, MIBSPI1SIMO, MIBSPI1SOMI, MIBSPI1CLK,4mA ECAP2, ECAP3 nRST AD1EVT, CAN1RX, CAN1TX, CAN2RX, CAN2TX, CAN3RX, CAN3TX, GIOA[0-7],GIOB[0-7], LINRX, LINTX, 2mA zero-dominant MIBSPI1NCS[0], MIBSPI1NCS[1-3], MIBSPI1NENA, MIBSPI3NCS[0-3], MIBSPI3NENA, MIBSPI5NCS[0-3],MIBSPI5NENA, N2HET1[0-31],N2HET2[0], N2HET2[2], N2HET2[4], N2HET2[5], N2HET2[6], N2HET2[7], N2HET2[8],N2HET2[9],N2HET2[10],N2HET2[11],N2HET2[12],N2HET2[13],N2HET2[14], N2HET2[15],N2HET2[16],N2HET2[18], SPI2NCS[0],SPI2NENA ,SPI4NCS[0],SPI4NENA ECLK, selectable8mA /2mA SPI2CLK, SPI2SIMO, SPI2SOMI The defaultoutputbufferdrivestrengthis8mA forthesesignals.

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3.8 InputTimings

Figure3-2.TTL-LevelInputs Table3-3.Timing Requirements forInputs(1) Parameter MIN MAX Unit tpw Inputminimum pulsewidth tc(VCLK) + 10(2) ns tin_slew Time forinputsignaltogo fromVILtoVIH orfromVIH toVIL 1 ns (1) tc(VCLK) = peripheralVBUS clockcycletime= 1 /f(VCLK) (2) The timingshown above isonlyvalidforpinused ingeneral-purposeinputmode.

3.9 Output Timings

Table3-4.SwitchingCharacteristicsforOutput Timings versus Load Capacitance(CL) Parameter MIN MAX Unit Risetime,tr 8mA lowEMI pins CL = 15 pF 2.5 ns (seeTable3-2) CL = 50 pF 4 CL = 100 pF 7.2 CL = 150 pF 12.5 Falltime,tf CL = 15 pF 2.5 ns CL = 50 pF 4 CL = 100 pF 7.2 CL = 150 pF 12.5 Risetime,tr 4mA lowEMI pins CL = 15 pF 5.6 ns (seeTable3-2) CL = 50 pF 10.4 CL = 100 pF 16.8 CL = 150 pF 23.2 Falltime,tf CL = 15 pF 5.6 ns CL= 50 pF 10.4 CL = 100 pF 16.8 CL = 150 pF 23.2 Risetime,tr 2mA-z lowEMI pins CL = 15 pF 8 ns (seeTable3-2) CL = 50 pF 15 CL = 100 pF 23 CL = 150 pF 33 Falltime,tf CL = 15 pF 8 ns CL = 50 pF 15 CL = 100 pF 23 CL = 150 pF 33 Copyright© 2012,Texas InstrumentsIncorporated DeviceOperatingConditions 51 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW tftr VCCIO V OH VOH VOL VOL Output RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com Table3-4.SwitchingCharacteristicsforOutput Timings versus Load Capacitance(CL)(continued) Parameter MIN MAX Unit Risetime,tr Selectable8mA /2mA-z 8mA mode CL = 15 pF 2 ns pins CL = 50 pF 4(seeTable3-2) CL = 100 pF 8 CL = 150 pF 11 Falltime,tf CL = 15 pF 2 ns CL = 50 pF 4 CL = 100 pF 8 CL = 150 pF 11 Risetime,tr 2mA-z mode CL = 15 pF 8 ns CL = 50 pF 15 CL = 100 pF 23 CL = 150 pF 33 Falltime,tf CL = 15 pF 8 ns CL = 50 pF 15 CL = 100 pF 23 CL = 150 pF 33 Figure3-3.CMOS-Level Outputs Table3-5.Timing Requirements forOutputs(1) Parameter MIN MAX UNIT td(parallel_out) Delaybetween lowtohigh,orhightolowtransitionofgeneral-purposeoutputsignals 6 ns thatcan be configuredby an applicationinparallel,e.g.allsignalsina GIOA port,or allN2HET1 signals,etc. (1) Thisspecificationdoes notaccountforany outputbufferdrivestrengthdifferencesorany externalcapacitiveloadingdifferences.Check Table3-2foroutputbufferdrivestrengthinformationon each signal.

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3.10 Low-EMI Output Buffers

The low-EMI outputbufferhas been designedexplicitlyto addressthe issueof decouplingsourcesof emissionsfromthepinswhichtheydrive.Thisisaccomplishedby adaptivelycontrollingtheimpedance of theoutputbuffer,and isparticularlyeffectivewithcapacitiveloads. Thisisnotthedefaultmode ofoperationofthelow-EMIoutputbuffersand must be enabledby settingthe system module GPCR1 registerforthedesiredmodule orsignal,as shown in.The adaptiveimpedance controlcircuitmonitorsthe DC bias pointof the outputsignal.The bufferinternallygeneratestwo referencelevels,VREFLOW and VREFHIGH, which are setto approximately10% and 90% of VCCIO, respectively. Once theoutputbufferhas driventheoutputtoa low level,iftheoutputvoltageisbelow VREFLOW, then the outputbuffer’s impedance willincreaseto hi-Z.A high degree of decouplingbetween the internal groundbus and theoutputpinwilloccurwithcapacitiveloads,orany loadinwhichno currentisflowing, e.g.thebufferisdrivinglowon a resistivepathtoground.Currentloadson thebufferwhichattempttopull theoutputvoltageabove VREFLOW willbe opposed by thebuffer’s outputimpedance so as tomaintain theoutputvoltageatorbelowVREFLOW. Conversely,once the outputbufferhas driventhe outputto a highlevel,ifthe outputvoltageisabove VREFHIGH thentheoutputbuffer’s impedance willagainincreasetohi-Z.A highdegree ofdecoupling between internalpower bus ad outputpinwilloccurwithcapacitiveloadsorany loadsinwhichno current isflowing,e.g.bufferisdrivinghighon a resistivepath to VCCIO. Currentloadson the bufferwhich attempttopulltheoutputvoltagebelow VREFHIGH willbe opposed by thebuffer’s outputimpedance so as tomaintaintheoutputvoltageatorabove VREFHIGH. The bandwidthof the controlcircuitryisrelativelylow,so thatthe outputbufferinadaptiveimpedance controlmode cannot respond to high-frequencynoisecouplingintothe buffer’s power buses.In this manner,internalbus noiseapproaching20% peak-to-peakofVCCIO can be rejected. Unlikestandardoutputbufferswhich clamp totherails,an outputbufferinimpedance controlmode will allowa positivecurrentloadto pullthe outputvoltageup to VCCIO + 0.6V withoutopposition.Also,a negativecurrentloadwillpulltheoutputvoltagedown toVSSIO – 0.6V withoutopposition.Thisisnotan issuesincetheactualclamp currentcapabilityisalwaysgreaterthantheIOH /IOL specifications. The low-EMI outputbuffersare automaticallyconfiguredto be in the standardbuffermode when the deviceentersa low-powermode. Table3-6.Low-EMI Output BufferHookup Module or SignalName ControlRegistertoEnable Low-EMI Mode Module:MibSPI1 GPREG1.0 Module:SPI2 GPREG1.1 Module:MibSPI3 GPREG1.2 Reserved GPREG1.3 Module:MibSPI5 GPREG1.4 Reserved GPREG1.5 Module:EMIF GPREG1.6 Reserved GPREG1.7 Signal:TMS GPREG1.8 Signal:TDI GPREG1.9 Signal:TDO GPREG1.10 Signal:RTCK GPREG1.11 Signal:TEST GPREG1.12 Signal:nERROR GPREG1.13 Signal:AD1EVT GPREG1.14 Copyright© 2012,Texas InstrumentsIncorporated DeviceOperatingConditions 53 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

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4 System Informationand ElectricalSpecifications

4.1 Device Power Domains

The devicecorelogicissplitup intomultiplepower domains inordertooptimizethepower fora given applicationuse case.There are 6 core power domains intotal:PD1, PD2, PD3, PD5, RAM_PD1, and RAM_PD2. RefertoSection1.4formore information. PD1 isan "always-ON"power domain,whichcannotbe turnedoff.Each oftheothercorepower domains can be turnedON/OFF one timeduringdeviceinitializationas per theapplicationrequirement.Referto thePower Management Module (PMM) chapterofthedevicetechnicalreferencemanual formore details. NOTE The clocksto a module must be turnedoffbeforepoweringdown the core domain that containsthemodule. NOTE The logicinthemodules thatare powered down losesitspower completely.Any access to modules thatare powered down resultsin an abortbeing generated.When power is restored,themodules power-uptotheirdefaultstates(afternormalpower-up).No registeror memory contentsarepreservedinthecoredomains thatareturnedoff.

4.2 VoltageMonitorCharacteristics

A voltagemonitorisimplementedon thisdevice.The purposeofthisvoltagemonitoristoeliminatethe requirementfora specificsequence when poweringup thecoreand I/Ovoltagesupplies.

4.2.1 ImportantConsiderations

• The voltagemonitordoes noteliminatetheneed ofa voltagesupervisorcircuittoguaranteethatthe deviceisheldinresetwhen thevoltagesuppliesareoutofrange.
• The voltagemonitoronlymonitorsthe core supply(VCC) and the I/O supply(VCCIO). The other suppliesare notmonitoredby theVMON. For example,iftheVCCAD or VCCP are suppliedfrom a sourcedifferentfrom thatforVCCIO, then thereisno internalvoltagemonitorforthe VCCAD and VCCP supplies.

4.2.2 VoltageMonitorOperation

The voltagemonitorgeneratesthePower Good MCU signal(PGMCU) as wellas theI/OsPower Good IO signal(PGIO)on thedevice.Duringpower-uporpower-down,thePGMCU and PGIO aredrivenlowwhen the core or I/O suppliesare lowerthan the specifiedminimum monitoringthresholds.The PGIO and PGMCU beinglow isolatesthecorelogicas wellas theI/Ocontrolsduringthepower-uporpower-down ofthesupplies.Thisallowsthecoreand I/Osuppliestobe powered up ordown inany order. When thevoltagemonitordetectsa low voltageon theI/Osupply,itwillasserta power-onreset.When thevoltagemonitordetectsan out-of-rangevoltageon thecoresupply,itasynchronouslymakes alloutput pinshighimpedance,and assertsa power-on reset.The voltagemonitorisdisabledwhen the device entersa lowpower mode. The VMON alsoincorporatesa glitchfilterforthenPORRST input.RefertoSection4.3.3.1forthetiming informationon thisglitchfilter.

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Table4-1.VoltageMonitoringSpecifications PARAMETER MIN TYP MAX UNIT VCC low-VCC levelbelowthis 0.8 0.9 1.0 V thresholdisdetectedas toolow. Voltagemonitoring VCC high-VCC levelabove this 1.40 1.7 2.1VMON thresholds thresholdisdetectedas toohigh. VCCIO low-VCCIO levelbelowthis 1.9 2.4 2.9 thresholdisdetectedas toolow.

4.2.3 Supply Filtering

The VMON has thecapabilitytofilterglitcheson theVCC and VCCIO supplies. The followingtableshows thecharacteristicsofthesupplyfiltering.Glitchesinthesupplylargerthanthe maximum specificationcannotbe filtered. Table4-2.VMON Supply GlitchFilteringCapability Parameter MIN MAX Widthofglitchon VCC thatcan be filtered 250ns 1us Widthofglitchon VCCIO thatcan be filtered 250ns 1us Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 55 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

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4.3 Power Sequencing and Power On Reset

4.3.1 Power-Up Sequence

There isno timingdependency between theramp oftheVCCIO and theVCC supplyvoltage.The power- up sequence startswiththeI/Ovoltagerisingabove theminimum I/Osupplythreshold,(seeTable4-4for more details),corevoltagerisingabove theminimum coresupplythresholdand thereleaseofpower-on reset.The highfrequencyoscillatorwillstartup firstand itsamplitudewillgrow toan acceptablelevel.The oscillatorstartup timeisdependenton thetypeofoscillatorand isprovidedby theoscillatorvendor.The differentsuppliestothedevicecan be powered up inany order. The devicegoes throughthefollowingsequentialphases duringpower up. Table4-3.Power-Up Phases Oscillatorstart-upand validitycheck 1032 oscillatorcycles eFuse autoload 1160 oscillatorcycles Flashpump power-up 688 oscillatorcycles Flashbank power-up 617 oscillatorcycles Total 3497 oscillatorcycles The CPU resetisreleasedattheend oftheabove sequence and fetchesthefirstinstructionfromaddress 0x00000000.

4.3.2 Power-Down Sequence

The differentsuppliestothedevicecan be powered down inany order.

4.3.3 Power-On Reset:nPORRST

Thisisthepower-onreset.Thisresetmust be assertedby an externalcircuitrywhenever theI/Oorcore suppliesareoutsidethespecifiedrecommended range.Thissignalhas a glitchfilteron it.Italsohas an internalpulldown. 4.3.3.1 nPORRST Electricaland Timing Requirements Table4-4.ElectricalRequirements fornPORRST NO Parameter MIN MAX Unit VCCPORL VCC lowsupplylevelwhen nPORRST must be activeduringpower- 0.5 V up VCCPORH VCC highsupplylevelwhen nPORRST must remainactiveduring 1.14 V power-upand become activeduringpower down VCCIOPORL VCCIO /VCCP lowsupplylevelwhen nPORRST must be activeduring 1.1 V power-up VCCIOPORH VCCIO /VCCP highsupplylevelwhen nPORRST must remainactive 3.0 V duringpower-upand become activeduringpower down VIL(PORRST) Low-levelinputvoltageofnPORRST VCCIO > 2.5V 0.2*VCCIO V Low-levelinputvoltageofnPORRST VCCIO < 2.5V 0.5 V 3 tsu(PORRST) Setuptime,nPORRST activebeforeVCCIO and VCCP > VCCIOPORL 0 ms duringpower-up 6 th(PORRST) Holdtime,nPORRST activeafterVCC > VCCPORH 1 ms 7 tsu(PORRST) Setuptime,nPORRST activebeforeVCC < VCCPORH duringpower 2 µs down 8 th(PORRST) Holdtime,nPORRST activeafterVCCIO and VCCP > VCCIOPORH 1 ms 9 th(PORRST) Holdtime,nPORRST activeafterVCC < VCCPORL 0 ms

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3.3 V VCCIOPORH

1.2 V VCCPORH VCCIOPORL V (1.2 V) V / V (3.3 V) CC CCIO CCP nPORRST 6 6 VCCPORL VIL(PORRST) V / VCCIO CCP VCC VCCPORL VIL(PORRST)VIL VIL VIL VCCIOPORH VCCPORH VCCIOPORL NOTE: There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage; this is just an exemplary drawing. RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Table4-4.ElectricalRequirements fornPORRST (continued) NO Parameter MIN MAX Unit tf(nPORRST) 500 2000 nsFiltertimenPORRST pin; pulseslessthan MIN willbe filteredout,pulsesgreaterthan MAX willgeneratea reset. Figure4-1.nPORRST Timing Diagram Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 57 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

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4.4 Warm Reset (nRST)

Thisisa bidirectionalresetsignal.The internalcircuitrydrivesthesignallow on detectingany devicereset condition.An externalcircuitcan asserta deviceresetby forcingthe signallow.On thisterminal,the outputbufferisimplementedas an open drain(driveslow only).To ensure an externalresetisnot arbitrarilygenerated,TIrecommends thatan externalpullupresistorisconnectedtothisterminal. Thisterminalhas a glitchfilter.Italsohas an internalpullup

4.4.1 Causes ofWarm Reset

Table4-5.Causes ofWarm Reset DEVICE EVENT SYSTEM STATUS FLAG Power-Up Reset ExceptionStatusRegister,bit15 Oscillatorfail GlobalStatusRegister,bit0 PLL slip GlobalStatusRegister,bits8 and 9 Watchdog exception/Debugger reset ExceptionStatusRegister,bit13 CPU Reset(drivenby theCPU STC) ExceptionStatusRegister,bit5 SoftwareReset ExceptionStatusRegister,bit4 ExternalReset ExceptionStatusRegister,bit3 4.4.2 nRST Timing Requirements Table4-6.nRST Timing Requirements(1) PARAMETER MIN MAX UNIT tv(RST) Validtime,nRST activeafter 1160 tc(OSC) + 1048tc(OSC) ns nPORRST inactive Validtime,nRST active(allother 8tc(VCLK) System resetconditions) tf(nRST) 500 2000 nsFiltertimenRST pin; pulses less than MIN willbe filteredout,pulsesgreaterthan MAX willgeneratea reset (1) Specifiedvaluesdo NOT includerise/falltimes.Forriseand falltimings,see Table3-4.

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4.5 ARM © Cortex-R4F™ CPU Information

4.5.1 Summary ofARM Cortex-R4F™ CPU Features

The featuresoftheARM Cortex-R4F™ CPU include:

• An integerunitwithintegralEmbeddedICE-RT logic.
• High-speedAdvanced MicroprocessorBus Architecture(AMBA) Advanced eXtensibleInterfaces(AXI) forLeveltwo (L2)masterand slaveinterfaces.
• FloatingPointCoprocessor
• Dynamic branchpredictionwitha globalhistorybuffer,and a 4-entryreturnstack
• Low interruptlatency.
• Non-maskableinterrupt.
• A HarvardLevelone (L1)memory systemwith: – Tightly-CoupledMemory (TCM) interfaceswith supportforerrorcorrectionor paritychecking memories – ARMv7-R architectureMemory ProtectionUnit(MPU) with12 regions
• Dualcorelogicforfaultdetectioninsafety-criticalapplications.
• An L2 memory interface: – Single64-bitmasterAXI interface – 64-bitslaveAXI interfacetoTCM RAM blocks
• A debug interfacetoa CoreSightDebug Access Port(DAP).
• A PerformanceMonitoringUnit(PMU).
• A VectoredInterruptController(VIC)port. Formore informationon theARM Cortex-R4F™ CPU pleasesee www.arm.com .

4.5.2 ARM Cortex-R4F™ CPU FeaturesEnabled by Software

The followingCPU featuresaredisabledon resetand must be enabledby theapplicationifrequired.

• ECC On Tightly-CoupledMemory (TCM) Accesses
• Hardware VectoredInterrupt(VIC)Port
• FloatingPointCoprocessor
• Memory ProtectionUnit(MPU)

4.5.3 Dual Core Implementation

The devicehas two Cortex-R4Fcores,where theoutputsignalsofbothCPUs arecompared intheCCM- R4 unit.To avoidcommon mode impactsthesignalsoftheCPUs tobe compared aredelayedby 2 clock cyclesas shown inFigure4-3. The CPUs have a diverseCPU placementgivenby followingrequirements:

• differentorientation;e.g.CPU1 = "north"orientation,CPU2 = "flipwest"orientation
• dedicatedguardringforeach CPU Figure4-2.Dual -CPU Orientation Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 59 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

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4.5.4 DuplicateclocktreeafterGCLK

The CPU clockdomain issplitintotwo clocktrees,one foreach CPU, withthe clockof the 2nd CPU runningatthesame frequencyand inphase totheclockofCPU1. See Figure4-3.

4.5.5 ARM Cortex-R4F™ CPU Compare Module (CCM) forSafety

Thisdevicehas two ARM Cortex-R4F™ CPU cores,where theoutputsignalsofbothCPUs arecompared intheCCM-R4 unit.To avoidcommon mode impactsthesignalsoftheCPUs tobe compared aredelayed ina differentway as shown inthefigurebelow. Figure4-3.Dual Core Implementation To avoidan erroneousCCM-R4 compare error,the applicationsoftwaremust initializethe registersof both CPUs beforethe registersare used,includingfunctioncallswhere the registervaluesare pushed ontothestack.

4.5.6 CPU Self-Test

The CPU STC (Self-TestController)is used to testthe two Cortex-R4F CPU Cores using the DeterministicLogicBIST Controlleras thetestengine. The main featuresoftheself-testcontrollerare:

• Abilitytodividethecompletetestrunintoindependenttestintervals
• Capableofrunningthecompletetestas wellas runningfew intervalsata time
• Abilityto continuefrom the lastexecuted interval(testset)as wellas abilityto restartfrom the beginning(Firsttestset)
• Completeisolationoftheself-testedCPU corefromrestofthesystemduringtheself-testrun
• AbilitytocapturetheFailureintervalnumber
• TimeoutcounterfortheCPU self-testrunas a fail-safefeature

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4.5.6.1 ApplicationSequence forCPU Self-Test

1. Configureclockdomain frequencies. 2. Selectnumber oftestintervalstobe run. 3. Configurethetimeoutperiodfortheself-testrun. 4. Enableself-test. 5. WaitforCPU reset. 6. Intheresethandler,readCPU self-teststatustoidentifyany failures. 7. RetrieveCPU stateifrequired. Formore informationsee thedeviceTechnicalReferenceManual.

4.5.6.2 CPU Self-TestClock Configuration

The maximum clockratefortheself-testis100MHz. The STCCLK isdivideddown from theCPU clock. Thisdividerisconfiguredby theSTCCLKDIV registerataddress0xFFFFE108. Formore informationsee thedeviceTechnicalReferenceManual.

4.5.6.3 CPU Self-TestCoverage

Table4-7 shows CPU testcoverageachievedforeach self-testinterval.Italsoliststhecumulativetest cycles.The testtimecan be calculatedby multiplyingthenumber oftestcycleswiththeSTC clockperiod. Table4-7.CPU Self-TestCoverage INTERVALS TEST COVERAGE, % TEST CYCLES 0 0 0 1 62.13 1365 2 70.09 2730 3 74.49 4095 4 77.28 5460 5 79.28 6825 6 80.90 8190 7 82.02 9555 8 83.10 10920 9 84.08 12285 10 84.87 13650 11 85.59 15015 12 86.11 16380 13 86.67 17745 14 87.16 19110 15 87.61 20475 16 87.98 21840 17 88.38 23205 18 88.69 24570 19 88.98 25935 20 89.28 27300 21 89.50 28665 22 89.76 30030 23 90.01 31395 24 90.21 32760 Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 61 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW OSCIN OSCOUT (see Note A) Crystal (a) OSCIN OSCOUT (b) External (toggling 0-3.3V) Clock Signal Note A: The values of C1 and C2 should be provided by the resonator/crystal vendor. Kelvin_GND Note B: Kelvin_GND should not be connected to any other GND. (see Note B) RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com

4.6 Clocks

4.6.1 Clock Sources

The tablebelow liststheavailableclocksourceson thedevice.Each oftheclocksourcescan be enabled or disabledusingthe CSDISx registersin the system module. The clocksource number in the table correspondstothecontrolbitintheCSDISx registerforthatclocksource. The tablealsoshows thedefaultstateofeach clocksource. Table4-8.AvailableClock Sources Clock Name Description DefaultStateSource #

0 OSCIN Main Oscillator Enabled

1 PLL1 OutputFrom PLL1 Disabled

2 Reserved Reserved Disabled

3 EXTCLKIN1 ExternalClockInput#1 Disabled

4 LFLPO Low FrequencyOutputofInternalReferenceOscillator Enabled

HighFrequencyOutputofInternalReference5 HFLPO EnabledOscillator

6 PLL2 OutputFrom PLL2 Disabled

7 EXTCLKIN2 ExternalClockInput#2 Disabled

4.6.1.1 Main Oscillator

The oscillatorisenabledby connectingtheappropriatefundamentalresonator/crystaland loadcapacitors acrossthe externalOSCIN and OSCOUT pinsas shown inFigure4-4. The oscillatorisa singlestage inverterheld in bias by an integratedbias resistor.This resistoris disabledduringleakage test measurement and lowpower modes. TI stronglyencourages each customer to submit samples of the device to the resonator/crystal vendors forvalidation.The vendors are equipped to determinewhat load capacitorswillbest tune theirresonator/crystalto the microcontrollerdevice for optimum start-upand operation over temperature/voltageextremes. An externaloscillatorsourcecan be used by connectinga 3.3V clocksignaltotheOSCIN pinand leaving theOSCOUT pinunconnected(open)as shown inthefigurebelow. Figure4-4.Recommended Crystal/ClockConnection

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 4.6.1.1.1Timing Requirements forMain Oscillator Table4-9.Timing Requirements forMain Oscillator Parameter MIN Type MAX Unit tc(OSC) Cycletime,OSCIN (when usinga sine-waveinput) 50 200 ns tc(OSC_SQR) Cycletime,OSCIN, (when inputtotheOSCIN isa 12.5 200 ns squarewave ) tw(OSCIL) Pulseduration,OSCIN low(when inputtotheOSCIN 15 ns isa squarewave) tw(OSCIH) Pulseduration,OSCIN high(when inputtotheOSCIN 15 ns isa squarewave) Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 63 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW BIAS_EN Low Power Oscillator LFEN LF_TRIM HFEN HF_TRIM LFLPO HFLPO HFLPO_V ALID nPORRST RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com

4.6.1.2 Low Power Oscillator

The Low Power Oscillator(LPO) iscomprisedof two oscillators— HF LPO and LF LPO, ina single macro. 4.6.1.2.1Features The main featuresoftheLPO are:

• Suppliesa clockatextremelylow power forpower-savingmodes. Thisisconnectedas clocksource# 4 oftheGlobalClockModule.
• Suppliesa high-frequencyclockfornon-timing-criticalsystems.Thisisconnectedas clocksource# 5 oftheGlobalClockModule.
• Providesa comparisonclockforthecrystaloscillatorfailuredetectioncircuit. Figure4-5.LPO Block Diagram Figure4-5shows a blockdiagramoftheinternalreferenceoscillator.Thisisa low power oscillator(LPO) and providestwo clocksources:one nominally80KHz and one nominally10MHz. Table4-10.LPO Specifications Parameter MIN Typical MAX Unit ClockDetection oscillatorfailfrequency-lowerthreshold,using 1.375 2.4 4.875 MHz untrimmedLPO output oscillatorfailfrequency-higherthreshold,using 22 38.4 78 MHz untrimmedLPO output LPO -HF oscillator untrimmedfrequency 5.5 9.6 19.5 MHz startuptimefromSTANDBY (LPO BIAS_EN Highfor 10 µs atleast900µs) coldstartuptime 900 µs LPO -LF oscillator untrimmedfrequency 36 85 180 kHz startuptimefromSTANDBY (LPO BIAS_EN Highfor 100 µs atleast900µs) coldstartuptime 2000 µs

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PRODUCT□PREVIEW /NR /1 to /64 OSCIN PLL INTCLK /OD /1 to /8 VCOCLK /R /1 to /32 post_ODCLK /NF /1 to /256 PLLCLK /NR2 /1 to /64 OSCIN PLL#2 INTCLK2 /OD2 /1 to /8 VCOCLK2 /R2 /1 to /32 post_ODCLK2 /NF2 /1 to /256 PLL2CLK fPLLCLK = (fOSCIN / NR) * NF / (OD * R) fPLL2CLK = (fOSCIN / NR2) * NF2 / (OD2 * R2) RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012

4.6.1.3 Phase Locked Loop (PLL)Clock Modules

The PLL isused tomultiplytheinputfrequencytosome higherfrequency. The main featuresofthePLL are:

• Frequency modulationcan be optionallysuperimposedon the synthesizedfrequencyof PLL1. The frequencymodulationcapabilityofPLL2 ispermanentlydisabled.
• Configurablefrequencymultipliersand dividers.
• Built-inPLL Slipmonitoringcircuit.
• Optiontoresetthedeviceon a PLL slipdetection. 4.6.1.3.1Block Diagram Figure4-6shows a high-levelblockdiagramofthetwo PLL macros on thismicrocontroller.PLLCTL1 and PLLCTL2 areused toconfigurethemultiplierand dividersforthePLL1. PLLCTL3 isused toconfigurethe multiplierand dividersforPLL2. Figure4-6.PLLx Block Diagram 4.6.1.3.2PLL Timing Specifications Table4-11.PLL Timing Specifications PARAMETER MIN MAX UNIT fINTCLK PLL1 ReferenceClockfrequency 1 f(OSC_SQR) MHz fpost_ODCLK Post-ODCLK – PLL1 Post-dividerinput 400 MHz clockfrequency fVCOCLK VCOCLK – PLL1 OutputDivider(OD) input 150 550 MHz clockfrequency fINTCLK2 PLL2 ReferenceClockfrequency 1 f(OSC_SQR) MHz fpost_ODCLK2 Post-ODCLK – PLL2 Post-dividerinput 400 MHz clockfrequency fVCOCLK2 VCOCLK – PLL2 OutputDivider(OD) input 150 550 MHz clockfrequency Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 65 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

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4.6.1.4 ExternalClock Inputs

The devicesupportsup totwo externalclockinputs.Thisclockinputmust be a squarewave input.The electricaland timingrequirementsfortheseclockinputsarespecifiedbelow. Table4-12.ExternalClock Timing and ElectricalSpecifications Parameter Description Min Max Unit fEXTCLKx Externalclockinputfrequency 80 MHz tw(EXTCLKIN)H EXTCLK high-pulseduration 6 ns tw(EXTCLKIN)L EXTCLK low-pulseduration 6 ns viL(EXTCLKIN) Low-levelinputvoltage -0.3 0.8 V viH(EXTCLKIN) High-levelinputvoltage 2 VCCIO + 0.3 V

4.6.2 Clock Domains

4.6.2.1 Clock Domain Descriptions

The tablebelow liststhedeviceclockdomains and theirdefaultclocksources.The tablealsoshows the systemmodule controlregisterthatisused toselectan availableclocksourceforeach clockdomain. Table4-13.Clock Domain Descriptions Clock Domain Name DefaultClock Clock Source Description Source SelectionRegister HCLK OSCIN GHVSRC • IsdisabledviatheCDDISx registersbit1

• Used forallsystemmodules includingDMA, ESM GCLK OSCIN GHVSRC • Alwaysthesame frequencyas HCLK
• Inphase withHCLK
• IsdisabledseparatelyfromHCLK viatheCDDISx registersbit0
• Can be dividedby 1up to8 when runningCPU self-test(LBIST) usingtheCLKDIV fieldoftheSTCCLKDIV registerataddress 0xFFFFE108 GCLK2 OSCIN GHVSRC • Alwaysthesame frequencyas GCLK
• 2 cyclesdelayedfromGCLK
• IsdisabledalongwithGCLK
• Gets dividedby thesame dividersettingas thatforGCLK when runningCPU self-test(LBIST) VCLK OSCIN GHVSRC • Divideddown fromHCLK
• Can be HCLK/1, HCLK/2, ...orHCLK/16
• IsdisabledseparatelyfromHCLK viatheCDDISx registersbit2 VCLK2 OSCIN GHVSRC • Divideddown fromHCLK
• Can be HCLK/1, HCLK/2, ...orHCLK/16
• Frequencymust be an integermultipleofVCLK frequency
• IsdisabledseparatelyfromHCLK viatheCDDISx registersbit3 VCLK3 OSCIN GHVSRC • Divideddown fromHCLK
• Can be HCLK/1, HCLK/2, ...orHCLK/16
• IsdisabledseparatelyfromHCLK viatheCDDISx registersbit8 VCLK4 OSCIN GHVSRC • Divideddown fromHCLK
• Can be HCLK/1, HCLK/2, ...orHCLK/16
• IsdisabledseparatelyfromHCLK viatheCDDISx registersbit9 VCLKA1 VCLK VCLKASRC • DefaultstoVCLK as thesource
• IsdisabledviatheCDDISx registersbit4 VCLKA2 VCLK VCLKASRC • DefaultstoVCLK as thesource
• IsdisabledviatheCDDISx registersbit5

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Table4-13.Clock Domain Descriptions(continued) Clock Domain Name DefaultClock Clock Source Description Source SelectionRegister VCLKA3_S VCLK VCLKACON • DefaultstoVCLK as thesource

• Frequencycan be as fastas HCLK frequency.
• IsdisabledviatheCDDISx registersbit10 VCLKA3_DIVR VCLK VCLKACON1 • Divideddown fromtheAVCLK3_S usingtheVCLKA3R fieldof theVCLKACON1 registerataddress0xFFFFE140
• Frequencycan be VCLKA3_S/1, VCLKA3_S/2, ...,or VCLKA3_S/8
• DefaultfrequencyisVCLKA3_S/2
• IsdisabledseparatelyviatheVCLKACON1 register VCLKA3_DIV_CDDIS bitonlyiftheVCLKA3_S clockisnot disabled VCLKA4_S VCLK VCLKACON1 • DefaultstoVCLK as thesource
• Frequencycan be as fastas HCLK frequency
• IsdisabledviatheCDDISx registersbit11 VCLKA4_DIVR VCLK VCLKACON1 • Divideddown fromtheVCLKA4_S usingtheVCLKA4R fieldof theVCLKACON1 registerataddress0xFFFFE140
• Frequencycan be VCLKA4_S/1, VCLKA4_S/2, ...,or VCLKA4_S/8
• DefaultfrequencyisVCLKA4_S/2
• IsdisabledseparatelyviatheVCLKACON1 register VCLKA4_DIV_CDDIS bitonlyiftheVCLKA4_S clockisnot disabled RTICLK VCLK RCLKSRC • DefaultstoVCLK as thesource
• Ifa clocksourceotherthanVCLK isselectedforRTICLK, then theRTICLK frequencymust be lessthanorequaltoVCLK/3 – Applicationcan ensurethisby programmingtheRTI1DIV fieldoftheRCLKSRC register,ifnecessary
• IsdisabledviatheCDDISx registersbit6 Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 67 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW HCLK (to□SYSTEM) GCLK,□GCLK2 (to□CPU) GCM VCLK_peri (VCLK to peripherals on□PCR1) VCLK2□(to□N2HETx and□HTUx) /1..16 /1..16 OSCIN Low□Power Oscillator 10MHz 80kHz PLL #□2 /1,2,..256 SPIx,MibSPIx /2,3..224 LIN,□SCI SPI LIN /□SCI /1,2..32 MibADCx ADCLK /1,2..65536 External□Clock ECLK VCLK2 N2HETx HRP /1..64 LRP /20..25 Loop Resolution□Clock High Baud□Rate Baud□Rate VCLK2 Ethernet VCLKA4_DIVR EXTCLKIN1 EXTCLKIN2 VCLKA1□(to DCANx)to VCLK RTICLK (to□RTI,□DWWD) /1,□2,□4,□or□8 VCLK VCLK3 VCLK3□(to□Ethernet,□USB)/1..16 VCLK_sys (VCLK to system□modules) exceed□the□maximum□HCLK□specifiation. /1,2..256 I2C I2C□baud rate VCLK NTU[1] NTU[0] NTU[2] NTU[3] RTI PLL#2□output EXTCLKIN1 Reserved Reserved VCLK /1,2,..1024 Phase_seg2 CAN□Baud□Rate Phase_seg1 VCLKA1 Prop_seg (FMzPLL) VCLKA3_S□(left□open) /DIVR VCLKA3_DIVR (to□USB□Device□/□48MHZ USB□Host VCLKA3_DIVR□/□4 VCLKA3_DIVR DCANx EMIF USB□Device VCLKA3_DIVR N2HETx TU VCLKA4_DIVR/DIVR PLL2□ODCLK/8 PLL2□ODCLK/16 VCLKA4_DIVR_EMAC (to□EMAC) VCLKA4_S□(left□open) VCLK /4 VCLKA3_DIVR□/□4 VCLKA4_SRC RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com

4.6.2.2 Mapping ofClock Domains toDevice Modules

Each clockdomain has a dedicatedfunctionalityas shown inthefiguresbelow. Figure4-7.Device Clock Domains

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PRODUCT□PREVIEW VCLKA4_SRC VCLK VCLKA4_S□(left□open) /DIVR PLL2□post_ODCLK/8 PLL2□post_ODCLK/16 VCLKA4_DIVR_EMAC (to□EMAC) RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012

4.6.2.3 SpecialClock Source SelectionScheme forVCLKA4_DIVR_EMAC

Some applicationsmay need to use both the of Ethernetinterfaces.The MII interfacerequires VCLKA4_DIVR_EMAC tobe 25MHz and theRMII requiresVCLKA4_DIVR_EAMC tobe 50MHz. These differentfrequenciesare supportedby addingspecialdedicatedclocksourceselectionoptionsfor theVCLKA4_DIVR_EMAC clockdomain.Thislogicisshown in. Figure4-8.VCLKA4_DIVR Source SelectionOptions The PLL2 post_ODCLK isbroughtoutas a separateoutputfromthePLL wrappermodule.There aretwo additionaldividersimplementedatthedevice-leveltodividethisPLL2 post_ODCLK by 8 and by 16. As shown in,theVCLKA4_SRC configuredviathesystem module VCLKACON1 controlregisterisused to determinethe clocksource forthe VCLKA4_S and VCLKA4_DIVR. An additionalmultiplexoris implemented to selectbetween the VCLKA4_DIVR and the two additionalclock sources – PLL2 post_ODCLK/8 and post_ODCLK/16. The selectionisdone as shown inthefollowingtable. Table4-14.VCLKA4_DIVR_EMAC Clock Source Selection VCLKA4_SRC from Clock Source for VCLKACON1[19 –16] VCLKA4_DIVR_EMAC 0x0 OSCIN /VCLKA4R 0x1 PLL1CLK /VCLKA4R 0x2 Reserved 0x3 EXTCLKIN1 /VCLKA4R 0x4 LF LPO /VCLKA4R 0x5 HF LPO /VCLKA4R 0x6 PLL2CLK /VCLKA4R 0x7 EXTCLKIN2 /VCLKA4R Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 69 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

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4.6.3 Clock TestMode

The RM4x platformarchitecturedefinesa specialmode thatallowsvariousclocksignalstobe broughtout on totheECLK pinand N2HET1[12] deviceoutputs.Thismode iscalledtheClockTestmode. Itisvery usefulfordebuggingpurposesand can be configuredviatheCLKTEST registerinthesystemmodule. Table4-15.Clock TestMode Options SEL_ECP_PIN SEL_GIO_PIN = SIGNAL ON ECLK = SIGNAL ON N2HET1[12] CLKTEST[3-0] CLKTEST[11-8]

0000 Oscillator 0000 OscillatorValidStatus

0001 Main PLL free-runningclockoutput 0001 Main PLL Validstatus

0010 Reserved 0010 Reserved

0011 EXTCLKIN1 0011 Reserved

0100 LFLPO 0100 Reserved

0101 HFLPO 0101 HFLPO Validstatus

0110 SecondaryPLL free-runningclockoutput 0110 SecondaryPLL ValidStatus

0111 EXTCLKIN2 0111 Reserved

1000 GCLK 1000 LFLPO

1001 RTI Base 1001 OscillatorValidstatus

1010 Reserved 1010 OscillatorValidstatus

1011 VCLKA1 1011 OscillatorValidstatus

1100 Reserved 1100 OscillatorValidstatus

1101 VCLKA3_DIVR 1101 VCLKA3_S

1110 VCLKA4_DIVR 1110 VCLKA4_S

1111 Reserved 1111 OscillatorValidstatus

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PRODUCT□PREVIEW f[MHz]1.375 4.875 22 78 guaranteed fail lower threshold guaranteed pass upper threshold guaranteed fail RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012

4.7 Clock Monitoring

The LPO ClockDetect(LPOCLKDET) module consistsofa clockmonitor(CLKDET) and an internallow power oscillator(LPO). The LPO providestwo differentclocksources– a lowfrequency(LFLPO) and a highfrequency(HFLPO). The CLKDET isa supervisorcircuitforan externallysuppliedclocksignal(OSCIN).Incase theOSCIN frequencyfallsoutofa frequencywindow,theCLKDET flagsthisconditionintheglobalstatusregister (GLBSTAT bit0:OSC FAIL)and switchesallclockdomains sourcedby OSCIN totheHFLPO clock(limp mode clock). The validOSCIN frequencyrangeisdefinedas:fHFLPO /4 < fOSCIN < fHFLPO *4.

4.7.1 Clock MonitorTimings

Formore informationon LPO and Clockdetection,refertoTable4-10. Figure4-9.LPO and Clock Detection,Untrimmed HFLPO

4.7.2 ExternalClock (ECLK) Output Functionality

The ECLK pincan be configuredtooutputa pre-scaledclocksignalindicativeofan internaldeviceclock. Thisoutputcan be externallymonitoredas a safetydiagnostic.

4.7.3 Dual Clock Comparators

The Dual Clock Comparator (DCC) module determinesthe accuracyof selectableclocksources by countingthe pulsesof two independentclocksources(counter0 and counter1).Ifone clockisout of spec,an errorsignalisgenerated.For example,the DCC1 can be configuredto use HFLPO as the referenceclock(forcounter0) and VCLK as the "clockunder test"(forcounter1).Thisconfiguration allowstheDCC1 tomonitorthePLL outputclockwhen VCLK isusingthePLL outputas itssource. An additionaluse ofthismodule istomeasure thefrequencyofa selectableclocksource,usingtheinput clockas a reference,by countingthe pulsesof two independentclocksources.Counter0 generatesa fixed-widthcountingwindow aftera preprogrammed number ofpulses.Counter1 generatesa fixed-width pulse(1 cycle)aftera pre-programmednumber ofpulses.Thispulsesetsas an errorsignalifcounter1 does notreach0 withinthecountingwindow generatedby counter0.

4.7.3.1 Features

• Takes two differentclocksourcesas inputtotwo independentcounterblocks.
• One oftheclocksourcesistheknown-good,orreferenceclock;thesecond clocksourceisthe"clock undertest."
• Each counterblockisprogrammablewithinitial,orseed values.
• The counterblocksstartcountingdown fromtheirseed valuesatthesame time;a mismatch fromthe expectedfrequencyforthe clockunder testgeneratesan errorsignalwhich isused to interruptthe CPU. Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 71 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

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4.7.3.2 Mapping ofDCC Clock Source Inputs

Table4-16.DCC1 Counter 0 Clock Sources CLOCK SOURCE [3:0] CLOCK NAME others oscillator(OSCIN) 0x5 highfrequencyLPO 0xA testclock(TCK) Table4-17.DCC1 Counter 1 Clock Sources KEY [3:0] CLOCK SOURCE [3:0] CLOCK NAME others - N2HET1[31] 0x0 Main PLL free-runningclockoutput 0x1 PLL #2 free-runningclockoutput 0x2 lowfrequencyLPO 0xA 0x3 highfrequencyLPO 0x4 reserved 0x5 EXTCLKIN1 0x6 EXTCLKIN2 0x7 reserved 0x8 -0xF VCLK Table4-18.DCC2 Counter 0 Clock Sources CLOCK SOURCE [3:0] CLOCK NAME others oscillator(OSCIN) 0xA testclock(TCK) Table4-19.DCC2 Counter 1 Clock Sources KEY [3:0] CLOCK SOURCE [3:0] CLOCK NAME others - N2HET2[0] 0xA 00x0 -0x7 Reserved 0x8 -0xF VCLK

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4.8 GlitchFilters

A glitchfilterispresenton thefollowingsignals. Table4-20.GlitchFilterTiming Specifications Pin Parameter MIN MAX Unit nPORRST tf(nPORRST) 500 2000 nsFiltertimenPORRST pin; pulseslessthan MIN willbe filteredout,pulsesgreaterthan MAX willgeneratea reset(1) nRST tf(nRST) 500 2000 nsFiltertimenRST pin; pulseslessthan MIN willbe filteredout,pulsesgreaterthan MAX willgeneratea reset TEST tf(TEST) 500 2000 nsFiltertimeTEST pin; pulseslessthan MIN willbe filteredout,pulsesgreaterthan MAX willpass through (1) The glitchfilterdesignon thenPORRST signalisdesignedsuch thatno sizepulsewillresetany partofthemicrocontroller(flashpump, I/Opins,etc.)withoutalsogeneratinga validresetsignaltotheCPU. Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 73 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW Flash□(1.25MB) RAM□(192KB) 0x00000000 0x0013FFFF 0x08000000 0x0802FFFF CRC0xFE000000 Peripherals -□Frame□1 0xFF000000 SYSTEM□Modules0xFFFFFFFF 0xF07FFFFF RAM□-□ECC0x08400000 0x0842FFFF RESERVED RESERVED RESERVED 0xF0000000 0x60000000 0x6FFFFFFF CS2 RESERVED CS3 Flash□(1.25MB)□(Mirrored□Image)0x20000000 RESERVED CS4 RESERVED Peripherals -□Frame□20xFC000000 0xFCFFFFFF 0xFFF80000 0x80000000 0x87FFFFFF CS 0 RESERVED reserved Async□RAM SDRAM 0x64000000 0x68000000 0x6C000000 Flash□Module□Bus2□Interface RESERVED (Flash□ECC,□OTP and EEPROM□Emulation□accesses) EMIF□(64MB) EMIF□(32kB□*□3) 0x2013FFFF RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com

4.9 Device Memory Map

4.9.1 Memory Map Diagram

The figurebelowshows thedevicememory map. Figure4-10.Memory Map The Flash memory ismirroredto supportECC logictesting.The base address of the mirroredFlash image is0x2000 0000.

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4.9.2 Memory Map Table

Pleaserefertoand fora blockdiagramsshowingthedevicesinterconnect. Table4-21.Device Memory Map FRAME ADDRESS RANGE RESPNSE FOR ACCESS TOFRAME CHIP FRAME ACTUAMODULE NAME UNIMPLEMENTED LOCATIONS INSELECT SIZE L SIZESTART END FRAME Memories tightlycoupled totheARM Cortex-R4FCPU TCM Flash CS0 0x0000_0000 0x00FF_FFFF 16MB 1.25MB TCM RAM + RAM CSRAM0 0x0800_0000 0x0BFF_FFFF 64MB 192kBECC Abort FlashmirrorMirroredFlash 0x2000_0000 0x20FF_FFFF 16MB 1.25MBframe ExternalMemory Accesses EMIF ChipSelect EMIF select2 0x6000_0000 0x63FF_FFFF 64MB 32kB2 (asynchronous) EMIF ChipSelect EMIF select3 0x6400_0000 0x67FF_FFFF 64MB 32kB3 (asynchronous) Access to"Reserved"space will generateAbortEMIF ChipSelect EMIF select4 0x6800_0000 0x6BFF_FFFF 64MB 32kB4 (asynchronous) EMIF ChipSelect EMIF select0 0x8000_0000 0x87FF_FFFF 128MB 64MB0 (synchronous) FlashModule Bus2 Interface Customer OTP, 0xF000_0000 0xF000_1FFF 8kB 4kBTCM FlashBanks Customer OTP, 0xF000_E000 0xF000_FFFF 8kB 4kBBank 7 Customer OTP –ECC, TCM 0xF004_0000 0xF004_03FF 1kB 512B FlashBanks Customer OTP –ECC, 0xF004_1C00 0xF004_1FFF 1kB 512B Bank 7 TIOTP, TCM 0xF008_0000 0xF008_1FFF 8kB 4kB AbortFlashBanks TIOTP, 0xF008_E000 0xF008_FFFF 8kB 4kBBank 7 TIOTP –ECC, 0xF00C_0000 0xF00C_03FF 1kB 512BTCM FlashBanks TIOTP –ECC, 0xF00C_1C00 0xF00C_1FFF 1kB 512BBank 7 Bank 7 – ECC 0xF010_0000 0xF013_FFFF 256kB 8kB Bank 7 0xF020_0000 0xF03F_FFFF 2MB 64kB FlashData Space 0xF040_0000 0xF04F_FFFF 1MB 160kBECC Ethernetand EMIF slaveinterfaces CPPI Memory Slave(Ethernet 0xFC52_0000 0xFC52_1FFF 8kB 8kB Abort RAM) CPGMAC Slave 0xFCF7_8000 0xFCF7_87FF 2kB 2kB No error(EthernetSlave) CPGMACSS Wrapper 0xFCF7_8800 0xFCF7_88FF 256B 256B No error(Ethernet Wrapper) EthernetMDIO 0xFCF7_8900 0xFCF7_89FF 256B 256B No errorInterface Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 75 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com Table4-21.Device Memory Map (continued) FRAME ADDRESS RANGE RESPNSE FOR ACCESS TOFRAME CHIP FRAME ACTUAMODULE NAME UNIMPLEMENTED LOCATIONS INSELECT SIZE L SIZESTART END FRAME W2FC (USB devicecontroller 0xFCF7_8A00 0xFCF7_8A7F 128B 128B Abort registers) OHCI (USB Host controller 0xFCF7_8B00 0xFCF7_8BFF 256B 256B Abort registers) EMIF Registers 0xFCFF_E800 0xFCFF_E8FF 256B 256B Abort SCR5: Enhanced Timer Peripherals ePWM1 0xFCF7_8C00 0xFCF7_8CFF 256B 256B Abort ePWM2 0xFCF7_8D00 0xFCF7_8DFF 256B 256B Abort ePWM3 0xFCF7_8E00 0xFCF7_8EFF 256B 256B Abort ePWM4 0xFCF7_8F00 0xFCF7_8FFF 256B 256B Abort ePWM5 0xFCF7_9000 0xFCF7_90FF 256B 256B Abort ePWM6 0xFCF7_9100 0xFCF7_91FF 256B 256B Abort ePWM7 0xFCF7_9200 0xFCF7_92FF 256B 256B Abort eCAP1 0xFCF7_9300 0xFCF7_94FF 256B 256B Abort eCAP2 0xFCF7_9400 0xFCF7_95FF 256B 256B Abort eCAP3 0xFCF7_9500 0xFCF7_96FF 256B 256B Abort eCAP4 0xFCF7_9600 0xFCF7_97FF 256B 256B Abort eCAP5 0xFCF7_9700 0xFCF7_98FF 256B 256B Abort eCAP6 0xFCF7_9800 0xFCF7_99FF 256B 256B Abort eQEP1 0xFCF7_9900 0xFCF7_9AFF 256B 256B Abort eQEP2 0xFCF7_9A00 0xFCF7_9BFF 256B 256B Abort CyclicRedundancy Checker (CRC) Module Registers CRC CRC frame 0xFE00_0000 0xFEFF_FFFF 16MB 512B Accessesabove 0x200 generateabort. PeripheralMemories MIBSPI5 RAM PCS[5] 0xFF0A_0000 0xFF0B_FFFF 128kB 2kB Abortforaccessesabove 2kB MIBSPI3 RAM PCS[6] 0xFF0C_0000 0xFF0D_FFFF 128kB 2kB Abortforaccessesabove 2kB MIBSPI1 RAM PCS[7] 0xFF0E_0000 0xFF0F_FFFF 128kB 2kB Abortforaccessesabove 2kB Wrap aroundforaccessesto unimplementedaddressoffsetslowerDCAN3 RAM PCS[13] 0xFF1A_0000 0xFF1B_FFFF 128kB 2kB than0x7FF.Abortgeneratedfor accessesbeyond offset0x800. Wrap aroundforaccessesto unimplementedaddressoffsetslowerDCAN2 RAM PCS[14] 0xFF1C_0000 0xFF1D_FFFF 128kB 2kB than0x7FF.Abortgeneratedfor accessesbeyond offset0x800. Wrap aroundforaccessesto unimplementedaddressoffsetslowerDCAN1 RAM PCS[15] 0xFF1E_0000 0xFF1F_FFFF 128kB 2kB than0x7FF.Abortgeneratedfor accessesbeyond offset0x800. Wrap aroundforaccessesto unimplementedaddressoffsetslowerMIBADC2 RAM 8kB than0x1FFF.Abortgeneratedfor accessesbeyond 0x1FFF. Look-Up TableforADC2 wrapper.PCS[29] 0xFF3A_0000 0xFF3B_FFFF 128kB Startsataddressoffset0x2000 and MIBADC2 Look- ends ataddressoffset0x217F.Wrap384BUp Table aroundforaccessesbetween offsets 0x0180 and 0x3FFF.Abortgenerated foraccessesbeyond offset0x4000.

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Table4-21.Device Memory Map (continued) FRAME ADDRESS RANGE RESPNSE FOR ACCESS TOFRAME CHIP FRAME ACTUAMODULE NAME UNIMPLEMENTED LOCATIONS INSELECT SIZE L SIZESTART END FRAME Wrap aroundforaccessesto unimplementedaddressoffsetslowerMIBADC1 RAM 8kB than0x1FFF.Abortgeneratedfor accessesbeyond 0x1FFF. Look-Up TableforADC1 wrapper.PCS[31] 0xFF3E_0000 0xFF3F_FFFF 128kB Startsataddressoffset0x2000 and MibADC1 Look- ends ataddressoffset0x217F.Wrap384BUp Table aroundforaccessesbetween offsets 0x0180 and 0x3FFF.Abortgenerated foraccessesbeyond offset0x4000. Wrap aroundforaccessesto unimplementedaddressoffsetslowerN2HET2 RAM PCS[34] 0xFF44_0000 0xFF45_FFFF 128kB 16kB than0x3FFF.Abortgeneratedfor accessesbeyond 0x3FFF. Wrap aroundforaccessesto unimplementedaddressoffsetslowerN2HET1 RAM PCS[35] 0xFF46_0000 0xFF47_FFFF 128kB 16kB than0x3FFF.Abortgeneratedfor accessesbeyond 0x3FFF. N2HET2 TU2 PCS[38] 0xFF4C_0000 0xFF4D_FFFF 128kB 1kB AbortRAM N2HET1 TU1 PCS[39] 0xFF4E_0000 0xFF4F_FFFF 128kB 1kB AbortRAM Debug Components CoreSightDebug Reads returnzeros,writeshave noCSCS0 0xFFA0_0000 0xFFA0_0FFF 4kB 4kBROM effect Cortex-R4F Reads returnzeros,writeshave noCSCS1 0xFFA0_1000 0xFFA0_1FFF 4kB 4kBDebug effect POM CSCS4 0xFFA0_4000 0xFFA0_4FFF 4kB 4kB Abort PeripheralControlRegisters Reads returnzeros,writeshave noHTU1 PS[22] 0xFFF7_A400 0xFFF7_A4FF 256B 256B effect Reads returnzeros,writeshave noHTU2 PS[22] 0xFFF7_A500 0xFFF7_A5FF 256B 256B effect Reads returnzeros,writeshave noN2HET1 PS[17] 0xFFF7_B800 0xFFF7_B8FF 256B 256B effect Reads returnzeros,writeshave noN2HET2 PS[17] 0xFFF7_B900 0xFFF7_B9FF 256B 256B effect Reads returnzeros,writeshave noGIO PS[16] 0xFFF7_BC00 0xFFF7_BDFF 512B 256B effect Reads returnzeros,writeshave noMIBADC1 PS[15] 0xFFF7_C000 0xFFF7_C1FF 512B 512B effect Reads returnzeros,writeshave noMIBADC2 PS[15] 0xFFF7_C200 0xFFF7_C3FF 512B 512B effect Reads returnzeros,writeshave noI2C PS[10] 0xFFF7_D400 0xFFF7_D4FF 256B 256B effect Reads returnzeros,writeshave noDCAN1 PS[8] 0xFFF7_DC00 0xFFF7_DDFF 512B 512B effect Reads returnzeros,writeshave noDCAN2 PS[8] 0xFFF7_DE00 0xFFF7_DFFF 512B 512B effect Reads returnzeros,writeshave noDCAN3 PS[7] 0xFFF7_E000 0xFFF7_E1FF 512B 512B effect Reads returnzeros,writeshave noLIN PS[6] 0xFFF7_E400 0xFFF7_E4FF 256B 256B effect Reads returnzeros,writeshave noSCI PS[6] 0xFFF7_E500 0xFFF7_E5FF 256B 256B effect Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 77 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com Table4-21.Device Memory Map (continued) FRAME ADDRESS RANGE RESPNSE FOR ACCESS TOFRAME CHIP FRAME ACTUAMODULE NAME UNIMPLEMENTED LOCATIONS INSELECT SIZE L SIZESTART END FRAME Reads returnzeros,writeshave noMibSPI1 PS[2] 0xFFF7_F400 0xFFF7_F5FF 512B 512B effect Reads returnzeros,writeshave noSPI2 PS[2] 0xFFF7_F600 0xFFF7_F7FF 512B 512B effect Reads returnzeros,writeshave noMibSPI3 PS[1] 0xFFF7_F800 0xFFF7_F9FF 512B 512B effect Reads returnzeros,writeshave noSPI4 PS[1] 0xFFF7_FA00 0xFFF7_FBFF 512B 512B effect Reads returnzeros,writeshave noMibSPI5 PS[0] 0xFFF7_FC00 0xFFF7_FDFF 512B 512B effect System Modules ControlRegistersand Memories DMA RAM PPCS0 0xFFF8_0000 0xFFF8_0FFF 4kB 4kB Abort Wrap aroundforaccessesto VIM RAM PPCS2 0xFFF8_2000 0xFFF8_2FFF 4kB 1kB unimplementedaddressoffsets between 1kB and 4kB. FlashModule PPCS7 0xFFF8_7000 0xFFF8_7FFF 4kB 4kB Abort eFuse Controller PPCS12 0xFFF8_C000 0xFFF8_CFFF 4kB 4kB Abort Power Management PPSE0 0xFFFF_0000 0xFFFF_01FF 512B 512B Abort Module (PMM) Reads returnzeros,writeshave noPCR registers PPS0 0xFFFF_E000 0xFFFF_E0FF 256B 256B effect System Module - Reads returnzeros,writeshave noFrame 2 (see PPS0 0xFFFF_E100 0xFFFF_E1FF 256B 256B effectdeviceTRM) Reads returnzeros,writeshave noPBIST PPS1 0xFFFF_E400 0xFFFF_E5FF 512B 512B effect Generatesaddresserrorinterrupt,ifSTC PPS1 0xFFFF_E600 0xFFFF_E6FF 256B 256B enabled IOMM Reads returnzeros,writeshave noMultiplexing PPS2 0xFFFF_EA00 0xFFFF_EBFF 512B 512B effectControlModule Reads returnzeros,writeshave noDCC1 PPS3 0xFFFF_EC00 0xFFFF_ECFF 256B 256B effect Reads returnzeros,writeshave noDMA PPS4 0xFFFF_F000 0xFFFF_F3FF 1kB 1kB effect Reads returnzeros,writeshave noDCC2 PPS5 0xFFFF_F400 0xFFFF_F4FF 256B 256B effect Reads returnzeros,writeshave noESM PPS5 0xFFFF_F500 0xFFFF_F5FF 256B 256B effect Reads returnzeros,writeshave noCCMR4 PPS5 0xFFFF_F600 0xFFFF_F6FF 256B 256B effect Reads returnzeros,writeshave noRAM ECC even PPS6 0xFFFF_F800 0xFFFF_F8FF 256B 256B effect Reads returnzeros,writeshave noRAM ECC odd PPS6 0xFFFF_F900 0xFFFF_F9FF 256B 256B effect Reads returnzeros,writeshave noRTI + DWWD PPS7 0xFFFF_FC00 0xFFFF_FCFF 256B 256B effect Reads returnzeros,writeshave noVIM Parity PPS7 0xFFFF_FD00 0xFFFF_FDFF 256B 256B effect Reads returnzeros,writeshave noVIM PPS7 0xFFFF_FE00 0xFFFF_FEFF 256B 256B effect System Module - Reads returnzeros,writeshave noFrame 1 (see PPS7 0xFFFF_FF00 0xFFFF_FFFF 256B 256B effectdeviceTRM)

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4.9.3 SpecialConsiderationforCPU Access ErrorsResultinginImpreciseAborts

Any CPU writeaccess to a Normal or Device typememory, which generatesa fault,willgeneratean impreciseabort.The impreciseabortexceptionisdisabledby defaultand must be enabledfortheCPU to handle thisexception.The impreciseaborthandlingis enabled by clearingthe "A" bitin the CPU ’s programstatusregister(CPSR).

4.9.4 Master/SlaveAccess Privileges

The tablebelowliststheaccesspermissionsforeach bus masteron thedevice.A bus masterisa module thatcan initiatea readora writetransactionon thedevice. Each slavemodule on themain interconnectislistedinthetable.A "Yes"indicatesthatthemodule listed inthe"MASTERS" column can accessthatslavemodule. Table4-22.Master /SlaveAccess Matrix MASTERS ACCESS MODE SLAVES ON MAIN SCR FlashModule Non-CPU CRC EMIF, Ethernet, Peripheral Bus2 Interface: Accesses to USB Slave Control OTP, ECC, Bank Program Flash Interfaces Registers,All 7 and CPU Data Peripheral RAM Memories, And AllSystem Module Control RegistersAnd Memories CPU READ User/Privilege Yes Yes Yes Yes Yes CPU WRITE User/Privilege No Yes Yes Yes Yes DMA User Yes Yes Yes Yes Yes POM User Yes Yes Yes Yes Yes DAP Privilege Yes Yes Yes Yes Yes HTU1 Privilege No Yes Yes Yes Yes HTU2 Privilege No Yes Yes Yes Yes EMAC User No Yes No Yes No OHCI User No Yes No Yes No

4.9.5 SpecialNotes on Accesses toCertainSlaves

WriteaccessestothePower Domain Management Module (PMM) controlregistersarelimitedtotheCPU (masterid= 1).The othermasterscan onlyreadfromtheseregisters. A debuggercan alsowritetothePMM registers.The master-idcheckisdisabledindebug mode. The devicecontainsdedicatedlogictogeneratea bus errorresponseon any accesstoa module thatisin a power domain thathas been turnedOFF.

4.9.6 Parameter OverlayModule (POM) Considerations

• The POM can map ontoup to8MB oftheinternalorexternalmemory space.The startingaddressand thesizeofthememory overlayareconfigurableviathePOM controlregisters.Care must be takento ensurethattheoverlayismapped on toavailablememory.
• ECC must be disabledby softwareviaCP15 incase POM overlayisenabled;otherwiseECC errors willbe generated.
• POM overlaymust notbe enabledwhen theflashand internalRAM memories are swapped viathe MEM SWAP fieldoftheBus MatrixModule ControlRegister1 (BMMCR1). Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 79 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

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• When POM isused to overlaythe flashon to internalor externalRAM, thereisa bus contention possibilitywhen anothermasteraccessestheTCM flash.Thisresultsina systemhang. – The POM implementsa timeoutfeatureto detectthisexactscenario.The timeoutneeds to be enabledwhenever POM overlayisenabled. – The timeoutcan be enabledby writing1010 totheEnableTimeOut (ETO) fieldofthePOM Global Controlregister(POMGLBCTRL, address= 0xFFA04000). – Incase a readrequestby thePOM cannotbe completedwithin32 HCLK cycles,thetimeout(TO) flagis set in the POM Flag register(POMFLG, address = 0xFFA0400C). Also,an abortis generatedtotheCPU. Thiscan be a prefetchabortforan instructionfetchor a dataabortfora datafetch. – The prefetch-and data-aborthandlersmust be modifiedtocheck iftheTO flaginthePOM isset.If so,thentheapplicationcan assume thatthetimeoutiscaused by a bus contentionbetween the POM transactionand anothermasteraccessingthesame memory region.The aborthandlersneed tocleartheTO flag,so thatany furtherabortsarenotmisinterpretedas havingbeen caused due to a timeoutfromthePOM.

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4.10 FlashMemory

4.10.1 FlashMemory Configuration

Flash Bank: A separateblockof logicconsistingof 1 to 16 sectors.Each flashbank normallyhas a customer-OTP and a TI-OTP area.These flashsectorsshare input/outputbuffers,data paths,sense amplifiers,and controllogic. Flash Sector:A contiguousregionofflashmemory whichmust be erasedsimultaneouslydue tophysical constructionconstraints. Flash Pump: A charge pump which generatesallthe voltagesrequiredforreading,programming,or erasingtheflashbanks. FlashModule: Interfacecircuitryrequiredbetween thehostCPU and theflashbanks and pump module. Table4-23.FlashMemory Banks and Sectors Memory Arrays(orBanks) Sector Segment Low Address High Address No. BANK0 (1.25MBytes) 0 16K Bytes 0x0000_0000 0x0000_3FFF 1 16K Bytes 0x0000_4000 0x0000_7FFF 2 16K Bytes 0x0000_8000 0x0000_BFFF 3 16K Bytes 0x0000_C000 0x0000_FFFF 4 16K Bytes 0x0001_0000 0x0001_3FFF 5 16K Bytes 0x0001_4000 0x0001_7FFF 6 32K Bytes 0x0001_8000 0x0001_FFFF 7 128K Bytes 0x0002_0000 0x0003_FFFF 8 128K Bytes 0x0004_0000 0x0005_FFFF 9 128K Bytes 0x0006_0000 0x0007_FFFF 10 128K Bytes 0x0008_0000 0x0009_FFFF 11 128K Bytes 0x000A_0000 0x000B_FFFF 12 128K Bytes 0x000C_0000 0x000D_FFFF 13 128K Bytes 0x000E_0000 0x000F_FFFF 14 128K Bytes 0x0010_0000 0x0011_FFFF 15 128K Bytes 0x0012_0000 0x0013_FFFF BANK7 (64kBytes)forEEPROM emulation 0 16K Bytes 0xF020_0000 0xF020_3FFF 1 16K Bytes 0xF020_4000 0xF020_7FFF 2 16K Bytes 0xF020_8000 0xF020_BFFF 3 16K Bytes 0xF020_C000 0xF020_FFFF

4.10.2 Main FeaturesofFlashModule

• Supportformultipleflashbanks forprogramand/ordatastorage
• Simultaneousreadaccesson a bank whileperformingprogramoreraseoperationon any otherbank
• Integratedstatemachinestoautomateflasheraseand programoperations
• Pipelinedmode operationtoimproveinstructionaccessinterfacebandwidth
• SupportforSingleErrorCorrectionDoubleErrorDetection(SECDED) blockinsideCortex-R4FCPU – Erroraddressiscapturedforhostsystemdebugging
• Supportfora richsetofdiagnosticfeatures Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 81 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

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4.10.3 ECC ProtectionforFlashAccesses

Allaccessestotheprogramflashmemory areprotectedby SingleErrorCorrectionDoubleErrorDetection (SECDED) logicembedded insidetheCPU. The flashmodule provides8 bitsofECC code for64 bitsof instructionsordatafetchedfromtheflashmemory. The CPU calculatestheexpectedECC code based on the64 bitsreceivedand compares itwiththeECC code returnedby theflashmodule.A single-biterroris correctedand flaggedby theCPU, whilea multi-biterrorisonlyflagged.The CPU signalsan ECC error viaitsEventbus.Thissignalingmechanism isnotenabledby defaultand must be enabledby settingthe "X"bitofthePerformanceMonitorControlRegister,c9. MRCp15,#0,r1,c9,c12,#0;EnablingEventmonitorstates ORRr1,r1,#0x00000010 MCRp15,#0,r1,c9,c12,#0;Set4thbit(‘X’)ofPMNCregister MRCp15,#0,r1,c9,c12,#0 The applicationmust alsoexplicitlyenablethe CPU's ECC checkingforaccesses on the CPU's ATCM and BTCM interfaces.These are connected to the program flashand data RAM respectively.ECC checkingfortheseinterfacescan be done by settingtheB1TCMPCEN, B0TCMPCEN and ATCMPCEN bitsoftheSystem Controlcoprocessor'sAuxiliaryControlRegister,c1. MRCp15,#0,r1,c1,c0,#1 ORRr1,r1,#0x0e000000;EnableECCcheckingforATCMandBTCMs DMB MCRp15,#0,r1,c1,c0,#1

4.10.4 FlashAccess Speeds

Forinformationon flashmemory accessspeeds and therelevantwaitstatesrequired,refertoSection3.4.

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4.10.5 Program Flash

Table4-24.Timing Requirements forProgram Flash Parameter MIN NOM MAX Unit tprog(144bit) Wide Word (144bit)programmingtime 40 300 µs tprog(Total) 1.25MByteprogrammingtime(1) -40°C to105°C 13 s 0°C to60°C, forfirst 3.3 6.6 s 25 cycles terase(bank0) Sector/Bankerasetime -40°C to105°C 0.3 4 s 0°C to60°C, forfirst 30 500 ms 25 cycles twec Write/erasecycleswith15 yearData Retention -40°C to105°C 1000 cycles requirement (1) Thisprogrammingtimeincludesoverheadofstatemachine,butdoes notincludedatatransfertime.The programmingtimeassumes programming144 bitsata timeatthemaximum specifiedoperatingfrequency.

4.10.6 Data Flash

Table4-25.Timing Requirements forData Flash Parameter MIN NOM MAX Unit tprog(144bit) Wide Word (144bit)programmingtime 40 300 µs tprog(Total) EEPROM Emulation(bank7)64kByte -40°C to105°C 660 ms programmingtime(1) 0°C to60°C, forfirst 165 330 ms 25 cycles EEPROM Emulation(bank7)Sector/Bankerasetimeterase(bank7) -40°C to105°C 0.08 8 s 0°C to60°C, forfirst 30 500 ms 25 cycles twec Write/erasecycleswith15 yearData Retention -40°C to105°C 100000 cycles requirement (1) Thisprogrammingtimeincludesoverheadofstatemachine,butdoes notincludedatatransfertime.The programmingtimeassumes programming144 bitsata timeatthemaximum specifiedoperatingfrequency. Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 83 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW TCM□BUS TCM□BUS 72□Bit□data□+□ECC 72□Bit□data□+□ECC Upper□32□bits data□& 4□ECC□bits Lower32□bits data□& 4□ECC□bits 36□Bit wide RAM 36□Bit wide RAM 36□Bit wide RAM 36□Bit wide RAM 36□Bit wide RAM 36□Bit wide RAM Upper□32□bits data□& 4□ECC□bits Lower32□bits data□& 4□ECC□bits 36□Bit wide RAM 36□Bit wide RAM 36□Bit wide RAM 36□Bit wide RAM 36□Bit wide RAM 36□Bit wide RAM TCRAM Interface□1 Cortex□R4F™ TCM TCM A TCM TCRAM Interface□2 RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com

4.11 Tightly-CoupledRAM InterfaceModule

Figure4-11illustratestheconnectionoftheTightlyCoupledRAM (TCRAM) totheCortex-R4F™ CPU. Figure4-11.TCRAM Block Diagram

4.11.1 Features

The featuresoftheTightlyCoupledRAM (TCRAM) Module are:

• Actsas slavetotheCortex-R4FCPU's BTCM interface
• SupportsCPU's internalECC scheme by providing64-bitdataand 8-bitECC code
• MonitorsCPU EventBus and generatessingleormulti-biterrorinterrupts
• Storesaddressesforsingleand multi-biterrors
• SupportsRAM tracemodule
• ProvidesCPU addressbus integritycheckingby supportingparitycheckingon theaddressbus
• PerformsredundantaddressdecodingfortheRAM bank chipselectand ECC selectgenerationlogic
• Providesenhanced safetyforthe RAM addressingby implementingtwo 36-bitwide byte-interleaved RAM banks and generatingindependentRAM accesscontrolsignalstothetwo banks
• Supportsauto-initializationoftheRAM banks alongwiththeECC bits

4.11.2 TCRAMW ECC Support

The TCRAMW passes on theECC code foreach datareadby theCortex-R4FCPU fromtheRAM. Italso storesthe CPU's ECC portcontentsin the ECC RAM when the CPU does a writeto the RAM. The TCRAMW monitorsthe CPU's eventbus and providesregistersforindicatingsingle/multi-biterrorsand alsoforidentifyingtheaddressthatcaused thesingleormulti-biterror.The eventsignalingand theECC checkingfortheRAM accessesmust be enabledinsidetheCPU. Formore informationsee thedeviceTechnicalReferenceManual.

4.12 ParityProtectionforAccesses toperipheralRAMs

Accesses tosome peripheralRAMs areprotectedby odd/evenparitychecking.Duringa readaccessthe parityiscalculatedbased on thedataread from theperipheralRAM and compared withthegood parity valuestoredintheparityRAM forthatperipheral.Ifany word failstheparitycheck,themodule generates a parityerrorsignalthatis mapped to the ErrorSignalingModule. The module also capturesthe peripheralRAM addressthatcaused theparityerror.

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 The parityprotectionforperipheralRAMs is not enabled by defaultand must be enabled by the application.Each individualperipheralcontainscontrolregistersto enable the parityprotectionfor accessestoitsRAM. NOTE The CPU read access getstheactualdatafrom theperipheral.The applicationcan choose togeneratean interruptwhenever a peripheralRAM parityerrorisdetected. Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 85 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

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4.13 On-Chip SRAM Initializationand Testing

4.13.1 On-Chip SRAM Self-TestUsing PBIST

4.13.1.1Features

• Extensiveinstructionsettosupportvariousmemory testalgorithms
• ROM-based algorithmsallowapplicationtorunTIproduction-levelmemory tests
• Independenttestingofallon-chipSRAM 4.13.1.2PBIST RAM Groups Table4-26.PBIST RAM Grouping TestPattern(Algorithm) March 13N (1) March 13N (1) tripleread tripleread two port singleportMemory RAM Group TestClock MEM Type slow read fastread (cycles) (cycles) ALGO MASK ALGO MASK ALGO MASK ALGO MASK 0x1 0x2 0x4 0x8 PBIST_ROM 1 ROM CLK ROM X X STC_ROM 2 ROM CLK ROM X X DCAN1 3 VCLK DualPort 25200 DCAN2 4 VCLK DualPort 25200 DCAN3 5 VCLK DualPort 25200 ESRAM1 6 HCLK SinglePort 266280 MIBSPI1 7 VCLK DualPort 33440 MIBSPI3 8 VCLK DualPort 33440 MIBSPI5 9 VCLK DualPort 33440 VIM 10 VCLK DualPort 12560 MIBADC1 11 VCLK DualPort 4200 DMA 12 HCLK DualPort 18960 N2HET1 13 VCLK DualPort 31680 HET TU1 14 VCLK DualPort 6480 MIBADC2 18 VCLK DualPort 4200 N2HET2 19 VCLK DualPort 31680 HET TU2 20 VCLK DualPort 6480 ESRAM5 21 HCLK SinglePort 266280 ESRAM6 22 HCLK SinglePort 266280 23 8700 DualPort ETHERNET 24 VCLK3 6360

25 SinglePort 133160

26 DualPort 4240

27 SinglePort 66600

(1) Thereareseveralmemory testingalgorithmsstoredinthePBIST ROM. However,TIrecommends theMarch13N algorithmfor applicationtesting. The PBIST ROM clockfrequencyislimitedto 100MHz, if100MHz < HCLK <= HCLKmax, or HCLK, if HCLK <= 100MHz. The PBIST ROM clockisdivideddown fromHCLK. The dividerisselectedby programmingtheROM_DIV fieldoftheMemory Self-TestGlobalControlRegister(MSTGCR) ataddress0xFFFFFF58.

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4.13.2 On-Chip SRAM Auto Initialization

This microcontrollerallowssome of the on-chipmemories to be initializedviathe Memory Hardware Initializationmechanism in the System module. This hardware mechanism allowsan applicationto program thememory arrayswitherrordetectioncapabilitytoa known statebased on theirerrordetection scheme (odd/evenparityorECC). The MINITGCR registerenablesthe memory initializationsequence,and the MSINENA registerselects thememories thataretobe initialized. Formore informationon theseregisterssee thedeviceTechnicalReferenceManual. The mapping ofthedifferenton-chipmemories tothespecificbitsoftheMSINENA registersisshown in Table4-27. Table4-27.Memory Initialization ADDRESS RANGE CONNECTING MODULE MSINENA REGISTER BIT # BASE ADDRESS ENDING ADDRESS RAM (PD#1) 0x08000000 0x0800FFFF 0(1) RAM (RAM_PD#1) 0x08010000 0x0801FFFF 0(1) RAM (RAM_PD#2) 0x08020000 0x0802FFFF 0(1) MIBSPI5 RAM 0xFF0A0000 0xFF0BFFFF 12(2) MIBSPI3 RAM 0xFF0C0000 0xFF0DFFFF 11(2) MIBSPI1 RAM 0xFF0E0000 0xFF0FFFFF 7(2) DCAN3 RAM 0xFF1A0000 0xFF1BFFFF 10 DCAN2 RAM 0xFF1C0000 0xFF1DFFFF 6 DCAN1 RAM 0xFF1E0000 0xFF1FFFFF 5 MIBADC2 RAM 0xFF3A0000 0xFF3BFFFF 14 MIBADC1 RAM 0xFF3E0000 0xFF3FFFFF 8 N2HET2 RAM 0xFF440000 0xFF57FFFF 15 N2HET1 RAM 0xFF460000 0xFF47FFFF 3 HET TU2 RAM 0xFF4C0000 0xFF4DFFFF 16 HET TU1 RAM 0xFF4E0000 0xFF4FFFFF 4 DMA RAM 0xFFF80000 0xFFF80FFF 1 VIM RAM 0xFFF82000 0xFFF82FFF 2 USB DeviceRAM RAM isnotCPU-Addressable n/a EthernetRAM (CPPI Memory 0xFC520000 0xFC521FFF n/aSlave) (1) The TCM RAM wrapperhas separatecontrolbitstoselecttheRAM power domain thatistobe auto-initialized. (2) The MibSPIxmodules performan initializationofthetransmitand receiveRAMs as soon as themodule isreleasedfromitslocalreset.. ThisisindependentofwhethertheapplicationchoosestoinitializetheMibSPIxRAMs usingthesystemmodule auto-initialization method.The MibSPIxmodule must be firstbroughtoutofitslocalresetinordertouse thesystemmodule auto-initializationmethod. Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 87 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW EMIF_nCS[3:2] EMIF_BA[1:0] EMIF_ADDR[12:0] EMIF_nOE EMIF_DA T A[15:0] EMIF_nWE EMIF_nDQM[1:0] 3029 RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com

4.14 ExternalMemory Interface(EMIF)

4.14.1 Features

The EMIF includesmany featuresto enhance the ease and flexibilityof connectingto external asynchronousmemories orSDRAM devices.The EMIF featuresincludessupportfor:

• 3 addressablechipselectforasynchronousmemories ofup to32kB each
• 1 addressablechipselectspace forSDRAMs up to128MB
• 8 or16-bitdatabus width
• Programmable cycletimingssuch as setup,strobe,and holdtimesas wellas turnaroundtime
• Selectstrobemode
• ExtendedWaitmode
• Data bus parking

4.14.2 Electricaland Timing Specifications

4.14.2.1Read Timing (Asynchronous RAM) Figure4-12.Asynchronous Memory Read Timing

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PRODUCT□PREVIEW EMIF_nCS[3:2] EMIF_BA[1:0] EMIF_ADDR[12:0] EMIF_nWE EMIF_DAT A[15:0] EMIF_nOE EMIF_nDQM[1:0] EMIF_nCS[3:2] 1 1 Asserted Deasserted EMIF_BA[1:0] EMIF_ADDR[12:0] EMIF_DA T A[15:0] EMIF_nOE EMIF_WAIT SETUP Extended Due to EMIF_WAIT STROBE HOLD STROBE RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Figure4-13.EMIFnWAIT Read Timing Requirements 4.14.2.2WriteTiming (Asynchronous RAM) Figure4-14.Asynchronous Memory WriteTiming Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 89 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW EMIF_CLK EMIF_BA[1:0] EMIF_ADDR[12:0] EMIF_DAT A[15:0] 2 2 1 1 17 18

2 EM_CLK Delay

EMIF_nCS[0] EMIF_nDQM[1:0] EMIF_nRAS EMIF_nCAS EMIF_nWE EMIF_nCS[3:2] Asserted EMIF_BA[1:0] EMIF_ADDR[12:0] EMIF_DA T A[15:0] EMIF_nWE EMIF_WAIT SETUP Extended Due to EMIF_WAIT Deasserted STROBE STROBE HOLD RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com Figure4-15.EMIFnWAIT WriteTiming Requirements 4.14.2.3Read Timing (Synchronous RAM) Figure4-16.Basic SDRAM Read Operation

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PRODUCT□PREVIEW EMIF_CLK EMIF_BA[1:0] EMIF_ADDR[12:0] EMIF_DA T A[15:0] 2 2 1 1 BASIC SDRAM WRITE OPERA TION EMIF_CS[0] EMIF_DQM[1:0] EMIF_nRAS EMIF_nCAS EMIF_nWE RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 4.14.2.4WriteTiming (Synchronous RAM) Figure4-17.Basic SDRAM WriteOperation 4.14.2.5EMIF Asynchronous Memory Timing Table4-28.EMIF Asynchronous Memory Timing Requirements NO. Value Unit MIN NOM MAX Reads and Writes 2 tw(EM_WAIT) Pulseduration,EMIFnWAIT 2E ns assertionand deassertion Reads 12 tsu(EMDV-EMOEH) Setuptime,EMIFDATA[15:0] 11 ns validbeforeEMIFnOE high 13 th(EMOEH-EMDIV) Holdtime,EMIFDATA[15:0] 0.5 ns validafterEMIFnOE high 14 tsu(EMOEL-EMWAIT) SetupTime,EMIFnWAIT 4E+3 ns assertedbeforeend ofStrobe Phase (1) Writes 28 tsu(EMWEL-EMWAIT) SetupTime,EMIFnWAIT 4E+3 ns assertedbeforeend ofStrobe Phase(1) (1) Setupbeforeend ofSTROBE phase (ifno extendedwaitstatesareinserted)by whichEMIFnWAIT must be assertedtoadd extended waitstates.FigureFigure4-13and FigureFigure4-15describeEMIF transactionsthatincludeextendedwaitstatesinsertedduringthe STROBE phase.However,cyclesinsertedas partofthisextendedwaitperiodshouldnotbe counted;the4E requirementistothestart ofwhere theHOLD phase wouldbeginiftherewere no extendedwaitcycles. Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 91 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com Table4-29.EMIF Asynchronous Memory SwitchingCharacteristics(1)(2)(3) NO Parameter Value Unit MIN NOM MAX Reads and Writes 1 td(TURNAROUND) Turnaroundtime (TA)*E-3 (TA)*E (TA)*E+ 3 ns Reads 3 tc(EMRCYCLE) EMIF readcycletime(EW = 0) (RS+RST+RH)* (RS+RST+RH)* (RS+RST+RH)* ns E -3 E E + 3 EMIF readcycletime(EW = 1) (RS+RST+RH+( (RS+RST+RH+( (RS+RST+RH+( ns EWC*16))*E -3 EWC*16))*E EWC*16))*E + 4 tsu(EMCEL-EMOEL) Outputsetuptime, (RS)*E-3 (RS)*E (RS)*E+3 ns EMIFnCS[4:2]lowtoEMIFnOE low(SS = 0) Outputsetuptime, -3 0 +3 ns EMIFnCS[4:2]lowtoEMIFnOE low(SS = 1) 5 th(EMOEH-EMCEH) Outputholdtime,EMIFnOE high (RH)*E-3 (RH)*E (RH)*E+ 3 ns toEMIFnCS[4:2]high(SS = 0) Outputholdtime,EMIFnOE high -3 0 +3 ns toEMIFnCS[4:2]high(SS = 1) 6 tsu(EMBAV-EMOEL) Outputsetuptime,EMIFBA[1:0] (RS)*E-3 (RS)*E (RS)*E+3 ns validtoEMIFnOE low 7 th(EMOEH-EMBAIV) Outputholdtime,EMIFnOE high (RH)*E-3 (RH)*E (RH)*E+3 ns toEMIFBA[1:0]invalid 8 tsu(EMBAV-EMOEL) Outputsetuptime, (RS)*E-3 (RS)*E (RS)*E+3 ns EMIFADDR[12:0] validto EMIFnOE low 9 th(EMOEH-EMAIV) Outputholdtime,EMIFnOE high (RH)*E-3 (RH)*E (RH)*E+3 ns toEMIFADDR[12:0] invalid 10 tw(EMOEL) EMIFnOE activelowwidth(EW (RST)*E-3 (RST)*E (RST)*E+3 ns = 0) EMIFnOE activelowwidth(EW (RST+(EWC*16 (RST+(EWC*16 (RST+(EWC*16 ns 11 td(EMWAITH-EMOEH) DelaytimefromEMIFnWAIT 3E-3 4E 4E+3 ns deassertedtoEMIFnOE high Writes 15 tc(EMWCYCLE) EMIF writecycletime(EW = 0) (WS+WST+WH (WS+WST+WH (WS+WST+WH ns )*E-3 )*E )*E+3 EMIF writecycletime(EW = 1) (WS+WST+WH (WS+WST+WH (WS+WST+WH ns +(EWC*16))*E +(E WC*16))*E +(EWC*16))*E -3 + 3 16 tsu(EMCEL-EMWEL) Outputsetuptime, (WS)*E -3 (WS)*E (WS)*E + 3 ns EMIFnCS[4:2]lowtoEMIFnWE low(SS = 0) Outputsetuptime, -3 0 +3 ns EMIFnCS[4:2]lowtoEMIFnWE low(SS = 1) 17 th(EMWEH-EMCEH) Outputholdtime,EMIFnWE (WH)*E-3 (WH)*E (WH)*E+3 ns hightoEMIFnCS[4:2]high(SS = (1) TA = Turnaround,RS = Read setup,RST = Read strobe,RH = Read hold,WS = Writesetup,WST = Writestrobe,WH = Writehold, MEWC = Maximum externalwaitcycles.These parametersareprogrammed viatheAsynchronousBank and AsynchronousWaitCycle ConfigurationRegisters.These supportthefollowingrangesofvalues:TA[4–1],RS[16–1],RST[64–1],RH[8–1],WS[16 –1],WST[64 –1], WH[8 –1],and MEWC[1 –256].See theEMIF User’s guideformore information. (2) E = EMIF_CLK periodinns. (3) EWC = externalwaitcyclesdeterminedby EMIFnWAIT inputsignal.EWC supportsthefollowingrangeofvalues.EWC[256 –1].Note thatthemaximum waittimebeforetimeoutisspecifiedby bitfieldMEWC intheAsynchronousWaitCycleConfigurationRegister.See theEMIF User’s Guide formore information.

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Table4-29.EMIF Asynchronous Memory SwitchingCharacteristics(1)(2)(3)(continued) NO Parameter Value Unit MIN NOM MAX Outputholdtime,EMIFnWE -3 0 +3 ns hightoEMIFCS[4:2]high(SS = 18 tsu(EMDQMV-EMWEL) Outputsetuptime,EMIFBA[1:0] (WS)*E-3 (WS)*E (WS)*E+3 ns validtoEMIFnWE low 19 th(EMWEH-EMDQMIV) Outputholdtime,EMIFnWE (WH)*E-3 (WH)*E (WH)*E+3 ns hightoEMIFBA[1:0]invalid 20 tsu(EMBAV-EMWEL) Outputsetuptime,EMIFBA[1:0] (WS)*E-3 (WS)*E (WS)*E+3 ns validtoEMIFnWE low 21 th(EMWEH-EMBAIV) Outputholdtime,EMIFnWE (WH)*E-3 (WH)*E (WH)*E+3 ns hightoEMIFBA[1:0]invalid 22 tsu(EMAV-EMWEL) Outputsetuptime, (WS)*E-3 (WS)*E (WS)*E+3 ns EMIFADDR[12:0] validto EMIFnWE low 23 th(EMWEH-EMAIV) Outputholdtime,EMIFnWE (WH)*E-3 (WH)*E (WH)*E+3 ns hightoEMIFADDR[12:0] invalid 24 tw(EMWEL) EMIFnWE activelowwidth(EW (WST)*E-3 (WST)*E (WST)*E+3 ns = 0) EMIFnWE activelowwidth(EW (WST+(EWC*1 (WST+(EWC*1 (WST+(EWC*1 ns 25 td(EMWAITH-EMWEH) DelaytimefromEMIFnWAIT 3E-3 4E 4E+3 ns deassertedtoEMIFnWE high 26 tsu(EMDV-EMWEL) Outputsetuptime, (WS)*E-3 (WS)*E (WS)*E+3 ns EMIFDATA[15:0]validto EMIFnWE low 27 th(EMWEH-EMDIV) Outputholdtime,EMIFnWE (WH)*E-3 (WH)*E (WH)*E+3 ns hightoEMIFDATA[15:0]invalid Table4-30.EMIF Synchronous Memory Timing Requirements NO. Parameter MIN MAX Unit 19 tsu(EMIFDV-EM_CLKH) Inputsetuptime,readdatavalidon 1 ns EMIFDATA[15:0]beforeEMIF_CLK rising 20 th(CLKH-DIV) Inputholdtime,readdatavalidon 1.5 ns EMIFDATA[15:0]afterEMIF_CLK rising Table4-31.EMIF Synchronous Memory SwitchingCharacteristics NO. Parameter MIN MAX Unit 1 tc(CLK) Cycletime,EMIF clockEMIF_CLK 10 ns 2 tw(CLK) Pulsewidth,EMIF clockEMIF_CLK 3 ns highorlow 3 td(CLKH-CSV) Delaytime,EMIF_CLK risingto 7 ns EMIFnCS[0] valid 4 toh(CLKH-CSIV) Outputholdtime,EMIF_CLK risingto 1 ns EMIFnCS[0] invalid 5 td(CLKH-DQMV) Delaytime,EMIF_CLK risingto 7 ns EMIFnDQM[1:0] valid 6 toh(CLKH-DQMIV) Outputholdtime,EMIF_CLK risingto 1 ns EMIFnDQM[1:0] invalid 7 td(CLKH-AV) Delaytime,EMIF_CLK risingto 7 ns EMIFADDR[12:0] and EMIFBA[1:0] valid Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 93 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com Table4-31.EMIF Synchronous Memory SwitchingCharacteristics(continued) NO. Parameter MIN MAX Unit 8 toh(CLKH-AIV) Outputholdtime,EMIF_CLK risingto 1 ns EMIFADDR[12:0] and EMIFBA[1:0] invalid 9 td(CLKH-DV) Delaytime,EMIF_CLK risingto 7 ns EMIFDATA[15:0]valid 10 toh(CLKH-DIV) Outputholdtime,EMIF_CLK risingto 1 ns EMIFDATA[15:0]invalid 11 td(CLKH-RASV) Delaytime,EMIF_CLK risingto 7 ns EMIFnRAS valid 12 toh(CLKH-RASIV) Outputholdtime,EMIF_CLK risingto 1 ns EMIFnRAS invalid 13 td(CLKH-CASV) Delaytime,EMIF_CLK risingto 7 ns EMIFnCAS valid 14 toh(CLKH-CASIV) Outputholdtime,EMIF_CLK risingto 1 ns EMIFnCAS invalid 15 td(CLKH-WEV) Delaytime,EMIF_CLK risingto 7 ns EMIFnWE valid 16 toh(CLKH-WEIV) Outputholdtime,EMIF_CLK risingto 1 ns EMIFnWE invalid 17 tdis(CLKH-DHZ) Delaytime,EMIF_CLK risingto 7 ns EMIFDATA[15:0]tri-stated 18 tena(CLKH-DLZ) Outputholdtime,EMIF_CLK risingto 1 ns EMIFDATA[15:0]driving

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4.15 VectoredInterruptManager

The vectoredinterruptmanager (VIM) provideshardware assistanceforprioritizingand controllingthe many interruptsourcespresenton thisdevice.Interruptsarecaused by eventsoutsideofthenormalflow ofprogram execution.Normally,theseeventsrequirea timelyresponsefrom thecentralprocessingunit (CPU);therefore,when an interruptoccurs,theCPU switchesexecutionfromthenormalprogram flowto an interruptserviceroutine(ISR).

4.15.1 VIM Features

The VIM module has thefollowingfeatures:

• Supports128 interruptchannels. – Providesprogrammablepriorityand enableforinterruptrequestlines.
• Providesa directhardwaredispatchmechanism forfastestIRQ dispatch.
• Providestwo softwaredispatchmechanisms when theCPU VIC portisnotused. – Indexinterrupt – Registervectoredinterrupt
• Parityprotectedvectorinterrupttableagainstsofterrors.

4.15.2 InterruptRequest Assignments

Table4-32.InterruptRequest Assignments Modules InterruptSources DefaultVIM Interrupt Channel ESM ESM Highlevelinterrupt(NMI) 0 Reserved Reserved 1 RTI RTI compare interrupt0 2 RTI RTI compare interrupt1 3 RTI RTI compare interrupt2 4 RTI RTI compare interrupt3 5 RTI RTI overflowinterrupt0 6 RTI RTI overflowinterrupt1 7 RTI RTI timebaseinterrupt 8 GIO GIO interruptA 9 N2HET1 N2HET1 level0 interrupt 10 HET TU1 HET TU1 level0 interrupt 11 MIBSPI1 MIBSPI1 level0 interrupt 12 LIN LIN level0 interrupt 13 MIBADC1 MIBADC1 eventgroupinterrupt 14 MIBADC1 MIBADC1 sw group1 interrupt 15 DCAN1 DCAN1 level0 interrupt 16 SPI2 SPI2 level0 interrupt 17 Reserved Reserved 18 CRC CRC Interrupt 19 ESM ESM Low levelinterrupt 20 SYSTEM Softwareinterrupt(SSI) 21 CPU PMU Interrupt 22 GIO GIO interruptB 23 N2HET1 N2HET1 level1 interrupt 24 HET TU1 HET TU1 level1 interrupt 25 MIBSPI1 MIBSPI1 level1 interrupt 26 Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 95 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com Table4-32.InterruptRequest Assignments (continued) Modules InterruptSources DefaultVIM Interrupt Channel LIN LIN level1 interrupt 27 MIBADC1 MIBADC1 sw group2 interrupt 28 DCAN1 DCAN1 level1 interrupt 29 SPI2 SPI2 level1 interrupt 30 MIBADC1 MIBADC1 magnitudecompare interrupt 31 Reserved Reserved 32 DMA FTCA interrupt 33 DMA LFSA interrupt 34 DCAN2 DCAN2 level0 interrupt 35 MIBSPI3 MIBSPI3 level0 interrupt 37 MIBSPI3 MIBSPI3 level1 interrupt 38 DMA HBCA interrupt 39 DMA BTCA interrupt 40 EMIF AEMIFINT3 41 DCAN2 DCAN2 level1 interrupt 42 DCAN1 DCAN1 IF3interrupt 44 DCAN3 DCAN3 level0 interrupt 45 DCAN2 DCAN2 IF3interrupt 46 Reserved Reserved 47 Reserved Reserved 48 SPI4 SPI4 level0 interrupt 49 MIBADC2 MibADC2 eventgroupinterrupt 50 MIBADC2 MibADC2 sw group1interrupt 51 Reserved Reserved 52 MIBSPI5 MIBSPI5 level0 interrupt 53 SPI4 SPI4 level1 interrupt 54 DCAN3 DCAN3 level1 interrupt 55 MIBSPI5 MIBSPI5 level1 interrupt 56 MIBADC2 MibADC2 sw group2interrupt 57 Reserved Reserved 58 MIBADC2 MibADC2 magnitudecompare interrupt 59 DCAN3 DCAN3 IF3interrupt 60 FMC FSM_DONE interrupt 61 Reserved Reserved 62 N2HET2 N2HET2 level0 interrupt 63 SCI SCI level0 interrupt 64 HET TU2 HET TU2 level0 interrupt 65 I2C I2C level0 interrupt 66 USB Host OHCI_INT 67 USB Device USB_FUNC.IRQISOON 68 USB Device USB_FUNC.IRQGENION 69 USB Device USB_FUNC.IRQNONISOON 70 USB Device not(USB_FUNC.DSWAKEREQON) 71 USB Device USB_FUNC.USBRESETO 72 N2HET2 N2HET2 level1 interrupt 73 SCI SCI level1 interrupt 74 HET TU2 HET TU2 level1 interrupt 75

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Table4-32.InterruptRequest Assignments (continued) Modules InterruptSources DefaultVIM Interrupt Channel Ethernet C0_MISC_PULSE 76 Ethernet C0_TX_PULSE 77 Ethernet C0_THRESH_PULSE 78 Ethernet C0_RX_PULSE 79 HWAG1 HWA_INT_REQ_H 80 HWAG2 HWA_INT_REQ_H 81 DCC1 DCC done interrupt 82 DCC2 DCC2 done interrupt 83 Reserved Reserved 84 PBIST Controller PBIST Done Interrupt 85 Reserved Reserved 86-87 HWAG1 HWA_INT_REQ_L 88 HWAG2 HWA_INT_REQ_L 89 ePWM1INTn ePWM1 Interrupt 90 ePWM1TZINTn ePWM1 TripZone Interrupt 91 ePWM2INTn ePWM2 Interrupt 92 ePWM2TZINTn ePWM2 TripZone Interrupt 93 ePWM3INTn ePWM3 Interrupt 94 ePWM3TZINTn ePWM3 TripZone Interrupt 95 ePWM4INTn ePWM4 Interrupt 96 ePWM4TZINTn ePWM4 TripZone Interrupt 97 ePWM5INTn ePWM5 Interrupt 98 ePWM5TZINTn ePWM5 TripZone Interrupt 99 ePWM6INTn ePWM6 Interrupt 100 ePWM6TZINTn ePWM6 TripZone Interrupt 101 ePWM7INTn ePWM7 Interrupt 102 ePWM7TZINTn ePWM7 TripZone Interrupt 103 eCAP1INTn eCAP1 Interrupt 104 eCAP2INTn eCAP2 Interrupt 105 eCAP3INTn eCAP3 Interrupt 106 eCAP4INTn eCAP4 Interrupt 107 eCAP5INTn eCAP5 Interrupt 108 eCAP6INTn eCAP6 Interrupt 109 eQEP1INTn eQEP1 Interrupt 110 eQEP2INTn eQEP2 Interrupt 111 Reserved Reserved 112-127 NOTE Address location0x00000000 in the VIM RAM isreservedforthe phantom interruptISR entry;thereforeonlyrequestchannels0..126can be used and areoffsetby 1 addressinthe VIM RAM. Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 97 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com NOTE The EMIF_nWAIT signalhas a pull-upon it.The EMIF module generatesa "WaitRise" interruptwhenever itdetectsa risingedge on the EMIF_nWAIT signal.This interrupt conditionisindicatedas soon as the deviceispowered up. This can be ignoredifthe EMIF_nWAIT signalisnotused intheapplication.IftheEMIF_nWAIT signalisactuallyused intheapplication,thentheexternalslavememory must alwaysdrivetheEMIF_nWAIT signal such thatan interruptisnotcaused due tothedefaultpull-upon thissignal. NOTE The lower-orderinterruptchannelsarehigherprioritychannelsthanthehigher-orderinterrupt channels. NOTE The applicationcan change themapping ofinterruptsourcestotheinterruptchannelsviathe interruptchannelcontrolregisters(CHANCTRLx) insidetheVIM module.

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4.16 DMA Controller

The DMA controllerisused totransferdatabetween two locationsinthememory map inthebackground ofCPU operations.Typically,theDMA isused to:

• Transferblocksofdatabetween externaland internaldatamemories
• Restructureportionsofinternaldatamemory
• Continuallyservicea peripheral

4.16.1 DMA Features

• CPU independentdatatransfer
• One 64-bitmasterportthatinterfacestotheRM4x Memory System.
• FIFO buffer(4entriesdeep and each 64bitwide)
• ChannelcontrolinformationisstoredinRAM protectedby parity
• 16 channelswithindividualenable
• Channelchainingcapability
• 32 peripheralDMA requests
• Hardware and SoftwareDMA requests
• 8,16,32 or64-bittransactionssupported
• Multipleaddressingmodes forsource/destination(fixed,increment,offset)
• Auto-initiation
• Power-management mode
• Memory Protectionwithfourconfigurablememory regions Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 99 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

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4.16.2 DefaultDMA Request Map

The DMA module on thismicrocontrollerhas 16 channelsand up to 32 hardware DMA requests.The module containsDREQASIx registerswhichareused tomap theDMA requeststotheDMA channels.By default,channel0 ismapped torequest0,channel1 torequest1,and so on. Some DMA requestshave multiplesources,as shown inTable 4-33. The applicationmust ensure that onlyone oftheseDMA requestsourcesisenabledatany time. Table4-33.DMA Request LineConnection Modules DMA Request Sources DMA Request MIBSPI1 MIBSPI11 DMAREQ[0] MIBSPI1 MIBSPI10 DMAREQ[1] SPI2 SPI2 receive DMAREQ[2] SPI2 SPI2 transmit DMAREQ[3] MIBSPI1 /MIBSPI3 /DCAN2 MIBSPI1[2]/MIBSPI3[2]/DCAN2 IF3 DMAREQ[4] MIBSPI1 /MIBSPI3 /DCAN2 MIBSPI1[3]/MIBSPI3[3]/DCAN2 IF2 DMAREQ[5] DCAN1 /MIBSPI5 DCAN1 IF2/MIBSPI5[2] DMAREQ[6] MIBADC1 /MIBSPI5 MIBADC1 event/MIBSPI5[3] DMAREQ[7] MIBSPI1 /MIBSPI3 /DCAN1 MIBSPI1[4]/MIBSPI3[4]/DCAN1 IF1 DMAREQ[8] MIBSPI1 /MIBSPI3 /DCAN2 MIBSPI1[5]/MIBSPI3[5]/DCAN2 IF1 DMAREQ[9] MIBADC1 /I2C /MIBSPI5 MIBADC1 G1 /I2C receive/MIBSPI5[4] DMAREQ[10] MIBADC1 /I2C /MIBSPI5 MIBADC1 G2 /I2C transmit/MIBSPI5[5] DMAREQ[11] RTI /MIBSPI1 /MIBSPI3 RTI DMAREQ0 /MIBSPI1[6]/MIBSPI3[6] DMAREQ[12] RTI /MIBSPI1 /MIBSPI3 RTI DMAREQ1 /MIBSPI1[7]/MIBSPI3[7] DMAREQ[13] MIBSPI3 /USB Device/MibADC2 /MIBSPI5 MIBSPI31/USB_FUNC.DMATXREQ_ON[0] / DMAREQ[14] MibADC2 event/MIBSPI5[6] MIBSPI3 /USB Device/MIBSPI5 MIBSPI30/USB_FUNC.DMARXREQ_ON[0] / DMAREQ[15] MIBSPI5[7] MIBSPI1 /MIBSPI3 /DCAN1 /MibADC2 MIBSPI1[8]/MIBSPI3[8]/DCAN1 IF3/MibADC2 G1 DMAREQ[16] MIBSPI1 /MIBSPI3 /DCAN3 /MibADC2 MIBSPI1[9]/MIBSPI3[9]/DCAN3 IF1/MibADC2 G2 DMAREQ[17] RTI /USB Device/MIBSPI5 RTI DMAREQ2 /USB_FUNC.DMATXREQ_ON[1] / DMAREQ[18] MIBSPI5[8] RTI /USB Device/MIBSPI5 RTI DMAREQ3 /USB_FUNC.DMARXREQ_ON[1] / DMAREQ[19] MIBSPI5[9] N2HET1 /N2HET2 /DCAN3 N2HET1 DMAREQ[4] /N2HET2 DMAREQ[4] /DCAN3 DMAREQ[20] IF2 N2HET1 /N2HET2 /DCAN3 N2HET1 DMAREQ[5] /N2HET2 DMAREQ[5] /DCAN3 DMAREQ[21] IF3 MIBSPI1 /MIBSPI3 /MIBSPI5 MIBSPI1[10]/MIBSPI3[10]/MIBSPI5[10] DMAREQ[22] MIBSPI1 /MIBSPI3 /MIBSPI5 MIBSPI1[11]/MIBSPI3[11]/MIBSPI5[11] DMAREQ[23] N2HET1 /N2HET2 /SPI4 /MIBSPI5 N2HET1 DMAREQ[6] /N2HET2 DMAREQ[6] /SPI4 DMAREQ[24] receive/MIBSPI5[12] N2HET1 /N2HET2 /SPI4 /MIBSPI5 N2HET1 DMAREQ[7] /N2HET2 DMAREQ[7] /SPI4 DMAREQ[25] transmit/MIBSPI5[13] CRC /MIBSPI1 /MIBSPI3 CRC DMAREQ[0] /MIBSPI1[12]/MIBSPI3[12] DMAREQ[26] CRC /MIBSPI1 /MIBSPI3 CRC DMAREQ[1] /MIBSPI1[13]/MIBSPI3[13] DMAREQ[27] LIN /USB Device/MIBSPI5 LIN receive/USB_FUNC.DMATXREQ_ON[2] / DMAREQ[28] MIBSPI5[14] LIN /USB Device/MIBSPI5 LIN transmit/USB_FUNC.DMARXREQ_ON[2] / DMAREQ[29] MIBSPI5[15] MIBSPI1 /MIBSPI3 /SCI /MIBSPI5 MIBSPI1[14]/MIBSPI3[14]/SCI receive/ DMAREQ[30] MIBSPI51 (1) SPI1,SPI3,SPI5 receivewhen configuredinstandardSPI mode (2) SPI1,SPI3,SPI5 transmitwhen configuredinstandardSPI mode

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Table4-33.DMA Request LineConnection (continued) Modules DMA Request Sources DMA Request MIBSPI1 /MIBSPI3 /SCI /MIBSPI5 MIBSPI1[15]/MIBSPI3[15]/SCI transmit/ DMAREQ[31] MIBSPI50 Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 101 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RTICLK External control CAP event□source□0 CAP event□source□1 =Up□counter Capture up□counter Compare up□counter Free□running□counter Capture RTIFRCx free□running□counter RTICAFRCx OVLINTxRTICPUCx RTIUCx RTICAUCx To□Compare UnitNTU0 NTU1 NTU2 NTU3 RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com

4.17 Real Time InterruptModule

The real-timeinterrupt(RTI) module providestimer functionalityfor operatingsystems and for benchmarkingcode.The RTI module can incorporateseveralcountersthatdefinethetimebasesneeded forschedulingan operatingsystem. The timersalsoallowyou tobenchmark certainareasofcode by readingthevaluesofthecountersatthe beginningand theend ofthedesiredcode rangeand calculatingthedifferencebetween thevalues.

4.17.1 Features

The RTI module has thefollowingfeatures:

• Two independent64 bitcounterblocks
• Four configurablecompares forgeneratingoperatingsystem ticksor DMA requests.Each eventcan be drivenby eithercounterblock0 orcounterblock1.
• Fastenabling/disablingofevents
• Two time-stamp(capture)functionsforsystemorperipheralinterrupts,one foreach counterblock

4.17.2 Block Diagrams

Figure4-18 shows a high-levelblockdiagram forone of the two 64-bitcounterblocksinsidethe RTI module. Both the counterblocksare identicalexceptthe Network Time Unit(NTUx) inputsare only availableas timebase inputsforthecounterblock0. Figure4-18.Counter Block Diagram

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PRODUCT□PREVIEW 31 0 Compare control INTy DMAREQyCompare Update compare From counter block 0 From counter block 1 RTIUDCPy RTICOMPy 31 0 RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Figure4-19.Compare Block Diagram

4.17.3 Clock Source Options

The RTI module uses theRTI1CLK clockdomain forgeneratingtheRTI timebases. The applicationcan selecttheclocksourcefortheRTI1CLK by configuringtheRCLKSRC registerinthe System module ataddress0xFFFFFF50. The defaultsourceforRTI1CLK isVCLK. Formore informationon clocksourcesrefertoTable4-8and Table4-13.

4.17.4 Network Time SynchronizationInputs

The RTI module supports4 NetworkTime Unit(NTU) inputsthatsignalinternalsystem events,and which can be used tosynchronizethetimebase used by theRTI module.On thisdevice,theseNTU inputsare connectedas shown below. Table4-34.Network Time SynchronizationInputs NTU Input Source

0 Reserved

1 Reserved

2 PLL2 Clockoutput

3 EXTCLKIN1 clockinput

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4.18 ErrorSignalingModule

The ErrorSignalingModule (ESM) manages thevariouserrorconditionson theRM4x microcontroller.The errorconditionishandledbased on a fixedseveritylevelassignedtoit.Any severeerrorconditioncan be configuredtodrivea low levelon a dedicateddeviceterminalcallednERROR. Thiscan be used as an indicatortoan externalmonitorcircuittoputthesystemintoa safestate.

4.18.1 Features

The featuresoftheErrorSignalingModule are:

• 128 interrupt/errorchannelsaresupported,dividedinto3 differentgroups – 64 channelswithmaskableinterruptand configurableerrorpinbehavior – 32 errorchannelswithnon-maskableinterruptand predefinederrorpinbehavior – 32 channelswithpredefinederrorpinbehavioronly
• Errorpintosignalseveredevicefailure
• Configurabletimebaseforerrorsignal
• Errorforcingcapability

4.18.2 ESM Channel Assignments

The ErrorSignalingModule (ESM) integratesallthedeviceerrorconditionsand groupsthem intheorder ofseverity.Group1 isused forerrorsofthelowestseveritywhileGroup3 isused forerrorsofthehighest severity.The deviceresponse to each erroris determinedby the severitygroup itis connected to. Table4-36shows thechannelassignmentforeach group. Table4-35.ESM Groups ERROR GROUP INTERRUPT CHARACTERISTICS INFLUENCE ON ERROR PIN Group1 maskable,loworhighpriority configurable Group2 non-maskable,highpriority fixed Group3 no interruptgenerated fixed Table4-36.ESM Channel Assignments ERROR Condition Group Channels Reserved Group1 0 MibADC2 -RAM parityerror Group1 1 DMA -MPU configurationviolation Group1 2 DMA -controlpacketRAM parityerror Group1 3 Reserved Group1 4 DMA -erroron DMA readaccess,impreciseerror Group1 5 FMC -correctableECC error:bus1 and bus2 interfaces Group1 6 (doesnotincludeaccessestoBank 7) N2HET1 -RAM parityerror Group1 7 HET TU1/HET TU2 -dual-controlpacketRAM parityerror Group1 8 HET TU1/HET TU2 -MPU configurationviolation Group1 9 PLL1 -Slip Group1 10 ClockMonitor-oscillatorfail Group1 11 Reserved Group1 12 DMA -erroron DMA writeaccess,impreciseerror Group1 13 Reserved Group1 14 VIM RAM -parityerror Group1 15 Reserved Group1 16 MibSPI1 -RAM parityerror Group1 17

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Table4-36.ESM Channel Assignments (continued) ERROR Condition Group Channels MibSPI3 -RAM parityerror Group1 18 MibADC1 -RAM parityerror Group1 19 Reserved Group1 20 DCAN1 -RAM parityerror Group1 21 DCAN3 -RAM parityerror Group1 22 DCAN2 -RAM parityerror Group1 23 MibSPI5 -RAM parityerror Group1 24 Reserved Group1 25 RAM even bank (B0TCM) -correctableECC error Group1 26 CPU -self-testfailed Group1 27 RAM odd bank (B1TCM) -correctableECC error Group1 28 Reserved Group1 29 DCC1 -error Group1 30 CCM-R4 -self-testfailed Group1 31 Reserved Group1 32 Reserved Group1 33 N2HET2 -RAM parityerror Group1 34 FMC -correctableECC error(Bank7 access) Group1 35 FMC -uncorrectableECC error(Bank7 access) Group1 36 IOMM -Access tounimplementedlocationinIOMM frame,orwriteaccess Group1 37 detectedinunprivilegedmode Power domain controllercompare error Group1 38 Power domain controllerself-testerror Group1 39 eFuse farmerror– thiserrorsignalisgeneratedwhen any bitintheeFuse farm Group1 40 errorstatusregisterisset.The applicationcan choose togeneratean interrupt whenever thisbitissettoserviceany eFuse farmerrorconditions. eFuse farm-selftesterror.Thiserrorsignalisgeneratedonlywhen a selfteston Group1 41 theeFuse controllergeneratesan errorcondition.When thiserrorsignalisset, group1 channel40 errorsignalwillalsobe set. PLL#2 -Slip Group1 42 EthernetControllerbus masteraccesserror Group1 43 USB HostControllermasterinterface Group1 44 Reserved Group1 45 Reserved Group1 46 Reserved Group1 47 Reserved Group1 48 Reserved Group1 49 Reserved Group1 50 Reserved Group1 51 Reserved Group1 52 Reserved Group1 53 Reserved Group1 54 Reserved Group1 55 Reserved Group1 56 Reserved Group1 57 Reserved Group1 58 Reserved Group1 59 Reserved Group1 60 Reserved Group1 61 Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 105 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com Table4-36.ESM Channel Assignments (continued) ERROR Condition Group Channels DCC2 -error Group1 62 Reserved Group1 63 Reserved Group2 0 Reserved Group2 1 CCMR4 -dual-CPU lock-steperror Group2 2 Reserved Group2 3 FMC -uncorrectableaddressparityerroron accessestomain flash Group2 4 Reserved Group2 5 RAM even bank (B0TCM) -uncorrectableredundantaddressdecode error Group2 6 Reserved Group2 7 RAM odd bank (B1TCM) -uncorrectableredundantaddressdecode error Group2 8 Reserved Group2 9 RAM even bank (B0TCM) -addressbus parityerror Group2 10 Reserved Group2 11 RAM odd bank (B1TCM) -addressbus parityerror Group2 12 Reserved Group2 13 Reserved Group2 14 Reserved Group2 15 Flash(ATCM) -ECC livelockdetect Group2 16 Reserved Group2 17 Reserved Group2 18 Reserved Group2 19 Reserved Group2 20 Reserved Group2 21 Reserved Group2 22 Reserved Group2 23 Windowed Watchdog (WWD) violation Group2 24 Reserved Group2 25 Reserved Group2 26 Reserved Group2 27 Reserved Group2 28 Reserved Group2 29 Reserved Group2 30 Reserved Group2 31 Reserved Group3 0 eFuse Farm -autoloaderror Group3 1 Reserved Group3 2 RAM even bank (B0TCM) -ECC uncorrectableerror Group3 3 Reserved Group3 4 RAM odd bank (B1TCM) -ECC uncorrectableerror Group3 5 Reserved Group3 6 FMC -uncorrectableECC error:bus1 and bus2 interfaces Group3 7 (doesnotincludeaddressparityerrorand errorson accessestoBank 7) Reserved Group3 8 Reserved Group3 9 Reserved Group3 10 Reserved Group3 11 Reserved Group3 12

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Table4-36.ESM Channel Assignments (continued) ERROR Condition Group Channels Reserved Group3 13 Reserved Group3 14 Reserved Group3 15 Reserved Group3 16 Reserved Group3 17 Reserved Group3 18 Reserved Group3 19 Reserved Group3 20 Reserved Group3 21 Reserved Group3 22 Reserved Group3 23 Reserved Group3 24 Reserved Group3 25 Reserved Group3 26 Reserved Group3 27 Reserved Group3 28 Reserved Group3 29 Reserved Group3 30 Reserved Group3 31 Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 107 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

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4.19 Reset /Abort /ErrorSources

Table4-37.Reset/Abort/ErrorSources ESM HOOKUPERROR SOURCE SYSTEM MODE ERROR RESPONSE group.channel CPU TRANSACTIONS Precisewriteerror(NCNB/StronglyOrdered) User/Privilege PreciseAbort(CPU) n/a Precisereaderror(NCB/DeviceorNormal) User/Privilege PreciseAbort(CPU) n/a Imprecisewriteerror(NCB/DeviceorNormal) User/Privilege ImpreciseAbort(CPU) n/a UndefinedInstructionTrapIllegalinstruction User/Privilege n/a(CPU)(1) MPU accessviolation User/Privilege Abort(CPU) n/a SRAM B0 TCM (even)ECC singleerror(correctable) User/Privilege ESM 1.26 Abort(CPU),ESM =>B0 TCM (even)ECC doubleerror(non-correctable) User/Privilege 3.3nERROR B0 TCM (even)uncorrectableerror(i.e.redundantaddress User/Privilege ESM => NMI => nERROR 2.6decode) B0 TCM (even)addressbus parityerror User/Privilege ESM => NMI => nERROR 2.10 B1 TCM (odd)ECC singleerror(correctable) User/Privilege ESM 1.28 Abort(CPU),ESM =>B1 TCM (odd)ECC doubleerror(non-correctable) User/Privilege 3.5nERROR B1 TCM (odd)uncorrectableerror(i.e.redundantaddress User/Privilege ESM => NMI => nERROR 2.8decode) B1 TCM (odd)addressbus parityerror User/Privilege ESM => NMI => nERROR 2.12 FLASH WITH CPU BASED ECC FMC correctableerror-Bus1 and Bus2 interfaces(doesnot User/Privilege ESM 1.6includeaccessestoBank 7) FMC uncorrectableerror-Bus1 and Bus2 accesses Abort(CPU),ESM =>User/Privilege 3.7(doesnotincludeaddressparityerror) nERROR FMC uncorrectableerror-addressparityerroron Bus1 User/Privilege ESM => NMI => nERROR 2.4accesses FMC correctableerror-AccessestoBank 7 User/Privilege ESM 1.35 FMC uncorrectableerror-AccessestoBank 7 User/Privilege ESM 1.36 DMA TRANSACTIONS Externalimpreciseerroron read(Illegaltransactionwithok User/Privilege ESM 1.5response) Externalimpreciseerroron write(Illegaltransactionwithok User/Privilege ESM 1.13response) Memory accesspermissionviolation User/Privilege ESM 1.2 Memory parityerror User/Privilege ESM 1.3 HET TU1 (HTU1) NCNB (StronglyOrdered)transactionwithslaveerrorresponse User/Privilege Interrupt=> VIM n/a Externalimpreciseerror(Illegaltransactionwithok response) User/Privilege Interrupt=> VIM n/a Memory accesspermissionviolation User/Privilege ESM 1.9 Memory parityerror User/Privilege ESM 1.8 HET TU2 (HTU2) NCNB (StronglyOrdered)transactionwithslaveerrorresponse User/Privilege Interrupt=> VIM n/a Externalimpreciseerror(Illegaltransactionwithok response) User/Privilege Interrupt=> VIM n/a Memory accesspermissionviolation User/Privilege ESM 1.9 Memory parityerror User/Privilege ESM 1.8 (1) The UndefinedInstructionTRAP isNOT detectableoutsidetheCPU. The trapistakenonlyiftheinstructionreachestheexecutestage oftheCPU.

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Table4-37.Reset/Abort/ErrorSources (continued) ESM HOOKUPERROR SOURCE SYSTEM MODE ERROR RESPONSE group.channel N2HET1 Memory parityerror User/Privilege ESM 1.7 N2HET2 Memory parityerror User/Privilege ESM 1.34 ETHERNET MASTER INTERFACE Any errorreportedby slavebeingaccessed User/Privilege ESM 1.43 USB HOST CONTROLLER (OHCI)MASTER INTERFACE Any errorreportedby slavebeingaccessed User/Privilege ESM 1.44 MIBSPI MibSPI1 memory parityerror User/Privilege ESM 1.17 MibSPI3 memory parityerror User/Privilege ESM 1.18 MibSPI5 memory parityerror User/Privilege ESM 1.24 MIBADC MibADC1 Memory parityerror User/Privilege ESM 1.19 MibADC2 Memory parityerror User/Privilege ESM 1.1 DCAN DCAN1 memory parityerror User/Privilege ESM 1.21 DCAN2 memory parityerror User/Privilege ESM 1.23 DCAN3 memory parityerror User/Privilege ESM 1.22 PLL PLL sliperror User/Privilege ESM 1.10 PLL #2 sliperror User/Privilege ESM 1.42 CLOCK MONITOR Clockmonitorinterrupt User/Privilege ESM 1.11 DCC DCC1 error User/Privilege ESM 1.30 DCC2 error User/Privilege ESM 1.62 CCM-R4 Selftestfailure User/Privilege ESM 1.31 Compare failure User/Privilege ESM => NMI => nERROR 2.2 VIM Memory parityerror User/Privilege ESM 1.15 VOLTAGE MONITOR VMON outofvoltagerange n/a Reset n/a CPU SELFTEST (LBIST) CPU Selftest(LBIST)error User/Privilege ESM 1.27 PIN MULTIPLEXING CONTROL Mux configurationerror User/Privilege ESM 1.37 POWER DOMAIN CONTROL PSCON compare error User/Privilege ESM 1.38 PSCON self-testerror User/Privilege ESM 1.39 eFuse CONTROLLER eFuse ControllerAutoloaderror User/Privilege ESM => nERROR 3.1 eFuse Controller-Any bitsetintheerrorstatusregister User/Privilege ESM 1.40 eFuse Controllerself-testerror User/Privilege ESM 1.41 WINDOWED WATCHDOG WWD Non-MaskableInterruptexception n/a ESM => NMI => nERROR 2.24 Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 109 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com Table4-37.Reset/Abort/ErrorSources (continued) ESM HOOKUPERROR SOURCE SYSTEM MODE ERROR RESPONSE group.channel ERRORS REFLECTED IN THE SYSESR REGISTER Power-Up Reset n/a Reset n/a Oscillatorfail/PLL slip(2) n/a Reset n/a Watchdog exception n/a Reset n/a CPU Reset(drivenby theCPU STC) n/a Reset n/a SoftwareReset n/a Reset n/a ExternalReset n/a Reset n/a (2) Oscillatorfail/PLLslipcan be configuredinthesystemregister(SYS.PLLCTL1) togeneratea reset.

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4.20 DigitalWindowed Watchdog

Thisdeviceincludesa digitalwindowed watchdog (DWWD) module thatprotectsagainstrunaway code execution. The DWWD module allowstheapplicationtoconfigurethetimewindow withinwhichtheDWWD module expectstheapplicationtoservicethewatchdog.A watchdogviolationoccursiftheapplicationservicesthe watchdog outsideof thiswindow, or failsto servicethe watchdog at all.The applicationcan choose to generatea systemresetoran ESM group2errorsignalincase ofa watchdogviolation. The watchdog isdisabledby defaultand must be enabledby theapplication.Once enabled,thewatchdog can onlybe disabledupon a systemreset. Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 111 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW TRST TMS TCK TDI TDO RTCK ICEPICK_C Boundary□Scan BSR/BSDL Boundary□Scan□I/F Secondary□Tap□0 DAP Debug APB Debug ROM1 APB□slave Cortex R4F APB□Mux AHB-AP POM to□SCR1□via A2A from PCR1/Bridge Test□Tap□0 eFuse□Farm Secondary□Tap□2 AJSM Test□Tap□1 PSCON RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com

4.21 Debug Subsystem

4.21.1 Block Diagram

The devicecontainsan ICEPICK module toallowJTAG accesstothescan chains. Figure4-20.Debug Subsystem Block Diagram

4.21.2 Debug Components Memory Map

Table4-38.Debug Components Memory Map FRAME ADDRESS RANGE RESPNSE FOR ACCESS TOFRAME CHIP FRAME ACTUAMODULE NAME UNIMPLEMENTED LOCATIONS INSELECT SIZE L SIZESTART END FRAME CoreSightDebug Reads returnzeros,writeshave noCSCS0 0xFFA0_0000 0xFFA0_0FFF 4kB 4kBROM effect Cortex-R4F Reads returnzeros,writeshave noCSCS1 0xFFA0_1000 0xFFA0_1FFF 4kB 4kBDebug effect

4.21.3 JTAG IdentificationCode

The JTAG ID code forthisdeviceis0x0B95502F. Thisisthesame as thedeviceICEPickIdentification Code.

4.21.4 Debug ROM

The Debug ROM storesthelocationofthecomponents on theDebug APB bus:

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Table4-39.Debug ROM table ADDRESS DESCRIPTION VALUE 0x000 pointertoCortex-R4F 0x0000 1003 0x001 Reserved 0x0000 2002 0x002 Reserved 0x0000 3002 0x003 POM 0x0000 4003 0x004 end oftable 0x0000 0000 Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 113 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW 1 1 TMS TDI TDO RTCK TCK RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com

4.21.5 JTAG Scan InterfaceTimings

Table4-40.JTAG Scan InterfaceTiming(1) No. Parameter Min MAX Unit fTCK TCK frequency(atHCLKmax) 12 MHz fRTCK RTCK frequency(atTCKmax and HCLKmax) 10 MHz 1 td(TCK-RTCK) Delaytime,TCK toRTCK 24 ns 2 tsu(TDI/TMS-RTCKr) Setuptime,TDI,TMS beforeRTCK rise(RTCKr) 21 ns 3 th(RTCKr-TDI/TMS) Holdtime,TDI,TMS afterRTCKr 0 ns 4 th(RTCKr-TDO) Holdtime,TDO afterRTCKf 0 ns 5 td(TCKf-TDO) Delaytime,TDO validafterRTCK fall(RTCKf) 10 ns (1) TimingsforTDO arespecifiedfora maximum of50pF loadon TDO Figure4-21.JTAG Timing

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PRODUCT□PREVIEW H L H L H L L H .□.□. .□.□. 128-bit□comparator H L L H H L L H UNLOCK Flash□Module□Output OTP Contents Unlock□By□Scan Register Internal□Tie-Offs (example□only) (example) L H H L LInternal□Tie-Offs (example□only) L H H RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012

4.21.6 Advanced JTAG SecurityModule

Thisdeviceincludesa an Advanced JTAG SecurityModule (AJSM).whichprovidesmaximum securityto thedevice’s memory contentby allowinguserstosecurethedeviceafterprogramming. Figure4-22.AJSM Unlock The deviceisunsecure by defaultby virtueof a 128-bitvisibleunlockcode programmed in the OTP address0xF0000000.The OTP contentsare XOR-ed withthe "UnlockBy Scan" registercontents.The outputsoftheseXOR gatesare againcombined witha setofsecretinternaltie-offs.The outputofthis combinationallogicis compared againsta secrethard-wired128-bitvalue.A match resultsin the UNLOCK signalbeingasserted,so thatthedeviceisnow unsecure. A usercan securethedeviceby changingatleastone bitinthevisibleunlockcode from1 to0.Changing a 0 to1 isnotpossiblesincethevisibleunlockcode isstoredintheOne Time Programmable (OTP) flash region.Also,changingallthe128 bitstozerosisnota validconditionand willpermanentlysecurethe device. Once secured,a user can unsecurethe deviceby scanningan appropriatevalueintothe "UnlockBy Scan" registeroftheAJSM module.Thisregisterisaccessibleby configuringan IR valueof0b1011 on theAJSM TAP. The valuetobe scanned issuch thattheXOR oftheOTP contentsand theUnlock-By- Scan registercontentsresultsintheoriginalvisibleunlockcode. The Unlock-By-Scanregisterisresetonlyupon assertingpower-onreset(nPORRST). A securedeviceonlypermitsJTAG accessestotheAJSM scan chainviatheSecondary Tap # 2 ofthe ICEPickmodule.Allothersecondarytaps,testtapsand theboundaryscan interfacearenotaccessiblein thisstate. Copyright© 2012,Texas InstrumentsIncorporated System Informationand ElectricalSpecifications 115 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW TRST TMS TCK TDI TDO RTCK IC EPICK Boundary BSDL Boundary Scan Interface Scan Device Pins (conceptual) TDI TDO RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com

4.21.7 Boundary Scan Chain

The devicesupportsBSDL-compliantboundary scan fortestingpin-to-pincompatibility.The boundary scan chainisconnectedtotheBoundaryScan InterfaceoftheICEPICK module. Figure4-23.Boundary Scan Implementation(ConceptualDiagram) Data isseriallyshiftedintoallboundary-scanbuffersviaTDI,and outviaTDO.

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PRODUCT□PREVIEW SOCA1,□SOCB1 EPWM1INTn EPWM1TZINTn EQEP1ERR□/□EQEP2ERR□/ EQEP1ERR□or□EQEP2ERR Debug□Mode□Entry OSC□FAIL or□PLL Slip IOMUX EPWMSYNCI EPWM1 ECAP EPWM1A EPWM1B EPWM2/3/4/5/6A EPWM2/3/4/5/6B EPWM EPWM7A ECAP1 Pulse Stretch, 8□VCLK4 cycles EPWMSYNCO ADC□Wrapper VBus32□/□VBus32DP TZ1/2/3n EPWM1ENCLK TBCLKSYNC VIM VCLK4,□SYS_nRST EPWM2/3/4/5/6ENCLK TBCLKSYNC EPWM7ENCLK TBCLKSYNC ECAP1INTn EPWM 2/3/4/5/6 VIM EQEP1□+□EQEP2 EPWM7B CPU System□Module TZ6n TZ5n TZ4n VCLK4,□SYS_nRST TZ1/2/3n TZ1/2/3n Debug□Mode□Entry OSC□FAIL or□PLL Slip TZ6n TZ5n TZ4n Debug□Mode□Entry OSC□FAIL or□PLL SLip TZ6n TZ5n TZ4n SOCA2/3/4/5/6 SOCB2/3/4/5/6 EPWM2/3/4/5/6INTn EPWM2/3/4/5/6TZINTn EPWM7INTn EPWM7TZINTn VBus32 VBus32 VCLK4,□SYS_nRST VBus32 VIM ADC□Wrapper VIM EQEP1□+□EQEP2 CPU System□Module VIM ADC□Wrapper VIM EQEP1□+□EQEP2 CPU System□Module VIM Mux Selector Mux Selector EQEP1ERR□/□EQEP2ERR□/ EQEP1ERR□or□EQEP2ERR EQEP1ERR□/□EQEP2ERR□/ EQEP1ERR□or□EQEP2ERR SOCA7,□SOCB7Mux Selector NHET1_LOOP_SYNC PINMMR36[25] RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012

5 PeripheralInformationand ElectricalSpecifications

5.1 Enhanced TranslatorPWM Modules (ePWM)

Figure5-1 illustratesthe connectionsbetween the seven ePWM modules (ePWM1,2,3,4,5,6,7)on the device. Figure5-1.ePWMx Module Interconnections Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 117 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW N2HET1 N2HET2 ePWM1 2□VCLK4□cycles Pulse□Strength ePWM1_SYNCI SYNCI EXT_LOOP_SYNCN2HET1_LOOP_SYNC ePWM1_SYNCI_SYNCED ePWM1_SYNCI_FILTERED PINMMR47[8,9,10] PINMMR36[25] RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com 5.1.1 ePWM Clockingand Reset Each ePWM module has a clockenable (EPWMxENCLK). When SYS_nRST isactivelow,the clock enables are ignoredand the ePWM logicis clockedso thatitcan resetto a properstate.When SYS_nRST goes in-activehigh,thestateofclockenableisrespected. Table5-1.ePWMx Clock Enable Control ePWM Module Instance ControlRegistertoEnable Clock DefaultValue ePWM1 PINMMR37[8] 1 ePWM2 PINMMR37[16] 1 ePWM3 PINMMR37[24] 1 ePWM4 PINMMR38[0] 1 ePWM5 PINMMR38[8] 1 ePWM6 PINMMR38[16] 1 ePWM7 PINMMR38[24] 1 The defaultvalueofthecontrolregisterstoenabletheclockstotheePWMx modules is1.Thismeans thatthe VCLK4 clockconnectionsto the ePWMx modules are enabledby default.The applicationcan choose togateofftheVCLK4 clocktoany ePWMx module individuallyby clearingtherespectivecontrol registerbit.

5.1.2 SynchronizationofePWMx Time Base Counters

A time-basesynchronizationscheme connectsallof the ePWM modules on a device.Each ePWM module has a synchronizationinput(EPWMxSYNCI) and a synchronizationoutput(EPWMxSYNCO). The inputsynchronizationforthe firstinstance(ePWM1) comes from an externalpin.Figure5-1 shows the synchronizationconnectionsforalltheePWMx modules.Each ePWM module can be configuredtouse or ignorethesynchronizationinput.RefertotheePWM chapterinthedeviceTechnicalReferenceManual formore information.

5.1.3 SynchronizingallePWM Modules totheN2HET1 Module Time Base

The connectionbetween theN2HET1_LOOP_SYNC and SYNCI inputofePWM1 module isimplemented as shown inFigure5-2. Figure5-2.SynchronizingTime Bases Between N2HET1, N2HET2 and ePWMx Modules

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5.1.4 Phase-Locking theTime-Base Clocks ofMultipleePWM Modules

The TBCLKSYNC bitcan be used to globallysynchronizethe time-baseclocksof allenabled ePWM modules on a device.Thisbitisimplementedas PINMMR37 registerbit1. When TBCLKSYNC = 0, the time-baseclockof allePWM modules is stopped.This is the default condition. When TBCLKSYNC = 1,allePWM time-baseclocksarestartedwiththerisingedge ofTBCLK aligned. For perfectlysynchronizedTBCLKs, theprescalerbitsintheTBCTL registerofeach ePWM module must be setidentically.The properprocedureforenablingtheePWM clocksisas follows: 1. EnabletheindividualePWM module clocks(ifdisable)usingthecontrolregistersshown inTable5-1. 2. ConfigureTBCLKSYNC = 0.Thiswillstopthetime-baseclockwithinany enabledePWM module. 3. Configuretheprescalervaluesand desiredePWM modes. 4. ConfigureTBCLKSYNC = 1. 5.1.5 ePWM SynchronizationwithExternalDevices The outputsync fromEPWM1 Module isalsoexportedtoa deviceoutputterminalso thatmultipledevices can be synchronizedtogether.The signalpulseisstretchedby eightVCLK4 cyclesbeforebeingexported on theterminalas theEPWM1SYNCO signal. 5.1.6 ePWM TripZones The ePWMx modules have sixtripzone inputseach.These are active-lowsignals.The applicationcan controltheePWMx module responsetoeach ofthetripzone inputseparately.The timingrequirements fromtheassertionofthetripzone inputstotheactualresponsearespecifiedinSection5.1.8.

5.1.6.1 TripZones TZ1n, TZ2n, TZ3n

These threetripzone inputsare drivenby externalcircuitsand are connectedto device-levelinputs. These signalsare eitherconnected asynchronouslyto the ePWMx tripzone inputs,or double- synchronizedwithVCLK4, or double-synchronizedand thenfilteredwitha 6-cycleVCLK4-based counter beforeconnectingto the ePWMx. By default,the tripzone inputsare asynchronouslyconnectedto the ePWMx modules. Table5-2.Connection toePWMx Modules forDevice-LevelTripZone Inputs TripZone Input Controlfor ControlforDouble-Synchronized ControlforDouble-Synchronizedand Filtered Asynchronous Connection toePWMx Connection toePWMx Connection toePWMx TZ1n PINMMR46[16] = 1 PINMMR46[16] = 0 AND PINMMR46[16] = 0 AND PINMMR46[17] = 0 PINMMR46[17] = 1 AND PINMMR46[18] = 1 TZ2n PINMMR46[24] = 1 PINMMR46[24] = 0 AND PINMMR46[24] = 0 AND PINMMR46[25] = 0 PINMMR46[25] = 1 AND PINMMR46[26] = 1 TZ3n PINMMR47[0] = 1 PINMMR47[0] = 0 AND PINMMR47[1] PINMMR47[0] = 0 AND PINMMR47[1] = 0 AND = 1 PINMMR47[2] = 1

5.1.6.2 TripZone TZ4n

Thistripzone inputisdedicatedtoeQEPx errorindications.There aretwo eQEP modules on thisdevice. Each eQEP module indicatesa phase errorby drivingitsEQEPxERR outputHigh.The followingcontrol registersallowtheapplicationtoconfigurethetripzone input(TZ4n)toeach ePWMx module based on theapplication’s requirements. Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 119 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com Table5-3.TZ4n Connections forePWMx Modules ePWMx ControlforTZ4n = ControlforTZ4n = not(EQEP1ERR) ControlforTZ4n = not(EQEP2ERR) not(EQEP1ERR OR EQEP2ERR) ePWM1 PINMMR41[0] = 1 PINMMR41[0] = 0 AND PINMMR41[1] PINMMR41[0] = 1 AND PINMMR41[1] = 0 AND = 1 PINMMR41[2] = 1 ePWM2 PINMMR41[8] PINMMR41[8] = 0 AND PINMMR41[9] PINMMR41[8] = 1 AND PINMMR41[9] = 0 AND = 1 PINMMR41[10] = 1 ePWM3 PINMMR41[16] PINMMR41[16] = 0 AND PINMMR41[16] = 1 AND PINMMR41[17] = 0 PINMMR41[17] = 1 AND PINMMR41[18] = 1 ePWM4 PINMMR41[24] PINMMR41[24] = 0 AND PINMMR41[24] = 1 AND PINMMR41[25] = 0 PINMMR41[25] = 1 AND PINMMR41[26] = 1 ePWM5 PINMMR42[0] PINMMR42[0] = 0 AND PINMMR42[1] PINMMR42[0] = 1 AND PINMMR42[1] = 0 AND = 1 PINMMR42[2] = 1 ePWM6 PINMMR42[8] PINMMR42[8] = 0 AND PINMMR42[9] PINMMR42[8] = 1 AND PINMMR42[9] = 0 AND = 1 PINMMR42[10] = 1 ePWM7 PINMMR42[16] PINMMR42[16] = 0 AND PINMMR42[16] = 1 AND PINMMR42[17] = 0 PINMMR42[17] = 1 AND PINMMR42[18] = 1

5.1.6.3 TripZone TZ5n

Thistripzone inputisdedicatedtoa clockfailureon thedevice.That is,thistripzone inputisasserted whenever an oscillatorfailureor a PLL slipisdetectedon the device.The applicationcan use thistrip zone inputforeach ePWMx module inordertopreventtheexternalsystemfromgoingoutofcontrolwhen thedeviceclocksarenotwithinexpectedrange(systemrunningatlimpclock). The oscillatorfailureand PLL slipsignalsused forthistripzone inputaretakenfromthestatusflagsinthe systemmodule.These arelevelsignalsaresetuntilclearedby theapplication.

5.1.6.4 TripZone TZ6n

Thistripzone inputtotheePWMx modules isdedicatedtoa debug mode entryoftheCPU. Ifenabled, theusercan forcethePWM outputstoa known statewhen theemulatorstopstheCPU. Thispreventsthe externalsystemfromgoingoutofcontrolwhen theCPU isstopped.

5.1.7 TriggeringofADC StartofConversion Using ePWMx SOCA and SOCB Outputs

A specialscheme isimplementedin orderto selectthe actualsignalused fortriggeringthe startof

5.1.8 Enhanced Translator-PulseWidth Modulator(ePWMx) Timings

Table5-4.ePWMx Timing Requirements PARAMETER TEST CONDITIONS MIN MAX UNIT tw(SYNCIN) Synchronizationinputpulsewidth Asynchronous 2 tc(VCLK4) cycles Synchronous 2 tc(VCLK4) cycles Synchronous,withinput 2 tc(VCLK4) + filterwidth cycles filter Table5-5.ePWMx SwitchingCharacteristics PARAMETER TEST CONDITIONS MIN MAX UNIT tw(PWM) Pulseduration,ePWMx outputhighorlow 33.33 ns tw(SYNCOUT SynchronizationOutputPulseWidth 8 tc(VCLK4) cycles td(PWM)tza Delaytime,tripinputactivetoPWM forcedhigh, no pinload 25 ns OR Delaytime,tripinputactivetoPWM forced low

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Table5-5.ePWMx SwitchingCharacteristics(continued) PARAMETER TEST CONDITIONS MIN MAX UNIT td(TZ- Delaytime,tripinputactivetoPWM Hi-Z 20 ns PWM)HZ Table5-6.ePWMx Trip-ZoneTiming Requirements PARAMETER TEST CONDITIONS MIN MAX UNIT tw(TZ) Pulseduration,TZn inputlow Asynchronous 2 *TBePWMx cycles Synchronous 2 tc(VCLK4) cycles Synchronous,withinput 2 tc(VCLK4)+ filter cycles filter width Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 121 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW IOMUX EPWM1SYNCO ECAP1 ECAP ECAP1INTn ECAP1ENCLK VCLK4,□SYS_nRST ECAP2ENCLK ECAP 2/3/4/5 VCLK4,□SYS_nRST ECAP2INTn ECAP6INTn VBus32 VBus32 VIM VIM VIM ECAP1 ECAP1SYNCI ECAP1SYNCO ECAP2SYNCI ECAP2SYNCO ECAP2 ECAP6ENCLK VCLK4,□SYS_nRST VBus32 ECAP6 RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com

5.2 Enhanced Capture Modules (eCAP)

Figure5-3shows how theeCAP modules areinterconnectedon thismicrocontroller. Figure5-3.eCAP Module Connections

5.2.1 Clock Enable ControlforeCAPx Modules

Each oftheECAPx modules have a clockenable(ECAPxENCLK). These signalsneed tobe generated froma device-levelcontrolregister.When SYS_nRST isactivelow,theclockenablesareignoredand the ECAPx logicisclockedso thatitcan resettoa properstate.When SYS_nRST goes in-activehigh,the stateofclockenableisrespected.

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Table5-7.eCAPx Clock Enable Control ePWM Module Instance ControlRegistertoEnable Clock DefaultValue eCAP1 PINMMR39[0] 1 eCAP2 PINMMR39[8] 1 eCAP3 PINMMR39[16] 1 eCAP4 PINMMR39[24] 1 eCAP5 PINMMR40[0] 1 eCAP6 PINMMR40[8] 1 The defaultvalueofthecontrolregisterstoenabletheclockstotheeCAPx modules is1.Thismeans that theVCLK4 clockconnectionstotheeCAPx modules areenabledby default.The applicationcan choose togateofftheVCLK4 clocktoany eCAPx module individuallyby clearingtherespectivecontrolregister bit.

5.2.2 PWM Output CapabilityofeCAPx

When not used incapturemode, each of the eCAPx modules can be used as a single-channelPWM output.ThisiscalledtheauxiliaryPWM (APWM) mode ofoperationoftheeCAP modules.Refertothe eCAP chapterofthedeviceTechnicalReferenceManual formore information.

5.2.3 InputConnection toeCAPx Modules

The inputconnectionto each of the eCAP modules can be selectedbetween a double-VCLK4- synchronizedinputora double-VCLK4-synchronizedand filteredinput,as shown inTable5-8. Table5-8.Device-LevelInputConnection toeCAPx Modules InputSignal ControlforDouble-SynchronizedConnection to ControlforDouble-Synchronizedand Filtered eCAPx Connection toeCAPx eCAP1 PINMMR43[0] = 1 PINMMR43[0] = 0 AND PINMMR43[1] = 1 eCAP2 PINMMR43[8] = 1 PINMMR43[8] = 0 AND PINMMR43[9] = 1 eCAP3 PINMMR43[16] = 1 PINMMR43[16] = 0 AND PINMMR43[17] = 1 eCAP4 PINMMR43[24] = 1 PINMMR43[24] = 0 AND PINMMR43[25] = 1 eCAP5 PINMMR44[0] = 1 PINMMR44[0] = 0 AND PINMMR44[1] = 1 eCAP6 PINMMR44[8] = 1 PINMMR44[8] = 0 AND PINMMR44[9] = 1

5.2.4 Enhanced Capture Module (eCAP) Timings

Table5-9.eCAPx Timing Requirements PARAMETER TEST CONDITIONS MIN MAX UNIT tw(CAP) Captureinputpulsewidth Synchronous 2 tc(VCLK4) cycles Synchronous,withinput 2 tc(VCLK4) + filterwidth cycles filter Table5-10.eCAPx SwitchingCharacteristics PARAMETER TEST CONDITIONS MIN MAX UNIT tw(APWM) Pulseduration,APWMx outputhighorlow 20 ns Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 123 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW EQEP1A VIM EQEP1INTn EQEP1 Module IO Mux EQEP1ENCLK EQEP1IO EQEP1I VBus32 VCLK4 SYS_nRST EQEP1B EQEP1IOE EQEP1SO EQEP1S EQEP1SOE EQEP1ERR EPWM1/../7 TZ4n EQEP2A VIM EQEP2INTn EQEP2 Module EQEP2ENCLK EQEP2IO EQEP2I VBus32 VCLK4 SYS_nRST EQEP2B EQEP2IOE EQEP2SO EQEP2S EQEP2SOE EQEP2ERR Connection Selection Mux RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com

5.3 Enhanced QuadratureEncoder (eQEP)

Figure5-4shows theeQEP module interconnectionson thedevice. Figure5-4.eQEP Module Interconnections

5.3.1 Clock Enable ControlforeQEPx Modules

Device-levelcontrolregistersareimplementedtogeneratetheEQEPxENCLK signals.When SYS_nRST isactivelow,theclockenablesareignoredand theeQEPx logicisclockedso thatitcan resettoa proper state.When SYS_nRST goes in-activehigh,thestateofclockenableisrespected. Table5-11.eQEPx Clock Enable Control ePWM Module Instance ControlRegistertoEnable Clock DefaultValue eQEP1 PINMMR40[16] 1 eQEP2 PINMMR40[24] 1 The defaultvalueofthecontrolregisterstoenabletheclockstotheeQEPx modules is1.Thismeans that theVCLK4 clockconnectionstotheeQEPx modules areenabledby default.The applicationcan choose togateofftheVCLK4 clocktoany eQEPx module individuallyby clearingtherespectivecontrolregister bit.

5.3.2 Using eQEPx Phase ErrortoTripePWMx Outputs

The eQEP module setsthe EQEPERR signaloutputwhenever a phase errorisdetectedinitsinputs EQEPxA and EQEPxB. ThiserrorsignalfromboththeeQEP modules isinputtotheconnectionselection multiplexor.ThismultiplexorisdefinedinTable5-3.As shown inFigure5-1,theoutputofthisselection multiplexorisinvertedand connectedtotheTZ4n trip-zoneinputofallEPWMx modules.Thisconnection allowstheapplicationtodefinetheresponseofeach ePWMx module on a phase errorindicatedby the eQEP modules.

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5.3.3 InputConnections toeQEPx Modules

The inputconnectionsto each of the eQEP modules can be selectedbetween a double-VCLK4- synchronizedinputora double-VCLK4-synchronizedand filteredinput,as shown inTable5-12. Table5-12.Device-LevelInputConnection toeCAPx Modules InputSignal ControlforDouble-SynchronizedConnection to ControlforDouble-Synchronizedand Filtered eQEPx Connection toeQEPx eQEP1A PINMMR44[16] = 1 PINMMR44[16] = 0 and PINMMR44[17] = 1 eQEP1B PINMMR44[24] = 1 PINMMR44[24] = 0 and PINMMR44[25] = 1 eQEP1I PINMMR45[0] = 1 PINMMR45[0] = 0 and PINMMR45[1] = 1 eQEP1S PINMMR45[8] = 1 PINMMR45[8] = 0 and PINMMR45[9] = 1 eQEP2A PINMMR45[16] = 1 PINMMR45[16] = 0 and PINMMR45[17] = 1 eQEP2B PINMMR45[24] = 1 PINMMR45[24] = 0 and PINMMR45[25] = 1 eQEP2I PINMMR46[0] = 1 PINMMR46[0] = 0 and PINMMR46[1] = 1 eQEP2S PINMMR46[8] = 1 PINMMR46[8] = 0 and PINMMR46[9] = 1

5.3.4 Enhanced QuadratureEncoder Pulse (eQEPx) Timing

Table5-13.eQEPx Timing Requirements PARAMETER TEST CONDITIONS MIN MAX UNIT tw(QEPP) QEP inputperiod Synchronous 2 tc(VCLK4) cycles Synchronous,withinput 2 tc(VCLK4) + filterwidth cycles filter tw(INDEXH) QEP IndexInputHighTime Synchronous 2 tc(VCLK4) cycles Synchronous,withinput 2 tc(VCLK4) + filterwidth cycles filter tw(INDEXL) QEP IndexInputLow Time Synchronous 2 tc(VCLK4) cycles Synchronous,withinput 2 tc(VCLK4) + filterwidth cycles filter tw(STROBH) QEP StrobeInputHighTime Synchronous 2 tc(VCLK4) cycles Synchronous,withinput 2 tc(VCLK4) + filterwidth cycles filter tw(STROBL) QEP StrobeInputLow Time Synchronous 2 tc(VCLK4) cycles Synchronous,withinput 2 tc(VCLK4) + filterwidth cycles filter Table5-14.eQEPx SwitchingCharacteristics PARAMETER MIN MAX UNIT td(CNTR)xin Delaytime,externalclocktocounterincrement 4 tc(VCLK4) cycles td(PCS-OUT)QEP Delaytime,QEP inputedge topositioncompare syncoutput 6 tc(VCLK4) cycles Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 125 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

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5.4 Multi-Buffered12bitAnalog-to-DigitalConverter

The multibufferedA-to-Dconverter(MibADC) has a separatepower bus foritsanalog circuitrythat enhances theA-to-Dperformanceby preventingdigitalswitchingnoiseon thelogiccircuitrywhich could be presenton VSS and VCC fromcouplingintotheA-to-Danalogstage.AllA-to-Dspecificationsaregiven withrespecttoAD REFLO unlessotherwisenoted. Table5-15.MibADC Overview Description Value Resolution 12 bits Monotonic Assured Outputconversioncode 00h to3FFh [00forVAI ≤ AD REFLO ;3FFh forVAI ≥ AD REFHI ]

5.4.1 Features

• 12-bitresolution
• AD REFHI and AD REFLO pins(highand lowreferencevoltages)
• TotalSample/Hold/Converttime:600ns Minimum at30MHz ADCLK
• One memory regionperconversiongroupisavailable(event,group1,group2)
• Allocationofchannelstoconversiongroupsiscompletelyprogrammable
• Supportsflexiblechannelconversionorder
• Memory regionsareservicedeitherby interruptorby DMA
• Programmable interruptthresholdcounterisavailableforeach group
• Programmable magnitudethresholdinterruptforeach groupforany one channel
• Optiontoreadeither8-bit,10-bitor12-bitvaluesfrommemory regions
• Singleorcontinuousconversionmodes
• Embedded self-test
• Embedded calibrationlogic
• Enhanced power-down mode – Optionalfeaturetoautomaticallypower down ADC corewhen no conversionisinprogress
• Externaleventpin(ADxEVT) programmableas general-purposeI/O

5.4.2 Event TriggerOptions

The ADC module supports3 conversiongroups:Event Group, Group1 and Group2. Each of these 3 groups can be configuredto be hardware event-triggered.In thatcase,the applicationcan selectfrom among 8 eventsourcestobe thetriggerfora group'sconversions.

5.4.2.1 MIBADC1 Event TriggerHookup

Table5-16.MIBADC1 Event TriggerHookup TriggerEvent SignalGroup Source Select,G1SRC, PINMMR30[0] = 0 and PINMMR30[1] = 1Event # PINMMR30[0] = 1G2SRC or Controlfor Controlfor(default) Option A Option BEVSRC Option A Option B 000 1 AD1EVT AD1EVT — AD1EVT — PINMMR30[8] = 0 001 2 N2HET1[8] N2HET2[5] PINMMR30[8] = 1 ePWM_B and PINMMR30[9] = 1 010 3 N2HET1[10] N2HET1[27] — N2HET1[27] —

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Table5-16.MIBADC1 Event TriggerHookup (continued) PINMMR30[16] = RTI Compare 0 RTI Compare 0 PINMMR30[16] = 0 and011 4 ePWM_A1Interrupt Interrupt 1 PINMMR30[17] = 100 5 N2HET1[12] N2HET1[17] — N2HET1[17] — PINMMR30[24] = PINMMR30[24] = 0 and101 6 N2HET1[14] N2HET1[19] N2HET2[1]1 PINMMR30[25] = PINMMR31[0] = 0 110 7 GIOB[0] N2HET1[11] PINMMR31[0] = 1 ePWM_A2 and PINMMR31[1] = 1 PINMMR31[8] = 0 111 8 GIOB[1] N2HET2[13] PINMMR31[8] = 1 ePWM_AB and PINMMR31[9] = 1 NOTE IfADEVT, N2HET1 or GIOB isused as a triggersource,the connectionto the MibADC1 module triggerinputismade from the outputsideof the inputbuffer.Thisway, a trigger conditioncan be generatedeitherby configuringthefunctionas outputontothepad (viathe mux control),or by drivingthefunctionfrom an externaltriggersourceas input.Ifthemux controlmodule isused toselectdifferentfunctionalityinsteadoftheADEVT, N2HET1[x] or GIOB[x] signals,then care must be taken to disablethese signalsfrom triggering conversions;thereisno multiplexingon theinputconnections. IfN2HET2[5], ePWM_B, N2HET1[17], N2HET1[19], N2HET2[1], N2HET1[11], ePWM_S2, N2HET2[13] or ePWM_AB isused to triggerthe ADC the connectionto the ADC ismade directlyfrom theN2HETx or ePWM module outputs.As a result,theADC can be triggered withouthavingtoenablethesignalfrombeingoutputon a deviceterminal. NOTE For theRTI compare 0 interruptsource,theconnectionismade directlyfrom theoutputof theRTI module.That is,theinterruptconditioncan be used as a triggersourceeven ifthe actualinterruptisnotsignaledtotheCPU.

5.4.2.2 MIBADC2 Event TriggerHookup

Table5-17.MIBADC2 Event TriggerHookup TriggerEvent SignalGroup Source Select,G1SRC, PINMMR30[0] = 0 and PINMMR30[1] = 1Event # PINMMR30[0] = 1G2SRC or Controlfor Controlfor(default) Option A Option BEVSRC Option A Option B 000 1 AD2EVT AD1EVT — AD1EVT — PINMMR31[16] = PINMMR31[16] = 0 and001 2 N2HET1[8] N2HET2[5] ePWM_B1 PINMMR31[17] = 010 3 N2HET1[10] N2HET1[27] — N2HET1[27] — PINMMR31[24] = RTI Compare 0 RTI Compare 0 PINMMR31[24] = 0 and011 4 ePWM_A1Interrupt Interrupt 1 PINMMR31[25] = 100 5 N2HET1[12] N2HET1[17] — N2HET1[17] — PINMMR32[0] = 0 101 6 N2HET1[14] N2HET1[19] PINMMR32[0] = 1 N2HET2[1] and PINMMR32[1] = 1 Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 127 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com Table5-17.MIBADC2 Event TriggerHookup (continued) PINMMR32[8] = 0 110 7 GIOB[0] N2HET1[11] PINMMR32[8] = 1 ePWM_A2 and PINMMR32[9] = 1 PINMMR32[16] = PINMMR32[16] = 0 and111 8 GIOB[1] N2HET2[13] ePWM_AB1 PINMMR32[17] = NOTE IfAD2EVT, N2HET1 or GIOB isused as a triggersource,theconnectiontotheMibADC2 module triggerinputismade from the outputsideof the inputbuffer.Thisway, a trigger conditioncan be generatedeitherby configuringthefunctionas outputontothepad (viathe mux control),or by drivingthefunctionfrom an externaltriggersourceas input.Ifthemux controlmodule isused toselectdifferentfunctionalityinsteadoftheAD2EVT, N2HET1[x] or GIOB[x] signals,then care must be taken to disablethese signalsfrom triggering conversions;thereisno multiplexingon theinputconnections. IfN2HET2[5], ePWM_B, N2HET1[17], N2HET1[19], N2HET2[1], N2HET1[11], ePWM_S2, N2HET2[13] or ePWM_AB isused to triggerthe ADC the connectionto the ADC ismade directlyfrom theN2HETx or ePWM module outputs.As a result,theADC can be triggered withouthavingtoenablethesignalfrombeingoutputon a deviceterminal. NOTE For theRTI compare 0 interruptsource,theconnectionismade directlyfrom theoutputof theRTI module.That is,theinterruptconditioncan be used as a triggersourceeven ifthe actualinterruptisnotsignaledtotheCPU.

5.4.2.3 ControllingADC1 and ADC2 Event TriggerOptions Using SOC Output from ePWM Modules

As shown inFigure5-5,theePWMxSOCA and ePWMxSOCB outputsfromeach ePWM module areused togenerate4 signals– ePWM_B, ePWM_A1, ePWM_A2 and ePWM_AB, thatareavailabletotriggerthe ADC based on theapplicationrequirement.

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PRODUCT□PREVIEW EPWM2 module EPWM2SOCA EPWM2SOCB EPWM1 module EPWM1SOCA EPWM1SOCB EPWM3 module EPWM3SOCA EPWM3SOCB EPWM4 module EPWM4SOCA EPWM4SOCB EPWM5 module EPWM5SOCA EPWM5SOCB EPWM6 module EPWM6SOCA EPWM6SOCB EPWM7SOCA EPWM7SOCB EPWM7 module ePWM_B ePWM_A1 ePWM_A2 ePWM_AB SOCAEN,□SOCBEN□bits inside□ePWMx□modules Controlled□by□PINMMR RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Figure5-5.ADC TriggerSource Generationfrom ePWMx Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 129 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com Table5-18.ControlBittoSOC Output ControlBit SOC Output PINMMR35[0] SOC1A_SEL PINMMR35[8] SOC2A_SEL PINMMR35[16] SOC3A_SEL PINMMR35[24] SOC4A_SEL PINMMR36[0] SOC5A_SEL PINMMR36[8] SOC6A_SEL PINMMR36[16] SOC7A_SEL The SOCA outputfromeach ePWM module isconnectedtoa "switch"shown inFigure5-5. The logicequationsforthe4 outputsfromthecombinationallogicshown inFigure5-5are: ePWM_ SOC1B orSOC2B orSOC3B orSOC4B orSOC5B orSOC6B orSOC7BB = ePWM_ [SOC1A and not(SOC1A_SEL) ]or[SOC2A and not(SOC2A_SEL) ]or[SOC3A and not(SOC3A_SEL) ]orA1 = [SOC4A and not(SOC4A_SEL) ]or[SOC5A and not(SOC5A_SEL) ]or[SOC6A and not(SOC6A_SEL) ]or [SOC7A and not(SOC7A_SEL) ] ePWM_ [SOC1A and SOC1A_SEL ]or[SOC2A and SOC2A_SEL ]or[SOC3A and SOC3A_SEL ]orA2 = [SOC4A and SOC4A_SEL ]or[SOC5A and SOC5A_SEL ]or[SOC6A and SOC6A_SEL ]or [SOC7A and SOC7A_SEL ] ePWM_ ePWM_B orePWM_A2AB =

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PRODUCT□PREVIEW VS1 On-State Leakage Off-State Leakages VS2 VS24 39*IAIL IAIL IAIL Rext Rext Rext Pin Smux Rmux Pin Smux Rmux Pin Smux Rmux Ssamp Rsamp Csamp Cext IAIL IAIL IAIL IAIL Cmux Cext Cext RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012

5.4.3 ADC Electricaland Timing Specifications

Table5-19.MibADC Recommended OperatingConditions Parameter MIN MAX Unit AD REFHI A-to-Dhigh-voltagereferencesource AD REFLO VCCAD V AD REFLO A-to-Dlow-voltagereferencesource VSSAD AD REFHI V VAI Analoginputvoltage AD REFLO AD REFHI V IAIC Analoginputclamp current -2 2 mA (VAI< VSSAD – 0.3orVAI > VCCAD + 0.3) Table5-20.MibADC ElectricalCharacteristicsOver FullRanges ofRecommended OperatingConditions Parameter Description/Conditions MIN MAX Unit R mux Analoginputmux on-resistanceSee Figure5-6 250 Ω R samp ADC sample switchon- See Figure5-6 250 Ω resistance C mux Inputmux capacitance See Figure5-6 16 pF C samp ADC sample capacitance See Figure5-6 13 pF IAIL Analogoff-stateinputleakage Off-stateinputleakageper VSSAD < VIN < VSSAD + 100mV 300 nA current,forVCCAD = 3.6V ADC inputpin VSSAD + 100mV < VIN < VCCAD 200 nAmaximum -200mV VCCAD -200mV < VIN < VCCAD 500 nA IAIL Analogoff-stateinputleakage Off-stateinputleakageper VIN > VSSAD , 1 µA current,forVCCAD = 5.5V ADC inputpin VIN < VSSAD + 300mV maximum VIN > VSSAD + 300mV, 250 nA VIN < VCCAD -300mV VIN > VCCAD -300mV, 1 µA VIN < VCCAD IADREFHI AD REFHI inputcurrent AD REFHI = VCCAD ,AD REFLO = VSSAD 3 mA ICCAD Staticsupplycurrent Normal operatingmode 15 mA ADC coreinpower down mode 5 µA Figure5-6.MibADC InputEquivalentCircuit Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 131 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com Table5-21.MibADC Timing Specifications Parameter MIN NOM MAX Unit tc(ADCLK) (1) Cycletime,MibADC clock 0.033 µs td(SH)(2) Delaytime,sample and hold 0.2 µs time 12-bitmode td© ) Delaytime,conversiontime 0.4 µs td(SHC)(3) Delaytime,totalsample/hold 0.6 µs and conversiontime 10-bitmode td© ) Delaytime,conversiontime 0.33 µs td(SHC)(3) Delaytime,totalsample/hold 0.53 µs and conversiontime (1) The MibADC clockistheADCLK, generatedby dividingdown theVCLK by a prescalefactordefinedby theADCLOCKCR registerbits 4:0. (2) The sample and holdtimefortheADC conversionsisdefinedby theADCLK frequencyand theAD <GP >SAMP registerforeach conversiongroup.The sample timeneeds tobe determinedby accountingfortheexternalimpedance connectedtotheinputchannelas wellas theADC ’s internalimpedance. (3) Thisistheminimum sample/holdand conversiontimethatcan be achieved.These parametersaredependenton many factors,e.gthe prescalesettings.

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Table5-22.MibADC OperatingCharacteristicsOver FullRanges ofRecommended Operating Conditions(1)(2) Parameter Description/Conditions MIN Type MAX Unit CR Conversionrangeover AD REFHI -AD REFLO 3 5.5 V whichspecified accuracyis maintained ZSET ZeroScaleOffset Differencebetween thefirstidealtransition 10-bit 1 LSB (fromcode 000h to001h)and theactual mode transition 12-bit 2 LSB mode FSET FullScaleOffset Differencebetween therangeofthe 10-bit 2 LSB measured code transitions(fromfirsttolast) mode and therangeoftheidealcode transitions 12-bit 3 LSB mode EDNL Differential Differencebetween theactualstepwidthand 10-bit ± 1.5 LSB nonlinearityerror theidealvalue.(See Figure76) mode 12-bit ± 2 LSB mode EINL Integralnonlinearity Maximum deviationfromthebeststraightline 10-bit ± 2 LSB error throughtheMibADC. MibADC transfer mode characteristics,excludingthequantization 12-bit ± 2 LSBerror. mode ETOT Totalunadjustederror Maximum valueofthedifferencebetween an 10-bit ± 2 LSB (aftercalibration) analogvalueand theidealmidstepvalue. mode 12-bit ± 4 LSB mode (1) 1 LSB = (ADREFHI – AD REFLO )/212 for12-bitmode (2) 1 LSB = (ADREFHI – AD REFLO )/210 for10-bitmode Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 133 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW Differential Linearity Error (–½ LSB)

1 LSB

Error (–½ LSB) 0 ... 110 0 ... 101 0 ... 100 0 ... 011 0 ... 010 0 ... 001 0 ... 000 0 1 2 3 4 5 Digital Output Code Analog Input Value (LSB) NOTE A: 1 LSB = (AD – AD )/2REFHI REFLO RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com

5.4.4 Performance (Accuracy)Specifications

5.4.4.1 MibADC NonlinearityErrors

The differentialnonlinearityerrorshown inFigure5-7(sometimesreferredtoas differentiallinearity)isthe differencebetween an actualstepwidthand theidealvalueof1 LSB. Figure5-7.DifferentialNonlinearity(DNL) Error

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PRODUCT□PREVIEW 0 ... 111 0 ... 101 0 ... 100 0 ... 011 0 ... 010 0 ... 001 0 ... 000 0 1 2 3 4 5 Digital Output Code Analog Input Value (LSB) 0 ... 110 6 7 At Transition (–½ LSB) At Transition 001/010 (–1/4 LSB) Actual Transition Ideal Transition End-Point Lin. Error NOTE A: 1 LSB = (AD – AD )/2REFHI REFLO RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 The integralnonlinearityerrorshown in Figure5-8 (sometimes referredto as linearityerror)is the deviationofthevalueson theactualtransferfunctionfroma straightline. Figure5-8.IntegralNonlinearity(INL)Error Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 135 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW 0 ... 111 0 ... 101 0 ... 100 0 ... 011 0 ... 010 0 ... 001 0 ... 000 0 1 2 3 4 5 Digital Output Code Analog Input Value (LSB) 0 ... 110 6 7 Total Error At Step Total Error At Step 0 ... 101 (–1 1/4 LSB) NOTE A: 1 LSB = (AD – AD )/2REFHI REFLO RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com

5.4.4.2 MibADC TotalError

The absoluteaccuracyor totalerrorofan MibADC as shown inFigure5-9 isthemaximum valueofthe differencebetween an analogvalueand theidealmidstepvalue. Figure5-9.AbsoluteAccuracy (Total)Error

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5.5 General-PurposeInput/Output

The GPIO module on thisdevicesupportstwo ports,GIOA and GIOB. The I/Opinsarebidirectionaland bit-programmable.BothGIOA and GIOB supportexternalinterruptcapability.

5.5.1 Features

The GPIO module has thefollowingfeatures:

• Each IO pincan be configuredas: – Input – Output – Open Drain
• The interruptshave thefollowingcharacteristics: – Programmable interruptdetectioneitheron bothedges oron a singleedge (setinGIOINTDET) – Programmable edge-detectionpolarity,eitherrisingorfallingedge (setinGIOPOL register) – Individualinterruptflags(setinGIOFLG register) – Individualinterruptenables,set and clearedthroughGIOENASET and GIOENACLR registers respectively – Programmable interruptpriority,setthroughGIOLVLSET and GIOLVLCLR registers
• Internalpullup/pulldownallowsunused I/Opinstobe leftunconnected Forinformationon inputand outputtimingssee Section3.8and Section3.9 Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 137 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

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5.6 Enhanced High-End Timer (N2HET)

The N2HET isan advanced intelligenttimerthatprovidessophisticatedtimingfunctionsforreal-time applications.The timerissoftware-controlled,usinga reduced instructionset,witha specializedtimer micromachineand an attachedI/O port.The N2HET can be used forpulsewidthmodulated outputs, captureor compare inputs,or general-purposeI/O..Itisespeciallywellsuitedforapplicationsrequiring multiplesensorinformationand driveactuatorswithcomplexand accuratetimepulses.

5.6.1 Features

The N2HET module has thefollowingfeatures:

• Programmable timerforinputand outputtimingfunctions
• Reduced instructionset(30instructions)fordedicatedtimeand anglefunctions
• 160 words ofinstructionRAM protectedby parity
• User definednumber of25-bitvirtualcountersfortimer,eventcountersand anglecounters
• 7-bithardwarecountersforeach pinallowup to32-bitresolutioninconjunctionwiththe25-bitvirtual counters
• Up to32 pinsusableforinputsignalmeasurements oroutputsignalgeneration
• Programmable suppressionfilterforeach inputpinwithadjustablelimitingfrequency
• Low CPU overheadand interruptload
• EfficientdatatransfertoorfromtheCPU memory withdedicatedHigh-End-TimerTransferUnit(HTU) orDMA
• Diagnosticcapabilitieswithdifferentloopbackmechanisms and pinstatusreadbackfunctionality

5.6.2 N2HET RAM Organization

The timerRAM uses 4 RAM banks,where each bank has two portaccesscapability.Thismeans thatone RAM addressmay be writtenwhileanotheraddressisread.The RAM words are96-bitswide,whichare splitintothree32-bitfields(program,control,and data).

5.6.3 InputTiming Specifications

The N2HET instructionsPCNT and WCAP impose some timingconstraintson theinputsignals. Figure5-10.N2HET InputCapture Timings

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PRODUCT□PREVIEW N2HET1 N2HET2 IOMM□mux□control□signal□x NHET_LOOP_SYNC EXT_LOOP_SYNC EXT_LOOP_SYNC NHET_LOOP_SYNC N2HET1 N2HET2 RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Table5-23.Dynamic CharacteristicsfortheN2HET InputCapture Functionality PARAMETER MIN MAX UNIT

1 Inputsignalperiod,PCNT orWCAP forrisingedge (HRP) (LRP)tc(VCLK2) + 2 225 (HRP) (LRP)tc(VCLK2) -2 ns

2 Inputsignalperiod,PCNT orWCAP forfallingedge (HRP) (LRP)tc(VCLK2) + 2 225 (HRP) (LRP)tc(VCLK2) -2 ns

3 Inputsignalhighphase,PCNT orWCAP forrising 2 (HRP) tc(VCLK2) + 2 225 (HRP) (LRP)tc(VCLK2) -2 ns

4 Inputsignallowphase,PCNT orWCAP forfalling 2 (HRP) tc(VCLK2) + 2 225 (HRP) (LRP)tc(VCLK2) -2 ns

5.6.4 N2HET1-N2HET2 Synchronization

In some applicationsthe N2HET resolutionsmust be synchronized.Some otherapplicationsrequirea singletimebase tobe used forallPWM outputsand inputtimingcaptures. The N2HET providessuch a synchronizationmechanism. The Clk_master/slave(HETGCR.16) configures theN2HET inmasterorslavemode (defaultisslavemode).A N2HET inmastermode providesa signal tosynchronizetheprescalersoftheslaveN2HET. The slaveN2HET synchronizesitsloopresolutionto theloopresolutionsignalsentby themaster.The slavedoes notrequirethissignalafteritreceivesthe firstsynchronizationsignal.However, anytimethe slavereceivesthe re-synchronizationsignalfrom the master,theslavemust synchronizeitselfagain.. Figure5-11.N2HET1 – N2HET2 SynchronizationHookup

5.6.5 N2HET Checking

5.6.5.1 InternalMonitoring

To assurecorrectnessofthehigh-endtimeroperationand outputsignals,thetwo N2HET modules can be used tomonitoreach other’s signalsas shown inFigure5-12.The directionofthemonitoringiscontrolled by theI/Omultiplexingcontrolmodule. Figure5-12.N2HET Monitoring

5.6.5.2 Output Monitoringusing Dual Clock Comparator (DCC)

N2HET1[31] isconnectedas a clocksourceforcounter1 inDCC1. Thisallowstheapplicationtomeasure thefrequencyofthepulse-widthmodulated(PWM) signalon N2HET1[31]. Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 139 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com Similarly,N2HET2[0] isconnectedas a clocksourceforcounter1 inDCC2. Thisallowstheapplicationto measure thefrequencyofthepulse-widthmodulated(PWM) signalon N2HET2[0]. Both N2HET1[31] and N2HET2[0] can be configuredtobe internal-onlychannels.Thatis,theconnection totheDCC module ismade directlyfromtheoutputoftheN2HETx module (fromtheinputoftheoutput buffer). Formore informationon DCC see Section4.7.3.

5.6.6 DisablingN2HET Outputs

Some applicationsrequirethe N2HET outputsto be disabledunder some faultcondition.The N2HET module providesthiscapabilityviathe"PinDisable"inputsignal.Thissignal,when drivenlow,causes the N2HET outputsidentifiedby a programmable register(HETPINDIS) to be tri-stated.Please referto the deviceTerminalReferenceManual formore detailson the"N2HET PinDisable"feature. GIOA[5] is connected to the "PinDisable"inputforN2HET1, and GIOB[2] is connected to the "Pin Disable"inputforN2HET2.

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5.6.7 High-End Timer TransferUnit(HET-TU)

A High End TimerTransferUnit(HET-TU) can performDMA typetransactionstotransferN2HET datato orfrommain memory. A Memory ProtectionUnit(MPU) isbuiltintotheHET-TU.

5.6.7.1 Features

• CPU and DMA independent
• MasterPorttoaccesssystemmemory
• 8 controlpacketssupportingdualbufferconfiguration
• ControlpacketinformationisstoredinRAM protectedby parity
• Eventsynchronization(HET transferrequests)
• Supports32 or64 bittransactions
• Addressingmodes forHET address(8 byteor 16 byte)and system memory address(fixed,32 bitor 64bit)
• One shot,circularand autoswitchbuffertransfermodes
• Requestlostdetection

5.6.7.2 TriggerConnections

Table5-24.HET TU1 Request LineConnection Modules Request Source HET TU1 Request N2HET1 HTUREQ[0] HET TU1 DCP[0] N2HET1 HTUREQ[1] HET TU1 DCP[1] N2HET1 HTUREQ[2] HET TU1 DCP[2] N2HET1 HTUREQ[3] HET TU1 DCP[3] N2HET1 HTUREQ[4] HET TU1 DCP[4] N2HET1 HTUREQ[5] HET TU1 DCP[5] N2HET1 HTUREQ[6] HET TU1 DCP[6] N2HET1 HTUREQ[7] HET TU1 DCP[7] Table5-25.HET TU2 Request LineConnection Modules Request Source HET TU2 Request N2HET2 HTUREQ[0] HET TU2 DCP[0] N2HET2 HTUREQ[1] HET TU2 DCP[1] N2HET2 HTUREQ[2] HET TU2 DCP[2] N2HET2 HTUREQ[3] HET TU2 DCP[3] N2HET2 HTUREQ[4] HET TU2 DCP[4] N2HET2 HTUREQ[5] HET TU2 DCP[5] N2HET2 HTUREQ[6] HET TU2 DCP[6] N2HET2 HTUREQ[7] HET TU2 DCP[7] Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 141 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

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5.7 ControllerArea Network (DCAN)

The DCAN supportsthe CAN 2.0B protocolstandardand uses a serial,multimastercommunication protocolthatefficientlysupportsdistributedreal-timecontrolwithrobustcommunicationratesofup to1 megabit per second (Mbps). The DCAN is idealfor applicationsoperatingin noisy and harsh environments(e.g.,automotiveand industrialfields)that requirereliableserialcommunication or multiplexedwiring.

5.7.1 Features

FeaturesoftheDCAN module include:

• SupportsCAN protocolversion2.0partA,B
• Bitratesup to1 MBit/s
• The CAN kernelcan be clockedby theoscillatorforbaud-rategeneration.
• 64 mailboxeson each DCAN
• Individualidentifiermask foreach message object
• Programmable FIFO mode formessage objects
• Programmable loop-backmodes forself-testoperation
• Automaticbus on afterBus-Offstateby a programmable32-bittimer
• Message RAM protectedby parity
• DirectaccesstoMessage RAM duringtestmode
• CAN Rx /Tx pinsconfigurableas generalpurposeIO pins
• Message RAM AutoInitialization
• DMA support Formore informationon theDCAN see thedeviceTechnicalReferenceManual.

5.7.2 Electricaland Timing Specifications

Table5-26.Dynamic CharacteristicsfortheDCANx TX and RX pins Parameter MIN MAX Unit td(CANnTX) Delaytime,transmitshiftregistertoCANnTX pin(1) 15 ns td(CANnRX) Delaytime,CANnRX pintoreceiveshiftregister 5 ns (1) These valuesdo notincluderise/falltimesoftheoutputbuffer.

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5.8 LocalInterconnectNetwork Interface(LIN)

The SCI/LINmodule can be programmed towork eitheras an SCI oras a LIN.The coreofthemodule is an SCI.The SCI’s hardwarefeaturesareaugmented toachieveLIN compatibility. The SCI module isa universalasynchronousreceiver-transmitterthatimplementsthestandardnonreturn tozeroformat.The SCI can be used tocommunicate,forexample,throughan RS-232 portorovera K- line. The LIN standardisbased on the SCI (UART) serialdata linkformat.The communicationconceptis single-master/multiple-slavewitha message identificationformulti-casttransmissionbetween any network nodes.

5.8.1 LIN Features

The followingarefeaturesoftheLIN module:

• CompatibletoLIN 1.3,2.0and 2.1protocols
• Multi-bufferedreceiveand transmitunitsDMA capabilityforminimalCPU intervention
• Identificationmasks formessage filtering
• AutomaticMasterHeader Generation – Programmable Synch BreakField – Synch Field – IdentifierField
• SlaveAutomaticSynchronization – Synch breakdetection – Optionalbaudrateupdate – SynchronizationValidation
• 231 programmabletransmissionrateswith7 fractionalbits
• Errordetection
• 2 Interruptlineswithpriorityencoding Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 143 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

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5.9 SerialCommunication Interface(SCI)

5.9.1 Features

• Standarduniversalasynchronousreceiver-transmitter(UART) communication
• Supportsfull-orhalf-duplexoperation
• Standardnonreturntozero(NRZ) format
• Double-bufferedreceiveand transmitfunctions
• Configurableframeformatof3 to13 bitspercharacterbased on thefollowing: – Data word lengthprogrammablefromone toeightbits – Additionaladdressbitinaddress-bitmode – Parityprogrammableforzeroorone paritybit,odd oreven parity – Stopprogrammableforone ortwo stopbits
• Asynchronousorisosynchronouscommunicationmodes
• Two multiprocessorcommunicationformatsallowcommunicationbetween more thantwo devices.
• Sleepmode isavailabletofreeCPU resourcesduringmultiprocessorcommunication.
• The 24-bitprogrammablebaud ratesupports224 differentbaud ratesprovidehighaccuracybaud rate selection.
• Fourerrorflagsand FivestatusflagsprovidedetailedinformationregardingSCI events.
• Capabilitytouse DMA fortransmitand receivedata.

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5.10 Inter-IntegratedCircuit(I2C)

The inter-integratedcircuit(I2C)module isa multi-mastercommunicationmodule providingan interface between theRM4x microcontrollerand devicescompliantwithPhilipsSemiconductorI2C-busspecification version2.1and connectedby an I2C-bus.Thismodule willsupportany slaveor masterI2C compatible device.

5.10.1 Features

The I2C has thefollowingfeatures:

• CompliancetothePhilipsI2C bus specification,v2.1(The I2C Specification,Philipsdocument number 9398 393 40011) – Bit/Byteformattransfer – 7-bitand 10-bitdeviceaddressingmodes – Generalcall – START byte – Multi-mastertransmitter/slavereceivermode – Multi-masterreceiver/slavetransmittermode – Combined mastertransmit/receiveand receive/transmitmode – Transferratesof10 kbps up to400 kbps (Phillipsfast-moderate)
• Freedataformat
• Two DMA events(transmitand receive)
• DMA eventenable/disablecapability
• Seven interruptsthatcan be used by theCPU
• Module enable/disablecapability
• The SDA and SCL areoptionallyconfigurableas generalpurposeI/O
• Slew ratecontroloftheoutputs
• Open draincontroloftheoutputs
• Programmable pullup/pulldowncapabilityon theinputs
• SupportsIgnoreNACK mode NOTE ThisI2C module does notsupport:
• High-speed(HS)mode
• C-bus compatibilitymode
• The combined formatin10-bitaddressmode (theI2C sends theslaveaddresssecond byteeverytimeitsends theslaveaddressfirstbyte) Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 145 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW SDA SCL tw(SDAH) tw(SCLL) tw(SCLH) tw(SP) th(SCLL-SDAL) th(SDA-SCLL) th(SCLL-SDAL) tsu(SCLH-SDAL) tf(SCL)tc(SCL) tr(SCL) tsu(SCLH-SDAH) Stop Start Repeated Start Stop tsu(SDA-SCLH) RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com

5.10.2 I2C I/OTiming Specifications

Table5-27.I2C Signals(SDA and SCL) SwitchingCharacteristics(1) Parameter Standard Mode FastMode Unit MIN MAX MIN MAX tc(I2CCLK) Cycletime,InternalModule clockforI2C, 75.2 149 75.2 149 ns prescaledfromVCLK tc(SCL) Cycletime,SCL 10 2.5 ms tsu(SCLH-SDAL) Setuptime,SCL highbeforeSDA low(fora 4.7 0.6 ms repeatedSTART condition) th(SCLL-SDAL) Holdtime,SCL lowafterSDA low(fora repeated 4 0.6 ms START condition) tw(SCLL) Pulseduration,SCL low 4.7 1.3 ms tw(SCLH) Pulseduration,SCL high 4 0.6 ms tsu(SDA-SCLH) Setuptime,SDA validbeforeSCL high 250 100 ns th(SDA-SCLL) Holdtime,SDA validafterSCL low(forI2C bus 0 3.45(2) 0 0.9 ms devices) tw(SDAH) Pulseduration,SDA highbetween STOP and 4.7 1.3 ms START conditions tsu(SCLH-SDAH) Setuptime,SCL highbeforeSDA high(forSTOP 4.0 0.6 ms condition) tw(SP) Pulseduration,spike(mustbe suppressed) 0 50 ns C b (3) Capacitiveloadforeach bus line 400 400 pF (1) The I2C pinsSDA and SCL do notfeaturefail-safeI/Obuffers.These pinscouldpotentiallydraw currentwhen thedeviceispowered down. (2) The maximum th(SDA-SCLL) forI2C bus deviceshas onlytobe met ifthedevicedoes notstretchthelowperiod(tw(SCLL))oftheSCL signal. (3) C b = The totalcapacitanceofone bus lineinpF. Figure5-13.I2C Timings

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• A devicemust internallyprovidea hold time of at least300 ns forthe SDA signal (referredto the VIHmin of the SCL signal)to bridgethe undefinedregionof the falling edge ofSCL.
• The maximum th(SDA-SCLL) has onlyto be met ifthe devicedoes not stretchthe LOW period(tw(SCLL))oftheSCL signal.
• A Fast-mode I2C-busdevicecan be used ina Standard-modeI2C-bussystem,butthe requirementtsu(SDA-SCLH) ≥ 250 ns must thenbe met.Thiswillautomaticallybe thecase if the devicedoes not stretchthe LOW periodof the SCL signal.Ifsuch a devicedoes stretchtheLOW periodoftheSCL signal,itmust outputthenextdatabittotheSDA line trmax + tsu(SDA-SCLH).
• C b = totalcapacitanceofone bus lineinpF.Ifmixed withfast-modedevices,fasterfall- timesareallowed. Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 147 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

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5.11 Multi-Buffered/Standard SerialPeripheralInterface

The MibSPI is a high-speedsynchronous serialinput/outputportthatallowsa serialbitstream of programmed length(2to16 bits)tobe shiftedinand outofthedeviceata programmed bit-transferrate. TypicalapplicationsfortheSPI includeinterfacingtoexternalperipherals,such as I/Os,memories,display drivers,and analog-to-digitalconverters.

5.11.1 Features

BothStandardand MibSPI modules have thefollowingfeatures:

• 16-bitshiftregister
• Receivebufferregister
• 8-bitbaud clockgenerator
• SPICLK can be internally-generated(mastermode) or receivedfrom an externalclocksource(slave mode)
• Each word transferredcan have a uniqueformat
• SPI I/Osnotused inthecommunicationcan be used as digitalinput/outputsignals Table5-28.MibSPI/SPIConfigurations MibSPIx/SPIx I/Os MibSPI1 MIBSPI1SIMO[1:0],MIBSPI1SOMI[1:0],MIBSPI1CLK, MIBSPI1nCS[5:0],MIBSPI1nENA MibSPI3 MIBSPI3SIMO, MIBSPI3SOMI, MIBSPI3CLK, MIBSPI3nCS[5:0],MIBSPI3nENA MibSPI5 MIBSPI5SIMO[3:0],MIBSPI5SOMI[3:0],MIBSPI5CLK, MIBSPI5nCS[3:0],MIBSPI5nENA SPI2 SPI2SIMO, ZSPI2SOMI, SPI2CLK, SPI2nCS[1:0],SPI2nENA SPI4 SPI4SIMO, SPI4SOMI, SPI4CLK, SPI4nCS[0],SPI4nENA

5.11.2 MibSPI Transmitand Receive RAM Organization

The MultibufferRAM iscomprisedof128 buffers.Each entryintheMultibufferRAM consistsof4 parts:a 16-bittransmitfield,a 16-bitreceivefield,a 16-bitcontrolfieldand a 16-bitstatusfield.The Multibuffer RAM can be partitionedintomultipletransfergroup withvariablenumber ofbufferseach.Each MibSPIx module supports8 transfergroups.

5.11.3 MibSPI TransmitTriggerEvents

Each ofthetransfergroupscan be configuredindividually.For each ofthetransfergroupsa triggerevent and a triggersourcecan be chosen.A triggereventcan be forexample a risingedge ora permanentlow levelat a selectabletriggersource.For example,up to 15 triggersourcesare availablewhich can be utilizedby each transfergroup.These triggeroptionsare listedinTable 5-29 and Section5.11.3.2for MibSPI1 and MibSPi3respectively.

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 5.11.3.1MIBSPI1 Event TriggerHookup Table5-29.MIBSPI1 Event TriggerHookup Event # TGxCTRL TRIGSRC[3:0] Trigger Disabled 0000 No triggersource EVENT0 0001 GIOA[0] EVENT1 0010 GIOA[1] EVENT2 0011 GIOA[2] EVENT3 0100 GIOA[3] EVENT4 0101 GIOA[4] EVENT5 0110 GIOA[5] EVENT6 0111 GIOA[6] EVENT7 1000 GIOA[7] EVENT8 1001 N2HET1[8] EVENT9 1010 N2HET1[10] EVENT10 1011 N2HET1[12] EVENT11 1100 N2HET1[14] EVENT12 1101 N2HET1[16] EVENT13 1110 N2HET1[18] EVENT14 1111 InternTickcounter NOTE For N2HET1 triggersources,the connectionto the MibSPI1 module triggerinputismade from the inputsideof the outputbuffer(atthe N2HET1 module boundary).This way, a triggerconditioncan be generatedeven iftheN2HET1 signalisnotselectedtobe outputon thepad. NOTE For GIOx triggersources,theconnectiontotheMibSPI1 module triggerinputismade from theoutputsideoftheinputbuffer.Thisway, a triggerconditioncan be generatedeitherby selectingtheGIOx pinas an outputpinand selectingthepintobe a GIOx pin,orby driving the GIOx pinfrom an externaltriggersource.Ifthe mux controlmodule isused to select differentfunctionalityinsteadof the GIOx signal,then care must be takento disableGIOx fromtriggeringMibSPI1 transfers;thereisno multiplexingon theinputconnections. 5.11.3.2MIBSPI3 Event TriggerHookup Table5-30.MIBSPI3 Event TriggerHookup Event # TGxCTRL TRIGSRC[3:0] Trigger Disabled 0000 No triggersource EVENT0 0001 GIOA[0] EVENT1 0010 GIOA[1] EVENT2 0011 GIOA[2] EVENT3 0100 GIOA[3] EVENT4 0101 GIOA[4] EVENT5 0110 GIOA[5] EVENT6 0111 GIOA[6] EVENT7 1000 GIOA[7] EVENT8 1001 N2HET1[8] Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 149 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com Table5-30.MIBSPI3 Event TriggerHookup (continued) Event # TGxCTRL TRIGSRC[3:0] Trigger EVENT9 1010 N2HET1[10] EVENT10 1011 N2HET1[12] EVENT11 1100 N2HET1[14] EVENT12 1101 N2HET1[16] EVENT13 1110 N2HET1[18] EVENT14 1111 InternTickcounter NOTE For N2HET1 triggersources,the connectionto the MibSPI3 module triggerinputismade from the inputsideof the outputbuffer(atthe N2HET1 module boundary).This way, a triggerconditioncan be generatedeven iftheN2HET1 signalisnotselectedtobe outputon thepad. NOTE For GIOx triggersources,theconnectiontotheMibSPI3 module triggerinputismade from theoutputsideoftheinputbuffer.Thisway, a triggerconditioncan be generatedeitherby selectingtheGIOx pinas an outputpinand selectingthepintobe a GIOx pin,orby driving the GIOx pinfrom an externaltriggersource.Ifthe mux controlmodule isused to select differentfunctionalityinsteadof the GIOx signal,then care must be takento disableGIOx fromtriggeringMibSPI3 transfers;thereisno multiplexingon theinputconnections. 5.11.3.3MIBSPI5 Event TriggerHookup Table5-31.MIBSPI5 Event TriggerHookup Event# TGxCTRL TRIGSRC[3:0] Trigger Disabled 0000 No triggersource EVENT0 0001 GIOA[0] EVENT1 0010 GIOA[1] EVENT2 0011 GIOA[2] EVENT3 0100 GIOA[3] EVENT4 0101 GIOA[4] EVENT5 0110 GIOA[5] EVENT6 0111 GIOA[6] EVENT7 1000 GIOA[7] EVENT8 1001 N2HET1[8] EVENT9 1010 N2HET1[10] EVENT10 1011 N2HET1[12] EVENT11 1100 N2HET1[14] EVENT12 1101 N2HET1[16] EVENT13 1110 N2HET1[18] EVENT14 1111 InternTickcounter NOTE For N2HET1 triggersources,the connectionto the MibSPI5 module triggerinputismade from the inputsideof the outputbuffer(atthe N2HET1 module boundary).This way, a triggerconditioncan be generatedeven iftheN2HET1 signalisnotselectedtobe outputon thepad.

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PRODUCT□PREVIEW RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 NOTE For GIOx triggersources,theconnectiontotheMibSPI5 module triggerinputismade from theoutputsideoftheinputbuffer.Thisway, a triggerconditioncan be generatedeitherby selectingtheGIOx pinas an outputpinand selectingthepintobe a GIOx pin,orby driving the GIOx pinfrom an externaltriggersource.Ifthe mux controlmodule isused to select differentfunctionalityinsteadof the GIOx signal,then care must be takento disableGIOx fromtriggeringMibSPI5 transfers;thereisno multiplexingon theinputconnections. Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 151 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

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5.11.4 MibSPI/SPIMaster Mode I/OTiming Specifications

Table5-32.SPI Master Mode ExternalTiming Parameters (CLOCK PHASE = 0,SPICLK = output,SPISIMO = output,and SPISOMI = input)(1)(2)(3) NO. Parameter MIN MAX Unit 1 tc(SPC)M Cycletime,SPICLK (4) 4040 256tc(VCLK) ns 2(5) tw(SPCH)M Pulseduration,SPICLK high(clock 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3 ns polarity= 0) tw(SPCL)M Pulseduration,SPICLK low(clock 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3 polarity= 1) 3(5) tw(SPCL)M Pulseduration,SPICLK low(clock 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3 ns polarity= 0) tw(SPCH)M Pulseduration,SPICLK high(clock 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3 polarity= 1) 4(5) td(SPCH-SIMO)M Delaytime,SPISIMO validbefore 0.5tc(SPC)M – 5 ns SPICLK low(clockpolarity= 0) td(SPCL-SIMO)M Delaytime,SPISIMO validbefore 0.5tc(SPC)M – 5 SPICLK high(clockpolarity= 1) 5(5) tv(SPCL-SIMO)M Validtime,SPISIMO datavalidafter 0.5tc(SPC)M – tf(SPC)– 3 ns SPICLK low(clockpolarity= 0) tv(SPCH-SIMO)M Validtime,SPISIMO datavalidafter 0.5tc(SPC)M – tr(SPC)– 3 SPICLK high(clockpolarity= 1) 6(5) tsu(SOMI-SPCL)M Setuptime,SPISOMI beforeSPICLK 0.5tf(SPC)+ 2 ns low(clockpolarity= 0) tsu(SOMI-SPCH)M Setuptime,SPISOMI beforeSPICLK 0.5tf(SPC)+ 2 high(clockpolarity= 1) 7(5) th(SPCL-SOMI)M Holdtime,SPISOMI datavalidafter 5 ns SPICLK low(clockpolarity= 0) th(SPCH-SOMI)M Holdtime,SPISOMI datavalidafter 5 SPICLK high(clockpolarity= 1) 8(6) tC2TDELAY SetuptimeCS active CSHOLD = 0 C2TDELAY*t c(VCLK) + 2*tc(VCLK) (C2TDELAY+2) *tc(VCLK) - ns untilSPICLK high -tf(SPICS)+ tr(SPC)– 15 tf(SPICS)+ tr(SPC)+ 3 (clockpolarity= 0) CSHOLD = 1 C2TDELAY*t c(VCLK) + 3*tc(VCLK) (C2TDELAY+3) *tc(VCLK) - -tf(SPICS)+ tr(SPC)– 15 tf(SPICS)+ tr(SPC)+ 3 SetuptimeCS active CSHOLD = 0 C2TDELAY*t c(VCLK) + 2*tc(VCLK) (C2TDELAY+2) *tc(VCLK) - ns untilSPICLK low -tf(SPICS)+ tf(SPC)– 15 tf(SPICS)+ tf(SPC)+ 3 (clockpolarity= 1) CSHOLD = 1 C2TDELAY*t c(VCLK) + 3*tc(VCLK) (C2TDELAY+3) *tc(VCLK) - -tf(SPICS)+ tf(SPC)– 15 tf(SPICS)+ tf(SPC)+ 3 9(6) tT2CDELAY HoldtimeSPICLK lowCS untilinactive 0.5*tc(SPC)M + 0.5*tc(SPC)M + ns (clockpolarity= 0) T2CDELAY*t c(VCLK) + tc(VCLK) - T2CDELAY*t c(VCLK) + tc(VCLK) - tf(SPC)+ tr(SPICS)-5 tf(SPC)+ tr(SPICS)+ 8 HoldtimeSPICLK highuntilCS 0.5*tc(SPC)M + 0.5*tc(SPC)M + ns inactive(clockpolarity= 1) T2CDELAY*t c(VCLK) + tc(VCLK) - T2CDELAY*t c(VCLK) + tc(VCLK) - tr(SPC)+ tr(SPICS)-5 tr(SPC)+ tr(SPICS)+ 8 10 tSPIENA SPIENAn Sample point (C2TDELAY+1) *tc(VCLK) - (C2TDELAY+1)*tc(VCLK) ns tf(SPICS)– 25 11 tSPIENAW SPIENAn Sample pointfromwriteto (C2TDELAY+2)*tc(VCLK) ns buffer (1) The MASTER bit(SPIGCR1.0)issetand theCLOCK PHASE bit(SPIFMTx.16)isset. (2) tc(VCLK) = interfaceclockcycletime= 1 /f(VCLK) (3) Forriseand falltimings,see Table3-4. (4) When theSPI isinMastermode, thefollowingmust be true: ForPS valuesfrom1 to255:tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 40ns,where PS istheprescalevaluesetintheSPIFMTx.[15:8]registerbits. ForPS valuesof0:tc(SPC)M = 2tc(VCLK) ≥ 40ns. The externalloadon theSPICLK pinmust be lessthan60pF. (5) The activeedge oftheSPICLK signalreferencediscontrolledby theCLOCK POLARITY bit(SPIFMTx.17). (6) C2TDELAY and T2CDELAY isprogrammed intheSPIDELAY register

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PRODUCT□PREVIEW SPICLK (clock polarity=0) SPISIMO SPICSn Master Out Data Is Valid SPICLK (clock polarity=1) SPIENAn Write to buffer SPISOMI SPISIMO SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) Master In Data Must Be Valid Master Out Data Is Valid RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Figure5-14.SPI Master Mode ExternalTiming (CLOCK PHASE = 0) Figure5-15.SPI Master Mode Chip SelectTiming (CLOCK PHASE = 0) Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 153 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com Table5-33.SPI Master Mode ExternalTiming Parameters (CLOCK PHASE = 1,SPICLK = output,SPISIMO = output,and SPISOMI = input)(1)(2)(3) NO. Parameter MIN MAX Unit 1 tc(SPC)M Cycletime,SPICLK (4) 40 256tc(VCLK) ns 2(5) tw(SPCH)M Pulseduration,SPICLK high(clock 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3 ns polarity= 0) tw(SPCL)M Pulseduration,SPICLK low(clock 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3 polarity= 1) 3(5) tw(SPCL)M Pulseduration,SPICLK low(clock 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3 ns polarity= 0) tw(SPCH)M Pulseduration,SPICLK high(clock 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3 polarity= 1) 4(5) tv(SIMO-SPCH)M Validtime,SPICLK highafter 0.5tc(SPC)M – 5 ns SPISIMO datavalid(clockpolarity= tv(SIMO-SPCL)M Validtime,SPICLK lowafter 0.5tc(SPC)M – 5 SPISIMO datavalid(clockpolarity= 5(5) tv(SPCH-SIMO)M Validtime,SPISIMO datavalidafter 0.5tc(SPC)M – tr(SPC)– 3 ns SPICLK high(clockpolarity= 0) tv(SPCL-SIMO)M Validtime,SPISIMO datavalidafter 0.5tc(SPC)M – tf(SPC)– 3 SPICLK low(clockpolarity= 1) 6(5) tsu(SOMI-SPCH)M Setuptime,SPISOMI before tr(SPC) ns SPICLK high(clockpolarity= 0) tsu(SOMI-SPCL)M Setuptime,SPISOMI before tf(SPC) SPICLK low(clockpolarity= 1) 7(5) tv(SPCH-SOMI)M Validtime,SPISOMI datavalidafter 5 ns SPICLK high(clockpolarity= 0) tv(SPCL-SOMI)M Validtime,SPISOMI datavalidafter 5 SPICLK low(clockpolarity= 1) 8(6) tC2TDELAY SetuptimeCS CSHOLD = 0 0.5*tc(SPC)M + 0.5*tc(SPC)M + ns activeuntilSPICLK (C2TDELAY+2) *tc(VCLK) - (C2TDELAY+2) *tc(VCLK) - high(clockpolarity= tf(SPICS)+ tr(SPC)– 15 tf(SPICS)+ tr(SPC)+ 3 0) CSHOLD = 1 0.5*tc(SPC)M + 0.5*tc(SPC)M + (C2TDELAY+3) *tc(VCLK) - (C2TDELAY+3) *tc(VCLK) - tf(SPICS)+ tr(SPC)– 15 tf(SPICS)+ tr(SPC)+ 3 SetuptimeCS CSHOLD = 0 0.5*tc(SPC)M + 0.5*tc(SPC)M + ns activeuntilSPICLK (C2TDELAY+2) *tc(VCLK) - (C2TDELAY+2) *tc(VCLK) - low(clockpolarity= tf(SPICS)+ tf(SPC)– 15 tf(SPICS)+ tf(SPC)+ 3 1) CSHOLD = 1 0.5*tc(SPC)M + 0.5*tc(SPC)M + (C2TDELAY+3) *tc(VCLK) - (C2TDELAY+3) *tc(VCLK) - tf(SPICS)+ tf(SPC)– 15 tf(SPICS)+ tf(SPC)+ 3 9(6) tT2CDELAY HoldtimeSPICLK lowCS until T2CDELAY*t c(VCLK) + T2CDELAY*t c(VCLK) + ns inactive(clockpolarity= 0) tc(VCLK) -tf(SPC)+ tr(SPICS)- tc(VCLK) -tf(SPC)+ tr(SPICS)+ 4 8 HoldtimeSPICLK highuntilCS T2CDELAY*t c(VCLK) + T2CDELAY*t c(VCLK) + ns inactive(clockpolarity= 1) tc(VCLK) -tr(SPC)+ tr(SPICS)- tc(VCLK) -tr(SPC)+ tr(SPICS)+ 4 8 10 tSPIENA SPIENAn Sample Point (C2TDELAY+1)* tc(VCLK) - (C2TDELAY+1)*tc(VCLK) ns tf(SPICS)– 25 11 tSPIENAW SPIENAn Sample pointfromwriteto (C2TDELAY+2)*tc(VCLK) ns buffer (1) The MASTER bit(SPIGCR1.0)issetand theCLOCK PHASE bit(SPIFMTx.16)isset. (2) tc(VCLK) = interfaceclockcycletime= 1 /f(VCLK) (3) Forriseand falltimings,see Table3-4. (4) When theSPI isinMastermode, thefollowingmust be true: ForPS valuesfrom1 to255:tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 40ns,where PS istheprescalevaluesetintheSPIFMTx.[15:8]registerbits. ForPS valuesof0:tc(SPC)M = 2tc(VCLK) ≥ 40ns. The externalloadon theSPICLK pinmust be lessthan60pF. (5) The activeedge oftheSPICLK signalreferencediscontrolledby theCLOCK POLARITY bit(SPIFMTx.17). (6) C2TDELAY and T2CDELAY isprogrammed intheSPIDELAY register

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PRODUCT□PREVIEW SPICLK (clock polarity=0) SPISIMO SPICSn Master Out Data Is Valid SPICLK (clock polarity=1) SPIENAn Write to buffer SPISOMI SPISIMO SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) Data Valid Master In Data Must Be Valid Master Out Data Is Valid RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Figure5-16.SPI Master Mode ExternalTiming (CLOCK PHASE = 1) Figure5-17.SPI Master Mode Chip SelectTiming (CLOCK PHASE = 1) Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 155 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com

5.11.5 SPI SlaveMode I/OTimings

Table5-34.SPI SlaveMode ExternalTiming Parameters (CLOCK PHASE = 0,SPICLK = input,SPISIMO = input,and SPISOMI = output)(1)(2)(3)(4) NO. Parameter MIN MAX Unit 1 tc(SPC)S Cycletime,SPICLK (5) 40 256tc(VCLK) ns 2(6) tw(SPCH)S Pulseduration,SPICLK high(clockpolarity= 0) 14 ns tw(SPCL)S Pulseduration,SPICLK low(clockpolarity= 1) 14 3(6) tw(SPCL)S Pulseduration,SPICLK low(clockpolarity= 0) 14 ns tw(SPCH)S Pulseduration,SPICLK high(clockpolarity= 1) 14 4(6) td(SPCH-SOMI)S Delaytime,SPISOMI validafterSPICLK high(clock trf(SOMI)+ 13 ns polarity= 0) td(SPCL-SOMI)S Delaytime,SPISOMI validafterSPICLK low(clockpolarity trf(SOMI)+ 13 = 1) 5(6) th(SPCH-SOMI)S Holdtime,SPISOMI datavalidafterSPICLK high(clock 2 ns polarity=0) th(SPCL-SOMI)S Holdtime,SPISOMI datavalidafterSPICLK low(clock 2 polarity=1) 6(6) tsu(SIMO-SPCL)S Setuptime,SPISIMO beforeSPICLK low(clockpolarity= 2 ns tsu(SIMO-SPCH)S Setuptime,SPISIMO beforeSPICLK high(clockpolarity= 2 7(6) th(SPCL-SIMO)S Holdtime,SPISIMO datavalidafterSPICLK low(clock 2 ns polarity= 0) th(SPCH-SIMO)S Holdtime,SPISIMO datavalidafterS PICLK high(clock 2 polarity= 1) 8 td(SPCL-SENAH)S Delaytime,SPIENAn highafterlastSPICLK low(clock 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn) ns polarity= 0) td(SPCH-SENAH)S Delaytime,SPIENAn highafterlastSPICLK high(clock 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn) polarity= 1) 9 td(SCSL-SENAL)S Delaytime,SPIENAn lowafterSPICSn low(ifnew data tf(ENAn) tc(VCLK)+tf(ENAn)+1 ns has been writtentotheSPI buffer) 4 (1) The MASTER bit(SPIGCR1.0)issetand theCLOCK PHASE bit(SPIFMTx.16)isset. (2) IftheSPI isinslavemode, thefollowingmust be true:tc(SPC)S ≥ (PS + 1)tc(VCLK),where PS = prescalevaluesetinSPIFMTx.[15:8]. (3) Forriseand falltimings,see Table3-4. (4) tc(VCLK) = interfaceclockcycletime= 1 /f(VCLK) (5) When theSPI isinSlavemode, thefollowingmust be true: ForPS valuesfrom1 to255:tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40ns,where PS istheprescalevaluesetintheSPIFMTx.[15:8]registerbits. ForPS valuesof0:tc(SPC)S = 2tc(VCLK) ≥ 40ns. (6) The activeedge oftheSPICLK signalreferencediscontrolledby theCLOCK POLARITY bit(SPIFMTx.17).

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PRODUCT□PREVIEW SPICLK (clock polarity=0) SPICSn SPICLK (clock polarity=1) SPIENAn SPISOMI SPICLK (clock□polarity□=□1) SPICLK (clock□polarity□=□0) SPISIMO□Data Must□Be□Valid SPISOMI□Data□Is□Valid 666 SPISIMO RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Figure5-18.SPI SlaveMode ExternalTiming (CLOCK PHASE = 0) Figure5-19.SPI SlaveMode Enable Timing (CLOCK PHASE = 0) Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 157 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com Table5-35.SPI SlaveMode ExternalTiming Parameters (CLOCK PHASE = 1,SPICLK = input,SPISIMO = input,and SPISOMI = output)(1)(2)(3)(4) NO. Parameter MIN MAX Unit 1 tc(SPC)S Cycletime,SPICLK (5) 40 256tc(VCLK) ns 2(6) tw(SPCH)S Pulseduration,SPICLK high(clockpolarity= 0) 14 ns tw(SPCL)S Pulseduration,SPICLK low(clockpolarity= 1) 14 3(6) tw(SPCL)S Pulseduration,SPICLK low(clockpolarity= 0) 14 ns tw(SPCH)S Pulseduration,SPICLK high(clockpolarity= 1) 14 4(6) td(SOMI-SPCL)S Delaytime,SPISOMI datavalidafterSPICLK low trf(SOMI)+ 13 ns (clockpolarity= 0) td(SOMI-SPCH)S Delaytime,SPISOMI datavalidafterSPICLK high trf(SOMI)+ 13 (clockpolarity= 1) 5(6) th(SPCL-SOMI)S Holdtime,SPISOMI datavalidafterSPICLK high 2 ns (clockpolarity=0) th(SPCH-SOMI)S Holdtime,SPISOMI datavalidafterSPICLK low(clock 2 polarity=1) 6(6) tsu(SIMO-SPCH)S Setuptime,SPISIMO beforeSPICLK high(clock 2 ns polarity= 0) tsu(SIMO-SPCL)S Setuptime,SPISIMO beforeSPICLK low(clockpolarity 2 = 1) 7(6) tv(SPCH-SIMO)S Hightime,SPISIMO datavalidafterSPICLK high 2 ns (clockpolarity= 0) tv(SPCL-SIMO)S Hightime,SPISIMO datavalidafterSPICLK low(clock 2 polarity= 1) 8 td(SPCH-SENAH)S Delaytime,SPIENAn highafterlastSPICLK high 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn) ns (clockpolarity= 0) td(SPCL-SENAH)S Delaytime,SPIENAn highafterlastSPICLK low(clock 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn) polarity= 1) 9 td(SCSL-SENAL)S Delaytime,SPIENAn lowafterSPICSn low(ifnew data tf(ENAn) tc(VCLK)+tf(ENAn)+14 ns has been writtentotheSPI buffer) 10 td(SCSL-SOMI)S Delaytime,SOMI validafterSPICSn low(ifnew data tc(VCLK) 2tc(VCLK)+trf(SOMI)+8 ns has been writtentotheSPI buffer) (1) The MASTER bit(SPIGCR1.0)issetand theCLOCK PHASE bit(SPIFMTx.16)isset. (2) IftheSPI isinslavemode, thefollowingmust be true:tc(SPC)S≤ (PS + 1)tc(VCLK),where PS = prescalevaluesetinSPIFMTx.[15:8]. (3) Forriseand falltimings,see Table3-4. (4) tc(VCLK) = interfaceclockcycletime= 1 /f(VCLK) (5) When theSPI isinSlavemode, thefollowingmust be true: ForPS valuesfrom1 to255:tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40ns,where PS istheprescalevaluesetintheSPIFMTx.[15:8]registerbits. ForPS valuesof0:tc(SPC)S = 2tc(VCLK) ≥ 40ns. (6) The activeedge oftheSPICLK signalreferencediscontrolledby theCLOCK POLARITY bit(SPIFMTx.17).

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PRODUCT□PREVIEW SPISOMI Slave Out Data Is Valid SPICLK (clock polarity=0) SPICSn SPICLK (clock polarity=1) SPIENAn SPISIMO SPISOMI SPISIMO Data Must Be Valid SPISOMI Data Is Valid 666 SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Figure5-20.SPI SlaveMode ExternalTiming (CLOCK PHASE = 1) Figure5-21.SPI SlaveMode Enable Timing (CLOCK PHASE = 1) Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 159 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW 1 2 MII_MRCLK MII_MRXD MII_MRXDV MII_MRXER V ALID RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com

5.12 EthernetMedia Access Controller

The EthernetMedia Access Controller(EMAC) providesan efficientinterfacebetween thedeviceand the network.The EMAC supportsboth10Base-T and 100Base-TX,or10 Mbits/second(Mbps)and 100 Mbps ineitherhalf-orfull-duplexmode, withhardwareflowcontroland qualityofservice(QoS) support. The EMAC controlstheflowofpacketdatafromthedevicetothePHY. The MDIO module controlsPHY configurationand statusmonitoring. Both the EMAC and the MDIO modules interfaceto the devicethrougha custom interfacethatallows efficientdata transmissionand reception.This custom interfaceis referredto as the EMAC control module,and isconsideredintegralto the EMAC/MDIO peripheral.The controlmodule isalsoused to multiplexand controlinterrupts.

5.12.1 EthernetMIIElectricaland Timing Specifications

Figure5-22.MIIReceive Timing Table5-36.MIIReceive Timing Parameter Description MIN MAX tsu(MIIMRXD) Setuptime,MIIMRXD toMIIMRCLK risingedge 8ns tsu(MIIMRXDV) Setuptime,MIIMRXDV toMIIMRCLK risingedge 8ns tsu(MIIMRXER) Setuptime,MIIMRXER toMIIMRCLK risingedge 8ns th(MIIMRXD) Holdtime,MIIMRXD validafterMIIRCLK risingedge 8ns th(MIIMRXDV) Holdtime,MIIMRXDV validafterMIIRCLK risingedge 8ns th(MIIMRXER) Holdtime,MIIMRXDV validafterMIIRCLK risingedge 8ns

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PRODUCT□PREVIEW MII_MTCLK MII_MTXD MII_MTXEN V ALID RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012 Figure5-23.MIITransmitTiming Table5-37.MIITransmitTiming Parameter Description MIN MAX td(MIIMTXD) Delaytime,MIIMTCLK risingedge toMIIMTXD 5ns 25ns td(MIIMTXEN) Delaytime,MIIMTCLK risingedge toMIIMTXEN 5ns 25ns Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 161 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW RMII_MHz_50_CLK RMII_TXEN RMII_TXD[1:0] RMII_RXD[1:0] RMII_CRS_DV RMII_RXER 1 1 RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com

5.12.2 EthernetRMII Timing

Figure5-24.RMII Timing Diagram Table5-38.RMII Timing Requirements NO. Parameter Value Unit MIN NOM MAX 1 tc(REFCLK) Cycletime,RMII_REF_CLK - 20 - ns 2 tw(REFCLKH) Pulsewidth,RMII_REF_CLK High 7 - 13 ns 3 tw(REFCLKL) Pulsewidth,RMII_REF_CLK Low 7 - 13 ns 6 tsu(RXD-REFCLK) Inputsetuptime,RMII_RXD validbefore 4 - - ns RMII_REF_CLK High 7 th(REFCLK-RXD) Inputholdtime,RMII_RXD validafter 2 - - ns RMII_REF_CLK High 8 tsu(CRSDV-REFCLK) Inputsetuptime,RMII_CRSDV validbefore 4 - - ns RMII_REF_CLK High 9 th(REFCLK-CRSDV) Inputholdtime,RMII_CRSDV validafter 2 - - ns RMII_REF_CLK High 10 tsu(RXER-REFCLK) Inputsetuptime,RMII_RXER validbefore 4 - - ns RMII_REF_CLK High 11 th(REFCLK-RXER) Inputholdtime,RMII_RXER validafter 2 - - ns RMII_REF_CLK High 4 td(REFCLK-TXD) Outputdelaytime,RMII_REF_CLK Highto 2 - 16 ns RMII_TXD valid 5 td(REFCLK-TXEN) Outputdelaytime,RMII_REF_CLK Highto 2 - 16 ns RMII_TX_EN valid

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PRODUCT□PREVIEW MDCLK MDIO (output) MDCLK MDIO (input) RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012

5.12.3 Management Data Input/Output(MDIO)

Figure5-25.MDIO InputTiming Table5-39.MDIO InputTiming Requirements NO. Parameter Value Unit MIN MAX 1 tc(MDCLK) Cycletime,MDCLK 400 - ns 2 tw(MDCLK) Pulseduration,MDCLK high/low 180 - ns 3 tt(MDCLK) Transitiontime,MDCLK - 5 ns 4(1) tsu(MDIO-MDCLKH) Setuptime,MDIO datainputvalidbeforeMDCLK 10 - ns High 5 th(MDCLKH-MDIO) Holdtime,MDIO datainputvalidafterMDCLK 10 - ns High (1) The minimum 10ns ofsetuptimeisdictatedby theIEEE MDIO standard.Thisdesigndoes notmeet thisstandardspecification.The actualrequiredminimum setuptimeforMDIO datainputvalidbeforeMDCLK highis17 ns. Figure5-26.MDIO Output Timing Table5-40.MDIO Output Timing Requirements NO. Parameter Value Unit MIN MAX 1 tc(MDCLK) Cycletime,MDCLK 400 - ns 7 td(MDCLKL-MDIO) Delaytime,MDCLK lowtoMDIO dataoutput 0 100 ns valid Copyright© 2012,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 163 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW T XENL T XDPLS T XSE0 RCVDPLS RCVDMNS RCVDAT A T ransmit Receive FSU15 FSU18 FSU16 FSU19FSU17 FSU20 FSU20 FSU21 FSU21 RM46L450 RM46L850 SPNS184 –SEPTEMBER 2012 www.ti.com

5.13 UniversalSerialBus Controller

5.13.1 Features

ThisdeviceprovidesseveralvaritiesofUSB functionality,including:

• One full-speedUSB device portcompatiblewith the USB SpecificationRevision2.0 and USB SpecificationRevision1.1
• Two USB hostportscompatiblewithUSB SpecificationRevision2.0,which isbased on the OHCI SpecificationForUSB Release1.0.

5.13.2 Electricaland Timing Specifications

Table5-41.Full-SpeedUSB InterfaceTiming Requirements(1) NO. Parameter MIN MAX Unit FSU20 td(VPL,VML) Time duration,RCVDPLS and 14 ns RCVDMNS lowtogetherduring transition FSU21 td(VPH, VMH) Time duration,RCVDPLS and 8 ns RCVDMNS hightogetherduring transition (1) The capacitiveloadingisequivalenttp15 pF Table5-42.Full-SpeedUSB InterfaceSwitchingCharacteristics(1) NO. Parameter MIN MAX Unit FSU15 td(TXENL –DATV) DelaytimeTXENL activeto 0 1.5 ns TXDPLS valid FSU16 td(TXENL –SE0V) DelaytimeTXENL activetoTXSE0 0 1.5 ns valid FSU17 ts(DAT–SE0) Skew between TXDPLS and TXSE0 1.5 ns transition FSU18 td(TXENH –DATI) DelaytimeTXENL inactiveto 0 1.5 ns TXDPLS invalid FSU19 td(TXENH –SE0I) DelaytimeTXENL inactiveto 0 1.5 ns TXSE0 invalid (1) The capacitiveloadingisequivalenttp15 pF Figure5-27.Full-SpeedUSB Interface– Transmitand Receive Modes

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PRODUCT□PREVIEW x RM 4 6 L 8 5 0 ZWT T R Prefix: x = Not Qualified Removed when qualified RM = Real Time Microcontroller CPU: 4 = ARM Cortex-R4 Flash / RAM Size: 4 = 1MB flash, 128kB RAM 8 = 1.25MB flash, 192kB RAM Network Interfaces: 5 = Ethernet and USB Package Type: PGE = 144 Pin Package ZWT = 337 BGA Package Temperature Range: T = -40...+105 C o Shipping Options: R = Tape and Reel Series Number Architecture: L = Lockstep Frequency: 0 = 200MHz RM46L450 RM46L850 www.ti.com SPNS184 –SEPTEMBER 2012

6 Device and Documentation Support

6.1 Device and Development-Support Tool Nomenclature

To designatethestagesintheproductdevelopmentcycle,TIassignsprefixestothepartnumbers of alldevices.Eachdevicehas one ofthreeprefixes:X, P, ornull(noprefix)(forexample,xRM46L852). These prefixesrepresentevolutionarystagesof productdevelopmentfrom engineeringprototypes throughfullyqualifiedproductiondevices/tools. Devicedevelopmentevolutionaryflow: x Experimentaldevicethatis not necessarilyrepresentativeof the finaldevice'selectrical specificationsand may notuse productionassemblyflow. P Prototypedevicethatisnot necessarilythe finalsilicondieand may not necessarilymeet finalelectricalspecifications. null Fully-qualifiedproductiondevice. x and P devicesand TMDX development-supporttoolsareshippedagainstthefollowingdisclaimer: "Developmentalproductisintendedforinternalevaluationpurposes." Productiondeviceshave been characterizedfully,and the qualityand reliabilityof the devicehave been demonstratedfully.TI'sstandardwarrantyapplies. Predictionsshow thatprototypedeviceshave a greaterfailureratethan the standardproduction devices.Texas Instrumentsrecommends thatthesedevicesnot be used inany productionsystem because theirexpectedend-usefailureratestillisundefined.Only qualifiedproductiondevicesareto be used. The figurebelowillustratesthenumberingand symbolnomenclaturefortheRM46Lx50 devices. Figure6-1.RM46Lx50 Device Numbering Conventions

6.2 Community Resources

The followinglinksconnectto TI community resources.Linkedcontentsare provided"AS IS"by the respectivecontributors.They do notconstituteTI specificationsand do notnecessarilyreflectTI'sviews; see TI'sTerms ofUse. Hercules™ ARM ® Cortex™ SafetyMicrocontrollerSectionoftheTIE2E Support Community. TI's Engineer-to-Engineer(E2E)Community. Createdtofostercollaborationamong engineers. At e2e.ti.com,you can ask questions,share knowledge,exploreideas and help solve problemswithfellowengineers. Copyright© 2012,Texas InstrumentsIncorporated Deviceand DocumentationSupport 165 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

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6.3 Device Identification

6.3.1 Device IdentificationCode Register

The deviceidentificationcode registeridentifiesseveralaspectsofthedeviceincludingthesiliconversion. The detailsofthedeviceidentificationcode registerareshown inTable6-1.The deviceidentificationcode registervalueforthisdeviceis:

• Rev 0 = 0x8046AD05 Figure6-2.Device ID BitAllocationRegister 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CP-15 UNIQUE ID TECH R-1 R-00000000100011 R-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TECH I/O PERIPH FLASH ECC RAM VERSION 1 0 1 VOLT PARITY ECC AGE R-101 R-0 R-1 R-10 R-1 R-00000 R-1 R-0 R-1 LEGEND: R/W = Read/Write;R = Read only;-n = valueafterreset Table6-1.Device ID BitAllocationRegisterFieldDescriptions Bit Field Value Description

31 CP15 Indicatesthepresenceofcoprocessor15

1 CP15 present

30-17 UNIQUE ID 100011 Uniquedeviceidentificationnumber Thisbitfieldholdsa uniquenumber fora dedicateddeviceconfiguration(die). 16-13 TECH Processtechnologyon whichthedeviceismanufactured.

0101 F021

12 I/OVOLTAGE I/Ovoltageofthedevice. 0 I/Oare3.3v

11 PERIPHERAL 1 PeripheralParity

PARITY Parityon peripheralmemories 10-9 FLASH ECC FlashECC

10 Program memory withECC

8 RAM ECC IndicatesifRAM memory ECC ispresent.

1 ECC implemented

7-3 REVISION RevisionoftheDevice. 2-0 101 The platformfamilyID isalways0b101

6.3.2 Die IdentificationRegisters

The fourdieID registersataddresses0xFFFFE1F0, 0xFFFFE1F4, 0xFFFFE1F8 and FFFFE1FC form a 128-bitdieidwiththeinformationas shown inTableTable6-2. Table6-2.Die-IDRegisters Item # ofBits BitLocation X Coord.on Wafer 8 7..0 Y Coord.on Wafer 8 15..8 Wafer # 6 21..16 Lot# 24 45..22 Reserved 82 127..46

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7 MechanicalData

7.1 Thermal Data

Table7-1shows thethermalresistancecharacteristicsfortheQFP -PGE mechanicalpackage. Table7-2shows thethermalresistancecharacteristicsfortheBGA -ZWT mechanicalpackage. Table7-1.Thermal ResistanceCharacteristics (PGE Package) PARAMETER °C /W R ΘJA 45 R ΘJC 5 Table7-2.Thermal ResistanceCharacteristics (ZWT Package) PARAMETER °C /W R ΘJA 18.8 R ΘJC 7.1

7.2 Packaging Information

The followingpackaginginformationreflectsthemost currentreleaseddataavailableforthedesignated device(s).Thisdataissubjecttochange withoutnoticeand withoutrevisionofthisdocument. Copyright© 2012,Texas InstrumentsIncorporated MechanicalData 167 SubmitDocumentationFeedback ProductFolderLinks:RM46L450 RM46L850

PRODUCT□PREVIEW FunctionalSafetyDisclaimerforSafetyCriticalSolutions TI'ssafetycriticalsolutions,includingintegratedcircuits,softwareand toolshelpTI'scustomerscreateend productsthatmay be used inappropriatelydesignedsafety-criticalapplicationstocomplywithfunctionalsafetystandardsorrequirements. Buyers representand agree thatthey have allthe necessaryexpertiseto design,manage and assure effectivesystem-level safeguardsto anticipate,monitorand controlsystem failuresin safety-criticalapplications.Buyers agree and accept sole responsibilitytomeet and comply withallapplicableregulatorystandardsand safety-relatedrequirementsconcerningtheirsystems and end-productswhich use TI'ssafety-criticalapplications.Buyers willfullyindemnifyTI and itsrepresentativesagainstany damages arisingoutoftheuse ofTIproductsinsafety-criticalapplications. TIintegratedcircuitsarenotauthorizedforuse inFDA ClassIII(orsimilarlife-criticalmedicalequipment)unlessauthorizedofficers ofthepartieshave executeda specialagreementspecificallygoverningsuch use.

www.ti.com 3-May-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples RM46L450PGET ACTIVE LQFP PGE 144 TBD Call TI Call TI -40 to 105 RM46L450ZWTT ACTIVE NFBGA ZWT 337 TBD Call TI Call TI -40 to 105 RM46L850PGET ACTIVE LQFP PGE 144 TBD Call TI Call TI -40 to 105 RM46L850ZWTT ACTIVE NFBGA ZWT 337 TBD Call TI Call TI -40 to 105 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK 4040147/C 10/96 0,27 0,17 0,13 NOM 0,25 0,75 0,45 0,05 MIN Seating Plane Gage Plane 108 109 144 SQ SQ22,20 21,80 19,80 17,50 TYP 20,20 1,35 1,45 1,60 MAX M0,08 0°–7° 0,08 0,50 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026

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