RM0029

STMicroelectronics

The primary objective of this document 24-Sep-2013

Manufacturer: STMicroelectronics

Document: 1740 Pages / 13Mb

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PDF pages: 1740

Technical content

Datasheet sections

1 Introduction
1.1 The SPC564A74xx, SPC564A80xx Microcontroller Family
1.2 SPC564A80 and SPC564A70 Device Comparison
1.3 Device block diagram
1.4 Feature summary
1.4.1 Feature details
1.4.3 Crossbar Switch (XBAR)
1.4.5 Interrupt controller
1.4.6 Memory protection unit (MPU)
1.4.7 FMPLL
1.4.8 SIU
1.4.9 Flash memory
1.4.10 BAM
1.4.13 Reaction module
1.4.15 DSPI
1.4.17 FlexCAN
1.4.18 FlexRay
1.4.19 System timers
1.4.20 Software watchdog timer (SWT)
1.4.21 Cyclic redundancy check ( CRC) module
1.4.22 Error correction status module (ECSM)

Datasheet sections

5 Operating Modes and Clocking
5.1 Overview
5.2 Modes of operation
5.2.1 Normal mode
5.2.2 Debug mode
5.2.3 Low power modes
5.3 Clock architecture
5.3.1 Overview
5.3.2 Block diagram
5.3.3 System clock sources
5.3.4 FMPLL modes of operation
6 Device Performance Optimization
6.1 Introduction
6.2 Features
6.3 Configuring hardware features
6.3.1 Branch target buffer (BTB)
6.3.2 Frequency-modulated PLL
6.3.3 Flash bus interface unit
6.3.4 Crossbar switch
6.3.5 Cache
6.3.6 Memory management unit (MMU)
6.4 Application software
6.4.1 Compiler optimizations
6.4.2 Signal processing extension
6.4.3 Hardware single precision floating point
6.4.4 Variable length encoding
6.5 Peripherals and general application guidelines
6.6 Performance optimization checklist
7.1 Overview
7.2 Features
7.3 Microarchitecture summary
7.3.1 Instruction unit features
7.3.2 Integer unit features

Datasheet sections

9.2.3 Coherency
9.3 Function
9.3.1 Arbitration
9.3.2 Priority assignment
10 Peripheral Bridge (PBRIDGE)
10.1 PBRIDGE features
10.2 PBRIDGE modes of operation
10.3 PBRIDGE block diagram
10.4 PBRIDGE signal description
10.5 PBRIDGE functional description
10.5.1 Read cycles
10.5.2 Write cycles
10.6 Memory map and register description
10.6.1 Memory map
10.6.2 Register descriptions
11 General-Purpose Static RAM (SRAM)
11.1 Introduction
11.2 Features
11.3 Modes of operation
11.3.1 Normal (Functional) mode
11.3.2 Standby mode
11.4 Block diagram
11.5 External signal description
11.6 Register memory map
11.7 Functional description
11.8 SRAm ecc mechanism
11.8.1 Access timing
11.8.2 Reset effects on SRAM accesses
11.9 Initialization and application information
11.9.1 Example code
12 Flash memory
12.1 Introduction

Datasheet sections

14.1.1 Device-Specific Features
14.1.2 Unsupported Features
14.2 Introduction
14.2.1 Overview
14.2.2 Features
14.2.3 Modes of operation
14.3 External signal description
14.3.1 Overview
14.3.2 Detailed signal descriptions
14.3.3 Signal output buffer enable logic by mode
14.4 Memory map/Register definition
14.4.1 Register Descriptions
14.5 Functional Description
14.5.1 External Bus Interface Features
14.5.2 External bus operations
14.6 Initialization/Application information
14.6.1 Booting from external memory
14.6.2 Running with SDR (Single Data Rate) burst memories
14.6.3 Running with asynchronous memories
14.6.4 Connecting an mcu to multiple memories
14.6.5 EBI operation with reduced Pinout MCUs
15 Interrupt Controller (INTC)
15.1 Information specific to this device
15.1.1 Device-specific features
15.2 Introduction
15.2.1 Block diagram
15.2.2 Overview
15.2.3 Features
15.2.4 Modes of operation
15.3 External signal description
15.4 Memory map and register definition
15.4.1 Register descriptions
15.5 Functional description
15.5.1 Interrupt request sources
15.5.2 Priority management

Datasheet sections

16.6.15 Pad Configuration Registers (SIU_PCR)
16.6.16 GPIO Pin Data Output Registers (SIU_GPDO0_3 – SIU_GPDO412_413)
16.6.17 GPIO Pin Data Input Registers (SIU_GPDI0_3 – SIU_GPDI_232)
16.6.19 External IRQ Input Select Register (SIU_EIISR)
16.6.20 DSPI Input Select Register (SIU_DISR)
16.6.21 IMUX Select Register 3 (SIU_ISEL3)
16.6.22 IMUX Select Register 8 (SIU_ISEL8)
16.6.23 IMUX Select Register 9 (SIU_ISEL9)
16.6.24 IMUX Select Register 10 (SIU_ISEL10)
16.6.25 Chip Configuration Register (SIU_CCR)
16.6.26 External Clock Control Register (SIU_ECCR)
16.6.27 Compare A High Register (SIU_CARH)
16.6.28 Compare A Low Register (SIU_CARL)
16.6.29 Compare B High Register (SIU_CBRH)
16.6.30 Compare B Low Register (SIU_CBRL)
16.6.31 System Clock Register (SIU_SYSDIV)
16.6.32 Halt Register (SIU_HLT)
16.6.33 Halt Acknowledge Register (SIU_HLTACK)
16.6.34 Core MMU PID Control Register (SIU_EMPCR0)
16.7 Functional description
16.7.1 System configuration
16.7.2 Reset control
16.7.3 External interrupt request input (IRQ)
16.7.4 GPIO operation
16.7.5 Internal multiplexing
17 Frequency-modulated phase locked loop (FMPLL)
17.1 Information specific to this device
17.1.1 Device-specific features
17.1.2 Device-specific parameters
17.2 Introduction
17.2.1 Overview
17.2.2 Features
17.2.3 Modes of operation
17.3 External signal description

Datasheet sections

20.1.2 Features
20.1.3 Modes of operation
20.2 External signal description
20.3 Memory map and register definition
20.3.1 Memory map
20.3.2 Register descriptions
20.4 Functional description
21 Boot Assist Module (BAM)
21.1 Overview
21.2 Features
21.3 Modes of operation
21.3.1 Normal mode
21.3.2 Debug mode
21.3.3 Internal boot mode
21.3.4 Serial boot mode
21.3.5 Calibration bus boot mode
21.4 Memory map
21.5 Functional description
21.5.1 BAM Program flow chart
21.5.2 BAM program operation
21.5.3 Reset configuration half word (RCHW)
21.5.4 Internal boot mode
21.5.5 Serial boot mode
21.5.6 Booting from the External Bus Interface (EBI)
22 Configurable Enhanced Modular IO Subsystem (eMIOS200)
22.1 Device-specific features
22.2 Introduction
22.2.1 Features
22.2.2 Modes of operation
22.2.3 Channel configurations
22.3 External signals description
22.4 Memory map/register definition
22.4.1 Memory map
22.4.2 Global registers

Datasheet sections

23.4 Functional description
23.4.1 Reaction channel
23.4.2 Modulation control words bank
23.4.3 Shared timer bank
23.4.4 Hold-off timer bank
23.4.5 Threshold bank and comparator
23.4.6 ADC interface
23.4.7 Prescalers
23.4.8 Banked mode support
23.5 Modulation Modes
23.5.1 Threshold/Threshold mode
23.5.2 Threshold/Hold-off mode
23.5.3 Limitations on the modulation process
23.6 Monitored modulation
23.7 DMA support
23.8 Reset overview
23.9 Reaction module interrupts
23.9.1 Interrupt sources
23.10 Use cases
23.10.1 Advancing modulation phase on a threshold level
23.10.2 Controlling the loop function
23.10.3 Banked mode
24 Enhanced Time Processing Unit (eTPU2)
24.1 Information specific to this device
24.1.1 Device-specific features
24.2 Introduction
24.2.1 Overview
24.2.2 Features
24.2.3 Modes of operation
24.3 External signal description
24.3.1 Overview
24.3.2 Detailed signal descriptions
24.4 Memory map/register definition
24.4.1 Memory map
24.4.2 System configuration registers

Datasheet sections

25.3 Modes of operation
25.3.1 Normal mode
25.3.2 Streaming mode
25.3.3 Debug mode
25.3.4 Stop mode
25.4 External signal description
25.4.1 Overview
25.4.2 Detailed signal descriptions
25.5 Memory Map/Register Definition
25.5.1 EQADC Memory Map
25.5.2 EQADC Register Descriptions
25.5.3 On-Chip ADC Registers
25.6 Functional Description
25.6.1 Overview
25.6.2 Data Flow in EQADC
25.6.3 Command/Result Queues
25.6.4 EQADC Command FIFOs
25.6.5 EQADC Result FIFOs
25.6.6 On-Chip ADC Configuration and Control
25.6.7 Internal/External Multiplexing
25.6.8 EQADC DMA/Interrupt request
25.6.9 EQADC Synchronous Serial Interface (SSI) Sub-Block
25.6.10 EQADC Parallel Side Interface (PSI) Sub-Block
25.6.11 Analog Sub-Block
25.7 Initialization/Application information
25.7.1 Multiple queues control setup example
25.7.2 EQADC/DMAC Interface
25.7.3 Sending immediate command setup example
25.7.4 Modifying queues
25.7.5 CQueue and RQueues usage
25.7.6 ADC Result Calibration
25.7.7 EQADC versus QADC
26 Decimation Filter
26.1 Information specific to this device
26.1.1 Device-specific features

Datasheet sections

26.8 Filter example simulation
26.8.1 Coefficients calculation
26.8.2 Input data calculation
26.8.3 Filter results
27 Temperature Sensor
27.1 Overview
27.2 Detailed description
27.3 Temperature formula
27.3.1 T LOW and THIGH
27.3.2 T TSENS_CODE(TLOW) and TTSENS_CODE(THIGH)
27.3.3 V BG_CODE(TLOW)
27.3.4 Temperature sensor voltage (V TENS(T))
27.3.5 Bandgap reference voltage (V BG_CODE(T))
27.3.6 Registers
28 System Information Module and Trim (SIM)
28.1 Overview
28.2 User trim values
29 Cyclic Redundancy Checker (CRC) Unit
29.1 Overview
29.2 Features
29.2.1 Access and performance
29.3 Calculating a CRC checksum
29.3.1 Configuring the context
29.3.2 Initializing the context seed value
29.3.3 Writing the data stream to the context input
29.3.4 Reading the checksum
29.4 Register descriptions
29.4.1 CRC Configuration Register (CRC_CFG)
29.4.2 CRC Input Register (CRC_INP)
29.4.3 CRC Current Status Register (CRC_CSTAT)
29.4.4 CRC Output Register (CRC_OUTP)
29.5 Use cases and limitations

Datasheet sections

30.9.13 Peripheral chip select expansion and deglitching
30.9.14 DMA and interrupt conditions
30.9.15 Modified SPI transfer format
30.9.16 LVDS pad usage
30.9.17 DSPI connections to eTPU_A, eMIOS and SIU
30.9.18 Power saving features
30.10 Initialization/Application information
30.10.1 How to manage DSPI queues
30.10.2 Switching master and slave mode
30.10.3 Baud rate settings
30.10.4 Delay settings
30.10.5 Calculation of FIFO pointer addresses
31 Enhanced Serial Communication Interface (eSCI)
31.1 Introduction
31.1.1 Bibliography
31.1.2 Acronyms and abbreviations
31.1.3 Glossary
31.1.4 Overview
31.1.5 Features
31.1.6 Modes of operation
31.2 External signal description
31.2.1 Detailed signal descriptions
31.3 Memory map and register definition
31.3.1 Memory map
31.3.2 Register descriptions
31.4 Functional description
31.4.1 Module control
31.4.2 Frame formats
31.4.3 Baud rate and clock generation
31.4.4 Baud rate tolerance
31.4.5 SCI mode
31.4.6 LIN mode
31.4.7 Interrupts
31.5 Application Information
31.5.1 SCI data frames separated by preamble

Datasheet sections

33.1.3 Color coding
33.1.4 Overview
33.1.5 Features
33.1.6 Modes of operation
33.2 External signal description
33.2.1 Detailed signal descriptions
33.3 Controller host interface clocking
33.4 Protocol engine clocking
33.4.1 Oscillator clocking
33.4.2 PLL clocking
33.5 Memory map and register description
33.5.1 Memory map
33.5.2 Register descriptions
33.6 Functional description
33.6.1 Message buffer concept
33.6.2 Physical message buffer
33.6.3 Message buffer types
33.6.4 FlexRay memory area layout
33.6.5 Physical message buffer description
33.6.6 Individual message buffer functional description
33.6.7 Individual message buffer search
33.6.8 Individual message buffer reconfiguration
33.6.9 Receive FIFOs
33.6.10 Channel device modes
33.6.11 External clock synchronization
33.6.12 Sync frame ID and sync frame deviation tables
33.6.13 MTS generation
33.6.14 Key slot transmission
33.6.15 Sync frame filtering
33.6.16 Strobe signal support
33.6.17 Timer support
33.6.18 Slot status monitoring
33.6.19 System bus access
33.6.20 Interrupt support
33.6.21 Lower bit rate support
33.6.22 PE data memory (PE DRAM)

Datasheet sections

35.3.2 Trimming Register (TRIMR)
35.3.3 Status Register (SR)
35.4 Functional description
35.4.1 Bandgap
35.4.7 Resets and interrupts
35.4.9 ADC test mux
35.5 Electrical characteristics
36 JTAG Controller (JTAGC)
36.1 Information specific to this device
36.1.1 Device-specific parameters
36.1.2 Device identification register parameters
36.1.3 Auxiliary TAP controller instructions
36.2 Introduction
36.2.1 Overview
36.2.2 Features
36.2.3 Modes of operation
36.3 External signal description
36.3.1 Overview
36.3.2 Detailed signal descriptions
36.4 Register definition
36.4.1 Register descriptions
36.5 Functional description
36.5.1 JTAGC reset configuration
36.5.3 TAP controller state machine
36.5.4 JTAGC block instructions
36.5.5 Boundary scan
36.6 Initialization/application information

Datasheet sections

39 Revision history

September 2013 Doc ID 15177 Rev 8 1/1740 RM0029 Reference manual SPC564A74xx, SPC564A80xx 32-bit MCU family built on the embedded Power Architecture® Introduction The primary objective of this document is to define the functionality of the SPC564A74xx, SPC564A80xx family of microcontrollers for use by software and hardware developers. The SPC564A74xx, SPC564A80xx family is built on Power Architecture ® technology and integrates technologies that are important for today’s lower-end applications.

15.6.6 Selecting priorities according to request rates and

Doc ID 15177 Rev 8 11/1740

Doc ID 15177 Rev 8 13/1740 23.3.13 REACM ADC result maximum limit check register (REACM_ADCMAX) . 741

23.3.14 REACM Modulation Range Pulse Width Register (REACM_RANGEPWD)

23.3.15 REACM Modulation Minimum Pulse Width Register (REACM_MINPWD)

23.3.16 REACM Modulation Control Word Bank Registers (REACM_MWBK) 743

Doc ID 15177 Rev 8 15/1740

Doc ID 15177 Rev 8 17/1740

Doc ID 15177 Rev 8 19/1740

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Doc ID 15177 Rev 8 23/1740

Doc ID 15177 Rev 8 25/1740

Table 21. Performance optimization checklist—Part 3. Peripherals and general application guidelines

Table 98. EBI Base Registers (EBI_BR0-EBI_BR3, EBI_CAL_BR0-3)

Table 99. EBI Option Registers (EBI_OR0-EBI_OR3, EBI_CAL_OR0-3)

Table 564. EQADC Null Message Send Format Register (EQADC_NMSFR) field description . . . 1042 Table 565. EQADC External Trigger Digital Filter Register (EQADC_ETDFR) field description . . . 1043

Table 584. EQADC STAC Client Configuration Register (EQADC_REDLCCR) field description . . 1069 Table 613. Write Configuration Command Format for On-Chip ADC Operation field description . . 1102 Table 614. Read Configuration Command Format for On-Chip ADC Operation field description . . 1103

Table 671. Temperature Calculati on Constants Register 0 (TSENS_TCCR0) field descriptions. . . 1249 Table 672. Temperature Calculati on Constants Register 1 (TSENS_TCCR1) field descriptions. . . 1250

Table 918. Minimum f

66/1740 Doc ID 15177 Rev 8 Preface Overview The primary objective of this document is to define the functionality of the SPC564A74xx, SPC564A80xx family of microcontrollers for use by software and hardware developers. The SPC564A74xx, SPC564A80xx family is built on Power Architecture ® technology and integrates technologies that are important for today’s lower-end applications. As with any technical documentation, it is the reader’s responsibility to be sure he or she is using the most recent version of the documentation. To locate any published errata or updates for this document, visit the ST Web site at www.st.com. Audience This manual is intended for system software and hardware developers and applications programmers who want to develop products with the SPC564A74xx, SPC564A80xx device. It is assumed that the reader understands operating systems, microprocessor system design, basic principles of software and hardware, and basic details of the Power Architecture. Chapter organization and device-specific information This document includes chapters that describe:

The device as a whole
The functionality of the individual modules on the device In the latter, any device-specific information is presented in the section “Information Specific to This Device” at the beginning of the chapter. References In addition to this reference manual, the following documents provide additional information on the operation of the SPC564A74xx, SPC564A80xx:
IEEE-ISTO 5001™ - 2003 and 2010, The Nexus 5001™ Forum Standard for a Global Embedded Processor Debug Interface
IEEE 1149.1-2001 standard - IEEE Standard Test Access Port and Boundary-Scan Architecture

Doc ID 15177 Rev 8 67/1740

1 Introduction

1.1 The SPC564A74xx, SPC564A80xx Microcontroller Family

The SPC564A74xx, SPC564A80xx is part of a family of microcontrollers that serves two main application areas:

Mid-range engine management
Automotive transmission control The SPC564A74xx, SPC564A80xx contains features of ST’s SPC563M family and many new features coupled with high performance 90 nm CMOS technology to provide substantial reduction of cost per feature and significant performance improvement. The e200z4 host processor core of the SPC564A74xx, SPC564A80xx complies with the Power Architecture ® embedded category architecture. It is 100% user mode compatible (with floating point library) with the classic PowerPC instruction set. In addition to the Power Architecture instruction set, this core also has additional instruction support for digital signal processing (DSP). The SPC564A74xx, SPC564A80xx has two levels of memory hierarchy consisting of 8 KB of instruction cache, backed by up to 192 KB on-chip SRAM and up to 4 MB of internal flash memory. The SPC564A74xx, SPC564A80xx includes an external bus interface and a “calibration bus” that is only accessible when using calibration tools. On-chip modules include:
Dual issue, 32-bit Power Architecture embedded category compliant e200z4 CPU core complex
Memory protection unit (MPU)
Interrupt controller (INTC)
Frequency-modulated phase-locked loop (FMPLL)
System integration unit (SIU)
Boot assist module (BAM)
32-channel second generation enhanced time processor unit (eTPU2)
24-channel enhanced modular Input Output System (eMIOS)
Enhanced queued analog-to-digital converter (eQADC)
3 deserial serial peripheral interface (DSPI) modules
3 enhanced serial communication interface (eSCI) modules
3 controller-area network (FlexCAN) modules
Cyclic redundancy check (CRC) module
System timers
Nexus development interface (NDI) per IEEE-ISTO 5001-2003 and 2010 standards
On-chip voltage regulator for regulating 5 V down to 3.3 V for internal functions and Nexus interface
On-chip voltage Regulator controller for regulating 5 V down to 1.2 V for core logic

1.2 SPC564A80 and SPC564A70 Device Comparison

Table 1 summarizes the features SPC564A80 and SPC564A70 microcontrollers. Table 1. SPC564A80 and SPC564A70 comparison

5 PIT channels

4 STM channels

1 Software Watchdog

Interrupt controller 486 ch.

199 interrupt vectors are reserved.
5 V single supply only for LQFP176.
Pinout compatible with STMicroelectronics’ SPC563M64 devices.
For ST calibration tool only.

Table 1. SPC564A80 and SPC564A70 comparison (continued)

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1.3 Device block diagram

Figure 1 shows a top-level block diagram of the SPC564A74xx, SPC564A80xx.

Figure 1. SPC564A74xx, SPC564A80xx Block Diagram

3 KB Data

14 KB Code

64 Channel

8 KB I-cache

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1.4 Feature summary

150 MHz e200z4 Power Architecture core – Variable length instruction encoding (VLE) – Superscalar architecture with 2 execution units – Up to 2 integer or floating point instructions per cycle – Up to 4 multiply and accumulate operations per cycle
Memory organization – 4 MB on-chip flash memory with ECC and Read While Write (RWW) – 192 KB on-chip SRAM with standby functionality (32 KB) and ECC – 8 KB instruction cache (with line locking), configurable as 2- or 4-way – 14 + 3 KB eTPU code and data RAM –5 × 4 crossbar switch (XBAR) – 24-entry MMU – External Bus Interface (EBI) with slave and master port
Fail Safe Protection – 16-entry Memory Protection Unit (MPU) – CRC unit with 3 sub-modules – Junction temperature sensor
Interrupts – Configurable interrupt controller (with NMI) – 64-channel DMA
Serial channels –3 × eSCI –3 × DSPI (2 of which support downstream Micro Second Channel [MSC]) –3 × FlexCAN with 64 messages each –1 × FlexRay module (V2.1) up to 10 Mbit/s with dual or single channel and 128 message objects and ECC
1 × eMIOS – 24 unified channels
1 × eTPU2 (second generation eTPU) – 32 standard channels –1 × reaction module (6 channels with three outputs per channel)
2 enhanced queued analog-to-digital converters (eQADCs) – Forty 12-bit input channels (multiplexed on 2 ADCs); expandable to 56 channels with external multiplexers – 6 command queues – Trigger and DMA support – 688 ns minimum conversion time
On-chip CAN/SCI/FlexRay Bootstrap loader with Boot Assist Module (BAM)
Nexus – Class 3+ for the e200z4 core – Class 1 for the eTPU

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JTAG (5-pin)
Development Trigger Semaphore (DTS) – Register of semaphores (32-bits) and an identification register – Used as part of a triggered data acquisition protocol – EVTO pin is used to communicate to the external tool
Clock generation – On-chip 4–40 MHz main oscillator – On-chip FMPLL (frequency-modulated phase-locked loop)
Up to 120 general purpose I/O lines – Individually programmable as input, output or special function – Programmable threshold (hysteresis)
Power reduction mode: slow, stop and stand-by modes
Flexible supply scheme – 5 V single supply with external ballast – Multiple external supply: 5 V, 3.3 V and 1.2 V
Packages –L Q F P 1 7 6 – LBGA208 – PBGA324 – Known Good Die (KGD) – 496-pin CSP (calibration tool only)

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1.4.1 Feature details

1.4.2 e200z4 core SPC564A74xx, SPC564A80xx devices have a high performance e200z448n3 core processor:

Dual issue, 32-bit Power Architecture embedded category CPU
Variable Length Encoding Enhancements
8 KB instruction cache: 2- or 4- way set associative instruction cache
Thirty-two 64-bit general purpose registers (GPRs)
Memory management unit (MMU) with 24-entry fully-associative translation look-aside buffer (TLB)
Harvard Architecture: Separate instruction bus and load/store bus
Vectored interrupt support
Non-maskable interrupt input
Critical Interrupt input
New ‘Wait for Interrupt’ instruction, to be used with new low power modes
Reservation instructions for implementing read-modify-write accesses
Signal processing extension (SPE) APU
Single Precision Floating point (scalar and vector)
Nexus Class 3+ debug
Process ID manipulation for the MMU using an external tool

1.4.3 Crossbar Switch (XBAR)

The XBAR multiport crossbar switch supports simultaneous connections between five master ports and four slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width. The crossbar allows three concurrent transactions to occur from the master ports to any slave port but each master must access a different slave. If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher priority master and grants it ownership of the slave port. All other masters requesting that slave port are stalled until the higher priority master completes its transactions. Requesting masters are treated with equal priority and are granted access to a slave port in round-robin fashion,

Doc ID 15177 Rev 8 75/1740 based upon the ID of the last master to be granted access. The crossbar provides the following features:

5 master ports – CPU instruction bus – CPU data bus –e D M A –F l e x R a y – External Bus Interface
4 slave ports –F l a s h – Calibration and EBI bus –S R A M – Peripheral bridge
32-bit internal address, 64-bit internal data paths 1.4.4 eDMA The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data movements via 64 programmable channels, with minimal intervention from the host processor. The hardware micro-architecture includes a DMA engine which performs source and destination address calculations, and the actual data movement operations, along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation is utilized to minimize the overall block size. The eDMA module provides the following features:
All data movement via dual-address transfers: read from source, write to destination
Programmable source and destination addresses, transfer size, plus support for enhanced addressing modes
Transfer control descriptor organized to support two-deep, nested transfer operations
An inner data transfer loop defined by a “minor” byte transfer count
An outer data transfer loop defined by a “major” iteration count
Channel activation via one of three methods: – Explicit software initiation – Initiation via a channel-to-channel linking mechanism for continuous transfers – Peripheral-paced hardware requests (one per channel)
Support for fixed-priority and round-robin channel arbitration
Channel completion reported via optional interrupt requests
One interrupt per channel, optionally asserted at completion of major iteration count
Error termination interrupts optionally enabled
Support for scatter/gather DMA processing
Ability to suspend channel transfers by a higher priority channel

1.4.5 Interrupt controller

The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time systems.

76/1740 Doc ID 15177 Rev 8 For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of interrupt request, the priority of each interrupt request is software configurable. When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource cannot preempt each other. The INTC provides the following features:

9-bit vector addresses
Unique vector for each interrupt request source
Hardware connection to processor or read from register
Each interrupt source can assigned a specific priority by software
Preemptive prioritized interrupt requests to processor
ISR at a higher priority preempts executing ISRs or tasks at lower priorities
Automatic pushing or popping of preempted priority to or from a LIFO
Ability to modify the ISR or task priority to implement the priority ceiling protocol for accessing shared resources
Low latency—three clocks from receipt of interrupt request from peripheral to interrupt request to processor This device also includes a non-maskable interrupt (NMI) pin that bypasses the INTC and multiplexing logic.

1.4.6 Memory protection unit (MPU)

The Memory Protection Unit (MPU) provides hardware access control for all memory references generated in a device. Using preprogrammed region descriptors, which define memory spaces and their associated access rights, the MPU concurrently monitors all system bus transactions and evaluates the appropriateness of each transfer. Memory references with sufficient access control rights are allowed to complete; references that are not mapped to any region descriptor or have insufficient rights are terminated with a protection error response. The MPU has these major features:

Support for 16 memory region descriptors, each 128 bits in size – Specification of start and end addresses provide granularity for region sizes from 32 bytes to 4 GB – MPU is invalid at reset, thus no access restrictions are enforced – Two types of access control definitions: processor core bus master supports the traditional {read, write, execute} permissions with independent definitions for

Doc ID 15177 Rev 8 77/1740 supervisor and user mode accesses; the remaining non-core bus masters (eDMA, FlexRay, and EBI1) support {read, write} attributes – Automatic hardware maintenance of the region descriptor valid bit removes issues associated with maintaining a coherent image of the descriptor – Alternate memory view of the access control word for each descriptor provides an efficient mechanism to dynamically alter the access rights of a descriptor only(a) – For overlapping region descriptors, priority is given to permission granting over access denying as this approach provides more flexibility to system software

Support for two XBAR slave port connections (SRAM and PBRIDGE) – For each connected XBAR slave port (SRAM and PBRIDGE), MPU hardware monitors every port access using the pre-programmed memory region descriptors – An access protection error is detected if a memory reference does not hit in any memory region or the reference is flagged as illegal in all memory regions where it does hit. In the event of an access error, the XBAR reference is terminated with an error response and the MPU inhibits the bus cycle being sent to the targeted slave device – 64-bit error registers, one for each XBAR slave port, capture the last faulting address, attributes, and detail information

1.4.7 FMPLL

The FMPLL allows the user to generate high speed system clocks from a 4 MHz to 40 MHz crystal oscillator or external clock generator. Further, the FMPLL supports programmable frequency modulation of the system clock. The PLL multiplication factor, output clock divider ratio are all software configurable. The PLL has the following major features:

Input clock frequency from 4 MHz to 40 MHz
Reduced frequency divider (RFD) for reduced frequency operation without forcing the PLL to relock
3 modes of operation – Bypass mode with PLL off – Bypass mode with PLL running (default mode out of reset) – PLL normal mode
Each of the three modes may be run with a crystal oscillator or an external clock reference a. EBI not available on all packages and is not available, as a master, for customer.

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Programmable frequency modulation – Modulation enabled/disabled through software – Triangle wave modulation up to 100 kHz modulation frequency – Programmable modulation depth (0% to 2% modulation depth) – Programmable modulation frequency dependent on reference frequency
Lock detect circuitry reports when the PLL has achieved frequency lock and continuously monitors lock status to report loss of lock conditions
Clock Quality Module – Detects the quality of the crystal clock and causes interrupt request or system reset if error is detected – Detects the quality of the PLL output clock; if error detected, causes system reset or switches system clock to crystal clock and causes interrupt request
Programmable interrupt request or system reset on loss of lock
Self-clocked mode (SCM) operation

1.4.8 SIU

The SPC564A74xx, SPC564A80xx SIU controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO), internal peripheral multiplexing, and the system reset operation. The reset configuration block contains the external pin boot configuration logic. The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU. The reset controller performs reset monitoring of internal and external reset sources, and drives the RSTOUT pin.

Doc ID 15177 Rev 8 79/1740 Communication between the SIU and the e200z4 CPU core is via the crossbar switch. The SIU provides the following features:

System configuration – MCU reset configuration via external pins – Pad configuration control for each pad – Pad configuration control for virtual I/O via DSPI serialization
System reset monitoring and generation – Power-on reset support – Reset status register provides last reset source to software – Glitch detection on reset input – Software controlled reset assertion
External interrupt – Rising or falling edge event detection – Programmable digital filter for glitch rejection – Critical Interrupt request – Non-Maskable Interrupt request
GPIO – Centralized control of I/O and bus pins – Virtual GPIO via DSPI serialization (requires external deserialization device) – Dedicated input and output registers for setting each GPIO and Virtual GPIO pin
Internal multiplexing – Allows serial and parallel chaining of DSPIs – Allows flexible selection of eQADC trigger inputs – Allows selection of interrupt requests between external pins and DSPI

1.4.9 Flash memory

The SPC564A74xx, SPC564A80xx provides up to 4 MB of programmable, non-volatile, flash memory. The non-volatile memory (NVM) can be used to store instructions or data, or both. The flash module includes a Fetch Accelerator that optimizes the performance of the flash array to match the CPU architecture. The flash module interfaces the system bus to a dedicated flash memory array controller. For CPU ‘loads’, DMA transfers and CPU instruction fetch, it supports a 64-bit data bus width at the system bus port, and 128- and 256-bit read data interfaces to flash memory. The module contains a prefetch controller which prefetches sequential lines of data from the flash array into the buffers. Prefetch buffer hits allow no-wait responses. The flash memory provides the following features:

Supports a 64-bit data bus for instruction fetch, CPU loads and DMA access. Byte, halfword, word and doubleword reads are supported. Only aligned word and doubleword writes are supported.
Fetch Accelerator – Architected to optimize the performance of the flash – Configurable read buffering and line prefetch support – Four-entry 256-bit wide line read buffer – Prefetch controller

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Hardware and software configurable read and write access protections on a per-master basis
Interface to the flash array controller pipelined with a depth of one, allowing overlapped accesses to proceed in parallel for interleaved or pipelined flash array designs
Configurable access timing usable in a wide range of system frequencies
Multiple-mapping support and mapping-based block access timing (0-31 additional cycles) usable for emulation of other memory types
Software programmable block program/erase restriction control
Erase of selected block(s)
Read page size of 128 bits (four words)
ECC with single-bit correction, double-bit detection
Program page size of 128 bits (four words) to accelerate programming
ECC single-bit error corrections are visible to software
Minimum program size is two consecutive 32-bit words, aligned on a 0-modulo-8 byte address, due to ECC
Embedded hardware program and erase algorithm
Erase suspend, program suspend and erase-suspended program
Shadow information stored in non-volatile shadow block
Independent program/erase of the shadow block

1.4.10 BAM

The BAM (Boot Assist Module) is a block of read-only memory that is programmed once by ST and is identical for all SPC564A74xx, SPC564A80xx MCUs. The BAM program is executed every time the MCU is powered-on or reset in normal mode. The BAM supports different modes of booting. They are:

Booting from internal flash memory
Serial boot loading (A program is downloaded into RAM via eSCI or the FlexCAN and then executed)
Booting from external memory on external bus The BAM also reads the reset configuration half word (RCHW) from internal flash memory and configures the SPC564A74xx, SPC564A80xx hardware accordingly. The BAM provides the following features:
Sets up MMU to cover all resources and mapping of all physical addresses to logical addresses with minimum address translation
Sets up MMU to allow user boot code to execute as either Power Architecture embedded category (default) or as VLE code
Location and detection of user boot code
Automatic switch to serial boot mode if internal flash is blank or invalid
Supports user programmable 64-bit password protection for serial boot mode
Supports serial bootloading via FlexCAN bus and eSCI using standard protocol
Supports serial bootloading via FlexCAN bus and eSCI with auto baud rate sensing

Doc ID 15177 Rev 8 81/1740

Supports serial bootloading of either Power Architecture code (default) or VLE code
Supports booting from calibration bus interface
Supports censorship protection for internal flash memory
Provides an option to enable the core watchdog timer
Provides an option to disable the system watchdog timer 1.4.11 eMIOS The eMIOS timer module provides the capability to generate or measure events in hardware. The eMIOS module features include:
Twenty-four 24-bit wide channels
3 channels’ internal timebases can be shared between channels
1 Timebase from eTPU2 can be imported and used by the channels
Global enable feature for all eMIOS and eTPU timebases
Dedicated pin for each channel (not available on all package types) Each channel (0–23) supports the following functions:
General-purpose input/output (GPIO)
Single-action input capture (SAIC)
Single-action output compare (SAOC)
Output pulse-width modulation buffered (OPWMB)
Input period measurement (IPM)
Input pulse-width measurement (IPWM)
Double-action output compare (DAOC)
Modulus counter buffered (MCB)
Output pulse width and frequency modulation buffered (OPWFMB) 1.4.12 eTPU2 The eTPU2 is an enhanced co-processor designed for timing control. Operating in parallel with the host CPU, the eTPU2 processes instructions and real-time input events, performs output waveform generation, and accesses shared data without host intervention. Consequently, for each timer event, the host CPU setup and service times are minimized or eliminated. A powerful timer subsystem is formed by combining the eTPU2 with its own instruction and data RAM. High-level assembler/compiler and documentation allows customers to develop their own functions on the eTPU2. SPC564A74xx, SPC564A80xx devices feature the second generation of the eTPU, called eTPU2. Enhancements of the eTPU2 over the standard eTPU include:
The Timer Counter (TCR1), channel logic and digital filters (both channel and the external timer clock input [TCRCLK]) now have an option to run at full system clock speed or system clock / 2.
Channels support unordered transitions: transition 2 can now be detected before transition 1. Related to this enhancement, the transition detection latches (TDL1 and TDL2) can now be independently negated by microcode.

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A new User Programmable Channel Mode has been added: the blocking, enabling, service request and capture characteristics of this channel mode can be programmed via microcode.
Microinstructions now provide an option to issue Interrupt and Data Transfer requests selected by channel. They can also be requested simultaneously at the same instruction.
Channel Flags 0 and 1 can now be tested for branching, in addition to selecting the entry point.
Channel digital filters can be bypassed. The eTPU2 includes these distinctive features:
32 channels; each channel associated with one input and one output signal – Enhanced input digital filters on the input pins for improved noise immunity – Identical, orthogonal channels: each channel can perform any time function. Each time function can be assigned to more than one channel at a given time, so each signal can have any functionality. – Each channel has an event mechanism which supports single and double action functionality in various combinations. It includes two 24-bit capture registers, two 24-bit match registers, 24-bit greater-equal and equal-only comparators. – Input and output signal states visible from the host
2 independent 24-bit time bases for channel synchronization: – First time base clocked by system clock with programmable prescale division from 2 to 512 (in steps of 2), or by output of second time base prescaler – Second time base counter can work as a continuous angle counter, enabling angle based applications to match angle instead of time – Both time bases can be exported to the eMIOS timer module – Both time bases visible from the host
Event-triggered microengine: – Fixed-length instruction execution in two-system-clock microcycle – 14 KB of code memory (SCM) – 3 KB of parameter (data) RAM (SPRAM) – Parallel execution of data memory, ALU, channel control and flow control sub- instructions in selected combinations – 32-bit microengine registers and 24-bit wide ALU, with 1 microcycle addition and subtraction, absolute value, bitwise logical operations on 24-bit, 16-bit, or byte operands, single-bit manipulation, shift operations, sign extension and conditional execution – Additional 24-bit Multiply/MAC/Divide unit which supports all signed/unsigned Multiply/MAC combinations, and unsigned 24-bit divide. The MAC/Divide unit works in parallel with the regular microcode commands.
Resource sharing features support channel use of common channel registers, memory and microengine time: – Hardware scheduler works as a “task management” unit, dispatching event service routines by predefined, host-configured priority – Automatic channel context switch when a “task switch” occurs, that is, one function thread ends and another begins to service a request from other channel:

Doc ID 15177 Rev 8 83/1740 channel-specific registers, flags and parameter base address are automatically loaded for the next serviced channel – SPRAM shared between host CPU and eTPU2, supporting communication either between channels and host or inter-channel – Hardware implementation of four semaphores support coherent parameter sharing between both eTPU engines – Dual-parameter coherency hardware support allows atomic access to two parameters by host

Test and development support features: – Nexus Class 1 debug, supporting single-step execution, arbitrary microinstruction execution, hardware breakpoints and watchpoints on several conditions – Software breakpoints – SCM continuous signature-check built-in self test (MISC - multiple input signature calculator), runs concurrently with eTPU2 normal operation

1.4.13 Reaction module

The reaction module provides the ability to modulate output signals to manage closed loop control without CPU assistance. It works in conjunction with the eQADC and eTPU2 to increase system performance by removing the CPU from the current control loop. The reaction module has the following features:

6 reaction channels
Each channel output is a bus of 3 signals, providing ability to control 3 inputs.
Each channel can implement a peak and hold waveform, making it possible to implement up to six independent peak and hold control channels Target applications include solenoid control for direct injection systems and valve control in automatic transmissions 1.4.14 eQADC The enhanced queued analog to digital converter (eQADC) block provides accurate and fast conversions for a wide range of applications. The eQADC provides a parallel interface to two on-chip analog to digital converters (ADC), and a single master to single slave serial interface to an off-chip external device. Both on-chip ADCs have access to all the analog channels. The eQADC prioritizes and transfers commands from six command conversion command ‘queues’ to the on-chip ADCs or to the external device. The block can also receive data from the on-chip ADCs or from an off-chip external device into the six result queues, in parallel, independently of the command queues. The six command queues are prioritized with Queue_0 having the highest priority and Queue_5 the lowest. Queue_0 also has the added ability to bypass all buffering and queuing and abort a currently running conversion on either ADC and start a Queue_0 conversion. This means that Queue_0 will always have a deterministic time from trigger to start of conversion, irrespective of what tasks the ADCs were performing when the trigger occurred. The eQADC supports software and external hardware triggers from other blocks to initiate transfers of commands from the queues to the on-chip ADCs or to the external device. It also monitors the fullness of command queues and result queues, and accordingly generates DMA or interrupt requests to control data movement between the queues and the system memory, which is external to the eQADC.

84/1740 Doc ID 15177 Rev 8 The ADCs also support features designed to allow the direct connection of high impedance acoustic sensors that might be used in a system for detecting engine knock. These features include differential inputs; integrated variable gain amplifiers for increasing the dynamic range; programmable pull-up and pull-down resistors for biasing and sensor diagnostics. The eQADC also integrates a programmable decimation filter capable of taking in ADC conversion results at a high rate, passing them through a hardware low pass filter, then down-sampling the output of the filter and feeding the lower sample rate results to the result FIFOs. This allows the ADCs to sample the sensor at a rate high enough to avoid aliasing of out-of-band noise; while providing a reduced sample rate output to minimize the amount DSP processing bandwidth required to fully process the digitized waveform. The eQADC provides the following features:

Dual on-chip ADCs –2 × 12-bit ADC resolution – Programmable resolution for increased conversion speed (12-bit, 10-bit, 8-bit) 12-bit conversion time: 938 ns (1 M sample/sec) 10-bit conversion time: 813 ns (1.2 M sample/second) 8-bit conversion time: 688 ns (1.4 M sample/second) – Up to 10-bit accuracy at 500 KSample/s and 8-bit accuracy at 1 MSample/s – Differential conversions – Single-ended signal range from 0 to 5 V – Variable gain amplifiers on differential inputs ( ×1, ×2, ×4) – Sample times of 2 (default), 8, 64 or 128 ADC clock cycles – Provides time stamp information when requested – Allows time stamp information relative to eTPU clock sources, such as an angle clock – Parallel interface to eQADC CFIFOs and RFIFOs – Supports both right-justified unsigned and signed formats for conversion results
40 single-ended input channels, expandable to 56 channels with external multiplexers (supports four external 8-to-1 muxes)
8 channels can be used as 4 pairs of differential analog input channels
Differential channels include variable gain amplifier for improved dynamic range
Differential channels include programmable pull-up and pull-down resistors for biasing and sensor diagnostics (200 kΩ, 100 kΩ, 5k Ω)
Additional internal channels for monitoring voltages (such as core voltage, I/O voltage, LVI voltages, etc.) inside the device
An internal bandgap reference to allow absolute voltage measurements
Silicon die temperature sensor – Provides temperature of silicon as an analog value – Read using an internal ADC analog channel – May be read with either ADC

Doc ID 15177 Rev 8 85/1740

2 Decimation Filters – Programmable decimation factor (1 to 16) – Selectable IIR or FIR filter – Up to 4th order IIR or 8th order FIR – Programmable coefficients – Saturated or non-saturated modes – Programmable Rounding (Convergent; Two’s Complement; Truncated) – Prefill mode to precondition the filter before the sample window opens – Supports Multiple Cascading Decimation Filters to implement more complex filter designs – Optional Absolute Integrators on the output of Decimation Filters
Full duplex synchronous serial interface to an external device – Free-running clock for use by an external device – Supports a 26-bit message length
Priority based queues – Supports six queues with fixed priority. When commands of distinct queues are bound for the same ADC, the higher priority queue is always served first – Queue_0 can bypass all prioritization, buffering and abort current conversions to start a Queue_0 conversion a deterministic time after the queue trigger – Supports software and hardware trigger modes to arm a particular queue – Generates interrupt when command coherency is not achieved
External hardware triggers – Supports rising edge, falling edge, high level and low level triggers – Supports configurable digital filter

1.4.15 DSPI

The deserial serial peripheral interface (DSPI) block provides a synchronous serial interface for communication between the SPC564A74xx, SPC564A80xx MCU and external devices. The DSPI supports pin count reduction through serialization and deserialization of eTPU and eMIOS channels and memory-mapped registers. The channels and register content are transmitted using a SPI-like protocol. This SPI-like protocol is completely configurable for baud rate, polarity and phase, frame length, chip select assertion, etc. Each bit in the frame may be configured to serialize either eTPU channels, eMIOS channels or GPIO signals. The DSPI can be configured to serialize data to an external device that implements the Microsecond Bus protocol. There are three identical DSPI blocks on the SPC564A74xx, SPC564A80xx MCU. The DSPI pins support 5 V logic levels or Low Voltage Differential Signalling (LVDS) to improve high speed operation. DSPI module features include:

Selectable LVDS pads working at 40 MHZ for SOUT and SCK pins for DSPI_B and DSPI_C
3 sources of serialized data: eTPU_A, eMIOS output channels and memory-mapped register in the DSPI
4 destinations for deserialized data: eTPU_A and eMIOS input channels, SIU external Interrupt input request, memory-mapped register in the DSPI

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32-bit DSI and TSB modes require 32 PCR registers, 32 GPO and GPI registers in the SIU to select either GPIO, eTPU or eMIOS bits for serialization
The DSPI Module can generate and check parity in a serial frame 1.4.16 eSCI Three enhanced serial communications interface (eSCI) modules provide asynchronous serial communications with peripheral devices and other MCUs, and include support to interface to Local Interconnect Network (LIN) slave devices. Each eSCI block provides the following features:
Full-duplex operation
Standard mark/space non-return-to-zero (NRZ) format
13-bit baud rate selection
Programmable 8-bit or 9-bit, data format
Programmable 12-bit or 13-bit data format for Timed Serial Bus (TSB) configuration to support the Microsecond bus standard
Automatic parity generation
LIN support – Autonomous transmission of entire frames – Configurable to support all revisions of the LIN standard – Automatic parity bit generation – Double stop bit after bit error – 10- or 13-bit break support
Separately enabled transmitter and receiver
Programmable transmitter output parity
2 receiver wake-up methods: – Idle line wake-up – Address mark wake-up
Interrupt-driven operation with flags
Receiver framing error detection
Hardware parity checking
1/16 bit-time noise detection
DMA support for both transmit and receive data – Global error bit stored with receive data in system RAM to allow post processing of errors

1.4.17 FlexCAN

The SPC564A74xx, SPC564A80xx MCU includes three controller area network (FlexCAN) blocks. The FlexCAN module is a communication controller implementing the CAN protocol according to Bosch Specification version 2.0B. The CAN protocol was designed to be used primarily as a vehicle serial data bus, meeting the specific requirements of this field: real- time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness and required bandwidth. Each FlexCAN module contains 64 message buffers.

Doc ID 15177 Rev 8 87/1740 The FlexCAN modules provide the following features:

Full Implementation of the CAN protocol specification, Version 2.0B – Standard data and remote frames – Extended data and remote frames – Zero to eight bytes data length – Programmable bit rate up to 1 Mbit/s
Content-related addressing
64 message buffers of zero to eight bytes data length
Individual Rx Mask Register per message buffer
Each message buffer configurable as Rx or Tx, all supporting standard and extended messages
Includes 1088 bytes of embedded memory for message buffer storage
Includes 256-byte memory for storing individual Rx mask registers
Full featured Rx FIFO with storage capacity for six frames and internal pointer handling
Powerful Rx FIFO ID filtering, capable of matching incoming IDs against 8 extended, 16 standard or 32 partial (8 bits) IDs, with individual masking capability
Selectable backwards compatibility with previous FlexCAN versions
Programmable clock source to the CAN Protocol Interface, either system clock or oscillator clock
Listen only mode capability
Programmable loop-back mode supporting self-test operation
3 programmable Mask Registers
Programmable transmit-first scheme: lowest ID, lowest buffer number or highest priority
Time Stamp based on 16-bit free-running timer
Global network time, synchronized by a specific message
Maskable interrupts
Warning interrupts when the Rx and Tx Error Counters reach 96
Independent of the transmission medium (an external transceiver is assumed)
Multi-master concept
High immunity to EMI
Short latency time due to an arbitration scheme for high-priority messages
Low power mode, with programmable wake-up on bus activity

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1.4.18 FlexRay

The SPC564A74xx, SPC564A80xx includes one dual-channel FlexRay module that implements the FlexRay Communications System Protocol Specification, Version 2.1 Rev A. Features include:

Single channel support
FlexRay bus data rates of 10 Mbit/s, 8 Mbit/s, 5 Mbit/s, and 2.5 Mbit/s supported
128 message buffers, each configurable as: – Receive message buffer – Single buffered transmit message buffer – Double buffered transmit message buffer (combines two single buffered message buffer)
2 independent receive FIFOs – 1 receive FIFO per channel – Up to 255 entries for each FIFO
ECC support

1.4.19 System timers

The system timers include two distinct types of system timer:

Periodic interrupts/triggers using the Periodic Interrupt Timer (PIT)
Operating system task monitors using the System Timer Module (STM) Periodic interrupt timer (PIT) The PIT provides five independent timer channels, capable of producing periodic interrupts and periodic triggers. The PIT has no external input or output pins and is intended to provide system ‘tick’ signals to the operating system, as well as periodic triggers for eQADC queues. Of the five channels in the PIT, four are clocked by the system clock and one is clocked by the crystal clock. This one channel is also referred to as Real-Time Interrupt (RTI) and is used to wake up the device from low power stop mode. The following features are implemented in the PIT:
5 independent timer channels
Each channel includes 32-bit wide down counter with automatic reload
4 channels clocked from system clock
1 channel clocked from crystal clock (wake-up timer)
Wake-up timer remains active when System STOP mode is entered; used to restart system clock after predefined time-out period
Each channel optionally able to generate an interrupt request or a trigger event (to trigger eQADC queues) when timer reaches zero System timer module (STM) The System Timer Module (STM) is designed to implement the software task monitor as defined by AUTOSAR (b). It consists of a single 32-bit counter, clocked by the system clock, b. AUTOSAR: AUTomotive Open System ARchitecture (see www.autosar.org)

Doc ID 15177 Rev 8 89/1740 and four independent timer comparators. These comparators produce a CPU interrupt when the timer exceeds the programmed value. The following features are implemented in the STM:

One 32-bit up counter with 8-bit prescaler
Four 32-bit compare channels
Independent interrupt source for each channel
Counter can be stopped in debug mode

1.4.20 Software watchdog timer (SWT)

The Software Watchdog Timer (SWT) is a second watchdog module to complement the standard Power Architecture watchdog integrated in the CPU core. The SWT is a 32-bit modulus counter, clocked by the system clock or the crystal clock, that can provide a system reset or interrupt request when the correct software key is not written within the required time window. The following features are implemented:

32-bit modulus counter
Clocked by system clock or crystal clock
Optional programmable watchdog window mode
Can optionally cause system reset or interrupt request on timeout
Reset by writing a software key to memory mapped register
Enabled out of reset
Configuration is protected by a software key or a write-once register

1.4.21 Cyclic redundancy check (CRC) module

The CRC computing unit is dedicated to the computation of CRC off-loading the CPU. The CRC features:

Support for CRC-16-CCITT (x25 protocol): –X 16 + X12 + X5 + 1
Support for CRC-32 (Ethernet protocol): 32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1
Zero wait states for each write/read operations to the CRC_CFG and CRC_INP registers at the maximum frequency

1.4.22 Error correction status module (ECSM)

The ECSM provides a myriad of miscellaneous control functions regarding program-visible information about the platform configuration and revision levels, a reset status register, a software watchdog timer, wakeup control for exiting sleep modes, and information on platform memory errors reported by error-correcting codes and/or generic access error information for certain processor cores.

90/1740 Doc ID 15177 Rev 8 The Error Correction Status Module supports a number of miscellaneous control functions for the platform. The ECSM includes these features:

Registers for capturing information on platform memory errors if error-correcting codes (ECC) are implemented
For test purposes, optional registers to specify the generation of double-bit memory errors are enabled on the SPC564A74xx, SPC564A80xx. The sources of the ECC errors are:
Flash
SRAM
Peripheral RAM (FlexRay, CAN, eTPU2 Parameter RAM)

1.4.23 External bus interface (EBI)

The SPC564A74xx, SPC564A80xx device features an external bus interface that is available in PBGA324 and calibration packages. The EBI supports operation at frequencies of system clock /1, /2 and /4, with a maximum frequency support of 80 MHz. Customers running the device at 120 MHz or 132 MHz will use the /2 divider, giving an EBI frequency of 60 MHz or 66 MHz. Customers running the device at 80 MHz will be able to use the /1 divider to have the EBI run at the full 80 MHz frequency. Features include:

1.8 V to 3.3 V ± 10% I/O (1.6 V to 3.6 V)
Memory controller with support for various memory types
16-bit data bus, up to 22-bit address bus
Pin muxing included to support 32-bit muxed bus
Selectable drive strength
Configurable bus speed modes
Bus monitor
Configurable wait states

1.4.24 Calibration EBI

The Calibration EBI controls data transfer across the crossbar switch to/from memories or peripherals attached to the calibration tool connector in the calibration address space. The Calibration EBI is only available in the calibration tool. Features include:

1.8 V to 3.3 V ± 10% I/O (1.6 V to 3.6 V)
Memory controller supports various memory types
16-bit data bus, up to 22-bit address bus
Pin muxing supports 32-bit muxed bus
Selectable drive strength
Configurable bus speed modes
Bus monitor
Configurable wait states

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1.4.25 Power management controller (PMC)

The power management controller contains circuitry to generate the internal 3.3 V supply and to control the regulation of 1.2 V supply with an external NPN ballast transistor. It also contains low voltage inhibit (LVI) and power-on reset (POR) circuits for the 1.2 V supply, the 3.3 V supply, the 3.3 V/5 V supply of the closest I/O segment (VDDEH1) and the 5 V supply of the regulators (VDDREG).

1.4.26 Nexus port controller

The NPC (Nexus Port Controller) block provides real-time Nexus Class3+ development support capabilities for the SPC564A74xx, SPC564A80xx Power Architecture-based MCU in compliance with the IEEE-ISTO 5001-2003 and 2010 standards. MDO port widths of 4 pins and 12 pins are available in all packages.

1.4.27 JTAG

The JTAGC (JTAG Controller) block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. Testing is performed via a boundary scan technique, as defined in the IEEE 1149.1-2001 standard. All data input to and output from the JTAGC block is communicated in serial format. The JTAGC block is compliant with the IEEE 1149.1-2001 standard and supports the following features:

IEEE 1149.1-2001 Test Access Port (TAP) interface 4 pins (TDI, TMS, TCK, and TDO)
A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions: – BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD, HIGHZ, CLAMP
A 5-bit instruction register that supports the additional following public instructions: – ACCESS_AUX_TAP_NPC – ACCESS_AUX_TAP_ONCE – ACCESS_AUX_TAP_eTPU – ACCESS_CENSOR
3 test data registers to support JTAG Boundary Scan mode – Bypass register – Boundary scan register – Device identification register
A TAP controller state machine that controls the operation of the data registers, instruction register and associated circuitry
Censorship Inhibit Register – 64-bit Censorship password register – If the external tool writes a 64-bit password that matches the Serial Boot password stored in the internal flash shadow row, Censorship is disabled until the next system reset.

1.4.28 Development Trigger Semaphore (DTS)

SPC564A74xx, SPC564A80xx devices include a system development feature, the Development Trigger Semaphore (DTS) module, that enables software to signal an external tool by driving a persistent (affected only by reset or an external tool) signal on an external

92/1740 Doc ID 15177 Rev 8 device pin. There is a variety of ways this module can be used, including as a component of an external real-time data acquisition system.

2 Memory Map

2.1 Introduction

SPC564A74xx, SPC564A80xx, including those that are reserved, are identified in the table. The addresses represent the physical addresses assigned to each IP block.

2.2 Memory map

Table 2. SPC564A74xx, SPC564A80xx memory map

Table 2. SPC564A74xx, SPC564A80xx memory map (continued)

3 Signal Description

This chapter describes signals that connect off chip. It includes a table of signal properties and the detailed descriptions of signals.

3.1 Signal Properties

Table 3. SPC564A74xx, SPC564A80xx signal properties

Table 3. SPC564A74xx, SPC564A80xx signal properties (continued)

For each pin in the table, each line in the Function column is a separate function of the pin. For all I/O pins the selection of primary pin function or secondary function or

GPIO is done in the SIU except where explicitly noted. See the Signal details table for a description of each signal.

The P/A/G column indicates the position a signal occupies in t he muxing order for a pin—Primary, Alternate 1, Alternate 2, Alternate 3, or GPIO. Signals are selected by
The Pad Configuration Register (PCR) PA field is used by software to select pin function.
Values in the PCR No. column refer to registers in the System Integration Unit (SIU). The actual register name is “SIU_PCR” suffixed by the PCR number. For example,

PCR[190] refers to the SIU register named SIU_PCR190.

The VDDE and VDDEH supply inputs are broken into segments. Each segment of slow I/O pins (VDDEH) may have a separate supply in the 3.3 V to 5.0 V range (-

10%/+5%). Each segment of fast I/O (VDDE) may have a separate supply in the 1.8 V to 3.3 V range (+/- 10%).

See Table 4 for details on pad types.

Doc ID 15177 Rev 8 127/1740 7. The Status During Reset pin is sampled after the internal PO R is negated. Prior to exiting POR, the signal has a high impedan ce. Terminology is O - output, I - input, Up - weak pull up enabled, Down - weak pull down enabled, Low - output driven low, High - output driven high. A dash for the function in this column denotes that both the input and output buffer are turned off. The signal name to the left or right of the slash indicates the pin is enabled. 8. Output only. 9. When used as ETRIG, this pin must be configured as an input. For GPIO it can be configured either as an input or output. 10. Maximum frequency is 50 kHz. 11. The SIU_PCR219 register is unusual in that it contro ls pads for two separate device pins: GPIO[219] and MCKO. Section , Pad Configuration Register 219 (SIU_PCR219)”. 12. Multivoltage pads are automatically confi gured in low swing mode when a JTAG or Nexus function is selected, otherwise they a re high swing. 13. On LQFP176 and LBGA208 packages, th is pin is tied low internally. 14. Nexus multivoltage pads default to 5 V operation until the Nexus module is enabled. 15. EVTO should be clamped to 3.3 V to prevent possible dam age to external tools that only support 3.3 V. 16. Do not connect pin directly to a power supply or ground. 17. This signal name is used to support legacy naming. 18. During and just after POR negates, internal pull resistors can be ena bled, resulting in as much as 4 mA of current draw. The pull resistors are disabled when the system clock propagates through the device. 19. For pins AN12-AN15, if the analog features are used the VDDEH7 input pins should be tied to VDDA because that segment must meet the VDDA specification to support analog input function. 20. Do not use VRC33 to dr ive external circuits. 21. VDDA0 and VDDA1 are short ed together internally in BGA packages. In the QFP package the two pads are double bonded on one pi n called VDDA. 22. VSSA0 and VSSA1 are shorted together internally in BGA packages. In the QFP package the two pads are double bonded on one pi n called VSSA. 23. VDDE2 and VDDE3 are shorted toge ther in all production packages. 24. VDDE2 and VDDE3 are shorted toge ther in all production packages. 25. VDDEH1A, VDDEH1B, and VDDEH1AB are short ed together in all production packages. The separation of the signal names is present to support legacy naming, however they should be considered as the same signal in this document. 26. VDDEH4, VDDEH4A, VDDEH4B, and VDDEH4AB ar e shorted together in all production package s. The separation of the signal names i s present to support legacy naming, however they should be consider ed as the same signal in this document. 27. VDDEH6, VDDEH6A, VDDEH6B, and VDDEH6AB ar e shorted together in all production package s. The separation of the signal names i s present to support legacy naming, however they should be consider ed as the same signal in this document.

Table 4. Pad types

Multivoltage pads are automatically configured in low swing mode when a

JTAG or Nexus function is selected, otherwise they are high swing.

VDDEH7 supply cannot be below 4.5 V when in low-swing mode.

3.2 Signal Details

Table 5. Signal details source based on the value driven on the PLLREF pin at reset. compatibility with previous devices . 0: External reference clock is selected. 0: External reference clock is selected. 1: XTAL oscillator mode is selected. If RSTCFG is 1, XTAL oscillator mode is selected.

another data beat following the current one. even if more than one write data beat is transferred. Table 5. Signal details (continued)

FCK eQADC eQADC free running clock for eQADC SSI. an external Analog Mux for expansion channels.

JCOMP JTAG Enables the JTAG TAP controller. TCK JTAG Clock input for the on-chip test logic. TDI JTAG Serial test instruction and data input for the on-chip test logic. TDO JTAG Serial test data output for the on-chip test logic. TMS JTAG Controls test mode operations for the on-chip test logic. watchpoint or breakpoint occurrence. which is used for timing of the MDO and MSEO signals. oscillator clock achieves stability and is then negated. to the Nexus read/write access registers.

initiate a FlexCAN or eSCI boot. cycles before the negation of the RSTOUT pin. 1:Weak pullup applied to eTPU and eMIOS pins at reset.

(SIU_EIISR) for more detail. configured using a dedicated SIU_PCR register. the device is in reset causes the reset cycle to start over. switch point of the input buffer logic of the VDDEH input pins. VIH specifications for the VDDEH input pins.

always 0, so PLLREF and BOOTCFG signals are used. RSTOUT pin. See Section 4.3.2: RSTOUT for details.

Do not connect pin directly to a power supply or ground.

Table 6. Power/ground segmentation

Do not use VRC33 to dr ive external circuits.

4 Resets

Not all packages have BOOTCFG[0]. In this case, BOOTCFG[0] is sampled as 0b0.

4.1 Reset sources

Power-on Reset
External Reset
Loss of Lock Reset
Loss of Clock Reset
Watchdog Timer/Debug Reset
JTAG Reset
Software System Reset
Software External Reset (resets external resources but not the device) All reset sources are processed by the reset controller, which monitors the reset input sources, and upon detection of a reset event, resets internal logic and controls the assertion of the RSTOUT pin. The Software External Reset only causes the RSTOUT pin to be asserted for a number of clock cycles determined by the PLL mode (refer to Section 4.3.2, RSTOUT), and does not reset the device. For all reset sources, the BOOTCFG[0:1] and PLLREF signals are used to determine the boot mode and configuration of the FMPLL, respectively. Table 7 shows the options for BOOTCFG[0:1] and Table 8 for PLLCFG[0:2]. Refer to 17, Frequency-modulated phase locked loop (FMPLL), for information on the FMPLL during reset.

Table 7. BOOTCFG options

This mode is only available in packages that have an EBI.

11 R e s e r v e d

Table 8. PLLREF options

0 Normal mode with external reference

1 Normal mode with crystal reference

138/1740 Doc ID 15177 Rev 8 The Reset Status Register (SIU_RSR) gives the source, or sources, of the last reset and indicates whether a glitch has occurred on the RESET pin. The SIU_RSR is updated for all reset sources except JTAG reset. All reset sources initiate execution of the Boot Assist Module (BAM) program with the exception of the Software External Reset. The Reset Configuration Half Word (RCHW) determines the MCU configuration after reset. The RCHW is stored in internal flash, or a default configuration is used. During reset, the RCHW is read from internal flash memory. The BOOTCFG[0:1] (c) pins are defined in Chapter 16: System Integration Unit (SIU). The BAM program reads the value of the BOOTCFG[0:1] pins from field SIU_RSR[BOOTCFG], then reads the RCHW from the specified location, and then uses the RCHW value to determine and execute the specified boot procedure. Note: the reset controller latches the value on the BOOTCFG input to the SIU four clock cycles prior to the negation of RSTOUT

4.2 Reset vector

The reset vector for this device is 0xFFFF_FFFC. This is a fixed location in the BAM. The BAM program executes after every internal reset. The BAM program determines where to branch after its execution completes based on the value on the BOOTCFG[0:1] pins. See the BAM chapter’s functional description for details on the BAM program operation and branch location to application software.

4.3 Reset pins

4.3.1 RESET

The RESET pin is an active low input. The RESET pin must be asserted by an external device during a power-on or whenever an external reset is required. The internal reset signal asserts only if the RESET pin asserts for 10 clock cycles. Assertion of the RESET pin while the reset state machine is already processing a reset causes the reset cycle to start over. The RESET pin has a glitch detector which detects spikes greater than two clocks in duration that fall below the switch point of the input buffer logic of the VDDEH input pins. The switch point lies between the maximum VIL and minimum VIH specifications for the VDDEH input pins. Figure 2 and Figure 3 show logic flows of the reset state machine on assertion of RESET

4.3.2 RSTOUT

The RSTOUT pin is an active low output that uses a push/pull configuration. The RSTOUT pin is driven to the low state by the MCU for all internal and external reset sources. Depending on the PLL configuration, External Reference or Crystal Mode, the RSTOUT pin is asserted after a delay defined in Table 9, plus four cycles for sampling of the configuration pins. c. BOOTCFG[0] is not available on all packages.

the value specified in Table 9.

4.4 FMPLL lock gating signal

4.5 Reset source descriptions

Figure 3. Figure 2 shows the reset flow for assertion of the RESET pin. Figure 3 shows the internal processing of reset for all reset sources. Table 9. Timing for reset sources

Figure 2. External reset flow diagram

Figure 3. Internal reset flow diagram

The clock count CNT depends on the reset source and type of clock reference. Please refer to Table 9.

142/1740 Doc ID 15177 Rev 8

4.5.1 Power-on reset (POR)

The internal power-on reset signal is asserted when either the supply voltages, nominally 3.3 V or 1.2 V or the RESET supply (VDDEH6a) fall below defined values. See the device data sheet for the threshold specifications of these voltages. The output signals from the power-on reset circuits are active low signals. All power-on reset output signals are combined into one POR signal at the 1.2 V level and input to the reset controller. Although assertion of the power-on reset signal causes reset, the RESET pin must be asserted during a power-on reset to guarantee proper operation of the MCU. The PLLREF pin determines the source of reference clock, either crystal or external, at the negation of RSTOUT. During the assertion of RSTOUT, the system clock will switch to the input specified by the PLLREF pin. The value on the PLLREF pin must be kept constant during reset to avoid transients in the system clock. See Section 17.2.3, Modes of operation, for more details. The signal on the WKPCFG pin determines whether weak pull up or pull down devices are enabled after reset on the eTPU and eMIOS pins. The WKPCFG pin is applied on the assertion of the internal reset signal (assertion of RSTOUT ). See Section 4.7.3, Reset weak pull up/down configuration, for more information. Once a power-on-reset is triggered, if the clock reference is the crystal (PLLREF = 1), then the clock to the whole chip, including the reset state machine, is kept frozen until the Clock Quality Monitor detects that the crystal oscillator has already stabilized. If the clock reference is external (PLLREF = 0) the clock is released to the system immediately. When the clock is stable and released to the chip, the reset controller counts a predetermined number of clock cycles (refer to Section 4.3.2, RSTOUT) before negating the RSTOUT pin. The WKPCFG and BOOTCFG[0:1] pins are sampled four clock cycles before the negation of RSTOUT , and the associated bits/fields are updated in the SIU_RSR. In addition, SIU_RSR[PORS] and SIU_RSR[ERS] are set, and all other reset status bits are cleared in the SIU_RSR.

4.5.2 External reset

When the reset controller detects assertion of the RESET pin, the internal reset signal and RSTOUT pin are asserted. The values on the WKPCFG pin and PLLCFG pins are applied at the assertion of the internal reset signal (assertion of RSTOUT). Once the RESET pin is negated and the FMPLL Loss of Lock reset request signal is negated, the reset controller waits for a predetermined number of clock cycles (refer to Section 4.3.2, RSTOUT). Once the clock count finishes, the reset configuration pins are latched. The reset controller then waits four clock cycles before negating RSTOUT , and the associated bits/fields are updated in the SIU_RSR. In addition, SIU_RSR[ERS] is set, and all other reset status bits in the SIU_RSR are cleared.

4.5.3 Loss of lock

A Loss of Lock Reset occurs when the FMPLL loses lock and the Loss of Lock Reset Enable (LOLRE) bit in the FMPLL Synthesizer Control Register (SYNCR) is set. The internal reset signal and RSTOUT pin are asserted. The value on the WKPCFG pin is applied at the assertion of the internal reset signal (assertion of RSTOUT), as is the PLLREF value. Once the FMPLL Loss of Lock reset request signal is negated, the reset controller waits for a predetermined number of clock cycles (refer to Section 4.3.2, RSTOUT). Once the clock count finishes, the WKPCFG and BOOTCFG[0:1] pins are sampled. The reset controller then waits four clock cycles before negating RSTOUT , and the

Doc ID 15177 Rev 8 143/1740 associated bits/fields are updated in the SIU_RSR. In addition, SIU_RSR[LLRS] is set, and all other reset status bits in the SIU_RSR are cleared. Refer to Section 17.5.3, Lock detection, for more information on loss of lock.

4.5.4 Loss of clock

A Loss of Clock Reset occurs when the Clock Quality Monitor Module (CQM) detects a failure in either the reference signal or FMPLL output, and the Loss of Clock Reset Enable (LOCRE) bit in the SYNCR is set. The internal reset signal and RSTOUT pin are asserted. The value on the WKPCFG pin is applied at the assertion of the internal reset signal (assertion of RSTOUT ), as is the PLLREF value. Once the Loss of Clock reset request signals is negated, the reset controller waits for a predetermined number of clock cycles (refer to Section 4.3.2, RSTOUT). Once the clock count finishes, the WKPCFG and BOOTCFG[0:1] pins are sampled. The reset controller then waits four clock cycles before negating RSTOUT , and the associated bits/fields are updated in the SIU_RSR. In addition, SIU_RSR[LCRS] is set, and all other reset status bits in the SIU_RSR are cleared. Refer to Section 17.5.3, Lock detection, for more information on loss of clock. The CQM module, when enabled, can generate either a system reset or an interrupt signal (refer to Section 17.5.4, Loss-of-clock detection, for details).

4.5.5 Core watchdog timer/debug reset

There are two watchdog timer resets: A core watchdog and a platform watchdog. A Core Watchdog Timer Reset occurs when the e200z4 core watchdog timer is enabled (the e200z4 core watchdog is counting core clocks, which is different than the peripheral/platform clocks), and a time-out occurs with the Enable Next Watchdog Timer (EWT) and Watchdog Timer Interrupt Status (WIS) bits set in the Timer Status Register, and with the Watchdog Reset Control (WRC) field in the Timer Control Register configured for a reset. SIU_RSR[WDRS] is also set when a debug reset command is issued from a debug tool. To determine whether SIU_RSR[WDRS] was set due to a Watchdog Timer or Debug Reset, see the WRS field in the e200z4 core Timer Status Register. The effect of a Watchdog Timer or Debug Reset request is the same for the reset controller. The internal reset signal and RSTOUT pin are asserted. The value on the WKPCFG pin is applied at the assertion of the internal reset signal (assertion of RSTOUT), as is the PLLREF value. Once the Watchdog Timer/Debug reset request is negated and the FMPLL Loss of Lock reset request signal is negated, the reset controller waits for a predetermined number of clock cycles (refer to Section 4.3.2, RSTOUT). Once the clock count finishes the reset configuration pins are sampled. The reset controller then waits four clock cycles before negating RSTOUT , and the associated bits/fields are updated in the SIU_RSR. In addition, SIU_RSR[WDRS] is set, and all other reset status bits in the SIU_RSR are cleared. Refer to the e200z4 Power Architecture  Core Reference Manual for descriptions of the Timer Status Register and Timer Control Register, as for more information on the core watchdog timer and debug operation.Refer to 20, Software Watchdog Timer (SWT), for more information on the platform watchdog.

4.5.6 JTAG reset

A system reset occurs when JTAG is enabled and either the EXTEST, CLAMP, or HIGHZ instructions are executed by the JTAG controller. The internal reset signal is asserted. The

144/1740 Doc ID 15177 Rev 8 state of the RSTOUT pin is determined by the JTAG instruction. The value on the WKPCFG pin is applied at the assertion of the internal reset signal, as is the PLLREF value. After the JTAG reset request is negated, the reset controller waits for a predetermined number of clock cycles (refer to Section 4.3.2, RSTOUT). Once the clock count finishes the WKPCFG and BOOTCFG[0:1] pins are sampled, and the associated bits/fields are updated in the SIU_RSR. The reset status bits in the SIU_RSR are unaffected. Refer to 36, JTAG Controller (JTAGC), for more information.

4.5.7 Software system reset

A Software System Reset is caused by a write to field SIU_SRCR[SSR]; see Section 16.6.5, System Reset Control Register (SIU_SRCR). A write of ‘1’ to SIU_SRCR[SSR] causes an internal reset of the MCU. The internal reset signal and RSTOUT pin are asserted. The value on the WKPCFG pin is applied at the assertion of the internal reset signal (assertion of RSTOUT ), as is the PLLREF value. SIU_SRCR[SSR] is automatically cleared and the reset controller waits for a predetermined number of clock cycles (refer to Section 4.3.2, RSTOUT). Once the clock count finishes the WKPCFG and BOOTCFG[0:1] pins are sampled. The reset controller then waits four clock cycles before negating RSTOUT, and the associated bits/fields are updated in the SIU_RSR. In addition, SIU_RSR[SSRS] is set, and all other reset status bits in the SIU_RSR are cleared.

4.5.8 Software external reset

A write of ‘1’ to field SIU_SRCR[SER] causes the external RSTOUT pin to be asserted for a predetermined number of clock cycles (refer to Section 4.3.2, RSTOUT). SIU_SRCR[SER] automatically clears after the clock counting expires. A Software External Reset does not cause a reset of the MCU, the BAM program is not executed, the PLLREF, BOOTCFG, and WKPCFG pins are not sampled. Field SIU_RSR[SERF] is set, but no other status bits are affected. SIU_RSR[SERF] is not automatically cleared and remains set until cleared by software or another reset besides the Software External Reset occurs. For a Software External Reset, the e200z4 core will continue to execute instructions, timers that are enabled will continue to operate, and interrupt requests will continue to be processed. The application must ensure that devices connected to RSTOUT are not accessed during a Software External Reset, and it must determine how to manage MCU resources when using the Software External Reset.

4.6 Reset registers in the SIU

The System Integration Unit (SIU) on this device includes two registers, SIU_RSR and SIU_SRCR, that affect the reset behavior of this device. See Chapter 16: System Integration Unit (SIU), for descriptions of these registers.

4.7 Reset configuration

4.7.1 Reset configuration half word (RCHW)

The Reset Configuration Half Word (RCHW) defines boot options and must be programmed in a choice of predefined locations in internal flash. The word at the word address boundary

passes control to the user application at this starting address. modes, the BAM attempts to read the RCHW from internal or external memory respectively. download protocol. Refer to the BAM Chapter for complete details. Table 10. RCHW location Figure 4. Reset Configuration Half Word Table 11. Reset Configuration Half Word (RCHW) field descriptions These bit values are ignored when the halfword is read. Program to 0 for future compatibility.

0 Disable software watchdog timer

1 Enable software watchdog timer after reset. The timeout period is 261,600 system clocks.

0 Disable core software watchdog timer

1 Enable core watchdog timer after reset. The timeout period is 2.5*2 17 system clocks.

The SWT clock source is directly from the crystal oscillator. The core WD is clocked by the PLL.
The core WD timeouts reported here correspond to the PLL settings after reset. Core WD timeouts will change as soon as the PLL is programmed with different multipliers.

4.7.2 Reset configuration timing

changes D_CS0 to a 16-bit port to fetch the RCHW from either 16- or 32-bit external memories. Then the BAM reconfigures the EBI as a 16- or 32-bit port, depending on this bit. instructions or as VLE instructions.

0 User code executes as classic Book E code

1 User code executes as VLE code

Table 12. Watchdog timeout periods

the RSTOUT pin and stored in the SIU_RSR. Figure 5. Reset configuration timing

4.7.3 Reset weak pull up/down configuration

treated as ‘1’ during POR assertion. are applied, but not latched.

The clock count CNT depends on the reset source and type of clock reference. Please refer to Table 9.

Operating Modes and Clocking RM0029 148/1740 Doc ID 15177 Rev 8

5 Operating Modes and Clocking

5.1 Overview

This section gives a brief overview of the operating modes of this device.

5.2 Modes of operation

5.2.1 Normal mode

Normal Mode is the functional mode of this device.

5.2.2 Debug mode

Debug Mode provides access to powerful debugging and development features of this device. The debug and development features are distributed between Nexus blocks in the e200z4 core, eDMA and the eTPU, and some of the peripheral modules. The Nexus debug and development features are described in Chapter 37: Nexus Port Controller (NPC). The peripheral blocks that implement Debug Mode are:

DSPI B, DSPI C, DSPI D
FlexCAN A, FlexCAN B, FlexCAN C
eMIOS
eQADC
eTPU (referenced as Halt State in Chapter 24: Enhanced Time Processing Unit (eTPU2)) See the “Modes of Operation” section of the individual module for a description of how the Debug Mode affects the behavior of the module.

5.2.3 Low power modes

This device can be configured such that the clock to some or all of the modules can be stopped to reduce the power consumption. A tiered approach towards clock gating is implemented. In the first tier (Module Disable mode) some modules can be configured to stop the clock to the non-memory mapped registers within the module. In the second tier (Module Halt mode) the clock to each of the modules, including the CPU, can be completely stopped. Module disable mode Module Disable Mode is a low-power mode supported by some of the modules on this device, in which the clock to the non-memory mapped registers within the module is gated- off. Table 14 lists the modules that support Module Disable Mode. The register and bit in each module that must be written to enter or exit this mode are also listed. See the “Modes of Operation” section of the individual module for a description of how the Module Disable Mode affects the behavior of the module.

RM0029 Operating Modes and Clocking Doc ID 15177 Rev 8 149/1740 Module halt mode Module Halt mode is a low power mode in which the clock to all registers within each module can be completely halted. The control of the clock gating is centralized in the SIU_HLT register, which has one control bit for each module to be halted. The CPU itself can also be halted. Standby mode In this mode, the power is removed from all functions except the standby RAM. Standby mode is entered by removing all power supplies except the one on the VSTBY pin. The device is recovered from the standby mode when powered again; see Chapter 4: Resets for more information.

5.3 Clock architecture

The following sections detail the SPC564A74xx, SPC564A80xx clocking architecture.

5.3.1 Overview

This section describes different sources for the system clocks. The SPC564A74xx, SPC564A80xx clocking architecture consists of the following:

On-chip MHz oscillator: Range (4–40 MHz)
Relaxation oscillator (RCOSC): 16 MHz
Phase-locked loop (PLL): VCO range (256–512 MHz)
PLLREF top level pin to control PLL reference
Clock quality monitor
System Clock Divider (SYSDIV) used to further reduce the system clock frequency
Register to control system clock source and programming of PLL parameter
Clock gating for individual modules controlled by either SIU_HLT register or module’s MDIS register bit

5.3.2 Block diagram

Figure 6. System clock diagram Figure 7. FMPLL

5.3.3 System clock sources

PLL disabled – MHz crystal oscillator with crystal as the reference – MHz crystal oscillator bypassed
PLL enabled – MHz crystal oscillator (with crystal as the reference) output used as PLL reference frequency – MHz crystal oscillator (bypassed) output used as PLL reference frequency 1 1 XTAL OSC FMPLLXTAL EXTAL PLLREF clkcfg[0] SYSDIV /2, /4, /8, /16 bypass_sysdiv siu_system_div[1:0] IDF PDODFNDIV Lock Control & Status Registers PHI CLKIN Clock Quality Monitor (CQM) loss of VCO loss of Reference system clock RCOSC PFD Charge pump Low Pass Filter VCO /NDIV /IDF CLKIN /ODF FMPLL PHI FM Controller PHI1

RM0029 Operating Modes and Clocking Doc ID 15177 Rev 8 151/1740 Upon Reset, the system clock source is the oscillator clock with either crystal as reference or bypassed based on the PLLREF pin value driven during system reset. Please note the following: 1. RCOSC is never used as a source of system clock. 2. PHI1 output from PLL is never used as a source of system clock. It is used as one of the clock sources for the FlexRay module. 3. See the FMPLL chapter for details on FMPLL operation. Support for 150 MHz system clock generation The oscillator and PLL support generation of a 150 MHz system clock while using the 40 MHz crystal required for FlexRay operation. A possible PLL configuration is shown below:

Input clock (crystal frequency): 40 MHz
EPREDIV/IDF divider = /8 (1–15 range supported)
EMFD/NDIV loop divider = 60 (32–96 supported)
VCO clock out = 300 MHz (256–512 MHz range supported)
ERFD/ODF output divider = /2 (/2, /4, /8, /16 supported)
SYSDIV divider = /1 (/1, /2, /4, /8, /16 supported)
System clock = 150 MHz Support for 100 MHz system clock generation The oscillator and PLL support generation of a 100 MHz system clock while using the 40 MHz crystal required fro FlexRay operation. A possible PLL configuration is shown below:
Input clock (crystal frequency): 40 MHz
EPREDIV/IDF divider = /8 (1–15 range supported)
EMFD/NDIV loop divider = 80 (32–96 supported)
VCO clock out = 400 MHz (256–512 MHz range supported)
ERFD/ODF output divider = /4 (/2, /4, /8, /16 supported)
SYSDIV divider = /1 (/1, /2, /4, /8, /16 supported)
System clock = 100 MHz Support for FlexRay operation The SPC564A74xx, SPC564A80xx MCU supports generation of the clock signals needed for the operation of the FlexRay module. Two options are supported for the generation of the FlexRay clock:
If the PLL is used with Frequency Modulation enabled, a 40 MHz crystal or external clock source must be used to supply the FlexRay clock.
If the PLL is configured to generate a 120 MHz system clock without Frequency Modulation, then the FlexRay module can be clocked from the system clock, allowing the use of other crystal frequencies. In this mode of operation, the VCO frequency would be 480 MHz (256–512 MHz VCO range supported) with the /4 output divider to achieve 120 MHz system clock. The VCO/6 (80 MHz) output from PLL(PHI1) would be selected as the clock source for FlexRay by configuration of the MCF[CLKSEL] control bit on the FlexRay module.

clock source ensures very low jitter on the CAN bus.

5.3.4 FMPLL modes of operation

available modes are specified in Table 13.

25 MHz to 125 MHz, unconnected from the system clock (since bypass is the default mode

Table 13. Clock Mode Selection

CLKCFG[1] is not writable to zero while CLKCFG[]=1.
The reset state of this bit is determined by the logical state applied to the PLLREF pin.

support circuitry, and short signal route from the MCU to the crystal. Figure 8. Bypass mode with crystal reference frequency modulation is not available. FMPLL_ESYNCR1[CLKCFG] as shown in Table 13.

Figure 9. Bypass mode with external reference route from the MCU to the crystal. divider. The system clock divider can be programmed by writing to SIU_SYSDIV[SYSDIV]. See Section 16.6.31, System Clock Register (SIU_SYSDIV) for details. frequency, the only division factor allowed in the system clock divider is divide-by-1.

the MDIS and halt bits affect the clocks to the modules. Figure 12. MDIS and halt clock gating NPC can be configured to disable the MCKO clock when there are no messages pending. The flash memory array can be disabled by writing to a bit in the flash memory map. d. For compatibility with legacy devices, the default value of MDIS bit is zero.

when the CPU comes out of reset. which modules are clock gated. signals are also captured in the SIU_HLTACK read-only register bits. negate the stop request signal after the required timing has been met. execution of the WAIT instruction. Table 14. MDIS support

The MDIS bit default reset value is zero.

Operating Modes and Clocking RM0029 158/1740 Doc ID 15177 Rev 8 Note: To gate the CPU clock you need to first program the SIU_HLT register bit assigned for CPU and then execute the CPU WAIT instruction. The CPU recovers from the halted state when one of the following events happens:

A valid pending interrupt is detected by the core
A request to enter debug mode is made by setting the DR bit in the OnCE control register (OCR)
The processor is in a debug session
A request to enable the CPU clock input has been made by setting the WKUP bit in the OCR When one of these events is detected, the CPU asserts an asynchronous output signal that re-enables the clock to the CPU so that it can exit the stopped state. Typically, the wake-up interrupt request will come from one of three sources: periodic interval timer (PIT) interrupt, external pin interrupt or CAN wake-up interrupt. When the clock to the CPU is gated, the clocks to the platform, the system RAM and the flash memory are also gated. The platform logic includes the cross-bar, peripheral bridge, DMA and flash memory controller. Note that the interrupt controller (INTC) and the SIU are not clock gated to allow interrupts to be used to recover the CPU halt state. Clock dividers The MCU provides five clock dividers:
System Clock Divider (SYSDIV)
External Bus Clock Divider (CLKOUT-DIV)
Nexus Message Clock Divider (MCKO-DIV)
Engineering Clock Divider (ENGDIV)
FlexCAN clock divider (CAN2:1) System Clock Divider (SYSDIV) The system clock divider is placed right at the output of the system clock mux (selection between FMPLL and the crystal clock) and before the clock is used by any other circuits, including the other clock dividers. It affects the clock in both normal mode and bypass mode. The system clock divider can be programmed to divide by 1, 2, 4, 8, or 16 depending on the values of fields BYPASS and SYSCLKDIV in the SIU_SYSDIV register. SIU_SYSDIV[BYPASS] determines whether or not the system clock divider is bypassed. The SIU_SYSDIV[BYPASS] reset value ‘1’ causes the system clock divider to be bypassed and results in a divide-by-1 reset configuration of the system clock divider. Only if the SIU_SYSDIV[BYPASS] value is ‘0’ can field SIU_SYSDIV[SYSCLKDIV] be programmed to divide by 2, 4, 8, or 16. External Bus Clock (CLKOUT) The external bus clock (CLKOUT) divider can be programmed to divide the system clock by one, two or four based on the settings of the EBDF field in the SIU external clock control register (SIU_ECCR). The reset value of SIU_ECCR[EBDF] selects a CLKOUT frequency of one half of the system clock frequency. The EBI supports gating of the CLKOUT signal when there are no external bus accesses in progress. The hold time for external bus pins can be changed by writing to SIU_ECCR[EBTS] (external bus tap select bit).

RM0029 Operating Modes and Clocking Doc ID 15177 Rev 8 159/1740 Note: The CLKOUT pin is only available in the 324-pin package. Nexus Message Clock (MCKO) The Nexus message clock (MCKO) divider can be programmed to divide the system clock by two, four or eight based on the MCKO_DIV field in the port configuration register (PCR) in the Nexus port controller (NPC). The reset value of NPC_PCR[MCKO_DIV] selects an MCKO clock frequency one half of the system clock frequency. The MCKO divider is configured by writing to the NPC through the JTAG port. Engineering Clock Divider (ENGDIV) The engineering clock divider (ENGDIV) can be programmed to divide system clock. This clock is mainly used to clock some ASIC devices integrated on the board. There is no timing relation of this clock with respect to any other clock in the design. Refer to Section 16.6.26: External Clock Control Register (SIU_ECCR) for ENGDIV register bit programming. FlexCAN Clock Divider (CAN2:1) The FlexCAN module has the ability to run from the system clock. It is possible, at the input to the FlexCAN module, to perform a divide-by-1 or a divide-by-2 division of the system clock. This FlexCAN system clock divider can be programmed by configuring the FlexCAN2:1 mode bit (field SIU_SYSDIV[CAN_SRC]). The reset value is to divide-by-1. The FlexCAN module does not support a divide-by-1 of the system clock above a certain frequency, defined in the devicedatasheet. When running at maximum system frequency this setting will have to be adjusted from its default value.

Device Performance Optimization RM0029 160/1740 Doc ID 15177 Rev 8

6 Device Performance Optimization

6.1 Introduction

The SPC564A74xx, SPC564A80xx contains several features that can influence the overall level of performance provided by the device. Some of these features may be initialized upon negation of reset either by a software program called the Boot Assist Module (BAM), by a hardware state machine or by appropriate default register settings. Although the device exits the reset state into a functional state it does not necessarily have the default optimum performance settings for any given application. This chapter provides guidance for users to fully optimize their application to achieve the highest possible performance from the SPC564A74xx, SPC564A80xx. It provides a description of the areas that should be focused on when optimizing an application for performance by describing the features and recommending settings to be applied. It focuses on hardware configurations although certain aspects of the application software such as compiler settings and optimizations will be discussed.

6.2 Features

The SPC564A74xx, SPC564A80xx has the following hardware features that can be configured to impact the overall performance of the device:

Branch Prediction – Branch Target Buffer – Branch Prediction Control
Frequency-modulated PLL
Flash Bus Interface Unit – Flash access wait state and address pipelining control – Flash instruction prefetching – Flash data prefetching
Crossbar switch
System Cache – Instruction Cache
Memory Management Unit Further application level features can impact the application performance:
Hardware Single Precision Floating point
Signal Processing Extension (SPE-APU)
Variable Length Encoding (VLE)
Compiler optimizations

RM0029 Device Performance Optimization Doc ID 15177 Rev 8 161/1740 Further factors that impact the overall application performance are the use of the intelligent peripherals:

Use of DMA rather than CPU to transfer data efficiently
Use of DMA service requests rather than CPU interrupts to avoid software polling
Off-loading tasks from the CPU to the eTPU2 or eDMA
Careful allocation of cache usage for code and data ranges, particularly when using with external memories. Different items in this list will have different performance impacts in a real system. Features like the system cache, the FMPLL and the flash access times tend to provide the most significant performance impacts in terms of hardware settings. The subsequent sections in this chapter describe how to configure and use these features.

6.3 Configuring hardware features

6.3.1 Branch target buffer (BTB)

Description

To resolve branch instructions and improve the accuracy of branch predictions the e200z4 core implements a dynamic branch prediction mechanism using a branch target buffer (BTB), a fully associative address cache of branch target addresses. Its purpose is to accelerate the execution of software loops with some potential change of flow within the loop body. In addition, the BTB on the e200z4 has a subroutine call stack that speeds up indirect branches. Recommended configuration By default, this BTB is disabled following negation of reset. It is controlled by the Branch Unit Control and Status Register (BUCSR). The BTB’s contents should be flushed and invalidated by writing BUCSR[BBFI] = 1, and it may be enabled by subsequently writing BUCSR[BPEN] = 1. Additional control is available in BUCSR[BPRED] and BUCSR[BALLOC] to control whether forward or backward branches (or both) are candidates for entry into the BTB, and thus for branch prediction. By default the BUCSR[BPRED] and BUCSR[BALLOC] fields are set to 0b00, which enables forward and backward branch prediction. It is recommended to not disable branch prediction although for extremely fine tuning of a given application the optimum setting of BUCSR[BPRED] and BUCSR[BALLOC] should be assessed. Figure 13. Branch Unit Control and Status Register (BUCSR)

Device Performance Optimization RM0029 162/1740 Doc ID 15177 Rev 8 Further details of the BUCSR can be found in the e200z4 Power Architecture® Core Reference Manual.

6.3.2 Frequency-modulated PLL

The frequency-modulated phase-locked loop (FMPLL) allows the user to generate high speed system clocks from a crystal oscillator or external clock generator. Further, the FMPLL supports programmable frequency modulation of the system clock. This module is typically configured early in the initialization code to ensure satisfactory performance levels are achieved. Recommended configuration The default operating frequency of the SPC564A74xx, SPC564A80xx device is 2 to 3 times the crystal reference frequency depending on the state of the PLL configuration pins as reset negates. Typically, the system frequency is increased shortly after reset negates to provide acceptable performance. 17, Frequency-modulated phase locked loop (FMPLL), Table 15. BUCSR field descriptions Note: BBFI is always read as 0. 00: Branch Target Buffer allocation for all branches is enabled. 01: Branch Target Buffer allocation is disabled for backward branches. 10: Branch Target Buffer allocation is disabled for forward branches. 11: Branch Target Buffer allocation is disabled for both branch directions. field is still used to indicate forward/backward, even though the branch is absolute. 00: Branch predicted taken on BTB miss for all branches. 01: Branch predicted taken on BTB miss only for forward branches. 10: Branch predicted taken on BTB miss only for backward branches. 11: Branch predicted not taken on BTB miss for both branch directions. setting BPRED to a non-default value may result in improved performance. 0: BTB prediction disabled. No hits are generated from the BTB and no new entries are allocated. Entries are not automatically invalidated when BPEN is cleared; BBFI controls entry invalidation. 1: BTB prediction enabled (enables BTB to predict branches).

RM0029 Device Performance Optimization Doc ID 15177 Rev 8 163/1740 provides details on how the frequency-modulated phase-locked loop should be initialized in an application. The maximum frequency of operation for this device is specified in the device data sheet. System performance cannot be linearly extrapolated with system frequency, as is often the expectation. It is due to the insertion of additional Flash wait states as system frequency increases that system performance does not scale linearly. Take care to ensure that the correct internal and/or external Flash configuration is chosen for the selected system frequency. The specific flash access times to be applied are detailed in Section , Bus Interface Unit Configuration Register (BIUCR).

6.3.3 Flash bus interface unit

The Flash Bus Interface Unit (FBIU) interfaces the system bus to the Flash memory array controller. The FBIU contains prefetch buffers and a prefetch controller which, if enabled, speculatively prefetches sequential lines of data from the Flash array into the buffer. Prefetch buffer hits allow zero-wait state responses. The Flash Bus Interface Configuration Registers (BIUCRx) control access to the internal Flash array. Its settings define the number of cycles required to access the array, access times, and how the prefetch buffering scheme operates. Following negation of reset and execution of the BAM, the instruction and data prefetching is disabled, and the number of cycles required to access the internal Flash array is set to its maximum value of fifteen additional wait states. Recommended configuration As the operating frequency of the device is set by configuring the FMPLL (see Section 6.3.2, Frequency-modulated PLL), the number of cycles required to access the internal array should be configured accordingly. Note that the Flash BIUCRx registers cannot be altered by code executing from the Flash array. Code for configuring the Flash should be executed from a separate memory array i.e copied to and executed from system RAM. Section , Bus Interface Unit Configuration Register (BIUCR), documents the register fields used to configure flash wait state settings. The “Platform flash controller electrical characteristics” section of the device data sheet contains the specific values for the flash wait state settings for a given operating frequency. This also provides recommendations for the prefetch buffer settings. Note that the BIUCRx settings may vary between revisions of the SPC564A74xx, SPC564A80xx.

6.3.4 Crossbar switch

The multi-port crossbar switch (XBAR) supports simultaneous connections between master ports and slave ports. The XBAR allows for concurrent transactions to occur from any master port to any slave port. If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher priority master and grants it ownership of the slave port. All other masters requesting that slave port are stalled until the higher priority master completes its transactions. By default, requesting masters are granted access based on a fixed priority. A round-robin priority mode also is available.

Device Performance Optimization RM0029 164/1740 Doc ID 15177 Rev 8 The main goal of the XBAR is to increase overall system performance by allowing multiple masters to communicate concurrently with multiple slaves. In order to maximize data throughput it is essential to keep arbitration delays to a minimum. The configuration of the crossbar can have implications for the performance of a system and particular care should be taken when assigning master priorities in a fixed priority application. Further, by correctly parking saves on relevant masters the initial access times to the slaves can be minimized by negating any initial arbitration penalties. Recommended configuration The specific settings for a given situation are application dependent and thus should be assessed by the user. However, some general guidelines are available. Optimal XBAR settings are application dependent, but in e200z4/7 (Harvard configuration) based devices assigning the CPU data bus to have highest priority and parking the slave port associated with system RAM on this master generally provides the best overall performance. To reconfigure the XBAR as described on the SPC564A74xx, SPC564A80xx, write the following registers: 1. XBAR_SGPCR2 = 0x0000_0001. This parks slave 2 (internal SRAM) on master port 1 (CPU data bus). 2. Write XBAR_MPR0 = 0x5432_0001. This sets slave port 0 (Flash) to give the master port 1 (CPU data bus) highest priority. On the e200z4 based devices it may also be beneficial to assign the eDMA to have highest priority for the Flash slave port depending upon the application. More details of the XBAR register configuration can be found in Section 9.2, XBAR registers.

6.3.5 Cache

The SPC564A74xx, SPC564A80xx provides an 8 KB Instruction, 2-way or 4-way set- associative, Harvard cache design with a 32-byte line size. The cache is disabled by default when reset is negated. The cache improves system performance by providing low-latency instructions to the e200z4 instruction pipelines, which decouples processor performance from system memory performance. There are several stages to enabling the cache. Not only does the cache itself have to be invalidated then enabled, but memory regions upon which it can operate must be configured in the MMU to permit cache access. Recommended configuration The exact usage of cache is application dependent but some general guidelines for using cache to improve performance in a typical application are listed below:

Enable instruction cache for all internal and external memories that code is being executed from.
Consider locking critical performance routines in cache.

the cache (by setting L1CSR1[ICE]). configuration registers, refer to the e200z4 Power Architecture® Core Reference Manual. Figure 14. L1 Cache Control and Status Register 1 (L1CSR1) Table 16. L1CSR1 field descriptions

0 The cache is organized as 64 sets and 2 ways

1 The cache is organized as 32 sets and 4 ways

software writing 0 to this bit location. ICINV is set to ‘1’ for proper operation of the cache.

Device Performance Optimization RM0029 166/1740 Doc ID 15177 Rev 8 Note that configuration of the cache has to be performed in conjunction with configuration of the Memory Management unit. Refer to Section 6.3.6, Memory management unit (MMU).

6.3.6 Memory management unit (MMU)

The Memory Management Unit is a 32-bit Power Architecture compliant implementation which provides functionality that includes address translation and application of access attributes to memory ranges defined in Translation Lookaside Buffer entries. Although the MMU does not directly impact performance, it is within the MMU that memory regions are configured to permit the use of system cache to improve performance and Variable Length Encoding (VLE) to enhance code density. Thus it is essential that the MMU is correctly configured to ensure optimal application performance is achieved. Recommended configuration The core uses MMU Assist Registers (MASx) which are special purpose registers to facilitate reading, writing and searching the Translation Lookaside Buffer (TLB) entries. These MAS registers are software managed by tlbre, tlbwe, tlbsx, tlbsync, and tlbivax instructions. Refer to the core reference manual for full details of the MMU and its configurations. There are several MMU Assist Register registers (MAS0–3) that require configuring. Details of these are provided in the e200z4 Power Architecture® Core Reference Manual. Specifically, the MAS2 register contains the fields to control whether a specified memory region described by the valid TLB Entry is cache inhibited or whether VLE encoding is valid. ICE Instruction Cache Enable 0: Cache is disabled 1: Cache is enabled When disabled, cache lookups are not performed for instruction accesses. Other L1CSR0 cache control operations are still available. Table 16. L1CSR1 field descriptions (continued) Figure 15. MMU Assist Register 2 (MAS2) Table 17. MAS2 field descriptions

6.4 Application software

6.4.1 Compiler optimizations

performance and minimized code size.

Optimized for small code size
Optimized for high performance
A trade-off between code size and performance Although this is an extreme example, it highlights how significant the role of the compiler and linker is in determining the overall performance of an application. W Write-through required I Cache inhibited 0: This page is considered cacheable 1: This page is considered cache-inhibited M Memory coherence required G Guarded E Endianness

Table 17. MAS2 field descriptions (continued)

Figure 16. Influence of compiler settings on application performance and code size device that uses a standard commercial compiler. The compiler optimizations do not necessarily have to be applied to the entire application. for usage guidelines on Small Data Areas.

6.4.2 Signal processing extension

6.4.3 Hardware single precision floating point

correct compiler options, the single precision floating point instructions may be used. Section 6.4.2, Signal processing extension for register details.

6.4.4 Variable length encoding

Figure 17. Machine State Register (MSR) Table 18. MSR field descriptions 1: Execution of SPE APU vector instructions is enabled.

Device Performance Optimization RM0029 170/1740 Doc ID 15177 Rev 8 1. Select the appropriate compiler target and option to generate VLE code. 2. Configure the Memory Management Unit (MMU) to specify VLE attributes for the relevant MMU pages. Refer to the register description in Section 6.3.6, Memory management unit (MMU). VLE-enabled cores run both Power Architecture and VLE instruction encodings on a page by page basis, with pages defined by the MMU. The reduction is code size is typically between 25% and 30%.

6.5 Peripherals and genera l application guidelines

Optimizing the device configuration and compiler setup is only one part of optimizing an entire application. Correct use of the peripherals can also dramatically improve overall system performance. In particular, use of the interrupt controller, the enhanced Direct Memory Access (eDMA), and intelligent peripherals such as the Enhanced Timer Processing unit (eTPU2), can off-load significant work from the CPU. For example, eDMA may be used to shift data to avoid unnecessary CPU loading. Most peripheral modules can generate eDMA requests to trigger data transfers. An example of a typical application is to use the eDMA to pass conversion commands to the analog to digital converter (ADC) ,while maintaining circular buffers results of the ADC in the system RAM, with no core intervention. Section 6.6, Performance optimization checklist provides several system level examples of how to optimize an application.

6.6 Performance optimization checklist

Table 19. Performance optimization checklist—Part 1. Hardware configuration BIUCR settings for FMPLL frequency ranges. Enable prefetching for instructions. Algorithm BIUCR2[LBCFG] Allocate buffers to data and/or instructions. Fine tune for specific applications. optimize for Harvard architecture. by setting MMU TLB attributes. Table 20. Performance optimization checklist—Part 2. Software configuration critical functions using SPE assembly code. take advantage of the VLE-APU.

Table 21. Performance optimization checklist—Pa rt 3. Peripherals and general application – Create circular buffers so that ADC results can be stored in RAM with no core overhead. Shift loading from the CPU to the eTPU2 whenever possible. – The eTPU2 can provide effective CPU off-loading for time and angle based operations. – The eTPU2 can trigger the ADC directly with no need for CPU interruption. Avoid software polling and allow peripherals to trigger interrupts or request eDMA servicing. – Use hardware instead of software vectored interrupts to reduce latency. – Trigger eDMA requests rather than interrupting the CPU to move data/results. Configure the external memory interface. – Enable bursting on the external bus. – Reduce external bus wait states from default maximum settings. – Place time critical functions in internal memory. – Small, but frequently executed routines can be considered as candidates to be locked in cache.

Doc ID 15177 Rev 8 173/1740 7 e200z4 Core This chapter contains an overview of the e200z4 processor core integrated in SPC564A74xx, SPC564A80xx devices.For detailed information see the publication e200z4 Power Architecture core reference manual. Note: There are two differences between the processor core in SPC564A74xx, SPC564A80xx devices and the e200z4 documented in the core reference manual. SPC564A74xx, SPC564A80xx devices feature a e200z448n3 core with 8 KB of instruction cache (vs. 4 KB) and 24 MMU entries (vs. 16).

7.1 Overview

The microcontroller’s cost-efficient e200z4 host processor core is built on the Power Architecture technology and designed specifically for embedded applications. The e200z4 is a dual-issue, 32-bit Power Architecture compliant design with 64-bit general purpose registers (GPRs). Power Architecture floating-point instructions are not supported by this core in hardware, but are trapped and may be emulated by software. An Embedded Floating-point (EFPU) APU is provided to support real-time single-precision embedded numerics operations using the general-purpose registers. A Signal Processing Extension (SPE) APU is provided to support real-time SIMD fixed point and single-precision, embedded numerics operations using the general-purpose registers. All arithmetic instructions that execute in the core operate on data in the general purpose registers (GPRs). The GPRs have been extended to 64-bits in order to support vector instructions defined by the SPE APU. These instructions operate on a vector pair of 16-bit or 32-bit data types, and deliver vector and scalar results. In addition to the base Power Architecture instruction set support, the e200z4 core also implements the VLE (variable-length encoding) technology, providing improved code density. The e200z4 processor integrates a pair of integer execution units, a branch control unit, instruction fetch unit and load/store unit, and a multi-ported register file capable of sustaining six read and three write operations per clock. Most integer instructions execute in a single clock cycle. Branch target prefetching is performed by the branch unit to allow single-cycle branches in many cases. The e200z4 contains an 8 KB Instruction Cache as well as a Memory Management Unit. A Nexus Class 3 module is also integrated.

174/1740 Doc ID 15177 Rev 8

7.2 Features

Features of the e200z4 core include:

Dual issue, 32-bit Power Architecture compliant CPU
Implements the VLE APU for reduced code footprint
In-order execution and retirement
Precise exception handling
Branch processing unit – Dedicated branch address calculation adder – Branch target prefetching using 8-entry BTB
Supports independent instruction and data accesses to different memory subsystems, such as SRAM and Flash memory via independent Instruction and Data BIUs
Load/store unit – 2 cycle load latency – Fully pipelined – Big and Little endian support – Misaligned access support
64-bit General Purpose Register file
64-bit Instruction bus, 64-bit Data bus
Memory Management Unit (MMU) with 24-entry fully-associative TLB and multiple page size support
8 KB, 2-way or 4-way Set Associative Instruction Cache
Signal Processing Extension (SPE1.1) APU supporting SIMD fixed-point operations using the 64-bit General Purpose Register file.
Embedded Floating-Point (EFP2) APU supporting scalar and vector SIMD single- precision floating-point operations, using the 64-bit General Purpose Register file.
Nexus Class 3 real-time Development Unit
Power management – Power saving mode: WAIT
Process ID manipulation for the MMU using an external tool

7.3 Microarchitecture summary

The e200z4 utilizes a five-stage pipeline for instruction execution. These stages are:

Instruction Fetch (stage 1)
Instruction Decode/Register file Read/Effective Address Calculation (stage 2)
Execute 0/Memory Access 0 (stage 3)
Execute 1/Memory Access 1 (stage 4)
Register Writeback (stage 5) The stages operate in an overlapped fashion, allowing single clock instruction execution for most instructions.

Doc ID 15177 Rev 8 175/1740 The integer execution unit consists of a 32-bit Arithmetic Unit (AU), a Logic Unit (LU), a 32- bit Barrel shifter (Shifter), a Mask-Insertion Unit (MIU), a Condition Register manipulation Unit (CRU), a Count-Leading-Zeros unit (CLZ), a 32x32 Hardware Multiplier array, and result feed-forward hardware. Integer EU1 also supports hardware division. Most arithmetic and logical operations are executed in a single cycle with the exception of multiply, which is implemented with a 2-cycle pipelined hardware array, and the divide instructions. A Count-Leading-Zeros unit operates in a single clock cycle. The Instruction Unit contains a PC incrementer and dedicated Branch Address adders to minimize delays during change of flow operations. Sequential prefetching is performed to ensure a supply of instructions into the execution pipeline. Branch target prefetching using the BTB is performed to accelerate taken branches. Prefetched instructions are placed into an 8-entry instruction buffer, with each entry capable of holding a single 32-bit instruction or a pair of 16-bit instructions. Branch target addresses are calculated in parallel with branch instruction decode. Conditional branches, which are not taken execute in a single clock. Branches with successful BTB target prefetching have an effective execution time of one clock if correctly predicted. Memory load and store operations are provided for byte, halfword, word (32-bit), and doubleword data with automatic zero or sign extension of byte and halfword load data as well as optional byte reversal of data. These instructions can be pipelined to allow effective single cycle throughput. Load and store multiple word instructions allow low overhead context save and restore operations. The load/store unit contains a dedicated effective address adder to allow effective address generation to be optimized. There is a single load- to-use bubble for load instructions. The Condition Register unit supports the condition register (CR) and condition register operations defined by the Power Architecture technology. The condition register consists of eight 4-bit fields that reflect the results of certain operations, such as move, integer and floating-point compare, arithmetic, and logical instructions, and provides a mechanism for testing and branching. Vectored and autovectored interrupts are supported by the CPU. Vectored interrupt support is provided to allow multiple interrupt sources to have unique interrupt handlers invoked with no software overhead. The SPE APU supports vector instructions operating on 16 and 32-bit fixed-point data types, as well as 32-bit IEEE-754 single-precision floating-point formats, and supports single- precision floating-point operations in a pipelined fashion. The 64-bit general purpose register file is used for source and destination operands, and there is a unified storage model for single-precision floating-point data types of 32-bits and the normal integer type. Low latency fixed-point and floating-point add, subtract, multiply, multiply-add, multiply-sub, divide, compare, and conversion operations are provided, and most operations can be pipelined.

Figure 18. e200z4 block diagram

7.3.1 Instruction unit features

64-bit path to cache supports fetching of two 32-bit instruction per clock
Instruction buffer holds up to eight 32-bit instructions
Dedicated PC incrementer supporting instruction prefetches
Branch unit with dedicated branch address adder, and branch lookahead logic (BTB) supporting single cycle execution of successfully predicted branches CPU CONTROL LOGIC LOAD/ DATA MEMORY MANAGEMENT UNIT ADDRESS STORE UNIT INSTRUCTION UNIT BRANCH UNIT PC UNIT INSTRUCTION BUFFER GPRCRSPR MULTIPLY UNITS SPE UNIT DATA BUS INTERFACE UNIT CONTROL 32 64 N EXTENDED FUNCTIONAL CONTROL INST DATA OnCE/NEXUS CONTROL LOGIC UNIT INTERFACE INTERFACE CONTROL DATA (MTSPR/MFSPR) INTEGER EXECUTION UNITS EXTERNAL SPR CTR XER LR DATA ADDRESS INSTRUCTION BUS INTERFACE UNIT CONTROL 3264N INSTRUCTION CACHE

Doc ID 15177 Rev 8 177/1740

7.3.2 Integer unit features

The e200z4 integer units support single cycle execution of most integer instructions:

32-bit AU for arithmetic and comparison operations
32-bit LU for logical operations
32-bit priority encoder for count leading zero’s function
32-bit single cycle barrel shifter for static shifts and rotates
32-bit mask unit for data masking and insertion
Divider logic for signed and unsigned divide in <=14 clocks with minimized execution timing (EU1 only)
Pipelined 32x32 hardware multiplier array supports 32x32->32 multiply with 2 clock latency, 1 clock throughput

7.3.3 Load/Store unit features

The e200z4 load/store unit supports load, store, and the load multiple / store multiple instructions:

32-bit effective address adder for data memory address calculations
Pipelined operation supports throughput of one load or store operation per cycle
Dedicated 64-bit interface to memory supports saving and restoring of up to two registers per cycle for load multiple and store multiple word instructions

7.3.4 Cache features

The features of the e200z4 Cache are as follows:

8 KB, 2- or 4-way configurable set-associative Instruction Cache
Linefill Buffer
32-bit address bus plus attributes and control
Supports cache line locking
Supports Way allocation
Supports Tag and Data Parity
Supports Tag and Data Double Error Detection
Correction/Auto-invalidation capability

7.3.5 MMU features

The features of the MMU are as follows:

Virtual Memory support
32-bit Virtual and Physical Addresses
8-bit Process Identifier
24-entry fully-associative TLB
Per-entry multiple page size support from 1 Kbyte to 4 Gbyte
Entry Flush Protection
Process ID manipulation for the MMU using an external tool

178/1740 Doc ID 15177 Rev 8 7.3.6 e200z4 system bus features The features of the e200z4 System Bus interface are as follows:

Independent Instruction and Data buses
32-bit address bus, 64-bit data bus, plus attributes and control
Data interface provides separate unidirectional 64-bit read and write data buses

7.3.7 Nexus 3 features

The Nexus 3 module is compliant with Class 3 of the IEEE-ISTO 5001™ - 2003 standard, with certain additional Class 4 features available. The following features are implemented:

Program Trace via Branch Trace Messaging (BTM). Branch trace messaging displays program flow discontinuities (direct and indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires between the discontinuities. Thus, static code may be traced.
Data Trace via Data Write Messaging (DWM) and Data Read Messaging (DRM). This provides the capability for the development tool to trace reads and/or writes to selected internal memory resources.
Ownership Trace via Ownership Trace Messaging (OTM). OTM facilitates ownership trace by providing visibility of which process ID or operating system task is activated. An Ownership Trace Message is transmitted when a new process/task is activated, allowing the development tool to trace ownership flow.
Run-time access to the processor memory map via the JTAG port. This allows for enhanced download/upload capabilities.
Watchpoint Messaging via the auxiliary interface.
Watchpoint Trigger enable of Program and/or Data Trace Messaging.
Data Acquisition Messaging (DQM) allows code to be instrumented to export customized information to the Nexus Auxiliary Output Port.
Auxiliary interface for higher data input/output.
Registers for Program Trace, Data Trace, Ownership Trace, Data Acquisition, and Watchpoint Trigger control.
All features controllable and configurable via the JTAG port.

8 Enhanced Direct Memory Access Controller (eDMA)

8.1 Introduction

an SRAM-based memory containing the transfer control descriptors (TCD) for the channels.

8.1.1 Block diagram

Figure 19 shows a simplified block diagram of the eDMA. Figure 19. eDMA block diagram

Enhanced Direct Memory Access Controller (eDMA) RM0029 180/1740 Doc ID 15177 Rev 8

8.1.2 Features

The eDMA has these major features:

All data movement via dual-address transfers: read from source, write to destination – Programmable source, destination addresses, transfer size, and support for enhanced addressing modes
Both 32- and 64-channel implementation performs complex data transfers with minimal intervention from a host processor – 32 bytes of data registers, used as temporary storage to support burst transfers (refer to SSIZE bit) – Connections to the crossbar switch for bus mastering the data movement
Transfer control descriptor organized to support two-deep, nested transfer operations – An inner data transfer loop defined by a minor byte transfer count – An outer data transfer loop defined by a major iteration count
Channel activation via 1 of 3 methods: – Explicit software initiation – Initiation via a channel-to-channel linking mechanism for continuous transfers – Peripheral-paced hardware requests (one per channel) All three methods require one activation per execution of the minor loop
Support for fixed-priority and round-robin channel arbitration
Support for complex data structures
Support to cancel transfers via software
Channel completion reported via optional interrupt requests – 1 interrupt per channel, optionally asserted at completion of major iteration count – Error terminations are optionally enabled per channel and logically summed together to form a single error interrupt (32-channel eDMA) or two error interrupts (64-channel eDMA).
Support for scatter-gather DMA processing
Support for complex data structures
Any channel can be programmed to be suspended by a higher priority channel’s activation, before completion of a minor loop.

8.1.3 Modes of operation

There are two main operating modes of eDMA: normal mode and debug mode. These modes are briefly described in this section. Normal mode In normal mode, the eDMA is used to transfer data between a source and a destination. The source and destination can be a memory block or an I/O block capable of operation with the eDMA. Debug mode In debug mode, the eDMA does not accept new transfer requests when its debug input signal is asserted. If the signal is asserted during transfer of a block of data described by a

completion of the minor loop.

8.2 External signal description

The eDMA has no external signals.

8.3 Memory map and registers

This section provides a detailed description of all eDMA registers.

8.3.1 Module memory map

in one of the eDMAs, the register description will state that. the local transfer control descriptor memory. signaling the high and low portions of the control function. Table 22. eDMA memory map

Table 22. eDMA memory map (continued)

Table 23. eDMA 32-bit memory map—graphical view

Table 23. eDMA 32-bit memory map—graphical view (continued)

8.3.2 Register descriptions

64 bits for eDMA (made up of two 32-bit registers: high and low—for example, EDMA_ERQRH has upper 32 channels of eDMA) eDMA Control Register (EDMA_CR) The 32-bit EDMA_CR defines the basic operating configuration of the eDMA. The eDMA arbitrates channel service requests in four (eDMA) groups (0, 1, 2, 3) of 16 channels each:
Group 0 contains channels 0–15
Group 1 contains channels 16–31
Group 2 contains channels 32–47 (eDMA only)
Group 3 contains channels 48–63 (eDMA only) Arbitration within a group can be configured to use a fixed priority or a round robin. In fixed- priority arbitration, the highest priority channel requesting service is selected to execute. The priorities are assigned by the channel priority registers. See Section , eDMA Channel n 0xFFF4_4114 eDMA Channel 52 Priority (EDMA_CPR52) eDMA Channel 53 Priority (EDMA_CPR53) eDMA Channel 54 Priority (EDMA_CPR54) eDMA Channel 55 Priority (EDMA_CPR55) 0xFFF4_4118 eDMA Channel 56 Priority (EDMA_CPR56) eDMA Channel 57 Priority (EDMA_CPR57) eDMA Channel 58 Priority (EDMA_CPR58) eDMA Channel 59 Priority (EDMA_CPR59) 0xFFF4_411C eDMA Channel 60 Priority (EDMA_CPR60) eDMA Channel 61 Priority (EDMA_CPR61) eDMA Channel 62 Priority (EDMA_CPR62) eDMA Channel 63 Priority (EDMA_CPR63) 0xFFF4_5000 – 0xFFF4_51FC EDMA_TCD00–EDMA_TCD15 0xFFF4_5200 – 0xFFF4_53FC EDMA_TCD16–EDMA_TCD31 0xFFF4_5400 – 0xFFF4_55FC EDMA_TCD32–EDMA_TCD47 0xFFF4_5600 – 0xFFF4_57FC EDMA_TCD48–EDMA_TCD63 0xFFF4_5800 Reserved

channel 0,without regard to priority. cycled through, from group 3 (eDMA) down to group 0, without regard to priority. EDMA_TCD[SADDR] and EDMA_TCD[DADDR] values. both source and destination minor loop offsets. cleared and DMLOE is cleared), the NBYTES field becomes a 30-bit vector. Figure 20. eDMA Control Register (EDMA_CR)

Table 24. EDMA_CR field descriptions

0 Normal operation

eDMA Error Status Register (EDMA_ESR). Group 3 priority level when fixed priority group arbitration is enabled. Group 2 priority level when fixed priority group arbitration is enabled. Group 1 priority level when fixed priority group arbitration is enabled. Group 0 priority level when fixed priority group arbitration is enabled. 0 Minor loop mapping disabled. TCD Word 2 is defined as a 32-bit nbytes field. reduced when either offset is enabled.

0 A minor loop channel link made to itself goes through channel arbitration before being activated

1 A minor loop channel link made to itself does not go through channel arbitration before being

loop offsets and restarts the next minor loop. execution resumes when the HALT bit is cleared.

the programmed transfer size respectively. of error. All channel priority levels must be unique before any service requests are made. reported if the scatter-gather address (DLAST_SGA) is not aligned on a 32-byte boundary. 0 Fixed-priority arbitration is used for selection among the groups. 1 Round-robin arbitration is used for selection among the groups. 0 Fixed-priority arbitration is used for channel selection within each group. 1 Round-robin arbitration is used for channel selection within each group. 0 The assertion of the system debug control input is ignored.

1 The assertion of the system debug control input causes the eDMA to stall the start of a new

the system debug control input is negated or the EDBG bit is cleared. Table 24. EDMA_CR field descriptions (continued)

major or minor loop, the cancel request is discarded and the channel retires normally. to Section , eDMA Error Registers (EDMA_ERH, EDMA_ERL). channel will execute and terminate with the same error condition. Figure 21. eDMA Error Status Register (EDMA_ESR) Table 25. EDMA_ESR field descriptions Logical OR of all EDMA_ERL status bits. 1 At least one EDMA_ER bit is set indicating a valid error exists that has not been cleared.

0 No canceled transfers

1 The last recorded entry was a canceled transfer via the error cancel transfer input.

0 No group-priority error

1 The last recorded error was a configuration error among the group priorities indicating not all

group priorities are unique.

0 No channel-priority error

1 The last recorded error was a configuration error in the channel priorities within a group,

indicating not all channel priorities within a group are unique. transfer that was error cancelled. registers to find groups or channels with duplicate priority level.

0 No source address configuration error

1 The last recorded error was a configuration error detected in field EDMA_TCD[SADDR],

indicating EDMA_TCD[SADDR] is inconsistent with EDMA_TCD[SSIZE].

0 No source offset configuration error

1 The last recorded error was a configuration error detected in field EDMA_TCD[SOFF], indicating

EDMA_TCD[SOFF] is inconsistent with EDMA_TCD[SSIZE].

0 No destination address configuration error

1 The last recorded error was a configuration error detected in field EDMA_TCD[DADDR],

indicating EDMA_TCD[DADDR] is inconsistent with EDMA_TCD[DSIZE].

0 No destination offset configuration error

1 The last recorded error was a configuration error detected in field EDMA_TCD[DOFF], indicating

EDMA_TCD[DOFF] is inconsistent with EDMA_TCD[DSIZE].

0 No NBYTES/CITER configuration error

1 The last recorded error was a configuration error detected in fields EDMA_TCD[NBYTES] or

– EDMA_TCD[CITER.E_LINK] is not equal to EDMA_TCD[BITER.E_LINK].

0 No scatter-gather configuration error

1 The last recorded error was a configuration error detected in field EDMA_TCD[DLAST_SGA],

Table 25. EDMA_ESR field descriptions (continued)

63–32, while EDMA_ERQRL covers channels 31–0.

0 No source bus error

1 The last recorded error was a bus error on a source read.

0 No destination bus error

1 The last recorded error was a bus error on a destination write. Figure 22. eDMA Enable Request High Register (EDMA_ERQRH)

the D_REQ bit is cleared, the state of the EDMA_ERQR bit is unaffected. channels 63–32, while EDMA_EEIRL covers channels 31–0. an error interrupt request for a given channel is asserted. Figure 23. eDMA Enable Request Register (EDMA_ERQRL) Table 26. EDMA_ERQRL field descriptions 0 The eDMA request signal for channel n is disabled. 1 The eDMA request signal for channel n is enabled.

eDMA request inputs. Reads of this register return all zeroes. written as a 32-bit word. Reads of this register return all zeroes. Figure 26. eDMA Set Enable Request Register (EDMA_SERQR) Table 28. EDMA_SERQR field descriptions 1 No operation, ignore bits 1–7. 0–32 (64 for eDMA) Set corresponding bit in EDMA_ERQRH or EDMA_ERQRL. 64–127 Set all bits in EDMA_ERQRH and EDMA_ERQRL. Figure 27. eDMA Clear Enable Request Register (EDMA_CERQR) Table 29. EDMA_CERQR field descriptions 1 No operation, ignore bits 1–7. 0–32 (64 for eDMA) Clear corresponding bit in EDMA_ERQRH or EDMA_ERQRL. 64–127 Clear all bits in EDMA_ERQRH and EDMA_ERQRL.

as a 32-bit word. Reads of this register return all zeroes. interrupts for all channels. Reads of this register return all zeroes. as a 32-bit word. Reads of this register return all zeroes. Figure 28. eDMA Set Enable Error Interrupt Register (EDMA_SEEIR) Table 30. EDMA_SEEIR field descriptions 1 No operation, ignore bits 1–7. 0–32 (64 for eDMA) Set corresponding bit in EDMA_EIRRH or EDMA_EIRRL. 64–127 Set all bits in EDMA_EIRRH or EDMA_EEIRL. Figure 29. eDMA Clear Enable Error Interrupt Register (EDMA_CEEIR)

interrupt requests. Reads of this register return all zeroes. as a 32-bit word. Reads of this register return all zeroes. error indicators. Reads of this register return all zeroes. Table 31. EDMA_CEEIR field descriptions 1 No operation, ignore bits 1-7. 0–32 (64 for eDMA) Clear corresponding bit in EDMA_EEIRH or EDMA_EEIRL. 64–127 Clear all bits in EDMA_EEIRH or EDMA_EEIRL. Figure 30. eDMA Clear Interrupt Request (EDMA_CIRQR) Table 32. EDMA_CIRQR field descriptions 1 No operation, ignore bits 1–7. 0–32 (64 for eDMA) Clear corresponding bit in EDMA_IRQRH or EDMA_IRQRL. 64–127 Clear all bits in EDMA_IRQRH or EDMA_IRQRL.

written as a 32-bit word. Reads of this register return all zeroes. set function, forcing all START bits to be set. Reads of this register return all zeroes. as a 32-bit word. Reads of this register return all zeroes. Figure 31. eDMA Clear Error Register (EDMA_CER) Table 33. EDMA_CER field descriptions 1 No operation, ignore bits 1–7. 0–32 (64 for eDMA) Clear corresponding bit in EDMA_ERH or EDMA_ERL. 64–127 Clear all bits in EDMA_ERH or EDMA_ERL. Figure 32. eDMA Set START Bit Register (EDMA_SSBR) Table 34. EDMA_SSBR field descriptions 1 No operation, ignore bits 1–7. 0–32 (64 for eDMA) Set the corresponding channel’s TCD START bit. 64–127 Set all TCD START bits.

global clear function, forcing all DONE bits to be cleared. as a 32-bit word. Reads of this register return all zeroes. and EDMA_IRQRL maps to channels 31–0. register. The outputs of this register are directly routed to the interrupt controller (INTC). the EDMA_CIRQR in the interrupt service routine is used for this purpose. Figure 33. eDMA Clear DONE Status Bit Register (EDMA_CDSBR) Table 35. EDMA_CDSBR field descriptions 1 No operation, ignore bits 1–7. 0–32 (64 for eDMA) Clear the corresponding channel’s DONE bit. 64–127 Clear all TCD DONE bits.

in the EDMA_CR. See Figure 20 and Table 24 for the EDMA_CR definition. when fixed arbitration is selected for both group and channel arbitration modes. ECP setting. This allows for a pool of low priority, large data moving channels to be defined. Figure 40. eDMA Channel n Priority Register (EDMA_CPRn)

The reset value for the channel priority field, CHPRI[0–3], is equal to the corresponding channel number for

each priority register; that is, EDMA_CPRI0[CHPRI] = 0b0000 and EDMA_CPR15[CHPRI] = 0b1111. Table 39. EDMA_CPRn field descriptions 0 Channel n cannot be suspended by a higher priority channel’s service request. 1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0 Channel n can suspend a lower priority channel. 1 Channel n cannot suspend any channel, regardless of channel priority.

presented as eight 32-bit values. Table 40 is a field list of the basic TCD structure. Figure 41 and Table 41 define the fields of the TCDn structure. corresponding channel number for each priority register; that is, EDMA_CPR31[GRPPRI] = 0b01. Table 39. EDMA_CPRn field descriptions (continued) Table 40. TCD n 32-bit memory structure

must be initialized by the application code before activating that channel. Figure 41. TCD structure

The fields implemented in Word 2 depend on whether EDMA_CR(EMLM) is set to ‘0’ or ‘1’. Refer to Table 24.

Table 41. TCDn field descriptions Memory address pointing to the source data. 0 Source address modulo feature is disabled.

100 Reserved

110 Reserved

111 Reserved

See the SMOD[0:5] definition. See the SSIZE[0:2] definition. state value as each source read is completed. address upon minor loop completion. 0 The minor loop offset is not applied to the saddr. 1 The minor loop offset is applied to the saddr.

address upon minor loop completion. 0 The minor loop offset is not applied to the daddr. 1 The minor loop offset is applied to the daddr. value after the minor loop is completed. Memory address pointing to the destination data. favor of the MAJOR.E_LINK channel linking. 0 The channel-to-channel linking is disabled. 1 The channel-to-channel linking is enabled. Table 41. TCDn field descriptions (continued)

that channel’s EDMA_TCD[START] bit. CITER field from the beginning iteration count (BITER) field. value as that contained in the BITER field. of BITER and CITER should be 0x0001. next-state value as each destination write is completed. transfer control descriptor to be loaded into this channel (scatter-gather). the outer major iteration count. value, or adjust the address to reference the next data structure. otherwise a configuration error is reported.

favor of the MAJOR.E_LINK channel linking. 0 The channel-to-channel linking is disabled. 1 The channel-to-channel linking is enabled. that channel’s EDMA_TCD[START] bit. exhausted, the contents of this field are reloaded into the CITER field. of BITER and CITER should be 0x0001. seen by the system bus crossbar switch (XBAR).

00 No DMA engine stalls

01 Reserved

10 DMA engine stalls for 4 cycles after each r/w

11 DMA engine stalls for 8 cycles after each r/w

major loop counter is exhausted. by setting that channel’s EDMA_TCD[START] bit. begun processing the channel, not when the first data transfer occurs). This bit must be cleared to write the MAJOR.E_LINK or E_SG bits. completes or if any error condition is detected. sets bit EDMA_TCD[START] of the specified channel. written to while the bit EDMA_TCD[DONE] is set. 0 The channel-to-channel linking is disabled. 1 The channel-to-channel linking is enabled. zero when written to while the bit EDMA_TCD[DONE] is set. 0 The current channel’s TCD is normal format. loaded into this channel after the outer major loop completes its execution.

8.4 Functional description

submodules, which are detailed below.

DMA engine – Address path: This module implements registered versions of two channel transfer control descriptors: channel x and channel y, and is responsible for all the master bus address calculations. All the implemented channels provide the same functionality. This hardware structure allows the data transfers associated with one channel to be pre-empted after the completion of a read/write sequence if a higher 252 / 0x1C [28] D_REQ Disable hardware request If this flag is set, the eDMA hardware automatically clears the corresponding EDMA_ERQH or EDMA_ERQL bit when the current major iteration count reaches zero. 0 The channel’s EDMA_ERQH or EDMA_ERQL bit is not affected.

1 The channel’s EDMA_ERQH or EDMA_ERQL bit is cleared when the

outer major loop is complete. (CITER == (BITER >> 1)) after a single activation. 0 The half-point interrupt is disabled. 1 The half-point interrupt is enabled. major iteration count reaches zero. 0 The end-of-major loop interrupt is disabled. 1 The end-of-major loop interrupt is enabled. If this flag is set the channel is requesting service. 0 The channel is not explicitly started. 1 The channel is explicitly started via a software initiated service request.

Enhanced Direct Memory Access Controller (eDMA) RM0029 214/1740 Doc ID 15177 Rev 8 priority channel service request is asserted while the first channel is active. After a channel is activated, it runs until the minor loop is completed unless pre-empted by a higher priority channel. This capability provides a mechanism (optionally enabled by EDMA_CPRn[ECP]) where a large data move operation can be pre- empted to minimize the time another channel is blocked from execution. – When another channel is activated, the contents of its transfer control descriptor is read from the local memory and loaded into the registers of the other address path channel{x,y}. After the inner minor loop completes execution, the address path hardware writes the new values for the TCDn.{SADDR, DADDR, CITER} back into the local memory. If the major iteration count is exhausted, additional processing is performed, including the final address pointer updates, reloading the TCDn.CITER field, and a possible fetch of the next TCDn from memory as part of a scatter-gather operation. – Data path: This module implements the actual bus master read/write datapath. It includes 32 bytes of register storage (matching the maximum transfer size) and the necessary mux logic to support any required data alignment. The system read data bus is the primary input, and the system write data bus is the primary output. – The address and data path modules directly support the two-stage pipelined system bus. The address path module represents the 1st stage of the bus pipeline (the address phase), while the data path module implements the second stage of the pipeline (the data phase). – Program model/channel arbitration: This module implements the first section of eDMA’s programming model and also the channel arbitration logic. The programming model registers are connected to the slave bus (not shown). The eDMA peripheral request inputs and eDMA interrupt request outputs are also connected to this module (via the control logic). – Control: This module provides all the control functions for the DMA engine. For data transfers where the source and destination sizes are equal, the DMA engine performs a series of source read, destination write operations until the number of bytes specified in the inner minor loop byte count has been moved. A minor loop interaction is defined as the number of bytes to transfer (nbytes) divided by the transfer size. Transfer size is defined as: if (SSIZE < DSIZE) transfer size = destination transfer size (# of bytes) else transfer size = source transfer size (# of bytes) Minor loop TCD variables are SOFF, SMOD, DOFF, DMOD, NBYTES, SADDR, DADDR, BWC, ACTIVE, AND START. Major loop TCD variables are DLAST, SLAST, CITER, BITER, DONE, D_REQ, INT_MAJ, MAJOR_LNKCH, and INT_HALF. For descriptors where the sizes are not equal, multiple access of the smaller size data are required for each reference of the larger size. For example, if the source size references 16-bit data and the destination is 32-bit data, two reads are performed, then one 32-bit write.

TCD local memory – Memory controller: This logic implements the required dual-ported controller, handling accesses from both the DMA engine as well as references from the slave bus. As noted earlier, in the event of simultaneous accesses, the DMA engine is

RM0029 Enhanced Direct Memory Access Controller (eDMA) Doc ID 15177 Rev 8 215/1740 given priority and the slave transaction is stalled. The hooks to a BIST controller for the local TCD memory are included in this module. – Memory array: The TCD is implemented using a single-ported, synchronous compiled RAM memory array. 8.4.1 eDMA basic data flow The eDMA transfers data based on a two-deep, nested flow. The basic flow of a data transfer can be partitioned into three segments. As shown in Figure 42, the first segment involves the channel service request. In the diagram, this example uses the assertion of the eDMA peripheral request signal to request service for channel n. Channel service request via software and the TCDn.START bit follows the same basic flow as an eDMA peripheral request. The eDMA peripheral request input signal is registered internally and then routed to through the DMA engine, first through the control module, then into the program model/channel arbitration module. In the next cycle, the channel arbitration is performed using the fixed-priority or round-robin algorithm. After the arbitration is complete, the activated channel number is sent through the address path and converted into the required address to access the TCD local memory. Next, the TCD memory is accessed and the required descriptor read from the local memory and loaded into the DMA engine address path channel{x,y} registers. The TCD memory is organized 64-bits in width to minimize the time needed to fetch the activated channel’s descriptor and load it into the eDMA engine address path channel{x,y} registers.

Figure 42. eDMA operation, Part 1 handshake signal is asserted at the end of the minor byte count transfer.

Figure 44. eDMA operation, Part 3

8.5 Initialization / Application information

Write the EDMA_CR if a configuration other than the default is desired.
Write the channel priority levels into the EDMA_CPR n registers if a configuration other

than the default is desired.

Enable error interrupts in the EDMA_EEIRL and/or EDMA_EEIRH registers if desired.
Write the 32-byte TCD for each channel that may request service.
Enable any hardware service requests via the EDMA_ERQRH and/or EDMA_ERQRL
Request channel service by software (setting bit EDMA_TCD[START]) or by hardware

(slave device asserting its DMA peripheral request signal).

the beginning iteration count (biter). Table 42. TCD primary control and status fields

Figure 45. Example of multiple loop iterations Figure 46 lists the memory array terms and how the TCD settings interrelate. Figure 46. Memory array terms

8.5.2 DMA programming errors

and EDMA_ESR[CPE], respectively. activation of the problem channel, the error is detected and recorded again.

The DMA is configured for fixed-group and fixed-channel arbitration modes.
Group 1 is the highest priority and all channels are unique in that group.
Group 0 is the next highest priority and has two channels with the same priority level.
If group 1 has any service requests, those requests are executed.
After all of group 1 requests have completed, group 0 becomes the next active group.
If group 0 has a service request, then an undefined channel in group 0 is selected and

a channel-priority error will occur.

This repeats until the all of group 0 requests have been removed or a higher priority

signals, error interrupts, and error reporting are associated with the selected channel.

8.5.3 DMA request assignments

syntax is module_instance.register[bit]. Table 43. DMA request summary for eDMA

Table 43. DMA request summary for eDMA (continued)

8.5.4 DMA arbitration mode considerations

quickly. pre-emption is available in this scenario only. number containing a service request. or skipping a group if it has no pending requests. channels can prevent the servicing of lower priority channels in the same group. serviced from each requesting group for each round robin pass through the groups. rotating through to the lowest channel number without regard to channel priority levels. DMA requests that are not serviced are simply lost, but at least one channel gets serviced.

RM0029 Enhanced Direct Memory Access Controller (eDMA) Doc ID 15177 Rev 8 225/1740 This scenario ensures that all channels are guaranteed service at some point, regardless of the request rates. However, the potential latency could be high. All channels are treated equally. Priority levels are not used in round-robin/round-robin mode. Fixed-group arbitration, round-robin channel arbitration The highest priority group with a request is serviced. Lower priority groups are serviced if no pending requests exist in the higher priority groups. Within each group, channels are serviced starting with the highest channel number and rotating through to the lowest channel number without regard to the channel priority levels assigned within the group. This scenario could cause the same bandwidth consumption problem as indicated in Section , Fixed-group arbitration, fixed-channel arbitration but all the channels in the highest priority group get serviced. Service latency is short on the highest priority group, but could potentially get longer and longer as the group priority decreases.

8.5.5 DMA transfer

To perform a simple transfer of n bytes of data with one activation, set the major loop to ‘1’ (EDMA_TCD[CITER] = EDMA_TCD[BITER] = 1). The data transfer begins after the channel service request is acknowledged and the channel is selected to execute. After the transfer is complete, bit EDMA_TCD[DONE] is set and an interrupt is generated if properly enabled. For example, the following TCD entry is configured to transfer 16 bytes of data. The eDMA is programmed for one iteration of the major loop transferring 16 bytes per iteration. The source memory has a byte wide memory port located at 0x1000. The destination memory has a word wide port located at 0x2000. The address offsets are programmed in increments to match the size of the transfer; one byte for the source and four bytes for the destination. The final source and destination addresses are adjusted to return to their beginning values. EDMA_TCD[CITER] = EDMA_TCD[BITER] = 1 EDMA_TCD[NBYTES] = 16 EDMA_TCD[SADDR] = 0x1000 EDMA_TCD[SOFF] = 1 EDMA_TCD[SSIZE] = 0 EDMA_TCD[SLAST] = –16 EDMA_TCD[DADDR] = 0x2000 EDMA_TCD[DOFF] = 4 EDMA_TCD[DSIZE] = 2 EDMA_TCD[DLAST_SGA] = –16 EDMA_TCD[INT_MAJ] = 1 EDMA_TCD[START] = 1 (Must be written last after all other fields have been initialized) All other TCD fields = 0 This would generate the following sequence of events:

Enhanced Direct Memory Access Controller (eDMA) RM0029 226/1740 Doc ID 15177 Rev 8 1. Slave write to the EDMA_TCD[START] bit requests channel service. 2. The channel is selected by arbitration for servicing. 3. eDMA engine writes: EDMA_TCD[DONE] = 0, EDMA_TCD[START] = 0, EDMA_TCD[ACTIVE] = 1. 4. eDMA engine reads: channel TCD data from local memory to internal register file. 5. The source to destination transfers are executed as follows: a) read_byte(0x1000), read_byte(0x1001), read_byte(0x1002), read_byte(0x1003) b) write_word(0x2000) Æ first iteration of the minor loop c) read_byte(0x1004), read_byte(0x1005), read_byte(0x1006), read_byte(0x1007) d) write_word(0x2004) Æ second iteration of the minor loop e) read_byte(0x1008), read_byte(0x1009), read_byte(0x100A), read_byte(0x100B) f) write_word(0x2008) Æ third iteration of the minor loop g) read_byte(0x100C), read_byte(0x100D), read_byte(0x100E), read_byte(0x100F) h) write_word(0x200C) Æ last iteration of the minor loop Æ major loop complete 6. eDMA engine writes: EDMA_TCD[SADDR] = 0x1000, EDMA_TCD[DADDR] = 0x2000, EDMA_TCD[CITER] = 1 (EDMA_TCD[BITER]). 7. eDMA engine writes: EDMA_TCD[ACTIVE] = 0, EDMA_TCD[DONE] = 1, EDMA_IRQRn =1 . 8. The channel retires. The eDMA goes idle or services the next channel. Multiple requests The next example is the same as previous, excepting transferring 32 bytes via two hardware requests. The only fields that change are the major loop iteration count and the final address offsets. The eDMA is programmed for two iterations of the major loop transferring 16 bytes per iteration. After the channel’s hardware requests are enabled in the EDMA_ERQR, channel service requests are initiated by the slave device (ERQR should be set after TCD). Note that EDMA_TCD[START] = 0. EDMA_TCD[CITER = EDMA_TCD[BITER] = 2 EDMA_TCD[NBYTES] = 16 EDMA_TCD[SADDR] = 0x1000 EDMA_TCD[SOFF] = 1 EDMA_TCD[SSIZE] = 0 EDMA_TCD[SLAST] = –32 EDMA_TCD[DADDR] = 0x2000 EDMA_TCD[DOFF] = 4 EDMA_TCD[DSIZE] = 2 EDMA_TCD[DLAST_SGA] = –32 EDMA_TCD[INT_MAJ] = 1 EDMA_TCD[START] = 0 (Must be written last after all other fields have been initialized) All other TCD fields = 0 This generates the following sequence of events:

RM0029 Enhanced Direct Memory Access Controller (eDMA) Doc ID 15177 Rev 8 227/1740 1. First hardware (eDMA peripheral request) request for channel service. 2. The channel is selected by arbitration for servicing. 3. eDMA engine writes: EDMA_TCD[DONE] = 0, EDMA_TCD[START] = 0, EDMA_TCD[ACTIVE] = 1. 4. eDMA engine reads: channel TCD data from local memory to internal register file. 5. The source to destination transfers are executed as follows: a) read_byte(0x1000), read_byte(0x1001), read_byte(0x1002), read_byte(0x1003) b) write_word(0x2000) Æ first iteration of the minor loop c) read_byte(0x1004), read_byte(0x1005), read_byte(0x1006), read_byte(0x1007) d) write_word(0x2004) Æ second iteration of the minor loop e) read_byte(0x1008), read_byte(0x1009), read_byte(0x100A), read_byte(0x100B) f) write_word(0x2008) Æ third iteration of the minor loop g) read_byte(0x100C), read_byte(0x100D), read_byte(0x100E), read_byte(0x100F) h) write_word(0x200C) Æ last iteration of the minor loop 6. eDMA engine writes: EDMA_TCD[SADDR] = 0x1010, EDMA_TCD[DADDR] = 0x2010, EDMA_TCD[CITER] = 1. 7. eDMA engine writes: EDMA_TCD[ACTIVE] = 0. 8. The channel retires Æ one iteration of the major loop. The eDMA goes idle or services the next channel. 9. Second hardware (eDMA peripheral request) requests channel service. 10. The channel is selected by arbitration for servicing. 11. eDMA engine writes: EDMA_TCD[DONE] = 0, EDMA_TCD[START] = 0, EDMA_TCD[ACTIVE] = 1. 12. eDMA engine reads: channel TCD data from local memory to internal register file. 13. The source to destination transfers are executed as follows: a) read_byte(0x1010), read_byte(0x1011), read_byte(0x1012), read_byte(0x1013) b) write_word(0x2010) Æ first iteration of the minor loop c) read_byte(0x1014), read_byte(0x1015), read_byte(0x1016), read_byte(0x1017) d) write_word(0x2014) Æ second iteration of the minor loop e) read_byte(0x1018), read_byte(0x1019), read_byte(0x101A), read_byte(0x101B) f) write_word(0x2018) Æ third iteration of the minor loop g) read_byte(0x101C), read_byte(0x101D), read_byte(0x101E), read_byte(0x101F) h) write_word(0x201C) Æ last iteration of the minor loop Æ major loop complete 14. eDMA engine writes: EDMA_TCD[SADDR] = 0x1000, EDMA_TCD[DADDR] = 0x2000, EDMA_TCD[CITER] = 2 (EDMA_TCD[BITER]). 15. eDMA engine writes: EDMA_TCD[ACTIVE] = 0, EDMA_TCD[DONE] = 1, EDMA_IRQRn =1 . 16. The channel retires Æ major loop complete. The eDMA goes idle or services the next channel. Modulo feature The modulo feature of the eDMA provides the ability to implement a circular data queue in which the size of the queue is a power of two. MOD is a 5-bit bitfield for both the source and

same as in the original value. A setting of 0 for this field disables the modulo feature. 4 byte (16-byte) size queue.

8.5.6 TCD status

status may be missed if the channel execution is short in duration.

EDMA_TCD[START] = 1, EDMA_TCD[ACTIVE] = 0, EDMA_TCD[DONE] = 0 (channel

service request via software).

EDMA_TCD[START] = 0, EDMA_TCD[ACTIVE] = 1, EDMA_TCD[DONE] = 0 (channel
EDMA_TCD[START] = 0, EDMA_TCD[ACTIVE] = 0, EDMA_TCD[DONE] = 0 (channel
EDMA_TCD[START] = 0, EDMA_TCD[ACTIVE] = 0, EDMA_TCD[DONE] = 1 (channel

has completed the major loop and is idle). and acknowledge handshakes signals are not visible in the programmer’s model. Table 44. Modulo feature example

RM0029 Enhanced Direct Memory Access Controller (eDMA) Doc ID 15177 Rev 8 229/1740 1. eDMA peripheral request asserts (channel service request via hardware). 2. EDMA_TCD[START] = 0, EDMA_TCD[ACTIVE] = 1, EDMA_TCD[DONE] = 0 (channel is executing). 3. EDMA_TCD[START] = 0, EDMA_TCD[ACTIVE] = 0, EDMA_TCD[DONE] = 0 (channel has completed the minor loop and is idle), or 4. EDMA_TCD[START] = 0, EDMA_TCD[ACTIVE] = 0, EDMA_TCD[DONE] = 1 (channel has completed the major loop and is idle). For both activation types, the major loop complete status is explicitly indicated via bit EDMA_TCD[DONE]. Bit EDMA_TCD[START] is cleared automatically when the channel begins execution, regardless of how the channel was activated. Active channel TCD reads The eDMA will read back the true EDMA_TCD[SADDR], EDMA_TCD[DADDR], and EDMA_TCD[NBYTES] values if read while a channel is executing. The true values of the SADDR, DADDR, and NBYTES are the values the eDMA engine is currently using in its internal register file and not the values in the TCD local memory for that channel. The addresses (SADDR and DADDR) and NBYTES (decrements to zero as the transfer progresses) can give an indication of the progress of the transfer. All other values are read back from the TCD local memory. Pre-emption status Pre-emption is available only when fixed arbitration is selected for both group- and channel- arbitration modes. A pre-emptable situation is one in which a pre-empt-enabled channel is running and a higher priority request becomes active. When the eDMA engine is not operating in fixed group, fixed-channel arbitration mode, the determination of the relative priority of the actively running and the outstanding requests become undefined. Channel and group priorities are treated as equal (or more exactly, constantly rotating) when round- robin arbitration mode is selected. Bit EDMA_TCD[ACTIVE] for the pre-empted channel remains asserted throughout the pre- emption. The pre-empted channel is temporarily suspended while the pre-empting channel executes one iteration of the major loop. Two EDMA_TCD[ACTIVE] bits set at the same time in the overall TCD map indicates a higher priority channel is actively pre-empting a lower priority channel.

8.5.7 Channel linking

Channel linking (or chaining) is a mechanism in which one channel sets bit EDMA_TCD[START] of another channel (or itself), thus initiating a service request for that channel. This operation is automatically performed by the eDMA engine at the conclusion of the major or minor loop when properly enabled. The minor loop channel linking occurs at the completion of the minor loop (or one iteration of the major loop). Field EDMA_TCD[CITER.E_LINK] is used to determine whether a minor loop link is requested. When enabled, the channel link is made after each iteration of the minor loop except for the last. When the major loop is exhausted, only the major loop

Minor loop done Æ set channel 12 EDMA_TCD[START] bit
Minor loop done Æ set channel 12 EDMA_TCD[START] bit
Minor loop done Æ set channel 12 EDMA_TCD[START] bit
Minor loop done, major loop done Æ set channel 7 EDMA_TCD[START] bit

EDMA_TCD[CITER] uses a 9-bit vector to form the current iteration count. to increase the range of the CITER. must be equal to calculate the major loop, halfway done interrupt point. another channel’s TCD, at the end of a loop.

8.5.8 Dynamic programming

allowing the user to enable the feature during channel execution. Table 45. Channel linking parameters major.e_link Enable channel-to-channel linking on major loop completion. major.linkch Link channel number when linking at end of major loop.

would be unclear whether the actual link was made before the channel retired. Dynamic scatter/gather is the process of setting the TCD.e_sg bit during channel execution. the user to enable the feature during channel execution. unclear whether the actual scatter/gather request was honored before the channel retired. TCD.word7 if that channel’s TCD.done bit is set indicating the major loop is complete. used for a dynamic scatter/gather request. the TCD.major.linkch field as a TCD indentification (ID). Table 46. Coherency model for a dynamic channel link request 1 Write 1b to the TCD.major.e_link bit. 2 Read back the TCD.major.e_link bit. – If TCD.major.e_link = 1b, the dynamic link attempt was successful.

Table 47. Coherency model for method 1 each TCD associated with a channel using dynamic scatter/gather. Write 1b to theTCD.d_req bit. 3 Write theTCD.dlast_sga field with the scatter/gather address. 4 Write 1b to the TCD.e_sg bit. 5 Read back the 16 bit TCD control/status field. – If e_sg = 1b, the dynamic link attempt was successful. succeed (the channel was already retiring). (the new TCD’s e_sg value cleared the e_sg bit). Table 48. Coherency model for method 2 Write 1b to theTCD.d_req bit. 2 Write theTCD.dlast_sga field with the scatter/gather address. 3 Write 1b to the TCD.e_sg bit. 4 Read back the TCD.e_sg bit. – If e_sg = 1b, the dynamic link attempt was successful. – If e_sg = 0b, read the 32 bit TCD dlast_sga field. succeed (the channel was already retiring). new TCD’s e_sg value cleared the e_sg bit).

9 Multi-Layer AHB Crossbar Switch (XBAR)

9.1 Introduction

9.1.1 Overview

Figure 47. XBAR device-specific block diagram The port mappings are shown in Table 49. Table 49. Master/Slave mappings

9.1.2 Features

system and ensuring that no bus activity will be interrupted. dynamically change master priority levels on a slave port by slave port basis. master completes its transactions. The XBAR has a 32-bit internal address bus and a 64-bit internal data bus.

9.1.3 Limitations

request/bus grant protocol; the XBAR assumes it is the sole master of each slave port.

9.1.4 General operation

depends on each master’s priority level and the responding peripheral’s access time.

The EBI (External Bus Interface) is connected as a master but is not implemented with a multi-master

mode so it is, in effect, “parked”. Regardless, it must be configured as with other supported masters.

The calibration bus is only available on the calibration package.

the master does not have control of the slave port it is targeting it will simply be wait stated. of the higher priority master. master may be granted access to the slave port. also be put into low power park mode in attempt to save power.

9.2 XBAR registers

This section provides information on XBAR registers.

9.2.1 Register summary

bus compliant registers. Read and write transfers both require two IP bus clock cycles. Read and writen operations can be performed on these registers only in supervisor mode. Additionally, these registers can only be read from or written to by 32-bit accesses. location is accessed within the XBAR. have no effect on the registers and will be terminated with an error response. The memory map for the XBAR program-visible registers is shown in Table 50. Table 50. XBAR Register Configuration Summary

9.2.2 XBAR register descriptions

The following paragraphs provide detailed descriptions of the various XBAR registers. Refer to Figure 48 for the various bit configurations that appear in the register maps. Table 50. XBAR Register Conf iguration Summary (continued) Figure 48. Key to Register Fields

“BIT” refers to a field name in the register. Some fields span multiple bits.

Figure 49. Master Priority Register (XBAR_MPRn) Table 51. XBAR Master Priority Register Field Descriptions These bits set the arbitration priority for master port 7 (EBI) on the associated slave port. These bits are initialized by hardware reset. The reset value is 111. 000: This master has the highest priority when accessing the slave port. 111: This master has the lowest priority when accessing the slave port.

These bits set the arbitration priority for master port 6 (FlexRay) on the associated slave port. These bits are initialized by hardware reset. The reset value is 110. 000: This master has the highest priority when accessing the slave port. 111: This master has the lowest priority when accessing the slave port. These bits set the arbitration priority for master port 4 (eDMA) on the associated slave port. These bits are initialized by hardware reset. The reset value is 100. 000: This master has the highest priority when accessing the slave port. 111: This master has the lowest priority when accessing the slave port. Table 51. XBAR Master Priority Register Field Descriptions (continued)

The Master Priority Register can only be accessed in supervisor mode with 32-bit accesses. on the MPR and result in an error response. response and the MPR will not be updated. once it is written to a 1 only a reset condition will allow it to be written again. access it when it is not in use because it will not be parked on any master. Nexus) on the associated slave port. These bits are initialized by hardware reset. The reset value is 001. 000: This master has the highest priority when accessing the slave port. 111: This master has the lowest priority when accessing the slave port. 000: This master has the highest priority when accessing the slave port. 111: This master has the lowest priority when accessing the slave port.

implementation undefined behavior will result. to it will have no effect on the SGPCR and result in an error response. Figure 50. Slave General Purpose Control Register (XBAR_SGPCRn) Table 52. XBAR Slave General Purpose Control Register Field Descriptions This bit is initialized by hardware reset. The reset value is 0. 0: All this slave port’s registers can be written. and result in an error response).

These bits are used to enable the mX_high_priority inputs for the respective master. These bits are initialized by hardware reset. The reset value is 0. 1: The mX_high_priority input is enabled on this slave port. These bits are used to select the arbitration policy for the slave port. These bits are initialized by hardware reset. The reset value is 00. These bits determine the parking control used by this slave port. These bits are initialized by hardware reset. The reset value is 00. all outputs to a constant safe state. Table 52. XBAR Slave General Purpose Control Register Field Descriptions (continued)

9.2.3 Coherency

accesses but instead track only with IP bus accesses.

9.3 Function

This section describes in more detail the functionality of the XBAR.

9.3.1 Arbitration

programmable for each slave port. actively making requests and the PCTL bits are set to 00. These bits are initialized by hardware reset. The reset value is 000.

RM0029 Multi-Layer AHB Crossbar Switch (XBAR) Doc ID 15177 Rev 8 243/1740 control over the slave port is running a fixed length burst transfer or a locked transfer. In this case the new requesting master will have to wait until the end of the burst transfer or locked transfer before it will be granted control of the slave port. If the master is running an undefined length burst transfer the new requesting master must wait until an arbitration point for the undefined length burst transfer before it will be granted control of the slave port. Arbitration points for an undefined length burst are defined in the MGPCR for each master. If the new requesting master’s priority level is lower than that of the master that currently has control of the slave port the new requesting master will be forced to wait until the master that currently has control of the slave port either runs an IDLE cycle or runs a non IDLE cycle to a location other than the current slave port. Round-Robin priority operation When operating in round-robin mode, each master is assigned a relative priority based on the master number.This relative priority is compared to the ID of the last master to perform a transfer on the slave bus. The highest priority requesting master will become owner of the slave bus as the next transfer boundary (accounting for locked and fixed-length burst transfers). Priority is based on how far ahead the ID of the requesting master is to the ID of the last master (ID is defined by master port number). Once granted access to a slave port, a master may perform as many transfers as desired to that port until another master makes a request to the same slave port. The next master in line will be granted access to the slave port if the current master has no pending access request. As an example of arbitration in round-robin mode, assume the XBAR is implemented with master ports 0, 1, 4 and 5. If the last master of the slave port was master 1, and master 0, 4 and 5 make simultaneous requests, they will be serviced in the order 4, 5 and then 0. Parking may still be used in a round-robin mode, but will not affect the round-robin pointer unless the parked master actually performs a transfer. Handoff occurs to the next master in line after one cycle of arbitration. If the slave port is put into low power park mode the round- robin pointer is reset to point at master port 0, giving it the highest priority. Parking If no master is currently requesting the slave port, the slave port is parked. The slave port parks in one of three places, indicated by the value of the PCTL field in the XBAR_SGPCR.

If park-on-specific master mode is selected, the slave port parks on the master designated by the PARK field. When the master accesses the slave port again, a one clock arbitration penalty is incurred only for an access request made by another master port to the slave port. No other arbitration penalties are incurred. All other masters pay a one clock penalty.
If park-on-last (POL) mode is selected, then the slave port parks on the last master to access it, passing that master’s signals through to the slave bus. When the master accesses the slave port again, no other arbitration penalties are incurred except that a one clock arbitration penalty is incurred for each access request to the slave port made by another master port. All other masters pay a one clock penalty.
If the low-power-park (LPP) mode is selected, then the slave port enters low-power park mode. It is not under control by any master and does not transmit any master signals to the slave bus. All slave bus activity halts because all slave bus signals are not toggling. This saves power if the slave port is not used for some time. However,

Multi-Layer AHB Crossbar Switch (XBAR) RM0029 244/1740 Doc ID 15177 Rev 8 when a master does make a request to a slave port parked in low-power-park, a one clock arbitration delay is incurred to get ownership of the slave port.

9.3.2 Priority assignment

Each master port needs to be assigned a unique 3-bit priority level. If an attempt is made to program multiple master ports with the same priority level within a register (MPR) the XBAR will respond with an error and the registers will not be updated.

10 Peripheral Bridge (PBRIDGE)

switch bus and the lower-bandwidth peripheral bus.

10.1 PBRIDGE features

Is only meant for slave peripherals
Supports 32-bit peripherals (byte, halfword, and word reads and write are supported to each)
Supports a pair of accesses for 64-bit fetches

10.2 PBRIDGE modes of operation

The PBRIDGE has only one operating mode.

10.3 PBRIDGE block diagram

Figure 51. PBRIDGE interface

10.4 PBRIDGE signal description

The PBRIDGE has no external signals.

10.5 PBRIDGE functional description

individual module selects for peripheral devices.

10.5.1 Read cycles

10.5.2 Write cycles

10.6 Memory map and register description

10.6.1 Memory map

The module has multiple registers with the same register name (MPCR, PACR, OPACR), each at a different address offset.
Each register has multiple similarly-named fields, each with a different number.
Each field has subfields as defined elsewhere in this section. Accesses to registers or register fields marked as reserved will return zeros on reads, and will be ignored on writes.

Table 53. PBRIDGE registers

This memory range contains reserved areas. See Table 54.

Table 53. PBRIDGE registers (continued) Table 54. PBRIDGE memory map

4 Reserved

8 Reserved

4 Reserved OPACR2

7 Reserved OPACR3

8 Reserved OPACR7

2 Reserved OPACR7

2 Reserved

10.6.2 Register descriptions

Each MPCR register contains one or more 4-bit fields, called MPCRn, as shown in Table 54. chapter for a list of master numbers and names. Each MPCRn field has the structure described in Figure 52 and Table 55. Figure 52. MPCR n field structure Each PACR register contains one or more 4-bit fields, called PACRn, as shown in Table 54. of modules and their corresponding numbers are shown in Table 58. Table 55. MPCR n field structure descriptions This bit determines whether the master is trusted for read accesses. 0 This master is not trusted for read accesses. 1 This master is trusted for read accesses. This bit determines whether the master is trusted for write accesses. 0 This master is not trusted for write accesses. 1 This master is trusted for write accesses. This bit determines how the privilege level of the master is determined. 0 Accesses from this master are forced to user-mode. 1 Accesses from this master are not forced to user-mode. Table 56. MPCR register fields

Each PACRn field has the structure described in Figure 53 and Table 57. Figure 53. PACR n field structure Table 57. PACR n field structure descriptions This bit determines whether the peripheral requires supervisor privilege level for access. 0 This peripheral does not require supervisor privilege level for accesses. access is initiated on the IPS bus. This bit determines whether the peripheral allows write accesses. 0 This peripheral allows write accesses. error response and no peripheral access is initiated on the IPS bus. This bit determines whether the peripheral allows accesses from an untrusted master. 0 Accesses from an untrusted master are allowed. Table 58. Peripheral Access Control Register (PACR) fields

Table 59. Off-platform Peripheral Access Control Register (OPACR) fields

11 General-Purpose Static RAM (SRAM)

11.1 Introduction

first 32 Kbytes of SRAM is powered by its own power supply pin during standby operation.

11.2 Features

Supports read/write accesses mapped to the SRAM memory from any master
32-Kbyte block powered by separate supply for standby operation
Byte, halfword, word and doubleword addressable
7-bit ECC

11.3 Modes of operation

11.3.1 Normal (Functional) mode

Allows reads and writes of the SRAM memory arrays.

11.3.2 Standby mode

enables a standby regulator.

11.4 Block diagram

The SRAM block diagram is shown in Figure 54. Figure 54. SRAM Block Diagram

160 KB VSTBY32 KB

11.5 External signal description

SRAM is not used, tie the VSTBY pin to VSS.

11.6 Register memory map

The internal SRAM has no registers. Registers for the SRAM ECC are located in the ECSM. See Chapter 18: Error Correction Status Module (ECSM).

11.7 Functional description

SRAM. For more information, see Section 11.9, Initialization and application information.

11.8 SRAm ecc mechanism

Detects and corrects all 1-bit errors
Detects and flags all 2-bit errors as non-correctable errors SRAM does not detect all errors greater than 2 bits. Internal SRAM writes are done on byte boundaries:
1 byte (0:7 bits)
2 bytes (0:15 bits)
4 bytes or 1 word (0:31 bits) If the entire 32 data bits are written to SRAM, no read operation is performed and the ECC is calculated across the 32 bits of data. The 7-bit ECC is appended to the data segment and written to SRAM. If the write operation is less than the entire 32-bit data width (1- or 2-byte segment), the following occurs:

Table 60. SRAM memory map

The ECC mechanism checks the entire 32 bits of data for errors, detecting and either

correcting or flagging errors.

The write data bytes (1- or 2-byte segment) are merged with the corrected 32 bits on
The ECC is then calculated on the resulting 32 bits formed in the previous step.
The 7-bit ECC result is appended to the 32 bits from the data, and the 39-bit value is

11.8.1 Access timing

11.8.2 Reset effects on SRAM accesses

to memory unless the region is set for write-through mode. Table 61. Number of wait states required for RAM operation

Applies if additional SRAM read wait state in ECSM_MUDCR is disabled
Applies if additional SRAM read wait state in ECSM_MUDCR is enabled

General-Purpose Static RAM (SRAM) RM0029 254/1740 Doc ID 15177 Rev 8

11.9 Initialization and application information

To use the SRAM, the ECC must check all bits that require initialization after power on. Use either a 32-bit or 64-bit cache-inhibited write to each SRAM location to initialize the SRAM array as part of the application initialization code. All writes must specify an even number of registers performed on 32-bit or 64-bit word-aligned boundaries respectively. If the write is not the entire 32 bits (8 or 16 bits), a read/modify/write operation is generated that checks the ECC value upon the read. See Section 11.8, SRAm ecc mechanism. Note: You must initialize SRAM, even if the application does not use ECC reporting.

11.9.1 Example code

To initialize SRAM correctly, use a store multiple word (stmw) instruction to implement 64- bit writes to all SRAM locations. The stmw instruction concatenates two 32-bit registers to implement a single 64-bit write. To ensure the writes are 64 bits, specify an even number of registers and write on 64-bit word-aligned boundaries. The following example code illustrates the use of the stmw instruction to initialize the SRAM ECC bits. init_RAM: lis r11,0x4000 # base address of the SRAM, 64-bit word aligned ori r11,r11,0 # not needed for this address but could be for others li r12,1536 # loop counter to get all of SRAM; # 192*1024/4 bytes/32 GPRs =1536 mtctr r12 init_ram_loop: stmw r0,0(r11) # write all 32 GPRs to SRAM addi r11,r11,128 # inc the ram ptr; 32 GPRs * 4 bytes = 128 bdnz init_ram_loop # loop for 192K of SRAM blr # done

Doc ID 15177 Rev 8 255/1740

12 Flash memory

12.1 Introduction

This section presents information about the following components on this device:

The flash memory blocks
The platform flash memory controller The primary function of the flash memory module is to serve as electrically programmable and erasable non-volatile memory. The NVM memory can be used for instruction and data storage. The block is a non-volatile solid-state silicon memory device consisting of blocks of single-transistor storage elements, an electrical means for selectively adding (programming) and removing (erasing) charge from these elements, and a means of selectively sensing (reading) the charge stored in these elements. The flash is addressable by word (32 bits) and page (128 bits). There are two flash array blocks (Flash_A and Flash_B). Within each flash block are two functional units: the flash core (FC) and the memory interface (MI). The FC is composed of arrayed non-volatile storage elements, sense amplifiers, row selects, column selects, charge pumps, and redundancy logic. The arrayed storage elements in the FC are subdivided into physically separate units referred to as blocks. The MI contains the registers and logic which control the operation of the FC. The MI is also the interface to the platform flash bus interface unit (PFBIU). The flash array’s core has three address spaces: low-address space, mid-address space, and high-address space (see Figure 55).

Figure 55. Flash segmentation

12.1.1 Block diagram

Figure 56. Flash system block diagram array (see Section 12.2, External signal description ).

258/1740 Doc ID 15177 Rev 8

12.1.2 Features

The flash memory module has these major features:

Support for a 64-bit data bus for instruction fetch
Support for a 32-bit data bus for CPU loads and DMA access. Byte, halfword, word and doubleword reads are supported. Only aligned word and doubleword writes are supported.
Configurable read buffering and line prefetch support. Device flash has 2 sets of 4 line read buffers—1 set for the 128-bit wide low- and medium-address space and 1 set for the 256-bit wide high address space.
Hardware and software configurable(e) read and write access protections on a per- master basis
Interface to the flash array controller is pipelined with a depth of 1, allowing overlapped accesses to proceed in parallel for interleaved or pipelined flash array designs.
Configurable access timing allowing use in a wide range of system frequencies.
Multiple-mapping support and mapping-based block access timing (0–31 additional cycles) allowing use for emulation of other memory types
Software programmable block program/erase restriction control for low, mid and high address spaces
Erase of selected block(s)
Read page size of 128 bits (low/mid-address space) and 256 bits (for high-address space)
ECC with single-bit correction, double-bit detection
Minimum program size is 2 consecutive 32 bit words, aligned on a 0-modulo-8 byte address, due to ECC.
Embedded hardware program and erase algorithm
Read-while-write with multiple partitions
Erase suspend, program suspend and erase-suspended program
Automotive flash which meets automotive endurance and reliability requirements
Shadow information stored in non-volatile shadow block
Independent program/erase of the shadow block

12.1.3 Modes of operation

User mode is the default operating mode of the flash module. In this mode, it is possible to read and write, program and erase the flash module. e. Software executing from flash must not write to register s that control flash behavior, e.g., wait state settings or prefetch enable/disable. Doing so can cause data corruption. On SPC564A74xx, SPC564A80xx devices these registers include BIUCR, BIUAPR, and BIUCR2.Further, fl ash configuration registers should be written only with 32-bit write operations to avoid any issues associ ated with register “incoherency” caused by bit fields spanning smaller size (8- and 16-bit) boundaries.

12.2 External signal description

12.3 Memory map and registers

This section provides a detailed description of all flash memory registers.

12.3.1 Module memory map

registers only with 32-bit accesses. Table 62. Flash memory map

For read-while-write operations, the shadow row behaves as if it is in all partitions.

Table 62. Flash memory map (continued) Table 63. Flash Shadow block mapping Table 64. Flash configuration register memory map

12.3.2 Register descriptions

FLASH_A_REGS_BASE = 0xC3F8_8000
Register is only accessible via Flas h A. Treat as “Reserved” in Flash B.

Table 64. Flash configuration register memory map (continued)

Figure 57. Module Configur ation Register (MCR) Table 65. MCR field description The value of the SIZE field is dependent upon the size of the flash module. SIZE is read only.

128 KB of LAS available, and no MAS or HAS available)

The value of the LAS field corresponds to the configuration of the Low-Address Space. LAS is read only. The value of the MAS field corresponds to the configuration of the Mid-Address Space. MAS is read only.

EER provides information on previous reads. If a double bit detection occurred, the EER bit is set to a 1. 0: Reads are occurring normally. 1: An ECC Error occurred during a previous read.

This bit must then be cleared, or a reset must occur before this bit returns to a 0 state. This bit may

cleared to a 0 by writing a 1 to the register location. A write of 0 has no effect. 0: Reads are occurring normally. 1: A Read While Write Error occurred during a previous read. a 0 by writing a 1 to the register location. A write of 0 has no effect. 0: Reads are occurring without corrections. 1: A Single Bit Correction occurred during a previous read. 0: Shadow address space is disabled for program/erase and main address space enabled. 1: Shadow address space is enabled for program/erase and main address space disabled. EHV which initiates a high voltage operation. DONE is cleared of resuming a suspended operation. 1 to 0 transition of EHV which aborts a high voltage operation. 0: Flash is executing a high voltage operation. 1: Flash is not executing a high voltage operation. Table 65. MCR field description (continued)

cleared, indicating the sequence failed. PEG is set to a 1 when the module is reset. PEG is read only. happens in an erase-suspended program operation. 0: Flash is not executing a program sequence. 1: Flash is executing a program sequence. erase may corrupt FC data. This should be avoided due to reliability implications. places the flash module in program suspend. The module enters suspend within this transition. exit program suspend and clear DONE while EHV is low. PSUS is cleared on reset. 0: Program sequence is not suspended. 1: Program sequence is suspended. ERS is used to set up flash for an erase operation. A 0 to 1 transition of ERS initiates an erase sequence. high. ERS is cleared on reset. 0: Flash is not executing an erase sequence. 1: Flash is executing an erase sequence.

specific state. These write locks are covered on a bit by bit basis in the preceding section. module in an illegal state are detailed here. bit changing priorities are detailed in Table 66. cannot exit erase suspend and clear DONE while EHV is low. ESUS is cleared on reset. 0: Erase sequence is not suspended. 1: Erase sequence is suspended. erase suspend before setting PGM. current program/erase high voltage operation. indeterminate data after an abort. 0: Flash is not enabled to perform a high voltage operation. 1: Flash is enabled to perform a high voltage operation. executing an erase on the affected blocks.

existing write locks or do not put the flash in an illegal state. For example, setting ERS and PGM simultaneously results in only ERS being set. determines the final lock status. Table 66. MCR bit set/clear priority levels

4 ESUS, PSUS

Figure 58. Low/Mid-Address Space Block Lock Register (LMLR)

Table 67. LMLR field descriptions register writes. LME is a status bit only, and may not be written or cleared, and the reset value is 0. must be written to the LMLR. 0: Low/Mid-Address Locks are disabled, and can not be modified. 1: Low/Mid-Address Locks are enabled to be written. This SLOCK bit is used to lock the shadow block from programs and erases. 1: Shadow block is locked for program and erase. 0: Shadow block is available to receive program and erase pulses. of the requested operation. Likewise, SLOCK is not writable if a high voltage operation is suspended. SLOCK is also not writeable during UTest operations, when AIE is high. SLOCK bit (assuming erased shadow location) is locked. SLOCK is not writable unless LME is high. continues until all blocks are accounted. operation is suspended. MLOCK is also not writeable during UTest operations, when AIE is high. value of the LOCK bits (assuming erased shadow location) is locked. block), and register writes have no effect. MLOCK is not writable unless LME is high. continues until all blocks are accounted. For more details on LLOCK, please see MLOCK field description. LLOCK is not writable unless LME is high.

from program or erase. An “OR” of LMLR and SLMLR determine the final lock status. Figure 59. High-Address Space Block Lock Register (HLR) Table 68. HLR field descriptions This bit is used to enable the Lock registers (HBLOCK) to be set or cleared by register writes. password B2B2_2222h must be written to the HLR. 0: High-Address Locks are disabled, and can not be modified. 1: High-Address Locks are enabled to be written. until all blocks are accounted. HBLOCK is not writable unless HBE is high.

blocks to be operated on during erase. Figure 60. Secondary Low/Mid-Address Space Block Lock Register (SLMLR) Table 69. SLMLR field descriptions password 0xC3C3_3333 must be written to the SLMLR. 0: Secondary Low/Mid-Address Locks are disabled, and can not be modified. 1: Secondary Low/Mid-Address Locks are enabled to be written. writable unless SLE is high.

be operated on during erase. Figure 61. Low/Mid-Address Space Block Select Register (LMSR) Table 70. LMSR field descriptions also not writable during UTest operations, when AIE is high. also not writable during UTest operations, when AIE is high.

Table 72. AR field descriptions The SAD register is not writable. 0: Address Captured is from Main Array Space. 1: Address Captured is from Shadow Array Space. fails simultaneously. This address is always a Double Word address that selects 64 bits. writability of the ADDR field. Figure 64. Bus Interface Unit Configuration Register (BIUCR)

Table 73. BIUCR field descriptions requesting master. These bits are cleared by hardware reset. This field is used to control the number of cycles between pipelined access requests. The settings for APC and RWSC should be the same.

7 External Bus Interface (EBI)

This field is set to 0b111 by hardware reset. The settings for APC and RWSC should be the same. misses. In all situations when enabled, only a single prefetch is initiated on each buffer miss or hit. This field is cleared by hardware reset. 00: No prefetching or buffering is performed. 01: The referenced line is prefetched on a buffer miss, that is, prefetch on miss. buffer hit (if not already present), that is, prefetch on miss or hit. 0: The line read buffers are disabled from satisfying read requests, and all buffer valid bits are cleared. the buffers are successfully filled.

Valid settings are specif ied in the device datasheet.

Table 73. BIUCR field descriptions (continued)

Figure 65. Bus Interface Unit Access Protection Register (BIUAPR) Table 74. BIUAPR field descriptions the master ID of a requesting master.

only writable when the flash is put into UTest mode by writing a passcode. Figure 66. Bus Interface Unit Configuration Register 2 (BIUCR2) Table 75. BIUCR2 field descriptions block of the flash array. An erased or unprogrammed flash sets this field to 0b11. This field controls the configuration of both the 4 x 128 and 4 x 256 line buffers. and buffers 2 and 3 for data accesses.

Figure 67. User Test 0 (UT0) Register Table 76. UT0 field descriptions 0xF9F9_9999 must be written to the UT0 register. 0: Single Bit Corrections observation is disabled. 1: Single Bit Correction observation is enabled. Hamming code is used, or a modified Hsiao code is used. 0: Default ECC Algorithm, modified Hamming algorithm. 1: Optional/Alternative ECC Algorithm, modified Hsiao algorithm. 0: Margin reads are not enabled. 1: Margin reads are enabled during Array Integrity Checks.

The User Test 1 (UT1) Register provides added controllability to UTest. set. MRV is not writable if AID is low. 0: Zero’s margin reads are requested. 1: One’s margin reads are requested. as UTI is being cleared to a 0. 0: Data read is from the flash array. 1: Data read is from the DSI and DAI registers. run the proprietary sequence. If MRE is set, AIS has no effect. 0: Array integrity sequence is proprietary sequence. 1: Array integrity sequence is sequential. simultaneously writable to a 1 as UTI is being cleared to a 0. 0: Array integrity checks are not enabled. 1: Array integrity checks are enabled. (UMISR registers) can be checked. AID can not be written, and is status only. 0: Array integrity check is ongoing. 1: Array integrity check is done. Table 76. UT0 field descriptions (continued)

Table 79. UMISR n field descriptions The UMISR provides a means to calculate an MISR during Array Integrity operations. MISR[6], MISR[5], MISR[1], and MISR[0]. The result of the “exclusive OR” is shifted left on each read. The MISR is used in Array Integrity operations. recalculated and the previous value is retained. 1) Assert reset after each user margin read sequence so that MISRs can be written again. 2) Do a dummy program to a locked block after user margin read.

Doc ID 15177 Rev 8 283/1740

12.4 Functional description

12.4.1 Flash User Mode

In user mode the flash module can be read and written (register writes and interlock writes), programmed or erased. The following subsections define all actions that can be performed in user mode.

12.4.2 Flash Read and Write

The default state of the flash module is read. The main and shadow address space can be read only in the read state. The module configuration register (MCR) is always available for read. The flash module enters the read state on reset. The flash module is in the read state under three sets of conditions:

The read state is active when PGM = 1 or ERS = 1 in the MCR and high-voltage operation is ongoing (read while write). Note: Reads done to the partition(s) being operated on (either erased or programmed) will result in an error and the RWE bit in the MCR will be set.
The read state is active when PGM = 1 and PSUS = 1 in the MCR (program suspend).
The read state is active when ERS = 1 and ESUS = 1 and PGM = 0 in the MCR (erase suspend). Note: FC reads are done through the BIU. In many cases the BIU will do page buffering to allow sequential reads to be done with higher performance. This can create a data coherency issue that must be handled with software. Data coherency can be an issue after a program, erase, or shadow row operations. In flash user mode, registers can be written. Array can be written to do interlock writes. Array reads attempted to invalid locations will result in indeterminate data. Invalid locations occur when addressing is done to blocks that do not exist in non 2 n array sizes. Interlock writes attempted to invalid locations (due to blocks that do not exist in non 2n array sizes), will result in an interlock occurring, but attempts to program or erase these blocks will not occur since they are forced to be locked.

12.4.3 Read While Write (RWW)

The flash core is divided into partitions. Partitions always comprise two or more blocks. Partitions are used to determine read-while-write (RWW) groupings. While a write (program or erase) is being done within a given partition, a read can be simultaneously executed to any other partition. Partitions are listed in Table 62. Each partition in high address space comprises two 128 KB blocks. The shadow block has unique RWW restrictions described in Section 12.4.7, Flash shadow block. The FC is also divided into blocks to implement independent erase or program protection. The shadow block exists outside the normal address space and is programmed, erased, and read independently of the other blocks. The shadow block is included to support systems that require NVM for security or system initialization information. A software mechanism is provided to independently lock or unlock each block in high-, mid- , and low-address space against program and erase. Two hardware locks are also provided to enable/disable the FC for program/erase. See Section , Software Locking for more information.

284/1740 Doc ID 15177 Rev 8

12.4.4 UTest Mode

UTest mode is a mode that customers can put the flash module in to do specific tests to check the integrity of the Flash module. Array Integrity Self Check Array Integrity is checked using a pre-defined address sequence (based on UT0[AIS]), and this operation is executed on selected blocks. The data to be read is customer specific, thus a customer can provide user code into the flash and the correct MISR value is calculated. The customer is free to provide any random or non-random code, and a valid MISR signature is calculated. Once the operations is completed, the results of the reads can be checking by reading the MISR value, to determine if an incorrect read, or ECC detection was noted. Array integrity is controlled by the system clock (IPG), and it is required that the Read Wait States and Address Pipelined control registers in the BIU be set to match the user defined frequency being used. Note: While Array Integrity is being executed, flash memory array accesses through the BIU should not be requested. The Array Integrity Check consists of the following sequence of events: 1. Enable UTest mode. 2. Select the block, or blocks to receive array integrity check by writing ones to the appropriate registers in LMS or HBS registers. Note: Locked Blocks can be tested with Array Integrity if selected in LMS and HBS. Note: It is not possible to do UTest operations on the shadow block. 3. If desired, Set the UT0[AIS] bit to 1 for sequential addressing only. Note: For normal integrity checks of the flash memory, sequential addressing is recommended. If it is required to more fully check the read path (in a diagnostic mode), it is recommend that AIS be left at 0, to use the address sequence that checks the read path more fully, and examine read transitions. This sequence takes more time. 4. Seed the MISR UMISR0 through UMISR4 with desired values. 5. Set the UT0[AIE] bit. a) If desired, the Array Integrity operation may be aborted prior to UT0[AID] going high. This may be done by clearing the UT0[AIE] bit and then continuing to the next step. It should be noted that in the event of an aborted array integrity check the MISR registers will contain a signature for the portion of the operation that was completed prior to the abort, and will not be deterministic. Prior to doing another array integrity operation, the UMISR0, UMISR1, UMISR2, and UMISR3 registers may need to be initialized to the desired seed value by doing register writes. 6. Wait until the UT0[AID] bit goes high. 7. Read values in the MISR registers (UMISR0 through UMISR4) to ensure correct signature. 8. Write a logic 0 to the UT0[AIE] bit. Factory Margin Read Factory Margin Read must be done following “Initial Factory Conditions”. One Factory Margin Read is allowed per erase.

Doc ID 15177 Rev 8 285/1740 Factory Margin Read may be done to selected and unlocked blocks by combining UT0[MRE] and UT0[MRV] with the Array Integrity check. If UT0[MRE] is set, UT0[AIS] has no affect, and the reads will be done sequentially. The data to be read is customer specific, thus a customer can provide user code into the flash and the correct MISR value is calculated. The customer is free to provide any random or non-random code, and a valid MISR signature is calculated. Once the operations is completed, the results of the reads can be checking by reading the MISR value. Factory Margin Read is a self timed event, and is independent of system clocks, or wait states selected. Margin ECC corrections or detections are not done during the Factory Margin Read test: 1. Enable UTest mode. 2. Select the block, or blocks to be receive margin read check by writing ones to the appropriate registers in LMS or HBS/EHS registers. Make sure that selected blocks are also unlocked. Note: It is not possible to do UTest operations on the shadow block. Note: It is possible to do User Mode array reads during the Factory Margin Read test, if desired, but the partition rules for Read While Write used during program and erase are in effect during Factory Margin Reads. 3. Set the UT0[MRE] bit. 4. Set the UT0[MRV] bit to desired value depending on it is desired to do One’s Margin or Zero’s Margin. 5. Seed the MISR UMISR0 thru UMISR4 with desired values. 6. Set the UT0[AIE] bit. a) If desired, the Margin Read operation may be aborted prior to UT0[AID] going high. This may be done by clearing the UT0[AIE] bit and then continuing to the next step. It should be noted that in the event of an aborted Margin Read check the MISR registers will contain a signature for the portion of the operation that was completed prior to the abort, and will not be deterministic. 7. Wait until the UT0[AID] bit goes high. 8. Read values in the MISR registers (UMISR0 through UMISR4) to ensure correct signature. 9. Write a logic 0 to the UT0[AIE] bit. Note: If it is desired to do two or more margin reads, and it is desired to re-seed the MISR, a reset must be done between operations. If the subsequent margin reads can be done with the previously calculated MISR value, then a reset is not required. ECC Logic Check ECC logic can be checked by providing data to be read in the UT0[DSI], UT1[DAI] and/or UT2[DAI] registers. Then array reads can be done, ensuring expected results. The ECC Logic Check consists of the following sequence of events:

286/1740 Doc ID 15177 Rev 8 1. Enable UTest mode. 2. Write UT0[EIE] to 1. 3. Write UT0[DSI], UT1[DAI] and/or UT2[DAI] bits to provide data and check bit values to be read. Single or Double bit detections/corrections can be simulated by properly choosing Data and Check Bit combinations. 4. Write double word address to receive the data inputted in step 3 into the ADR register. 5. Reads can now be done through the BIU in a Read Request type fashion. In the event of a BIU read requested from an address that matches the address in the ADR register, expected data, and corrections or detections should be observed based on data written into the UT0[DSI], UT1[DAI] and/or UT2[DAI] registers. MCR[EER] and MCR[SBCSBC] can be checked to evaluate the status of reads done. Note: In the event of an ECC error or Single Bit Correction, during the ECC Logic Check (UTO[EIE] high), the ADR register will not be loaded, and the address tagged to receive the UT0[DSI], UT1[DAI] and/or UT2[DAI] values will be persevered. 6. Once completed, clear the UT0[EIE] bit to 0.

12.4.5 Flash Programming

Programming changes the value stored in an array bit from logic 1 to logic 0 only. Programming cannot change a stored logic 0 to a logic 1. Addresses in locked/disabled blocks cannot be programmed. The user can program the values in any or all of four words within a page in a single program sequence. Word addresses are selected using bits 3:2 of the page-bound word. Whenever a program operation occurs, ECC bits are programmed. ECC is handled on a 64- bit boundary. Thus, if only one word in any given 64-bit ECC segment is programmed, the adjoining word (in that segment) should not be programmed because ECC calculation has already completed for that 64-bit segment. Attempts to program the adjoining word will probably result in an operation failure. It is recommended that all programming operations be from 64 bits to 128 bits, and be 64-bit aligned. The programming operation should completely fill selected ECC segments within the page. The program operation consists of the following sequence of events: 1. Change the value in the MCR[PGM] bit from a 0 to a 1. Note: Ensure the block that contains the address to be programmed is unlocked. See Section , Low/Mid-Address Space Block Lock Register (LMLR), Section , High-Address Space Block Lock Register (HLR) and Section , Secondary Low/Mid-Address Space Block Lock Register (SLMLR) for more information. 2. Write the first address to be programmed in the flash module with the program data. This write is referred to as a program data interlock write. An interlock write may be either be an aligned word or doubleword. 3. If more than one word or doubleword is to be programmed, write each additional address in the page with data to be programmed. This is referred to as a program data write. All unwritten data words default to 0xFFFF_FFFF. 4. Write a logic 1 to the MCR[EHV] bit to start the internal program sequence or skip to step 9 to terminate.

Doc ID 15177 Rev 8 287/1740 5. Wait until the MCR[DONE] bit goes high. 6. Confirm MCR[PEG] = 1. 7. Write a logic 0 to the MCR[EHV] bit. 8. If more addresses are to be programmed, return to step 2. 9. Write a logic 0 to the MCR[PGM] bit to terminate the program sequence. The program sequence is presented graphically in Figure 75. The program suspend operation detailed in Figure 75 is discussed in Section , Flash Program Suspend/Resume. The first write after a program is initiated determines the page address to be programmed. Program may be initiated with the 0 to 1 transition of the MCR[PGM] bit or by clearing the MCR[EHV] bit at the end of a previous program. This first write is referred to as an interlock write. If the program is not an erase-suspended program, the interlock write determines if the shadow or normal array space will be programmed and causes MCR[PEAS] to be set/cleared. In the case of an erase-suspended program, the value in MCR[PEAS], is retained from the erase. An interlock write must be performed before setting MCR[EHV]. The user may terminate a program sequence by clearing MCR[PGM] prior to setting MCR[EHV]. If multiple writes are done to the same location the data for the last write is used in programming. While MCR[DONE] is low, MCR[EHV] is high, and MCR[PSUS] is low, the user may clear MCR[EHV], resulting in a program abort. A program abort forces the module to step 8 of the program sequence. An aborted program will result in MCR[PEG] being set low, indicating a failed operation. The data space being operated on before the abort will contain indeterminate data. The user may not abort a program sequence while in program suspend. Caution: Aborting a program operation will leave the flash core addresses being programmed in an indeterminate data state. This may be recovered by executing an erase on the affected blocks.

Figure 75. Program Sequence

Doc ID 15177 Rev 8 289/1740 Software Locking A software mechanism is provided to independently lock/unlock each high-, mid-, and low- address space against program and erase. Software locking is done through the LMLR (low/mid-address space block lock register), SLMLR (secondary low/mid-address space block lock register), or HLR (high-address space block lock register). These can be written through register writes and read through register reads. When the program/erase operations are enabled through hardware, software locks are enforced through doing register writes. Flash Program Suspend/Resume The program sequence may be suspended to allow read access to the flash core. It is not possible to erase or program during a program suspend. Interlock writes should not be attempted during program suspend. A program suspend can be initiated by changing the value of the MCR[PSUS] bit from a 0 to a 1. MCR[PSUS] can be set high at any time when MCR[PGM] and MCR[EHV] are high. A 0 to 1 transition of MCR[PSUS] causes the flash module to start the sequence to enter program suspend, which is a read state. The module is not suspended until MCR[DONE] = 1. At this time flash core reads may be attempted. After it is suspended, the flash core may be read only. Reads to the blocks being programmed/erased return indeterminate data. The program sequence is resumed by writing a logic 0 to MCR[PSUS]. MCR[EHV] must be set to a 1 before clearing MCR[PSUS] to resume operation. When the operation resumes, the flash module continues the program sequence from one of a set of predefined points. This may extend the time required for the program operation.

12.4.6 Flash Erase

Erase changes the value stored in all bits of the selected block(s) to logic 1. An erase sequence operates on any combination of blocks in the Low, Mid or High Address Space, or the shadow block. The erase sequence is fully automated within the flash. The user only needs to select the blocks to be erased and initiate the erase sequence. Locked/disabled blocks cannot be erased. If multiple blocks are selected for erase during an erase sequence, the blocks are erased sequentially starting with the lowest numbered block and terminating with the highest. The erase sequence consists of the following sequence of events: The erase sequence consists of the following sequence of events: 1. Change the value in the MCR[ERS] bit from 0 to a 1. 2. Select the block, or blocks, to be erased by writing 1s to the appropriate bits in LMSR or HSR. If the shadow row is to be erased, this step may be skipped, and LMSR and HSR are ignored. For shadow row erase, see Section 12.4.7, Flash shadow block for more information. Note: Lock and select are independent. If a block is selected and locked, no erase will occur. See Section , Low/Mid-Address Space Block Lock Register (LMLR), Section , High-Address Space Block Lock Register (HLR) and Section , Secondary Low/Mid-Address Space Block Lock Register (SLMLR) for more information.

290/1740 Doc ID 15177 Rev 8 3. Write to any address in flash. This is referred to as an erase interlock write. The interlock write causes the values of SOC specific shadow enable to be captured and causing MCR[PEAS] to be set/cleared. 4. Write a logic 1 to the MCR[EHV] bit to start an internal erase sequence or skip to step 9 to terminate. 5. Wait until the MCR[DONE] bit goes high. 6. Confirm MCR[PEG] = 1. 7. Write a logic 0 to the MCR[EHV] bit. 8. If more blocks are to be erased, return to step 2. 9. Write a logic 0 to the MCR[ERS] bit to terminate the erase. The erase sequence is presented graphically in Figure 76. The erase suspend operation detailed in Figure 76 is discussed in Section , Flash erase suspend/resume. After setting MCR[ERS], one write, referred to as an interlock write, must be performed before MCR[EHV] can be set to a 1. This interlock causes the values of SOC specific shadow enable to be captured. Data words written during erase sequence interlock writes are ignored. The user may terminate the erase sequence by clearing MCR[ERS] before setting MCR[EHV]. An erase operation may be aborted by clearing MCR[EHV] assuming MCR[DONE] is low, MCR[EHV] is high, and MCR[ESUS] is low. An erase abort forces the module to step 8 of the erase sequence. An aborted erase results in MCR[PEG] being set low, indicating a failed operation. The blocks being operated on before the abort contain indeterminate data. The user may not abort an erase sequence while in erase suspend. Warning: Aborting an erase operation will leave the flash core blocks being erased in an indeterminate data state. This may be recovered by executing an erase on the affected blocks. Flash erase suspend/resume The erase sequence may be suspended to allow read access to the FC. The erase sequence may also be suspended to program (erase-suspended program) the FC. A program started during erase suspend can in turn be suspended. Only one erase suspend and one program suspend are allowed at a time during an operation. It is not possible to erase during an erase suspend, or program during a program suspend. During suspend, all reads to FC locations targeted for program and blocks targeted for erase return indeterminate data. Programming locations in blocks targeted for erase during erase- suspended program may result in corrupted data. Read While Write may also be used to read the array during an erase sequence providing the read is to a partition not selected for erase. An erase suspend can be initiated by changing the value of the MCR[ESUS] bit from a 0 to a 1. MCR[ESUS] can be set to a 1 at any time when MCR[ERS] and MCR[EHV] are high and MCR[PGM] is low. A 0 to 1 transition of MCR[ESUS] causes the module to start the sequence which places it in erase suspend. The user must wait until MCR[DONE] = 1 before the module is suspended and further actions are attempted. MCR[DONE] goes high no more than T esus after MCR[ESUS] is set to a 1. Once suspended, the array may be read

Doc ID 15177 Rev 8 291/1740 or a program sequence may be initiated (erase-suspended program). Before initiating a program sequence the user must first clear MCR[EHV]. If a program sequence is initiated the values of SOC specific shadow enable is recaptured. Once the erase-suspended program is completed, the value of PEAS is returned to its “erase” value. FC reads while MCR[ESUS] = 1 from the blocks being erased return indeterminate data. The erase sequence is resumed by writing a logic 0 to MCR[ESUS]. MCR[EHV] must be set to a 1 and MCR[PGM] must be cleared (in the event of an erase suspended program) before MCR[ESUS] can be cleared to resume the operation. The module continues the erase sequence from one of a set of predefined points. This may extend the time required for the erase operation. Warning: Repeated suspends at a high frequency may result in the operation timing out, and the flash module will respond by completing the operation with a fail code (MCR[PEG] = 0), or the operation not able to finish (MCR[DONE] = 1 during Erase operation). The minimum time between erase suspends to ensure this does not occur is Tesrt. Warning: In an erase-suspended program, programming flash locations in blocks which were being operated on in the erase may corrupt flash core data.

Figure 76. Erase sequence

12.4.7 Flash shadow block

Doc ID 15177 Rev 8 293/1740 program the main address space and vice-versa. The user must terminate the shadow erase operation to program or erase the main address space. Note: If an erase of user space is requested, and a suspend is done with attempts to erase suspend program shadow space, this attempted program will be directed to user space as dictated by the state of MCR[PEAS]. Likewise an attempted erase suspended program of user space, while the shadow space is being erased, will be directed to shadow space as dictated by the state of MCR[PEAS]. The shadow block cannot use the RWW feature. After an operation is started in the shadow block, a read cannot be done to the shadow block, or any other block. Likewise, after an operation is started in a block in low-/mid-/high-address space, a read cannot be done in the shadow block. The shadow block contains information about how the lock registers are reset. The first and second words can be used for reset configuration words. All other words can be used for user-defined functions or other configuration words. The shadow block may be locked/unlocked against program or erase by using the LMLR or SLMLR discussed in Section 12.3.2, Register descriptions. Programming the shadow row has similar restrictions to programming the array in terms of how ECC is calculated. See Section 12.4.5, Flash Programming for more information. Only one program is allowed per 64-bit ECC segment between erases. Erase of the shadow row is done similarly as an array erase. See Section 12.4.6, Flash Erase for more information.

12.4.8 Flash reset

A reset is the highest priority operation for the flash and terminates all other operations. The flash uses reset to initialize register and status bits to their default reset values. If the flash is executing a program or erase operation and a reset is issued, the operation will be aborted and the flash will disable the high voltage logic without damage to the high-voltage circuits. Reset aborts all operations and forces the flash into user mode ready to receive accesses. After reset is negated, register accesses can be performed, although it should be noted that registers that require updating from shadow information, or other inputs, cannot read updated values until flash exits reset.

12.4.9 DMA requests

The flash has no DMA requests.

12.4.10 Interrupt requests

The flash has no interrupt requests.

Memory Protection Unit (MPU) RM0029 294/1740 Doc ID 15177 Rev 8

13 Memory Protection Unit (MPU)

13.1 Introduction

The memory protection unit (MPU) provides hardware access control for all memory references generated in a device. Using preprogrammed region descriptors that define memory spaces and their associated access rights, the MPU concurrently monitors all system bus transactions and evaluates the appropriateness of each transfer. Memory references with sufficient access control rights are allowed to complete, but references that are not mapped to any region descriptor or have insufficient rights are terminated with a protection error response. The MPU implements a set of program-visible region descriptors that monitor all system bus addresses. The result is a hardware structure with a two-dimensional connection matrix, where the region descriptors represent one dimension and the individual system bus addresses and attributes are the second dimension.

13.1.1 Features

The MPU has these major features:

Support for 16 memory region descriptors, each 128 bits in size – Specification of start and end addresses provide granularity for region sizes from 32 bytes to 4 GB – MPU is invalid at reset, thus no access restrictions are enforced – 2 types of access control definitions: processor core bus master supports the traditional {read, write, execute} permissions with independent definitions for supervisor and user mode accesses; the remaining non-core bus masters (eDMA, FlexRay, and EBI (f)) support {read, write} attributes – Automatic hardware maintenance of the region descriptor valid bit removes issues associated with maintaining a coherent image of the descriptor – Alternate memory view of the access control word for each descriptor provides an efficient mechanism to dynamically alter the access rights of a descriptor only – For overlapping region descriptors, priority is given to permission granting over access denying as this approach provides more flexibility to system software
Support for two XBAR slave port connections (SRAM and PBRIDGE) – For each connected XBAR slave port (SRAM and PBRIDGE), MPU hardware monitors every port access using the preprogrammed memory region descriptors – An access protection error is detected if a memory reference does not hit in any memory region or the reference is flagged as illegal in all memory regions where it does hit. In the event of an access error, the XBAR reference is terminated with an error response and the MPU inhibits the bus cycle being sent to the targeted slave device – 64-bit error registers, one for each XBAR slave port, capture the last faulting address, attributes, and detail information f. EBI not available on all packages and is not available, as a master, for customer.

13.1.2 Modes of operation

The MPU does not support any special modes of operation.

13.2 MPU-to-XBAR slave port mapping

13.3 Signal description

The MPU does not include any external signals.

13.4 Memory map and registers

This section provides a detailed description of all MPU registers.

13.4.1 Module memory map

name and mnemonic, and list the type of accesses allowed. register) generate an error termination. Table 80. MPU-to-XBAR slave port mapping Table 81. MPU Memory Map

Table 81. MPU Memory Map (continued)

13.4.2 Register descriptions

register) generate a bus error termination. information. A global MPU enable/disable bit is also included in this register. Figure 77. MPU Control/Error Status Register (MPU_CESR)

Each SPERR bit can be cleared by writing a one to the bit location.

Table 82. MPU_CESR field descriptions detect the presence of a captured error.

0 The corresponding MPU_EAR n/MPU_EDRn registers do not contain an unread captured error

1 The corresponding MPU_EAR n/MPU_EDRn registers do contain an unread captured error

Bit 0 indicates an SRAM access protection error and bit 1 a peripheral bridge protection error. This 4-bit read-only field specifies the number of slave ports [1–8] connected to the MPU. This field reads as 0b0010 on the SPC564A74xx, SPC564A80xx at reset, indicating two slaves.

MPU_EDRn register at the same time. This bit provides a global enable/disable for the MPU.

0 The MPU is disabled

1 The MPU is enabled

While the MPU is disabled, all accesses from all bus masters are allowed.

See Table 80 in Section 13.2, MPU-to-XBAR slave port mapping , for MPU slave port details.

Table 82. MPU_CESR field descriptions (continued) g. See Table 80 in Section 13.2, MPU-to-XBAR slave port mapping , for MPU slave port details. Figure 78. MPU Error Address Register, Slave Port n (MPU_EARn)

in this read-only register and the corresponding bit in the MPU_CESR[SPERR] field is set. Table 83. MPU_EAR n field descriptions This read-only field is the reference address from slave port n that generated the access error. h. See Table 80 in Section 13.2, MPU-to-XBAR slave port mapping , for MPU slave port details. Figure 79. MPU Error Detail Register, Slave Port n (MPU_EDRn) Table 84. MPU_EDR n field descriptions the hit-qualified access control vector is captured in this field. region descriptor(s), but failed due to a protection error as defined by the specific set bits.

each of the four 32-bit words are detailed in the subsequent sections. the memory region. Writes to this word clear the region descriptor’s valid bit. typically driven by processor cores only; for other bus masters, this field is cleared. determine the bus master that generated the access error.

000 User mode, instruction access

001 User mode, data access

010 Supervisor mode, instruction access

011 Supervisor mode, data access

wired to supervisor, data (0b011). This 1-bit read-only field signals the access type (read, write) of the faulting reference. Table 84. MPU_EDR n field descriptions (continued)

locations do not affect the descriptor’s valid bit.

M0: e200z4 core
M4: eDMA
M6: FlexRay
M7: EBI

Table 86. MPU_RGD n Word 1 field description properly load these region descriptor fields.

Figure 82. MPU Region Descriptor n, Word 2 Register (MPU_RGDn.Word2) Refer to Table 49, in the XBAR chapter, to see the Master ID assignments. Table 87. MPU_RGD n Word 2 field description master ID 4 terminates with an access error and the read is not performed. Bus Master 7 (EBI) is available for Factory Test only. master ID 7 terminates with an access error and the write is not performed. Bus Master 7 (EBI) is available for Factory Test only. master ID 6 terminates with an access error and the read is not performed. master ID 6 terminates with an access error and the write is not performed. master ID 4 terminates with an access error and the read is not performed. master ID 4 terminates with an access error and the write is not performed.

mask, plus the region descriptor’s valid bit. words {0,1,2} of the descriptor. Writes to this word set/clear the valid bit in a normal manner. control n) as stores to these locations do not affect the descriptor’s valid bit. hit evaluation does not include the process identifier.

11 Same access controls as that defined by M0UM for user mode

terminated with an access error (if not allowed by any other descriptor) and the access not performed. Table 87. MPU_RGD n Word 2 field description (continued)

locations do not affect the descriptor’s valid bit. Figure 83. MPU Region Descriptor n, Word 3 Register (MPU_RGDn.Word3) Table 88. MPU_RGD n Word 3 field description included in the region hit determination if MPU_RGDn.Word2[MxPE] is set. Section , Access Evaluation—Hit Determination . write to MPU_RGDn.Word3 sets or clears this bit depending on bit 31 of the write operand.

0 Region descriptor is invalid

1 Region descriptor is valid

the field definitions shown in Table 89 are identical to those presented in Table 87. Figure 84. MPU RGD Alternate Access Control n (MPU_RGDAACn) Table 89. MPU_RGDAAC n field descriptions master ID 4 terminates with an access error and the read is not performed. Bus Master 7 (EBI) is available for Factory Test only. master ID 7 terminates with an access error and the write is not performed. Bus Master 7 (EBI) is available for Factory Test only. master ID 6 terminates with an access error and the read is not performed. master ID 6 terminates with an access error and the write is not performed. These bits must never be set. master ID 4 terminates with an access error and the read is not performed.

13.5 Functional Description

error-terminated XBAR bus cycles.

13.5.1 Access Evaluation

of an access protection violation. identifier, the MPU forces the PID term to be asserted. master 4 terminates with an access error and the write is not performed. terminated with an access error (if not allowed by any other descriptor) and the access not performed. Table 89. MPU_RGDAAC n field descriptions (continued)

RM0029 Memory Protection Unit (MPU) Doc ID 15177 Rev 8 309/1740 Access Evaluation—Privilege Violation Determination While the access evaluation macro is making the region hit determination, the logic is also evaluating if the current access is allowed by the permissions defined in the region descriptor. Using the XBAR supervisor/user mode signals, a set of permissions is generated from the appropriate fields in the region descriptor. The protection violation logic evaluates the access against the effective permissions. The access evaluation macro then uses the hit and permission signals to determine if the current access is allowed and the MPU_EDRn (error detail register) is updated in the event of an error.

13.5.2 XBAR Error Terminations

For each XBAR slave port being monitored, the MPU tests any access for permission violations as above. If a violation occurs, the MPU terminates the bus cycle and reports a protection error for three conditions: 1. If the access does not hit in any region descriptor, a protection error is reported. 2. If the access hits in a single region descriptor and that region signals a protection violation, a protection error is reported. 3. If the access hits in multiple (overlapping) regions and all regions signal protection violations, then a protection error is reported. The third condition reflects that priority is given to permission granting over access denying for overlapping regions as this approach provides more flexibility to system software in region descriptor assignments. For an example of the use of overlapping region descriptors, see Section 13.7, Application Information. When the MPU causes a termination error to occur, the effect on the system depends on the bus master requesting the access. If the error was caused by a core access, a machine check is taken. If the error was caused by an eDMA access, an eDMA source or destination error occurs in the eDMA controller, which can be enabled to provide an interrupt request through the INTC. If the error was caused by a FlexRay access, a controller host interface (CHI) illegal system memory access error occurs in the FlexRay controller, which can be enabled to provide an interrupt request to the INTC.

13.6 Initialization Information

The reset state of MPU_CESR[VLD] disables the entire module. While the MPU is disabled, all accesses from all bus masters are allowed. This state also minimizes the power dissipation of the MPU. The power dissipation of each access evaluation macro is minimized when the associated region descriptor is marked as invalid or when MPU_CESR[VLD] = 0. Typically the appropriate number of region descriptors (MPU_RGDn) are loaded at system startup, including the setting of the MPU_RGDn.Word3[VLD] bits, before MPU_CESR[VLD] is set, enabling the module. This approach allows all the loaded region descriptors to be enabled simultaneously. Once the MPU is enabled, if a memory reference does not hit in any region descriptor, the attempted access is terminated with an error.

Memory Protection Unit (MPU) RM0029 310/1740 Doc ID 15177 Rev 8

13.7 Application Information

In an application’s system, interfacing with the MPU can generally be classified into the following activities: 1. Creation of a new memory region requires loading the appropriate region descriptor into an available register location. When a new descriptor is loaded into a RGD n, it would typically be performed using four 32-bit word writes. As discussed in Section , MPU Region Descriptor n, Word 3 (MPU_RGDn.Word3), the hardware assists in the maintenance of the valid bit, so if this approach is followed, there are no coherency issues associated with the multi-cycle descriptor writes. Deletion/removal of an existing memory region is performed by clearing MPU_RGDn.Word3[VLD]. 2. If only the access rights for an existing region descriptor need to change, a 32-bit write to the alternate version of the access control word (MPU_RGDAACn) would typically be performed. Writes to the region descriptor using this alternate access control location do not affect the valid bit, so there are, by definition, no coherency issues involved with the update. The access rights associated with the memory region switch instantaneously to the new value as the IPS write completes. 3. If the region’s start and end addresses are to be changed, this would typically be performed by writing a minimum of three words of the region descriptor: MPU_RGDn.Word{0,1,3}, where the writes to Word0 and Word1 redefine the start and end addresses respectively and the write to Word3 re-enables the region descriptor valid bit. In many situations, all four words of the region descriptor would be rewritten. 4. Typically, references to the MPU’s programming model would be restricted to supervisor mode accesses from a specific processor(s), so a region descriptor would be specifically allocated for this purpose with attempted accesses from other masters or while in user mode terminated with an error. 5. When the MPU detects an access error, the current XBAR bus cycle is terminated with an error response and information on the faulting reference captured in the MPU_EARn and MPU_EDRn registers. The error-terminated XBAR bus cycle typically initiates some type of error response in the originating bus master. For example, a processor core may respond with a bus error exception, while a data movement bus master may respond with an error interrupt. In any event, the processor can retrieve the captured error address and detail information simply be reading the MPU_E{A,D}Rn registers. Information on which error registers contain captured fault data is signaled by MPU_CESR[SPERR]. 6. Finally, consider the use of overlapping region descriptors. Application of overlapping regions can reduce the number of descriptors required for a given set of access controls. In the overlapping memory space, the protection rights of the corresponding region descriptors are logically summed together (the boolean OR operator). In the following example of a dual-core system, there are four bus masters: the two processors (CP0, CP1) and two DMA engines (eDMA, a traditional data movement engine transferring data between RAM and peripherals, and FlexRay, a second engine transferring data to/from the RAM only). Consider the region descriptor assignments shown in Table 90:

this space. Both DMA engines are excluded from this shared processor data region. (RGD7) accessible to both processors and the traditional eDMA master. memory protection unit in a typical system. Table 90. Overlapping region descriptor example

Memory Protection Unit (MPU) RM0029 312/1740 Doc ID 15177 Rev 8 (region #1) from instruction fetches by the core (or any PID=1 access). If the last instruction in the MPU region #0 space is a branch which the core takes while the core attempts to fetch instructions via instruction cache line fill from the MPU region #1 the MPU asserts a bus error (a PID=1 executable access into a region which only allows read/write accesses from PID=2). The core immediately takes the exception as a 'machine check'. In this case, modify the 'machine check' exception handler to expect this behavior.

RM0029 External Bus Interface (EBI) Doc ID 15177 Rev 8 313/1740

14 External Bus Interface (EBI)

14.1 Information Specific to This Device

This section presents device-specific parameterization and customization information not specifically referenced in the remainder of this chapter.

14.1.1 Device-Specific Features

3.3 V operation
24-bit address bus (2 most significant signals multiplexed with 2 chip selects)
The SPC564A74xx, SPC564A80xx MCU has only 16 data bus signals pinned out. The data bus can be multiplexed with the address bus to have a 32-bit data width mode.
Memory controller with support for various memory types: – Asynchronous/legacy flash and SRAM
Bus monitor – User selectable – Programmable timeout period (with 8 external bus clock resolution)
Configurable wait states (via chip selects)
Three chip-select (Cal_CS[0], Cal_CS[2:3]) signals (Multiplexed with 2 most significant address signals) for the calibration bus. 4 chip selects for EBI
Configurable bus speed modes – system frequency – 1/2 of system frequency – 1/4 of system frequency
Optional automatic CLKOUT gating to save power and reduce EMI
Selectable drive strengths; 10 pF, 20 pF, 30 pF, 50 pF
Note that the SPC564A74xx, SPC564A80xx EBI implementation doesn’t support external arbitration
Burst is supported in SPC564A74xx, SPC564A80xx MCU only by the External Bus interface (not by the calibration interface)

14.1.2 Unsupported Features

External arbitration

14.2 Introduction

The External Bus Interface (EBI) provides an on-board interface for mapping external memory to the SPC564A74xx, SPC564A80xx microcontroller. The EBI includes a memory controller that generates interface signals to support a variety of external memory types, including Single Data Rate (SDR) burst mode flash, SRAM, and asynchronous memories.

External Bus Interface (EBI) RM0029 314/1740 Doc ID 15177 Rev 8

14.2.1 Overview

On the SPC564A74xx, SPC564A80xx microcontroller, the EBI supports two sets of external signals: the EBI bus signals and the calibration bus signals. They are very similar in function but have different purposes. The calibration bus is a powerful development feature that enables system designers to interface dual-port SRAM with a system under development. This gives the system the capability of loading engine calibration data into SRAM instead of flash memory, making reprogramming the calibration data considerably faster and avoids the necessity of having to reconfigure pins each time calibration data is changed. Note: The calibration signals are only available on the calibration package. It is a very useful development feature but not used in production systems. Figure 85 shows an overview of the EBI, including the calibration signals. Each external memory component used is mapped to its own addressing region. Each region is separately programmable with region address and bus configuration information. Available bus configurations include 16-bit, 16-bit multiplexed and 32-bit multiplexed. In the multiplexed modes. address and data signals are multiplexed on the same pins.

Figure 85. External Bus Interface with Calibration Bus

External Bus Interface (EBI) RM0029 316/1740 Doc ID 15177 Rev 8

14.2.2 Features

Note: This list is a superset list of all possible features the EBI supports. Refer to Section 14.1, Information Specific to This Device, for details on specifics for a particular device due to package limitations.

32-Bit Address bus with transfer size indication (only 24-29 available on pins)
32-Bit Data bus (16-bit Data Bus Mode also supported)
Multiplexed Address on Data pins (single master)
Memory controller with support for various memory types: – synchronous burst SDR flash and SRAM – asynchronous/legacy flash and SRAM
Burst support (wrapped only)
Bus monitor
Port size configuration per chip select (16 or 32 bits)
Configurable wait states
Configurable internal or external transfer acknowledge (TA) per chip select
Support for Dynamic Calibration with up to 4 chip-selects
Four Write/Byte Enable (WE[0:3]/BE[0:3]) signals
Slower-speed clock modes
Stop and Module Disable Modes for power savings
Optional automatic CLKOUT gating to save power and reduce EMI
Misaligned access support (for chip-select accesses only)

14.2.3 Modes of operation

The mode of the EBI is determined by the MDIS, EXTM, and AD_MUX bits in the EBI_MCR. See Section , EBI Module Configuration Register (EBI_MCR) for details. Slower-speed modes, Debug Mode, Stop Mode, and Factory Test Mode are modes that the MCU may enter, in parallel to the EBI being configured in one of its block-specific modes. Single master mode In Single Master Mode, the EBI responds to internal requests matching one of its regions, but ignores all externally-initiated bus requests. The MCU is the only master allowed to initiate transactions on the external bus in this mode; therefore, it acts as a parked master and does not have to arbitrate for the bus before starting each cycle. Single Master Mode is entered when EXTM=0 and MDIS=0 in the EBI_MCR. Module disable mode The Module Disable Mode is used for MCU power management. The clock to the non- memory mapped logic in the EBI can be stopped while in Module Disable Mode. Internal master requests made to the external bus in Module Disable Mode are terminated with transfer error. Module Disable Mode is entered when MDIS=1 in the EBI_MCR. Stop mode When a request is made to enter Stop Mode (controlled in device logic outside EBI), the EBI block completes any pending bus transactions and acknowledges the stop request. After the acknowledgement, the system clock input may be shut off by the clock driver on the

RM0029 External Bus Interface (EBI) Doc ID 15177 Rev 8 317/1740 MCU. While the clocks are shut off, the EBI is not accessible. While in stop mode, accesses to the EBI from the internal master will terminate with transfer error. Slower-speed modes In slower-speed modes, the external CLKOUT frequency is divided (by 2, 3, etc.) compared with that of the internal system bus. The EBI behavior remains dictated by the mode of the EBI, except that it drives and samples signals at the CLKOUT frequency rather than the internal system frequency. This mode is selected by writing a clock control register in a block outside of the EBI. Refer to the device-specific documentation to see which slower-speed modes are available for a particular MCU (1/2, 1/3, etc.). 16-Bit data bus mode For MCUs that have only 16 data bus signals pinned out, or for systems where the use of a different multiplexed function (e.g. GPIO) is desired on 16 of the 32 data pins, the EBI supports a 16-bit Data Bus Mode. In this mode, only 16 data signals are used by the EBI. The user can select which 16 data signals are used (DATA[0:15] or DATA[16:31]) by writing the D16_31 bit in the EBI_MCR. For EBI-mastered accesses, the operation in 16-bit Data Bus Mode (DBM=1, PS=x) is similar to a chip-select access to a 16-bit port in 32-bit Data Bus Mode (DBM=0, PS=1), except for the case of a non-chip-select access of exactly 32-bit size. EBI-mastered non-chip-select accesses of exactly 32-bit size are supported via a two (16- bit) beat burst for both reads and writes. See Section , Non-chip-select burst in 16-bit data bus mode. Non-chip-select transfers of non-32-bit size are supported in standard non-burst fashion. 16-bit Data Bus Mode is entered when DBM=1 in the EBI_MCR. Some MCUs may have DBM=1 by default out of reset. See the device-specific documentation for the DBM and D16_31 reset values. Multiplexed address on data bus mode This mode covers several cases aimed at reducing pin count on MCU and external components. In this mode, the DATA pins will drive (for internal master cycles) the address value on the first clock of the cycle (while TS is asserted).The memory controller supports per-chip-select selection of multiplexing address/data through the BRx[AD_MUX] bit. Address on Data bus multiplexing also supports the 16-bit data bus mode (MCR[DBM]=1) and 16-bit memories (ORx[PS]=1). The user can select which 16 data signals are used (DATA[0:15] or DATA[16:31]) by writing the D16_31 bit in the EBI_MCR. For either setting of D16_31, the 16 LSBs of external address (ADDR[16:31]) are driven onto the selected 16 DATA pins. If additional address lines are required to interface to the memory, then non- muxed address pins are sometimes (see note below) required to complete the address space (e.g. ADDR[8:15] are commonly present as non-muxed address pins). Note: The EBI also drives the unused 16 DATA signals with the MSBs of the external address, zero-padded in front (e.g. when D16_31 bit is set for a device with 24 ADDR pins, the EBI drives (0b00000000,ADDR[8:15]) on DATA[0:15]. This allows the device to optionally use DATA[8:15] for the upper 8 external address lines instead of requiring separate non-muxed ADDR[8:15] pins. This is relevant primarily for devices that support both 32-bit and 16-bit A/D muxed operation, so therefore have DATA[0:31] pins present on the device, and in that case are not required to have separate ADDR pins. For more details (e.g. timing diagrams), see Section , Address data multiplexing.

Table 91 summarizes pin usage by EBI mode. Table 91. Typical pin usage across supported EBI modes

8 ADDR[12] 0b001 ADDR[12] 0b001 GPIO[8] (5) 0b000

11 ADDR[15] 0b001 ADDR[15] 0b001 GPIO[11]

62 RD_WR 0b001 RD_WR 00b01 RD_WR 0b001

63 BDIP 0b001 BDIP 0b001 BDIP 0b001

64 WE[0]/BE[0] 0b001 WE[0]/BE[0] 0b001 WE[0]/BE[0] 0b001

65 WE[1]/BE[1] 0b001 WE[1]/BE[1] 0b001 WE[1]/BE[1] 0b001

68 OE 0b001 OE 0b001 OE 0b001

69 TS 0b001 ALE 0b010 ALE 0b010

70 TA 0b001 TS 0b010 TS 0b010

16-bit non-multiplexed mode supported for EBI configured with EBI_MCR[D16_31]=0, and respective
16 bit multiplexed mode shown for EBI configured with EBI_MCR[D16_31]=0, and respective BRx/CAL_BRx[AD_MUX]=1.

with EBI_MCR[D16_31]=1, using DATA[16:31] signals for EBI and leaving DATA[0:15] balls available for GPIO use.

32-bit multiplexed mode shown for EBI configured with EBI_MCR[D16_31]=0, and respective BRx/CAL_BRx[AD_MUX]=1.
Pin functionality chosen dependent on required addressing range and chip select availability.
Pin function/s not required to support EBI in this usage mode.
Data/address dynamically multiplexed in ternally by EBI, not SIU pin muxing.

14.3 External signal description

14.3.1 Overview

14.3.2 Detailed signal descriptions

The ADDR[3:31] signals specify the physical address of the bus transaction. The 29 address lines correspond to bits 3-31 of the EBI’s 32-bit internal address bus. Table 92. Signal Properties

This column shows which signals require a weak pullup or pulldown. The EBI block does not contain
The CLKOUT signal is driven by the System Clock Block outside the EBI.
In Address/Data multiplexing modes, Data w ill also show the address during the address phase.

External Bus Interface (EBI) RM0029 320/1740 Doc ID 15177 Rev 8 CLKOUT — Clockout CLKOUT is a general-purpose clock output signal to connect to the clock input of SDR external memories and in some cases to the input clock of another MCU in multi-master configurations. CAL_CS [0:3] — Calibration chip selects 0-3 CAL_CSx is asserted by the master to indicate that this transaction is targeted for a particular memory bank on the Calibration external bus. The calibration chip selects are driven only by the EBI. External master accesses on the Calibration bus are not supported. In all other aspects, the calibration chip-selects behave exactly as the primary chip-selects. See Section , Memory Controller with Support for Various Memory Types for details on chip-select operation. DATA [0:31] — Data lines 0-31 The DATA[0:31] signals contain the data to be transferred for the current transaction. DATA[0:31] is driven by the EBI when it owns the external bus and it initiates a write transaction to an external device.DATA[0:31] is driven by an external device during a read transaction from the EBI.For 8-bit and 16-bit transactions, the byte lanes not selected for the transfer do not supply valid data. DATA[0:31] is driven by the EBI in the address phase with the ADDR value if the Address on Data multiplexing mode is enabled. See Section , Multiplexed address on data bus mode, for details. In 16-bit Data Bus Mode, (or for chip-select accesses to a 16-bit port), only DATA[0:15] or DATA[16:31] are used by the EBI, depending on the setting of the D16_31 bit in the EBI_MCR. See Section , 16-Bit data bus mode. OE — Output Enable OE is used to indicate when an external memory is permitted to drive back read data. External memories must have their data output buffers off when OE is negated. OE is only asserted for chip-select accesses. For read cycles, OE is asserted one clock after TS assertion and held until the termination of the transfer. For write cycles, OE is negated throughout the cycle. RD_WR — Read / Write RD_WR indicates whether the current transaction is a read access or a write access. RD_WR is driven in the same clock as the assertion of TS and valid address, and is kept valid until the cycle is terminated. TA — Transfer Acknowledge TA is asserted to indicate that the slave has received the data (and completed the access) for a write cycle, or returned data for a read cycle. If the transaction is a burst read, TA is asserted for each one of the transaction beats. For write transactions, TA is only asserted once at access completion, even if more than one write data beat is transferred. TA is driven by the EBI when the access is controlled by the chip selects (and SETA=0). Otherwise, TA is driven by the slave device to which the current transaction was addressed.

See Section , Termination signals protocol for more details. successive clock cycles until the end of the transaction. [0:3]/BE[0:3] are only asserted for chip-select accesses. regardless of which half of the DATA bus is selected via the D16_31 bit in the EBI_MCR.

14.3.3 Signal output buffer enable logic by mode

see the device-specific documentation for any exceptions to the logic below. Table 93. Signal Output Buffer Enable Logic by Mode (1) phase when Addr/Data muxing is enabled.

The values in this table only indicate when signals are strongly driven, not the logic value on the pin itself.

14.4 Memory map/Register definition

Table 94 shows the EBI registers.

14.4.1 Register Descriptions

This assumes that the clock to the EBI is shut off when MDIS=1. This is an optional device feature. If the clocks are left

supported in this scenario). Table 94. EBI Address Map

See Section 14.6.1, Booting from external memory for related application information. Figure 86. EBI Module Configuration Register (EBI_MCR) associated with EBI operation. Table 95. EBI Module Configuration Re gister (EBI_MCR) Field Descriptions in-between external bus accesses. mapped logic in the EBI, effectively putting the EBI in a software controlled power-saving state. performed when the EBI is in Module Disable Mode (MDIS=1).

A/D muxing with a 16-bit port, it is recommended to set D16_31 to 1. bus in the address phase of a cycle. 1: Address on Data Multiplexing Mode is used for non-CS accesses. 0: Only Data on data pins for non-CS accesses. The DBM bit controls whether the EBI is in 32-bit or 16-bit Data Bus Mode.

Figure 87. EBI Transfer Error Status Register (EBI_TESR) clock modes, e.g., a bus error can be generated on a timeout. Table 96. EBI Transfer Error Status Re gister (EBI_TESR) Field Descriptions This bit is set if the cycle was terminated by a bus monitor timeout.

whether it is enabled or disabled. Figure 88. EBI Bus Monitor Control Register (EBI_BMCR) Table 97. EBI Bus Monitor Control Regi ster (EBI_BMCR) Field Descriptions Section , Bus Monitor for more details on bus monitor operation. Timeout Period = (2 + (8 * BMT)) / external bus clock frequency. is ignored (treated as 0) for chip-select accesses with internal TA (SETA=0).

Figure 89. EBI Base Registers (EBI_BR0-EBI_BR3, EBI_CAL_BR0-3)

Some upper bits of the BA field may be tied to a fixed value, in which case the reset value is this fixed value and not zero.

Refer to Section 14.1, Information Specific to This Device , to see which bits this applies to, if any. being accessed by an internal bus master. PS — The PS bit determines the data bus width of transactions to this chip-select bank. is always treated as a ’1’ (16-bit port).

1: Address on Data Multiplexing Mode is enabled for this chip select. 0: Address on Data Multiplexing Mode is disabled for this chip select. 16 according to the Port Size (PS bit) so that the burst fetches the number of words chosen by BL. For internal AMBA data bus width of 32-bits, the BL bit is ignored (treated as 1). bit external memory (nor a 2-beat burst to 32-bit external memory) are supported. This bit controls the functionality of the WE[0:3]/BE[0:3] signals. Section , TBDIP effect on burst transfer for details.

Total amount of data fetched in a burst transfer.
Number of external data beats used in external burst transfer. The size

of each beat is determined by PS value.

An 8-word burst length is only supported for device’s using 64-bit AMBA
A word always refers to 32-bits of data, regardless of PS.

the BI bit to be ignored (treated as 1, burst inhibited). BI bit is ignored (treated as 1) for chip-select accesses with external TA (SETA=1). 1: Disable burst accesses for this bank. This is the default value out of reset (or when SETA=1). are valid. The appropriate CS signal does not assert unless the corresponding V-bit is set.

CAL_BR0-3 registers do not support burst operation.

Figure 90. EBI Option Registers (E BI_OR0-EBI_OR3, EBI_CAL_OR0-3)

Some upper bits of the AM field may be tied to a fixed value, in which case the reset value is this fixed value and not zero.

Refer to Section 14.1, Information Specific to This Device , to see which bits this applies to, if any. be read or written at any time. particular MCU. Tied-off bits can be read but not written.

length of the cycle. These bits are ignored when SETA=1. cycle) = (2+SCY) external clock cycles. See Section , Example wait state calculation for related application information. SCY[0:3] to determine the length of the first beat. These bits are ignored when SETA=1. The total memory access length for each beat is (1 + BSCY) external clock cycles. The total cycle length (including the TS cycle) = (2+SCY) + (#beats(2)-1) * (BSCY+1).

CAL_BR0-3 registers do not support burst operation.
#beats is the number of beats (4,8,16) determined by BL and PS bits in Base Register.

14.5 Functional Description

14.5.1 External Bus Interface Features

Data Bus Mode available via the DBM bit in EBI_MCR. See Section , 16-Bit data bus mode. per chip-select access. See Section , Multiplexed address on data bus mode. handles the memory access (e.g., bank 0 is selected over bank 1). Figure 91. Bank Base Address & Match Structure

Number of wait states for a single memory access, and for any beat in a burst access
Burst enable
Port size for the external accessed device See Section , EBI Base Registers (EBI_BR0-EBI_BR3, EBI_CAL_BR0-3) and Section , EBI Option Registers (EBI_OR0-EBI_OR3, EBI_CAL_OR0-3) for a full description of all chip- select attributes. When no match is found on any of the chip-select banks, the default transfer attributes shown in Table 100 are used. Burst Support (wrapped only) The EBI supports burst read accesses of external burstable memory. To enable bursts to a particular memory region, clear the BI (Burst Inhibit) bit in the appropriate Base Register. External burst lengths of 4 and 8 words are supported. Burst length is configured for each chip select by using the BL bit in the appropriate Base Register. See Section , Burst transfer for more details on burst operation. In 16-bit data bus mode (DBM=1 in EBI_MCR), a special 2-beat burst case is supported for reads and writes for 32-bit non-chip-select accesses only. This is to allow 32-bit coherent accesses to another MCU. See Section , Non-chip-select burst in 16-bit data bus mode. Bursting of accesses that are not controlled by the chip selects is not supported for any other case besides the special case of 32-bit accesses in 16-bit data bus mode. Burst writes are not supported for any other case besides the special case of 32-bit non- chip-select writes in 16-bit data bus mode. Internal requests to write >32 bits (such as a cache line) externally are broken up into separate 32-bit or 16-bit external transactions according to the port size. See Section , Small accesses (Small port size and short burst length) for more detail on these cases.

Table 100. Default Attributes for Non-Chip-Select Transfers

External Bus Interface (EBI) RM0029 334/1740 Doc ID 15177 Rev 8 Bus Monitor When enabled (via the BME bit in the EBI_BMCR), the bus monitor detects when no TA assertion is received within a maximum timeout period for external TA accesses. The timeout for the bus monitor is specified by the BMT field in the EBI_BMCR. Each time a timeout error occurs, the BMTF bit is set in the EBI_TESR. The timeout period is measured in external bus (CLKOUT) cycles. Thus the effective real-time period is multiplied (by 2, 3, etc.) when a slower-speed mode is used, even though the BMT field itself is unchanged. Port Size Configuration per Chip Select (16 or 32 bits) The EBI supports memories with data widths of 16 or 32 bits. The port size for a particular chip select is configured by writing the PS bit in the corresponding Base Register. Configurable Wait States From 0 to 15 wait states can be programmed for any cycle that the memory controller generates, via the SCY bits in the appropriate Option Register. From 0 to 3 wait states between burst beats can be programmed using the BSCY bits in the appropriate Option Register. Configurable internal or external TA per chip select Each chip select can be configured (via the SETA bit) to have TA driven internally (by the EBI), or externally (by an external device). See Section , EBI Base Registers (EBI_BR0- EBI_BR3, EBI_CAL_BR0-3) for more details on SETA bit usage. Support for Dynamic Calibration with up to 4 chip-selects The EBI contains 4 calibration chip select signals, controlling 4 independent memory banks on an optional 2nd external bus for calibration. See Section , Calibration bus operation for more details on using the calibration bus. Four Write/Byte Enable (WE/BE) Signals The functionality of the WE[0:3]/BE[0:3] signals depends on the value of the WEBS bit in the corresponding Base Register. Setting WEBS to 1 configures these pins as BE[0:3], while resetting it to 0 configures them as WE[0:3]. WE[0:3] are asserted only during write accesses, while BE[0:3] is asserted for both read and write accesses. The timing of the WE[0:3]/BE[0:3] signals remains the same in either case. The upper Write/Byte Enable (WE0/BE0) indicates that the upper eight bits of the data bus (DATA[0:7]) contain valid data during a write/read cycle. The upper middle Write/Byte Enable (WE1 /BE1) indicates that the upper middle eight bits of the data bus (DATA[8:15]) contain valid data during a write/read cycle. The lower middle Write/Byte Enable (WE2/BE2) indicates that the lower middle eight bits of the data bus (DATA[16:23]) contain valid data during a write/read cycle. The lower Write/Byte Enable (WE3 /BE3) indicates that the lower eight bits of the data bus (DATA[24:31]) contain valid data during a write/read cycle. Note: The exception to the preceding WE /BE description is that for 16-bit port transfers (DBM=1 or PS=1), only the WE[0:1]/BE[0:1] signals are used, regardless of whether DATA[0:15] or DATA[16:31] are selected (via the D16_31 bit in the EBI_MCR). This means for the case where DATA[16:31] are selected, that WE0 indicates that DATA[16:23] contains valid data, and WE1 indicates that DATA[24:31] contains valid data. The Write/Byte Enable lines affected in a transaction for a 32-bit port (PS = 0) and a 16-bit port (PS=1) are shown in Table 101. Only Big Endian byte ordering is supported by the EBI.

that the frequency of CLKOUT is reduced. See Section 14.2.3, Modes of operation for a description of the power saving modes. enabled or disabled by the ACGE bit in the EBI_MCR. getting its clock source from the other master and needs it to stay valid continuously. Table 101. Write/Byte Enable Signals Function

This table applies to aligned internal master transfers only. In the case of a misaligned internal

X’d in the table will necessarily assert. See Section , Misaligned access support .

Also applies when DBM=1 for 16-bit data bus mode.

00 X X

01 X X

10 X X

11 X X

This case consists of two 16-bit exter nal transactions, but for both transactions the

WE[0:1]/BE[0:1] signals are the only WE/BE signals affected.

14.5.2 External bus operations

provided for data transfer operations, and error conditions. that take place while reset is asserted. protocol is shown in Figure 92. Figure 92. Basic Transfer Protocol needed in Single Master Mode because the EBI is the permanent bus owner in this mode. , ADDR (or DATA if Address/Data multiplexing is used), CS[0:3], RD_WR, and BDIP. writes with internal TA, RD_WR is not held one cycle past TA.

RM0029 External Bus Interface (EBI) Doc ID 15177 Rev 8 337/1740 address transfer cycle. The master can stop driving the data bus as soon as it samples the TA line asserted on the rising edge of CLKOUT. To facilitate asynchronous write support, the EBI keeps driving valid write data on the data bus until 1 clock after the rising edge where RD_WR and WE are negated (for chip-select accesses only). See Figure 98 for an example of write timing. On a read cycle, the master accepts the data bus contents as valid on the rising edge of the CLKOUT in which the TA signal is sampled asserted. See Figure 94 for an example of read timing. The termination phase is where the cycle is terminated by the assertion of either TA (normal termination) or TEA (termination with error). Termination is discussed in detail in Section , Termination signals protocol. Note: In the timing diagrams in this document, asynchronous relationships between signals that switch in the same CLKOUT cycle are not guaranteed. For example, in Figure 98, WE and write DATA change during the same CLKOUT cycle. There is no guarantee that DATA will be stable before WE assertion. External devices should not be latching write DATA on WE assertion, but instead must use a signal edge that takes place in a later CLKOUT cycle, such as WE negation. Single beat transfer The flow and timing diagrams in this section assume that the EBI is configured in Single Master Mode. Therefore, arbitration is not needed and is not shown in these diagrams. Single beat read flow The handshakes for a single beat read cycle are illustrated in the following flow and timing diagrams.

Figure 93. Basic Flow Diagram of a Single Beat Read Cycle

Figure 96. Single Beat 32-bit Read Cycle, Non-CS Access, Zero Wait States version of the external TA (1 cycle delayed) to terminate the cycle.

Figure 97. Basic Flow Diagram of a Single Beat Write Cycle

Figure 100. Single Beat 32-bit Write Cycle, Non-CS Access, Zero Wait States cycle between the TA of a previous transfer and the TS of the next transfer. back writes or read-after-write to the same chip-select. See Figure 104 and Figure 105.

Back-to-back accesses where the first access ends with an externally-driven TA or TEA. In these cases, an extra cycle is required between the end of the first access and the TS assertion of the second access. See Section , Termination signals protocol for more details. The following diagrams show a few examples of back-to-back accesses on the external bus. DATA is valid CLKOUT ADDR[3:31] TS TA (Input) RD_WR BDIP CS[n] DATA is valid The EBI drives address and control signals an extra cycle because it uses a latched version of the external TA (1 cycle delayed) to terminate the cycle. DATA[0:31] WE[0:3]

Figure 103. Write After Read to the Same CS Bank

Figure 104. Back-to-Back 32-bit Writes to the Same CS Bank

Figure 105. Read After Write to the Same CS Bank

one or more single-beat external transfers, not by an external burst transfer. EBI requires that addresses be aligned to a doubleword boundary on all burst cycles. Table 102 shows the burst order of beats returned for an 8-word burst to a 32-bit port. select burst in 16-bit data bus mode . Table 102. Wrap Bursts Order j. This case (of 2 external burst transfers being requir ed) applies only to AMBA data bus width of 64 bits.

RM0029 External Bus Interface (EBI) Doc ID 15177 Rev 8 349/1740 Since burst writes are not supported by the EBI(k), the EBI negates BDIP during write cycles. k. Except for the special case of a 32-bit non-ch ip-select access in 16-bit data bus mode. See Section , Non-chip- select burst in 16-bit data bus mode .

Figure 106. Basic Flow Diagram of a Burst Read Cycle

Figure 110. Burst 32-bit Read Cycle, One Wait State between Beats, TBDIP=1 that cause the EBI to run multiple external transactions to fulfill the request. Table 103. Small Access Cases

Figure 114. Single Beat 64-bit Read Cycle, 16-bit Port Size, Basic Timing asserted for these erroneous cases.

Or DATA[16:31], based on D16_31 bit in EBI_MCR.

Byte access can have any address
16-bit access, address bit 31 must be 0
32-bit access, address bits 30–31 must be 0
For burst accesses of any size, address bits 29–31 must be 0 The EBI never generates a misaligned external access. In the erroneous case that an externally-initiated misaligned access does occur, the EBI errors the access (by asserting TEA externally) and does not initiate the access on the internal bus. The EBI requires that the portion of the data bus used for a transfer to/from a particular port size be fixed. A 32-bit port must reside on data bus bits 0–31,and a 16-bit port must reside on bits 0–15. In the following figures and tables the following convention is adopted:
The most significant byte of a 32-bit operand is OP0, and OP3 is the least significant byte.
The two bytes of a 16-bit operand are OP0 (most significant) and OP1, or OP2 (most significant) and OP3, depending on the address of the access.
The single byte of a byte-length operand is OP0, OP1, OP2, or OP3, depending on the address of the access. This can be seen in Figure 115.

Table 105. Transaction Sizes Supported by EBI

Some misaligned access cases may result in 3-byte writes. These cases

make sure only the appropriate 3 bytes get written.

Only supported for case of 64-bit internal AMBA data bus.

acknowledges the cycle and not later than the termination of the next address phase cycle. weak internal pullup) to drive TA. Table 106. Data Bus Requirements for Read Cycles

Also applies when DBM=1 for 16-bit data bus mode.
For address/data muxed transfers, DATA[16: 23] are used externally, not DATA[0:7].
For address/data muxed transfers, DATA[24:31] are used externally, not DATA[8:15].
This case consists of two 16-bi t external transactions, the first fe tching OP0 and OP1, the second fetching

Table 107. Data Bus Contents for Write Cycles

Also applies when DBM=1 for 16-bit data bus mode.
For address/data muxed transfers, DATA[16: 23] are used externally, not DATA[0:7].
For address/data muxed transfers, DATA[24:31] are used externally, not DATA[8:15].
This case consists of two 16-bit external transacti ons, the first writing OP0 and OP1, the second writing OP2

owns the bus, it lets go of TA. EBI must be configured for SCY>=1. TA cycle for proper error termination. always treated as an error (terminating the access) regardless of SCY. Table 108. Termination Signals Protocol

Latched version (1 cycle delayed) used for externally driven

External Bus Interface (EBI) RM0029 364/1740 Doc ID 15177 Rev 8 Since the calibration bus has no arbitration signals, the arbitration on the primary bus controls accesses on the calibration bus as well, and no external master accesses can be performed on the calibration bus. Accesses cannot be performed in parallel on both external busses. However, back-to-back accesses can switch from one bus to the other, as determined by the type of chip-select each address matches. The timing diagrams and protocol for the calibration bus is identical to the primary bus, except that some signals are missing on the calibration bus. See the device-specific documentation for the calibration bus signal list for a particular MCU. There is an inherent dead cycle between a calibration chip-select access and a non- calibration access (chip-select or non-chip-select), just like the one between accesses to two different non-calibration chip-selects (described in Section , Back-to-Back accesses). Figure 120 shows an example of a non-calibration chip-select read access followed by a calibration chip-select read access. Note that this figure is identical to Figure 102, except the CSy is replaced by CAL_CSy. Timing for other cases on calibration bus can similarly be derived from other figures in this document (by replacing CS with CAL_CS).

Figure 120. Back-to-Back 32-bit Reads to CS , CAL_CS Banks access cases (to the EBI) other than the ones below.

Table 109. Misalignment Cases Supported by a 64 bit AMBA EBI (internal bus)

1 Half @0x1,0x9 001 0110_0000 10 1

2 Half @0x3,0xB 011 0001_1000 11 1

3 Half @0x5,0xD 101 0000_0110 10 1

5 Word @0x1,0x9 001 0111_1000 11 1

6 Word @0x2,0xA 010 0011_1100 11 1

7 Word @0x3,0xB 011 0001_1110 11 1

Misaligned case number. Only transfers where HUNALIGN=1 are numbered as misaligned cases.
Address on internal master AHB bus, not necessarily address on external ADDR pins.
Internal byte strobe signals on AHB bus. Shown with Big-Endi an byte ordering in this table, even though internal master

AHB bus uses Little-Endian byte-order ing (EBI flips order internally).

Internal signal on AHB bus; 00=8-bits, 01=16 bits, 10=32 bits , 11=64-bits. HSIZE is driven according to the smallest

aligned container that contains all the requested bytes. This results in extra EBI external transfers in some cases.

Internal signal on AHB bus that indicates that this transfer is misaligned (when 1).
For this case, the EBI internally treats HSIZE as 00 (1-byte access).
For this case, the EBI internally treats HSIZE as 01 (2-byte access).
For this case, the EBI internally treats HSIZE as 10 (4-byte access).

access cases in Table 109, for each port size. Table 110. Misalignment Cases Supported by a 64 bit AMBA EBI (external bus)

Misaligned case number, from Table 109.
Port size; 0=32 bits, 1=16 bits.
External ADDR pins, not necessarily t he address on internal master AHB bus.

RM0029 External Bus Interface (EBI) Doc ID 15177 Rev 8 369/1740 Address data multiplexing Address/Data multiplexing enables the design of a system with reduced pin count. In such a system, multiplexed address/data functions (on DATA pins) are used, instead of having separate address and data pins. Compared to the normal EBI specification (e.g. 24 address pins+32 data pins), only 32 data pins are required. Compared to a 16-bit bus implementation, only 24 pins are required (e.g. ADDR[8:15] + ADDR[16:31]/DATA[16:31]). When performing a small access read, as described in Section , Small accesses (Small port size and short burst length), with A/D multiplexing enabled for this access, the EBI inserts an idle clock cycle with OE negated and CS asserted, to allow for the memory to three-state the bus prior to the EBI driving the address on the next clock. This clock gap already exists (for other reasons) for non-small-access transfers, so no additional clock gap is inserted for those cases. See Figure 121 for an example of a small access read with A/D multiplexing enabled. In general, timing diagrams in A/D multiplexing mode are very similar to other diagrams in this document (including support for Burst accesses), except for the behavior of the ADDR and DATA busses, which can be seen in Figure 121. 4. External WE_BE pins. Note that these pins have negative polarity, opposite of t he internal byte strobes in Table 109. 5. Treated as 1-byte access. 6. Treated as 2-byte access. 7. Treated as 4-byte access.

Figure 121. Small access (32-bit read to 16-bit port) on Address/Data multiplexed bus

14.6 Initialization/Application information

14.6.1 Booting from external memory

system, as DATA[16:31] (or DATA[0:15]) would be used for address and data on an external muxed device. ** Or DATA[0:15], based on D16_31 bit in EBI_MCR.

external boot is supported for a particular MCU.

Copy the code that is doing the register writes (plus a return branch) to internal SRAM
Branch to internal SRAM to run this code, ending with a branch back to external flash

14.6.2 Running with SDR (Single Data Rate) burst memories

connected to a 32-bit SDR burst memory. Figure 122. MCU Connected to SDR Burst Memory

14.6.3 Running with asynchronous memories

access time of the asynchronous memory, just as done for a synchronous memory.

May or may not be connected, depending on the memory used.

Figure 124. Read Operation to Asynchronous Memory, Three Initial Wait States

3 Wait States

Figure 125. Write Operation to Asynchronous Memory, Three Initial Wait States

14.6.4 Connecting an mcu to multiple memories

The MCU can be connected to more than one memory at a time. Figure 126 shows an example of how two memories could be connected to one MCU.

Figure 126. MCU Connected to Multiple Memories

14.6.5 EBI operation with reduced Pinout MCUs

May or may not be connected, depending on the memory used.

External Bus Interface (EBI) RM0029 376/1740 Doc ID 15177 Rev 8 and arbitration pins (BB, BG, BR). This section describes how to configure dual-MCU systems for each of those scenarios, as well as describing limitations to EBI operation when other pins are missing (TA , TEA, BDIP). More than one section may apply if the applicable pins are not present on one or both MCUs. Connecting 16-bit MCU to 32-bit MCU (Master/Master or Master/Slave) This scenario is straightforward. Simply connect DATA[0:15] between both MCUs, and configure both for 16-bit Data Bus Mode operation (DBM=1 in EBI_MCR). Note that 32-bit external memories are not supported in this scenario. Transfer size with no TSIZ pins (Master/Master or Master/Slave) Since there are no TSIZ pins to communicate transfer size from master MCU to slave MCU, the internal SIZE field of the EBI_MCR must be used on the slave MCU (by setting SIZEN=1 in slave’s EBI_MCR). Anytime the master MCU needs to read or write the slave MCU with a different transfer size than the current value of the slave’s SIZE field, the master MCU must first write the slave’s SIZE field with the correct size for the subsequent transaction. No Transfer Acknowledge (TA) Pin If an MCU has no TA pin available, this restricts the MCU to chip-select accesses only (no MCU->MCU transfers are possible). Non-chip-select accesses have no way for the EBI to know which cycle to latch the data. The EBI has no built-in protection to prevent non-chip- select accesses in this scenario; it is up to the user to make certain they set up chip-selects and external memories correctly to ensure all external accesses fall in a valid chip-select region. No Transfer Error (TEA) Pin If an MCU has no TEA pin available, this eliminates the feature of terminating an access with TEA. This means if an access times out in the EBI bus monitor, the EBI (master) will still terminate the access early, but there will be no external visibility of this termination, so the slave device might end up driving data much later, when a subsequent access is already underway. Therefore, the EBI bus monitor should be disabled when no TEA pin exists. No Burst Data in Progress (BDIP) Pin If an MCU has no BDIP pin available, this eliminates burst support only if the burstable memory being used requires BDIP to burst. Many external memories use a self-timed configurable burst mechanism that does not require a dynamic burst indicator. Check the applicable external memory specification to see if BDIP is required in your system.

RM0029 Interrupt Controller (INTC) Doc ID 15177 Rev 8 377/1740

15 Interrupt Controller (INTC)

15.1 Information specific to this device

This section presents device-specific parameterization and customization information not specifically referenced in the remainder of this chapter.

15.1.1 Device-specific features

279 peripheral interrupts
199 reserved interrupts
8 software interrupts

15.2 Introduction

This chapter describes the interrupt controller (INTC), which schedules interrupt requests (IRQs) from software and internal peripherals to the e200z4 core. The INTC provides interrupt prioritization and preemption, interrupt masking, interrupt priority elevation, and protocol support. Interrupts implemented by the MCU are defined in the e200z4 Power Architecture ® Core Reference Manual.

15.2.1 Block diagram

Figure 127 shows the details of the interrupt controller.

Figure 127. INTC Block Diagram

15.2.2 Overview

controller. The CPU core has 19 exception sources, each of which can interrupt the core. optimized for a large number of interrupt requests. module; Figure 128 shows a general diagram of INTC software vector mode.

1 Although N (largest addressable IRQ vector number) = 485, this does not indicate the total number of

peripheral IRQs, 8 software-configurable IRQs, and 199 reserved. Table 111. Interrupt sources available

Figure 128. INTC software vector mode

Software vector mode
Hardware vector mode In software vector mode, as shown in Figure 128, the e200z4 branches to a common interrupt exception handler whose location is determined by an address derived from special purpose registers IVPR and IVOR4. The interrupt exception handler reads the INTC_IACKR to determine the vector of the interrupt request source. Typical program flow for software vector mode is shown in Figure 129. eDMA 66 FMPLL 2 External IRQ input pins (SIU) 6 eMIOS 24 eTPU engine A 33 eQADC 31 DSPI 15 eSCI 3 FlexCAN 63 FlexRay 8 STM 5 Decimation Filter 3 System (PIT, RTI, PMC, etc) 6

Table 111. Interrupt sources available (continued)

RM0029 Interrupt Controller (INTC) Doc ID 15177 Rev 8 381/1740 When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the Priority Ceiling Protocol (PCP) for coherent accesses. By providing a modifiable priority mask, the priority level can be raised temporarily so that no task can preempt another task that shares the same resource. Multiple processors can assert interrupt requests to each other through software configurable interrupt requests, i.e., by using application software to assert an interrupt request. These same software configurable interrupt requests also can be used to break the work involved in servicing an interrupt request into a high priority portion and a low priority portion. The high priority portion is initiated by a peripheral interrupt request, but the ISR can assert a software configurable interrupt request to finish the servicing in a low priority ISR.

15.2.3 Features

Features include the following:

Total number of interrupt vectors is 486, of which: – 279 are peripheral interrupt vectors – 8 are software configurable sources – 199 are reserved sources
9-bit unique vector for each interrupt request source in hardware vector mode.
Each interrupt source can be programmed to one of 16 priorities.
Preemption. – Preemptive prioritized interrupt requests to processor. – ISR at a higher priority preempts ISRs or tasks at lower priorities. – Automatic pushing or popping of preempted priority to or from a LIFO. – Ability to modify the ISR or task priority. Modifying the priority can be used to implement the PCP for accessing shared resources.
Low latency–three clocks from receipt of interrupt request from peripheral to interrupt request to processor.

15.2.4 Modes of operation

The interrupt controller has two handshaking modes with the processor: software vector mode and hardware vector mode. The state of the hardware vector enable bit, INTC_MCR[HVEN], determines which mode is used. In debug mode, the interrupt controller operation is identical to its normal operation of software vector mode or hardware vector mode. Software vector mode In the software vector mode, there is a common interrupt exception handler address that is calculated by hardware as shown in Figure 131. The upper half of the interrupt vector prefix register (IVPR) is added to the offset contained in the external input interrupt vector offset register (IVOR4). Note: Since bits IVOR4[28:31] are not part of the offset value, the vector offset must be located on a quad-word (16-byte) aligned location in memory. In the software vector mode, the interrupt exception handler software must read the INTC interrupt acknowledge register (INTC_IACKR) to obtain the vector number and base address of the handler associated with the corresponding peripheral or software interrupt

that peripheral or software interrupt source. Figure 131. Software Vector Mode: Interrupt Exception Handler Address Calculation generating an interrupt request to the processor.

INTC_IACKR to get the interrupt vector number. Figure 132. Hardware Vector Mode: Interrupt Exception Handler Address Calculation onto the LIFO and updates PRI in the INTC_CPR with the new priority.

15.3 External signal description

Refer to the Signals chapter for a list and number of the external interrupt pins.
Refer to the SIU chapter for more information on how to configure these pins.

15.4 Memory map and register definition

Table 112 is the INTC memory map. Table 112. INTC Memory Map

15.4.1 Register descriptions

include types and sizes of 8 bits, aligned 16 bits, and aligned 32 bits. 16-bit or 32-bit access, provided that the access does not cross a 32-bit boundary. does not affect the operation of the write. The INTC_MCR is used to configure options of the INTC.

When the HVEN bit in the INTC_MCR is asserted, a read of the INTC_IACKR has no side effects.
The PRI fields are “Reserved” fo r peripheral interrupt requests whose vectors are labeled as Reserved in Table 117.

Table 112. INTC Memory Map (continued)

Figure 133. INTC Module Configuration Register (INTC_MCR) PCP. Refer to Section 15.6.5, Priority ceiling protocol. Table 113. INTC_MCR Field Descriptions 0–25 Reserved, must be cleared. both hardware vector mode and software vector mode. 27–30 Reserved, must be cleared. Hardware vector enable. Controls whether the INTC is in hardware vector mode or software vector mode.

0 Software vector mode

1 Hardware vector mode

before lowering the PRI field. Refer to Section , Ensuring coherency. Figure 134. INTC Current Priority Register (INTC_CPR) respective interrupt vectors. Reading the INTC_IACKR does not have side effects in hardware vector mode. Table 114. INTC_CPR Field Descriptions 0–27 Reserved, must be cleared. Priority. PRI is the priority of the currently executing ISR according to the field values defined below.

1111 Priority 15 (highest)

1110 Priority 14

0001 Priority 1

0000 Priority 0 (lowest)

to this register neither update the INTC_EOIR contents nor affect whether the LIFO pops. For possible future compatibility, write four bytes of all 0’s to the INTC_EOIR. Reading the INTC_EOIR has no effect on the LIFO. Figure 137. INTC End-of-Interrupt Register (INTC_EOIR) SETn unchanged at 0 but sets CLRn. Writing a 0 to SETn has no effect. CLRn is the flag bit. Table 115. INTC_IACKR Field Descriptions only uses the left-most 20 bits when the VTES bit in INTC_MCR is asserted. whether the INTC is in software or hardware vector mode. 29–31 Reserved, must be cleared.

access, provided that the access does not cross a 32-bit boundary. Figure 138. INTC Software Set/Clear Interrupt Register (INTC_SSCIR n) that it does not cross a 32-bit boundary. n field in INTC_PSRn when the IRQ is asserted. Table 116. INTC_SSCIR n Field Descriptions 0–5 Reserved, must be cleared. simultaneously to its corresponding SETn bit. Writing a 0 to CLRn has no effect. 0 Interrupt request not pending within INTC. 1 Interrupt request pending within INTC.

Figure 139. INTC Priority Select Register 0–3 (INTC_PSR0_3) Figure 140. INTC Priority Select Register 482–485 (INTC_PSR482_485)

15.5 Functional description

15.5.1 Interrupt request sources

Table 117. INTC_PSR n Field Descriptions 0–3 Reserved, must be cleared. Priority select. Selects the priority for corresponding interrupt request.

INTC_PSRn, where the priority select register is assigned according to the vector number. Table 118. Interrupt Request Sources

Table 118. Interrupt Request Sources (continued)

196 Reserved Reserved

472 Reserved Reserved

current priority register (INTC_CPR). and updates the PRIn value in the INTC_CPR with the PRIn value in INTC_PSRn. INTC as an interrupt event setting the flag bit.

483 Reserved Reserved

The maximum vector number (485) is used to identify t he location of the last available interrupt vector in
Interrupt requests from the same module location are ORed together.

RM0029 Interrupt Controller (INTC) Doc ID 15177 Rev 8 403/1740 Peripheral interrupt requests An interrupt event in a peripheral’s hardware sets a flag bit, which resides in that peripheral. The interrupt request from the peripheral is driven by that flag bit. The time from when the peripheral starts to drive its peripheral interrupt request to the INTC to the time that the INTC starts to drive the interrupt request to the processor is three clocks. Software configurable interrupt requests The software set/clear interrupt registers (INTC_SSCIRx_x) support the setting or clearing of software-configurable interrupt requests. These registers contain eight independent sets of bits to set and clear a corresponding flag bit by software. With the exception of being set by software, this flag bit behaves the same as a flag bit set within a peripheral. This flag bit generates an interrupt request within the INTC just like a peripheral interrupt request. An interrupt request is triggered by software writing a 1 to the SETn bit in INTC software set/clear interrupt registers (INTC_SSCIR0–INTC_SSCIR7). This write sets a CLRn flag bit that generates an interrupt request. The interrupt request is cleared by writing a 1 to the CLRn bit. Specific behavior includes the following:

Writing a 1 to SETn leaves SETn unchanged at 0 but sets the flag bit (CLRn bit).
Writing a 0 to SETn has no effect.
Writing a 1 to CLRn clears the flag (CLRn) bit.
Writing a 0 to CLRn has no effect.
If a 1 is written to a pair of SETn and CLRn bits at the same time, the flag (CLRn) is set, regardless of whether CLRn was asserted before the write. The time from the write to the SETn bit to the time that the INTC starts to drive the interrupt request to the processor is four clocks. Unique vector for each interrupt request source Each peripheral and software configurable interrupt request is assigned a hardwired unique 9-bit vector. Software configurable interrupts 0–7 are assigned vectors 0–7, respectively. The peripheral interrupt requests are assigned vectors 8 to as high as needed to cover all of the peripheral interrupt requests.

15.5.2 Priority management

The asserted interrupt requests are compared to each other based on their PRIn values in INTC priority select registers (INTC_PSR0–INTC_PSR485). The result of the comparison also is compared to PRI in INTC current priority register (INTC_CPR). The results of those comparisons are used to manage the priority of the ISR being executed by the processor. The LIFO also assists in managing the priority. Current priority and preemption The priority arbitrator, selector, encoder, and comparator submodules shown in Figure 127 are used to compare the priority of the asserted interrupt requests to the current priority. If the priority of any asserted peripheral or software configurable interrupt request is higher than the current priority, then the interrupt request to the processor is asserted. Also, a unique vector for the preempting peripheral or software configurable interrupt request is generated for INTC interrupt acknowledge register (INTC_IACKR), and if in hardware vector mode, for the interrupt vector provided to the processor.

Interrupt Controller (INTC) RM0029 404/1740 Doc ID 15177 Rev 8 Priority arbitrator submodule The priority arbitrator submodule compares all the priorities of all of the asserted interrupt requests, both peripheral and software configurable. The output of the priority arbitrator submodule is the highest of those priorities. Also, any interrupt requests which have this highest priority are output as asserted interrupt requests to the request selector submodule. Request selector submodule If only one interrupt request from the priority arbitrator submodule is asserted, then it is passed as asserted to the vector encoder submodule. If multiple interrupt requests from the priority arbitrator submodule are asserted, then only the one with the lowest vector is passed as asserted to the vector encoder submodule. The lower vector is chosen regardless of the time order of the assertions of the peripheral or software configurable interrupt requests. Vector encoder submodule The vector encoder submodule generates the unique 9-bit vector for the asserted interrupt request from the request selector submodule. Priority comparator submodule The priority comparator submodule compares the highest priority output from the priority arbitrator submodule with PRI in INTC_CPR. If the priority comparator submodule detects that this highest priority is higher than the current priority, then it asserts the interrupt request to the processor. This interrupt request to the processor asserts whether this highest priority is raised above the value of PRI in INTC_CPR or the PRI value in INTC_CPR is lowered below this highest priority. This highest priority then becomes the new priority which is written to PRI in INTC_CPR when the interrupt request to the processor is acknowledged. Interrupt requests whose PRIn in INTC_PSRn are zero does not cause a preemption because their PRIn is not higher than PRI in INTC_CPR. LIFO The LIFO stores the preempted PRI values from the INTC_CPR. Therefore, because these priorities are stacked within the INTC, if interrupts need to be enabled during the ISR, at the beginning of the interrupt exception handler the PRI value in the INTC_CPR does not need to be loaded from the INTC_CPR and stored onto the context stack. Likewise at the end of the interrupt exception handler, the priority does not need to be loaded from the context stack and stored into the INTC_CPR. The PRI value in the INTC_CPR is pushed onto the LIFO when the INTC_IACKR is read in software vector mode or the interrupt acknowledge signal from the processor is asserted in hardware vector mode. The priority is popped into PRI in the INTC_CPR whenever the INTC_EOIR is written. Although the INTC supports 16 priorities, an ISR executing with PRI in the INTC_CPR equal to 15 is not preempted. Therefore, the LIFO supports the stacking of 15 priorities. However, the LIFO is only 14 entries deep. An entry for a priority of 0 is not needed because of how pushing onto a full LIFO and popping an empty LIFO are treated. If the LIFO is pushed 15 or more times than it is popped, the priorities first pushed are overwritten. A priority of 0 is an overwritten priority. However, the LIFO pop zeros if it is popped more times than it is pushed. Therefore, although a priority of 0 was overwritten, it is regenerated with the popping of an empty LIFO.

RM0029 Interrupt Controller (INTC) Doc ID 15177 Rev 8 405/1740 The LIFO is not memory mapped.

15.5.3 Details on handshaking with processor

Software vector mode handshaking Acknowledging interrupt request to processor A timing diagram of the interrupt request and acknowledge handshaking in software vector mode, along with the handshaking near the end of the interrupt exception handler, is shown in Figure 141. The INTC examines the peripheral and software configurable interrupt requests. When it finds an asserted peripheral or software configurable interrupt request with a higher priority than PRI in INTC current priority register (INTC_CPR), it asserts the interrupt request to the processor. The INTVEC field in INTC interrupt acknowledge register (INTC_IACKR) is updated with the preempting interrupt request’s vector when the interrupt request to the processor is asserted. The INTVEC field retains that value until the next time the interrupt request to the processor is asserted. The rest of the handshaking is described in Section , Software vector mode. End-of-interrupt exception handler Before the interrupt exception handling completes, INTC end-of-interrupt register (INTC_EOIR) must be written. When it is written, the LIFO is popped so that the preempted priority is restored into PRI of the INTC_CPR. Before it is written, the peripheral or software configurable flag bit must be cleared so that the peripheral or software configurable interrupt request is negated. Note: To ensure proper operation across all Power Architecture MCUs, execute an MBAR or MSYNC instruction between the access to clear the flag bit and the write to the INTC_EOIR. When returning from the preemption, the INTC does not search for the peripheral or software configurable interrupt request whose ISR was preempted. Depending on how much the ISR progressed, that interrupt request can no longer be asserted. When PRI in INTC_CPR is lowered to the priority of the preempted ISR, the interrupt request for the preempted ISR or any other asserted peripheral or software configurable interrupt request at or below that priority does not cause a preemption. Instead, after the restoration of the preempted context, the processor returns to the instruction address that it was to next execute before it was preempted. This next instruction is part of the preempted ISR or the interrupt exception handler’s prolog or epilog.

Figure 141. Software Vector Mode Handshaking Timing Diagram

Figure 142. Hardware Vector Mode Handshaking Timing Diagram

15.6 Initialization and application information

15.6.1 Initialization flow

15.6.2 Interrupt exception handler

These example interrupt exception handlers use Power Architecture assembly code.

Interrupt Controller (INTC) RM0029 408/1740 Doc ID 15177 Rev 8 lis r3,INTC_IACKR@ha# form adjusted upper half of INTC_IACKR address lwz r3,INTC_IACKR@l(r3)# load INTC_IACKR, which clears request to processor lwz r3,0x0(r3) # load address of ISR from vector table wrteei1 # enable processor recognition of interrupts code to save rest of context required by e500 EABI mtlr r3 # move the INTC_IACKR address into the link register blrl # branch to ISR; link register updated with epilog # address epilog: code to restore most of context required by e500 EABI # Popping the LIFO after the restoration of most of the context and the disabling of processor # recognition of interrupts eases the calculation of the maximum stack depth at the cost of # postponing the servicing of the next interrupt request. mbar # ensure store to clear flag bit has completed lis r3,INTC_EOIR@ha # form adjusted upper half of INTC_EOIR address li r4,0x0 # form 0 to write to INTC_EOIR wrteei0 # disable processor recognition of interrupts stw r4,INTC_EOIR@l(r3) # store to INTC_EOIR, informing INTC to lower priority code to restore SRR0 and SRR1, restore working registers, and delete stack frame rfi vector_table_base_address: address of ISR for interrupt with vector 0 address of ISR for interrupt with vector 1 address of ISR for interrupt with vector 510 address of ISR for interrupt with vector 511 ISRx: code to service the interrupt event code to clear flag bit which drives interrupt request to INTC blr # return to epilog Hardware vector mode This interrupt exception handler is useful with processor and system bus implementations that support a hardware vector. In this example, each interrupt_exception_handlerx has space for only four instructions, and therefore a branch to interrupt_ exception_handler_continuedx is needed. interrupt_exception_handlerx: b interrupt_exception_handler_continued x# 4 instructions available, branch to continue

RM0029 Interrupt Controller (INTC) Doc ID 15177 Rev 8 409/1740 interrupt_exception_handler_continuedx: code to create stack frame, save working register, and save SRR0 and SRR1 wrteei1 # enable processor recognition of interrupts code to save rest of context required by e500 EABI bl ISR x # branch to ISR for interrupt with vector x epilog: code to restore most of context required by e500 EABI # Popping the LIFO after the restoration of most of the context and the disabling of processor # recognition of interrupts eases the calculation of the maximum stack depth at the cost of # postponing the servicing of the next interrupt request. mbar # ensure store to clear flag bit has completed lis r3,INTC_EOIR@ha # form adjusted upper half of INTC_EOIR address li r4,0x0 # form 0 to write to INTC_EOIR wrteei0 # disable processor recognition of interrupts stw r4,INTC_EOIR@l(r3)# store to INTC_EOIR, informing INTC to lower priority code to restore SRR0 and SRR1, restore working registers, and delete stack frame rfi ISRx: code to service the interrupt event code to clear flag bit which drives interrupt request to INTC blr # branch to epilog

15.6.3 ISR, RTOS, and task hierarchy

The RTOS and all of the tasks under its control typically execute with PRI in INTC current priority register (INTC_CPR) having a value of 0. The RTOS execute the tasks according to whatever priority scheme that it has, but that priority scheme is independent and has a lower priority of execution than the priority scheme of the INTC. In other words, the ISRs execute above INTC_CPR priority 0 and outside the control of the RTOS, the RTOS executes at INTC_CPR priority 0, and while the tasks execute at different priorities under the control of the RTOS, they also execute at INTC_CPR priority 0. If a task shares a resource with an ISR and the PCP is being used to manage that shared resource, then the task’s priority can be elevated in the INTC_CPR while the shared resource is being accessed. An ISR whose PRIn in INTC priority select registers (INTC_PSR0–INTC_PSR485) has a value of 0 does not cause an interrupt request to the processor, even if its peripheral or software configurable interrupt request is asserted. For a peripheral interrupt request, not

interrupt exception handler, perhaps after executing another ISR.

15.6.4 Order of execution

configurable interrupt requests asserted. Table 119. Order of ISR Execution Example

2 Peripheral interrupt request 100 at

3 Peripheral interrupt request 400 at

4 Peripheral interrupt request 300 at

5 Peripheral interrupt request 200 at

interrupt request 300 asserted first.

15.6.5 Priority ceiling protocol

allows coherent accesses of the ISRs to that shared resource. For example, ISR1 has a priority of 1, ISR2 has a priority of 2, and ISR3 has a priority of 3. completes and execution returns to the lower priority ISR. the ISRs with a priority higher than 3 can preempt ISR1. value to a shared coherent data block. data block is now corrupted.

ISR108 executes for peripheral interrupt request 100 because the first eight ISRs ar e for software configurable interrupt

Table 119. Order of ISR Execution Example (continued)

Interrupt Controller (INTC) RM0029 412/1740 Doc ID 15177 Rev 8 GetResource: raise PRI mbar isync ReleaseResource: mbar lower PRI The selection of the priorities for the ISRs can be made using Rate Monotonic Scheduling (RMS) or a superset of it, Deadline Monotonic Scheduling (DMS). In RMS, the ISRs that have higher request rates have higher priorities. In DMS, if the deadline is before the next time the ISR is requested, then the ISR is assigned a priority according to the time from the request for the ISR to the deadline, not from the time of the request for the ISR to the next request for it. For example, ISR1 executes every 100 μs, ISR2 executes every 200 μs, and ISR3 executes every 300 μs. ISR1 has a higher priority than ISR2, which has a higher priority than ISR3. However, if ISR3 has a deadline of 150 μs, then it has a higher priority than ISR2. The INTC has 16 priorities, which can be considerably less than the number of ISRs. In this case, group the ISRs with other ISRs that have similar deadlines. For example, when a priority is allocated for every time, the request rate doubles ISRs with request rates around 1 ms share a priority; ISRs with request rates around 500 μs share a priority; ISRs with request rates around 250 μs share a priority, etc. With this approach, a range of ISR request rates of 2 16 can be covered, regardless of the number of ISRs. Reducing the number of priorities reduces the processor's ability to meet its deadlines. However, it also allows easier management of ISRs with similar deadlines that share a resource. They do not need to use the PCP to access the shared resource.

15.6.7 Software configurable interrupt requests

The software configurable interrupt requests can be used in two ways. They can be used to schedule a lower priority portion of an ISR and for processors to interrupt other processors in a multiple processor system. Scheduling a lower priority portion of an ISR A portion of an ISR needs to be executed at the PRIn value in INTC priority select registers (INTC_PSR0–INTC_PSR485), which becomes the PRI value in INTC current priority register (INTC_CPR) with the interrupt acknowledgement. The ISR, however, can have a portion of it that does not need to be executed at this higher priority. Therefore, executing this later portion that does not need to be executed at this higher priority can prevent the execution of ISRs, which do not have a higher priority than the earlier portion of the ISR but do have a higher priority than what the later portion of the ISR needs. This preemptive scheduling inefficiency reduces the processor's ability to meet its deadlines. One option is for the ISR to complete the earlier higher priority portion, but then schedule through the RTOS a task to execute the later lower priority portion. However, some RTOSs can require a large amount of time for an ISR to schedule a task. Therefore, a second option for the ISR is, after completing the higher priority portion, to set a SETn bit in INTC software

RM0029 Interrupt Controller (INTC) Doc ID 15177 Rev 8 413/1740 set/clear interrupt registers (INTC_SSCIR0–INTC_SSCIR7). Writing a 1 to SET n causes a software configurable interrupt request. This software configurable interrupt request, which usually has a lower PRIn value in the INTC_PSRn, does not cause preemptive scheduling inefficiencies. After generating a software configurable interrupt request, the higher priority ISR completes. The lower priority ISR is scheduled according to its priority. Execution of the higher priority ISR is not resumed after the completion of the lower priority ISR. Scheduling an ISR on another processor Since the SETn bits in the INTC_SSCIRn are memory mapped, processors in multiple processor systems can schedule ISRs on the other processors. One application is that one processor simply wants to command another processor to perform a piece of work, and the initiating processor does not need to use the results of that work. If the initiating processor is concerned that processor executing the software configurable ISR has not completed the work before asking it to again execute that ISR, it can check if the corresponding CLRn bit in INTC_SSCIRn is asserted before again writing a 1 to the SETn bit. Another application is the sharing of a block of data. For example, a first processor has completed accessing a block of data and wants a second processor to then access it. Furthermore, after the second processor has completed accessing the block of data, the first processor again wants to access it. The accesses to the block of data must be done coherently. The procedure is that the first processor writes a 1 to a SETn bit on the second processor. The second processor, after accessing the block of data, clears the corresponding CLRn bit and then writes 1 to a SETn bit on the first processor, informing it that it now can access the block of data.

15.6.8 Lowering priority within an ISR

In implementations without the software-configurable interrupt requests in the INTC software set/clear interrupt registers (INTC_SSCIR0–INTC_SSCIR7), a way — besides scheduling a task through an RTOS — to prevent preemptive scheduling inefficiencies with an ISR whose work spans multiple priorities (as described in Section , Scheduling a lower priority portion of an ISR) is to lower the current priority. However, the INTC has a LIFO whose depth is determined by the number of priorities. Note: Lowering the PRI value in INTC current priority register (INTC_CPR) within an ISR to below the ISR’s corresponding PRI value in INTC priority select registers (INTC_PSR0– INTC_PSR485) allows more preemptions than the depth of the LIFO can support. Therefore, through its use of the LIFO the INTC does not support lowering the current priority within an ISR as a way to avoid preemptive scheduling inefficiencies.

15.6.9 Negating an interrupt request outside of its ISR

Negating an interrupt request as a side effect of an ISR Some peripherals have flag bits which can be cleared as a side effect of servicing a peripheral interrupt request. For example, reading a specific register can clear the flag bits, and consequently their corresponding interrupt requests, too. This clearing as a side effect of servicing a peripheral interrupt request can cause the negation of other peripheral interrupt requests besides the peripheral interrupt request whose ISR presently is executing. This negating of a peripheral interrupt request outside of its ISR can be a desired effect.

Interrupt Controller (INTC) RM0029 414/1740 Doc ID 15177 Rev 8 Negating multiple interrupt requests in one ISR An ISR can clear other flag bits besides its own flag bit. One reason that an ISR clears multiple flag bits is because it serviced those other flag bits, and therefore the ISRs for these other flag bits do not need to be executed. Proper setting of interrupt request priority Whether an interrupt request negates outside of its own ISR due to the side effect of an ISR execution or the intentional clearing a flag bit, the priorities of the peripheral or software configurable interrupt requests for these other flag bits must be selected properly. Their PRIn values in INTC priority select registers (INTC_PSR0–INTC_PSR485) must be selected to be at or lower than the priority of the ISR that cleared their flag bits. Otherwise, those flag bits still can cause the interrupt request to the processor to assert. Furthermore, the clearing of these other flag bits also has the same timing relationship to the writing to INTC end-of-interrupt register (INTC_EOIR) as the clearing of the flag bit that caused the present ISR to be executed. Refer to Section , End-of-interrupt exception handler, for more information. A flag bit whose enable bit or mask bit is negating its peripheral interrupt request can be cleared at any time, regardless of the peripheral interrupt request’s PRIn value in INTC_PSRn.

15.6.10 Examining LIFO contents

Normally you do not need to know the contents of the LIFO, or even how deep the LIFO is nested. Although the LIFO contents are not memory mapped, you can read the contents by popping the LIFO and reading the PRI field in the INTC current priority register (INTC_CPR). Disabling processor recognition of interrupts while examining the LIFO contents provides a coherent view of the preempted priorities. The code sequence is: pop_lifo: store to INTC_EOIR load INTC_CPR, examine PRI, and store onto stack if PRI is not zero or value when interrupts were enabled, branch to pop_lifo When you are finished examining the LIFO contents, you can restore it in software vector mode using the following code sequence. In hardware vector mode, reading the INTC_IACKR does not push the INTC_CPR[PRI] onto the LIFO, therefore the LIFO contents cannot be restored in hardware vector mode. push_lifo: load stacked PRI value and store to INTC_CPR load INTC_IACKR if stacked PRI values are not depleted, branch to push_lifo Note: Reading the INTC_IACKR acknowledges the interrupt request to the processor and updates the INTC_CPR[PRI] with the priority of the preempting interrupt request. If the processor recognition of interrupts is disabled during the LIFO restoration, interrupt requests to the processor can go undetected. However, since the peripheral or software configurable interrupt requests are not cleared, the peripheral interrupt request to the processor re- asserts when INTC_CPR[PRI] is lower than the priorities of those peripheral or software configurable interrupt requests.

RM0029 System Integration Unit (SIU) Doc ID 15177 Rev 8 415/1740

16 System Integration Unit (SIU)

16.1 Overview

The System integration unit (SIU) controls this device’s reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO), internal peripheral multiplexing, and the system reset operation. The reset configuration block contains the external pin boot configuration logic. The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block provides uniform and discrete input/output control of the MCU I/O pins. The reset controller performs reset monitoring of internal and external reset sources, and drives the RSTOUT pin. The SIU is accessed by the core through the peripheral bus.

16.2 Features

System configuration – MCU reset configuration via external pins – Pad configuration control
System reset monitoring and generation – Power-on reset support – Reset Status Register provides last reset source to software – Glitch detection on reset input – Software controlled reset assertion
External interrupt – 15 interrupt requests – 1 Non-Maskable/Critical Interrupt request (NMI) – Rising or falling edge event detection – Programmable digital filter for glitch rejection
GPIO – GPIO function on 163 I/O pins – Dedicated input and output registers for each GPIO pin
Internal multiplexing – Allows serial and parallel chaining of DSPIs – Allows flexible selection of eQADC trigger inputs – Allows selection of interrupt requests between external pins and DSPI – Allows selection of some eTPU inputs from external eTPU pins or deserialized output from the DSPI module – Allows selection of serialized data source for the DSPI

System Integration Unit (SIU) RM0029 416/1740 Doc ID 15177 Rev 8

16.3 Modes of operation

16.3.1 Normal mode

In normal mode, the SIU provides the register interface and logic that controls system configuration, the reset controller, and GPIO.

16.3.2 Debug mode

SIU operation in debug mode is identical to operation in normal mode.

16.4 Block diagram

Figure 143 is a block diagram of the SIU. The signals shown are external pins to the device. The SIU registers are accessed through the crossbar switch. Note that the Power-on Reset Detection block, Pad Interface/Pad Ring block, and Peripheral I/O Channels are external to the SIU.

Figure 143. SIU block diagram

16.5 Signal description

Table 120 lists the external pins used by the SIU.

16.6 Memory map and register descriptions

16.6.1 Memory map

Table 121 is the address map for the SIU registers. Table 120. SIU signal properties

Internal weak pull up/down. The reset weak pull up/down st ate is given by the pull up/down state for the primary pin

function. For example, the reset weak pull up/down state of the BOOTCFG1 pin is weak pull down enabled.

See Table 5 in Section 3.1, Signal Properties for more information.

Table 121. SIU address map

Table 121. SIU address map (continued)

16.6.2 MCU ID Register 2 (SIU_MIDR2)

The MCU ID Register 2 contains additional configuration information about the device.

Gaps exist in this memory s pace where I/O pins are not available in the specified package.
The ETISR is sometimes referred to as ISEL0
The EIISR is sometimes referred to as ISEL1
The DISR is sometimes referred to as ISEL2

Figure 144. MCU ID Register 2 (SIU_MIDR2)

S_F set with metal option

Table 122. SIU_MIDR2 field description

15 SUPPLY

16.6.3 MCU ID Register (SIU_MIDR)

The MCU ID Register contains the part number and the package ID of the device. Table 123. Flash memory size Table 124. Flash memory size detailed (1)

Total flash memory size = (flash size 1) + (flash size 2)

Figure 145. MCU ID Register (SIU_MIDR)

16.6.4 Reset Status Register (SIU_RSR)

The Reset Status Register (SIU_RSR) reflects the most recent source, or sources, of reset. previously set bits in the SIU_RSR will be cleared.

Values corresponding to device packaging; see Table 125.
Values for these bits vary according to the package. See Table 125 for details.

Table 125. SIU_MIDR field description

16 CSP

Figure 146. Reset Status Register (SIU_RSR)

The reset values for this register are defined for power-on reset only.
The reset value of this bit is determined by the value latched on the associated pin at the negation of the last reset.
The reset value of this bit is determined by the inverse of the value latched on the associated EVTO pin.

Table 126. SIU_RSR field description 1: A Power-On Reset has occurred. 0: No Power-On Reset has occurred. 1: An External Reset has occurred. 0: No External Reset has occurred. 1: A Loss of Lock Reset has occurred. 0: No Loss of Lock Reset has occurred.

3 LCRS

0: No Loss of Clock Reset has occurred.

4 WDRS

1: A Watchdog Timer or Debug Reset has occurred. 0: No Watchdog Timer or Debug Reset has occurred. 1: An enabled SWT Reset has occurred. 0: No enabled SWT Reset has occurred.

16.6.5 System Reset Control Register (SIU_SRCR)

pin is negated regardless if the clock count has expired.

14 SSRS

1: A Software System Reset has occurred. 0: No Software System Reset has occurred.

15 SERF

1: A Software External Reset has occurred. 0: No Software External Reset has occurred.

16 WKPCFG

28 ABR

31 RGF

of the RESET pin or a power-on reset or a write of one to the bit. 1: A glitch was detected on the RESET pin. 0: No glitch was detected on the RESET pin. Table 126. SIU_RSR field description (continued)

Figure 147. System Reset Control Register (SIU_SRCR)

16.6.6 External Interrupt Status Register (SIU_EISR)

– IRQ15 inputs to the SIU. It also records the critical interrupts NMI and SWT.

This bit in the SPC564A74xx, SPC564A80xx MCU has no effect as checkstop reset is not supported.

Table 127. SIU_SRCR field description automatically cleared by all reset sources except the Software External Reset. 1: Generate a Software System Reset. 0: Do not generate a Software System Reset. predetermined number of clock cycles (refer to Section 4.3.2, RSTOUT), but the MCU is not reset. The bit is automatically cleared when the Software External Reset completes. 1: Generate a Software External Reset. 0: Do not generate a Software External Reset.

Figure 148. External IRQ Status Register (SIU_EISR)

16.6.7 DMA/Interrupt Request Enable Register (SIU_DIRER)

DMA request. There is only one interrupt request from the SIU to the interrupt controller. of the one interrupt request signal. Table 128. SIU_EISR field description This bit is set when a NMI interrupt occurs on the NMI input pin. This bit is set when a SWT interrupt occurs on the platform. This bit is set when an edge triggered event occurs on the corresponding IRQx input.

Figure 149. DMA/Interrupt Request Enable Register (SIU_DIRER)

16.6.8 DMA/Interrupt Request Select Register (SIU_DIRSR)

request for events on the IRQ[0:3] inputs.

This bit is cleared only by a reset.

Table 129. SIU_DIRER field description NMI pin. This bit is cleared only by a reset. interrupt. This bit is cleared only by a reset. when an edge triggered event occurs on the IRQx inputs.

Figure 150. DMA/Interrupt Request Select Register (SIU_DIRSR)

16.6.9 Overrun Status Register (SIU_OSR)

The Overrun Status Register contains flag bits that record an overrun. Figure 151. Overrun Status Register (SIU_OSR) Table 130. SIU_DIRSR field description

16.6.10 Overrun Request Enable Register (SIU_ORER)

interrupt controller is asserted. Figure 152. Overrun Request Enable Register (SIU_ORER)

16.6.11 IRQ Rising-Edge Event Enable Register (SIU_IREER)

by setting the corresponding bits in both the SIU_IREER and SIU_IFEER. Table 131. SIU_OSR field description This bit is set when an overrun occurs on the corresponding IRQx input. Table 132. SIU_ORER field description

Figure 153. IRQ Rising-Edge Event Enable Register (SIU_IREER)

16.6.12 External IRQ Falling-Edge Event Enable Register (SIU_IFEER)

enabled by setting the corresponding bits in both the SIU_IREER and SIU_IFEER.

This bit is cleared only by a reset.

Table 133. SIU_IREER field description This write once bit enables rising-edge triggered events by SWT. This bit is cleared only by a reset. This bit enables rising-edge triggered events on the corresponding IRQx input.

Figure 154. External IRQ Falling-Edge Event Enable Register (SIU_IFEER)

16.6.13 External IRQ Digital Filter Register (SIU_IDFR)

define the period of the digital filter.

This bit is cleared only by a reset.

Table 134. SIU_IFEER field description This write once bit enables falling-edge triggered events by SWT. This bit is cleared only by a reset. This bit enables falling-edge triggered events on the corresponding IRQx input.

Figure 155. IRQ Digital Filter Register (SIU_IDFR)

16.6.14 IRQ Filtered Input Register (SIU_IFIR)

The SIU_IFIR is a read-only register used to capture the filtered values of the IRQ0–31 pins. This feature is enabled with a parameter at the top level of the module. Table 135. SIU_IDFR field description accounts for synchronization of the IRQ input pins with the system clock. Using the same calculation, for a 150 MHz system clock, this gives a range of 13.3 ns to 218 µs.

Figure 156. IRQ Filtered Input Register (SIU_IFIR)

16.6.15 Pad Configuration Registers (SIU_PCR)

characteristics for configurable device pins. Not all device pins are configurable. for a definition of which I/O functions are available in each package. PCR but each field has an identical function in each register where it resides.

This bit is cleared only by a reset.

Table 136. SIU_PCR field description — Reserved fields are indicated by shading in the register maps. Selects the function of a multiplexed pad. Enables the pad as an output and drives the output buffer enable signal. 0 Disable output buffer for the pad. 1 Enable output buffer for the pad is enabled. Enables the pad as an input and drives the input buffer enable signal. 0 Disable input buffer for the pad. 1 Enable input buffer for the pad is enabled. the IBE bit is set, the actual value of the pin will be reflected in the corresponding GPDIx_x register. Controls the pad drive strength. Drive strength control pertains to pins with the fast I/O pad type. configurations can be selected. This feature applies to output pins only. 0 Disable open drain for the pad (push/pull driver enabled). 1 Enable open drain for the pad.

Depending on the register, the PA field size can vary in length.

appropriate number of leading ze roes from these values.

each register. Refer to Table 136 for the details of each field.

The register bit numbering order follows the Power Architecture standard of the most significant bit being bit 0. Field bit ranges are the opposite—the least significant bit is referred to as bit 0.
Bit 0 is an example of a reserved field. It is read-only and always returns a value of 0. HYS(4) Input hysteresis Controls whether hysteresis is enabled for the pad. 0 Disable hysteresis for the pad. 1 Enable hysteresis for the pad. SRC(3) Slew rate control Controls slew rate for the pad. Slew rate control pertains to pins with slow or medium I/O pad types, and the output signals are driven according to the value of this field. Actual slew rate depends on the pad type and load. Refer to the electrical specifications for this information.

00 Minimum slew rate

01 Medium slew rate

10 Invalid value

11 Maximum slew rate

devices are enabled by default. 0 Disable weak pull device for the pad. 1 Enable weak pull device for the pad. pullup/down devices are enabled. which the WKPCFG pin does not determine the reset weak pullup/down state. 0 Pulldown is enabled for the pad. 1 Pullup is enabled for the pad.

In cases where an I/O function is either input-only or output-only the IBE and OBE bits do not need to be set to enable pin
For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

If a pin is configured as an input, the ODE, SRC, and DSC bits do not apply.
If a pin is configured as an output, the HYS bit does not apply.
When a pin is configured as an output, the weak internal pull up/down is disabled regardless of the WPE or WPS settings in

Table 136. SIU_PCR field description (continued)

Figure 157. Sample PCR map

OBE bit is significant in GPIO
IBE bit is significant in GPIO
In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits.

Set IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

Figure 160. Pad Configuration Register (SIU_PCR2) Table 138. SIU_PCR1 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the

IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between

input and output is handled internally and the IBE and OBE bits are ignored.

When configured as CS[2] or ADDR[10] the OBE bit has no effect. When configured as GPO, set the OBE bit to one.
When configured as CS[2] or GPO, set the IBE bit to one to reflect the pin state in the GPDI register. When configured as

GPI, set the IBE bit to one.

When configured as CS[2] or ADDR[10], set the ODE bit to zero.
See the EBI section for weak pull up settings when configured as CS[0].

Table 139. SIU_PCR2 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the

IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between

input and output is handled internally and the IBE and OBE bits are ignored.

Figure 163. Pad Configuration Register (SIU_PCR9) Table 141. SIU_PCR8 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the

IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between

input and output is handled internally and the IBE and OBE bits are ignored.

When configured as ADDR[13] the OBE bit has no effect. When configured as GPO, the OBE bit should be set to one.
When configured as ADDR[13], WE [2] or GPO, the IBE bit may be set to one to reflect the pin state in the corresponding
When configured as ADDR[13], the ODE bit should be set to zero.
See the EBI section for weak pull up settings when configured as ADDR[13]

Table 142. SIU_PCR9 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the

IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between

input and output is handled internally and the IBE and OBE bits are ignored.

When configured as ADDR[14] the OBE bit has no effect. When configured as GPO, the OBE bit should be set to one.

Figure 168. Pad Configuration Register (SIU_PCR14) Table 146. SIU_PCR13 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

When configured as ADDR[18], FR_A_RX or DATA[18] the O BE bit has no effect. When configured as GPO, the OBE bit
When configured as ADDR[18] or GPO, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI

register. Setting the IBE bit to zero reduces power consumpt ion. When configured as GPI, the IBE bit should be set to one.

When configured as ADDR[18], the ODE bit should be set to zero.
See the EBI section for weak pull up settings when configured as ADDR[18]

Table 147. SIU_PCR14 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

Figure 171. Pad Configuration Register (SIU_PCR17) Table 149. SIU_PCR16 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

When configured as ADDR[21], FR_B_RX or DATA[21] the O BE bit has no effect. When configured as GPO, the OBE bit
When configured as ADDR[21], DATA[21] or GPO, the IBE bit may be set to one to reflect the pin state in the
When configured as ADDR[21] or DATA[21], the ODE bit should be set to zero.
See the EBI section for weak pull up setti ngs when configured as ADDR[21] or DATA[21].

Table 150. SIU_PCR17 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

Figure 174. Pad Configuration Register (SIU_PCR20) Table 152. SIU_PCR19 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the

IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically , such as the external data bus, switching between

input and output is handled internally and the IBE and OBE bits are ignored.

When configured as ADDR[24] or DATA[24] the OBE bit has no effect. When configured as GPO, the OBE bit should be
When configured as ADDR[24], DATA[24] or GPO, the IBE bit may be set to one to reflect the pin state in the
When configured as ADDR[24] or DATA[24], the ODE bit should be set to zero.
See the EBI section for weak pull up setti ngs when configured as ADDR[24] or DATA[24].

Table 153. SIU_PCR20 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the

IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically , such as the external data bus, switching between

input and output is handled internally and the IBE and OBE bits are ignored.

Figure 177. Pad Configuration Register (SIU_PCR23) Table 155. SIU_PCR22 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the

IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically , such as the external data bus, switching between

input and output is handled internally and the IBE and OBE bits are ignored.

When configured as ADDR[27] or DATA[27] the OBE bit has no effect. When configured as GPO, the OBE bit should be
When configured as ADDR[27], DATA[27] or GPO, the IBE bit may be set to one to reflect the pin state in the
When configured as ADDR[27] or DATA[27], the ODE bit should be set to zero.
See the EBI section for weak pull up setti ngs when configured as ADDR[27] or DATA[27].

Table 156. SIU_PCR23 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the

IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically , such as the external data bus, switching between

input and output is handled internally and the IBE and OBE bits are ignored.

Figure 180. Pad Configuration Register (SIU_PCR26) Table 158. SIU_PCR25 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the

IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically , such as the external data bus, switching between

input and output is handled internally and the IBE and OBE bits are ignored.

When configured as ADDR[30] or DATA[30], the OBE bit has no effect. When configured as GPO, the OBE bit should be
When configured as ADDR[30], ADDR[6], DATA[30] or GPO, the IBE bit may be set to one to reflect the pin state in the
When configured as ADDR[30], ADDR[6] or DATA[30], the ODE bit should be set to zero.
See the EBI section for weak pull up settings when configured as ADDR[30], ADDR[6] or DATA[30].

Table 159. SIU_PCR26 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the

IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically , such as the external data bus, switching between

input and output is handled internally and the IBE and OBE bits are ignored.

Figure 183. Pad Configuration Register (SIU_PCR29) Table 161. SIU_PCR28 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the

IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically , such as the external data bus, switching between

input and output is handled internally and the IBE and OBE bits are ignored.

When configured as DATA[1] or ADDR[17] the OBE bit has no effect. When configured as GPO, the OBE bit should be set
When configured as DATA[1], ADDR[17] or GPO, the IBE bit may be set to one to reflect the pin state in the corresponding
When configured as DATA[1] or ADDR[17], the ODE bit should be set to zero.
See the EBI section for weak pull up setti ngs when configured as DATA[1] or ADDR[17].

Table 162. SIU_PCR29 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the

IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically , such as the external data bus, switching between

input and output is handled internally and the IBE and OBE bits are ignored.

Figure 186. Pad Configuration Register (SIU_PCR32) Table 164. SIU_PCR31 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the

IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically , such as the external data bus, switching between

input and output is handled internally and the IBE and OBE bits are ignored.

When configured as DATA[4] or ADDR[20] the OBE bit has no effect. When configured as GPO, the OBE bit should be set
When configured as DATA[4], ADDR[20] or GPO, the IBE bit may be set to one to reflect the pin state in the corresponding
When configured as DATA[4] or ADDR[20], the ODE bit should be set to zero.
See the EBI section for weak pull up setti ngs when configured as DATA[4] or ADDR[20].

Table 165. SIU_PCR32 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the

IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically , such as the external data bus, switching between

input and output is handled internally and the IBE and OBE bits are ignored.

Figure 189. Pad Configuration Register (SIU_PCR35) Table 167. SIU_PCR34 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the

IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically , such as the external data bus, switching between

input and output is handled internally and the IBE and OBE bits are ignored.

When configured as DATA[7] or ADDR[23] the OBE bit has no effect. When configured as GPO, the OBE bit should be set
When configured as DATA[7], ADDR[23] or GPO, the IBE bit may be set to one to reflect the pin state in the corresponding
When configured as DATA[7] or ADDR[23], the ODE bit should be set to zero.
See the EBI section for weak pull up setti ngs when configured as DATA[7] or ADDR[23].

Table 168. SIU_PCR35 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the

IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically , such as the external data bus, switching between

input and output is handled internally and the IBE and OBE bits are ignored.

Figure 192. Pad Configuration Register (SIU_PCR38) Table 170. SIU_PCR37 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the

IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically , such as the external data bus, switching between

input and output is handled internally and the IBE and OBE bits are ignored.

When configured as DATA[10] or ADDR[26] the OBE bit has no effect. When configured as GPO, the OBE bit should be
When configured as DATA[10], ADDR[26] or GPO, the IBE bit may be set to one to reflect the pin state in the
When configured as DATA[10] or ADDR[26], the ODE bit should be set to zero.
See the EBI section for weak pull up setti ngs when configured as DATA[10] or ADDR[26].

Table 171. SIU_PCR38 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the

IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically , such as the external data bus, switching between

input and output is handled internally and the IBE and OBE bits are ignored.

Figure 195. Pad Configuration Register (SIU_PCR41) Table 173. SIU_PCR40 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the

IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically , such as the external data bus, switching between

input and output is handled internally and the IBE and OBE bits are ignored.

When configured as DATA[13] or ADDR[29] the OBE bit has no effect. When configured as GPO, the OBE bit should be
When configured as DATA[13], ADDR[29] or GPO, the IBE bit may be set to one to reflect the pin state in the
When configured as DATA[13] or ADDR[29], the ODE bit should be set to zero.
See the EBI section for weak pull up setti ngs when configured as DATA[13] or ADDR[29].

Table 174. SIU_PCR41 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the

IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically , such as the external data bus, switching between

input and output is handled internally and the IBE and OBE bits are ignored.

Figure 198. Pad Configuration Register (SIU_PCR62) Table 176. SIU_PCR43 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the

IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically , such as the external data bus, switching between

input and output is handled internally and the IBE and OBE bits are ignored.

When configured as RD_WR , the OBE bit has no effect. When configured as GPO, the OBE bit should be set to one.
When configured as RD_WR or GPO, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI

register. Setting the IBE bit to zero reduces power consumpt ion. When configured as GPI, the IBE bit should be set to one.

When configured as RD_WR , the ODE bit should be set to zero.
See the EBI section for weak pull up settings when configured as RD_WR .

Table 177. SIU_PCR62 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the

IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically , such as the external data bus, switching between

input and output is handled internally and the IBE and OBE bits are ignored.

When configured as GPO, the OBE bit should be set to one.

Figure 203. Pad Configuration Register (SIU_PCR69) Table 181. SIU_PCR68 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the

IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically , such as the external data bus, switching between

input and output is handled internally and the IBE and OBE bits are ignored.

When configured as TS , the OBE bit has no effect. When configured as GPO, the OBE bit should be set to one.
When configured as TS or GPO, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register.

Setting the IBE bit to zero reduces power consumption. When configured as GPI, the IBE bit should be set to one.

When configured as TS , the ODE bit should be set to zero.
See the EBI section for weak pull up settings when configured as TS .

Table 182. SIU_PCR69 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the

IBE and OBE bits. Set IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically , such as the external data bus, switching between

input and output is handled internally and the IBE and OBE bits are ignored.

When configured as TA , the OBE bit has no effect. When configured as GPO, the OBE bit should be set to one.

Figure 206. Pad Configuration Register (SIU_PCR76) Table 184. SIU_PCR75 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

This bit applies only to GPIO operation.
The ODE bit should be set to zero for MDO operation.
The HYS bit has no effect on MDO operation.
The WPE bit should be set to zero for MDO operation.

Table 185. SIU_PCR76 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

Figure 209. Pad Configuration Register (SIU_PCR79) Table 187. SIU_PCR78 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

This bit applies only to GPIO operation.
The ODE bit should be set to zero for MDO operation.
The HYS bit has no effect on MDO operation.
The WPE bit should be set to zero for MDO operation.

Table 188. SIU_PCR79 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

Figure 212. Pad Configuration Register (SIU_PCR82) Table 190. SIU_PCR81 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

This bit applies only to GPIO operation.
The ODE bit should be set to zero for MDO operation.
The HYS bit has no effect on MDO operation.
The WPE bit should be set to zero for MDO operation.

Table 191. SIU_PCR82 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

When configured as GPO, the OBE bit should be set to one.

Figure 217. Pad Configuration Register (SIU_PCR87)

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored. Table 195. SIU_PCR86 PA values

When configured as GPO, the OBE bit should be set to one.
When configured as CAN_C_TX, DSPI_D_PCS[3] or GPO, the IBE bit may be set to one to reflect the pin state in the

Table 196. SIU_PCR87 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

Figure 220. Pad Configuration Register (SIU_PCR90) Table 198. SIU_PCR89 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

When configured as SCI_A_RX the OBE bit has no effect. When configured as GPO, the OBE bit should be set to one.
When configured as EMIOS[15] or GPO, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI

consumption. When configured as GPI, the IBE bit should be set to one. Table 199. SIU_PCR90 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

Figure 225. Pad Configuration Register (SIU_PCR95) Table 203. SIU_PCR94 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

This signal name is us ed to support legacy naming.
The SOUTA function is not available on the SPC564A74xx, SPC564A80xx. Do not select 0b01 or 0b11 for the PA field.
When configured as GPO, the OBE bit should be set to one.
When configured as DSPI_C_PCS[5] or GPO, the IBE bit may be set to one to reflect the pin state in the corresponding

Table 204. SIU_PCR95 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

This signal name is us ed to support legacy naming.

Figure 228. Pad Configuration Register (SIU_PCR98) Table 206. SIU_PCR97 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

This signal name is us ed to support legacy naming.
The PCSA[2] function is not available on the SPC564A74xx, SPC564A80xx. Do not select 0b01 or 0b11 for the PA field.
When configured as DSPI_D_SCK, the OBE bit should be se t to one for master operation, and set to zero for slave

operation. When configured as GPO, the OBE bit should be set to one.

When configured as DSPI_D_SCK in sl ave operation, the IBE bit should be set to one. When configured as DSPI_D_SCK

in master operation or GPO, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register. Setting the IBE bit to zero reduces power consumption. When configured as GPI, the IBE bit should be set to one. Table 207. SIU_PCR98 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

The PCSA[3] function is not available on the SPC564A74xx, SPC564A80xx. Do not select 0b01 or 0b11 for the PA field.

Figure 233. Pad Configuration Register (SIU_PCR103) Table 211. SIU_PCR102 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

When configured as DSPI_B_SIN, the OBE bit should be set to zero. When configured as PCS, the OBE bit should be set
When configured as DSPI_B_SIN or DSPI_C_PCS[2], the IBE bit may be set to one to reflect the pin state in the

Table 212. SIU_PCR103 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

When configured as GPO, the OBE bit should be set to one.

Figure 238. Pad Configuration Register (SIU_PCR108) Table 216. SIU_PCR107 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

When configured as DSPI_C_SIN, the OBE bit has no effect. When configured as GPO, the OBE bit should be set to one.
When configured as DSPI_B_PCS[3] or GPO, the IBE bit ma y be set to one to reflect the pin state in the corresponding

Table 217. SIU_PCR108 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

When configured as DSPI_C_SCK, the OBE bit should be se t to one for master operation, and set to zero for slave

operation. When configured as GPO, the OBE bit should be set to one.

Figure 241. Pad Configuration Register (SIU_PCR113) ETPU_A[12:23] and GPIO[114:125] signals. input and output channels of the ETPU_A[0:11] signals are connected to pins.

When configured as TCRCLKA or IRQ, the OBE bit has no ef fect. When configured as GPO, the OBE bit should be set to
When configured as TCRCLKA or IRQ or GPO, the IBE bit may be set to one to reflect the pin state in the corresponding

Table 220. SIU_PCR113 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

Figure 244. Pad Configuration Register (SIU_PCR116)

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored. Table 222. SIU_PCR115 PA values

The OBE bit must be set to one for both ETPU_A[2] and GPIO[116] when configured as outputs.
The IBE bit must be set to one for both ETPU_A[2] and GP IO[116] when configured as inputs. When configured as

state in the corresponding GPDI register.

The weak pull up/down selection at reset for the ETPU_A[2] pin is determined by the WKPCFG pin.

Table 223. SIU_PCR116 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

The OBE bit must be set to one for both ETPU_A[3] and GPIO[117] when configured as outputs.

Figure 249. Pad Configuration Register (SIU_PCR121) Table 227. SIU_PCR120 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

The OBE bit must be set to one for both ETPU_A[7] and GPIO[121] when configured as outputs.
The IBE bit must be set to one for both ETPU_A[7] and GP IO[121] when configured as inputs. When configured as

state in the corresponding GPDI register.

The weak pull up/down selection at reset for the ETPU_A[7] pin is determined by the WKPCFG pin.

Table 228. SIU_PCR121 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

Figure 252. Pad Configuration Register (SIU_PCR124) Table 230. SIU_PCR123 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

The OBE bit must be set to one for both ETPU_A[10] and GPIO[124] when configured as outputs.
The IBE bit must be set to one for both ETPU_A[10] and GPIO[124] when configured as inputs. When configured as

state in the corresponding GPDI register.

The weak pull up/down selection at reset for the ETPU_A[10] pin is determined by the WKPCFG pin.

Table 231. SIU_PCR124 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

Figure 255. Pad Configuration Register (SIU_PCR127) Table 233. SIU_PCR126 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

The OBE bit must be set to one for both ETPUA and GPIO when configured as outputs.
The IBE bit must be set to one for both ETPUA and GPIO when configured as inputs. When configured as PCS, or ETPUA

or GPO outputs, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register.

The weak pull up/down selection at reset for the ETPU_A[13] pin is determined by the WKPCFG pin.

Table 234. SIU_PCR127 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

Figure 258. Pad Configuration Register (SIU_PCR130) Table 236. SIU_PCR129 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

The OBE bit must be set to one for both ETPUA and GPIO when configured as outputs.
The IBE bit must be set to one for both ETPUA and GPIO when configured as inputs. When configured as PCS, or ETPUA

or GPO outputs, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register.

The weak pull up/down selection at reset for the ETPU_A[16] pin is determined by the WKPCFG pin.

Table 237. SIU_PCR130 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

Figure 261. Pad Configuration Register (SIU_PCR133) Table 239. SIU_PCR132 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

The OBE bit must be set to one for both ETPUA and GPIO when configured as outputs.
The IBE bit must be set to one for both ETPUA and GPIO when configured as inputs. When configured as PCS, or ETPUA

or GPO outputs, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register.

The weak pull up/down selection at reset for the ETPU_A[19] pin is determined by the WKPCFG pin.

Table 240. SIU_PCR133 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

Figure 264. Pad Configuration Register (SIU_PCR136) Table 242. SIU_PCR135 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

When configured as IRQ, the OBE bit has no effect. The OBE bit must be set to one for both ETPU_A[22] and GPIO[136]
When configured as ETPU_A[17], IRQ or GPO, the IBE bit may be set to one to reflect the pin state in the corresponding

and GPIO[136] when configured as inputs.

The weak pull up/down selection at reset for the ETPU_A[22] pin is determined by the WKPCFG pin.

Table 243. SIU_PCR136 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

Figure 267. Pad Configuration Register (SIU_PCR139) Table 245. SIU_PCR138 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

The eTPU function controlled by this register has an additional dependency on the SIU_ISEL8 register settings. Please see

Section 16.6.22, IMUX Select Register 8 (SIU_ISEL8) , for more detail.

When configured as IRQ, the OBE bit has no effect. The OBE bit must be set to one for both ETPU_A[25] and GPIO[139]
When configured as IRQ, DSPI_C_SCK_LV DS+ or GPO, the IBE bit may be set to one to reflect the pin state in the

both ETPU_A[25] and GPIO[139] when configured as inputs.

The weak pull up/down selection at reset for the ETPU_A[25] pin is determined by the WKPCFG pin.

Table 246. SIU_PCR139 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

The eTPU function controlled by this register has an additional dependency on the SIU_ISEL8 register settings. Please see

Section 16.6.22, IMUX Select Register 8 (SIU_ISEL8) , for more detail.

Figure 270. Pad Configuration Register (SIU_PCR142) Table 248. SIU_PCR141 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

The eTPU function controlled by this register has an additional dependency on the SIU_ISEL8 register settings. Please see

Section 16.6.22, IMUX Select Register 8 (SIU_ISEL8) , for more detail.

When configured as GPO, the OBE bit should be set to one.
When configured as PCS or GPO, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register.

Setting the IBE bit to zero reduces power consumption. The IB E bit must be set to one for GPIO when configured as input.

The weak pull up/down selection at reset for the ETPU_A[28] pin is determined by the WKPCFG pin.

Table 249. SIU_PCR142 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

The eTPU function controlled by this register has an additional dependency on the SIU_ISEL8 register settings. Please see

Section 16.6.22, IMUX Select Register 8 (SIU_ISEL8) , for more detail.

Figure 273. Pad Configuration Register (SIU_PCR145) Table 251. SIU_PCR144 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

When configured as ETPUA output or GPO, the OBE bit should be set to one.
When configured as ETPUA output, DSPI_C_PCS[4], ETPU_A[13] or GPO, the IBE bit may be set to one to reflect the pin

one for ETPUA or GPIO when configured as input.

The weak pull up/down selection at reset for the ETPU_A[31] pin is determined by the WKPCFG pin.

Table 252. SIU_PCR145 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

Figure 276. Pad Configuration Register (SIU_PCR181)

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored. Table 254. SIU_PCR180 PA values

The OBE bit must be set to one for both EMIOS[2] and GPIO[181] when configured as outputs.
When configured as ETPU, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register. Setting

Table 255. SIU_PCR181 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

The OBE bit must be set to one for both EMIOS[3] and GPIO[182] when configured as outputs.

Figure 281. Pad Configuration Register (SIU_PCR186) Table 259. SIU_PCR185 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

The OBE bit must be set to one for both EMIOS[7] and GPIO[186] when configured as outputs.
When configured as ETPU, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register. Setting

Table 260. SIU_PCR186 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

The OBE bit must be set to one for both EMIOS[8] and GPIO[187] when configured as outputs.

Figure 286. Pad Configuration Register (SIU_PCR191) Table 264. SIU_PCR190 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

The OBE bit must be set to one for GPIO[191] when configured as an output.
When configured as ETPU_A[27] or GPO the IBE bit may be set to one to reflect the pin state in the corresponding GPDI
The weak pull up/down selection at reset for the EMIOS[12] pin is determined by the WKPCFG pin.

Table 265. SIU_PCR191 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

Figure 289. Pad Configuration Register (SIU_PCR194)

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored. Table 267. SIU_PCR193 PA values

The OBE bit must be set to one for GPIO[194] when configured as outputs.
When configured as IRQ, ETPU or GPO, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI

Table 268. SIU_PCR194 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

Figure 298. Pad Configuration Register (SIU_PCR203) Table 276. SIU_PCR202 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

The PA bit should be set to one for EMIOS and cleared to zero when used as GPIO.
When configured as GPO, the OBE bit should be set to one.
When configured as EMIOS or GPO, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI

register. Setting the IBE bit to zero reduces power consumpt ion. When configured as GPI, the IBE bit should be set to one. Table 277. SIU_PCR203 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

Figure 305. Pad Configuration Register (SIU_PCR211) Table 283. SIU_PCR210 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

The BOOTCFG function applies only during reset when the RSTCFG pin is asserted during reset.
When configured as IRQ, the OBE bit has no effect. When configured as GPO, the OBE bit should be set to one.
When configured as IRQ or GPO, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register.

Setting the IBE bit to zero reduces power consumption. When configured as GPI, the IBE bit should be set to one.

When configured as IRQ, the HYS bit should be set to one.

Table 284. SIU_PCR211 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

The BOOTCFG function applies only during reset when the RSTCFG pin is asserted during reset.
When configured as IRQ, the OBE bit has no effect. When configured as GPO, the OBE bit should be set to one.

Figure 312. Pad Configuration Register (SIU_PCR218) GPIO[219] and MCKO. Please carefully note the pin(s) affected by the bits in this register. Table 290. SIU_PCR217 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

Input and output buffers are enabled/disabled based on PA selection. Both input and output buffer disabled for AN[15]

function. Output buffer only enabled for FCK and ETPU functions. Table 291. SIU_PCR218 PA values

In cases where an I/O function can be either an input or an output, I/O direction is specified using the IBE and OBE bits. Set

IBE = 1 for input or OBE = 1 for output.

For I/O functions that change direction dynamically, such as the external data bus, switching between input and output is

handled internally and the IBE and OBE bits are ignored.

Figure 313. Pad Configuration Register (SIU_PCR219)

When configured as GPO, the OBE bit should be set to 1.
When configured as GPO, the IBE bit may be set to one to reflect the pin state in the corresponding GPDI register. When

configured as GPI, the IBE bit should be set to one. Table 292. SIU_PCR219 field descriptions Enables the pad as an output and drives the output buffer enable signal. 0 Disable output buffer for the pad. 1 Enable output buffer for the pad is enabled. This field affects only the GPIO[219] pin. Enables the pad as an input and drives the input buffer enable signal. 0 Disable input buffer for the pad. 1 Enable input buffer for the pad is enabled. IBE bit is set, the actual value of the pin will be reflected in the corresponding GPDIx_x register. This field affects only the GPIO[219] pin. Controls the pad drive strength. Drive strength control pertains to pins with the fast I/O pad type. This field affects only the MCKO pin.

can be selected. This feature applies to output pins only. 0 Disable open drain for the pad (push/pull driver enabled). 1 Enable open drain for the pad. This field affects both the GPIO[219] and MCKO pins. Controls whether hysteresis is enabled for the pad. 0 Disable hysteresis for the pad. 1 Enable hysteresis for the pad. This field affects both the GPIO[219] and MCKO pins. pad type and load. Refer to the electrical specifications for this information. This field affects only the GPIO[219] pin. devices are enabled by default. 0 Disable weak pull device for the pad. 1 Enable weak pull device for the pad. This field affects both the GPIO[219] and MCKO pins. WKPCFG pin does not determine the reset weak pullup/down state. 0 Pulldown is enabled for the pad. 1 Pullup is enabled for the pad. This field affects both the GPIO[219] and MCKO pins.

In cases where an I/O function is either input-only or output-only the IBE and OBE bits do not need to be set to enable pin

Table 292. SIU_PCR219 field descriptions (continued)

Figure 337. Pad Configuration Register 350 – 381 (SIU_PCR350 – SIU_PCR381) Table 316. SIU_PCR350 – SIU_PCR381 DSPI muxing

The SIU_PCR382 – SIU_PCR389 registers control the muxing of the signals to the DSPI. PA field values are shown in Table 317. Figure 338. Pad Configuration Register 382 – 389 (SIU_PCR382 – SIU_PCR389) The SIU_PCR390 – SIU_PCR413 registers control the muxing of the signals to the DSPI. PA field values are shown in Table 318. Table 316. SIU_PCR350 – SIU_PCR381 DSPI muxing (continued) Table 317. SIU_PCR382 – SIU_PCR389 DSPI muxing

Figure 339. Pad Configuration Register 390 – 413 (SIU_PCR390 – SIU_PCR413) Table 318. SIU_PCR390 – SIU_PCR413 DSPI muxing

16.6.16 GPIO Pin Data Output Registers (SIU_GPDO0_3 – SIU_GPDO412_413)

when the pins are configured for their primary function by the corresponding PCR. is not available in the package. Table 318. SIU_PCR390 – SIU_PCR413 DSPI muxing (continued)

Figure 340. GPIO Pin Data Out Register 0 – 3 (SIU_GPDO0 – SIU_GPDO3) Figure 341. GPIO Pin Data Out Register 412 – 413 (SIU_GPDO410 – SIU_GPDO413)

16.6.17 GPIO Pin Data Input Registers (SIU_GPDI0_3 – SIU_GPDI_232)

reflects the actual state of the output pin. Table 319. SIU_GPDOx_x field description 0 VOL is driven on the external GPIO pin when the pin is configured as an output. 1 VOH is driven on the external GPIO pin when the pin is configured as an output.

16.6.19 External IRQ Input Select Register (SIU_EIISR (m))

The EIISR selects the source for the external interrupt/DMA inputs. Table 321. SIU_ETISR field description

11 ETRIG[1] pin

11 ETRIG[0] pin

Figure 346. External IRQ Input Select Register (SIU_EIISR) Table 322. SIU_EIISR field description

00 IRQ[15] pin

01 DSPI_B[15] deserialized output

10 DSPI_C[0] deserialized output

11 DSPI_D[1] deserialized output

00 IRQ[14] pin

01 DSPI_B[14] deserialized output

10 DSPI_C[15] deserialized output

11 DSPI_D[0] deserialized output

00 IRQ[13] pin

01 DSPI_B[13] deserialized output

10 DSPI_C[14] deserialized output

11 DSPI_D[15] deserialized output

00 IRQ[12] pin

01 DSPI_B[12] deserialized output

10 DSPI_C[13] deserialized output

11 DSPI_D[14] deserialized output

00 IRQ[11] pin

01 DSPI_B[11] deserialized output

10 DSPI_C[12] deserialized output

11 DSPI_D[13] deserialized output

00 IRQ[10] pin

01 DSPI_B[10] deserialized output

10 DSPI_C[11] deserialized output

11 DSPI_D[12] deserialized output

00 IRQ[9] pin

01 DSPI_B[9] deserialized output

10 DSPI_C[10] deserialized output

11 DSPI_D[11] deserialized output

00 IRQ[8] pin

01 DSPI_B[8] deserialized output

10 DSPI_C[9] deserialized output

11 DSPI_D[10] deserialized output

00 IRQ[7] pin

01 DSPI_B[7] deserialized output

10 DSPI_C[8] deserialized output

11 DSPI_D[9] deserialized output

00 IRQ[6] pin

01 DSPI_B[6] deserialized output

10 DSPI_C[7] deserialized output

11 DSPI_D[8] deserialized output

00 IRQ[5] pin

01 DSPI_B[5] deserialized output

10 DSPI_C[6] deserialized output

11 DSPI_D[7] deserialized output

00 IRQ[4] pin

01 DSPI_B[4] deserialized output

10 DSPI_C[5] deserialized output

11 DSPI_D[6] deserialized output

00 IRQ[3] pin

01 DSPI_B[3] deserialized output

10 DSPI_C[4] deserialized output

11 DSPI_D[5] deserialized output

00 IRQ[2] pin

01 DSPI_B[2] deserialized output

10 DSPI_C[3] deserialized output

11 DSPI_D[4] deserialized output

Table 322. SIU_EIISR field description (continued)

16.6.20 DSPI Input Select Register (SIU_DISR (n))

input to allow serial and parallel chaining of the DSPI blocks. Figure 347. DSPI Input Select Register (SIU_DISR)

00 IRQ[1] pin

01 DSPI_B[1] deserialized output

10 DSPI_C[2] deserialized output

00 IRQ[0] pin

01 DSPI_B[0] deserialized output

10 DSPI_C[1] deserialized output

Table 323. SIU_DISR field description

00 DSPI_B_SIN pin

10 DSPI_C_SOUT

11 DSPI_D_SOUT

00 DSPI_B_PCS[0] pin

10 DSPI_C_PCS[0] (Master)

11 DSPI_D_PCS[0] (Master)

00 DSPI_B_SCK pin

10 DSPI_C_SCK (Master)

11 DSPI_D_SCK (Master)

00 Reserved

10 DSPI_C_PCS[4]

11 DSPI_D_PCS[4]

00 DSPI_C_SIN pin

10 DSPI_B_SOUT

00 DSPI_C_PCS[0] pin

10 DSPI_B_PCS[0] (Master)

00 DSPI_C_SCK pin

10 DSPI_B_SCK (Master)

10 DSPI_B_PCS[4]

00 DSPI_D_SIN pin

11 DSPI_C_SOUT

Table 323. SIU_DISR field description (continued)

16.6.21 IMUX Select Register 3 (SIU_ISEL3)

The SIU_ISEL 3 register selects the source for the external eQADC trigger inputs. Figure 348. IMUX Select Register 3 (SIU_ISEL3) can be commanded to make regular samples but only during a given time or angle window.

00 DSPI_D_PCS[0] pin

11 DSPI_C_PCS[0] (Master)

00 DSPI_D_SCK pin

11 DSPI_C_SCK (Master)

11 DSPI_C_PCS[4]

Table 324. eQADC queue0 enhanced trigger selection

Table 325. eQADC queue1 enhanced trigger selection

Table 326. eQADC queue2 enhanced trigger selection

Table 327. eQADC queue3 enhanced trigger selection

Table 328. eQADC queue4 enhanced trigger selection

00000 G P I O 2 0 6 ( e T R I G 0 )

16.6.22 IMUX Select Register 8 (SIU_ISEL8)

The SIU_ISEL8 Register is used to multiplex the eTPU[24:29] inputs. Table 329. eQADC queue5 enhanced trigger selection

These six eTPU channels can come from the output of the DSPI or the corresponding pad. connected to their respective output pin, irrespective of the SIU_PCR[PA] field. Figure 349. IMUX Select Register 8 (SIU_ISEL8) Table 330. SIU_ISEL8 field description

0 DSPI_B[8] deserialized output

0 DSPI_B[9] deserialized output

0 DSPI_B[10] deserialized output

0 DSPI_B[11] deserialized output

0 DSPI_B[12] deserialized output

16.6.23 IMUX Select Register 9 (SIU_ISEL9)

channels. A mux select register is required to select the source of this new queue0 trigger. Figure 350. IMUX Select Register 9 (SIU_ISEL9)

0 DSPI_B[13] deserialized output

Table 330. SIU_ISEL8 field description (continued) Table 331. eQADC advance trigger selection

16.6.24 IMUX Select Register 10 (SIU_ISEL10)

signal and Section 26.3.4, Integrator reset signal. Table 331. eQADC advance trigger selection (continued)

Figure 351. IMUX Select Register 10 (SIU_ISEL10 or SIU_DECFIL1) Table 332. Decimation filter control source selection

16.6.25 Chip Configuration Register (SIU_CCR)

Figure 352. Chip Configuration Register (SIU_CCR)

During reset the comparison is performed and result is uncertain
The value after reset is uncertain

Table 333. SIU_CCR field description of the SIU_CBRH/SIU_CBRL registers are equal.

0 Match input signal is negated

1 Match input signal is asserted

word and the boot configuration bits.

0 Nexus disable input signal is negated

1 Nexus disable input signal is asserted

driven onto the calibration bus pins will be reflected onto the non-calibration bus pins.

0 Calibration reflection suppression is disabled

1 Calibration reflection suppression is enabled

31 Reserved

16.6.26 External Clock Control Register (SIU_ECCR)

global signals asynchronous reset signal. Figure 353. External Clock Control Register (SIU_ECCR)

0 EBDF

Table 334. SIU_ECCR field description Engineering clock (ENGCLK) source select. 0 ENGCLK source is system clock. 1 ENGCLK source is crystal oscillator clock.

16.6.27 Compare A High Register (SIU_CARH)

Figure 354. Compare A High Register (SIU_CARH)

16.6.28 Compare A Low Register (SIU_CARL)

The EBTS bit must not be modified while an external bus transaction is in progress.

29 Reserved

00 External bus division factor = 1

01 External bus division factor = 2

10 Reserved

11 External bus division factor = 4

guarantee that the switch will be glitchless. Table 334. SIU_ECCR field description (continued)

Figure 355. Compare A Low Register (SIU_CARL)

16.6.29 Compare B High Register (SIU_CBRH)

Figure 356. Compare B High Register (SIU_CBRH)

16.6.30 Compare B Low Register (SIU_CBRL)

Figure 357. Compare B Low Register (SIU_CBRL)

16.6.31 System Clock Register (SIU_SYSDIV)

Figure 358. System Clock Register (SIU_SYSDIV) Table 335. SIU_SYSDIV field description

1 When CAN_CTRL[CLK_SRC] = 1, FlexCAN runs at half the system frequency

0 When CAN_CTRL[CLK_SRC] = 1, FlexCAN runs at the system frequency

See Section , Support for CAN interface operation.

16.6.32 Halt Register (SIU_HLT)

Figure 359. Halt Register (SIU_HLT)

1 System clock divider is bypassed

0 System clock divider is not bypassed

output of the clock divider is nominally a 50% duty cycle.

00 Divide by 2

01 Divide by 4

10 Divide by 8

11 Divide by 16

SIU_SYSDIV[BYPASS] = 1, the system clock divider is bypassed and “divide by 1” is selected. Table 335. SIU_SYSDIV fiel d description (continued)

Table 336. SIU_HLT field description

3 Reserved (unimplemented)

When asserted, a stop request is sent to the eTPU module and the eTPU Nexus module. When asserted, a stop request is sent to the Nexus Controller. When asserted, a stop request is sent to the eQADC module. When asserted, a stop request is sent to the Reaction module. When asserted, a stop request is sent to the eMIOS module. When asserted, a stop request is sent to the decimation filter module.

12 Reserved

When asserted, a stop request is sent to the periodic interrupt timer module.

When asserted, a stop request is sent to the FlexCAN C module. When asserted, a stop request is sent to the FlexCAN B module. When asserted, a stop request is sent to the FlexCAN A module. When asserted, a stop request is sent to the DSPI C. When asserted, a stop request is sent to the DSPI C. When asserted, a stop request is sent to the DSPI B. When asserted, a stop request is sent to the eSCI C module. When asserted, a stop request is sent to the eSCI B module. When asserted, a stop request is sent to the eSCI A module. Table 336. SIU_HLT field description (continued)

16.6.33 Halt Acknowledge Register (SIU_HLTACK)

module clocks disabled. This register is read-only. Figure 360. Halt Acknowledge Register (SIU_HLTACK) Table 337. SIU_HLTACK field description cross-bar, peripheral bridge, system RAM, Flash, STM, DMA. When asserted, indicates that a stop acknowledge was received from the NSETI module. When asserted, indicates that a stop acknowledge was received from the eTPU module.

When asserted, indicates that a stop acknowledge was received from the Nexus Controller. which handles the calibration interface. When asserted, indicates that a stop acknowledge was received from the eQADC module. When asserted, indicates that a stop acknowledge was received from the Reaction module. When asserted, indicates that a stop acknowledge was received from the eMIOS module. When asserted, indicates that a stop acknowledge was received from the decimation filter module. When asserted, indicates that a stop acknowledge was received from the FlexCAN C module. When asserted, indicates that a stop acknowledge was received from the FlexCAN B module. Table 337. SIU_HLTACK field description (continued)

16.6.34 Core MMU PID Control Register (SIU_EMPCR0)

in calibration activities requiring real-time switching between calibration data tables. When asserted, indicates that a stop acknowledge was received from the FlexCAN A module. When asserted, indicates that a stop acknowledge was received from the DSPI D. When asserted, indicates that a stop acknowledge was received from the DSPI C. When asserted, indicates that a stop acknowledge was received from the DSPI B. When asserted, indicates that a stop acknowledge was received from the eSCI C module. When asserted, indicates that a stop acknowledge was received from the eSCI B module. When asserted, indicates that a stop acknowledge was received from the eSCI A module.

The mechanism is detailed in Figure 361 and Table 338. Figure 361. Core MMU PID Control Register (SIU_EMPCR0) Table 338. SIU_EMPCR0 field description 0: The contents of this register are not used to select the alternate MMU mapping.

RM0029 System Integration Unit (SIU) Doc ID 15177 Rev 8 583/1740

16.7 Functional description

The following sections provide an overview of the SIU operation features.

16.7.1 System configuration

Two BOOTCFG signals are implemented in SPC564A74xx, SPC564A80xx MCUs. The BAM program uses the BOOTCFG0 bit to determine where to read the reset configuration word, and whether to initiate a FlexCAN or eSCI boot. See Section 4.7.1, Reset configuration half word (RCHW), for details on the RCHW. Table 387 in Section 21.5.2, BAM program operation, defines the boot modes specified by the BOOTCFG0 and BOOTCFG1 pins. During the assertion of RSTOUT, the BOOTCFG0 and BOOTCFG1 pins are used to update the RSR and the BAM boot mode. This device has a second serial boot mode to support a new serial boot with CAN and SCI baudrate auto-detection. For additional details on the BAM program operation see Chapter 21: Boot Assist Module (BAM). Pad configuration The Pad Configuration Registers (PCR) in the SIU allow software control of the static electrical characteristics of external pins. The multiplexed function of a pin, selection of pull up or pull down devices, the slew rate of I/O signals, open drain mode for output pins, hysteresis on input pins, and the drive strength for bus signals can be specified through the PCRs.

16.7.2 Reset control

The reset controller logic is located in the SIU. See Chapter 4: Resets for details on reset operation.

16.7.3 External interrupt request input (IRQ)

The fifteen external interrupt request inputs available on this device (IRQ[0:5,7:15]) connect to the SIU IRQ inputs. The External IRQ Input Select Register (EIISR) specifies the IRQ [0:5,7:15] signals that are input to the SIU IRQs. Note: IRQ[6] can be only generated by the deserialized output of the DSPI module—not the external pins. External interrupt requests are triggered by rising- and/or falling-edge events that are enabled by setting a bit in:

IRQ rising-edge event enable register (SIU_IREER)
IRQ falling-edge event enable register (SIU_IFEER) If the bit is set in both registers, both rising- and falling-edge events trigger an interrupt request. Each IRQ has a counter that tracks the number of system clock cycles that occur between the rising- and falling-edge events. An IRQ counter exists for each IRQ rising- or falling-edge event enable bit.

System Integration Unit (SIU) RM0029 584/1740 Doc ID 15177 Rev 8 The digital filter length field in the IRQ digital filter register (SIU_IDFR) specifies the minimum number of system clocks that the IRQ signal must hold a logic value to qualify the edge-triggered event as a valid state change. When the number of system clocks in the IRQ counter equals the value in the digital filter length field, the IRQ state latches and the IRQ counter is cleared. If the previous filtered state of the IRQ does not match the current state, and the rising- or falling-edge event is enabled, the IRQ flag bit is set to 1. For example, the IRQ flag bit is set if a rising-edge event occurs under the following conditions:

Previous filtered IRQ state was a logic 0
Current latched IRQ state is a logic 1
Rising-edge event is enabled for the IRQ When the counter for an IRQ is not enabled, the state of the IRQ is held in the current and previous state latches. The IRQ counter operates independently of the IRQ or overrun flag bit. Clearing the IRQ flag or overrun flag bits does not clear or reload the counter. Refer to the following sections for more information:
Section 16.6.6, External Interrupt Status Register (SIU_EISR)
Section 16.6.11, IRQ Rising-Edge Event Enable Register (SIU_IREER)
Section 16.6.12, External IRQ Falling-Edge Event Enable Register (SIU_IFEER)
Section 16.6.13, External IRQ Digital Filter Register (SIU_IDFR) External interrupts The IRQ signals map to 15 independent interrupt requests output from the SIU. The IRQ flag bit is set when a rising-edge and/or falling-edge event occurs for the IRQ. An external IRQ signal is asserted when all of the following occur:
Enable bit is set in the IRQ rising- and/or falling-edge event registers (SIU_IREER, SIU_IFEER)
IRQ flag bit is set in the external interrupt status register (SIU_EISR)
Enable bit is cleared in the DMA/Interrupt request enable register (SIU_DIRER)
Select bit is cleared in the DMA/Interrupt select register (SIU_DIRSR) The NMI and SWT Interrupts can each generate an NMI Exception or Critical Interrupt Exception as an input to the core. This selection is controlled by the NMI_SEL8 and NMI_SEL0 (SIU_DIRER) signals respectively. When WKPCFG_NMI_GPIO213 is enabled as NMI, the pin will override the PCR configuration after reset. The SIU_DIRER selects between critical and non-maskable interrupt use, the SIU_EISR reports the status of NMI, and the SIU_IFEER selects edge sensitivity of the NMI input.

Figure 362. SIU DMA/Interrupt request diagram

Section 16.6.7, DMA/Interrupt Request Enable Register (SIU_DIRER)
Section 16.6.8, DMA/Interrupt Request Select Register (SIU_DIRSR)

16.7.4 GPIO operation

input data register (SIU_GPDIx_x) and an output data register (SIU_GPDOx_x).

16.7.5 Internal multiplexing

that are used in the serial and parallel chaining of DSPI blocks.

external trigger is individually specified in the ETISR, SIU_ISEL3 and SIU_ISEL9 registers. Figure 363. eQADC trigger input multiplexing example channel can be used by the alternate function on that pin. similar to SIU_ISEL3, shown in the above figure. are multiplexed in the same manner. Only IRQ[0] and [1] have an eMIOS channel as input. o. The EIISR is sometimes referred to as ISEL1.

in the same bit location of the deserialized information. See Section 16.6.19, External IRQ Input Select Register (SIU_EIISR), for more information. Figure 364. SIU external interrupt input multiplexing example individually specified in the DSPI Input Select Register (DISR). the IMUX Select Register 8 (SIU_ISEL8). be modified if these signals are to be used as external inputs or outputs.

17 Frequency-modulated phase locked loop (FMPLL)

17.1 Information specific to this device

specifically referenced in the remainder of this chapter.

17.1.1 Device-specific features

On-chip oscillator for external crystal: Range (4–40 MHz)
Internal RC oscillator (RCOSC): 16 MHz
Phase-locked loop (PLL): VCO Range (256–512 MHz)
PLLREF top level pin to control PLL reference
Clock Quality monitor
System Clock Divider (SYSDIV) used to further reduce the system clock frequency
Register to control system clock source and programming of PLL parameter
Clock gating for individual modules controlled by either SIU_HLT or module’s MDIS register bit (Refer to Table 14 (MDIS support) 5, Operating Modes and Clocking, to see which modules implement the MDIS bit.)

17.1.2 Device-specific parameters

Table 339 shows the reset values for several register fields on this device.

17.2 Introduction

This chapter describes the features and functions of the FMPLL module.

17.2.1 Overview

speed system clocks from a crystal oscillator or from an external clock generator. Furthermore, the FMPLL supports programmable frequency modulation of the system clock. Table 339. Register field reset values

17.2.2 Features

Reference clock predivider for finer frequency synthesis resolution
Reduced frequency divider for reducing the FMPLL output clock frequency without forcing the FMPLL to relock
Input clock frequency range from 4 MHz to 20 or 40 MHz(p) before the predivider, and from 4 MHz to 16 MHz after the predivider
Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz
VCO free-running frequency range from 25 MHz to 125 MHz
4 bypass modes: crystal or external reference with PLL on or off
2 normal modes: crystal or external reference
Programmable frequency modulation – Triangle wave modulation – Register programmable modulation frequency and depth
Lock detect circuitry reports when the FMPLL has achieved frequency lock and continuously monitors lock status to report loss of lock conditions – User-selectable ability to generate an interrupt request upon loss of lock – User-selectable ability to generate a system reset upon loss of lock
Clock quality monitor (CQM) module provides loss-of-clock detection for the FMPLL reference and output clocks – User-selectable ability to generate an interrupt request upon loss of clock – User-selectable ability to generate a system reset upon loss of clock – Backup clock (reference clock or FMPLL free-running) can be applied to the system in case of loss of clock

17.2.3 Modes of operation

available modes are specified in Table 340. p. See Section 17.1, Information specific to this device , for information on crystal frequencies supported. Table 340. Clock mode selection

whole period while system reset is asserted. support circuitry, and short signal route from the MCU to the crystal. FMPLL_ESYNCR1[CLKCFG] as shown in Table 340. frequency modulation is not available. FMPLL_ESYNCR1[PLLCFG] as shown in Table 340. route from the MCU to the crystal.

CLKCFG[1] is not writable to zero while CLKCFG[0] = 1.
The reset state of this bit is determined by the logical state applied to the PLLREF pin.

Table 340. Clock mode selection (continued)

programmed by writing to the FMPLL registers. range is the same and frequency modulation is available.

17.3 External signal description

Table 341 lists external signals used by the FMPLL during normal operation.

17.3.1 Detailed signal descriptions

Table 342 describes the external signals used by the FMPLL. Table 341. Signal properties

This signal is internally bonded to VSS.

Table 342. FMPLL detailed signal descriptions PLL reference—Determines the reset state of the CLKCFG[2] bit in FMPLL_ESYNCR1. Asserted—Indicates that the reference clock comes from the crystal oscillator. then kept stable for the whole reset duration. XTAL O Crystal oscillator—Output for an external crystal oscillator. VDDPLL / VSSPLL — PLL power supply—These are the 1.2V supply and ground for the FMPLL.

17.4 Memory map and register definition

17.4.1 Memory map

17.4.2 Register descriptions

Legacy model—The FMPLL is controlled by the Synthesizer Control Register (SYNCR). In this model, the FMPLL operating mode changes automatically to normal mode when the register is written in the first time. There is no way to switch back to bypass mode once the operating mode has switched to normal.
Enhanced model—The PLL is controlled by the Enhanced Synthesizer Control Registers 1–2 (ESYNCR1/ESYNCR2). In this model, it is possible to change the FMPLL operating mode back and forth between bypass and normal modes by programming FMPLL_ESYNCR1[CLKCFG]. The reset value of FMPLL_ESYNCR1[EMODE] is determined by the SoC integration. This bit is write once. After it is set to ‘1’, further write attempts to this bit will have no effect. Synthesizer Control Register (SYNCR) This register is provided for backwards compatibility with previous devices. New applications should use ESYNCR1/ESYNCR2 instead of SYNCR.

Table 343. FMPLL memory map

Figure 366. Synthesizer Control Register (SYNCR)

Reset value is determined by the SoC integration.

Table 344. SYNCR field descriptions 0 Reserved, should be cleared.

000 Divide by 1

001 Divide by 2

010 Divide by 3

011 Divide by 4

100 Divide by 5

101 Divide by 6

110 Divide by 7

111 Clock inhibit

MFD bits establishes the multiplication factor applied to the reference frequency.

00100 Divide by 8

00101 Divide by 9

00110 Divide by 10

10011 Divide by 23

10100 Divide by 24

10101 Invalid

9 Reserved, should be cleared.

establishes the division factor applied to the FMPLL frequency.

010 Divide by 4

011 Invalid

LOCEN bit. Furthermore, the LOCEN bit has no effect on the loss-of-lock detection circuitry.

0 Loss of clock disabled

1 Loss of clock enabled

The LOLRE bit determines whether system reset is asserted or not upon a loss-of-lock indication. value of the LOLRE bit. See Section 17.5.3, Lock detection. 0 Ignore loss-of-lock. Reset not asserted. 1 Assert reset on loss-of-lock when operating in normal mode. not monitored at all. See Section , Loss-of-clock reset. 0 Ignore loss-of-clock. Reset not asserted. 1 Assert reset on loss-of-clock. 16 Reserved, should be cleared. Section 17.5.3, Lock detection. 0 Ignore loss-of-lock. Interrupt not requested. 1 Enable interrupt request upon loss-of-lock. Table 344. SYNCR field descriptions (continued)

0 Ignore loss-of-clock. Interrupt not requested. 1 Enable interrupt request upon loss-of-clock. 19–31 Reserved, should be cleared. Figure 367. Synthesizer Status Register (SYNSR)

Reset value is determined by the state of the PLLREF pin.

Table 345. SYNSR field descriptions 0–21 Reserved, should be cleared. if it was asserted while the FMPLL was in normal mode. See Section 17.5.3, Lock detection. 0 No loss of lock detected. Interrupt service not requested. 1 Loss of lock detected. Interrupt service requested.

clock on the reference clock causes reset). See Section 17.5.4, Loss-of-clock detection. 0 No loss-of-clock detected. Clocks are operating normally. 1 Loss-of-clock detected. Clocks are not operating normally.

0 Bypass mode

1 Normal mode

MODE bit reflects the value of the CLKCFG[1] bit of the FMPLL_ESYNCR1.

0 Legacy mode: bypass or dual controller; enhanced mode: PLL off

1 Legacy mode: normal; enhanced mode: PLL on

bit reflects the value of the CLKCFG[2] bit of the FMPLL_ESYNCR1.

0 External clock reference

1 Crystal oscillator reference

the FMPLL is locked, going from normal to bypass mode does not clear the LOCKS bit. 0 FMPLL has lost lock since last system reset or last write to PLL registers which affect the lock status. Table 345. SYNSR field descriptions (continued)

Figure 368. Enhanced Synthesizer Control Register 1 (ESYNCR1) operating modes and conditions can this flag be asserted. 0 No loss of clock detected. Interrupt service not requested. 1 Loss of clock detected. Interrupt service requested. 30–31 Reserved, should be cleared.

Reset value determined by the PLLREF pin.

Table 346. ESYNCR1 field descriptions written to ‘1’, further write attempts to this bit will have no effect. 0 Legacy mode. FMPLL controlled by SYNCR. 1 Enhanced mode. FMPLL controlled by ESYNCR1/ESYNCR2. 1 is ‘1’. The reset state of bit 3 is determined by the state of the PLLREF pin.

000 Bypass mode with external reference and PLL off

001 Bypass mode with crystal reference and PLL off

010 Bypass mode with external reference and PLL running

011 Bypass mode with crystal reference and PLL running

101 Reserved

110 Normal mode with external reference

111 Normal mode with crystal reference

4–11 Reserved, should be cleared.

0000 Divide by 1

0001 Divide by 2

0010 Divide by 3

0011 Divide by 4

0100 Divide by 5

0101 Divide by 6

0110 Divide by 7

0111 Divide by 8

1000 Divide by 9

1001 Divide by 10

1010 Divide by 11

1011 Divide by 12

1100 Divide by 13

1101 Divide by 14

1110 Divide by 15

1111 Clock inhibit

16–24 Reserved, should be cleared. cause the FMPLL to produce unpredictable clock output. Table 346. ESYNCR1 field descriptions (continued) Figure 369. Enhanced Synthesizer Control Register 2 (ESYNCR2) Table 347. ESYNCR2 field descriptions 0–7 Reserved, should be cleared. LOCEN bit. Furthermore, the LOCEN bit has no effect on the loss-of-lock detection circuitry.

frequency modulation is disabled and the FMPLL_SYNFMMR is reset. LOLRE bit. See Section 17.5.3, Lock detection. 0 Ignore loss-of-lock. Reset not asserted. 1 Assert reset on loss-of-lock when operating in normal mode. all. See Section , Loss-of-clock reset. 0 Ignore loss-of-clock. Reset not asserted. 1 Assert reset on loss-of-clock. Section 17.5.3, Lock detection. 0 Ignore loss-of-lock. Interrupt not requested. 1 Enable interrupt request upon loss-of-lock. 0 Ignore loss-of-clock. Interrupt not requested. 1 Enable interrupt request upon loss-of-clock. 13–29 Reserved, should be cleared. establishes the division factor applied to the FMPLL frequency. Table 347. ESYNCR2 field descriptions (continued)

Figure 370. Synthesizer FM Modulation Register (SYNFMMR) Table 348. SYNFMMR field descriptions the BSY flag is set will have no effect. 0 Write to the FMPLL_SYNFMMR is allowed.

1 The FMPLL is still busy processing the previous change on the FMPLL_SYNFMMR; write access

to the register is not possible. This bit enables the frequency modulation.

0 Frequency modulation disabled

1 Frequency modulation enabled

below the nominal frequency. 0 Modulation centered around nominal frequency. 1 Modulation spread below nominal frequency.

Note: The product of INCSTEP and MODPERIOD cannot be larger than (2 15 − 1).

17.5 Functional description

This section explains the FMPLL operation and configuration.

17.5.1 Input clock frequency

operating mode. The operating ranges for each mode are given in Table 349.

17.5.2 Clock configuration

16 Reserved, should be cleared. Table 348. SYNFMMR field descriptions (continued) Table 349. Input clock frequency at the predivider input

See Section 17.1, Information specific to this device , for information on crystal frequencies supported.
f sys is the system frequency of the MCU. The predivider ratio has to be chosen such that the input to the PLL itself (after the

predivider) does not exceed 16 MHz.

Frequency-modulated phase locked loop (FMPLL) RM0029 604/1740 Doc ID 15177 Rev 8 Equation 4 In enhanced mode, the relationship between input and output frequency is determined by the EPREDIV, EMFD and ERFD values programmed in the FMPLL_ESYNCR1 and FMPLL_ESYNCR2, according to the following equation: Equation 5 When programming the FMPLL, be sure not to violate the maximum system clock frequency or max/min VCO frequency specification. In enhanced mode, the VCO frequency is calculated according to the following equation: Equation 6 Note: Maximum system clock frequency is 150 MHz and max/min VCO frequency is 256 MHz to 512 MHz. Furthermore, the PREDIV or EPREDIV values must not be set to any value that causes the input frequency to the phase detector to go below 4 MHz. The LOCK flag is immediately negated after any of the following events: 1. In legacy mode, the PREDIV or MFD fields of the FMPLL_SYNCR are changed 2. In enhanced mode, the EMODE, EPREDIV, EMFD of CLKCFG[1:2] fields of the FMPLL_ESYNCR1 are changed(q) Upon any of these events an internal timer is initialized to count 64 cycles of the PLL input clock. During this period, the LOCK flag is held negated. After the timer expires, the LOCK flag reflects the value coming from the PLL lock detection circuitry. To prevent an immediate reset, the LOLRE bit must be cleared before doing any of the above operations. Changing RFD or ERFD does not affect the FMPLL, hence no relock delay is incurred. Resulting changes in clock frequency are synchronized to the next falling edge of the current system clock. However, RFD or ERFD should only be changed when the LOCK bit is set, to avoid exceeding the allowable system operating frequency. q. Note that changing only the CLKCFG[0] bit to move from bypass to normal or vice-versa, and keeping the values of the other FMPLL_ESYNCR1 fields unchanged, will not cause the PLL to lose lock or the lock flag to be cleared. fVCO 4f sys 2RFD××= fsys fref EMFD EPREDIV 1+() 2 ERFD 1+()× fVCO fref EMFD

RM0029 Frequency-modulated phase locked loop (FMPLL) Doc ID 15177 Rev 8 605/1740 Coming out of reset, the FMPLL will be enabled (on), but running in bypass mode. The recommended procedure to program the FMPLL and engage normal mode is: 1. Assert the EMODE bit and program the EPREDIV and EMFD fields of FMPLL_ESYNCR1 and the RFD field of FMPLL_ESYNCR2. 2. Poll FMPLL_SYNSR[LOCK] until it asserts. 3. If required, program the FMPLL_SYNFMMR with desired FM parameters, poll the BSY bit until it negates, then enable FM by asserting the MODEN bit. 4. Engage normal mode by writing to FMPLL_ESYNCR1[CLKCFG].

17.5.3 Lock detection

A pair of counters monitor the reference and feedback clocks to determine when the system has acquired frequency lock. Once the FMPLL has locked, the counters continue to monitor the reference and feedback clocks and will report if/when the FMPLL has lost lock. The FMPLL registers provide the flexibility to select whether to generate an interrupt, assert system reset or do nothing in the event that the FMPLL loses lock. Loss-of-lock reset and interrupt are only generated when the FMPLL is operating in normal mode. The LOCF bit is not asserted by a loss-of-lock condition detected during bypass, although going to bypass mode from normal mode does not automatically clear the flag if it was asserted while the FMPLL was in normal mode.

17.5.4 Loss-of-clock detection

The FMPLL reference and output clocks may be continuously monitored by a module called Clock Quality Monitor (CQM), shown in Figure 371. The intent of the CQM is to assure that the system bus clock is created from good clock sources. Whether the clocks are monitored or not is determined by the clock operating mode and control bits in the FMPLL registers, as shown in Table 350. In bypass mode with crystal reference, the reference clock is always monitored, regardless of the state of the LOCEN bit. In bypass mode with external reference, the reference clock is not monitored, regardless of the state of the LOCEN bit. This is done so that the whole device frequency range can be sourced from the external clock generator when using external reference mode. The FMPLL output may only monitored in normal mode, depending on the state of the LOCEN bit. The clock quality monitor uses an internal 4 MHz RC oscillator as a reference time base to measure the frequency of the crystal oscillator and the FMPLL output. The frequency of these clocks are expected to be within the following frequency ranges:

Reference clock must be within the crystal frequency range(r)
PLL output must be above 1.5 MHz (minimum VCO free-running frequency divided by the maximum ERFD) In the event either of the clocks fall outside the expected window, a loss of clock condition is reported. The FMPLL can be programmed to switch the system clock to a backup clock in the event of such a failure. Additionally, the user may select to have the system enter reset, assert an interrupt request, or do nothing if/when the FMPLL reports this condition. r. See Section 17.1, Information specific to this device , for information on crystal frequencies supported.

Figure 371. Clock quality monitor FMPLL failure, the system clock is connected back to the FMPLL output.

4 MHz

Table 350. Loss-of-clock monitoring

LOCEN is the loss-of-clock enable bit in either FMPLL_SYNCR or FMPLL_ESYNCR2, depending on

with external reference, no backup clock selection occurs if the reference fails. on the clock operating mode and control bits in the FMPLL registers, as shown in Table 351. another means must be used externally to determine that a loss-of-clock condition occurred. output because the FMPLL clock is not monitored in bypass mode. reference fails in bypass with external reference, no reset or interrupts are generated. Table 351. Loss-of-clock reset

11 N o Y e s

11 Y e s Y e s

LOCEN is the loss-of-clock enable bit in either FMPLL_SYNCR or FMPLL_ESYNCR2, depending on
LOCRE is the loss-of-clock reset enable bit in either FMPLL_SYNCR or FMPLL_ESYNCR2, depending on

17.5.5 Frequency modulation

Figure 372. Triangular frequency modulation Table 352. Loss-of-clock interrupt request

LOCEN is the loss-of-clock enable bit in ei ther FMPLL_SYNCR or FMPLL_ESYNCR2, depending on the
LOCIRQ is the loss-of-clock interrupt enable bi t in either FMPLL_SYNCR or FMPLL_ESYNCR2, depending on the

RM0029 Frequency-modulated phase locked loop (FMPLL) Doc ID 15177 Rev 8 609/1740 The following equations define how to calculate MODPERIOD and INCSTEP based on the frequency of the feedback divider (ffbk), the modulation frequency (fmod) and the modulation depth percentage (MD): Equation 7 Equation 8 MODPERIOD and INCSTEP are subject to the following restriction: Equation 9 Because of the above rounding operations, the effective modulation depth applied to the FMPLL is given by the following formula: Equation 10 As an example, suppose the following configuration:

Input frequency: 4 MHz
Load divider (EMFD): 64
Input divider: 1
VCO frequency: 4 MHz × 64 = 256 MHz
PLL output frequency: 256 MHz / ERFD
Center spread (MODSEL = 0)
Modulation frequency: 24 kHz
Modulation depth: +/− 2.0 % (4% peak-to-peak)
MODPERIOD = Round [(4 × 106)/(4 × 24 × 103)] = Round [41.66] = 42
MODPERIOD × INCSTEP = 42 × 200 = 8400 (which is less than 215) In this example, the modulation depth error is 0.00278%. The FM parameters can only be changed, and FM can only be enabled, when the PLL is locked. Writing to the FMPLL_SYNFMMR while the PLL is unlocked has no effect. MODPERIOD round ffbk INCSTEP round 215 1–() MD× EMFD× MODPERIOD INCSTEP×() 215< INCSTEP round MODPERIOD INCSTEP× 100 5×× 215 1–() EMFD×

Frequency-modulated phase locked loop (FMPLL) RM0029 610/1740 Doc ID 15177 Rev 8 Furthermore, when the PLL loses lock, the FM parameters are reset and the modulation is disabled until the PLL relocks and the FMPLL_SYNFMMR is programmed again. After programming the FM parameters, it takes some time until these parameters get propagated to the PLL analog circuitry. During this time, the BSY bit gets asserted. The modulation must only be enabled when the FM parameters have already propagated to the analog circuitry. Therefore, the sequence for programming FM is: 1. Poll FMPLL_SYNSR[LOCK] until it asserts. 2. Program the MODSEL, MODPERIOD and INCSTEP fields of the FMPLL_SYNFMMR. 3. Poll FMPLL_SYNFMMR[BSY] until it negates. 4. Assert FMPLL_SYNFMMR[MODEN].

18 Error Correction St atus Module (ECSM)

18.1 Overview

the IPS space and supports a number of miscellaneous control functions for the platform.

18.2 Features

Program-visible information on the platform configuration and revision
Optional address map for device’s crossbar switch (XBAR)
Miscellaneous Reset Status Register (ECSM_MRSR)
Registers for capturing information on memory errors if error-correcting codes (ECC) are implemented

18.3 Module memory map

The Error Correction Status Module does not include any logic that provides access control. Table 353 is a 32-bit view of the ECSM’s memory map. Table 353. ECSM 32-bit memory map

18.4 Register descriptions

writes to read-only registers are ignored and do not terminate with an error.

18.4.1 Miscellaneous Reset Status Register (ECSM_MRSR)

Table 353. ECSM 32-bit memory map (continued)

18.4.2 Miscellaneous Wakeup Control Register (ECSM_MWCR)

that the exact details are likely to be system-specific.

The processor core loads the appropriate data value into the ECSM_MWCR, setting

the ENBWCR bit and the desired interrupt priority level.

At the appropriate time, the processor ceases execution. The exact mechanism varies
After entering the low-power mode, the interrupt controller enables a special

Figure 373. Miscellaneous Reset Status Register (ECSM_MRSR) Table 354. ECSM_MRSR field description 1 = Last recorded event was a reset caused by a device input reset.

Once the appropriately-high interrupt request level arrives, the interrupt controller
The external logic senses the assertion of the “exit” signal, and re-enables the
With the processor core clocks enabled, the core handles the pending interrupt

18.4.3 Miscellaneous User-Defined Control Register (ECSM_MUDCR)

Figure 374. Miscellaneous Wakeup Control Register (ECSM_MWCR) Table 355. ECSM_MWCR field description than the PRILVL value is required to exit the mode. controller module for details.

18.4.4 ECC registers

ECC Configuration Register (ECSM_ECR)
ECC Status Register (ECSM_ESR)
ECC Error Generation Register (ECSM_EEGR)
Flash ECC Address Register (ECSM_FEAR)
Flash ECC Master Number Register (ECSM_FEMR)
Flash ECC Attributes Register (ECSM_FEAT)
Flash ECC Data Register (ECSM_FEDR)
RAM ECC Address Register (ECSM_REAR)
RAM ECC Syndrome Register (ECSM_PRESR)
RAM ECC Master Number Register (ECSM_REMR)
RAM ECC Attributes Register (ECSM_REAT)
RAM ECC Data Register (ECSM_REDR) The details on the ECC registers are provided in the subsequent sections.

Figure 375. Miscellaneous User-Defined Control Register (ECSM_MUDCR) Table 356. ECSM_MUDCR field description

0 Reserved

and the RAM bank chip selects. also provides improved correction capabilities compared to the 64-bit ECC implementation. Table 357. AHB Response and ECC Reporting for Even and Odd ECC

subsequent failure analysis. Figure 376. ECC Configuration Register (ECSM_ECR) Table 358. ECSM_ECR field description 0 = Reporting of single-bit platform RAM corrections is disabled. 1 = Reporting of single-bit platform RAM corrections is enabled. ECSM_REAR, ECSM_PRESR, ECSM_REMR, ECSM_REAT and ECSM_REDR registers. 0 = Reporting of single-bit platform flash corrections is disabled. 1 = Reporting of single-bit platform flash corrections is enabled. ECSM_FEAR, ECSM_FEMR, ECSM_FEAT and ECSM_FEDR registers. 0 = Reporting of non-correctable platform RAM errors is disabled. 1 = Reporting of non-correctable platform RAM errors is enabled. 0 = Reporting of non-correctable platform flash errors is disabled. 1 = Reporting of non-correctable platform flash errors is enabled. captured in the ECSM_FEAR, ECSM_FEMR, ECSM_FEAT and ECSM_FEDR registers.

Error Correction Status Module (ECSM) RM0029 618/1740 Doc ID 15177 Rev 8 ECC Status Register (ECSM_ESR) The ECC Status Register is an 8-bit control register for signaling which types of properly- enabled ECC events have been detected. The ECSM_ESR signals the last, properly- enabled memory event to be detected. An ECC interrupt request is asserted if any flag bit is asserted and its corresponding enable bit is asserted. ECC interrupt generation is separated into single-bit error detection/correction, uncorrectable error detection and the combination of the two as defined by the following boolean equations: ECSM_ECC1BIT_IRQ = ECSM_ECR[ER1BR] & ECSM_ESR[R1BC] // platform ram, 1-bit correction | ECSM_ECR[EF1BR] & ECSM_ESR[F1BC] // platform flash, 1-bit correction ECSM_ECCRNCR_IRQ = ECSM_ECR[ERNCR] & ECSM_ESR[RNCE] // platform ram, noncorrectable error ECSM_ECCFNCR_IRQ = ECSM_ECR[EFNCR] & ECSM_ESR[FNCE] // platform flash, noncorrectable error ECSM_ECC2BIT_IRQ = ECSM_ECCRNCR_IRQ // platform ram, noncorrectable error | ECSM_ECCFNCR_IRQ // platform flash, noncorrectable error ECSM_ECC_IRQ = ECSM_ECC1BIT_IRQ // 1-bit correction | ECSM_ECC2BIT_IRQ // noncorrectable error where the combination of a properly-enabled category in the ECSM_ECR and the detection of the corresponding condition in the ECSM_ESR produces the interrupt request. The ECSM allows a maximum of one bit of the ECSM_ESR to be asserted at any given time. This preserves the association between the ECSM_ESR and the corresponding address and attribute registers, which are loaded on each occurrence of a properly-enabled ECC event. If there is a pending ECC interrupt and another properly-enabled ECC event occurs, the ECSM hardware automatically handles the ECSM_ESR reporting, clearing the previous data and loading the new state and thus guaranteeing that only a single flag is asserted. To maintain the coherent software view of the reported event, the following sequence in the ECSM error interrupt service routine is suggested: 1. Read the ECSM_ESR and save it. 2. Read and save all the address and attribute reporting registers. 3. Re-read the ECSM_ESR and verify the current contents matches the original contents. If the two values are different, go back to step 1 and repeat. 4. When the values are identical, write a ‘1’ to the asserted ESR flag to negate the interrupt request.

Figure 377. ECC Status Register (ECSM_ESR) Table 359. ECSM_ESR field description 0 = No reportable single-bit platform RAM correction has been detected. 1 = A reportable single-bit platform RAM correction has been detected. ECSM_REDR registers. To clear this interrupt flag, write a ‘1’ to this bit. Writing a ‘0’ has no effect. 0 = No reportable single-bit platform flash correction has been detected. 1 = A reportable single-bit platform flash correction has been detected. clear this interrupt flag, write a ‘1’ to this bit. Writing a ‘0’ has no effect. 0 = No reportable non-correctable platform RAM error has been detected. 1 = A reportable non-correctable platform RAM error has been detected. write a ‘1’ to this bit. Writing a ‘0’ has no effect. 0 = No reportable non-correctable platform flash error has been detected. 1 = A reportable non-correctable platform flash error has been detected. bit. Writing a ‘0’ has no effect.

event with the R1BC as highest priority, then F1BC, then RNCE, and finally FNCE. of single- and double-bit data inversions in the memories with ECC, most notably the RAM.

It provides a software-controlled mechanism for “injecting” errors into the memories during data writes to verify the integrity of the ECC logic.
It provides a mechanism to allow testing of the software service routines associated with memory error logging. It should be noted that while the ECSM_EEGR is associated with the RAM, similar capabilities exist for the flash, that is, the ability to program the non-volatile memory with single- or double-bit errors is supported for the same two reasons previously identified. For both types of memories (RAM and flash), the intent is to generate errors during data write cycles, such that subsequent reads of the corrupted address locations generate ECC events, either single-bit corrections or double-bit non-correctable errors that are terminated with an error response.

Figure 378. ECC Error Generation Register (ECSM_EEGR)

0 ERRBIT[6:0]

This field is writable only in test mode in cut 1.0 devices.

Table 360. ECSM_EEGR field description 0 = All Platform masters are able to generate RAM ECC errors via the ECSM_EEGR. system, ensures that only one core can issue a RAM data inversion. master module. It is the responsibility of the software to ensure the proper setting of this bit.

0 = No RAM continuous 1-bit data inversions are generated. 1 = 1-bit data inversions in the RAM are continuously generated. bit position specified in ERRBIT[6:0], continuously on every write operation. defined by ERRBIT is inverted to introduce a 1-bit ECC event in the RAM. cleared before being set again to correctly re-enable the error generation logic. 0 = No RAM single 1-bit data inversion is generated. 1 = One 1-bit data inversion in the RAM is generated. the bit position specified in ERRBIT[6:0], on the first write operation after this bit is set. defined by ERRBIT is inverted to introduce a 1-bit ECC event in the RAM. being set again to properly re-enable the error generation logic. 0 = No RAM continuous 2-bit data inversions are generated. 1 = 2-bit data inversions in the RAM are continuously generated. must be cleared before being set again to properly re-enable the error generation logic. Table 360. ECSM_EEGR field description (continued)

0 = No RAM single 2-bit data inversions are generated. 1 = One 2-bit data inversion in the RAM is generated. again to properly re-enable the error generation logic.

of the ECC code are inverted. consider a 64-bit RAM implementation and ECC organized on a 32-bit boundary. bits are used by the platform RAM controller.

This field is writable only in test mode in cut 1.0 devices.

Status Register to be asserted. Figure 379. Flash ECC Address Register (ECSM_FEAR) Table 361. ECSM_FEAR field description

Status Register to be asserted. The data captured on a multi-bit non-correctable ECC error is undefined. Table 363. ECSM_FEAT field description

Figure 382. Flash ECC Data Register (ECSM_FEDRH, ECSM_FEDRL) Table 364. ECSM_FEDR field description enabled flash ECC event. The register contains the data value taken directly from the data bus.

readable when the ECSM_PRESR is read for the no error case. Table 366. ECSM_PRESR field description 7-bit ECC) code word of each bank for single-bit errors. Syndrome values for non-correctable errors are not defined. syndrome with the data bit in error. Table 367. RAM syndrome mapping for single-bit correctable errors

Table 367. RAM syndrome mapping for single-bit correctable errors (continued)

in the ECC Status Register to be asserted.

in the ECC Status Register to be asserted. The data captured on a multi-bit non-correctable ECC error is undefined. Table 369. ECSM_REAT field description

Figure 387. RAM ECC Data Register (ECSM_REDR) Table 370. ECSM_REDR field description

RM0029 System Timer Module (STM) Doc ID 15177 Rev 8 635/1740

19 System Timer Module (STM)

19.1 Information Specific to This Device

This section presents device-specific parameterization and customization information not specifically referenced in the remainder of this chapter.

19.1.1 Device-Specific Features

One 32-bit up counter with 8-bit prescaler
Four 32-bit compare channels
Independent interrupt source for each channel
Counter can be stopped in debug mode

19.2 Introduction

19.2.1 Overview

19.2.2 Modes of operation

The STM supports two device modes of operation: normal and debug. When the STM is enabled in normal mode, its counter runs continuously. In debug mode, operation of the counter is controlled by the FRZ bit in the STM_CR register. If the FRZ bit is set, the counter is stopped in debug mode, otherwise it continues to run.

19.3 External signal description

The STM does not have any external interface signals.

19.4 Memory map and register definition

The STM programming model has fourteen 32-bit registers. The STM registers can only be accessed using 32-bit (word) accesses. Attempted references using a different size or to a reserved address generates a bus error termination.

19.4.1 Memory map

The STM memory map is shown in Table 371.

19.4.2 Register descriptions

The following sections detail the individual registers within the STM programming model. Table 371. STM memory map

The STM Count Register (STM_CNT) holds the timer count value. Figure 388. STM Control Register (STM_CR) Table 372. STM_CR field description 0 = STM counter continues to run in debug mode. 1 = STM counter is stopped in debug mode.

System Timer Module (STM) RM0029 640/1740 Doc ID 15177 Rev 8

19.5 Functional Description

The System Timer Module (STM) is a 32-bit timer designed to support commonly required system and application software timing functions. The STM includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. The STM has one 32-bit up counter (STM_CNT) that is used as the time base for all channels. When enabled, the counter increments at the system clock frequency divided by a prescale value. The STM_CR[CPS] field sets the divider to any value in the range from 1 to 256. The counter is enabled with the STM_CR[TEN] bit. When enabled in normal mode the counter continuously increments. When enabled in debug mode the counter operation is controlled by the STM_CR[FRZ] bit. When the STM_CR[FRZ] bit is set, the counter is stopped in debug mode, otherwise it continues to run in debug mode. The counter rolls over at 0xFFFF_FFFF to 0x0000_0000 with no restrictions at this boundary. The STM has four identical compare channels. Each channel includes a channel control register (STM_CCRn), a channel interrupt register (STM_CIRn) and a channel compare register (STM_CMPn). The channel is enabled by setting the STM_CCRn[CEN] bit. When enabled, the channel will set the STM_CIR[CIF] bit and generate an interrupt request when the channel compare register matches the timer counter. The interrupt request is cleared by writing a ‘1’ to the STM_CIRn[CIF] bit. A write of ‘0’ to the STM_CIRn[CIF] bit has no effect.

RM0029 Software Watchdog Timer (SWT) Doc ID 15177 Rev 8 641/1740

20 Software Watchdog Timer (SWT)

20.1 Introduction

20.1.1 Overview

The Software Watchdog Timer (SWT) is a peripheral module that can prevent system lockup in situations such as software getting trapped in a loop or if a bus transaction fails to terminate. When enabled, the SWT requires periodic execution of a watchdog servicing operation. The servicing operation resets the timer to a specified time-out period. If this servicing action does not occur before the timer expires the SWT generates an interrupt or hardware reset. The SWT can be configured to generate a reset or interrupt on an initial time-out, a reset is always generated on a second consecutive time-out.

20.1.2 Features

The SWT has the following features:

32-bit time-out register to set the time-out period
Programmable selection of system or oscillator clock for timer operation
Programmable selection of window mode or regular servicing
Programmable selection of reset or interrupt on an initial time-out
Programmable selection of fixed or keyed servicing
Master access protection
Hard and soft configuration lock bits

20.1.3 Modes of operation

The SWT supports three device modes of operation: normal, debug and stop. When the SWT is enabled in normal mode, its counter runs continuously. In debug mode, operation of the counter is controlled by the FRZ bit in the SWT_MCR. If the FRZ bit is set, the counter is stopped in debug mode, otherwise it continues to run. In stop mode, operation of the counter is controlled by the STP bit in the SWT_MCR. If the STP bit is set, the counter is stopped in stop mode; otherwise, it continues to run.

20.2 External signal description

The SWT module does not have any external interface signals.

20.3 Memory map and register definition

The SWT programming model has seven 32-bit registers. The programming model can only be accessed using 32-bit (word) accesses. References using a different size are invalid. Other types of invalid accesses include: writes to read-only registers, incorrect values written to the service register when enabled, accesses to reserved addresses and accesses by masters without permission. If the RIA bit in the SWT_MCR is set then the SWT generates a system reset on an invalid access otherwise a bus error is generated. If either

SWT_SK registers are read-only.

20.3.1 Memory map

and SWT_WN are device specific. These values are determined by SWT inputs.

20.3.2 Register descriptions

The following sections detail the individual registers within the SWT programming model. SWT_MCR[HLK] or SWT_MCR[SLK] bits are set. Table 377. SWT memory map

Figure 393. SWT Module Control Register (SWT_MCR) Table 378. SWT_MCR field description The platform bus master assignments are device specific. This bit is only cleared at reset. This bit is cleared by writing the unlock sequence to the service register.

The SWT_IR contains the time-out interrupt flag. Table 378. SWT_MCR field description (continued) Figure 394. SWT Interrupt Register (SWT_IR) Table 379. SWT_IR field description The flag and interrupt are cleared by writing a ‘1’ to this bit. Writing a ‘0’ has no effect.

Figure 399. SWT Service Register (SWT_SK)

20.4 Functional description

(SWT_CO) and a service key register (SWT_SK). configuration of the module. The watchdog is enabled by setting the SWT_MCR[WEN] bit. oscillator) is used to drive the down counter. The configuration of the SWT can be locked through use of either a soft lock or a hard lock. Table 384. SWT_SK field description set, the next key value to be written to the SWT_SR is (17*SK+3) mod 216.

Software Watchdog Timer (SWT) RM0029 648/1740 Doc ID 15177 Rev 8 two writes and the service sequence logic ignores unlock sequence writes. If the SWT_MCR[KEY] bit is zero, the fixed sequence 0xA602, 0xB480 is written to the SWT_SR[WSC] field to service the watchdog. If the SWT_MCR[KEY] bit is set, then two pseudorandom keys are written to the SWT_SR[WSC] field to service the watchdog. The key values are determined by the pseudorandom key generator defined in Equation 11. This algorithm will generate a sequence of 2 16 different key values before repeating. The state of the key generator is held in the SWT_SK register. For example, if SWT_SK[SK] is 0x0100 then the service sequence keys are 0x1103, 0x2136. In this mode, each time a valid key is written to the SWT_SR register, the SWT_SK register is updated. So, after servicing the watchdog by writing 0x1103 and then 0x2136 to the SWT_SR[WSC] field, SWT_SK[SK] is 0x2136 and the next key sequence is 0x3499, 0x7E2C. Equation 11 Accesses to SWT registers occur with no peripheral bus wait states. (The peripheral bus bridge may add one or more system wait states.) However, due to synchronization logic in the SWT design, recognition of the service sequence or configuration changes may require up to three system plus seven counter clock cycles. If window mode is enabled (SWT_MCR[WND] bit is set), the service sequence must be performed in the last part of the time-out period defined by the window register. The window is open when the down counter is less than the value in the SWT_WN register. Outside of this window, service sequence writes are invalid accesses and generate a bus error or reset depending on the value of the SWT_MCR[RIA] bit. For example, if the SWT_TO register is set to 5000 and SWT_WN register is set to 1000 then the service sequence must be performed in the last 20% of the time-out period. There is a short lag in the time it takes for the window to open due to synchronization logic in the watchdog design. This delay could be up to three system plus four counter clock cycles. The interrupt then reset bit (SWT_MCR[ITR]) controls the action taken when a time-out occurs. If the SWT_MCR[ITR] bit is not set, a reset is generated immediately on a time-out. If the SWT_MCR[ITR] bit is set, an initial time-out causes the SWT to generate an interrupt and load the down counter with the time-out period. If the service sequence is not written before the second consecutive time-out, the SWT generates a system reset. The interrupt is indicated by the time-out interrupt flag (SWT_IR[TIF]). The interrupt request is cleared by writing a ‘1’ to the SWT_IR[TIF] bit. The SWT_CO register shows the value of the down counter when the watchdog is disabled. When the watchdog is enabled this register is cleared. The value shown in this register can lag behind the value in the internal counter for up to six system plus eight counter clock cycles. The SWT_CO can be used during a software self test of the SWT. For example, the SWT can be enabled and not serviced for a fixed period of time less than the time-out value. Then the SWT can be disabled (SWT_MCR[WEN] cleared) and the value of the SWT_CO read to determine if the internal down counter is working properly. SKn+1 = (17*SKn+3) mod 216

RM0029 Boot Assist Module (BAM) Doc ID 15177 Rev 8 649/1740

21 Boot Assist Module (BAM)

21.1 Overview

The Boot Assist Module (BAM) is a 4 KB block of read-only memory (ROM) containing the boot program code for this device. The BAM program supports four different boot modes:

Boot from internal Flash
Serial boot via SCI or CAN interface
Serial boot via SCI or CAN interface with baud rate detection
Boot from a memory connected to the External Bus Interface (EBI) The BAM program is executed by the core just after a device reset. Depending on the boot mode, the program initializes appropriate minimum device resources to start user code application.

21.2 Features

Initial core MMU setup with minimum address translation for all internal device resources
MMU configuration to boot user application, compiled as Power Architecture technology code or as VLE code
Passes control to user application code in the internal flash memory
Automatic switch to Serial Boot mode if internal flash is blank or invalid
Serial boot by loading user program via CAN bus or eSCI to the internal SRAM – User programmable 64-bit password protection – Optional automatic detection of the host SCI or CAN speed
Boot from an external memory device, connected to the EBI
Controls core Watchdog Timer or/and the Software Watchdog Timer (SWT)

21.3 Modes of operation

21.3.1 Normal mode

The BAM program is executed immediately following the negation of reset.

21.3.2 Debug mode

The BAM program is not executed when the device comes out of reset in OnCE debug mode. The user must provide the required device initialization using the development tool before accessing the device resources.

21.3.3 Internal boot mode

This mode of operation is intended for systems that boot from internal flash memory. The internal flash memory is used for all code and all boot configuration data.

21.3.4 Serial boot mode

21.3.5 Calibration bus boot mode

Calibration bus boot is not supported. External bus boot is supported instead.

21.4 Memory map

execution at its reset vector from address 0xFFFF_FFFC. instruction is a BLR. The link register is preloaded with the user application start address. Table 385 shows the BAM address map.

21.5 Functional description

21.5.1 BAM Program flow chart

The BAM program flow chart is shown in Figure 400. Table 385. BAM memory map

Figure 400. BAM program flow chart

21.5.2 BAM program operation

memory, to be executed from internal Flash. password in the internal Flash memory. Table 386. MMU configuration for internal flash boot

0 Peripheral Bridge B (1) and BAM 0xFFF0_0000 0xFFF0_0000 1 MB

1 Internal Flash 0x0000_0000 0x0000_0000 16 MB

2 EBI 0x2000_0000 0x0000_0000 16 MB

3 Internal SRAM 0x4000_0000 0x4000_0000 256 KB

4 Peripheral Bridge A (1) 0xC3F0_0000 0xC3F0_0000 1 MB

This device has only a single peripheral bridge, but to ma tch the memory map of other devices the peripherals are mapped

to appear as if they are on two different peripheral bridges. Table 387. Boot modes

01 Any value

password for serial boot mode. Figure 401. Censorship word

11 Invalid value

‘!’ = ‘NOT,’ as in!0x55AA, means all values except 0x55AA. Do not use 0x0000 or 0xFFFF for the value of the censorship

control or serial boot control words. Table 387. Boot modes (continued)

Figure 402. Serial boot flash password becomes corrupted for whatever reason.

21.5.3 Reset configuration half word (RCHW)

external flash device, the RCHW should reside in the very first 16-bit half word of the flash. Figure 403 shows the fields of the RCHW. Figure 403. Reset configuration half word

Table 388. RCHW field description These bit values are ignored when the halfword is read. Write to 0 for future compatibility. programmed to be 261600 system clocks. programmed to be 2.5*217 system clocks. Used in EBI boot mode only. Do not set the port to 32-bits if the device only has a 16-bit data bus.

0 User code executes as Power Architecture code

a valid boot identifier is 0x5A. Table 389. Watchdog timeouts

user application to switch to. Figure 404. Reset boot vector

21.5.4 Internal boot mode

possibility of booting to the serial boot mode. (RCHW). Possible RCHW locations are shown in Table 390. Table 390. Possible RCHW locations in the internal flash

Boot Assist Module (BAM) RM0029 658/1740 Doc ID 15177 Rev 8 1. After the RSTOUT pin has is negated, hold the device in system reset state using a debugger or other tool. 2. While the device is being held in system reset state shift the 64-bit password into the CENSOR_CTRL register (see Section , CENSOR_CTRL Register) via the JTAG port using the JTAG ENABLE_CENSOR_CTRL instruction. The JTAG serial password is compared against the serial boot flash password from the flash shadow block. 3. If there is a match the Nexus client TAP controller enters normal operation mode and the flag SIU_CCR[DISNEX] is negated, indicating Nexus is enabled. Upon negation of reset the debug / calibration tool is able to access the device via NEXUS port and JTAG. If the JTAG serial password does not match the serial boot flash password or the serial boot flash password is an illegal password then the debug / calibration tool is not able to access the device. After the debug port is enabled, the tool can access the censored device and can erase and reprogram the shadow flash block in order to uncensor the device. Note: If the shadow flash block is erased without reprogramming a new valid password before a reset it will contain an illegal password and the debug port will be inaccessible. 4. Subsequent resets will clear the JTAG censor password register and the Nexus client TAP controller will hold in reset again. Therefore, the tool must resend the JTAG serial password, as described above, in order to enable the Nexus client TAP controller again.

21.5.5 Serial boot mode

When the BAM program transitions to the Serial Boot mode, unused message buffers in CAN_A are used for the BAM program stack and variables and the SWT watchdog is reprogrammed with timeperiod greater than the default value. The MMU setup depends on the way BAM enters the serial boot mode. If EBI boot mode is taken, the MMU is set up for that mode (see Table 395). The serial boot mode can run in either of two modes of operation:

Standard serial boot mode using fixed baud rates derived from the crystal oscillator used
Baud Rate Detection serial boot mode, which allows communication with adaptable speed, based on measured input signal The Fixed Baud Rate mode or Baud Rate Detection mode are selected based on the state of the EVTO pin, recorded in the SIU_RSR[ABR] bit. If the bit is set, the Baud Rate Detection mode is selected if the bit is cleared, the Fixed Baud Rate is selected. SIU_RSR[ABR] bit reflects the inverted state of the EVTO pin, thus to select Baud Rate Detection mode, the EVTO pin needs to be driven low. When the Fixed Baud Rate mode is selected, the BAM program configures the SCI_A_RX pin to be the input of the eSCI_A module, CN_A_RX pin as an input, and CN_A_TX as an output of the CAN_A module. When Baud Rate Detection Mode is selected, the BAM program configures SCI_A_RX and CN_A_RX pins as GPI inputs for polling their state by the CPU. Table 391 shows the configuration summary for theSCI and CAN controllers pins.

shown in the Table 392 and waits for data reception. reconfiguring the SCI_A_RX pin to its reset state. submode, disables CAN_A module and configures its pins to their reset state. Then the BAM program transitions to the serial download protocol execution. divided by 40, using the standard 11-bit identifier format detailed in CAN 2.0A specification. Table 391. CAN/eSCI pins configuration for CAN/eSCI fixed baud rate boot modes Table 392. Serial boot mode – baud rate & watchdog summary

The SWT is used as a watchdog during serial boot mode, but t he core watchdog is enabled just before switching to the user

application to provide compatibility with earlier parts.

The bit timing is configured as shown in Figure 406. Figure 406. CAN bit timing the “echoes” with the sent data and restart the process if an error is detected. baud rate equal to system clock divided by 832. See Table 392 for examples of baud rates. compare the echoes with the sent data and restart the process if an error is detected.

Host sends 64-bit password.
Host sends start address, size of download code in bytes, and VLE bit.
Host sends the application code data.
The device switches to the loaded code at the start address.

1 Bit Time

A message with 0x11 ID and 8-byte length is used to send the password. The device transmits the same data, but the message ID is set to 0x1.
A message with 0x12 ID and 8-byte length is used to send the start address, length, and the VLE mode bit. The device transmits back the same data, but with ID set to 0x2.
Messages with 0x13 ID are used to send the downloaded data. The device transmits back received data with message ID of 0x3. When the SCI is used for serial download, the data has to be sent on a byte-by-byte basis. the device transmits back the received data. Download protocol execution The BAM program executes the serial boot as follows: 1. Download 64-bit password. The received 8-byte password is checked for validity. For a password to be valid, none of its four 16-bit half words must equal 0x0000 or 0xFFFF. The BAM program then checks the censorship status of the device by checking the bit SIU_CCR[DISNEX]. If Nexus is disabled, the device is considered to be censored and the password is compared with a password stored in the shadow row in internal flash memory. If Nexus is enabled, the device is not considered to be censored and the password is compared to the fixed value = 0xFEED_FACE_CAFE_BEEF. If the password check fails, the device stops responding. To get the device out of that state, the RESET signal must be asserted. If the password check passes, the BAM transitions to the next step in the protocol. 2. Download start address, size of download, and VLE bit. The next 8 bytes received by the device are considered to contain a 32-bit start address, the VLE mode bit, and a 31-bit code length (see Figure 407).

Figure 407. Start address, VLE bit and download size in bytes

Boot Assist Module (BAM) RM0029 662/1740 Doc ID 15177 Rev 8 address are ignored by the BAM program, such that the loaded code should be 32-bit word aligned. The length defines how many data bytes to be loaded. The VLE mode bit instructs the device to program MMU entries 1–3 with VLE attribute. If it is 1, the downloaded code must be compiled to VLE instructions, if it is 0 the code contains Power instructions. 3. Download data. Each byte of data received is stored in the device memory, starting at the address specified in the previous protocol step, and incrementing through memory until the number of bytes of data received and stored in memory matches the number specified in the previous protocol step. BAM program buffers incoming data, collecting up to eight bytes. The buffered data is written to the RAM with 64-bit writes to prevent ECC errors, which may happen if the device RAM is protected by 64-bit ECC code. Once the buffered data is written to the RAM the BAM program refreshes the SWT watchdog. Note: Only system RAM supports 64-bit writes; therefore, attempting to download data to other RAM apart from system RAM will cause errors. If the start address of the downloaded data is not on an 8-byte boundary, the BAM will write 0x0 to the memory locations from the proceeding 8-byte boundary to the start address (maximum 4 bytes). The BAM also writes 0x0 to all memory locations from the last byte of data downloaded to the following 8 byte boundary (maximum 7 bytes) and additional 8 zero bytes to prevent possible ECC errors may be caused by the CPU prefetching. 4. Switch to the loaded code. The BAM program waits for the last echo message transmission to complete, then the active communication controller is disabled. Its pins revert to GPIO inputs. To provide compatibility with older devices, the BAM writes the core time base registers (TBU and TBL) with 0x0 and enables the core watchdog to cause a reset after a time- out period of 2.5 x 2 27 system clock cycles and disables SWT watchdog. See Table 392 for examples of time out periods. The BAM code passes control to the loaded code at start address, which was received in step 2 of the protocol. Note: The loaded code must periodically refresh the core watchdog timer or change the timeout period to a value that will not cause resets during normal operation. Baud rate detection procedure To improve baud rate detection accuracy the baud rate detection routine is copied to the beginning of the system RAM from the BAM ROM. Then the CPU branches to the RAM. The device configures the CN_A_RX and SCI_A_RX pins as general purpose inputs and starts to poll them until one of them goes low. If the CN_A_RX pin transitions first, the BAM program starts CAN baud rate detection routine, ignoring SCI_A_RX. After detecting the CAN baud rate, the BAM program transitions to the CAN download protocol routine described above. If the SCI_A_RX pin transitions first, the SCI baud rate detection and download protocol routines are called, ignoring any further CAN pins activity.

host transmits 1 start bit, 8 zero data bits and 1 stop bit. The device does not echo it. over 9 bits with 16 system clocks per bit). does not acknowledge this message. FlexCAN chapter for the parameters definition). Table 393. CAN bit timing lookup table

device system frequency and shown in Table 394.

21.5.6 Booting from the External Bus Interface (EBI)

bus pins and tries to read RCHW from logical address 0x2000_0000. passes control to the user code. If no valid RCHW was read, BAM switches to the serial boot mode. Table 393. CAN bit timing lookup table (continued) Table 394. Maximum and minimum detectable baud rates

Limited to 1 Mbit/s by CAN standard

The BAM program sets up EBI related registers as shown in Table 396. Table 395. MMU Configuration for EBI Boot and Serial Boot modes

1 Internal Flash 0x0000_0000 0x2000_0000 16 Mbytes

2 EBI 0x2000_0000 0x2000_0000 16 Mbytes

Table 396. EBI register settings

Configurable Enhanced Modular IO Subsystem (eMIOS200) RM0029 666/1740 Doc ID 15177 Rev 8

22 Configurable Enhanced Modular IO Subsystem

(eMIOS200)

22.1 Device-specific features

Sixteen 24-bit wide channels
3 channels internal timebases can be shared between channels
1 timebase from the eTPU can be imported and used by the channels
Global enable feature for all eMIOS200 and eTPU timebases
Doze mode is not supported
Each channel has its own pin (not available on all package types)

22.2 Introduction

The eMIOS200 module provides the capability to generate or measure timed events, for example generating PWM waveforms or measuring input pulse width. It is implemented with its own configuration of timer channels to suit the target applications needs, while maintaining full backwards compatibility with previous eMIOS implementations. The SPC564A74xx, SPC564A80xx has one eMIOS200 module that implements twenty-four 24- bit counters. The overall architecture of the eMIOS200 resembles that of its predecessor, the MIOS. The MIOS timer block provided a framework where a set of sublocks with different timer functions were assembled to attend the specific needs of a device. The SPC564A74xx, SPC564A80xx eMIOS200 builds on this concept by using a modified Unified Channel module that provides a superset of the functionality of individual MIOS channels, while providing a consistent user interface. This allows more flexibility as each channel can be programmed for different functions in different applications of the device. In addition, the eMIOS200 architecture allows the use of dedicated channels that perform specific functions not included in MIOS inheritance. Note: The SPC564A74xx, SPC564A80xx eMIOS200 uses a modified version of the Unified Channel block that contains a reduced set of functions . See Section 22.2.3, Channel configurations, for details. Figure 408 shows the block diagram of the SPC564A74xx, SPC564A80xx eMIOS200 module.

Figure 408. eMIOS200 block diagram

22.2.1 Features

Twenty-four 24-bit wide channels
3 channels’ internal timebases can be shared between channels
1 timebase from eTPU2 can be imported and used by the channels
Global enable feature for all eMIOS and eTPU timebases
Dedicated pin for each channel (not available on all package types) Channel[7] Channel[0] [B] EMIOS[7] EMIOS[0] [A] Counter Buses (Time Bases) All Submodules Internal Counter Clock Enable IIB Output Disable Input[3:0] Global Time Base Enable Global Time Base Bit (GTBE) Output System Clock BIUIP Interface Clock Prescaler Output Disable Control Bus Channel[15] Channel[8] [C] EMIOS[15] EMIOS[8] Channel[23] Channel[16] [D] EMIOS[23] EMIOS[16] Enhanced Modular I/O System (eMIOS200)

General-purpose input/output (GPIO)
Single-action input capture (SAIC)
Single-action output compare (SAOC)
Output pulse-width modulation buffered (OPWMB)
Input period measurement (IPM)
Input pulse-width measurement (IPWM)
Double-action output compare (DAOC)
Modulus counter buffered (MCB)
Output pulse width and frequency modulation buffered (OPWFMB)

22.2.2 Modes of operation

Run mode is the normal operation mode.
Module disable mode is used for MCU power management. The clock to the non-memory-mapped logic in the eMIOS200 is stopped while in module disable mode. Module disable mode is entered when EMIOS_MCR[MDIS] = 1.
Debug mode is individually programmed for each channel. When entering this mode, the unified channel registers’ contents are frozen but remain available for read and write access through the IP interface.

22.2.3 Channel configurations

eMIOS200. These modes are described in Section , Channel modes of operation. Table 397. All available SPC564A74xx, SPC564A80xx eMIOS channel configurations

22.3 External signals description

single bidirectional pin. See Chapter 3: Signal Description for details.

22.4 Memory map/register definition

22.4.1 Memory map

The overall address map organization is shown in Table 398. Table 398. SPC564A74xx, SPC564A80xx eMIOS memory map

Table 398. SPC564A74xx, SPC564A80xx eMIOS memory map (continued)

22.4.2 Global registers

because the SPC564A74xx, SPC564A80xx has 24 channels and 24-bit counters. The EMIOS_MCR contains global control bits for the eMIOS200 module.

The alternate address register provides and alternate read-only address to access A2 channel register in

Figure 409. eMIOS200 Module Configuration Register (EMIOS_MCR)

Table 399. EMIOS_MCR field description except access to the EMIOS_MCR, EMIOS_OUDR and EMIOS_UCDIS registers.

0 Clock is running

1 Enter low power mode

MCU exits Debug mode or the channel’s FREN bit is cleared.

0 Exit freeze state

1 Stops channels operation when in Debug mode and the FREN bit is set in the EMIOS_CCR[n]

to start time bases of several blocks simultaneously.

0 Global Time Base Enable Out signal negated

1 Global Time Base Enable Out signal asserted

enabled. When negated, internal counters disabled. The ETB bit selects the time base source that drives counter bus[A].

0 Counter bus[A] assigned to eMIOS Channel

1 STAC drives counter bus [A]

for more information about the STAC. The GPREN bit enables the prescaler counter.

0 Prescaler disabled (no clock) and prescaler counter is cleared

1 Prescaler enabled

Selects the address of a specific STAC server to which the STAC client submodule is assigned. See Section 22.5.3, STAC client submodule.

0001 Reserved

0011 Reserved

The GPRE bits select the clock divider value for the global prescaler. Table 399. EMIOS_MCR field description (continued) Figure 410. eMIOS200 Global Flag Register (EMIOS_GFR)

Table 400. EMIOS_GFR field description Channel Status Register (EMIOS_CSR[n]), for more detail. Figure 411. eMIOS200 Output Update Disable Register (EMIOS_OUDR)

10 OU9 OU8 OU7 OU6 OU5 OU4 OU3 OU2 OU1 OU0

Table 401. EMIOS_OUDR field description next period. Unless stated otherwise, transfer occurs immediately.

22.4.3 Channel registers

because the SPC564A74xx, SPC564A80xx has 24 channels and 24-bit counters. captures, can be assigned to address EMIOS_CADR[n]. A1 and A2 are cleared by reset. modes. For more information see Section , Channel modes of operation. Figure 412. eMIOS200 Channel Disable Register (EMIOS_UCDIS) Table 402. EMIOS_UCDIS field description The CHDIS[n] bit is used to disable a channel by stopping its respective clock.

0 Channel [n] enabled

1 Channel [n] disabled

Figure 413. eMIOS200 Channel A Data Register (EMIOS_CADR[ n])

Section , Channel modes of operation. (EMIOS_CBDR) in all channels. Figure 414. eMIOS200 Channel B Data Register (EMIOS_CBDR[ n])

The EMIOS_CCNTR[n] contains the value of the internal counter for eMIOS channel n. When GPIO mode is selected or the channel is frozen the EMIOS_CCNTR[n] is read/write. Table 403. EMIOS_CADR[ n], EMIOS_CBDR[n], and EMIOS_ALTA[n] values assignment

In this mode, the register EMIOS_CBDR[n] is not used but B2 can be accessed.

Figure 415. eMIOS200 Channel Counter Register (EMIOS_CCNTR[ n])

In GPIO mode or freeze action, this register is writable.

condition of the internal counter, and several read/write control bits for eMIOS channel n. Figure 416. eMIOS200 Channel Control Register (EMIOS_CCR[ n]) Table 404. EMIOS_CCR field description debug mode, allowing the MCU to perform debug functions.

1 Freeze unified channel registers’ values

0 The output pin operates normally.

1 The output pin is driven to the value in EDPOL for OPWFMB and OPWMB modes and to the

negated, the output pin operates normally. The ODISSL bits select one of the four output disable input signals.

00 Output disable input 0

01 Output disable input 1

10 Output disable input 2

11 Output disable input 3

The UCPREN bit enables the prescaler counter.

0 Prescaler disabled (no clock) and prescaler counter is loaded with UCPRE value

0 FLAG/overrun assigned to interrupt request

1 FLAG/overrun assigned to DMA request

pass through the filter. For output modes, these bits have no meaning. The FCK bit selects the clock source for the programmable input filter.

0 Prescaled clock

1 Main clock

Table 404. EMIOS_CCR field description (continued)

Filter latency is three clock edges.

0000 Bypassed(2)

The input signal is synchronized before arriving to the digital filter.

signal (the type of signal to be generated is defined by the DMA bit).

0 Disable (FLAG does not generate an interrupt or DMA request)

1 Enable (FLAG generates an interrupt or DMA request)

valid for every output operation mode which uses comparator A, otherwise it has no effect.

0 Has no effect

1 Force a match at comparator A

For input modes, the FORCMA bit is not used and writing to it has no effect. valid for every output operation mode which uses comparator B, otherwise it has no effect. 1 Force a match at comparator B. For input modes, the FORCMB bit is not used and writing to it has no effect. All channels: Counter bus[A]. When BSL = 0, Channel 23 must be in MCB mode. time base to channels 0 to 7. time base to channels 8 to 15. time base to channels 16 to 23. When BSL = 1, Channels 0, 8 and 16 must be in MCB mode.

11 All channels: internal counter

description, this bit has no effect. 0 Single edge triggering defined by the EDPOL bit. For GPIO in mode, the EDSEL bit selects if a FLAG can be generated. 0 A FLAG is generated as defined by the EDPOL bit. For SAOC mode, the EDSEL bit selects the behavior of the output flip-flop at each match. 0 The EDPOL value is transferred to the output flip-flop. 1 The output flip-flop is toggled. capture or a FLAG. When not shown in the mode of operation description, this bit has no effect. 0 Trigger on a falling edge. For output modes, the EDPOL bit is used to select the logic level on the output pin. 0 A match on comparator A clears the output flip-flop, while a match on comparator B sets it. 1 A match on comparator A sets the output flip-f lop, while a match on comparator B clears it. to Table 397 for more information on the different modes. If a reserved value is written to MODE, the results are unpredictable. Table 405. MODE values

0000000 General purpose Input/Output mode (input)

0000001 General purpose Input/Output mode (output)

0000010 Single Action Input Capture

0000011 Single Action Output Compare

0000100 Input Pulse Width Measurement

0000101 Input Period Measurement

0000110 Double Action Output compare (with FLAG set on B match)

0000111 Double Action Output compare (with FLAG set on both match)

1001111 Reserved(1)

1111111 Reserved(1)

If a reserved value is written to MODE, the results are unpredictable.
b = adjust parameters for the mode of operation. Refer to Section , Channel modes of operation , for details.

Table 405. MODE values (continued) Figure 417. eMIOS200 Channel Status Register (EMIOS_CSR[ n]) Table 406. EMIOS_CSR[ n] field description can be cleared by clearing the FLAG bit or by software writing a ‘1’. cleared by software writing a ‘1’. 0 An overflow has not occurred.

EMIOS_ALTA[n], both A1 and A2 registers can be accessed in these modes.

22.5 Functional description

accessed by a host MCU. The channels are reduced-function versions of Unified Channels. channel can generate its own time base. The eMIOS200 block is reset asynchronously. All registers are cleared on reset. The UCIN bit reflects the input pin state after being filtered and synchronized. The UCOUT bit reflects the output pin state. must be cleared by software writing a ‘1’. 1 FLAG set event has occurred. When the DMA bit is set, the FLAG bit can be cleared by the DMA controller. Table 406. EMIOS_CSR[ n] field description (continued) Figure 418. eMIOS200 UC Alternate A Register (EMIOS_ALTA[n])

RM0029 Configurable Enhanced Modular IO Subsystem (eMIOS200) Doc ID 15177 Rev 8 691/1740

22.5.1 Unified channel (UC)

Figure 419 shows the eMIOS200 Unified Channel(s) block diagram. Each Unified Channel consists of:

Counter bus selector, which selects the time base to be used by the channel for all timing functions
A programmable clock prescaler
Two double buffered data registers A and B that allow up to two input capture and/or output compare events to occur before software intervention is needed.
Two comparators (equal only) A and B, which compares the selected counter bus with the value in the data registers
Internal counter, which can be used as a local time base or to count input events
Programmable input filter, which ensures that only valid pin transitions are received by channel
Programmable input edge detector, which detects the rising, falling or either edges
An output flip-flop, which holds the logic level to be applied to the output pin
eMIOS200 Status and Control register
An Output Disable Input selector, which selects the Output Disable Input signal that will be used as output disable s. The eMIOS200 Unified Channel has a reduced set of functions when compared to legacy Unified Channel implementations.

Figure 420. Unified Channel Control and Datapath block diagrams EMIOS_CCR[n] (see Table 405 for details). disabled state according to ODIS bit in the EMIOS_CCR[n]. mode), it is possible to use it as a time base if the resource is not used in the current mode.

Configurable Enhanced Modular IO Subsystem (eMIOS200) RM0029 694/1740 Doc ID 15177 Rev 8 To provide smooth waveform generation while allowing A and B registers to be asynchronously updated during UC operation, the double-buffered modes (MCB, OPWFMB and OPWMB) are provided. In these modes A and B registers are double buffered. General purpose input/output mode (GPIO) mode In GPIO mode, all input capture and output compare functions are disabled, the internal counter (EMIOS_CCNTR[n]) is cleared and disabled. All control bits remain accessible. In order to prepare the channel for a new operation mode, writing to registers EMIOS_CADR[n] or EMIOS_CBDR[n] stores the same value in registers A1/A2 or B1/B2, respectively. Writing to register EMIOS_ALTA[n] stores a value only in register A2. The EMIOS_CCR[n]’s MODE[6] bit selects between input (MODE[6] = 0) and output (MODE[6] = 1) modes. Note: It is required that when changing MODE[0:6], the application software goes to GPIO mode first in order to reset the channel’s internal functions properly. Failure to do this could lead to invalid and unexpected output compare or input capture results or the FLAGs being set incorrectly. In GPIO input mode (MODE[0:6] = 0000000), FLAG generation is determined according to the EMIOS_CCR[n]’s EDPOL and EDSEL bits and the input pin status can be determined by reading the EMIOS_CSR[n]’s UCIN bit. In GPIO output mode (MODE[0:6] = 0000001), the channel is used as a single output port pin and the value of the EMIOS_CCR[n]’s EDPOL bit is permanently transferred to the output flip-flop. When changing the EMIOS_CCR[n]’s MODE bits, the application software must go to GPIO mode first to reset the channel’s internal functions properly. Failure to do this could lead to invalid and unexpected output compare or input capture results or the FLAGs being set incorrectly. Single action input capture (SAIC) mode In SAIC mode (MODE[0:6] = 0000010), when a triggering event occurs on the input pin, the value on the selected time base is captured into register A2. The FLAG bit is set along with the capture event to indicate that an input capture has occurred. EMIOS_CADR[n] returns the value of register A2. As soon as the SAIC mode is entered exiting from GPIO mode the channel is ready to capture events. The events are captured as soon as they occur thus reading register A always returns the value of the latest captured event. Subsequent captures are enabled with no need of further reads from EMIOS_CADR[n]. The FLAG is set at any time a new event is captured. The input capture is triggered by a rising, falling or either edges in the input pin, as configured by EDPOL and EDSEL bits in EMIOS_CCR[n]. Figure 421 and Figure 422 show how the Unified Channel can be used for input capture.

register content even if B1 update is locked by a previous EMIOS_CADR[n] read operation. Figure 427. B1 and A1 updates at EMIOS_CADR[n] and EMIOS_CBDR[n] reads EMIOS_CBDR[n] is required in order to release B1 register updates. signal by capturing two consecutive rising edges or two consecutive falling edges. polarity is defined by the EDPOL bit in the EMIOS_CCR[n]. register B2 is transferred to register B1. register A2 and B1, respectively.

Configurable Enhanced Modular IO Subsystem (eMIOS200) RM0029 702/1740 Doc ID 15177 Rev 8 The internal counter values operates within a range from 0x1 up to register A1 value. If when entering MCB mode exiting from GPIO mode the internal counter value is not within that range then the A match will not occur causing the channel internal counter to wrap at the maximum counter value which is 0xFF_FFFF for a 24-bit counter. After the counter wrap occurs it returns to 0x1 and resume normal MCB mode operation. Thus in order to avoid the counter wrap condition make sure its value is within the 0x1 to A1 register value range when the MCB mode is entered. MODE[6] bit selects internal clock source if cleared or external if set. When external clock is selected the input channel pin is used as the channel clock source. The active edge of this clock is defined by EDPOL and EDSEL bits in the EMIOS_CCR[n]. When entering MCB mode, if the up counter is selected by MODE[4] = 0 (MODE[0:6] = 101000b), the internal counter starts counting from its current value to up direction until A1 match occurs. The internal counter is set to 0x1 when its value matches A1 value and a clock tick occurs (either prescaled clock or input pin event). If the up/down counter is selected by setting MODE[4] = 1, the counter changes direction at A1 match and counts down until it reaches the value 0x1. After it has reached 0x1 it is set to count in up direction again. The B1 register is used to generate a match in order to set the internal counter in up-count direction if up/down mode is selected. Register B1 cannot be changed while this mode is selected. Note that differently from the MC mode, the MCB mode counts between 0x1 and the A1 register value. Only values greater than 0x1 must be written at A1 register. Loading values other than those leads to unpredictable results. The counter cycle period is equal to A1 value in up counter mode. If in up/down counter mode, the period is defined by the expression: (2*A1)-2. Figure 433 describes the counter cycle for several A1 values. Register A1 is loaded with the A2 register value at the cycle boundary. Thus any value written to the A2 register within cycle n will be updated to A1 at the next cycle boundary and therefore will be used on cycle n+1. The cycle boundary between cycle n and cycle n+1 is defined as when the internal counter transitions from A1 value in cycle n to 0x1 in cycle n+1. Note that the FLAG is generated at the cycle boundary and has a synchronous operation, meaning that it is asserted one system clock cycle after the FLAG set event.

Configurable Enhanced Modular IO Subsystem (eMIOS200) RM0029 714/1740 Doc ID 15177 Rev 8 In order to ensure safe working and avoid glitches the following steps must be performed whenever any update in the prescaling rate is desired: 1. Write ‘0’ at both bit EMIOS_MCR[GPREN] and UCPREN bit in EMIOS_CCR[n], thus disabling prescalers; 2. Write the desired value for prescaling rate at UCPRE[0:1] bits in EMIOS_CCR[n]; 3. Enable channel prescaler by writing ‘1’ at UCPREN bit in EMIOS_CCR[n]; 4. Enable global prescaler by writing ‘1’ at bit EMIOS_MCR[GPREN]. The prescaler is not disabled during either freeze state or negated GTBE input. Effect of freeze on the unified channel When in debug mode, bit EMIOS_MCR[FRZ] and the FREN bit in the EMIOS_CCR[n] are both set, the internal counter and channel capture and compare functions are halted. The channel is frozen in its current state. During freeze, all registers are accessible. When the channel is operating in an output mode, the force match functions remain available, allowing the software to force the output to the desired level. Note that for input modes, any input events that may occur while the channel is frozen are ignored. When exiting debug mode or freeze enable bit is cleared (bit EMIOS_MCR[FRZ] or FREN in the EMIOS_CCR[n]), the channel actions resume but may be inconsistent until the channel enters GPIO mode again.

22.5.2 IP bus interface unit (BIU)

The BIU provides the interface between the Internal Interface Bus (IIB) and the Peripheral Bus, allowing communication among all submodules and this IP interface. The BIU allows 8, 16 and 32 bits access. They are performed over a 32-bit data bus in a single cycle clock. Effect of freeze on the BIU When bit EMIOS_MCR[FRZ] is set and the module is in debug mode, the operation of BIU is not affected.

22.5.3 STAC client submodule

The shared time and angle count (STAC) bus provides access to one external time base, imported from the STAC bus to the eMIOS unified channels. The eTPU module’s time bases and angle count can be exported and/or imported through the STAC client submodule interface. Time bases and/or angle information of the eTPU engine can be exported to the eMIOS module, which is only a STAC client. There are restrictions on engine export/import targets: an engine cannot export from or import to itself, nor can it import time base and/or angle count if in angle mode. The device’s STAC server identification assignment is shown in Table 407. The time slot assignment is fixed, so only time bases running at system clock divided by four or slower can be integrally exported. The STAC client submodule runs with the system clock, and its time slot timing is synchronized with the eTPU timing on reset. The time slot sequence is 0- 1-2-3.

Configurable Enhanced Modular IO Subsystem (eMIOS200) RM0029 716/1740 Doc ID 15177 Rev 8

22.5.4 Global clock prescaler submodule (GCP)

The GCP divides the system clock to generate a clock for the CPs of the channels. The main clock signal is prescaled by the value defined in the GPRE[0:7] bits in the EMIOS_MCR. The global prescaler is enabled by setting bit EMIOS_MCR[GPREN] and can be stopped at any time by clearing this bit, thereby stopping the internal counters in all the channels. In order to ensure safe working and avoid glitches the following steps must be performed whenever any update in the prescaling rate is desired: 1. Write ‘0’ at bit EMIOS_MCR[GPREN], thus disabling global prescaler. 2. Write the desired value for prescaling rate at GPRE[0:7] bits in EMIOS_MCR. 3. Enable global prescaler by writing ‘1’ at bit EMIOS_MCR[GPREN]. The prescaler is not disabled during either freeze state or negated GTBE input. Effect of freeze on the GCP When bit EMIOS_MCR[FRZ] is set and the module is in debug mode, the operation of GCP submodule is not affected, that is, there is no freeze function in this submodule.

22.6 Initialization/Application information

On resetting the eMIOS200 the channels enter GPIO input mode.

22.6.1 Considerations

Before changing an operating mode, the UC must be programmed to GPIO mode and EMIOS_CADR[n] and EMIOS_CBDR[n] registers must be updated with the correct values for the next operating mode. Then the EMIOS_CCR[n] can be written with the new operating mode. If a channel is changed from one mode to another without performing this procedure, the first operation cycle of the selected time base can be random, that is, matches can occur in random time if the contents of EMIOS_CADR[n] or EMIOS_CBDR[n] were not updated with the correct value before the time base matches the previous contents of EMIOS_CADR[n] or EMIOS_CBDR[n]. When interrupts are enabled, the software must clear the FLAG bits before exiting the interrupt service routine.

22.6.2 Application information

Correlated output signals can be generated by all output operation modes. Bits OU[n] of the EMIOS_OUDR can be used to control the update of these output signals. In order to guarantee that the internal counters of correlated channels are incremented in the same clock cycle, the internal prescalers must be set up before enabling the global prescaler. If the internal prescalers are set after enabling the global prescaler, the internal counters may increment in the same ratio but at a different clock cycle. Channel/Modes initialization The following basic steps summarize basic output mode startup, assuming the channels are initially in GPIO mode:

RM0029 Configurable Enhanced Modular IO Subsystem (eMIOS200) Doc ID 15177 Rev 8 717/1740 1. [global] Disable global prescaler. 2. [timebase channel] Disable channel prescaler. 3. [timebase channel] Write initial value at internal counter. 4. [timebase channel] Set A/B register. 5. [timebase channel] Set channel to MCB up mode. 6. [timebase channel] Set prescaler ratio. 7. [timebase channel] Enable channel prescaler. 8. [output channel] Disable channel prescaler. 9. [output channel] Set A/B register. 10. [output channel] Select timebase input through BSL[1:0] bits.

Reaction Module (REACM) RM0029 718/1740 Doc ID 15177 Rev 8

23 Reaction Module (REACM)

23.1 Introduction

The Reaction Module (REACM) is composed of 6 channels. Each channel contains three outputs. The primary application of this module is in the area of solenoid control for direct injection systems, valve control in automatic transmissions and others. It is connected to the on-chip ADC which monitors the current on the solenoid or valve. Based on that the reaction channel generates a PWM signal that modulates the current circulating in the solenoid or valve. It is a cost effective solution due to extensive sharing of several resources among channels and parameterized register banks for adequate dimensioning of resources and functionality.

23.1.1 Features

The REACM features include:

Per-channel architecture for independent output control
Interface with on-chip ADC for fast response times
Hardware connection with on-chip timer channels with channel routing capability
Innovative concept of Shared Modulation Control
Innovative concept of dynamic timer allocation
3 outputs per channel to support different driver architectures
Flexibility to operate based on timing and threshold
On-the-fly capture of ADC result reference for fast calibration
Open and short circuit monitoring capability Note: DMA is not supported in SPC564A80 devices.

23.1.2 Modes of operation

After a reset is applied, the reaction module is in programming mode. In this mode all channels are disabled and outputs are at logic zero. Note that this state does not necessarily mean that zero is the neutral state for the channel load, so care must be taken in order to disconnect the channel from the load in this case. In the programming mode the host CPU writes all module parameters including:

RM0029 Reaction Module (REACM) Doc ID 15177 Rev 8 719/1740 1. Modulation word data (see Section 23.4.2, Modulation control words bank) 2. Channel control data (see Section 23.3.7, REACM Channel n Configuration Register (REACM_CHCRn)) 3. Threshold data (see Section 23.3.12, REACM Threshold Bank Register (REACM_THBK)) 4. Timer bank data (see Section 23.3.10, REACM Shared Timer Bank Registers (REACM_STBK)) 5. Hold-off timer bank data (see Section 23.3.11, REACM Hold-off Timer Bank Registers (REACM_HOTBK)) 6. Timer router data (see Section 23.3.9, REACM Channel n Router Register (REACM_CHRRn)) 7. ADC router data (see Section 23.3.4, REACM Threshold Router Register (REACM_THRR)) The last action to perform is to enable the channel, after which the channel is able to respond to timer signals and ADC data, thus able to perform modulation on the output pins. It is recommended to keep the timer signals inactive until all data to all reaction channel modules are programmed and all channels have been put in the enabled mode. Low power mode Coming out of reset all channels are in the disabled state. The channel may also be in low power mode depending on a parameter that configures the initial state of the MDIS in the REACM module configuration register (REACM_MCR) (see Figure 453). If REACM_MCR[MDIS] = 1 the module clock may be disabled allowing for a low power state. The low power mode is controlled either by REACM_MCR[MDIS] or by a global stop signal. There is no explicit clock gating implemented in hardware within the reaction module. Note: Low power mode must be entered only when all channels are disabled by REACM_CHCRn[CHEN] = 00. Channel modes After a channel is in enabled mode that channel is also said to be in the normal mode of operation, which means it responds to timer signals from the timer inputs connected to the reaction module and also to ADC results received from the on-chip ADC module. Channel outputs are controlled in accordance with those inputs in order to perform an output modulation process. When performing a modulation the reaction channel is said to be in the active state. The modes a reaction channel can be in and the ability to execute a modulation related to the modes are:

Disabled: The channel cannot execute modulation.
Enabled: The channel is able to execute a modulation. It may be in the Active or Inactive state. – Inactive state: The channel is not executing a modulation. – Active state: The channel is executing a modulation. Debug mode The Reaction Module Debug operation is defined by bits FRZ and FREN in the REACM module configuration register (REACM_MCR) (see Figure 453). In debug mode all timers are halted, including the timers in the Shared Time Bank and Hold-off Timers.

Reaction Module (REACM) RM0029 720/1740 Doc ID 15177 Rev 8 The module can enter debug mode either by software control or by the hardware debug input signal controlled by the chip logic. In both cases the reaction module only enters debug mode if enabled by bit REACM_MCR[FREN]:

If the FREN bit and the FRZ bit are both is asserted the module enters debug mode.
If the FREN bit is asserted and a global debug signal is issued the module enters debug mode. In debug mode, the channel outputs are held at HOD (High Output Drive), LOD (Low Output Drive), or Drive Off (DOFF) state, as determined by the current channel state. When resuming normal operation after exiting debug mode the channel output is set to DOFF until the next timer control rising edge occurs. The ADC Maximum Limit Detection (REACM_CHSRn[MAXL]) flag is the only flag that operates in debug mode. All other flags keep the state present when the module entered debug mode. Note that the corresponding error flag in the REACM Global Error Flag Register (REACM_GEFR) (Figure 457) is also set. The REACM ADC Sensor Input Register (REACM_SINR) allows direct access for write to the TAG and ADC result values input to the reaction module. This software control may be used for module debug purposes. Please see Figure 456.

23.1.3 Block diagram

Figure 450 shows the on-chip connections of the reaction module. The ADC module is the source of data monitored from external sensors, usually voltage information, which is used by the reaction channel modulation to generate an PWM signal control signal in order to maintain the load current within a certain predefined boundary. The on-chip eTPU module is commonly used as the source for controlling the activation of a reaction channel. Alternatively an eMIOS or PIT module can be used to provide that control signal.

Figure 452. Reaction module block diagram Table 408 lists the SPC564A74xx, SPC564A80xx reaction module outputs.

3 Timers

Table 408. Reaction module outputs

can be routed to more than one reaction channel. The modulation process starts when an ADC result arrives and the time window is active. word using the information stored in the REACM_CHCRn. result back to the channels. Table 408. Reaction module outputs (continued)

23.2 Signal description

Table 409 shows the chip-level signals for the Reaction Module.

23.2.1 REACM_RCHn — REACM Channel (n) Output Pin a, b and c

23.3 Memory map and register definition

23.3.1 Module memory map

Table 410 presents the reaction module memory map. Table 409. Signal properties Table 410. Reaction module memory map

23.3.2 REACM module configuration register (REACM_MCR)

configure the general operation of the Reaction Module. Table 410. Reaction module memory map (continued)

Figure 453. REACM module configuration register (REACM_MCR) Table 411. REACM_MCR field descriptions same time a flag clear is done, the set event has precedence over the clear thus the flag remains set.

0 No action

1 Clears OVR bit

FRZ and FREN bits. The global debug signal state is not changed internally while in low power mode.

0 Normal Mode

1 Debug Mode

3 Reserved, should be cleared. Reaction Module is in stopped by a device stop request.

0 Debug Mode disabled

1 Debug Mode enable

The TPREN bit enables the Shared Timer Prescaler in the Reaction Module.

0 Prescaler Disabled

23.3.3 REACM Timer Configuration Register (REACM_TCR)

Figure 454. REACM Timer Configur ation Register (REACM_TCR) The HPREN bit enables the Hold-off Prescaler in the Reaction Module. in Section 23.3.7, REACM Channel n Configuration Register (REACM_CHCRn).

0 Interrupt disabled

1 Interrupt enabled

inhibit the channel interrupts. The OVREN enables the OVR flag, when set, to generate a global interrupt request for the CPU. 9–31 Reserved, should be cleared. Table 411. REACM_MCR field descriptions (continued)

23.3.4 REACM Threshold Router Register (REACM_THRR)

channels. In this case the results are routed to both, the channel and the Threshold Bank. used for the channel modulation being executed. Figure 455. REACM Threshold Router Register (REACM_THRR) Table 412. REACM_TCR field descriptions 0–3 Reserved, should be cleared. which defines system clock divided by 4096. 16–23 Reserved, should be cleared.

23.3.5 REACM ADC Sensor Input Register (REACM_SINR)

value for the channel outputs. Figure 456. REACM ADC Sensor Input Register (REACM_SINR) Table 413. REACM_THRR field descriptions 0–5 Reserved, should be cleared. will be written into address one of the Threshold Bank. will be written into address zero of the Threshold Bank. 8–19 Reserved, should be cleared. address one. Any ADC result which TAG matching THRADC1 will be routed to Threshold Bank. 24–27 Reserved, should be cleared. address zero. Any ADC result which TAG matching THRADC0 will be routed to Threshold Bank.

23.3.6 REACM Global Error Flag Register (REACM_GEFR)

Figure 457. REACM Global Error Flag Register (REACM_GEFR) Table 414. REACM_SINR field descriptions 0–11 Reserved, should be cleared. Module to select the reaction channel to execute the modulation. used for the Reaction Channel Modulation process or for capturing by the Threshold Bank. Table 415. REACM_GEFR field descriptions The OVR flag is used to indicate that an overrun condition was detected at the ADC Interface. See Section 23.4.6, ADC interface. 1–25 Reserved, should be cleared. corresponding channel flags are all cleared.

23.3.7 REACM Channel n Configuration Register (REACM_CHCRn)

Figure 458. REACM Channel n Confi guration Register (REACM_CHCRn) Table 416. REACM_CHCRn field descriptions

00 Channel disabled, meaning that it does not execute any modulation even if a timer

REACM_CHCR defines the state of the channel outputs.

01 Channel is enabled for timer control only, meaning that as soon as a timer window is

detected a modulation sequence starts.

11 Channel enabled for software control only, meaning that as soon as SWMC bit is set

a modulation sequence starts. and only after that write SWMC = 1. used it is required that CHEN[1:0] = 11.

1 Channel executes modulation

0 Channel does not perform modulation

The OCDFEN bit enables the OCDF bit to issue an interrupt request.

1 OCDF interrupt enabled

0 OCDF interrupt disabled

The SCDFEN bit enables the SCDF bit to issue an interrupt request.

1 SCDF interrupt enabled

0 SCDF interrupt disabled

The TAEREN bit enables the TAER bit to issue an interrupt request.

1 TAER interrupt enabled

0 TAER interrupt disabled

The SQEREN bit enables the SQER flag to generate an interrupt request.

1 SQER interrupt enabled

0 SQER interrupt disabled

The RAEREN bit enables the RAER flag to generate an interrupt request.

1 RAER interrupt enabled

0 RAER interrupt disabled

1 Enables channel DMA request

0 Disables channel DMA request

for the channel outputs. The output pins will set to DOFF value if CHOFF is asserted. only the channel outputs are forced to DOFF state.

1 Output Disable Enabled

0 Output Disable Disabled

11–12 Reserved, should be cleared. Table 416. REACM_CHCRn field descriptions (continued)

23.3.8 REACM Channel n Stat us Register (REACM_CHSRn)

being driven and the Modulation Word being accessed by the channel. by CHOFF in the Channel Configuration register. assured the new DOFF value is immediately used in the channel output. 16–20 Reserved, should be cleared. The BSB[2:0] provides control for a banked mode operation of the Reaction Module. Each bit in this field controls the channel outputs chn_c, chn_b and chn_a respectively. 24–25 Reserved, should be cleared. modified by the reaction channel in this process. Table 417. Output assignment through DOFF

Figure 459. REACM Channel n Status Register (REACM_CHSRn) Table 418. REACM_CHSRn field descriptions 0–1 Reserved, should be cleared.

1 Channel is active

0 Channel is not active

channel is in the active state (see Section , Channel modes).

1 ADC Maximum Limit Detected

only of the channel is in the active state.

1 Open Circuit Detected

the channel activation window signal is set (eTPU channel or SWMC bit).

1 Short Circuit Detected

1 Error occurred during timer allocation

0 No error occurred during timer allocation. indicates no advance, or SM = 00. This Flag is set only of the channel is in the active state.

1 Modulation Sequence Error occurred

0 Modulation Sequence Error did not occur. during software development and can be set only if the channel is in the enabled state.

1 Allocation error occurred

0 No allocation error occurred

pin. These bits are available independent of the channel mode or state. 12–18 Reserved, should be cleared.

1 Clears MAXL bit

Table 418. REACM_CHSRn field descriptions (continued)

23.3.9 REACM Channel n Router Register (REACM_CHRRn)

1 Clears OCDF bit

The SCDFC bit clears the SCDF flag if write ‘1’. This bit is self negated thus read always as ‘0’. the clear thus the flag remains set.

1 Clears SCDF

The TAERC bit clears the TAER bit if write ‘1’. This bit is self-negated thus reads always as ‘0’. the clear thus the flag remains set.

1 Clears TAER

The SQERC bit clears the SQER flag in the Channel Status register.

1 SQER flag is cleared

0 SQER flag is not cleared

The RAERC bit clears the RAER flag in the Channel Status register.

1 RAER flag is cleared

0 RAER flag is not cleared

25 Reserved, should be cleared. register is not buffered thus represents the current address being generated.

Figure 460. REACM Channel n Router Register (REACM_CHRRn) Table 419. REACM_CHRRn field descriptions 0–11 Reserved, should be cleared. The ADCR[3:0] field selects which ADC result is used by the reaction channel for the modulation. in order to define if the received result is used by the reaction channel. 16–27 Reserved, should be cleared. modulation. See Table 420 for valid values. Table 420. REACM_CHRRn[CHIR] values

23.3.10 REACM Shared Timer Bank Registers (REACM_STBK)

to indicate that a next Modulation Word should be used for the modulation. Figure 461. REACM Shared Timer Bank Registers (REACM_STBK)

23.3.11 REACM Hold-off Timer Bank Registers (REACM_HOTBK)

reaction channel based on the data read from a Modulation Word. Table 420. REACM_CHRRn[CHIR] values (continued) Table 421. REACM_STBK field descriptions 0–15 Reserved, should be cleared. values can be stored within the Timer Bank. greater than 64 clock cycles.

Figure 462. REACM Hold-off Timer Bank Registers (REACM_HOTBK)

23.3.12 REACM Threshold Bank Register (REACM_THBK)

channel decides the Channel output value to be either HOD or LOD. Figure 463. REACM Threshold Bank Register (REACM_THBK) Table 422. REACM_HOTBK field descriptions 0–19 Reserved, should be cleared. values can be stored within the Hold-off Timer Bank. greater than 64 clock cycles.

23.3.13 REACM ADC result maximum lim it check register (REACM_ADCMAX)

received the MAXL bit in the corresponding Channel Status Register Error is asserted. Figure 464. REACM ADC result maximum limit check register (REACM_ADCMAX)

23.3.14 REACM Modulation Range Pulse Width Register

Table 423. REACM_THBK field descriptions 0–15 Reserved, should be cleared. Register register used for a threshold modulation. Table 424. REACM_ADCMAX field descriptions 0–15 Reserved, should be cleared. performed, thus MAXL bit will not be set anyway. before any comparison is executed.

checking function is not active. Figure 465. REACM Modulation Range Pul se Width Register (REACM_RANGEPWD)

23.3.15 REACM Modulation Minimum Pu lse Width Register (REACM_MINPWD)

Table 425. REACM_RANGEPWD field descriptions 0–19 Reserved, should be cleared. RANGE_PWD = 0x00 then no maximum pulse width checking is performed.

Figure 466. REACM Modulation Minimum Pulse Width Register (REACM_MINPWD)

23.3.16 REACM Modulation Control Word Bank Registers (REACM_MWBK)

Figure 467. REACM Modulation Control Word Bank Registers (REACM_MWBK) Table 426. REACM_MINPWD field descriptions 0–19 Reserved, should be cleared. (MIN_PWD + 1) does not set the SCDF flag.

Table 427. REACM_MWBK field descriptions

1 Loop back to initial channel modulation word

0 Increment to the next modulation word

1 HOD[2:0] is initially used for chn_c, chn_b and chn_a respectively

0 LOD[2:0] is initially used for chn_c, chn_b and chn_a respectively

IOSS must not be 0b0 when MM is 0b01(threshold-holdoff). 2 Reserved, should be cleared. executed by the channel. Table 428 defines the modulation modes. IOSS must not be 0b0 when MM is 0b01(threshold-holdoff). 5 Reserved, should be cleared. defines the Sequencer modes. 8 Reserved, should be cleared. output pins, respectively, when the channel is at ON state. 12 Reserved, should be cleared. output pins, respectively, when the channel is at OFF state. 16 Reserved, should be cleared.

REACM Threshold Bank Register (REACM_THBK). The STPT[3:0] Shared Timer Pointer field is the pointer for the Shared Timer Bank. 27 Reserved, should be cleared. Table 427. REACM_MWBK field descriptions (continued) Table 428. MM[2:0] configuration: Modulation modes

00 Threshold/Threshold

defined by HOD and Output OFF state is defined by LOD.

01 Threshold/Hold-off

achieved which set channel outputs to an off state.

10 Reserved —

11 Reserved —

Table 429. SM[1:0] configuration: Sequencer modes

00 No advance Current modulation word is used, no advance is performed on any

event. No timer is activated by this modulation word.

01 Timer time-out

10 Hold-off timer time-out

modulation word is accessed by the channel.

11 Threshold level

achieved. The threshold level is defined by the THRESPT pointer.

Reaction Module (REACM) RM0029 746/1740 Doc ID 15177 Rev 8

23.4 Functional description

The following sections describe the Reaction Module functionality. The Reaction Module is designed to allow a closed feedback loop control over the driver load currents. The load can be an injector for a direct injection system or an electromagnetic actuator for a robotized transmission. In both cases it is expected that a solenoid will actually be the load. The module architecture is based on shared resources submodules that can be used by all six reaction channels. Please refer to Figure 452 for details about the module architecture. The Reaction Module comprises the following internal submodules:

Reaction Channel
Modulation Control Word Bank
Shared Timer Bank
Hold-off Bank
Threshold Bank The following sections describe each one of these submodules and their combined operation.

23.4.1 Reaction channel

The Reaction Channel is the core of the Reaction Module. Each channel controls three output pins and is controlled by a Control finite state machine (FSM) that receives parameters to generate a modulated waveform as well as the timer control window, usually provided by eTPU. The ADC interface indicates to the channel that a new ADC result is available. If activated by the eTPU channel, the reaction channel reads the Modulation Word which provides addresses for the Threshold Value bank, Shared Timer Bank and Hold-off Timer Bank. The date provided by the Threshold Bank is compared with the incoming ADC result. Based on that comparison the reaction channel state machine selects the values for the output pin registers. The modulation only occurs if activated by the timer control signal, which can be generated by eTPU, or can be controlled by software by writing to the SWMC, software modulation control bit, in the Channel Configuration register. The MM and SM fields in the Modulation Word provide the Modulation Mode and Sequencer Mode control, respectively. Figure 468 describes the internal architecture of the reaction channel and its interconnection with other submodules.

Figure 468. Reaction channel architecture simplified diagram The addresses stored in the Modulation Word are pointers to timers and threshold banks. generating the third waveform which represents the current passing through the load.

23.4.2 Modulation control words bank

Modulation control parameters for the reaction channel
Threshold Value Register Bank address
Hold-off bank address
Shared Timer bank address
DMA support All channels share the information stored in the Modulation Control Word Bank, which provides a size-effective implementation avoiding the duplication of information and allowing flexible implementation. The sharing of modulation control words allows several channels to execute the same modulation sequence. The Modulation Control is designed to be used by all reaction channels as a centralized resource. However, only one channel is able to access the Modulation bank at a given time. Therefore, there is a priority in the selection of the channel that will have the access granted, but note that this condition does not occur too often since ADC results are provided for one channel at a time. An arbiter in the Modulation Control Word bank selects one of the channels which are requesting access to a modulation word. The priority criteria is fixed and based on the channel number, considering Channel 0 the highest priority channel. The channel selected by the arbiter receives an acknowledge signal which indicates that channel was selected and therefore can access the modulation word. Note: In order to avoid an initial delay when processing a timer window start event, the channel performs a speculative read operation of the first modulation word when it is enabled (CHEN is configured). Therefore, when the modulation cycle is triggered by the timer window start event, all needed information for the modulation is already stored inside the channel.

Figure 469. Modulation control word bank interfaces

RM0029 Reaction Module (REACM) Doc ID 15177 Rev 8 749/1740

23.4.3 Shared timer bank

The Shared Timer bank is an innovative concept of dynamic timer allocation. Since the number of timers can be smaller than the number of channels in the Reaction Module, there is a possibility that all timers are allocated at a certain time. This architecture is based on the low probability of such scenario since the timer allocation is a sporadic event. The timers in the Shared Timer Bank are usually in IDLE state until they are allocated by a channel. Any timer can be allocated as soon as it is IDLE. The shared timers work in conjunction with a timer bank which stores values to be used by the timing measurement. The Shared Timer Bank block is composed of two submodules:

Three 16-bit counters
A bank with maximum of 16 selectable 16-bit time values If there is an attempt to allocate more than three timers then an error flag TAER (see Figure 459) is set and no timer is allocated by the requesting channel. As a general guideline the system should be dimensioned in such a way that the timer allocation is always possible. Note: In case of an allocation error the channel forces DOFF to its output pin preventing any damage to occur to the actuator being controlled. This state will not change until bit TAER is cleared. During the timer allocation the channel also provides the TIMERPT pointer which selects a timing value. The valued pointed by TIMERPT is loaded into one of the three counters which counts down until reaching zero. At this time a timeout indication is sent to the requesting channel and the timer is deallocate, moving back to IDLE state. In case of several timer activation requests being issued at the same time, the logic in the Timer Bank will prioritize giving higher priority for the channel with lower number, thus channel zero has higher priority than the others. No flags are set in the case several requests are issued simultaneously unless there are more requests than the number of available timers. In this case the TAER error flag is set in the requesting channel status register. Figure 470 presents a block diagram of the Timer Bank.

Figure 470. Shared timer bank block diagram

23.4.4 Hold-off timer bank

this bank and its interconnections. Figure 471. Hold-off timer bank block diagram

Hold-off Timer Bank. Each reaction channel has its own internal hold-off timer.

23.4.5 Threshold bank and comparator

and the selected threshold value. configuration defined during the module integration.

First comparison: COMP = ADC_DATA ≥ THRESHOLD_VALUE[THRESPT]
Second comparison: COMP = ADC_DATA < THRESHOLD_VALUE[THRESPT + 1] The COMP (comparison result) is routed to the channel selected by the received TAG. Once having received the comparison result the channel takes the appropriate actions in order to execute the modulation mode as defined by the modulation control word.

Figure 472. Threshold bank and comparator block diagram

23.4.6 ADC interface

interface data through the REACM_SINR register. in the case of an overrun condition occurs, indicating that at least one ADC data was lost. (the input data that caused the overrun is lost).

Two consecutive sample data are received from ADC or from CPU.
ADC and CPU sending sample data at the same time (asynchronous events).
Input buffer is holding sample data that are being processed by some channel and a new sample is received from ADC or CPU (normal mode of operation).

Figure 473. ADC interface block diagram

Reaction Module (REACM) RM0029 754/1740 Doc ID 15177 Rev 8

23.4.7 Prescalers

The prescalers provide internal system clock divided signals to be used by internal timers. The reaction module contains two prescalers: a 12-bit prescaler HPRE[11:0] and an 8-bit prescaler TPRE[7:0]. Both are defined in the REACM Timer Configuration Register (REACM_TCR) (see Figure 454 for details). Prescaler HPRE[11:0] is dedicated to the Hold- off timers within the reaction channels. Prescaler TPRE[7:0] is used by the Shared Timer Bank counters. The HPRE[11:0] and TPRE[7:0] prescalers are enabled by HPREN and TPREN bits, respectively, in the REACM module configuration register (REACM_MCR) (see Figure 453). Note that prescalers operate in a similar way regarding their activation. Once the prescaler is enabled by HPREN or TPREN bits in the REACM_MCR, it starts a new count sequence meaning that it is put in reset state and will generate the first prescaler tick after it reaches the programmed value defined by the HPRE or TPRE fields.

23.4.8 Banked mode support

Banked Mode is a reaction module hardware configuration which allows the sharing of reaction channel output pins at the device I/O level. The banked mode architecture allows the stacking of up to four reaction channels. Figure 475 shows the connection between two adjacent channels, CH0 and CH1. The REACM_CHCRn BSB bits are used to control the configuration of channel output logic. Thus if BSB[0] in reaction channel [0] is asserted to 1 and the channel is not in the active state, ch0_a output is switched from CH[0] OUT[0] to CH[1] OUT[0]. If a channel is active, that is, executing a modulation, it takes control over its outputs independent of the BSB bits setting. The banked mode logic is extended to reaction channels CH[2] and CH[3] thus defining a group of four channels. For simplification, Figure 475 shows only channels CH[0] and CH[1] logic. Note: When CHEN = 00 for CH0 (channel disabled), the BSB bits do not influence the channel output, which is driven CH0’s DOFF. Therefore, a banked injector driven by CH1 will have part of its controls off, even if CH1 is enabled. To use BSB of CH0 in this case, an option is to program channel CH0 with CHEN = 11 (channel enabled) and with SWMC = 0 (modulation OFF). In case of using CH2 in banked mode with CH0, the intermediate channel CH1 should also be configured with CHEN different from 00.

Figure 475. Banked mode showing stacking of channels [0] and [1] subsequent channel which are CH[4] and CH[0] respectively.

23.5 Modulation Modes

This section describes the modulation modes provided by the reaction module.

23.5.1 Threshold/Threshold mode

ADC result ≥ [THRESPT]: The reaction channel turns the outputs off by loading LOD[2:0] to the channel outputs.
ADC result < [THRESPT + 1]: The reaction channel turns the outputs on by loading HOD[2:0] to the channel outputs.
[THRESPT + 1] ≤ ADC result < [THRESPT]: The reaction channel keeps the outputs unchanged. Figure 476 indicates the threshold/threshold modulation mode. CH0 CH[1] BSB[0] BSB[1] BSB[2] out[0] out[1] out[2] From channel [2] och0_a och0_b och0_c och1_a och1_b och1_c active BSB[0] BSB[1] BSB[2] out[0] out[1] out[2] active chan chan NOTES: 1. CH[0] should be enabled by CHEN to use BSB. F/F F/F F/F F/F F/F F/F ch0_a ch0_b ch0_c ch1_a ch1_b ch1_c

Figure 476. Threshold/th reshold modulation mode

Feedback values are periodically sampled thus can present gaps on the measured
There is a delay between the sampling of feedback value and the reaction of the

23.5.2 Threshold/Hold-off mode

hold-off timer pointer are indicated by the modulation word in the REACM_MCR register. Threshold / Threshold modulation mode can be used. Figure 477. Threshold/hold-off modulation mode

23.5.3 Limitations on the modulation process

and distance between consecutive modulation pulses. output will be defined by the DOFF field. Note: No error flag is set if this violation occurs. timer control pulses is violated. Figure 478. Limitation on the OFF modulation timing occurs. Note that the channel output is driven to DOFF which causes the modulation to end.

are executed in the appropriate sequence. Figure 479. Early end of Timer Control pulse setting SQER flag. In this case, this SQER flag can be ignored (masked) without prejudice. avoiding unwanted SQER error. detected by the software, thus setting the channel outputs to a safe state defined by DOFF.

a sequence advance event (timeout or threshold, depending on SM).
a new sample is received (no matter if the comparison matches or not).
a hold-off timeout. Module initialization To execute the modulation process the Reaction Module must be initialized with a correct sequence. One method is described as follows: ab d c e timer control signal i time time OFF ON OFF modulation word 0 modulation word 1 modulation word 2 modulation word 3 early end of pulse DOFF Modulation words 3 and 4 are not executed Modulation word 2 is partially executed ab d ce modulation word 0 modulation word 1 modulation word 2 modulation word 3

RM0029 Reaction Module (REACM) Doc ID 15177 Rev 8 759/1740 1. Make sure eTPU channels are at zero, inactive state. 2. Set up eQADC module. 3. Program the Modulation Words. 4. Program the Threshold Bank. 5. Program the Shared Timer Bank. 6. Program the Holdoff Timer Bank. 7. Program Timer Configuration register. 8. Program the Module Configuration register. 9. Program the Channel Router register. 10. Program the Channel Configuration register. 11. Start eTPU channels. It is important to notice that the channel activation, by setting CHEN = 01, should be done after all other registers have been configured and before the input timer control signals are active. Violating this order may lead to errors when the modulation cycle is executed by the channel. Note: If a glitch is introduced in the input timer control pulse, the channel stops to modulate and does not operate during the pulse just after the glitch. The glitch value for wrong operation ranges from 1 system clock to about 5 times the number of channels.

23.6 Monitored modulation

The modulation executed by the reaction channel can be monitored by measuring the width of the PWM pulses provided by the channel. If the pulse becomes too narrow it means that the load impedance is probably too low, thus indicating a possible short circuit. If the PWM pulses become too wide it may indicate an open circuit on the solenoid. The limits for narrow and wide pulses are defined by RANGE_PWD and MIN_PWD registers (see Figure 465 and Figure 466). These values apply to all reaction channels. The PWM pulses are measured by the Hold-off timers within the reaction channels. This is possible only during idle periods of this timer, for example from the moment a hold-off timeout occurs until the maximum threshold is reached when HOD is being used for the channel output pins. During this period the hold-off counter is not used and thus it can measure pulse widths and compare them against predefined limits defined by RANGE_PWD and MIN_PWD registers, as shown in Figure 480. Note: Consider an uncertainty of (+1) in the value MIN_PWD and (MIN_PWD + RANGE_PWD) when calculating the pulse width limits. The Hold-off prescaler contributes to this uncertainty. For a programmed MIN_PWD value, a pulse wider than (MIN_PWD+1) does not set the SCDF flag. For a programmed (RANGE_PWD + MIN_PWD) value, a pulse narrower than or equal to (RANGE_PWD + MIN_PWD + 1) does not set the OCDF flag.

Reaction Module (REACM) RM0029 762/1740 Doc ID 15177 Rev 8 Note: In order to define RANGE_PWD value it is required to consider that the Hold-off timer already measured MIN_PWD, thus actually the maximum allowed pulse width = (MIN_PWD + RANGE_PWD). In other words, RANGE_PWD = (maximum allowed pulse width MIN_PWD). IF MIN_PWD = 0x00 or RANGE_PWD = 0x00 no pulse width is performed. The CHSR SCDF flag does not set if the pulse was finished by disabling the modulation (i.e., eTPU channel = 0 or SWMC = 0) or by disabling the channel, CHEN = 00, even if it ended shorter than MIN_PWD. However this flag can set in some situations that really indicates a short pulse detection but it is the result of some internal condition of the reaction module. The known situations are listed below:

when the shared timer error occurs (TAER flag is set), a narrow pulse can be generated and SCDF flag is set.
when the CHCR CHOFF bit is set, a narrow pulse can be generated and SCDF flag is set. The CHSR OCDF flag only sets when the channel is enabled (CHEN not null) and the eTPU channel signal or SWMC is active too. However, the OCDF flag can set in some cases when the CHOFF bit is set. In this case, this OCDF flag should be disregarded because it is a false indication of the detector. There can be a conflict of resource allocation if the Hold-off timer is used as the timer for the sequencer mode SM = 10. In this case it is not possible to detected minimum or maximum pulse widths thus the monitored modulation is deactivated. Which means the use of the Hold-off timer in the sequence mode has precedence over the monitored modulation. This configuration is not considered an error though, since it may occur during one of the phases of a modulation cycle and return to a sequence mode where the monitored modulation is possible. Thus no flags will be set to signal this conflict condition.

23.7 DMA support

The Reaction Module provides supports for one DMA channel per Reaction Channel. The DMA request signal is controlled by the DMAEN bit in the Channel Configuration Register Figure 458 and by the DMA bit in the Modulation Control Word, Figure 467. If the DMAEN = 1 and the DMA = 1 then a DMA request is issued by the Reaction Channel. Note that the DMA request is deaserted if the DMA done signal is asserted even though the channel is still pointing to the same Modulation Control Word that generated the DMA request. In order for a new DMA request be issued after the DMA done is issued, the Reaction Channel must access a new Modulation Control Word or execute a new modulation cycle controlled by the timer input signal. Figure 483 shows the DMA protocol executed by the Reaction Channel. The DMA request signal is asserted when the Modulation Word 1 is executed by the channel. This signal remains asserted until a DMA done signal is issued by the DMA controller.

Figure 483. DMA Req/Done protocol

23.8 Reset overview

channel output is set to DOFF state and the channel configuration can be changed safely. MODULATION ADDR field in the channel configuration register.

23.9 Reaction module interrupts

several interrupt sources by evaluating the flags MAXL, OCDF, SCDF, TAER, and SQER.

Reaction Module (REACM) RM0029 764/1740 Doc ID 15177 Rev 8

23.9.1 Interrupt sources

There are several sources of interrupts that indicates a faulty condition:

MAXL: maximum ADC result value was reached
OCDF: open circuit detected which indicates an open circuit and thus a potential malfunction in the circuitry controlled by the Reaction Module. Note that differently from the TAER, this flag does not indicate a faulty condition in the channel but in the circuit outside the device.
SCDF: short circuit detected which indicates a short circuit was detected on the off-chip logic controlled by the reaction channel.
TAER: timer allocation error which indicates a required Timer resource was not allocated properly thus leading to faulty operation of the Reaction module.
SQER: sequencer error occurred meaning that the timer input signal was deasserted in a modulation phase with SM != 00.

23.10 Use cases

Figure 484 shows an example of the Reaction Module used to control an Injector solenoid. Note that this is a dual injector which is also called banked injector. Two Reaction channels are used to control this injector. The injector Boost transistor on the top applies a higher voltage in order to minimize the time necessary for the injector to start injecting fuel. Transistors A and B control which injector is active in the injector bank. A sensor resistor is used to feed the current flowing through the solenoid back to the on-chip ADC. The current is sampled by the ADC and the result is sent to the Reaction Module, allowing closed loop control. Note: This injector bank architecture does not allow both injectors to operate at the same time since the sensor in the feedback loop is shared by both injectors.

Figure 484. Boosted Banked Direct Injection with Passive Recirculation reaction channels. Please see Figure 485 for more details.

Figure 486. System level connection in a banked configuration

Reaction Module (REACM) RM0029 768/1740 Doc ID 15177 Rev 8 execute the same type of modulation and use the same threshold values. Note also that the data stored in the Threshold bank in this case is also shared between these channels. This is an important feature of the Reaction Module architecture since it allows the sharing of resources and therefore provides savings in size without compromising the module functionality. Figure 487 shows an example of the required current levels through Injector A and B. In order to generate this waveform, the Reaction Module uses one Modulation Control Word for each one of the five phases of the waveform from A through F. In this example the Module should be configured in the following way: 1. Set the REACM_CHRR0 CHIR[3:0] = 0x0, thus routing eTPU channel 0 to reaction channel 0 2. Set the REACM_CHRR1 CHIR[3:0] = 0x1, thus routing eTPU channel 1 to reaction channel 1 3. Set the REACM_CHRR0 ADCR[3:0] = 0x0, th us routing ADC TAG 0 to reaction channel 0 4. Set the REACM_CHRR1 ADCR[3:0] = 0x0, th us routing ADC TAG 0 to reaction channel 1 5. Program Modulation Word Control bank according to Figure 488 6. Program Shared Timer Bank REACM_STBK for addresses from 0 through 3 with timing intervals related to the duration of phases A,B,C and D respectively. 7. Program appropriate values in the Threshold Bank. Since threshold-threshold modulation is to be used in this example, four pairs of values should be provided for phases A,B,C and D respectively. Each pair corresponds to one address of the REACM_THBK starting at address 0x0400. 8. Program configuration registers for bot h channels, REACM_CHCR0/1. The parameters are DOFF[2:0] which defines the OFF state of the channel outputs and the MODULATION_ADDR = 0x0, which defines the address of the Modulation Control word. It is assumed that the Modulation Word zero is the first word to be accessed by both channels. Since four Modulation words will be used the addresses will be incremented by the reaction channel as needed, thus only the address for the first word is required. Note that MODULATON_ADDR = 0x0 points to the first Modulation Word in the Modulation Word Bank. 9. Program the prescalers HPRE and TPRE in the REACM_TCR register. Also enable the prescalers by setting the TPREN and HPREN bits in the REACM_MCR register. 10. Enable channels CH0 and CH1 to start the modulation sequence by programing field CHEN = 01 on REACM_CHCR1/0 registers. At this time the Reaction channel CH0 accesses the Modulation Control word zero and switches to ON state as defined by the data stored HOD[2:0] field. Up to this point any activity in the eTPU channel or income ADC result is ignored by the Reaction module. After CHEN field is programed, the reaction channels wait until a timer window is initiated by eTPU for the modulation process to start.

Figure 487. Modulation phases as well. The modulation starts when the eTPU channel time window switches to ON state.

LOOP = 0
The initial value should be HOD (IOSS = 1)
Threshold-Threshold modulation mode is obtained with MM = 00
This phase ends when the threshold value I0 is achieved (SM = 11)
Necessary to have HOD = 111 for boosted operation and sensor active, LOD setting is not important in this case since it is not used
I0 is read from Threshold Bank by using THRESPT = 0x0 that points to address 0 of this bank
I1 is read from Threshold Bank by using (THRESPT + 1) = 0x1
Hold-off timer is not used, therefore HDOFFPT can have any value (X) At point b, phase B is initiated by the threshold being achieved from phase A. CH0 increments the Modulation Word address to MODULATION_ADDR = 0x1 and the second C ab c e d timer control signal Current in Injector time time OFF ON OFF AB Dmodulation word 0 modulation word 1 modulation word 2 modulation word 3 eTPU

levels I2 and I3 during a period defined by TB. Please see Figure 488. TD delay is measured. The channel outputs are kept in the OFF state. this address is not necessarily 0x0.

23.10.1 Advancing modulation phase on a threshold level

The Modulation Phase may be set to advance when a specific threshold value is reached. next modulation phase, thus making sure that the solenoid had the fastest opening speed. Figure 488. Modulation words for injector application

Figure 489. Advancing modulation phase on a threshold level

Initially at time a the reaction channel output is loaded with HOD[2:0] as indicated by IOSS value, both fields of modulation word 0.
If ADC result ≥ [THRESPT] the reaction channel turns the outputs off by loading LOD[2:0] to the channel outputs and advance to the next modulation cycle at time b. Note: The advance on threshold, SM = 11, is intended to be used with IOSS = 1, thus the advance occurs when the level from the ADC is greater or equal to the value pointed by THRESPT. IOSS = 0 is a reserved value for this bit in this configuration and should not be used.

23.10.2 Controlling the loop function

Modulation Words, in this case Modulation Word 0 and Modulation Word 1. Figure 490. LOOP function used within a modulation cycle

23.10.3 Banked mode

Figure 491 describes the interconnection of four channels controlling two injector banks. channels [0] and [1] and channels [2] and [3]. Figure 491. Four channels controlling two injector banks in banked mode

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 773/1740

24 Enhanced Time Processing Unit (eTPU2)

24.1 Information specific to this device

This section presents device-specific parameterization and customization information not specifically referenced in the remainder of this chapter.

24.1.1 Device-specific features

Single engine, 32 channel
SCM size: 14 KB, no ECC support
SDM size: 3 KB, no ECC support
Nexus class 1 support
Channels 24 to 29 input sources are selected via SIU IMUX (see Section 16.6.22: IMUX Select Register 8 (SIU_ISEL8))
Channel outputs can be serialized through via onboard DSPI
Channel outputs 26 to 31 can be used to trigger the eQADC
TCRCLK and Channel 0 are connected together internally on the 176-pin LQFP package

24.2 Introduction

eTPU is an intelligent, semi-autonomous co-processor designed for timing control. Operating in parallel with the Host CPU, the eTPU processes instructions, real-time input events, performs output waveform generation, and accesses shared data without Host intervention. Consequently, for each timer event, the Host CPU setup and service times are minimized or eliminated. High-level assembler, compiler and documentation allows customers to develop their own functions on the eTPU. eTPU is an enhanced version of the TPU module. Although there is no compatibility at microcode level, eTPU maintains several features of older TPU versions, making it easy to port older applications, at the same time adding several features listed in Section , eTPU enhancements over TPU3. This document also includes the new features belonging to the version of the eTPU known as eTPU2. The new features are summarized in Section , eTPU2 enhancements over eTPU. eTPU architecture aims at high resolution timing capabilities. From a system perspective, high resolution timing is limited by Host CPU overhead required for servicing timing tasks such as period measurement, pulse measurement, pulse width modulated waveform generation, etc. On the eTPU, high resolution timing is achieved by three main capabilities:

Reduced latency: pin actions are immediate.
Reduce or eliminate host interrupt service time.
Double action channel capability reducing the channel request rate. eTPU provides higher resolution than the Host CPU can achieve and creates no Host overhead for servicing timing tasks.

Enhanced Time Processing Unit (eTPU2) RM0029 774/1740 Doc ID 15177 Rev 8 Latency is the interval from occurrence of an event to the start of event servicing. eTPU can service its own events without interrupting the Host. There are two types of timing events:

Input pin transition
Selected Time Base match, that is, a selected Time Base counter reached or exceeded a preprogrammed value Service time is the time spent servicing an event. In general, in microcontrollers the service time is constrained because the instruction set is not optimized for time function synthesis. The eTPU instruction set is optimized, so that time functions can be implemented with much fewer instructions than the Host CPU. Instructions execute faster, service time is reduced and program memory compacted. Instructions executed by the eTPU are connected directly to the eTPU timing hardware and allow parallelism of hardware related actions.

24.2.1 Overview

Figure 492 shows a top-level eTPU block diagram.

Figure 492. eTPU block diagram (single-engine) interface with external time bases through the STAC bus. is accessed by Host and the microengine. Bus Interface Unit (BIU)—allows Host to access eTPU registers, SCM and SPRAM.

Enhanced Time Processing Unit (eTPU2) RM0029 776/1740 Doc ID 15177 Rev 8 Each I/O signal pair is associated with a dedicated Channel, which provides hardware for input signal processing and output signal generation, in relationship with selected Time Bases. The eTPU, as a microprocessed subsystem, works much like a typical real-time system: it runs microengine code from instruction memory (SCM) to handle specific events, accessing data memory (SPRAM) for parameters, work data and application state info; events may originate from I/O Channels (due to pin transitions and/or time base matches), Host CPU requests or inter-channel requests; events that call for local eTPU processing activate the microengine by issuing a Service Request. The Service Request microcode may set an interrupt to the Host CPU. I/O channel events cannot directly interrupt the Host CPU. Each channel is associated with a Function, which defines its behavior: the Function is a software entity consisting, within the eTPU, of a set of microengine routines that attend to Service Requests. The Function routines are also responsible for Channel configuration. Function routines reside in SCM, which may contain several Functions. A Function may be assigned to several Channels, but a Channel can be associated with just one Function at a given moment. The association between Functions and Channels is defined by Host CPU, and is explained in detail in Section 24.5.1, Functions and threads. eTPU hardware supplies resource sharing features that support concurrency:

a hardware Scheduler dispatches the Service Request microengine routines based on a set of priorities defined by the Host CPU. Each Channel has its associated priority;
a Service Request routine cannot be interrupted until it ends. This sequence of uninterrupted instruction execution is called a Thread.
Channel-specific context (registers and flags) is automatically switched between the end of a Thread and the beginning of the next one.
SPRAM arbitration, a dual-parameter coherency controller and semaphores can be used to ensure coherent access to eTPU data shared by both eTPU engines and Host CPU. eTPU engine The eTPU engine consists of two 24-bit time bases, 32 independent timer channels, a task scheduler, a microengine, and a Host interface and 32-bit Shared Parameter RAM (SPRAM). In dual-engine implementations of the eTPU, SPRAM is used for both eTPU engine’s data storage and for passing information between the eTPU engines and the host CPU. Figure 493 shows the block diagram for the eTPU engine.

Figure 493. eTPU engine block diagram eTPU engines 1 and 2 are sometimes called eTPU 1 and eTPU 2 throughout this document. to/from TCR1 or TCR2 in accordance to the Red Line bus specification. For further details refer to Section 24.5.6, Time Bases.

Enhanced Time Processing Unit (eTPU2) RM0029 778/1740 Doc ID 15177 Rev 8 eTPU timer channels The eTPU engine has 32 independent channels, each corresponding to an Input/Output signal pair. The channels time resolution is 24 bits, and are all identical. Each channel consists of logic which supports two events and output controls. The event logic contains two 24-bit capture registers, two 24-bit match registers, greater-equal and equal-only comparators. Supporting two events enables many combinations of double- action functions (for example the channel can handle two events with a single microcode service). The channel configuration can be changed by the microengine on the fly. Each channel can perform double capture, double match and other capture-match combinations. Channel modes available can do ordered or unordered match. Some modes are also provided that can block one match by the occurrence of the other. Service request can be generated on one or both of the match events. Input signal can be separated from output signal in each channel. They can, optionally, be combined in a single I/O pin driver. An output buffer enable signal, controlled by microcode, is provided for this case. Digital filters are provided for the input signals, with distinct filtering modes available. Each channel can use any time base or angle counter for either match or capture operation. For example, a match on TCR1 can capture the value of TCR2. The channels can request service from the microengine due to recognized pin transitions (input events) or timebase matches. The eTPU channels also support the basic single-action operations found on TPU3 functionality with the exception that time resolution is 24 bits. Channel configuration combinations:

Single input capture, no match (TPU3 functionality).
Single input capture with single match timeout (TPU3 functionality).
Single input capture with double match timeout with several double match submodes.
Double input capture with single or double match timeout with several double match submodes.
Single output match (TPU3 functionality).
Double output match with several double match submodes.
Input-dependent output generation. The double match functionality has various combinations for generation of service request and determining pin actions. For more details refer to Section 24.5.5, Enhanced Channels. In addition to the predefined channel configurations above, the user can also program its own channel configuration, defining how input captures, matches and service-requests are related. Host interface The Host interface allows the Host CPU to control the operation of the eTPU. The Host CPU must initialize the eTPU by writing to the appropriate Host interface registers to assign a Function and priority to each channel. In addition, the Host writes to the Host Service Request and channel configuration registers to further define Function operation for each initialized channel. Refer to Section 24.5.2, Host interface for a detailed description.

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 779/1740 When the SCM is implemented by RAM, the Host must first initialize it with the proper microcode program prior to enabling any eTPU Function, and then enable eTPU access (which also disables Host access). Shared parameter RAM (SPRAM) The SPRAM works as data RAM which can be accessed by the Host CPU and up to two eTPU engines. This memory is used for information transfer between the Host CPU and the eTPU, as data storage for the eTPU microcode program or for communication between the two eTPU engines. SPRAM width is 32 bits, and is accessible by the Host as byte, 16-bit or 32-bit wide. eTPU can access it as full 32 bits, lower 24 bits or upper byte (8-bit). The host can also access the SPRAM space mirrored in other area with Parameter Signal Extension (PSE). Parameter Signal Extension accesses differ from the usual host accesses to the original SPRAM area as follows:

Writes are effective only to the lower 3 bytes of a word: the word’s most significant byte is kept unaltered in SPRAM.
Reads return the lower 3 bytes of a word sign-extended to 32 bits, i.e.: the most significant bit of the word s 2nd most significant byte is copied in all 8 bits of the most significant read byte. Each eTPU channel can be associated with a variable number of parameters located in the SPRAM, according to its selected Function. In addition, the SPRAM can be fully shared between two eTPU engines, enabling direct communication between them. High flexibility of the SPRAM utilization is achieved as follows:
Each channel has a programmable base address pointing to the address of its first parameter with two parameter granularity. This way the SPRAM can be partitioned according to the actual function needs.
The microcode can access the first 128 parameters of the selected channel in channel relative access mode.
Each engine can access all the SPRAM address space in indirect addressing mode. Blocks of data are easily transferred using stack operation.
Absolute addressing mode can access the first 256 parameters (TPU3 functionality), implementing a shared pool of parameters holding global variables. In the Host address space each parameter occupies four bytes. eTPU usage of the upper byte is achieved by having a 32-bit P register which can access the upper byte, the lower 24 bits or all the 32 bits. The microcode can switch between access sizes at any time. Each Function may require a different number of parameters. During the eTPU initialization the Host has to program channel base addresses, allocating proper parameters for each channel according to its selected Function. Scheduler Out of reset, all channels are disabled. The Host CPU makes a channel active by assigning it one of three priorities: high, middle, or low. The Scheduler determines the order in which channels are serviced based on channel number and assigned priority. The priority mechanism, implemented in hardware, ensures that all requesting channels are serviced. For additional details refer to Section 24.5.3, Scheduler.

Enhanced Time Processing Unit (eTPU2) RM0029 780/1740 Doc ID 15177 Rev 8 Microengine eTPU microengine is a simple VLIW implementation that performs each instruction in a microcycle of two system clocks, while prefetching the next instruction through an instruction pipeline. Instruction execution time is constant unless it gets wait states from the SPRAM arbitration. Two eTPU engines share code memory without having any performance degradation by interleaving their accesses (the Shared Code Memory has one-clock access time). Instruction width is 32 bits. The microengine instruction set provides basic arithmetic and logic operations, flow control (jumps and subroutine calls), SPRAM access, and Channel configuration and control. The instruction formats are defined in such a way that allow particular combinations of two or three of these operations with unconflicting resources to be executed in parallel in the same microcycle. Microengine has also an independent Multiply/Divide/MAC unit that performs these complex operations in parallel with other microengine instructions. Channel functionality is tightly integrated to the instruction set through Channel Control operations and conditional Branch operations, which support jumps/calls on Channel- specific conditions. This allows quick and terse Channel configuration and control code, contributing to reduced service time. Detailed description can be found in Section 24.5.8, Microengine. Single vs. dual eTPU engine system An eTPU implementation can include one or two eTPU engines. The number is engines is specific to the microcontroller design and cannot be changed. Note: The SPC564A74xx, SPC564A80xx eTPU has one eTPU2 engine. On devices with two eTPU engines, the eTPU parameter RAM (SPRAM), code memory (SCM) and Bus Interface Unit (BIU) are shared by both engines, enabling processor core- to-eTPU communication and eTPU engine-to-engine communication. In dual-engine eTPUs the shared BIU includes coherency logic which supports dual- parameter (8 bytes) coherency in transfers between the processor core and eTPU, using a temporary parameter area within the SPRAM. More details on this can be found on Section 24.5.4, Parameter sharing and coherency.

24.2.2 Features

The eTPU includes these distinctive features:

Up to 32 channels per eTPU engine—each channel is associated with an I/O signal pair. – Enhanced input digital filters on the input pins for improved noise immunity. The eTPU digital filter can use 2 samples, 3 samples or work in continuous mode. – Identical, orthogonal channels, except for channel 0: each channel can perform any time function. Each time function can be assigned to more than one channel at a given time, so each signal can have any functionality. Channel 0 has the same

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 781/1740 capabilities of the others, but can also work with special Angle Counter logic (see below). – Link Service Request allows activation of a Channel function by request of another channel, even between eTPU engines. – Host Service Request allows activation of a Channel function by Host CPU request – Each channel has an event mechanism which supports single and double action functionality in various combinations. It includes two 24-bit capture registers, two 24-bit match registers, 24-bit greater-equal and equal-only comparators.

2 independent 24-bit time bases for channel synchronization: – First time base clocked by system clock with programmable prescaler division from 1 to 512 (in steps of 2), or by output of second time base prescaler. – First time base can also be clocked by external signal with programmable prescaler division of 1 to 256. – Second time base clocked by external signal with programmable prescaler division from 1 to 64. – Second time base external clock source can be replaced by system clock divided by 8. – Both time bases can be exported or imported via Shared Time and Counter) bus. – Second time base counter can work as an Angle counter, enabling angle based applications to match angle instead of time. – Second time base can also be used as a pulse accumulator gated by external signal.
Event-Triggered VLIW processor (microengine): – 2 stage pipeline implementation (fetch and execution), with separate instruction memory - SCM - and data memory - SPRAM (Harvard architecture) – Fixed-length instruction execution in two system clock microcycle – Interleaved SCM access in dual eTPU engine avoids contention in time for instruction memory – SCM address space of up to 16K positions (64 Kbytes) – SPRAM with interleaved access in dual eTPU engine avoids contention for data memory – SPRAM address space of up to 8 Kbytes (both engines). – Instruction set with embedded Channel support, including specialized Channel control subinstructions and conditional branching on Channel-specific flags. – Channel-oriented addressing: channel-bound address mode with Host configured Channel Base Address allows channel data isolation, independent of microengine application code. – Channel-bound data address space of up to 128 32-bit parameters (512 bytes) – Global parameter address mode allows access to common Channel data of up to 256 32-bit parameters (1024 bytes) – Support for indirect and stacked data access schemes. – Parallel execution of: data access, ALU, Channel control and flow control subinstructions in selected combinations. – 32-bit microengine registers and 24-bit resolution ALU, with 1 microcycle addition and subtraction, absolute value, bitwise logical operations on 24-bit, 16-bit, or byte

Enhanced Time Processing Unit (eTPU2) RM0029 782/1740 Doc ID 15177 Rev 8 operands; single-bit manipulation, shift operations, sign extension and conditional execution. – Additional 24-bit Multiply/MAC/Divide unit which supports all signed/unsigned Multiply/MAC combinations, and unsigned 24-bit Divide. The MAC/Divide unit works in parallel with the regular microcode commands.

Resource sharing features support channel sharing of channel registers, memory and microengine time: – Hardware Scheduler works as a “task management” unit, dispatching event service routines by predefined, Host-configured priority. – Automatic Channel context switch when a “task switch” occurs, i.e., one Function Thread ends and another begins to service a request from other Channel: Channel-specific registers, flags and parameter base address are automatically loaded for the next serviced channel. – Individual channel priority setting in 3 levels: high, middle and low. – Scheduler priority scheme allows calculation of worst-case latency for event servicing and ensures servicing all channels by preventing permanent blockage. – SPRAM shared between Host CPU and both eTPU engines, supporting communication either between Channels and Host or inter-channel. – Hardware implementation of 4 Semaphores supports resource sharing between both eTPU engines. – Hardware semaphores directly supported by the microengine instruction set. – Dual-parameter coherency hardware support allows atomic (to host) access to 2 parameters by microengine(s) in back-to-back accesses. – Coherent dual-parameter controller allows atomic (to microengines) accesses to 2 parameters by the host.
Test and Development support features: – Nexus class 3 debug support (optional, associated with the eTPU-Nexus Block NDEDI). – Software breakpoints. – Debug interface supporting single-step execution, forced microinstruction execution, Hardware breakpoints and watchpoints on several conditions. – SCM (code memory) continuous signature-check built-in self test (MISC, or Multiple Input Signature Calculator), runs concurrently with eTPU normal operation. eTPU enhancements over TPU3
32 orthogonal channels with enhanced functionality. Full support for double action with double match and double transition submode combinations.
Input and Output features separated in channel logic and microinstructions, allowing input and output signals to be processed separately or combined.
Increased time resolution and execution unit to 24 bits
Increased linear code memory, shared by two eTPU engines, configurable up to 16K positions (64 Kbytes)
Increased Parameter RAM address range (8 Kbytes each engine) and width (32 bits per parameter). The Parameter RAM can be dynamically allocated to support variable

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 783/1740 number of parameters for each channel. Each channel can have access to at least 256 parameters.

The Parameter RAM is fully shared by two eTPU engines (SPRAM), supporting direct inter-engine communication with the help of hardware semaphores.
Enhanced arithmetic operations, including add/subtract with carry, absolute value, multiple shift and rotate, conditional execution with variable operand widths
Enhanced logic operations, including bitwise operations (and, or, xor) and bit manipulation, with conditional execution. Support for read-modify-write of any bit in the SPRAM.
Hardware for Multiply/MAC/Divide, running in parallel to execution of other operations. The 24-bit divide result is available after 13 other unrelated instructions. Multiplication supports any data width of both operands (8, 16 or 24 bits), signed or unsigned. A 24x24 Multiply/MAC result is available after four other unrelated instructions. A 24x8 Multiply/MAC result is available after one other unrelated instruction.
Supports export/import of time bases from other sources through the real time bus (STAC - Shared Time and Counter bus). This internal bus is used for sharing real time data between multiple peripherals.
Contains angle clock hardware, supported by microcode, which can provide a 24-bit angle bus instead of time bus. This feature enables the eTPU to run angle based engine control applications.
More interrupt types. Each eTPU channel can generate a data transfer request interrupt, in addition to regular interrupts, and one global exception interrupt. Data Transfer requests can be used either as interrupt sources or DMA requests. This feature takes advantage of DMA peripherals which offload the Host. Interrupt Overflow status is also provided.
Improved visibility to the Host (pin states, time bases, serviced channel)
An edge case of priority inversion on TPU3 Scheduler was resolved.
Supports channel link requests between eTPU engines

Enhanced Time Processing Unit (eTPU2) RM0029 784/1740 Doc ID 15177 Rev 8 eTPU2 enhancements over eTPU

TCR1, channel logic and digital filters (both channel and TCRCLK) now have an option to run at divisions of full system clock speed, besides system clock / 2.
Channels support unordered transitions: transition B can now be detected before transition A. Related to this enhancement, TDLA and TDLB can now be independently negated by microcode.
Added a new User Programmable Channel Mode: the blocking, enabling, service request and capture characteristics of this channel mode can be programmed via microcode.
Microinstructions now provide an option to issue Interrupt and Data Transfer requests selected by CHAN. They can also be requested simultaneously at the same instruction.
Channel Flags 0 and 1 can now be tested for branching, besides selecting the entry point.
Channel digital filters can be bypassed.
Scheduler priority-passing mechanism can now be disabled.
New Watchdog mechanism kills threads over a programmable timeout.
New counter allows microengine load information collection for performance analysis
Channels 1 and 2 (besides channel 0) can now be selected to control the EAC.
Timebase prescalers are now reset when the GTBE input is negated, guaranteeing synchronization with eMIOS in all cases.
New MISC flag indicates when an SCM signature calculation round is completed. This allows measuring of the average MISC scan period in a real application situation.
New channel TCCEA flag allows continuous capture even after TDLA is set, making it fully compatible with TPU behavior.
New branch condition PRSS tells the pin state at the time when a channel (match or transition) service request occurred.
MRLEA/B can now be negated independently by microcode.
New engine Relative address mode allows a function to access SDM address space common to one engine, but distinct between engines.
Error Correction support for Code (SCM) and Data (SDM) memories (available on selected MCUs).
All changes above are upward compatible with the classic eTPU, so that legacy object code (both Host and microcode) runs on eTPU+ and eTPU2 without modification.

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 785/1740

24.2.3 Modes of operation

The eTPU2 is capable of working in the following modes:

User Configuration Mode User has the ability to program the eTPU Cores with User Time Functions, having access to the Shared Code Memory (SCM).
User Mode User does not access the eTPU Shared Code Memory: – Use of predefined eTPU Functions – No need for eTPU Core programming ability
Debug Mode User debugs eTPU code, accessing special Trace/Debug features via Nexus interface: – Hardware breakpoint/watchpoint setting – Access to internal registers – Single-step execution – Forced instruction execution – Software breakpoint insertion and removal.
Module Disable Mode eTPU engine clocks are stopped through a register write to ETPU_ECR bit MDIS, saving power. Input sampling stops. eTPU engines can be in Module Disable Mode independently. Module Disable Mode stops only the engine clock, so that the Shared BIU, and Global Channel registers can be accessed, and interrupts and DMAs can be cleared and enabled/disabled. An engine only enters Module Disable Mode when any currently running thread is finished (see Section 24.5.1, Functions and threads).
Stop Mode Stop Mode is entered when eTPU answers device stop request assertion with stop acknowledge. The definition of which clocks are stopped is made at the MCU level, which defines whether or not registers can be accessed, interrupts and DMA requests cleared. These modes are loosely selected: there is no unique register field or signals to choose between them. Some features of one mode can be used with features of other mode(s). More on this subject can be found on Section , eTPU mode selection, below. Note: Throughout this document, an engine is said to be “stopped” if it is either in Module Disable mode or Stop mode. eTPU mode selection User and User Configuration are the production operating modes, and differ from each other only in access to SCM. User programmability is only possible with a RAM SCM. On chips where the SCM is implemented as a RAM, it can either be accessed directly from IP-Bus for code loading, or for software breakpoint setting. On chips with a ROM SCM, an internal SCM Emulation RAM may be used, depending on the specific MCU implementation, to replace ROM SCM for test or debug purposes. SCM Emulation RAM is selected in an MCU-specific way. For more details, see Section , SCM emulation. For more information on SCM access, Debug and Test features, refer toSection 24.5.10: Test and Development Support.

may be used with Nexus implementation blocks to provide Nexus class 3 debug features. The use of eTPU-NDEDI interface and Nexus implementation is MCU-dependent. both eTPU engines to enter in stop mode, and then asserts the stop acknowledge line. stop request is negated and VIS = 1, eTPU will leave Stop Mode as soon as VIS = 0. even if the other leaves it.

24.3 External signal description

24.3.1 Overview

a dual-engine system. These signals are described in Table 430. buffer enable signal for each channel, controlled by microcode. Section 24.5.7, EAC – eTPU angle counter, for proper use of this signal. Table 430. eTPU signal properties

24.3.2 Detailed signal descriptions

Specify the logic level output to the signal when there is a match or a transition.
Immediately force a logic level. The output signal may also be forced to a logic level, independently of the output value from the channel logic, by one of the four (each engine) output disable input signals ipp_ind_etpuodis (see Section , ipp_ind_etpu_odis_[1|2]([0 – 3]) eTPU Channel Output Disable Signals). The output signal driver may be, depending on MCU integration, enabled by the output buffer enable internal signal that comes from eTPU. In this case, the output buffer can be controlled by microcode, through a specific microinstruction field. There is one independent output buffer Enable signal for each channel. For more information on output control from microcode, refer to Section , Transition detection and pin action control. ipp_ind_etpuch_[1|2]([0 – 31]) — eTPU Channel Input Signals Each channel input signal is associated with a channel. The microcode can directly control the effect of the transition edge. Each channel can be programmed to sense a transition when a rising and/or falling edge is detected. The channel logic can also process two transition events, and relate these events to each other and to other programmed timer events. The edge sensitivities of the two transition events are configured independently by microcode. For further information refer to Section 24.5.5, Enhanced Channels, and Section , Transition detection and pin action control. Each channel input signal has an associated synchronizer made of two flip-flops sampling the signal on every other system clock (u), followed by a digital filter. This digital filter can work in three submodes, whose purpose is to filter out noise pulses that have width less then a programmed value of system clocks, preventing these transitions from being input to the transition detect logic. The synchronizer and digital filter are guaranteed to pass pulses that are greater than a programmed value. All channel input filters in one engine work on the ipp_ind_etpu_odis_2(0) to ipp_ind_etpu_odis_2(3) Input eTPU engine 2 output disable signals — MCU dependent ipp_ind_tcrclk_2 Input Clock/gate for eTPU engine 2 TCR counters; entry of the tooth signal in Angle Mode — MCU dependent 1. Value 0 refers to the reset value of the signal. Hi-Z refers to the state of the pads, if controlled by the eTPU output buffe r Enable signals, i.e., eTPU output buffer Enable resets in negated state.

Table 430. eTPU signal properties (continued) u. Sampled on the T4 microcycle phase, see Section 24.7.1, Microcycle and I/O timing .

operations TCRCLK can be used to get the tooth transition indications in Angle Mode. channel input filters, through the field ETPU_TBCR[TCRCF]. TCRCLK signal digital filter (see Section 24.5.7, EAC – eTPU angle counter). The output disable channel groups are defined in Table 431. In a dual-engine eTPU there are 8 output disable signals for the 64 channels. Table 431. Output disable channel groups

The ETPU2 output_disable signals ipp_ind_etpu_odis_1(0 to 3) are connected to the EMIOS channel

_flags_ (channel 11 to 8) respectively.

24.4 Memory map/register definition

Section 24.5, Functional description, where those features are explained in detail.

24.4.1 Memory map

shown may have their own reserved address areas. Note: For SPC564A74xx, SPC564A80xx, the eTPU2 base address is 0xC3FC_0000. determined by the register ETPU_SCMOFFDATAR. Table 432. High level memory map

Reserved addresses must not be used. Access to these memory positions complete with 0-wait-states, but may cause
Actual sizes of SCM and SPRAM are MCU-dependent.
Parameter Sign Extension access area, see

SCM access is available only when bit VIS = 1 on register ETPU_MCR, under certain conditions (see Section ,

ETPU_MCR – eTPU Module Configuration Register ). Table 433. Detailed memory map

Table 433. Detailed memory map (continued)

This register is not implemented in some MCUs; see Section , ETPU_SCMOFFDATAR – eTPU SCM Off-range Data
The actual SPRAM size is MCU-dependent.
Parameter Sign Extension access area, see

Enhanced Time Processing Unit (eTPU2) RM0029 794/1740 Doc ID 15177 Rev 8 4. The actual SCM size is MCU-dependent. When the size not the maximum, the unused SCM address range returns the value of the register ETPU_SCMOFFDATAR. 5. SCM access is available only when bit VIS = 1 on register ETPU_MCR, under certain conditions (see Section , ETPU_MCR – eTPU Module Configuration Register ). SCM can only be written in 32-bit accesses.

24.4.2 System configuration registers

also used for configuring the SCM (Shared Code Memory) operation and test. Figure 494. ETPU_MCR Register

2 ILF1 ILF2

00 S C M S I Z E

Table 434. ETPU_MCR field description MGE2, ILF1, ILF2 and SCMMISF. 0: Keep Global Exception request and status bits MGE1, MGE2, ILF1, ILF2 and SCMMISF as is. GEC works the same way in Module Disable Mode.

1: Global Exception requested by SDM read error is pending. 0: No Global Exception pending because of SDM read error. Exception. This bit is cleared by writing 1 to GEC. 0: No Global Exception pending because of Watchdog timeout. Exception. This bit is cleared by writing 1 to GEC. 0: No Global Exception pending because of Watchdog timeout. coded in an SPRAM status parameter, for instance. This bit is cleared by writing 1 to GEC. 0: No microcode-requested Global Exception pending. coded in an SPRAM status parameter, for instance. This bit is cleared by writing 1 to GEC. 0: No microcode-requested Global Exception pending. bit is cleared by host writing 1 to GEC. See Section , Illegal Instructions, for more details. 1: Illegal Instruction detected by eTPU A. 0: Illegal Instruction not detected. bit is cleared by host writing 1 to GEC. See Section , Illegal Instructions, for more details. 1: Illegal Instruction detected by eTPU B. 0: Illegal Instruction not detected.

cleared by writing 1 to GEC. 1: Global Exception requested by SCM read error is pending. 0: No Global Exception pending because of SCM read error. other transfer sizes are used. the SCM memory scan, either if the signature matches or not. Section 24.5.10: Test and Development Support, for more details. 0: Signature mismatch not detected. This bit is cleared when Global Exception is cleared by writing 1 to GEC.

Development Support, for more details. 0: MISC operation disabled. The MISC logic is reset to its initial state. 0 to 1, disabling the MISC operation. VIS bit turns SCM visible to the IP-Bus and resets MISC state (but SCMMISEN keeps its value). 1: SCM is visible to the slave bus. MISC state is reset. protected and reads are meaningless. written to SCM is unpredictable if other transfer sizes are used. GTBE enables time bases in both engines, allowing them to be started synchronously. 1: time bases in both engines are enabled to run. 0: time bases in both engines are disabled to run. When GTBE is turned off with Angle Mode enabled, the EAC must be reinitialized before GTBE is turned on again. The EAC reinitialization procedure is described in Section , Restarting angle logic.

Engine is stopped in Module Disable or Stop Modes, but access es to registers in Stop Mode is defined in the MCU level.
Engine is stopped in Module Disable or Stop Modes, but access es to registers in Stop Mode is defined in the MCU level.

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 799/1740 ETPU_CDCR – eTPU Coherent Dual-Parameter Controller Register eTPU Shared Parameter RAM (SPRAM) can be accessed by the MCU’s processor core and the eTPU’s microengine(s) concurrently. In general, there is no guaranteed order by which a group of parameters is accessed, which may lead to a lack of internal consistency if two or more related parameters are read when only part of them is updated. The eTPU provides mechanisms to guarantee parameter coherency, including the use of transfer service thread mechanism. and a mailbox (or “software semaphore”) mechanism. A third mechanism, the Coherent Dual-parameter Controller (CDC), is also provided. It is used by the processor core to coherently transfer pairs of parameters between a parameter buffer located on SPRAM and locations on SPRAM where parameters are accessed directly by the channels. Coherency is guaranteed by SPRAM access arbitration. Although limited to two parameters only, it has low latency and wastes no microengine resources. This register is used to configure and initiate CDC transfers between the parameter buffer area and the channel parameter area. 1. The host asserts the STS bit to start the data transfer. 2. CDC contends for the SPRAM and starts the transfer. 3. When the data transfer is complete, STS returns to 0. The host receives wait-states for writing STS = 1 while CDC contends for SPRAM and during the transfer. 4. The write access ends when CDC finishes the transfer. The host receives wait-states during the CDC transfer. Note: If the host writes to the ETPU_CDCR with STS = 0 or does not write the STS bit, the CDC transfer does not occur. CDC programming can be summarized as follows: 1. If it is a write transfer, i.e., from host to channel, write the two parameters into temporary area. 2. Write the ETPU_CDCR with STS = 1 and the remaining CDC programming parameters: parameter width (32 or 24 bits, field PWIDTH), transfer direction (read or write, field WR), temporary parameter area base address (field PBBASE), and the absolute addresses of the parameters to be transferred (concatenation of the fields CTBASE and PARAM0/1). 3. If it is a read transfer, i.e., from channel to host, read the two parameters from the temporary area into host memory/registers.

Figure 495. ETPU_CDCR Register Table 435. ETPU_CDCR field description Section , Coherent Dual-parameter Controller (CDC)). Therefore, host always reads STS as 0. 1: (write) starts a coherent transfer. 0: (write) does not start a coherent transfer. Address. The microengine absolute (word) address of the first parameter in the buffer is PBBASE*2. This bit selects the width of the parameters to be transferred between the PB and the target address. 1: Transfer 32-bit parameters. All 32 bits of the parameters are written in the destination address. 0: Transfer 24-bit parameters. The upper byte remains unchanged in the destination address.

compared to the signature generated by the MISC.

The host loads the ETPU_MISCCMPR with the expected value to be found at the end
The host starts signature calculation by writing bit SCMMISEN = 1 in the ETPU_MCR.
After last SCM position is read, MISC compares the value in the signature accumulator
If no mismatch is found, MISC repeats the procedure automatically.

PARAM0} is the first transferred. This bit selects the direction of the coherent data transfer. 1: Write operation. Data transfer is from the PB to the selected parameter RAM address. 0: Read operation. Data transfer is from the selected parameter RAM address to the PB. PARAM0} is the first transferred.

Figure 496. ETPU_MISCCMPR Register comes from the ETPU_SCMOFFDATAR. error and can write on unspecified mirror addresses, so they should be avoided. The reset value is MCU dependent. Table 436. ETPU_MISCCMPR field description See Section , SCM Test – Multiple input signature calculator.

The reset value depends on the MCU, and is usually 0xf3775ffb, an instruction that clears MRLEs, MRLs and TDLs,

disables channel service requests, ends the thread and generates an illegal instruction Global Exception. Figure 492. ETPU_SCMOFFDATAR Register Table 437. ETPU_SCMOFFDATAR field description See Section , SCM off-range data.

are programmed independently in each engine.

0 S T F 0000 H L T F 000

The MDIS reset value is MCU-dependent. Please consult the Reference Manual of the specific MCU.
Engine may go to Debug state (halted) soon after reset, depending on the NDEDI configuration.

Figure 492. ETPU_ECR Register Table 438. ETPU_ECR field description Section , Ending current thread – END). microengine is in TST, halted, stopped, or idle (no thread executing). it negates as soon as the end begins execution.

microcode is executing, the eTPU will stop when the thread is complete. 1: Commands engine to stop its clocks. Channel Registers and SPRAM can be accessed normally. STF_1 and STF_2 mean STF bit from engine 1 and STF bit from engine 2 respectively.

support features, for further details about entering Halt Mode. 0: eTPU engine is not halted. 0: use system clock / 2 as EDF clock source before prescaler. FCSS = 1 also makes the channel work on T2/T4 timing mode (see Section , T2/T4 Channel Timing ). A new value written to FPSCK only becomes effective when the filter prescaler finishes the current count. Table 439. Filter prescaler clock control

changes the behavior of the transition detection logic while executing its operation.

18 Reserved

SPRAM address (see Section , Engine relative addressing mode). Primary scheme – priority among channels on different levels). 1: Scheduler priority passing mechanism disabled. 0: Scheduler priority passing mechanism enabled. SPPDIS bit must not be changed while any channel is enabled. Table 440. Channel digital filter control signal state. This is the default reset state.

See Section , T2/T4 Channel Timing

three consecutive samples which agree with each other sets the input signal state. eTPU Continuous Mode: Signal need to be stable for the whole filter clock period. other, input signal state is updated.

Section , Entry points). Table 441 shows the entry table base address options. Table 441. Entry table base address options

24.4.3 Time base registers

This register configures several timebase options. Figure 497. ETPU_TBCR Register

Table 442. ETPU_TBCR field description also determines the TCRCLK edge selected for angle tooth detection in angle mode. See Table 443. Table 443. TCR2 clock source

001 Rise transition on TCRCLK signal

010 Fall transition on TCRCLK signal

011 Rise or Fall transition on TCRCLK signal

100 DIV8 clock (system clock / 8)

101 Peripheral Timebase clock source

TCRCLK edges are not detected by the EAC logic, but they can still be detected by the channel 0

111 TCR2 frozen, except as STAC client do not use with AM = 1

whether the TCRCLK digital filter works in integrator mode or two sample mode (see Table 444). EAC (eTPU Angle Clock) hardware provides angle information to the channels using the TCR2 bus. used as general purpose. For more information, see Section 24.5.7, EAC – eTPU angle counter. and if AM is set the Angle Logic does not work properly. GTBE = 1, the recommended procedure is described in Section , Restarting angle logic. Table 442. ETPU_TBCR field description (continued) Table 444. TCRCLK filter clock/mode Table 445. AM - angle mode selection

Internal Timebase input, or TCRCLK filtered input. This field has no effect on TCR2 in Angle Mode. signal, a Peripheral Timebase source, system clock, or the system clock divided by 2 (see Table 446). source instead of system clock / 2. with TCR1CTL (see Table 446). TCR1CS = 1 also makes the channel work on T2/T4 timing mode (see Section , T2/T4 Channel Timing ). obeying to the fields TCR1P as if TCR1CS = 0 (see Section , Angle tick generator). Table 446. TCR1 clock source

All other combinations of TCR1CTL and TCR1CS are reserved.
This selection must not be used in Angle Mode.

prescaler divides this input by (TCR1P+1) allowing frequency divisions from 1 up to 256.

configuration set in ETPU_REDCR. Figure 498. ETPU_TB1R Register Table 447. ETPU_TB1R field description TCR1 value used on matches and captures. See Section 24.5.6, Time Bases.

Figure 499. ETPU_TB2R Register Table 448. ETPU_TB2R field description TCR2 value used on matches and captures. See Section 24.5.6, Time Bases.

(see Section , STAC Interface). Figure 500. ETPU_REDCR Register Table 449. ETPU_REDCR field description 1: Server/Client Operation for resource 1 is enabled. 0: Server/Client Operation for resource 1 is disabled. 1: Resource Server operation. 0: Resource Client operation. RSC1 must not be changed when the respective REN1 bit is asserted.

STAC Server Id (read-only plug values) used for TCR1 when STAC servers. configured as a STAC Client. SRV1 selects the STAC Server of TCR1. 1: Server/Client Operation for resource 2 is enabled. 0: Server/Client Operation for resource 2 is disabled. 1: Resource Server operation. 0: Resource Client operation. RSC2 must not be changed when the respective REN1,2 bit is asserted. STAC Server Id (read-only plug values) used for TCR2 when STAC servers. configured as a STAC Client. SRV2 selects the STAC Server of TCR2.

resource identifies any parameter that changes along the time and can be exported / imported from other device. In eTPU

context, a resource can be TCR1 or TCR2 (either Time or Angle values).

resource identifies any parameter that changes along the time and can be exported / imported from other device. In eTPU

context, a resource can be TCR1 or TCR2 (either Time or Angle values).

24.4.4 Engine related registers

ETPU_ECR – eTPU Engine Configuration Register). This register configures the watchdog timer for the engine. Figure 501. ETPU_WDTR Register Table 450. ETPU_WDTR field description operation, see Section , Watchdog. The watchdog must be disabled first before a new mode is configured.

stopped, or is in TST or halt states. Each eTPU2 engine has an associated ETPU_IDLE register. Figure 502. ETPU_IDLE Register information on Watchdog operation, see Section , Watchdog. The TST microcycles are also counted by the watchdog. Table 450. ETPU_WDTR field description (continued) Table 451. ETPU_IDLE field description idle counter operation, see Section , Idle Counter.

This write-only bit is used to clear the idle count IDLE_CNT. Table 451. ETPU_IDLE field description (continued)

24.4.5 Channel registers layout

number of channels to 64 for each eTPU engine. Figure 503. Channel registers area

24.4.6 Global channel registers

mirrored in the individual channel registers, grouped by channel.

write 1 to clear a status bit. Figure 504. ETPU_CISR Register

0 CIS9 CIS8 CIS7 CIS6 CIS5 CIS4 CIS3 CIS2 CIS1 CIS0

0 CIC9 CIC8 CIC7 CIC6 CIC5 CIC4 CIC3 CIC2 CIC1 CIC0

Table 452. ETPU_CISR field description 1: indicates that channel x has a pending interrupt to the Host CPU. 0: indicates that channel x has no pending interrupt to the Host CPU. 1: clear interrupt status bit. 0: keep interrupt status bit unaltered. For details about interrupts see Section , Channel interrupt and data transfer requests.

Figure 505. ETPU_CDTRSR Register Table 453. ETPU_CDTRSR field description to DTRCx) or by the assertion of corresponding DMA completion acknowledge line. 1: Indicates that channel x has a pending data transfer request. 0: Indicates that channel x has no pending data transfer request. For details about interrupts see Section , Channel interrupt and data transfer requests.

Register) and a write of ‘1’ clears a status bit. Figure 506. ETPU_CIOSR Register Table 454. ETPU_CIOSR field description 1: indicates that interrupt overflow occurred in the channel. 0: indicates that no interrupt overflow occurred in the channel. 0: keep status bit unaltered. For details about interrupt overflow, see Section , Interrupt and data transfer request overflow.

Control Register) and a write of ‘1’ clears a status bit. Figure 507. ETPU_CDTROSR Register Table 455. ETPU_CDTROSR field description 1: indicates that data transfer request overflow occurred in the channel. 0: indicates that no data transfer request overflow occurred in the channel. 0: keep status bit unaltered.

registers (see Section , ETPU_CxCR – eTPU Channel x Configuration Register ). Figure 508. ETPU_CIER Register Table 456. ETPU_CIER field description 0: interrupt disabled for channel x. For details about interrupts see Section , Channel interrupt and data transfer requests.

Figure 509. ETPU_CDTRER Register Table 457. ETPU_CDTRER field description 1: Data Transfer request enabled for channel x. 0: Data Transfer request disabled for channel x. For details about interrupts see Section , Channel interrupt and data transfer requests.

Requests (see Section 24.5.1, Functions and threads). Figure 510. ETPU_CPSSR Register a given time. When no channel is being serviced the register read value is 0x00000000. operation for monitoring the scheduler activity. Table 458. ETPU_CPSSR field description Indicates a pending Service Request for channel x. the end of the thread. SRx clear due to the other request sources is microcode dependent. respective bit being asserted in ETPU_CPSSR.

later can be changed by the service thread microcode. Figure 511. ETPU_CSSR Register Table 459. ETPU_CSSR field description Transition (see Section , Time slot transition), or when the microengine ends the thread.

24.4.7 Channel configurat ion and control registers

ETPU_ECR bit MDIS = 1. Writes are ineffective on bus error.

The SIU_ISEL8 Register is used to multiplex the eTPU[24:29] inputs. When SIU_SEL8

Table 460. Channel registers structure Table 461. Channel registers map

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 831/1740 There are 64 structures defined, one for each available channel in the eTPU System (32 for each engine). The base address for the structure presented can be calculated by using the following equation: Channel_Register_Base = ETPU_Engine_Channel_Base + (channel_number * 0x10) where: ETPU_Engine_Channel_Base = ETPU_Base + 0x400 for Engine 1 ETPU_Engine_Channel_Base = ETPU_Base + 0x800 for Engine 2

ETPU_CxCR gathers configurations set individually per channel. Figure 512. ETPU_CxCR Register Table 462. ETPU_CxCR field description 1: Enable interrupt for this channel. 0: Disable interrupt for this channel. See Section , Channel interrupt and data transfer requests. 1: Enable data transfer request for this channel. 0: Disable data transfer request for this channel. See Section , Channel interrupt and data transfer requests.

about Entry Table and condition encoding schemes, refer to Section , Entry points. 1: use PSTO for Entry Point selection. 0: use PSTI for Entry Point selection. Entry Table and condition encoding schemes, refer to Section , Entry points. 1: select Alternate Entry Table Condition encoding scheme. 0: select Standard Entry Table Condition encoding scheme. The fields ETCS, CFS and CPBA must only be changed while the channel is disabled (field CPR = 00). scheme, selected by field ETCS. The fields ETCS, CFS and CPBA must only be changed while the channel is disabled (field CPR = 00).

ipp_ind_etpu_odis_[1|2]([0 – 3]) eTPU Channel Output Disable Signals and Figure 528. 0: turns off the output disable feature for the channel. the ODIS bit, the channel output signal to the opposite of this polarity (see Figure 528). The fields ETCS, CFS and CPBA must only be changed while the channel is disabled (field CPR = 00).

Section 24.4.6, Global channel registers). Host must write 1 to clear a status bit. Figure 513. ETPU_CxSCR Register

The IPS value after reset is MCU dependent

Table 463. ETPU_CxSCR field description 1: channel has a pending interrupt to the Host CPU. 0: channel has no pending interrupt to the Host CPU. 1: clear interrupt status bit. 0: keep interrupt status bit unaltered. Register. See also Section , Channel interrupt and data transfer requests.

0: keep status bit unaltered. Overflow Status Register. See also Section , Interrupt and data transfer request overflow. 1: Channel has a pending data transfer request. 0: Channel has no pending data transfer request. Request Status Register. See also Section , Channel interrupt and data transfer requests.

16 IPS—Channel Input Pin State

18 OBE—Output Buffer Enable

This bit shows the state of the channel output buffer enable signal, controlled by microcode. Section , Conditional/Unconditional branch).

These bits are equivalent to the TPU/TPU2/TPU3 Host Sequence (HSQ) bits.

ETPU_CxHSRR is used by the Host to issue service requests to the channel. Figure 514. ETPU_CxHSRR Register Table 464. ETPU_CxHSRR field description HSR > 000: function-dependent Host Service Request pending.

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 839/1740

24.5 Functional description

24.5.1 Functions and threads

eTPU processing is event-driven, in the sense that eTPU microcode only runs to service a request from an event. Service Requests may result from the occurrence of any of the following events:

Host CPU writing a non-zero value to the channel HSR (Host Service Request) field in ETPU_CxHSR.
occurrence of a time base match, an input signal transition, or a specific combination of them (depending on the Channel Mode currently configured).
a Link Service Request. A given event is always associated to only one Channel:
There is one HSR register field for each Channel
Each signal is associated with only one Channel, which has its own Match registers and independent mode configuration.
Each Link Service Request can have only one Channel as a target. Service Request processing is done by a set of microengine routines. A set of related routines that implement a specific channel application is called a Function. One or more Functions reside on SCM, limited only by the SCM space available, size of microcode Functions and the number of entry points available. Each engine can be controlled by up to 32 Functions at a time. A Function can be assigned to several channels, but only one Function can be assigned to a given Channel at a time. This is defined by the Host through the Channel Configuration Registers (see Section 24.4.7, Channel configuration and control registers). The term Thread will be used hereafter to refer to a service routine of a Function, or its execution. A Thread is constructed of a specific number of microinstructions, typically the code necessary to calculate the next phase of waveform to be input to, or output from, a given channel. Once a Thread begins, its execution cannot be interrupted. A Thread normally finishes when an END microinstruction is executed. A given Thread is selected and called by the Scheduler depending on the following:
the type of event that generated the service request.
the Function assigned to the target channel.
target channel pin state.
the state of the channel logic.
the priority assigned to the target channel, relative to the priorities of other channels with pending service requests The mechanism to select a thread based on the channel Function and type of event is described in the Section , Entry points. The priority mechanism that determines the order of Thread execution amongst pending service requests is described in Section 24.5.3, Scheduler.

conditions. Entry Table layout is shown in Figure 515. Figure 515. Entry Table

the SCM, as shown in Figure 516. Figure 516. Entry Point Address (host address offset)

Standard Entry Table Condition encoding scheme, shown in Table 465, which privileges Host Service Requests.
Alternate Entry Table Condition encoding scheme, shown in Table 466, which focus on other events and state decoding. The events that take part on condition encoding generate a Service Request, and have four origins: 1. Match Recognition (caused by greater/equal match, or equal-only, between the value TCR1/2 and the value stored in the channel match registers). eTPU channels support single and double match in various modes of match recognition; see Section , Match Recognition. 2. Transition Detect Service Request (channel input signal transition detection of a selected edge). The eTPU channels support single and double transition, which together with the double match options provide various modes of transition detection; see Section , Transition Detection and Time Base Capture. 3. Channel Linking Service Request (microcode writing the channel number to the LINK register). Link service request allows one channel to activate another (see Section , Channel Link). 4. Host Service Request (Host writes a non-zero value to the HSR bits of the channel; see Section , Host service requests). ETB[4:0] (ETPU_ECR) (ETPU_CxCR) Encoded (C4-C1) Channel ConditionsCFS[4:0] Encoded (C0) Channel Conditions A5-A2A10-A6 A1A15-A11 Half-word SelectWord Address A0 = 0

Enhanced Time Processing Unit (eTPU2) RM0029 842/1740 Doc ID 15177 Rev 8 Note: Even if a Transition or Match Service Request is inhibited (by channel mode/state or SRI), the Transition Detection and Match Recognition are taken into account for condition encoding. That is, the MRLA/B and TDLA/B flags are used, not their respective Service Requests. Columns Host Request Bits, Link Request, MatchA/TransB, and MatchB/TransA determine the type of event. A non-zero value in these columns represents the recognition of the event, while “x” indicates that its recognition is irrelevant. Values 1 and 0 mean that event was recognized or not, respectively. Note that Match and Transition events may occur and not be recognized, and in this case it assumes value 0 for the condition encoding. The recognition of such an occurred event depends on the channel mode assigned and other conditions, as described in Section 24.5.5, Enhanced Channels. The Host Service Request Bits column refers to the value written by the Host CPU to the Host Service Request Register (ETPU_CxHSRR) of the Channel being serviced. Note that the bits on this row are coded (3-bit representation). If the value of HSR is not zero, then the Host actually requested service. The Link Request column refers to the occurrence of a Channel Link request. The MatchA/TransB column refers to the recognition of either a Match event specified by MatchA channel register or the detection of a channel input signal event specified by the IPACB configuration register (see Section , Pin Control Registers). The MatchB/TransA column refers to the recognition of either a Match event specified by MatchB channel register or the detection of a channel input signal event specified by the IPACA configuration register (see Section , Pin Control Registers). For the channel input signal, MatchA and MatchB provide double timeout conditions which depend on the channel mode programming (see Section , Channel Modes). If the channel is used for output only, there are no transition detections, so the MatchB/TransA column represents only Match B, and MatchA/TransB column the Match A. In this case Match A and Match B are separated to give better state resolution in double match output functions. For more information about channel requests refer to Section 24.5.5, Enhanced Channels. Besides those events, the following channel state conditions help to determine the Entry Point: 1. Channel Flags 0 and 1: these are channel-internal flags (not in SPRAM) associated with a channel. Their values are set by microcode (see Section , Channel flags operations). 2. Input Pin state or Output Flip Flop: the state (0 or 1) of the channel input signal after the Enhanced Filter (see Section , Enhanced Digital Filter – EDF), or the state driven to the output signal. Which one (input or output) is used is selected by the ETPU_CxCR bit ETPD. The two Entry Table Condition encoding schemes combine events and state conditions differently, as detailed in the following sections. Standard condition encoding scheme In this scheme, shown in Table 465, all seven HSR combinations are used and other event type columns are marked “x” when HSR is non-zero, indicating that Host Service Request has priority over any other type of event. However, when an HSR service thread is called (entry numbers 0 to 9), other events may also have been recognized, and it is microcode responsibility to check them.

channel flag 1 does not influence the encoding in this scheme. Table 465. Standard channel condition encoding scheme

HSR = 010 or 011, which are coded into the same Entry Points (0 to 3)
HSR = 100,101 or 001, which are all coded into Entry Point 4
HSR = 110 or 111, which are both coded into Entry Point 5
The ETPU_CxCR bit ETPD selects between input and output pin state.

Table 465. Standard channel condition encoding scheme (continued)

Table 466. Alternate channel condition encoding scheme

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 847/1740 Time slot transition The Time Slot Transition period (also called TST for short) is the interval between the servicing of two channels, during which all Channel-specific context is loaded for the new serviced Channel. The primary tasks completed during this period include:

Set MEF for the first microcycle plus eventual wait-states.
Reset the MEF for one microcycle after the first microcycle plus wait-states.
Update of the CHAN register with the number of the new channel to be serviced.
Parallel update of ERTA and ERTB from CaptureA and CaptureB registers of the new serviced channel.
Sampling of the branch conditions of the new channel to be serviced into the branch logic (this means flags TDLA/B, MRLA/B, LSR, FM[1], FM[0], and PSS). The branch conditions are coherent with the timebase capture values sampled into ERTA/B (if MRLA/B, TDLA/B are set at the same time of the sampling, either both old flag state and capture values are sampled, or both new values are sampled).
Formation of the entry point address.
Copy the ME bit in the Entry Point into MEF.
Access to the entry point location and getting the first microinstruction address.
Preload of two parameters from the SPRAM into P (32 bits) and DIOB (24 bits).
Fetch the first instruction of the thread to be executed for the new channel.
Preset the RAR value (see Section , RAR – Report Address Register). ME Match Enable ME specifies whether match event recognitions are enabled or disabled for the thread associated with the entry point during the thread execution. If they are disabled, a match recognition can only occur after channel service. For more details refer to Section , Match Recognition. Matches are disabled during the thread. Matches are enabled during the thread. The disabling of Match A/B recognition by MEF is dependent on IPACA/B configuration on the serviced channel (see Section , Pin Control Registers). If IPACA = 1xx, Match A is not disabled by ME = 0. Likewise, IPACB = 1xx overrides the effect of ME on Match B to “always on” If IPACA/B = 0xx, Match A/B is disabled for one microcycle during TST (see Section , Time slot transition) and is re-enabled when Entry Point is loaded, if ME = 1. Note that if the comparator is in equal-only mode and the time base reaches the value of the Match register during the time that recognition is disabled (beginning of TST, plus whole thread if ME = 0), the match recognition is lost. If the comparator is in greater-equal mode, the match event may be recognized after the disabling period if it satisfies the “greater-than” condition. PP Preload Parameter PP indicates which pair of channel parameters are loaded into registers P and DIOB from the SPRAM prior to the execution of a thread. Preloading occurs during the time-slot transition period (see Section , Time slot transition) Microengine register P is preloaded from parameter 0 and DIOB from parameter 1. Microengine register P is preloaded from parameter 2 and DIOB from parameter 3. The parameter numbers are offsets from the channel parameter base address. For more info, see Section , Parameter access. Field Description

Enhanced Time Processing Unit (eTPU2) RM0029 848/1740 Doc ID 15177 Rev 8 The preload operation is 32-bit wide for P and 24-bit wide for DIOB. The P register is loaded with all the 32-bit parameter. The DIOB register is loaded with the lower 24-bits of the parameter. The microcode can switch at any time to access the lower 24-bits, upper byte, or all the 32-bits of any parameter in the SPRAM. Preload of P-DIOB pair of parameters is atomic with respect to Host and CDC accesses, and so are coherent with their dual- parameter coherent transfers. For more details see Section 24.5.4, Parameter sharing and coherency. No instructions are executed at the engine where the time slot transition period occurs, but the other engine can execute normally. Match A/B is unconditionally disabled on the second TST microcycle, if IPACA/B = 0xx (respectively). During the rest of time slot transition, match recognition can be disabled or not, depending on IPACA/B field and ME. See Section , Match Recognition. Time Slot Transition takes a minimum of 3 microcycles (6 system clocks), which may be extended due to SPRAM arbitration wait-states for the first preload access (see Section , SPRAM Arbitration). When no wait-states are received (Figure 518), DIOB is preloaded twice, one for each PP value, and the correct value remains in DIOB when the Entry Point is loaded. Figure 519 and Figure 520 show the timing for one and two wait-states, respectively. Registers B, C, D and SR are not altered by TST and keep their values from the previous thread. The values of registers A, MACL and MACH are not guaranteed at the thread start.

Figure 518. TST Timing – No Wait-states

Figure 519. TST Timing – 1 Wait-State

Figure 520. TST Timing – 2 Wait-states

An instruction with the END field active (see Section , Ending current thread – END).
A forced END by host writing to the ETPU_ECR bit FEND (see Section , ETPU_ECR – eTPU Engine Configuration Register).
A forced END caused by Watchdog timeout (see Section , Watchdog). System Clock CHAN Register END Signal ERTA, ERTB Preload SPRAM Wait T2 T4 T2 T4 T2 T4 T2 T4 T2 T4 T2 T4 T2 T4 DIOB CHANNEL X CHANNEL Y X END TST1 wait TST1 wait TST1 TST2 TST3 Y 1st Inst Preload P TIME SLOT TRANSITION MEF μPC μINST END Y Entry Addr Y1st Inst Addr Entry Point Y 1st Inst Y2nd Inst Addr HSR sampled for Flags for Entry Point Entry Point and Branch Condition DIOBPP=1DIOBPP=0 Pentry point PP DIOBentry point PP XY

Enhanced Time Processing Unit (eTPU2) RM0029 852/1740 Doc ID 15177 Rev 8 Watchdog Each engine has a watchdog mechanism to prevent a thread or a sequence of threads from running too long, impacting the latency of the other channel services. The watchdog is configured through the register ETPU_WDTR (see Section , ETPU_WDTR – eTPU Watchdog Timer Register). When the watchdog is enabled, an internal counter increments on each microcycle when a thread is executing. If the count is greater than the value specified in the ETPU_WDTR field WDCNT and a thread is still executing, the watchdog: 1. Forces an END of the thread 2. Issues a Global Exception and sets the ETPU_MCR bit WDTO (see Section , ETPU_MCR – eTPU Module Configuration Register). The watchdog can be configured in one of the following modes, defining how the internal watchdog count is reset:

Thread Length Mode: the watchdog count is reset at the end of each thread.
Busy Length Mode: the watchdog count is reset when the microengine goes idle. A sequence of threads, one right after another, keeps the count running. The counter is also reinitialized when a thread is forced to end, so that a new count begins if another TST initiates at the following microcycle. The following applies to the watchdog mechanism:
Microcycles during TST and SDM access wait-states (on TST or instruction execution) are counted.
If the watchdog count equals WDCNT in the last microinstruction (with SDM wait-states or not) of a thread servicing a channel.
If the watchdog count expires (gets greater than WDCNT) during the TST, the thread is forced end on its first instruction.
The watchdog count does not wrap, so that a thread (in thread length mode) or a thread sequence (in busy length mode) that lasts for more than the maximum value of WDCNT does get a forced end. Note: Watchdog must not be enabled when the microengine enters halt mode. The counter does not run when the engine is stopped, and resets when the watchdog is disabled.

24.5.2 Host interface

System Configuration Registers are described in Section 24.4.2, System configuration registers. Detailed explanation on the configured functionalities is found throughout Section 24.5, Functional description, and a specification for the initial configuration sequence is found on Section 24.6.1, Configuration sequence. Interrupts and data transfer requests Interrupt types and sources Each one of the eTPU channels can be a source of two requests: Channel Interrupt request and Data Transfer Request. Channel Interrupts are targeted to a Host CPU. Data Transfer Requests may be targeted to a data transfer module (e.g., a DMA controller). Interrupt and Data Transfer registers are used by the Host to enable interrupts and data

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 853/1740 transfer requests, indicate their status and service them. Interrupt and Data Transfer requests have the same sets of registers and external signals, and are handled in the same way. They differ only by the fact that Data Transfer Requests are also cleared by the assertion of respective DMA completion acknowledge line. Data Transfer Requests can be used as another source for Host interrupts at MCU integration if not used with a DMA. Note: Interrupt and Data Transfer requests can be cleared even when engines are in Module Disable Mode, through the Global Channel Registers, and also DMA completion for Data Transfer requests. Channel Interrupts and Data Transfer Requests can only be issued by eTPU microcode, through one of the Channel Control instruction fields (see Section , Channel interrupt and data transfer requests). Both Channel Interrupt and Data Transfer requests can be individually enabled for each channel. eTPU Interrupt and Data Transfer Registers are mirrored in two organizations: grouped by Channel and grouped by type (interrupt status, interrupt enable, data transfer status, data transfer enable). This allows either “channel-oriented” or “bundled channel” Host interrupt service schemes, or a combination of them. For a detailed description, refer to eTPU can also assert a Global Exception interrupt indicating a global illegal state. There are three possible sources for a Global Exception:

Execution of an illegal instruction by the microengine (see Section , Illegal Instructions). This Global Exception source is flagged by the bits ILF1 and ILF2 in register ETPU_MCR.
An SCM signature mismatch detected by the Multiple Input Signature Calculator (MISC). See Section , SCM Test – Multiple input signature calculator. This source is flagged by the bit SCMMISF in register ETPU_MCR.
Microcode request, through microinstruction field CIRC (see Section , Channel interrupt and data transfer requests). This Global Exception source is flagged by bits MGE1(Engine 1) and MGE2(Engine 2) in register ETPU_MCR. The cause of this illegal state is application-dependent. The microcode may write an error code into the SPRAM to indicate the cause of the exception, for instance.
An SDM or SCM non-correctable error due to a microengine access Global Exceptions cannot be directly disabled within eTPU, except by disabling its sources (MISC and microcode), and it is cleared by writing 1 to the GEC bit in ETPU_MCR. Clearing Global Exception clears all Global Exception source status bits (ILF1, ILF2, SCMMISF, MGE1, MGE2). If GEC is written 1 at the same time any of the sources issues a Global Exception, both the interrupt and the status bit of that source remains asserted. The assertion of Global Exception by one of the sources above does not prevent the others from asserting it too, so any number of them, in any combination, can be flagged. Note: There can be a race between the clear of a Global Exception and occurrence of a new set condition, such that the set happens just before the clear and cannot be sensed by the Host. Therefore, Global Exception cannot be used as a normal interrupt source: it should only be used for emergency procedures. Interrupt and data transfer request overflow If a Channel Interrupt was issued, its status bit is still set, and microcode issues another Channel Interrupt, the Interrupt Overflow status bit is set for that channel. Interrupt Overflow

Enhanced Time Processing Unit (eTPU2) RM0029 854/1740 Doc ID 15177 Rev 8 status can be checked by the Host in Channel Status register ETPU_CxSCR bit CIOS (Section , ETPU_CxSCR – eTPU Channel x Status Control Register), mirrored in register ETPU_CIOSR (Section , ETPU_CIOSR – eTPU Channel Interrupt Overflow Status Register). Interrupt Overflow status is not cleared automatically when Interrupt Status is cleared. The same mechanism and respective registers (ETPU_CDTROSR) are available for Data Transfer Requests. If interrupt is set and cleared at the same time, set prevails and overflow is not altered (keeps the same state as it was before, asserted or not). Global Exception has no overflow status. Parameter access Parameter access widths From the Host side the SPRAM address space is mapped in bytes, and each 32-bit parameter occupies 4 contiguous, aligned bytes. The Host can read/write the SPRAM by 8- , 16-, or 32-bit accesses in aligned addresses. In 32-bit access, Host can access all 32 bits or only the lower 24 bits with an automatic sign extension (see Section , Parameter sign extension area). Parameter addresses and endianness To access parameter number xxx, eTPU Microengine(s) would select address xxx. The Host would add (xxx*4) to the SPRAM base address to access the same parameter. For example, parameter 0x101 is seen by the Host in (SPRAM base address +0x404). An example of SPRAM memory map is shown in Figure 521. The Host can access the SPRAM with a 32-bit-wide bus cycle to a four-byte aligned address, 16-bit-wide bus cycle to a two- byte aligned address, or 8-bit wide bus cycle to any byte address. The address of the 24-bit parameters and the most significant byte depends on the endianness of the MCU. For more details, see the Section 24.6.6, Endianness. Parameter concurrency Host accesses to parameters may occur in parallel with eTPU Microengine accesses. Readings taken from a group of parameters while they are being simultaneously updated may lack coherency. eTPU provides mechanisms to ensure parameter coherency in accesses from both Host side and Microengine side, including the use of a coherent dual- parameter transfer mechanism, described in detail on Section 24.5.4, Parameter sharing and coherency. Parameter sign extension area The SPRAM address space to the Host is mirrored in a Parameter Sign Extension (PSE) area (see Section 24.4.1, Memory map). Accesses from the Host to the PSE area differ from accesses to the standard SPRAM address space as follows:

Writes: the most significant byte of the parameters is not written, and the SPRAM retains the old byte value, regardless of the Host access size.
Reads: the most significant bit of the 24-bit parameter (that is, the msbit of the second most significant 32-bit parameter byte) is repeated in the 8 most significant bits of the read value on all 32-bit reads and most significant 16- and 8-bit reads.

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 855/1740 The same parameters written in the standard SPRAM address space are read from the PSE area with the same offsets, and vice-versa. See Table 557 for a reference of the address offsets in big and little endian machines. This feature reliefs the Host from extending the signal of 24-bit eTPU parameters before calculations, and from read-modify-write accesses to modify 24-bit parameters at the SPRAM. SPRAM organization The SPRAM internal partition for channel allocation is dynamic and programmed in the Channel Registers (see Section , ETPU_CxCR – eTPU Channel x Configuration Register ). The Host application is responsible for allocating a different parameter base address to each channel during the initial eTPU configuration, and to allocate enough parameters for the selected function, with no unintentional overlapping between parameters of different functions. Besides channel parameters, global areas may have to be allocated for parameters that are shared by more than one channel, in one or both engines. Also, temporary parameter areas should be reserved to be used by the coherent parameter transfer mechanisms described in Section 24.5.4, Parameter sharing and coherency, if necessary.

Figure 521. SPRAM organization example there is no limitation of fixed channel addresses, and the reduced array can be fully utilized. eTPU absolute addressing mode.

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 857/1740 Host Service Request Register). There is one HSR field for each channel, so that writing to it generates a Service Request to the respective channel only. A zero value in HSR means no Host Service Request is pending for the channel. HSR value turns to 000 automatically at the end of microengine service for that channel, but only if the thread started due to an HSR. The meaning of a non-zero HSR value depends on the Function assigned for the channel. These bits are part of the conditions which select the Function entry point, and cannot be tested by microcode. For more details, refer to Section , Entry points. If Host writes HSR = 000 when a thread for the same channel is already running, the thread runs until the end and is not aborted. If Host writes HSR>000 when an HSR thread for the same channel is already running, HSR value resets at the end of the thread, and no new HSR will be pending. If HSR is written before its value is resolved by the scheduler during TST, the entry point will obey the new HSR value, and if this new value is 000, no service thread is executed for the HSR. The scheduling of HSRs is completely asynchronous with Host accesses, and there is no race-free manner to change an HSR value before service thread execution, so generally the safe way is: write HSR>0 only when HSR = 0. Error recovery or emergency host procedures may require one to the safely abort service and reset channel state when an HSR is already pending or executing. In these cases, the procedure below should be followed: 1. Disable the channel, writing CPR = 00 in register ETPU_CxCR. That will prevent any pending HSR to be serviced. 2. Check if the channel is currently being serviced, reading its service status bit in register ETPU_CSSR. If it is, wait for the time necessary to finish the service pending, or check again until HSR == 0, or channel service bit in ETPU_CSSR is cleared. 3. Write HSR with the error recover value. This value should, possibly combined with other host-defined flags in SPRAM or FM bits, initiate a channel reset or error recovery procedure. 4. Re-enable the channel, writing CPR value > 0 in register ETPU_CxCR. SCM access Only Host can access SCM as data. Depending on the specific device, SCM may be implemented as a RAM or ROM. This determines Host accesses to the SCM as shown below. SCM RAM implementations When SCM is implemented as RAM, the Host may read or write to SCM by setting ETPU_MCR bit VIS = 1. If VIS = 0 and Host tries to access SCM space, a bus error is issued, writes are ineffective and read data is meaningless. Both engines must be stopped or halted to set VIS = 1. Only 32-bit aligned writes are allowed to SCM from the Host. Write accesses of other sizes store unpredictable values into SCM. Note: It is necessary to turn VIS bit on to set software breakpoints (see Section , Software breakpoints). SCM low power SCM turns off its internal clocks when both engines are stopped (ETPU_ECR bit STF asserted), VIS = 0 at ETPU_MCR, and MISC is not enabled (SCMMISEN = 0). The SCM

The conditions for SCM Clocks and MISC activation are summarized in Table 467. addresses, so they should be avoided.

24.5.3 Scheduler

instructions that, once begins execution, cannot be interrupted by host or channel events. Table 467. SCM clocks and MISC activation

VIS cannot be written 1 if ETPU_ECR_1 bit STF = 0 or ETPU_ECR_2 bit STF = 0, and both HLTF bits are 0.
If VIS = 1, neither MDIS can be written 0 nor the engine leave Stop Mode, regardless of device stop request.
MISC resets and stays so when VIS = 1, restarti ng automatically when VIS goes 0 if SCMMISEN = 1.

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 859/1740 The task of the Scheduler is to recognize and prioritize the channels needing service and to grant execution time to each channel. The time given to an individual Thread for execution or service is called a Time Slot. The duration of a time slot is determined by the number of instructions executed in the Thread plus SPRAM wait-states received, and varies in length. At any time, an arbitrary number of channels can require service. To request service, channel logic, eTPU microcode or Host application notifies the Scheduler by issuing a Service Request. Channel enabling and priority assignment Every channel is assigned one of three priority levels—high, middle, or low—by the Host CPU, through the Channel Configuration Register field CPR (see Section , ETPU_CxCR – eTPU Channel x Configuration Register). These registers are also used to disable the channel, which is equivalent to assigning it a “null” priority. In this case, the Scheduler does not grant any of its Service Requests. It is possible to change the channel priority level or disable it dynamically. If the Host disables a channel when it is currently being serviced, channel service thread will complete. This means that it is possible for the output level of a channel signal to change, or a Host interrupt occur, even after its priority register was written to “null”. For instance, if an output transition is scheduled, the transition will occur even after the channel is disabled. Service requests previously pending or that occur while a channel is disabled remain asserted while the channel is disabled, and are serviced if the channel is enabled again, in due time determined by the priority scheme and concurrent requests from other channels. Channels are disabled after reset, and it is recommended to configure a Host Service Request for initialization of a channel before that channel is enabled to active priority (see Section 24.6, Initialization/Application information). Channel priority schemes The Scheduler holds a Service Grant register with one bit for each channel. Once the Scheduler grants a time slot to channel, the Service Grant bit for that channel is asserted in the Service Grant register. When the Service Grant bit of a channel is set, the channel may request new service but is not serviced again before its Service Grant bit is cleared. When all channels in a same priority level are serviced, their Service Grant bits are cleared at the end of the thread, one system clock before the next serviced channel is calculated, according to the scheme below (w):

Clear all grant bits of priority High if all channels of that priority that are requesting have their grant bits in 1.
Clear all grant bits of priority Medium if all channels of that priority that are requesting have their grant bits in 1.
Clear all grant bits of priority Low if all channels of that priority that are requesting have their grant bits in 1.
Clear all grant bits of disabled channels. This scheme assures that no channel is left with its grant bit forever asserted (preventing it from being serviced again), even if the channel priorities are reassigned during the execution. w. Grant bits are also cleared in the next clock, when t he service channel is chosen, or when the microengine is idle, using the same scheme.

should be allocated a high priority level. prioritizes requesting channels that have the same priority level. honor low-level channels first. Only one request (in each engine) is serviced per time slot. Figure 522. Time Slot Priority levels to be serviced would be the low-priority channel.

level channel requests service, the Scheduler recognizes a requesting middle-level channel. sequence is resumed with the next time slot. Figure 523. Priority Passing Example requests before time slot six, so it passes the priority to a requesting high-level channel. Table 468. Priority passing

C is truncated and the Scheduler passes to time slot one of cycle D. incremented until a time slot that matches the priority of one of the requesting channel(s). no longer has the priority inversion. service, as only a low priority request remains also, and only time slot 4 is assigned to low. Table 469. Priority Passing Disabling

1 High Medium 2 High 3 Low 4

2 Medium High 3 Low 4 Medium 6

3 High Low 4 High 5 Medium 6

4 Low High 5 Medium 6 Low 4

5 High Medium 6 High 7 Low 4

6 Medium High 7 Medium 2 Low 4

7 High High 1 Medium 2 Low 4

It follows the same scheme until there are no other requests and cycle C is truncated,

resetting the time slot counter to 1. middle priority channel request in cycle D is finally serviced next, on time slot 5. Figure 524. Priority Passing Disabling Example with the lowest numbered channel on that level. schemes. Combining both schemes in the following example conveys their correlation.

One high-priority and one low priority channels request service, while the Scheduler is

Enhanced Time Processing Unit (eTPU2) RM0029 864/1740 Doc ID 15177 Rev 8 grant bit is asserted. At the end of the thread, the service grant bit is negated (no more requests of high priority level channels). 2. The Scheduler proceeds to time slot two, which has middle-level priority; however, no middle-level channel is requesting service. Priority is passed to the high level, but no high-level channel is requesting service; therefore, priority is passed again, and service is granted to the single requesting low-level channel. Once serviced, this channel’s grant bit is negated (no more low-level requests). 3. The Scheduler resumes with the fixed-priority sequence on time slot three; however, no channels are requesting service. The Scheduler returns to time slot one, waiting for requests. 4. Two high-level and two middle-level channels simultaneously request service. Being in time slot one which is assigned high priority, the Scheduler finds the lowest numbered high-level channel (secondary scheme) and selects it for service. This channel’s service grant bit is asserted. 5. The Scheduler continues to time slot two, which has middle priority (primary scheme), and allocates the slot to the lowest numbered middle-level channel requesting service (secondary scheme). The Scheduler notes the still unserviced middle-level channel and proceeds to time slot three. 6. Time slot three is allocated for high priority. The slot is allocated to the remaining unserviced high-priority channel, and the channel’s service grant bit is asserted. The Scheduler checks again at the end of the thread. All service grant bits of high-level requested channels are asserted; therefore, all high-priority channels that requested have been allocated execution time. Under this condition, all service grant bits of the high-level serviced channels are negated. The Scheduler proceeds to time slot four. 7. Time slot four is allocated for low-priority channel; however, no low-level channel is requesting service. Priority is passed to the high level, but no high-level channel is requesting service; therefore, priority is passed again, and service is granted to the remaining middle-level channel which requests service. This channel’s service grant bit is asserted. The Scheduler checks again at the end of the thread. All grant bits of middle-level requested channels are asserted; therefore, all middle-priority channels have been allocated execution time. Under this condition, all service grant bits of the middle-level serviced channels are negated. The Scheduler proceeds to time slot five. Meanwhile a low priority channel requests service. 8. Time slot five is allocated for high-priority channels, but there are no more requests from high-priority or middle priority channels. The single low-level channel which required service is granted time slot five. Once serviced, the channel’s service grant bit is asserted. Next, the service grant bit is negated (no more requests of low priority level channels). 9. The Scheduler resumes with the fixed-priority sequence on time slot six; however, no channels are requesting service. The Scheduler returns to time slot one and waits for requests.

Number of active channels
Number of channels on a priority level
Number of available time slots on a priority level
Number of microcycles required to execute a thread of a Function
Number of parameter RAM accesses during execution of a Function thread
System clock frequency. Each time slot may require a different number of microcycles, depending on the thread of a Function to be executed. This variation is shown in Figure 525. For more details on latency evaluation, see Section 24.6.5, Estimating worst-case latency.

Figure 525. Time-slot variation

24.5.4 Parameter sharing and coherency

parameters are read when only part of them is updated.

the use of Transfer Service Thread mechanism.
the mailbox (or “software semaphore”) mechanism. These mechanisms, described in Section 24.6.3, Multiple parameter coherency methods, use microcode to transfer parameters from temporary buffers in SPRAM to their definitive locations (or vice-versa). These methods have the disadvantage of wasting processing and code memory resources. eTPU also provides a Coherent Dual-parameter Controller (CDC) mechanism. It is used by Host to coherently transfer pairs of parameters from/to a parameter buffer located on SPRAM to/from the locations on SPRAM where parameters are accessed directly by the channels. Coherency is guaranteed by SPRAM access arbitration. Although limited to two parameters only, it has lower latency and wastes no microengine resources (y). CDC usage is described in Section , Coherent Dual-parameter Controller (CDC). Microcycles Time Slot Fixed Priority Level 1 23 4 5 H MH L H M

Enhanced Time Processing Unit (eTPU2) RM0029 866/1740 Doc ID 15177 Rev 8 For parameters shared by both engines, eTPU provides Hardware Semaphores. Coherency is assured given the semaphores are used to prevent concurrent access to the changing parameters. Microengine can request semaphores using specific microinstructions (see Section , Semaphore operations). Hardware Semaphores are described in detail in Section , Hardware Semaphores. Neither Host nor CDC have access to the hardware semaphores, but they can be combined with microcode transfer mechanisms if Host must coherently access parameters which are also shared by both engines. In order to ensure coherent access to a group of parameters by two or more contenders, each contender must have atomic access to the shared parameters. Atomicity conditions are discussed in Section , Host Side Atomic Access, and Section , Microengine Side Atomic Accesses. Host Side Atomic Access Host side atomic accesses can be achieved by either of following ways:

For one parameter, the SPRAM should be accessed by 32-bit-wide data transfers to ensure coherency
For two parameters only, using the Coherent Dual-Parameter Controller. indirectly, for any number of parameters, by requesting microcode to coherently access SPRAM in its behalf. The host side atomicity problem becomes, then, a microengine side atomicity problem. Some methods that use this approach to achieve coherency are described in Section 24.6.3, Multiple parameter coherency methods. Microengine Side Atomic Accesses Microengine single-parameter atomicity SPRAM should be accessed by 32-bit-wide data transfers to ensure atomicity for 32-bit parameters. This applies either to Host-Microengine coherency or Microengine-Microengine coherency in a dual eTPU engine system. Microengine dual-parameter atomicity Microengine has the ability to access two parameters coherently in back-to-back accesses, at random addresses: once it accesses SPRAM, it has priority over Host for another access in the next microcycle (see Section , SPRAM Arbitration). Note that it applies only to Microengine-Host coherency. For Microengine-Microengine coherency in a dual eTPU engine system, one must use Hardware Semaphores (see Section , Hardware Semaphores). Microengine dual back-to-back accesses are guaranteed to be atomic in relation to Host slave accesses or Coherent Dual-parameter Controller, regardless of semaphore usage: Host or CDC accesses cannot break-up a back-to-back Microengine access, neither Microengine can break a CDC transfer, due to the SPRAM arbitration mechanism described in Section , SPRAM Arbitration. y. A microengine access to the SPRAM in the moment CDC is performing the transfer may suffer a maximum of two wait-states.

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 867/1740 Atomicity is not guaranteed if microengine enters halt state in the middle of a back-to-back access (see Section , Microengine halt state): Host can access SPRAM while microengine is halted in the middle of a back-to-back access. Microengine Side Multiple Atomicity Hardware Semaphores must be used for Microengine-Microengine coherency (more than 1 parameter) since two or more accesses from one Microengine are not atomic with respect to the other. For multiple Microengine-Host coherency, the software methods described in Section 24.6.3, Multiple parameter coherency methods, or similar ones, must be used. Some of these methods rely on the fact that parameter access of a thread is atomic in relation to another thread in the same engine, since a thread cannot be suspended (pre- empted). For 1 parameter coherent access, or dual-parameter coherency between only one Microengine and Host, the alternatives shown in previous sections apply. Coherent Dual-parameter Controller (CDC) Dual-parameter coherency is supported by a Coherent Dual-parameter Controller hardware (CDC), which contends with microengine for SPRAM access. CDC atomically transfers, upon Host’s command, two parameters from one area of the SPRAM to another. One area is a temporary (buffer) area, where the two parameters are directly read or written by the Host. This temporary area has to begin in an SPRAM address multiple of 2 words, and the two parameters must be sequential. The other area is the channel parameter area where the microcode normally accesses the parameters, usually with the channel relative address mode (see Section , SPRAM Addressing Modes). In this area, the parameters transferred by CDC don’t have to be sequential. A transfer from the temporary area to the channel area, when the Host sends data to the channel, is called a write transfer. Inversely, in a read transfer the parameters are copied from the channel area to the temporary area (channel to Host). Coherency is guaranteed by the SPRAM access contention rules implemented in the SPRAM arbiter (see Section , SPRAM Arbitration). CDC transfers are coherent in respect to the two engines, so the target parameters in the channel area may be shared by channels on them both. During CDC operation, the Host may suffer from 3 up to 11 system clocks wait states (z), and the Microengine(s) may suffer up to 2 microcycle wait-states(aa). CDC accesses are atomic with respect to Microengine(s) accesses to the SPRAM. Even when neither engine is in TST, CDC may suffer up to 4 system clock internal wait-states from SPRAM arbiter, meaning 9 slave wait-states to Host, so that it does not break atomic back- to-back accesses from microengine(s). CDC also cannot break TST preload accesses. Host can initiate CDC back-to-back transfers: there is no need of idle slave cycles between two transfers. z. The maximum number of Host wait states on CDC occurs when both microengines overlap their TSTs, delayed 3 system clocks from each other. aa. One microcycle takes two system clocks. Microengines get wait-states in multiples of microcycles, while Host and CDC wait-states are multiples of system clocks.

Enhanced Time Processing Unit (eTPU2) RM0029 868/1740 Doc ID 15177 Rev 8 CDC Programming The Coherent Dual-parameter Controller Register (see Section , ETPU_CDCR – eTPU Coherent Dual-Parameter Controller Register) is used to configure and initiate CDC transfers between the temporary area and channel parameter area. Host asserts STS bit in order to start the data transfer. CDC then contends for the SPRAM and starts the transfer. When the data transfer is complete, STS returns to 0. Host receives wait-states for writing STS = 1 while CDC contends for SPRAM and during the transfer. The write access ends when CDC finishes the transfer. Host receives wait-states during the CDC transfer. If Host writes ETPU_CDCR with STS = 0 or does not write the STS byte, the CDC transfer does not occur. CDC programming can be summarized as follows: 1. If it is a write transfer, i.e., from Host to channel, write the two parameters into temporary area. 2. Write ETPU_CDCR with STS = 1 and the remaining CDC programming parameters: parameter width (32 or 24 bits, field PWIDTH), transfer direction (read or write, field WR), temporary parameter area base address (field PBBASE), and the absolute addresses of the parameters to be transferred (concatenation of the fields CTBASE and PARAM0/1). 3. If it is a read transfer, i.e., from channel to host, read the two parameters from the temporary area into Host memory/registers. Hardware Semaphores eTPU provides Hardware Semaphores accessible by the Microengine only. It is the responsibility of the application to ensure proper use of the semaphores (i.e., agree upon a specific semaphore and use it properly, to ensure coherency). The eTPU microinstruction set has support for locking and freeing the semaphores, described in Section , Semaphore operations, and this is the only way to access them. There are four semaphores available, which reduces the amount of collisions by assigning unrelated data transfers to different semaphores. Semaphores are used for parameters which can be shared by channels in different engines, and for engine-to-engine synchronization. Semaphores are also the only way to ensure coherent access to parameters shared between the two Microengines. Attempting to lock one semaphore (even not successfully) frees the other locked by the same engine, ensuring one can lock just one semaphore at a time. That prevents deadlock conditions between the two engines. Microcode END command or engine being in idle state (no thread executing) automatically releases all semaphores from one engine side, even if a semaphore lock is done in parallel. However, it is recommended to write the microcode in a way which locks semaphores for the shortest required period, and frees them without waiting for the END command, to improve the performance of the other microengine. Semaphores are free after reset. An engine can only free a sempaphore locked by itself. Semaphore lock requests are always non-blocking, in the sense that they do not suspend the requester in case the semaphore is already locked. The semaphore status after the lock request—indicating if it was successfully locked or not—must be tested through the SMLCK microengine branch condition (see Section , Branch Conditions).

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 869/1740 SPRAM Arbitration Up to four entities can access SPRAM:

Two Microengines (in a dual eTPU engine system)
The Coherent Dual-parameter Controller (CDC)
The Host CPU (direct memory-mapped access) The following rules specify the access priorities for contended access. They keep compatibility with the TPU3 dual-parameter access atomicity, but only between the microengine and CDC (not Host accesses through slave bus). 1. Microengine accesses from the two eTPU engines are interleaved between each other, but not with Host or CDC accesses; 2. The eTPU microengine(s) gives priority for SPRAM accesses to either the Host CPU or the CDC under any of the following conditions: a) The microengine has completed accessing the second parameter in a back-to- back SPRAM access (ab). b) The SPRAM was not accessed during the last arbitration slot for the microengine and the host does not loose the access to the other engine in the current arbitration slot (ac). c) CDC is transferring data, after its first (read) access. Note that the CDC can be in middle of a data transfer of another pair of parameters, unrelated to the ones that microengine tries to access. 3. The eTPU microengine takes priority for SPRAM accesses under either of the following conditions: a) The Host CPU or CDC has done a data trans fer during the last access arbitration slot for the engine ac. Also, the Host CPU does not hold a pending access against the other eTPU microengine. b) The microengine is arbitrating for the access of its second parameter in a back-to- back accessab. All pairs of back-to-back parameter accesses are coherent with respect to Host and CDC (not to the other microengine). The direction (read or write) of any individual access by Host or microengine is irrelevant to the arbitration. The use of Normal or PSE SPRAM area by the Host is also irrelevant to the arbitration. The first parameter preloading in a TST is considered first access by the arbiter, regardless of any access made at the END microinstruction of the previous thread, i.e.: the last access of a thread and the first preload are never considered a back-to-back access. On the other hand, the TST preload accesses are considered back-to-back and are, therefore, atomic with respect to Host or CDC. Note: The Zero SPRAM operation (see Section , Zero SPRAM operation) is considered an SPRAM access for arbitration purposes both on writes and reads; the fact that read SPRAM data is discarded is irrelevant for arbitration. ab. If microengine tries to access the SPRAM in the following microcycles, the third and fourth consecutive accesses are considered the first and second of a new back-to-back dual access. ac. The microengine access slot is between its own T4 and T2 edges (see Section 24.7.1, Microcycle and I/O timing).

Enhanced Time Processing Unit (eTPU2) RM0029 870/1740 Doc ID 15177 Rev 8

24.5.5 Enhanced Channels

Enhanced Channels comprise hardware support for input digital signal processing and output signal generation. Each Channel is associated with one input and one output signal. Enhanced Channel logic is combined with Function microcode (and optionally Angle Mode logic) to implement Channel I/O functionality. eTPU’s Enhanced Channels are capable of dual action, meaning that each channel logic can handle two events at different times and/or cause two separated actions—these actions and events can be mutually dependent (with the first either blocking or enabling the other), or both independent, depending on the programmed Channel Mode. Each Enhanced Channel contains event logic containing two Event Register sets, each set supporting one input and/or output action, the pair implementing dual-action support. Each Event Register set contains two 24 bit registers: Match and Capture. The Match register holds the pending match value which is compared against one of the two time bases by an equal-only/greater-equal comparator. The Capture register captures one of the two time bases as a result of a Match or Transition detection. Service Requests are issued on particular combination of match and capture events, defined by the selected Channel Mode. In the context of the eTPU channels, a Match is a comparison between a time base value and a channel Match register. If those two values are coincident, or the time base value is greater than the value of the Match register, a Match Event occurs. Depending on the channel mode of operation and current state of the channel logic, the match event may be recognized, i.e., change the state of the channel, or be ignored. A match event recognized by the channel logic is called a Match Recognition. Match Recognitions can cause, also depending on Channel Mode and current state, the channel to request service, configuring a Match Service Request. eTPU uses two kinds of comparator to assert a Match Event: an Equal comparator, in which both the Match Register and the value of the selected time base must match exactly, and a Greater-Equal comparator. The Greater-Equal comparator considers any time base value between the range [N: N+0x800000-1] as a valid match against the value of N in the Match Register, even when the value N+0x800000-1 wraps around the point of origin (0x0). Refer to Figure 526 for an illustration of the matching values on a Greater-Equal comparator. The second source of events for the eTPU channel is a Transition detected at the corresponding channel’s input signal. Two distinct Transition detections can be programmed individually for each channel, allowing recognition of all possible combinations of edge detection. It is also possible to check the sampled state of an input signal upon the occurrence of a Match: the sampling of the expected value is treated as a Transition, even if the input signal did not necessarily toggled at the time of the Match, or at any time at all. Like Match Events, Transitions Events may or not be recognized by the channel logic. When they are, a Transition Detection occurs. As well as Match Recognitions, Transition Detections can issue a Channel Service Request, depending on Channel Mode and current state. Transition Detections and Match Recognitions are sometimes simply called Transitions and Matches throughout this document, for short. Input and output signals can be processed separately by the channel logic and microcode, and can also be combined such that Matches and Transitions are used to cause output signal actions. The output signals can also be directly controlled by microcode. Many event combinations are allowed for a channel, given the possibility of configuring pairs of

Modes, exploring all the capabilities mentioned here. with the same previous value, a channel is selected and its flags and registers are updated. For further detail, see Section , Channel Selection Register – CHAN. Figure 526. Greater-Equal Comparator Channel Link for a complete description of this mechanism. channel service routine, which is the sequence of microinstructions that is called a Thread. For further detail, refer to Section 24.5.1, Functions and threads. signal. Output Buffer Enable is meant to control output MCU pad signal driver. A high level diagram of Channel logic and registers is shown in Figure 527. NOTE: the value opposed to N (N+0x800000) does not cause a match.

Figure 527. Channel Logic Block Diagram

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 873/1740 Channel Registers and Flags Channel configuration and control registers can be divided in the following groups:

Host Configuration and Control registers, which define channel Function and parameter allocation in SPRAM, input signal filtering, manage Host interrupts, and are used for Host Service Requests; they can only be accessed by Host, except for the Function Mode bits which can be also tested by microcode.
Event Registers, which can only be accessed by eTPU Microengine, through dedicated Channel Control microinstruction operations (see Section , Channel control and configuration microoperations); these registers are directly used to implement channel functionality, and include channel event status latches which can be directly tested by Microengine branch instructions.
Pin Control registers, which basically define pin state and transition polarity (but not input signal filtering); they are accessible only by dedicated Channel Control microinstruction operations.
Link registers, which implement the channel link mechanism that allows one channel to request service to another one; they are accessible only by microinstruction operations.
General Channel registers: CHAN, SRI, Flag0/1, PDCM, UDCM. Most of those registers are channel exclusive, i.e., there is one copy of them for each channel. Microcode can access registers from only one channel at a time. The Channel Selection (CHAN) register (see Section , Channel Selection Register – CHAN), accessible only by microcode, defines the channel whose registers are being accessed, with exception of link register and function mode. CHAN register assumes the value of the channel to be serviced at the beginning of TST. The Service Request Inhibit (SRI) register controls the generation of Service Requests on matches and transitions, also affecting channel logic behavior. For a full description see Section , SRI – Match/Transition Service Request Inhibit Latch. Flag0/1 are used to select channel service threads based on channel software state. See Section , Flag1,Flag0 – Channel “state resolution” flags, for more details. Host Configuration and Control registers are described in Section 24.4.7, Channel configuration and control registers. Time Base configuration is common to all channels, and described in Section 24.5.6, Time Bases. Time Base selection for matches and captures, however, is individual to each channel, and is part of the Event Registers. Link registers are described in Section , Channel Link. The following sections describe the Event Registers and Pin Control registers.

Enhanced Time Processing Unit (eTPU2) RM0029 874/1740 Doc ID 15177 Rev 8 ER – Event Registers Each channel contains two identical Event Register sets, named ERA and ERB, corresponding to the two actions supported. Each Event Register set contains:

A 24-bit Match register (Match A or Match B), which holds a match value. This value is compared against the selected match time base (TCR1 or TCR2).
A 24-bit Capture register (CaptureA or CaptureB), which samples the selected capture time base (TCR1 or TCR2)
A Time Base Selection register (TBSA or TBSB)
A Match Recognition status flag (or latch) (MRLA or MRLB)
A Match Recognition Enable latch (MRLEA or MRLEB)
A Transition Detection flag (or latch) (TDLA or TDLB)
A Transition Continuous Capture enable (TCCEA only) ERA and ERB are associated with the first and second events in double action modes, not necessarily in that order. The order of Match events associated with ERA and ERB depends on the programmed channel mode, the MatchA and MatchB values, and the timebases selected by TBSA and TBSB. Similarly, the order of Transition events associated with ERA and ERB depends on the programmed channel mode, and the transition detection selected by IPACA and IPACB. These registers are directly or indirectly accessed by the microcode. TBSA and TBSB registers are defined in Section , TBSA and TBSB – Time Base Selection Registers . The other registers are explained in Section , Match Recognition and Section , Transition Detection and Time Base Capture. Access to the Event Registers is qualified by the channel currently selected by the microengine (i.e., the channel value currently in the CHAN register). During the channel transition period (automatic CHAN assignment), or whenever CHAN is written by microcode, Capture values of the new selected channel are sampled into Microengine registers ERTA and ERTB, therefore becoming visible to the microcode. At the same time, updated values of MRLA, MRLB, TDLA and TDLB are sampled into the branch logic, making the register values and the flags coherent with respect to each other and with the thread selected by the Scheduler (ad). Note: The Function Mode bits are also sampled from the Host interface on Time Slot Transition, so that they remain constant to microengine even when Host changes them. During service, the microcode can access updated values of the Event Registers of any channel by writing the channel number to CHAN. Writing CHAN with the same value (CHAN := CHAN) updates ERTA and ERTB with the new captured values, the branch logic with updated MRLA/B and TDLA/B flags. Writing CHAN with a different value does the same with the values from the newly selected channel. Match values are also accessed through ERTA and ERTB Microengine registers, which are copied to/from the channel MatchA and MatchB registers by specific microinstruction operations. Microcode writes to the flags and selections (MRLA/B, TDLA/B and TBSA/B) are immediately effective to the channel. The MRLA/B and TDLA/B branch conditions are also ad. The thread selected is determined by the Entry Point which, in turn, is determi ned partially by the channel latches. See Section , Entry point address generation .

when respective Match register is updated from ERTA/B, and its negation is immediate. Table 470 summarizes Event Registers accesses. see Section , Match Recognition. Table 470. Event Registers microcode accesses CHAN assignment no T2ABD n.a.

See Section 24.5.9, Microinstruction set .
n.a. means that value of the register is undetermined after reset.

Selection of the timebase (TCR1 or TCR2) to be compared against the match values in MatchA and/or MatchB registers.
Selection of the timebase (TCR1 or TCR2) to be captured in the CaptureA and/or CaptureB registers by a match or transition detection event.
Selection of comparator mode to be used with MatchA and MatchB registers: equal- only or greater-equal. After reset TBSA/B are 000. Table 471 shows values of TBSA and TBSB for configuration selection. Note that the time base selection for capture is independent of the time base selected for matches. TBSA/B are written through the microcode fields TBSA/B (see Section , Comparator and time base selection). Note that microcode field TBSA is also used to control the OBE pin control register (see Section , Pin Control Registers), which is separate from the TBSA register. MRLA/B – Match Recognition Latches See Section , MRLA/B – Match Recognition Latches. MRLEA/B – Match Recognition Latch Enable See Section , MRLEA/B – Match Recognition Latch Enable . TDLA/B – Transition Detection Latch See Section , TDLA/B – Transition Detect Latches. TCCEA – Transition Continuous Capture Enable See Section , TCCEA – Transition Continuous Capture Enable. Pin Control Registers Pin Control Registers are replicated one per channel, accessed only by microcode and qualified by the CHAN register in the same way as Event Registers. Table 472 lists Pin Control Registers, explained in following subsections, and their accesses.

Table 471. TBSA/B Programming States Table 472. Pin Control Registers microcode accesses

Section , Transition Detection and Time Base Capture. of the corresponding Match (Match A used for IPACA, Match B used for IPACB).

See Section 24.5.9, Microinstruction set .
PSS is PSTI or PSTO sampled on CHAN assignments and at thread start.
PRSS is PSTI sampled on channel service request.

events. The PSTO register stores the driven pin state determined by the Pin Control logic. (using TBSA field) to make the pad propagate the PSTO register output to the actual pin. driven pin state (see Figure 528). PSTO is set to 0 on reset. For details refer to Section , Channel control and configuration microoperations. Table 473. IPACA/B and OPACA/B Encoding

000 Do not detect transitions Do not change output signal

001 Detect rising edge only Match (1) sets output signal high

010 Detect falling edge only Match (1) sets output signal low

011 Detect either edge Match (1) toggles output signal

100 Detect input signal = 0 on Match (1)

Match A is used for IPACA/OPACA, and Match B for IPACB/OPACB.

101 Detect input signal = 1 on Match (1) Transition detection sets output signal high

On the microinstruction fields IPACA/B and OPACA/ B this value is neutral, meaning that IPAC/OPAC

00 Force pin state according to

OPACA (PSCS = 0) or OPACB (PSCS = 1).

Mode (UDCM). For details refer to Section , Match/Transition Pin Action Conflict Resolution. ae. The filter can be bypassed. af. Output Buffer Enable: there is one independent OBE signal for each channel. Table 475. TBSA Output Buffer control

Figure 528. Pin State Input/Output Logic per channel. Table 476 summarizes the registers and access options.

time by microengine writing into CHAN register.

Conditional branch using LSR (see Section , LINK Register) or Function Mode (Section , ETPU_CxSCR – eTPU Channel x Status Control Register).
Negate channel flag LSR, Interrupt CPU and Data Transfer Request (see Section , Channel interrupt and data transfer requests). When CHAN register is written, accesses are qualified by the new CHAN register value from the instruction following CHAN assignment on, except CaptureA/B sampling into ERTA/B and Match register writing from ERTA/B (see Section , CHAN assignment, Read Match and ERWA/B). Writing CHAN (including with the same value, CHAN:= CHAN) updates ERTA and ERTB with the new captured values, the branch logic with updated MRLA/B and TDLA/B flags. Table 477 shows the commands, flags and registers selected by the CHAN register value

Table 476. General Channel registers microcode access

See Section 24.5.9, Microinstruction set .
CHAN is common to all channels in the engine.

Table 477. CHAN-selected features

matches and transitions. For a complete description see Section , Channel Modes. PDCM for each channel, initialized with 1100 on reset. UDCM – User Defined Channel Mode).

In TPU, these conditions retained the old values.
Refer to Section , Branch operations
If write Match (ERWA/B) occurs at the same time of a CHAN assignment, the channel which is target of the write is the one

selected by the new CHAN value. See Section , CHAN assignment, Read Match and ERWA/B .

can be independently programmed. microengine registers (see Section , Write Channel Match and UDCM Registers). Figure 529. UDCM Register Table 478. PDCM encoding

1010 User Defined Channel Mode

This is the reset value, also compatible with TPU channel behavior.
This value is used as a neutral (do not change) value in the PDCM microinstruction field.

2 TSR TCA

Enhanced Time Processing Unit (eTPU2) RM0029 884/1740 Doc ID 15177 Rev 8 MRLA/B or TDLA/B microcode branch tests nor Entry Table selection(ag). SRI is asserted during reset and is controlled by microcode field MTD. To unburden the microengine, SRI asserted configures a channel “dumb” regarding the servicing of match and capture channel service requests. Even with SRI = 1, TDLA/B and MRLA/B can still be asserted, and the level specified by the OPAC (Output Pin Action Control) registers will be output to the pin. Flag1,Flag0 – Channel “state resolution” flags Each channel has a pair of flags, simply called Flag0 and Flag1, that can be set/reset by microcode through microinstruction field FLC. FLC sets/resets Flag0/1 of the channel selected by CHAN. These flags can be tested by microcode, and are also used to resolve the microcode entry point for the channel service (see Section , Entry points). Flag0 and Flag1 are, so, typically used for fast state resolution. FLC microinstruction field also allows Flag1,Flag0 to be copied from selected bits of P register high byte, which is also meant to be used to hold application state. Flag0 and Flag1 are both zero out of reset. Match Recognition The match operation is performed every microcycle by comparing the channel MatchA and MatchB registers against the value of the TCR bus specified for each match. TCR1 or TCR2 bus is selected according to TBSA and TBSB fields. Both results have effect on the next clock cycle (see Section 24.7.1, Microcycle and I/O timing). A Match A/B event is qualified by a set of match enabling conditions to the Match Recognition Registers MRLA/B. To recognize the match and assert these registers, the following match enabling conditions are required:

For IPACA/B = 0xx, Match Enable Flag (MEF), qualified by the channel currently being serviced must be asserted. For IPACA/B = 1xx, Match A/B is always enabled (even during Time Slot Transition (TST)), regardless of the state of the Match Enable Flag (MEF). See Section , MEF – Match Enable Flag for the conditions of MEF assertion.
Match Recognition Latch Enable 1/2 (MRLEA/B) is asserted. A match event recognition may only occur if its corresponding MRLEA/B bit is set, which only happens upon a write to a channel match register by the microcode, copied from ERTA/B. MRLEA/B is negated when the respective match occurs or, in some double match channel modes, when a match for the other Match register occurs. It ensures that the greater-equal comparison will not cause additional matches (ah).
In selected modes (see Section , Channel Modes), the particular conditions of MRL and TDL flags of the other event, i.e: – MRLA, TDLA enable or block MRLB; – MRLB, TDLB enable or block MRLA.
The respective MRL is negated.
In selected modes (see Section , Channel Modes), the state of its respective TDL flag. If the Match A and/or Match B conditions are met, the channel immediately forces the pin state if specified by the appropriate OPACA/B registers (Output Pin Action Control 1/2) and, in some cases, by IPACA/B registers. Refer to Section , IPACA,IPACB and OPACA,OPACB – Input and Output Pin Action Control Registers. ag. In TPU, SRI also blocked TDL and MDL branches and enabled any transition to capture time base. ah. Microcode can also negate MRLEA/B.

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 885/1740 If both Match A and Match B events occur at the same time, with conflicting pin actions, the priority over the pin action is mode dependent. For further details on pin action resolution refer to Section , Match/Transition Pin Action Conflict Resolution. MRLA/B – Match Recognition Latches MRLA/B indicate the recognition of a match event detected by the comparator. They can be asserted either on T2 or T4 (see Section 24.7.1, Microcycle and I/O timing). Assertion of MRLA/B issues a match Service Request in specific channel modes, depending on previous events and state of SRI. After reset MRLA and MRLB are both negated. When MRLA or MRLB is asserted, it may change the output signal level according to the Input and Output Pin Action Control registers (refer to Section , IPACA,IPACB and OPACA,OPACB – Input and Output Pin Action Control Registers). Assertion of MRLA/B causes a capture of one or two time bases, according to the selected mode capturing scheme (see Section , Transition Detection and Time Base Capture). A match recognition is self-blocking, regardless of Channel Mode: once MRLA (MRLB) has been asserted, it negates its associated MRLEA (MRLEB) register, preventing future match recognitions, until the associated match register is rewritten by microcode. The microcode has to enable new matches by updating the new match value in the MatchA (MatchB) register (ai). In addition, assertion of MRLA/B can block its twin MRLB/A, depending on the channel mode. In some double match blocking channel modes, Match A/B event blocks the occurrence of Match B/A in a “first win” scheme. It is the transition from 0 to 1 in MRL that causes the Match actions: apart from MRLEA/B negation(s), no action due to a Match occurs if MRL was already set to 1, even if the other MRL assert conditions are satisfied. However, if a Match and a microoperation negating its corresponding MRL occur at the same time, MRL negation by microcode overrides its assertion, but any dependable captures and pin action occurs anyway (if MRL was already negated before), and also the negation of MRLE(s) (the respective one and, in some channel modes, the other, regardless of MRL state before). Note that MRLE must have been set before (by writing a new Match value). MEF – Match Enable Flag MEF is a one-bit latch that is unique for all channels in an engine. MEF can selectively enable assertion of MRLA/B, depending on the IPACA/B field. For IPACA/B = 0xx, MEF = 1 enables assertion of MRLA/B for the scheduled channel during service. For IPACA/B = 1xx, Match A/B is always enabled, regardless the state of the MEF, but it still depends on the other Match recognition conditions. Matches of channels not being serviced are never disabled by MEF. MEF is not accessible by Microengine or Host. MEF is negated for one microcycle in the middle of the time slot transition period. After two microcycles (plus wait-states) into TST, the ME bit in the entry point is copied to MEF to allow selective enabling of MRL for each thread (refer to Section , Time slot transition). MEF is asserted unconditionally soon after a thread ends. If a channel service needs to postpone a programmed match, MEF assures that microcode wins the race against match event after time slot transition (only for IPAC = 0xx). ai. Before that, microcode should also negate MRLA (MRLB), otherwise an old match may be recognized by the scheduler and serviced as a new one

Enhanced Time Processing Unit (eTPU2) RM0029 886/1740 Doc ID 15177 Rev 8 Note that a match event may be lost during the periods when MEF is negated only if:

the match comparator is configured for “equal-only” behavior, and
IPACA/B = 0xx, and
TCR increments at the rate of system clock divided by 2 or faster. When the comparator is configured as “greater-equal”, the match event that occurred when MEF was negated may be recognized after MEF is asserted again, due to the “greater than” condition. MRLEA/B – Match Recognition Latch Enable MRLEA/B is negated upon the assertion of its respective MRLA/B. In blocking match channel modes it may also be negated together with the assertion of the twin MRLB/A. The MRLEA/B bits ensure that data captured due to the first match event will not be overwritten when MRLA/B is negated: due to greater-equal comparison, the match condition continues to be true, but should not cause another capture event. In addition to negation by local match event, the microcode can negate both MRLEA and MRLEB, to block pending matches, and also MRLA/B, individually. This action will prevent future match events from the selected channel. Writing the MatchA/B registers by microcode to schedule the next match values sets MRLEA and/or MRLEB and enables new matches. This setting overrides the MRLE negation conditions due to channel logic or microcode (see Section , Channel Modes). By combining write to Match A/B with MRLEA/B negation microinstructions, the microcode can negate one MRLE while asserting the other. Note: If the MRLE negation conditions continue after writing MatchA/B registers, the respective MRLE does not keep asserted. For instance, if MRL = 1 and a match is programmed for a time value in the past during a thread with MEF = 1, then MRLE will be cleared soon after MatchA/B is written, even though a match does not occur (because MRL was already asserted, neither captures nor pin toggles occur). When the match register is updated (with MRLE already asserted before) and field MRLA/B = 1 (no clear, see Section , Clear transition/match event registers) and MRLA/B flag is zero, the eTPU behaves exactly as the TPU, that is: a match that comes concurrently with the rewrite of the match register, matching the old value, sets the MRL, as if the setting of the MRLE due to match register write had precedence over its clear by the match at that moment. After this simultaneous operation, the MRLE value stays at 1, and the captured time base value, if any, reflects the match value. When the match register is updated (with MRLE already asserted before) and field MRLA/B = 0 (clear MRL, see Section , Clear transition/match event registers) and MRLA/B flag is zero, the match captures will occur, the MRLA/B flag will keep negated, and MRLE will stay asserted. If a match is reprogrammed on TCR1 running at T2/T4 timing (TCR1CS = 1, see Section , ETPU_TBCR – eTPU Time Base Configuration Register), a match can occur after MRLA/B is cleared, together with the set of MRLE. In this case, both MRL and MRLE will be set, and a match service request will occur if enabled. However, the match happened on the old match value, not on the new (reprogrammed) one. In order to prevent this ambiguity to the code that services the match, it is advisable to clear the MRLE (besides MRL) together with the match reprogramming, avoiding the match on the old value to occur while the new match value is being written. The set of the MRLE due to match reprogramming prevails over the MRLE clear, thus allowing the new programmed match to occur.

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 887/1740 Transition Detection and Time Base Capture Time Base Capture(s) occur when the value of a specified TCR is sampled into the CaptureA and/or CaptureB register. TBSA[1] and TBSB[1] select which TCR will be captured in CaptureA and CaptureB, respectively. A capture event may occur due to either of the following events:

The assertion condition of Match Recognition Latch (MRL), even if MRL is simultaneously negated by microcode
The assertion condition of Transition Detection Latch (TDL), even if TDL is simultaneously negated by microcode.
Any Transition Event specified by IPACA if both the Transition Detection Latch TDLA and Transition Continuous Capture Enable TCCEA are asserted. A capture event occurs together with the assertion of MRL or TDL either on T2 or T4 positive edges, and captures the time-base value that caused the match, even if TCR1/2 increments concurrently with the assertion (see Section 24.7.1, Microcycle and I/O timing) (aj). MRLA/B and TDLA may, depending on the channel mode, inhibit the capture of the second event’s TCR into CaptureA/B. As a general rule, values captured by signal transitions are not overwritten by values captured by match events. When the enable bit TCCEA is asserted, captures due to Transition Events also occur after TDLA is asserted. Those captures happen on transition events specified by IPACA, and the TCR value is saved into CaptureA register only. The capturing scheme is defined by the Channel Mode programmed at register PDCM, or at register UDCM when User Defined Channel Mode is selected. For more information on mode-dependent capture schemes refer to Section , Channel Modes. TDLA/B – Transition Detect Latches TDLA/B indicate detection of specific transition occurrences on a channel input signal. TDLA and TDLB assertion causes service request in single and double transition predefined modes, respectively. TDLB assertion does not cause Service Request in single transition predefined modes, and TDLA assertion does not cause Service request in double transition predefined modes. In single transition channel predefined modes TDLB can be asserted on the second transition, but does not generate Service Request. Yet on predefined modes, TDLB assertion is enabled only if TDLA is asserted to detect an ordered input signal double transition. All the restrictions above, however, may be overridden by using the User Defined Channel Mode. The IPACA and IPACB registers indicate the programmed edges of the first and second detected transition, respectively. The sampling of a determined value (0 or 1) on the input signal due the occurrence of a Match is also treated as a “transition”, depending on IPACA/B programming (see Section , IPACA,IPACB and OPACA,OPACB – Input and Output Pin Action Control Registers). When using a channel mode where the transition1 is initially blocked and IPACA is programmed to detect such “transitions”, the occurrence of a Match A only unblocks the transition after the sampling. It means that the transition on the first Match (IPACA configurations 100 and 101) is not effective on predefined modes where Transition A is enabled by Match A (m2_st, m2_dt, m2_o_st and m2_o_dt) or user-defined modes with UDCM bit M1ET asserted. A aj. In TPU3, when TCR1 was counting at maximum rate of system clock divided by 2, the next value was captured.

Enhanced Time Processing Unit (eTPU2) RM0029 888/1740 Doc ID 15177 Rev 8 Transition A can still happen after the Match A, however, if MatchA register is reprogrammed without clearing MRLA. TDLA/B assertion conditions initiates a capture event of one or both selected TCR buses. TDLA or TDLB transition event generates a Service Request, depending on channel mode, previous events and the state of SRI. For more information on the service request scheme, refer to Section , Entry point address generation, and Section , Channel Modes. Assertion of TDLA/B occurs on either T2 or T4 positive edges. The capture event occurs on the same clock, and captures the time base value present when TDLA/B was asserted aj. TDLA and TDLB are negated during reset and may also be negated independently by microcode. TDLA/B is reset by no way other than reset and microcode. It is the transition from 0 to 1 in TDL that causes the Transition actions: even if TDL assert conditions are satisfied, no action due to a Transition occurs if TDL was already set to 1. However, if a Transition and a microoperation negating TDLs occur at the same time and TDL was already negated, TDL negation by microcode overrides its assertion, but any dependable captures and pin action occurs anyway. TCCEA – Transition Continuous Capture Enable TCCEA enables capture from transitions after the TDLA flag is set. TCCEA is negated on reset, so that a capture occurs only when TDLA asserts. TCCEA can be set and reset by microcode only, through the instruction field MTD (see Section , Disable match and transition service requests). It can only be set together with inhibiting of the channel service requests (SRI = 1) (ak). When TCCEA is asserted, the transition events specified by IPACA that occur after TDLA is set also cause captures into the CaptureA register only. However, output actions related to transition events are still blocked by TDLA. Channel Modes The Enhanced Channels support various modes of operation combining Match A/B recognition and transition detection events which set MRLA/B and TDLA/B. The channel mode is individually set for each channel by eTPU microcode, through the PDCM register (see Section , PDCM – Predefined Channel Mode). The PDCM register selects among a set of 13 predefined channel modes, and also a user-defined channel mode. The order in which events occur, combined with assigned channel mode, establish which following event detections are inhibited and/or enabled, as well as the actions taken: Time Base capture, flag setting (MRLA/B, TDLA/B), match disabling (MRLEA/B), output signal transition, and Service Request. Those channel mode characteristics are fixed in the predefined modes, but can be individually programmed in the user-defined channel mode. A generic description of channel modes from the usage point of view can be found in Section , Channel modes overview. Each mode is named with a mnemonic acronym for terse reference. The individual programmed attributes of the user-programmable channel mode are also described. The modes are used differently for input and output signals, as explained in Section , Predefined Channel Modes on Input Signal Processing, and Section , Channel Modes on Output Signal Generation. Modes also allow combining input processing and output ak. TCCEA provides compatibility with TPU when service request is inhibited.

mode can be found in Section 24.7.3, Predefined channel mode summary. respect to conditions for event blocking, enabling, capture, and service requests.

TSR (1 bit) defines Service Requests issued by Transitions, as shown in Table 480.
MSR (2 bits) defines Service Requests issued by Matches, as shown in Table 479.
TCAP (1 bit) defines time base captures caused by Transitions, as shown in Table 480.
MCAP (1bit) defines time base captures caused by Matches, as shown in Table 481.
M1ET, M1EM2, M1BM2, M2BM1, M2BT, T1BM1, T2BM1, TBM2, T1ET2 (1 bit each) define Match and Transition reciprocal blocking and enabling, as well as Transition ordering, as shown in Table 482 and Table 483. Table 484 shows the decoded values of those control signals for each predefined channel mode. The first column shows the mnemonic reference for the predefined channel modes described in the following sections. Changing PDCM or the UDCM when user mode is selected may set or reset any of the channel flags, or issue captures and service requests, so it is advisable to switch channel modes only in a quiescent channel state, with channel flags MRLEA/B, TDLA/B, MRLA/B cleared. Furthermore, an event flag asserted in one mode may keep asserted after the mode programming change, even if the flag is impossible to be set in the new mode.

Table 479. MSR[1:0] signals – Match Service Requests

2nd Match means the Match that happens after the 1st Match in time, either Match A or Match B.

Table 480. TCAP and TSR signals – Transition Captures and Service Requests 1 Transition A captures corresponding Time Base. Transition B captures corresponding Time Base.

1st Transition means the Transitio n that happens first in time, either Transition A or Transition B.
Match capture(s) never overwrites a Transition capture. Transition captures can al ways override a Match capture.
2nd Transition means the Transition that happens second in time, either Transition A or Transition B

Table 481. MCAP signal – Match Capture

0 Match A captures corresponding Time Base;

Match capture(s) never overrides a Transition capture. Transition capt ures can always override a Match

Table 482. TBM2 signal – Transition Blocks Match B

0 Transition A Blocks Match B

1 Transition B Blocks Match B

Table 483. M1ET, M1EM2, M1BM2, M2BM1, M2BT signals

The initial condition of M1EM2 prevails over M1 BM2, while M1BM2 blocking prevails over M1EM2

combination is used in single-match modes (sm_*).

Blocking of one Match by the other is done through MRLEs.
Matches always block themselves by resetting their own MRLEs (Match A always blocks Match A, Match B

Table 484. Predefined channel mode control signals decoding

Signals TSR, TCAP and TBM2 replace the signal DTM used in previous eTPU versions.
bm_dt and sm_dt are exceptions in the match blocking logic by transitions. See Section , Both Match Request Modes

(bm_st, bm_dt), and Section , Single match modes (sm_st, sm_dt) .

sm_st_e is an exception in the capture scheme. See Section , Single match enhanced mode (sm_st_e) .

Figure 530. Channel Mode Logic and Event Flags all control signals active high.

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 893/1740 Channel modes overview Predefined channel modes are divided according to the way they treat transitions in two basic modes:

Single Transition Modes (mnemonic suffix _st): In these modes the first transition (flagged in TDLA) issues a service request, and captures both time bases (selected by TBSA[1] and TBSB[1]) except on sm_st_e. The second transition (flagged in TDLB) does not issue a service request, but it captures time base selected by TBSB[1], except on sm_st_e.
Double Transition Modes (mnemonic suffix _dt): In these modes the second transition (flagged in TDLB) issues a service request, and each transition captures its own selected time base (Transition A and Transition B capture time bases selected by TBSA[1] and TBSB[1], respectively). In predefined modes, Transition B is always (but not only) enabled by Transition A, so that transitions are always ordered: TDLA is set on the first transition and TDLB on the second. Unordered transitions are possible with user-defined mode, when UDCM bit T1ET2 = 0. Matches are generally not ordered, except on specific ordered match modes m2_o_st and m2_o_dt. Match capture(s) never overrides a Transition capture, while Transition captures can always override a Match capture, either in predefined or user-defined modes. The following general rules apply to both predefined and user-defined modes:
Blocking of one Match by the other, when it occurs, is done through MRLEs.
Matches always block themselves by resetting their own MRLEs (Match A always blocks Match A, Match B always blocks Match B). Predefined modes differ mostly by the way matches affects and are affected by other matches and transitions, as explained in next sections. However, some general rules on Match blocking apply:
Match B is blocked by first transition (TDLA) in single transition modes, and by second transition (TDLB) in double transition modes.
Both Matches are blocked by first transition in single transition modes. Note: The rules above and in following sections may be overruled by the state of the channel latches if they are set/reset by microcode or if channel mode is changed. Care must be taken to change channel modes, and is advisable to reset channel flags MRLA/B, TDLA/B and MRLEA/B before writing PDCM, or to UDCM when user-defined mode is selected. Either Match, Blocking Modes (em_b_st, em_b_dt) In these modes the first match recognition that occurs blocks the other match recognition and generates a service request. They end up with one service request for two programmed match recognitions where only the first match recognition has an actual effect. If both match recognitions occur at the same time, both MRLA and MRLB are set, before the mutual blocking takes effect.

Figure 531. Either Match, Blocking Modes (em_b_st, em_b_dt) all control signals active high.

Figure 532. Either Match, Non Blocking Modes (em_nb_st, em_nb_dt) for selecting the pin action. all control signals active high.

Figure 533. Match B Request Modes (m2_st, m2_dt) all control signals active high.

Figure 534. Both Match Request Modes (bm_st, bm_dt) recognition (ordered 1->2). Match A asserts MRLA and enables Match B and transitions. Match B asserts MRLB, generates a match service request, and blocks both transitions. all control signals active high.

Figure 535. Ordered Modes with Match B Request (m2_o_st, m2_o_dt) Single match modes support single or double transition with single match recognition. MRLB is never set, and MRLEB has no effect. all control signals active high.

Figure 536. Single match modes (sm_st, sm_dt) bases at once due to a match recognition). all control signals active high.

Figure 537. Single match enhanced mode (sm_st_e) all control signals active high.

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 901/1740 Predefined Channel Modes on Input Signal Processing When processing an input signal, the predefined channel modes can be classified in the following primary mode groups:

Single Transition, Single Match: em_b_st, sm_st, sm_st_e
Single Transition, Double Match: em_nb_st, bm_st, m2_st, m2_o_st
Double Transition, Single Match: em_b_dt, sm_dt
Double Transition, Double Match: em_nb_dt, bm_dt, m2_dt, m2_o_dt In single transition modes, TDLA assertion may capture both time bases at once, while in double transition modes each transition captures its related time base in its related capture register. Double transition is always ordered, i.e TDLB is enabled by TDLA and generates the service request. The channel logic supports various input modes with combinations of single/double transition and single/double match, explained in the following subsections. Either Match, Blocking, Single Transition (em_b_st) On an input signal, this mode provides double timeout mechanism on a programmed transition edge with two timebases. The signal transition blocks both pending matches, indicating that no timeout condition occurred. The two match recognitions block each other, giving good separation in the entry table as to which match recognition caused the first timeout condition, and generating only one service request. Either match performs timebase captures which do not overwrite captures by transitions. Either Match, Blocking, Double Transition (em_b_dt) In double transition mode each transition is related to one match recognition. TDLA assertion captures its related timebase, blocks Match A and enables TDLB. TDLB assertion blocks Match B, captures its related timebase and generates a service request. Match recognitions block each other, so if there is a match timeout condition on TDLA, only one match service request is generated. This mode is good for qualifying two signal transitions by match timeout mechanisms, with one service request. Note that although TDLA assertion does not block Match B recognition, the value captured in CaptureA by TDLA assertion is not overwritten by this recognition. The second transition blocks Match B. Either match performs timebase captures which do not overwrite captures by transitions. Either Match, Non Blocking, Single Transition (em_nb_st) On an input signal, this is a double timeout mechanism of independent match recognitions of two different timebases. The match recognitions do not block each other, such that the microcode can check if one or two match recognitions occurred before their related signal transition. The signal transition detection (by IPACA) asserts TDLA, blocks both matches, captures both time bases and generates a transition service request, indicating that none of the two timeout conditions occurred. Any combination can be easily resolved by microcode (for example, signal transition after Match A and before Match B, or signal transition after both Match A and Match B). Another possible use of this mode is allocating one match recognition for transition timeout and the other for another non-critical timed task, adding functionality to a single channel. Since the transition detection blocks both match recognitions, the match recognition of the other timed task is based on the fact that the comparator checks greater-equal conditions. It may be delayed if it occurs in the period between the signal transition detection (which blocks it) and the time TDLA is negated by microcode. If matches are enabled during the

Enhanced Time Processing Unit (eTPU2) RM0029 902/1740 Doc ID 15177 Rev 8 service, the same code can check if the match recognition of the timed task occurred in this period, by negating TDLA and writing to the CHAN register its own value (in order to update the MRLA flag in the branch logic). Either Match, Non Blocking, Double Transition (em_nb_dt) In this mode each transition is related to one match recognition, and the match recognitions are independent of each other. This mode can be used to give independent timeout conditions for the first and the second signal transition recognitions, and call service in any case of any timeout condition. The first transition detection programmed in IPACA sets TDLA, captures its related timebase, blocks Match A recognition and enables TDLB assertion. The second transition detection programmed in IPACB sets TDLB, blocks Match B recognition, captures its related timebase and generates a service request. Any match recognition that occurs captures its related time base and generates a match service request, independent on the other match recognition. Match B Request, Single Transition (m2_st) On an input signal, this mode provides an open window filter for a single signal transition. MRLA assertion opens the window, and enables transition detection on TDLA from this time on. MRLB assertion blocks Match A (by negating MRLEA), providing conditional window opening, because transitions are indirectly blocked. It also generates service request, but if it happens after Match A it does not block transitions, providing a non-blocking timeout mechanism for the estimated signal transition time (typically it indicates a missing transition, or mis-prediction of the transition time). Transitions can be detected from the microcycle following MRLA assertion. The Transition A detection asserts TDLA, blocks both matches, captures both timebases and generates service request. Using this mode, the channel can replace software open window filtering of qualified transitions with the channel hardware window. The window opening and timeout can be scheduled for any of the two time bases or combination of them. Typically, Match A will be used to open a prediction window, and Match B will be used as a timeout condition which does not close the prediction window. This configuration improves noise immunity from early signal transitions, and reduces the probability for blocking late signal transitions due to timeout mis-prediction. Using these conditions, the microcode can easily resolve the state:

If TDLA and MRLA are asserted and MRLB negated, signal transition is in the expected range.
If MRLA and MRLB are both asserted, and TDLA is asserted, the signal transition had a timeout condition due to Match B mis-prediction.
If MRLB is asserted and TDLA negated, a timeout condition occurred, and the expected signal transition had not occurred yet.
If MRLA is negated and MRLB is asserted, the conditional window did not open at all (for example: a time window is open only after a specific angle, otherwise it is not opened). Match B Request, Double Transition (m2_dt) This mode is used as an open window filter for two signal transitions. In this case the Match A recognition opens the window (unless Match B recognition occurred first), and Match B recognition blocks Match A and generates a match service request. It is similar to m2_st, but in this case, it is the second transition that blocks Match B. MRLB assertion is a global

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 903/1740 timeout condition for the two pulses. Like m2_st, MRLB can conditionally eliminate the window from opening. Using the TDLA, TDLB, MRLA and MRLB conditions, the microcode can easily resolve the state, in a similar manner as m2_st, with additional information on the second transition (TDLB). Both Match Request, Single Transition (bm_st) On an input signal, this is a double timeout mechanism on two different time bases. Both match recognitions must occur before the signal transition to generate a match timeout service request. Assertion of TDLA blocks both Match A and Match B recognitions, and captures both time bases, indicating there was no double timeout condition from both time bases. Using the same timebase implements two timeout conditions, the first only sets its related MRL and the second generates a service request. Using these flags allows the microcode to check if one or both match recognitions precede the signal transition. Both Match Request, Double Transition (bm_dt) In this mode the first transition detection does not block matches, since both match recognitions are required to generate a match service request. The second transition detection asserts TDLB, blocks Match A and Match B, captures its related timebase and generates transition service request. In this mode, a Match A recognition which occurs after the assertion of TDLA does not capture a new value in CaptureA, to preserve the actual signal transition time. Assertion of TDLA, however, always captures its related timebase. This mode allows putting a double match timeout condition on the second transition. Typically, a pulse trailing edge timing can be checked against two time bases, to indicate if the pulse has not ended when both MRLA and MRLB are asserted. When a transition service request is generated by TDLB assertion, the state of MRLA and MRLB indicates which timeout condition occurred, if any. Ordered Mode with Match B Request, Single Transition (m2_o_st) On an input channel, this mode provides a closing window filter for a single signal transition. Match A assertion captures its programmed time base in CaptureA, opens the filter window (enables assertion of TDLA), and enables assertion of MRLB. Match B recognition captures its related timebase, closes the window (disables assertion of TDLA) and generates a service request. Due to Match A and Match B ordering, the window is opened for at least one microcycle. Match B recognition indicates a window timeout condition which blocks late signal transitions, outside the prediction window. Transition detection blocks both matches, indicating the transition occurred inside the estimated window. Transitions can be detected from the microcycle following MRLA assertion until the microcycle on which MRLB is asserted. When TDLA is asserted inside the window range it disables both matches, captures both time bases and generates a transition service request. Using this mode, the channel can replace software window filtering of qualified transitions with the channel hardware window. The window opening and closing time can be scheduled for any of the two time bases or a combination of them. Ordered Mode with Match B Request, Double Transition (m2_o_dt) In this mode the channel logic implements a window filter for two detected signal transitions. MRLA assertion captures its related timebase and enables the assertion of both TDLA and TDLB. MRLB assertion captures its related timebase and disables the assertion of both TDLA and TDLB. Transitions can be detected from the microcycle following MRLA assertion until the microcycle on which MRLB is asserted. The first signal transition (following MRLA

Enhanced Time Processing Unit (eTPU2) RM0029 904/1740 Doc ID 15177 Rev 8 assertion) asserts TDLA, captures its related timebase and enables assertion of TDLB. The second signal transition detection asserts TDLB, blocks Match B, captures its related timebase and generates the service request. If both signal transitions occur inside the scheduled window, Match B recognition is blocked. If one or both signal transitions do not occur inside the scheduled window, Match B recognition generates a match service request and blocks further transition detections. The microcode can resolve the state using MRLA, MRLB, TDLA and TDLB, which affect the entry point selection. Single Match Enhanced Mode (sm_st_e) This is an enhanced single transition and single match channel mode which provides timing information of the digital filter delay. The CaptureA register captures the timebase selected by TBSA due to transition detection specified by IPACA or match recognition, as in sm_st mode. Initially, the CaptureB register continuously captures the unfiltered IPACB-selected signal transitions from the digital filter input, directly from the signal synchronizer. When an IPACA-qualified, filtered transition detection occurs, TDLA is set, MRLA assertion is blocked, and, in addition, captures into CaptureB are also blocked. On service, CaptureA and CaptureB (copied into ERTA and ERTB) holds the time of the qualified transition detection (ERTA), and the time of the last signal transition at the input of the digital filter (ERTB). Subtracting the time in ERTB from the time in ERTA provides the delay of the digital filter. In a quiet environment, the two captures provide the accurate delay of the digital filter in granularity of two system clocks. In a noisy environment, false transitions may be detected at the input of the digital filter due to the noise, and the delay measurement may be reduced, especially if IPACB selects both edge detection. The microcode can do sanity checks on this value to recognize noise effects (for example: calculated delay is less than the minimum delay of the digital filter). Note: In Channel 0, if ETPU_TBCR field AM = 01 (Angle Mode), the unfiltered input comes from TCRCLK input and the filtered input comes from the TCRCLK filter output. The edge is selected by IPACA/B, and is independent of the edge selection by ETPU_TBCR field TCR2CTL. Single Match, Single Transition (sm_st) In this mode the channel logic is functionally back-compatible to a TPU3 single action channel, but a match or transition detection captures at once both timebases. The mode recognizes a single transition with single match timeout. Either TDLA or MRLA generates service request and captures both timebases. Assertion of TDLA blocks future assertions of MRLA. Single Match, Double Transition (sm_dt) In this mode, the first transition detection asserts TDLA, captures a timebase in CaptureA and enables TDLB. The second signal transition asserts TDLB, blocks Match A, captures a timebase in CaptureB and generates a service request. Match A (before TDLB) captures into CaptureB the timebase selected by TBSA, in order not to overwrite the captured value of TDLA. This mode is used for scheduling one timeout condition on two input signal transitions (pulse timeout).

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 905/1740 Channel Modes on Output Signal Generation Since channel logic can generate output signal transitions based on Matches, the channel can be viewed as working in the following primary mode groups for signal generation:

Single Match: em_b_st, sm_st, sm_st_e, em_b_dt, sm_dt
Double Match: em_nb_st, bm_st, m2_st, m2_o_st, em_nb_dt, bm_dt, m2_dt, m2_o_dt The channel logic supports various match channel modes with single/double match, as explained in the following subsections. Either Match, Blocking Modes (em_b_st, em_b_dt) On an output signal these modes are useful when using two different time bases to set a required signal transition. The first match condition which is met sets a required pin action, captures both time bases, blocks any effects of the other recognition, and generates a service request. Because the first match recognition blocks the other, the microcode can get good separation in the function entry table as to which match caused the timeout first, and both time bases are captured, enabling the microcode to compare one timebase to the other at the moment of the match recognition. These modes can be used for:
Scheduling a required pin action to the first match recognition of two different time bases.
Cancelling a programmed pin action scheduled on one time base by match on another timebase (as a consequence of Table 485). Microcode has to set the OPAC register of the cancelling match to no-action and the OPAC register of the other match to the required pin action which may be blocked. If Match A is the cancelling match, it blocks the pin action also in case of two matches at the same time, since it has priority in this case. If Match B is the cancelling match, it does not block the pin action in case of two matches at the same time. Either Match, Non Blocking Modes (em_nb_st, em_nb_dt) On an output signal these modes are useful in combination with the ME bit set on the entry point, to define an interlaced operation. For example, each match recognition can set a pin action, and the second pin action is not sensitive to microcode latency (ME bit asserted). Example for usage is PWM interlaced function on which the latency is determined by the period and not the duty cycle. Another possibility is using one match for pin actions and the other match for an unrelated timed task without pin action (double the functionality of a single channel). Match B Request Modes (m2_st, m2_dt) On an output signal, these modes can generate narrow pulses or do conditional pin actions. A conditional pin action means that the pin state is changed only if the match recognitions occurred in the correct order, since the Match B recognition which generates the service request also has priority over the pin action and blocks future Match A recognitions. Setting OPACA to a desired pin action and OPACB to no-action, and using different time bases for Match A and Match B defines a conditional OPACA pin action which can be blocked by Match B recognition. For example, setting Match A on time and Match B on angle can limit the pin action to a maximum angle value. When pulses are generated, the service is requested at the trailing edge of the pulse, after MRLB is asserted. Both Match Request Modes (bm_st, bm_dt) On an output signal, each match recognition can affect the pin state, and capture its programmed time base. This way the pin action can be programmed separately for both

Enhanced Time Processing Unit (eTPU2) RM0029 906/1740 Doc ID 15177 Rev 8 match recognitions. For example, both match recognitions can negate the signal, and service request is generated after both conditions are met. This mechanism can set two conditions to do a required pin action, and the first recognition changes the signal, but service is called only after both conditions occur. When using the same time base, these modes can generate narrow pulses in any required order. For example, in a PWM function, when duty cycle is below 50% the function can get service on the low time and program the pulse to the required duty cycle of the high time. When duty cycle is equal or above 50%, the function can get service on the high time and program a negative pulse with the width of the required low time. To switch between the two states the function can program once the same transition time to MatchA and Match B with a required pin action, and on the next service program double match for the new state. Another usage is generating a required pin action on one programmed time and service request later on another time, after the second match recognition occurs, or capturing some timebase on one time and generating a required signal transition and service request later. Ordered Modes with Match B Request (m2_o_st, m2_o_dt) The order of the match recognitions imply that OPACA register programmed pin action always precede the OPACB register pin action. Setting OPACA to no-action, based on the greater-equal comparator, enables using Match A on one time base to delay the signal effect of Match B on the other time base. This method implements a conditional pulse extension or conditional delay on signal transition. These modes can also be used for deferred pulse generation with microcode service request after its trailing edge (if Match A condition comes after Match B condition). Another option is having Match A recognition associated with output pin actions and Match B recognition for a timed microcode task which has to be scheduled at a programmed time which may be delayed by the Match A pin action. Single Match Modes (sm_st, sm_dt, sm_st_e) There is no difference between plain and enhanced single match modes on an output signal. In this mode the channel logic is functionally back-compatible to a TPU3 single match output channel. Match A recognition generates service request and sets the pin state according to OPACA register. It captures at once the timebase selected by TBSA in CaptureA and the timebase selected by TBSB in CaptureB. Match/Transition Pin Action Conflict Resolution In output signals, matches and/or transitions automatically cause pin actions defined by the OPACA/B and/or IPACA/B channel control registers (see Section , Pin Control Registers). Simultaneous matches/transitions may be associated with different, possibly contradictory, pin actions. These conflicts are resolved according to the Table 485. If an OPACA/B = 000 (no action) prevails over non-zero OPAC according to Table 485, then if Match A/Transition A and Match B/Transition B occur simultaneously, no output pin action occurs, that is: a match on the action logic with OPAC = 000 inhibits simultaneous actions of the other OPAC, if prevailing according to Table 485. That also applies when output actions are caused by inputs (OPAC = 1xx).

the output to go low immediately, because OPACB = 100. microcode intervention. Match A opens a window for transitions and also enables Match B. checked: if sampled high, the output resets; otherwise it stays high. of the pulse (Match B), if required (SRI := 0). blocking always prevails over enabling, effective on the next microcycle. Table 485. Simultaneous match pin action priority

Figure 538. Input/Output combination

specifies the target channel of the Link Service Request, as shown in Figure 539. Writing to the LINK register issues a link request to the target channel, setting its LSR flag. start, the value used to calculate the Entry Point. allows a channel to issue service requests to any number of channels, including itself. channel, the branch condition is cleared but the link service request remains pending. Figure 539. Microengine LINK Register engine eTPU, Link is ignored when sent to the other engine, or engine 2. some user-programmed protocol using SPRAM parameters. All links are negated on reset. al. That can only happen if the link service request came from the other engine or from the serviced channel itself.

Reserved bit must be written 0.

Table 486. LINK engine selection

01 Engine 1

Ignored in single-engine eTPU

Enhanced Time Processing Unit (eTPU2) RM0029 910/1740 Doc ID 15177 Rev 8 Enhanced Digital Filter – EDF The EDF eliminates passing of signal transitions which are caused by noise. Its purpose is to eliminate false transition service requests caused by noise pulses which are shorter than a programmed width. The EDF has three modes of operations, selected by the CDFC field in the ETPU_ECR (see Section , ETPU_ECR – eTPU Engine Configuration Register ). These modes offer selections of trade-off between noise immunity and signal latency. CDFC also allows the filter to be bypassed. Table 487 gives an example of minimum detected signal pulse and maximum filtered noise pulse in the three EDF operation modes. In Angle Mode, if AM = 01, the EDF in channel 0 is replaced with the digital filter and synchronizer of the TCRCLK signal. In this mode, channel 0 works in combination with the Angle Counter logic, and their operation is fully synchronized. Following subsections provide the functional description of the eTPU channel digital filter. Two-Sample Mode In this mode the EDF works like the TPU2/3 digital filter. It uses the filter clock which is the system clock divided by (2, 4, 8,.., 256) as a sampling clock. The filter clock is selected by the FPSCK field in the Engine Configuration Register (ETPU_ECR) (see Section , ETPU_ECR – eTPU Engine Configuration Register). The EDF compares two consecutive samples. If both samples have the same value, the input signal state is updated. Note that when the FPSCK field selects the system clock divided by two, the EDF works like the TPU1 four-clock digital filter. Three-Sample Mode In this mode, like in the TPU2/3 mode, the EDF uses the filter clock as a sampling clock. The EDF compares three consecutive samples. If all three samples have the same value, the input signal state is updated. The Three-Sample mode gives more signal latency than the Two-Sample mode, but also better noise immunity and better ratio between minimum detected signal pulse to maximum filtered noise pulse. When a certain filter clock frequency is selected for Two-sample mode, double filter clock frequency can be selected to get better latency in Three-sample mode. Continuous Mode In this mode the EDF compares all the values sampled at the rate of system clock divided by two, between two consecutive filter clock pulses. If the signal is continuously stable for the entire digital filter clock period (i.e all the samples have the same signal value), the input signal state is updated. This method gives the same latency and the same ratio between minimum detected signal pulse to maximum filtered noise pulse, as the Two-Sample mode, as long as there is no noise. Each sampled noise delays the signal transition detection by at least a whole digital filter clock period. The Continuous mode gives the best noise immunity by comparing multiple samples of the noise. On the other hand, when a short noise pulse appears in the middle of the filter clock period at the same time of a real signal transition, the Continuous mode may reject a real signal transition and delay the response to the first filter clock period in which the signal is continuously stable. This may add to the latency and also to the minimum detected signal pulse in a noisy environment.

T2/T4 timing mode (see Section , Channel Timing Modes). and edge detection logic are explained in Section , Input/Output signal delays. as if FCSS = 0 always dividing system clock /2 using FPSCK, regardless if FCSS is 0 or 1. Table 487. Pulse Widths and Delays

This table shows pulse widths and delays in number of periods of the system clock.
Integrator mode is available for TCRCLK filtering only, see Section , TCRCLK digital filter.

Enhanced Time Processing Unit (eTPU2) RM0029 912/1740 Doc ID 15177 Rev 8 Channel Timing Modes Channels can work on two different timing schemes, defining the period of channel clocking, tied to T2 and T4 microengine phases, as explained in subsections below. Microengine T2 and T4 phases are shown in Section 24.7.1, Microcycle and I/O timing. T2 Channel Timing In T2 timing mode the channel event state can only be updated every two system clocks (see Figure 566). Pin state, TDLs, MRLs and Capture registers are updated on the microengine’s T2 clock phase. MRLE clears also happen on T2, but MRLE setting occurs on T4, together with the Match register write by microcode (see Section , Write Channel Match and UDCM Registers). Channels work in T2 timing mode when all the following conditions are true:

ETPU_TBCR bit TCR1CS is 0 (see Section , ETPU_TBCR – eTPU Time Base Configuration Register).
the Enhanced Digital Filter is not configured as bypass (see Section , Enhanced Digital Filter – EDF).
ETPU_ECR bit FCSS is 0 (see Section , Filter Clock Prescaler). T2/T4 Channel Timing In T2/T4 timing mode the channel event state can be updated on any system clock (see Figure 567). Pin state, TDLs, MRLs, MRLEs, and Capture registers are updated either on microengine’s T2 or T4 clock phases. MRLE clears can happen on T2 or T4, but MRLE setting occurs on T4 only, together with the Match register write by microcode (see Section , Write Channel Match and UDCM Registers). Channels work in T2/T4 timing mode when either one the following conditions are true:
ETPU_TBCR bit TCR1CS is 1 (see Section , ETPU_TBCR – eTPU Time Base Configuration Register).
the Enhanced Digital Filter is configured as bypass (see Section , Enhanced Digital Filter – EDF).
ETPU_ECR bit FCSS is 1 (see Section , Filter Clock Prescaler).

24.5.6 Time Bases

Each eTPU engine has two Time Counter Registers, TCR1 and TCR2. They provide 24-bit time bases, shared by all 32 channels. Any channel can use both time bases to:

Match channel’s internal registers MatchA or MatchB;
Capture time base value to channel’s internal registers, CaptureA and/or CaptureB, when a match recognition or an Input transition detection occurs. For more information on channel events refer to Section 24.5.5, Enhanced Channels. The TCR1 and TCR2 counters are accessible by the microcode for read and write operations. Its current value is used for getting the current time, and the captured values are used for channel relative time calculations of future events. When they are written at the same time they are incremented from any clock source, the written value prevails. TCR1 with ETPU_TBCR[TCR1CS] = 0 and TCR2 values are updated in T2 and read in T4 (see Section 24.7.1, Microcycle and I/O timing). TCR1 can also work at full-speed system clock, and so be updated on both T2 and T4, when ETPU_TBCR[TCR1CS] = 1. Both TCR1 and TCR2 values can be imported from or exported to the STAC bus. When their values are

refer to IPI STAC and Section , STAC Interface. counters if ETPU_TBCR[TCR1CS] = 0, but they can be in phase otherwise.

Internally Clocked Mode
Externally Clocked Mode
STAC Bus Client Mode The host program can read TCR1 time base through the ETPU_TB1R (see Section , ETPU_TB1R – eTPU Time Base 1 (TCR1) Visibility Register). The TCR1 bus runs through all the local engine channels. In channels which select TCR1 as MatchA and/or MatchB source, when its value is greater or equal to the programmed match value, a Match A and/or Match B event occurs on that channel. A recognized match event sets its related Match Recognition Latch 1 or 2, and according to the Predefined Channel Modes (PDCM) it may generate a channel service request. For details on eTPU channels refer to Section 24.5.5, Enhanced Channels. Externally clocked mode TCR1 can be driven externally by the TCRCLK input, after the digital filter. The TCR1 clock source is configured by the TCR1CTL bit, as shown in Figure 540. For more information on clock source selection, please refer to Section , ETPU_TBCR – eTPU Time Base Configuration Register.

Figure 540. TCR1 Clock Selection TCR1 can be driven by the system clock or system clock divided by 2, before the prescaler. freeze TCR1 clock independently of TCR2 (unlike GTBE).

Enhanced Time Processing Unit (eTPU2) RM0029 914/1740 Doc ID 15177 Rev 8 TCR1 clock prescaling Any clock source selected by TCR1CTL is prescaled by a factor of 1 to 256, selected by ETPU_TBCR field TCR1P. For more information on prescaler configuration refer to Section , ETPU_TBCR – eTPU Time Base Configuration Register. The TCR1 Prescaler resets when etpu_gtbe_in is negated. After reset, it starts counting up to TCR1P when etpu_gtbe_in is asserted. When TCR1 increments (etpu_gtbe_in = 1), the prescaler starts a new count and the new TCR1P becomes effective. When TCR1 is written by microcode, the prescaler is reloaded with TCR1P and it becomes effective, if etpu_gtbe_in is asserted. STAC bus client mode In this mode the TCR1 register is continuously updated from the STAC bus, and the clock selection and prescaling logic becomes ineffective. It is not writable by the microcode, and when read, it reflects the STAC bus imported value. The use of EAC is forbidden in client mode. This mode is configured through the register ETPU_REDCR (see Section , ETPU_REDCR – eTPU STAC Configuration Register). STAC bus server mode TCR1 bus can be exported to the STAC bus as a server, providing time information to other peripherals. This mode is configured through the register ETPU_REDCR (see Section , ETPU_REDCR – eTPU STAC Configuration Register). Timer Count Register 2 – TCR2 The TCR2 is a 24-bit counter which can be used in the following modes:

Pin Transition Mode: Count the rise, fall or both transitions of TCRCLK signal.
Angle Clock Mode: Count internal tooth angle in combination with the eTPU Angle Counter (EAC) hardware which implements an Angle PLL, and generates angle information to the channels. This mode is targeted for angle based applications.
STAC (STAC) Bus Client Mode: TCR2 is driven by an external source (see Section , STAC bus client mode).
Gated Mode: Count with rate derived from the system clock divided by eight. The TCRCLK signal is used to gate this count, enabling pulse accumulator operations.
Internally Clocked Modes: TCR2 is driven by internal clock, with count rate either system clock divided by eight or driven from the rising edge of a Peripheral Timebase Clock defined at MCU integration. The use and rate of the Peripheral Timebase Clock is MCU-dependent, but must not exceed system clock divided by two. All clock sources pass through a prescaler. In addition, the TCR2 count can be originated from the EAC which is a hardware angle clock and angle counter. Figure 541 shows the diagram for TCR2 clock control. When TCR2 is not driven by the EAC or STAC, the ETPU_TBCR field TCR2CTL selects the clock source, also allowing TCR2 to be frozen independently of TCR1 (see Section , ETPU_TBCR – eTPU Time Base Configuration Register). When in Angle Mode, TCR2CTL selects the TCRCLK edge sensitivity.

Figure 541. TCR2 Clock Control replacing its input synchronizer and filter, to get the same timing in the EAC and Channel 0. Register, field TCRCF[1:0]—TCRCLK Signal Filter Control). details on eTPU channels refer to Section 24.5.5, Enhanced Channels. and read access from the microcode or from the host reflect the imported TCR2 value. configuration refer to Section , ETPU_TBCR – eTPU Time Base Configuration Register .

Enhanced Time Processing Unit (eTPU2) RM0029 916/1740 Doc ID 15177 Rev 8 by microcode, the prescaler is reloaded with TCR2P and it becomes effective, if etpu_gtbe_in is asserted. The counter that divides the system clock by 8 before the prescaler also resets when etpu_gtbe_in is negated, or when TCR2 is written by microcode. TCR2 gated mode TCR2 Gated mode is selected in field TCR2CTL of register ETPU_TBCR. In this mode the TCRCLK signal enables or disables transfer of the system clock divided by 8 to the TCR2 prescaler. By programming the prescaler, TCR2 can run at rates from system clock divided by eight down to system clock divided by 512, in steps of eight system clock divisions. For more information refer to Section , ETPU_TBCR – eTPU Time Base Configuration Register. TCR2 signal transition modes These modes are selected when the TCR2CTL field in ETPU_TBCR is set to rise, fall or “rise-and-fall”. In these modes the TCRCLK signal is the TCR2 clock source, and its maximum transition rate depends on the TCRCLK digital filter mode of operation. The TCRCLK digital filter can be programmed to use the system clock divided by two, or use the same filter clock of the channels, controlled by the TCRCF field in ETPU_TBCR. It contains an up-down counter which operates as a digital integrator, optimizing signal latency in the selected mode and clock rate. When system clock divided by two is selected, the synchronizer and the digital filter are guaranteed to pass pulses that are wider than four system clocks (two filter clocks). Otherwise the TCRCLK is filtered with the same filter clock as the channel input signals. For details on TCRCLK and channels digital filter control refer to Section , ETPU_TBCR – eTPU Time Base Configuration Register, and Section , Enhanced Digital Filter – EDF. STAC bus client mode In this mode the TCR2 register is continuously updated from the STAC bus, and the clock selection and prescaling logic becomes ineffective. It is not write accessible for the microcode, and when read, it reflects the STAC bus imported value. The use of EAC is forbidden in client mode. This mode is configured through the register ETPU_REDCR (see Section , ETPU_REDCR – eTPU STAC Configuration Register). STAC bus server mode When TCR2 bus is exported to the STAC bus as a server, it can provide either time or angle bus to other peripherals, according to its operation mode. This mode is configured through the register ETPU_REDCR (see Section , ETPU_REDCR – eTPU STAC Configuration Register). To provide sequential update of the STAC clients, the Angle tick rate must not be faster than the STAC programmed update rate. This requirement puts a limitation on the angle clock count rate on high rate mode. In this case the Angle and Angle Fraction accumulator (see Section , Angle tick generator, and Figure 547) are advanced at rate of system clock divided by eight. Therefore, the STAC update rate for the Angle Bus must not be slower than eight system clocks. TCR2 bus in angle clock mode In this mode the TCR2 counter operates as part of the eTPU Angle Counter (EAC). The TCR2 bus value reflects this angle representation in which it counts Angle Ticks. Angle Mode is selected when the AM bit is set in ETPU_TBCR.

acceleration and mechanical corrections. incremented by the EAC logic. In Angle Mode, eTPU channel 0, 1 or 2 operation is combined with the EAC operation. EAC and by channel 0 to get full synchronization between the two logics. counter, eliminating the microcode latency in updating the TCR2 value. operation refer to Section , ETPU_REDCR – eTPU STAC Configuration Register.

TCR1: Can be exported to or imported from the STAC bus. TCR1 can only be imported from STAC bus when the engine is not in Angle Mode. When TCR1 is imported from the STAC bus, it becomes read-only for the microcode and reflects the imported values. For details refer to Section , Timer Count Register 1 – TCR1.
TCR2: Can be exported to or imported from the STAC bus. TCR2 can only be imported from the STAC bus when engine is not in Angle Mode. When TCR2 is imported from the STAC bus, it becomes read-only for the microcode, and reflects the imported values. When exported to the STAC bus, TCR2 can work in either Angle Mode or as a free running counter associated with the TCRCLK signal. For details refer to Section 24.5.7, EAC – eTPU angle counter. Proper configuration of the following bits is necessary to determine what can drive the STAC bus: ETPU_TBCR[AM] and ETPU_REDCR[REN2, RSC2], according to Table 488.

Table 488. STAC Bus and Host Read Sources

bus (either Time Count or Angle). STAC bus configuration is provided by the ETPU_REDCR bits REN1/2 and RSC1/2. REN1/2 enable the STAC interface to interact with the resource (either TCR1 or TCR2 bus). RSC1/2 configure the resource (either TCR1 or TCR2 bus) as Server or Client. refer to Section , ETPU_REDCR – eTPU STAC Configuration Register. Note: Setting a timebase as client of itself is forbidden, and results are unpredictable. etpu_gtbe_in. GTBE bit sets etpu_gtbe_out, and etpu_gtbe_in enables time bases to start. enable only the eTPU time bases, etpu_gtbe_out is simply connected to etpu_gtbe_in. Note: The timebase prescalers are reset when the GTBE input is negated.

STAC client configuration in Angle Mode is also forbidden for TCR1.

Figure 542. Time base synchronization The TCRCLK signal has an improved integrating digital filter with a 2-bit up-down counter. mode as the channel filters (see Table 444).

24.5.7 EAC – eTPU angle counter

Enhanced Time Processing Unit (eTPU2) RM0029 920/1740 Doc ID 15177 Rev 8 the tooth period, for predicting the period of the next tooth. The tooth period is partitioned into a programmable number of Angle Ticks. The eTPU application will use the divider in the MAC/Divide unit to calculate an integer and a fraction part of the angle tick such that the full tooth period gets the correct programmed number of angle ticks with no accumulated error. Each single tooth can be divided in angle ticks, up to 1024. In a 60-tooth flywheel, 128 Angle Ticks per tooth provide resolution of ~0.05 degrees per tick, which meets the accuracy requirement of 0.1 degrees in current automotive applications. The measurement of one tooth in angle ticks is independent on engine RPM; it is the tooth period itself (and the corresponding tick period) that is re-calculated for each new tooth, based on the difference between the estimated tooth and the actual detection. For these applications, one of the eTPU channels 0, 1 or 2 is dedicated to service the physical tooth detection. Channel 0 shares the same filtered input as the TCRCLK signal to get the same timing as the EAC. The TCRCLK edge detection is selected by ETPU_TBCR field TCR2CTL for the EAC, and by IPACA/B on channel 0, which must be set to detect the same edge(s). When channels 1 or 2 are selected to work with the EAC, IPACA/B is used to select the tooth signal edge detection for both the channel and the EAC, and the tooth signal that feeds the EAC is the same filtered input which feeds the channel. Channel 0, 1 or 2 generates the signal transition service request, and can also be used for generation of a window filter on this transition, to qualify TCR2 clocks. For this purpose, the selected channel should be configured with double match window filtering mode (refer to Section , Channel Modes). Depending on the channel mode set for the channel, Match A recognition opens the window, and Match B recognition may close it or leave it open. See Section , Angle logic and channel modes, for details. Match B also generates a time-out service request. Its input signal transition comes from the tooth. The window can be defined by microcode to open at a predefined point inside the tooth period, and stay open for a desired percentage to the tooth period. The window can be measured in angle or time This method improves the noise immunity by allowing transition detection only on an expected period, a feature which was software responsibility in previous TPU versions. The EAC supports deceleration, acceleration, last tooth and missing tooth scenarios. The large range of angle ticks per tooth can be used to cover longer tick counts caused by one or more missing teeth, or to provide extra resolution for future application requirements. In case of a missing tooth, the EAC can be configured to insert a dummy tooth or to simply measure a longer tooth. Figure 547 shows the block diagram of the Angle Counter system. TCR1 is used as a time base which measures the tooth period and is used for partitioning the period to angle ticks. Angle mode registers In Angle Mode, the registers described below control eTPU angle operations. They are accessible only by microengine as source and destination registers in microinstructions. When eTPU is not in angle mode (AM bit is negated in ETPU_TBCR), all angle mode registers can be used as general purpose registers. TPR – Tooth program register TPR provides configuration for the Angle Counter circuit. In this register, the microcode can properly adjust the tooth count (controlling last tooth, missing teeth, dummy tooth insertion, halt until tooth detection) and the number of angle ticks per tooth (field TICKS). Note that this register is sampled into a temporary register in the EAC logic when the High Rate Mode

which means that changes to this register may take effect only for the next tooth. Several conflict issues on TPR writes are explained in Section , Special TPR write cases. Figure 543. TPR Register when EAC leaves High Rate mode. See also Section , Special TPR write cases. Bits LAST, IPH and HOLD must not be asserted all at once. that TPR can be used as a general purpose register bit when angle mode is off. that a false physical tooth is detected due to noise. Force EAC to halt until detection of a physical tooth.

Enhanced Time Processing Unit (eTPU2) RM0029 922/1740 Doc ID 15177 Rev 8 TCR2 – Timer Counter 2 In Angle Mode TCR2 counts angle ticks instead of time. IPH Insert Physical Tooth This bit generates a dummy physical tooth which has the same effect as a real physical tooth, and resets itself subsequently. If EAC is in Halt mode, it switches back to Normal mode(1). If EAC is in Normal Mode, it switches to High Rate Mode. If Angle Logic is frozen by HOLD = 1 (see below), it returns to the state it was at the freezing moment. No Operation. Insert dummy physical tooth. IPH reads as 1 in the next microinstruction after it is asserted, negating subsequently. However, it can be set twice in two consecutive microinstructions to generate two teeth and make the EAC go from Halt to Normal to High Rate Mode. 13-14 MISSCNT Missing Tooth Counter Decremented on each estimated tooth, stops at zero. Used for generation of “Dummy Tooth” whenever it holds a non-zero value. 00No missing tooth 01One missing tooth 10Two missing teeth 11Three missing teeth If the tooth is detected or inserted before the missing tooth tick count completes (going High Rate mode, see Section , High rate mode (Acceleration)), MISSCNT resets immediately, but missing teeth count continues in High Rate mode (see Section , TPR buffering). LAST Last Tooth Indication Asserted by microcode and negated when a tooth is detected or inserted via IPH. Not Last Tooth. Last Tooth - reset TCR2 Counter at the end of the tooth tick count (after physical tooth or IPH = 1) when MISSCNT = 0. If the tooth is detected or inserted before the tooth tick count completes (going High Rate mode, see Section , High rate mode (Acceleration)), LAST resets immediately, but TCR2 resets only when the tooth count completes and MISSCNT = 0 1. Missing a physical tooth naturally causes EAC to get into Halt mode. Field Description

FRACTION[8:0]—Nine-bit fractional part of TCR1 clocks in one angle tick. the Tick Prescaler is halted for one TCR1 clock. Figure 546. EAC “PLL”

Figure 547. eTPU angle counter system

10 Count Contol &

Enhanced Time Processing Unit (eTPU2) RM0029 926/1740 Doc ID 15177 Rev 8 Acceleration and deceleration Acceleration and deceleration affect the new tooth period relative to the known period of the last tooth. Changes in tooth period may be extreme at very low engine RPM (such as cold start and warm start). The worst case of tooth period changes is caused during missing teeth, since there is more time for changes in angular velocity to be unnoticed by the EAC hardware. For example, on cold start (~20 RPM) there may be extreme acceleration: the ratio between a known tooth period before two missing teeth and the new tooth period after the missing teeth can be very high (up to a factor of 75). Acceleration and deceleration effects from tooth to tooth are less extreme as the engine climbs to high RPM. In case of deceleration, the estimated tooth period ends before the actual tooth detection arrives. In this case, the EAC hardware waits at the end of the current tooth period, when it is said to be in Halt mode, until the real tooth indication is received, then continues with normal operation (Normal mode). See Table 546. In case of acceleration, the actual tooth period is shorter than the estimated tooth period. As a result, a new physical tooth indication arrives before the end of the estimated tooth period. In this case the EAC closes the gap on High Rate mode by counting on system clock divided by eight to the end of the tooth, advances to the next tooth, and switches back to normal operation mode. See Table 546. The reason that the EAC does not jump directly to the next tooth is the need to provide sequential angle count throughout the whole tooth period, for channels or external STAC clients (if TCR2 is a STAC server) which compare angle in “equal” mode. These peripherals must get all the valid angle values in a sequential manner, to avoid missing angle matches. TCR2 advancing from one tooth to another is a continuous count, and can be optionally reset at the end of the tooth. An estimated tooth is generated after the Tooth Tick Counter reaches the TICKS programmed value. The EAC works continuously and switches automatically between Normal, Halt and High Rate modes. It relies on the microcode to calculate the estimated tooth period on every tooth, and to update the correct angle tick and tooth parameters in the EAC control registers. On high RPM, tooth period changes are reduced from tooth to tooth, and the EAC may follow the angle with good accuracy for several teeth without microcode intervention. The EAC handles missing teeth by insertion of “dummy” teeth, or by enlarging the expected tooth period. It is a good practice to locate the flywheel missing teeth in non-critical angles, since a missing tooth may increase the angle measurement error (acceleration and deceleration is detected late). Angle tick generator The Angle Tick Generator is responsible for generating a programmed number of angle ticks in the tooth period. It generates the ticks in an average rate which ensures completion of the correct number of angle counts in the estimated period of the tooth, since the count of one tooth in angle ticks is independent on engine RPM. The main output of the Angle Tick Generator is the tick clock that feeds TCR2 in Angle Mode, as well as the internal Tooth Tick Counter (see Figure 547). The Tooth Tick Counter counts ticks within a tooth, from 0 up to TICKS, is controlled by the Angle Tick Generator logic and cannot be accessed by microcode. Refer to Figure 548 for a generic presentation of the angle tick count and the measurement of a single tooth period.

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 927/1740 Calculating the angle tick period integer and fraction On each tooth the microcode has to update the exact period of a single angle tick used for counting the internal angle in the tooth. The period of an angle tick or a tooth is measured in units of TCR1 clocks (if TCR1CS = 0) or TCR1 clocks divided by 2 (if TCR1CS = 1). The microcode can use the eTPU MAC Divider unit (see Section , MAC and Divide Unit (MDU)) to divide the tooth period by the number of angle ticks per tooth, which is stored in the TICKS field of TPR (refer to Section , Angle mode registers). This division yields the integer part of the angle tick period and the remainder. Dividing again the remainder shifted left nine positions, by the number of angle ticks per tooth translates the remainder to a 9-bit fraction. The microcode concatenates the 15-bit integer and the 9-bit fraction to a 24-bit value and writes it to TRR. The new rate is effective immediately after the next Angle Tick is generated by the Angle Tick Generator (am). For high RPM, note that shifting the tooth period value nine positions to the left prior to the first divide operation would calculate, in one operation, the integer and the fraction. For example: On 60-tooth flywheel running at 1000 RPM, tooth period is 1 ms. If TCR1 counts @ 25 MHz, it counts 25,000 times in a tooth, which can be represented by 15 bits. Therefore the tooth period can be shifted nine positions to the left prior to divide operation, and be represented with 24 bits. Using shift left nine positions and one divide operation would get the result in MACL register (in MDU) which holds the integer and nine bits of the fraction: Angle_Tick_Rate {Integer[14:0], Fraction[8:0]} = (TCR1ToothPeriod(an)<<9) / Ticks TRR = Angle_Tick_Rate {Integer[14:0], Fraction[8:0]} On low RPM the initial tooth period, measured in TCR1 counts, may be too big to be shifted nine positions to the left. For lower RPM (for example 500 RPM) the tooth period cannot be represented by 15 bits, and shifting it nine positions to the left would lose the MSB. In this case, two divide operations are required as follows: first divide the Tooth Period by the number of TICKS—the integer is stored in MACL and remainder in MACH. MACL is saved in another register. MACH is shifted 9 positions to the left and divided again by TICKS. In parallel with the second divide, the register which saved the original MACL is shifted left 9 positions. After the divide MACL contains the 9 bits fraction and the other register contains the 15-bit integer, shifted left nine times. The logical OR of the two registers is written to the TRR: Angle_Tick_Rate {Integer[14:0]} = (TCR1ToothPeriod) / Ticks Remainder[9:0] = TCR1ToothPeriod) mod Ticks Angle_Tick_Rate {Fraction[8:0]} = (Remainder[9:0] << 9) / Ticks TRR = Angle_Tick_Rate {Integer[14:0], Fraction[8:0]} = (Integer[14:0] << 9) | Fraction[8:0] am.In High-rate mode, the tick keeps being updated at the rate of system clock/8 until it goes back to Normal mode, when the new TRR value is used. an. The tooth period (TCR1ToothPeriod) is not, in general, the value of estimated tooth time. It is obtained by microcode by subtracting TCR1 values between two teeth detections. Its comparison with the estimated tooth time indicates acceleration (if minor) or deceleration (if greater) to the microcode.

Figure 548. Angle Ticks Generation scale (TICKS = 1023) or one LSB on lower scale (TICKS<=511). when the tick count advances to the next tooth, or when TRR is written by the microcode.

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 929/1740 The Count Control and High Rate Logic handles deceleration, acceleration, missing teeth and last tooth. On High Rate (acceleration) it ensures that the angle bus scans all valid angle values in a rate which can be traced by the STAC bus. This operation enables external STAC clients (if TCR2 is a STAC server) or channels working in “equal-only” comparator mode to match the TCR2 exported angle information in “equal” mode, in an exact match. Because the eTPU channels are capable of capturing either TCR1 or TCR2 due to signal transition, the microcode can get either the angle or time of the physical pin transition. Since the EAC channel (0, 1 or 2) is connected to the physical tooth, the microcode can get the EAC error in angle domain (tooth appears at the wrong angle) or time domain (physical tooth captured time into the EAC channel, relative to the estimated tooth time). Note that in angle mode, the transition detect logic of the channel 0, if selected as the EAC channel, is fed from the digital filter of the TCRCLK signal, and not from the channel 0 internal digital filter. This ensures synchronous operation of channel 0 and the EAC hardware. Another feature of the eTPU channel, when working in Single Match And Single Transition Enhanced Mode (refer to Section , Single Match Enhanced Mode (sm_st_e)), is capturing a single time base due to signal transition before and after the digital filter. This option allows subtracting the digital filter delay to get accurate signal transition timing on the channel. This way, the TCRCLK signal may be programmed with a slow and reliable digital filter, and get accurate time measurement of the digital filter delay. To assert the end of the estimated tooth period the Count Control and High Rate logic compares the TICKS field in TPR (refer to Section , Angle mode registers) with the current value of the tooth tick counter. When the Tooth Tick value is greater or equal to TICKS, it determines the end of the estimated tooth period. On acceleration this event occurs during High Rate mode operation, after the arrival of a physical tooth. In deceleration, this event occurs during Normal Mode, before the arrival of a physical tooth. On constant angular velocity, this event appears together with the arrival of a physical tooth. The following sections describe the operation of the Counter Control and High Rate logic. Normal mode In Normal mode the Counter Control logic advances TCR2 and the Tooth Tick counter as if the engine has a constant speed during the tooth period. It receives the angle ticks from the Angle Tick Generator in an average rate which is determined by the Tooth Rate Register (TRR). This is the reset mode. When the Tooth Tick Counter is about to reach the last value effectively stored in TPR field TICKS plus one, the hardware detects the end of the estimated tooth period. If the physical tooth and the estimated tooth arrive at the same time the EAC stays in Normal mode, the Tooth Tick Counter is reset, and TCR2 is incremented (depending on TPR bits LAST and MISSCNT). If the physical tooth and the estimated tooth do not arrive at the same time, either acceleration or deceleration is detected, and the EAC switches to the proper mode. See Figure 549 for a detailed diagram of Normal Mode behavior. The microcode which services the EAC channel physical tooth transition may update TRR according to various conditions to give the best estimation of the current tooth period, according to the previous tooth period and other engine parameters.

Figure 549. Normal Mode the tooth, waiting for the physical tooth to arrive. diagram of Halt Mode behavior.

Figure 550. Halt Mode – Deceleration

When the acceleration is detected (physical tooth arrives before the Tooth Tick Counter reaches the TICKS value), the Count Control and High Rate logic switches to High Rate mode in which both the Tooth Tick Counter and TCR2 count at rate of system clock divided by eight, until the Tooth Tick Counter reaches the current TICKS value. To ensure correct operation, the TICKS value is sampled in the logic at the beginning of the mode.
At this point, which represents the estimated tooth edge, the logic resets the Tooth Tick Counter and advances TCR2 (or resets it if LAST is asserted and MISSCNT = 0).
The control logic switches back to Normal Mode, using the most updated TRR value as input to the Angle Tick Generator. The logic samples the updated TICKS value for the tooth estimation, last tooth indication and number of missing teeth from TPR. In High Rate mode the angle ticks are provided at high speed until the end of the current tooth. This operation is required to scan all the valid angle values of the current tooth, in a rate which is not too high for the STAC bus continuous update, but much higher than the rate dictated by TRR. EAC channel microcode, which services the physical tooth transition detection, can start its service either before High Rate mode operation is complete (the Tooth Tick Counter has not reached the TICKS value) or after the EAC switched back to Normal mode. Any physical teeth received while the EAC is in High Rate Mode does not alter the immediate EAC state, but it is still detected by the EAC channel logic and can, therefore, alter future EAC behavior (for instance, closing the tooth detection window (see Section , Angle logic and channel modes). At the beginning of High Rate mode operation, the TPR value is preloaded into a temporary register in the Counter Control Logic, used for scanning all the valid values to the end of the Tooth Signal Angle Tick TRR P1 P2 P3 P4 EAC Channel Service Time Slot EAC Channel Capture TCR1 TCR1 TCR1 TCR1 P1/ n Ch0 y y+n y+n+1 Ch0Ch0 P2/ n Halt Mode *service request microcode updates TRR ** TCR2 - continuous Tooth Tick Counter 0 0 0

Enhanced Time Processing Unit (eTPU2) RM0029 932/1740 Doc ID 15177 Rev 8 current tooth, with its appropriate LAST and MISSCNT attributes. While the EAC is in High Rate mode operation, the effect of microcode update of TPR fields LAST, MISSCNT and TICKS is delayed to the next estimated tooth, after the High Rate mode operation is complete (ao) (see Section , Special TPR write cases). This is because the current physical tooth represents the next estimated tooth. If the microcode updates this field after High Rate mode operation is complete, the current physical tooth and estimated tooth are the same, and the effect is immediate. Either in High-Rate mode or not, the value read by microengine is the same written, even if not yet effective, until the EAC resets LAST and/or IPH, or decrements MISSCNT. Typically the microcode service may occur during the High Rate mode on extreme acceleration situation at low RPM. Therefore, the microcode operations are always related to the real physical tooth. From the above it can be seen that the microcode updates of the TICKS field in TPR affect the end time of the current physical tooth. For correct operation, this field should be updated before the Tooth Tick Counter has reached either the old or the new TICKS value. During High Rate mode operation, TRR is ignored and the Angle Tick Generator uses system clock divided by eight. Therefore, the TRR update by microcode will take effect only after the EAC switches back to Normal mode. If microcode service occurs after the Tooth Tick Counter has been reset, the EAC is already back in Normal mode, and some angle ticks may have been counted at the rate of the previous tooth. In this case the new TRR value will have immediate effect on the angle tick period, and the microcode should take into consideration the delay from the physical tooth to the estimated tooth in calculation of the next tooth period. See Figure 551 for a detailed diagram of High Rate Mode behavior. An angle error may be introduced by the duration of the High Rate mode. Also, the scheduler latency may introduce a small accumulated error by using TRR value of the previous estimated tooth at the beginning of the current tooth. After the estimated tooth has advanced, the duration of the High Rate mode operation is the actual delay from the physical tooth edge to the estimated tooth edge. This delay can be obtained by comparing the estimated tooth time with the EAC channel capture register which captured TCR1 on the physical pin transition. ao. The effect of microcode writes to fields HOLD and IPH is immediate in High Rate mode.

Figure 551. High Rate Mode – Acceleration The EAC handles cases of up to three missing teeth and the last tooth in the engine cycle. The following paragraphs describe these functions. continuous angle measurement.

Count the angle ticks relative to the last physical tooth. The microcode should update the TPR TICKS field to the number of angle ticks included in two, three or four teeth, according to the flywheel type (one, two or three missing teeth). EAC hardware works in its regular manner.
Insert a “dummy” tooth instead of the missing tooth, at the estimated point in time. After the “dummy” tooth, the Angle Tick Counter is incremented as if there was a physical tooth. A “dummy” tooth can be inserted only during Normal or High Rate operation modes. The microcode inserts “dummy” teeth by writing to the MISSCNT field in TPR. In the first option the missing tooth is not counted on the angle measurement. For example, a flywheel with 59 physical teeth and one missing tooth can be considered as 58 identical teeth numbered (0-57) and tooth number 58 has a double number of angle TICKS. In this Tooth Signal Angle Tick TRR P1 P2 P3 P4 EAC Channel Service Time Slot EAC Channel Capture P1/ n P2/ n P3/ n y y+n+1 Ch0Ch0 Ch0 High Rate Mode TCR1 TCR1 TCR1 TCR1 *service request microcode updates TRR ** TCR2 Tooth Tick Counter

Enhanced Time Processing Unit (eTPU2) RM0029 934/1740 Doc ID 15177 Rev 8 case a 720 degrees engine cycle has 118 teeth. TCR2 reflects the real angle, since it counts angle ticks continuously. In the second option, the missing teeth are counted as “regular” teeth by automatic insertion of “dummy” teeth. The microcode has to write a non-zero value to the MISSCNT field in TPR. This field is a 2-bit down counter which affects the operation of the Counter Control logic. For example, a flywheel with 59 physical teeth (0-58) and one missing tooth (59) can be considered as 60 teeth numbered (0-59), all having the same number of angle ticks. The microcode has to write “01” to the MISSCNT bits during the period of tooth number 58 to indicate that next tooth (59) is missing. When the Tooth Tick Counter reaches the TICKS value, TCR2 is incremented as if a physical tooth has been detected. In addition, the MISSCNT value initializes a “dummy tooth counter” which is decremented to indicate the number of left “dummy teeth” which still need to be generated. Because a dummy tooth was counted, EAC does not enter Halt Mode and Tooth Tick Counter continues incrementing in the absence of a physical tooth detection. In case of extreme acceleration on very low RPM (cold start) there can be a situation that the first physical tooth after one or two missing teeth appears even before the “dummy” tooth is generated. Due to the acceleration the EAC switches to High Rate mode in order to run through all the valid angle values, including the dummy teeth. When the Tooth Tick Counter reaches the TICKS value on High Rate mode, and the “dummy tooth” down counter is not zero, the generated “dummy tooth” advances to the next tooth and decrements the “dummy tooth” counter, but does not switch the EAC back to Normal mode. The last “dummy tooth” decrements the counter to zero, indicating that no more dummy teeth are to be inserted, and the next tooth is an estimated physical tooth. The EAC continues at High Rate mode until the Tooth Tick Counter reaches the TICKS value again, then advances to the next tooth while switching back to Normal mode. When in High Rate mode, the TPR does not reflect the MISSCNT downcounting; see Section , TPR buffering, for details. MISSCNT can be rewritten before it reaches 0, allowing it to count more than three missing teeth, as long as no physical tooth arrives between the first MISSCNT write and the rewrite. Combining missing teeth and last tooth The Last Tooth indication takes effect when there are no more missing teeth to be generated, i.e the “dummy tooth” counter value is zero. If, for example, the microcode sets the missing teeth counter to “10” (two missing teeth) and sets the LAST flag, the first and the second dummy teeth will increment TCR2, and the third estimated tooth, which correlates with the physical tooth (the first of the next cycle), will reset TCR2, because LAST was set. This scheme enables the microcode to define one or more missing teeth to be replaced by “dummy tooth” insertion, and the end of the engine cycle in one service request. It is assumed that the two missing teeth must come together in the same engine cycle, and not split between two engine cycles (either the missing teeth are both last in an engine cycle or both not last, but not last in one engine cycle and first in the next).

Figure 552. Missing Teeth and Last Tooth Combination be updated to the fixed period of any tooth, including its mechanical error. angle ticks, disregarding the boundary between two adjacent teeth. Match timeout event of EAC channel will call service which detects extreme deceleration. indicates extreme deceleration back to the original RPM.

Enhanced Time Processing Unit (eTPU2) RM0029 936/1740 Doc ID 15177 Rev 8 to freeze and wait for the next physical tooth to close the gap. When the next physical tooth arrives, HOLD is automatically negated and the EAC proceeds from that point to the remaining portion of the tooth period, in the same mode it was when HOLD bit was asserted. Angle logic and channel modes The TCRCLK transition detection is qualified by a signal that comes from channel 0 (see Figure 547) and depends on the particular mode (PDCM) programmed for that channel. This configures a window for TCRCLK detection for the angle logic which is the same (except on High Rate mode, see Section , High rate mode (Acceleration)) used to set the TDLA flag on single transition modes, and TDLB on double transition modes (see signals TSE1,TSE2 in Figure 530). The same applies when channels 1 or 2 are used to control EAC (see signals TS1, TS2 in Figure 530). As a consequence, the window depends on the channel mode as follows:

On all modes, the window closes upon a tooth edge detection: TDLA asserted on single transition modes, TDLB asserted on double transition modes.
On mode m2_st: the window opens on Match A (which enables Transition A) and does not close with Match B. If Match B comes before Match A, it blocks Match A and, hence, Transition A.
On mode m2_o_st: the window opens on Match A (which enables Transition A) and closes on Match B. Match B is enabled by Match A, so it cannot come before.
On all other Single Transition modes, the window is “always open”, independently of matches.
On mode m2_dt: the window opens on Transition A, which is enabled by Match A. The window does not close with Match B, but if it comes before Match A the later gets blocked and, hence, blocks Transitions. Match A is also a condition for the window, so the microcode closes it by clearing MRLA.
On mode m2_o_dt: the window opens on Transition A, which is enabled by Match A. The window closes on Match B, which is enabled by Match A. Match A is also a condition for the window, so the microcode closes it by clearing MRLA.
On all other Double Transition modes, the window opens on Transition A. Restarting angle logic It is not advisable to toggle the ETPU_TBCR bit AM while GTBE = 1. However, if the Angle Logic must be restarted without interfering with the timebase count running on TCR1, the procedure below must be followed: 1. Write ETPU_TBCR setting AM = 00 and TCR2CTL = 111 at once. That prevents TCR2 from incrementing while the Angle logic is disabled. The Angle Logic state-machine resets to Normal mode and the tick prescaler to the initial count by AM = 00, but not the microengine registers TPR and TRR. 2. Start a thread to reconfigure the EAC. The thread must set the EAC controlling channel (0, 1 or 2) flags in a state, depending on the channel mode, that lets the channel tooth detection window open (see Section , Angle logic and channel modes). It can optionally write TCR2 with an angle preset value equivalent to the first tooth expected after restart. The thread must also set TPR bit HOLD = 1. The TPR bit IPH must be 0. 3. After the thread is finished, write ETPU_TBCR setting AM = 01, 10 or 11, and TCR2CTL according to the desired tooth edge selection if AM = 01.

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 937/1740 The first tooth detected after this procedure restarts the TCR2 counting, unfreezing the Angle Mode logic into normal mode. Special TPR write cases This section describes how simultaneous modification of TPR fields are resolved, and how the effect of TPR writes depend on the EAC mode. TPR buffering In High Rate mode (see Section , High rate mode (Acceleration)), TPR writes are immediately effective only for bits IPH and HOLD. Writes to all other fields are “buffered” and become effective when EAC leaves High Rate mode. However, if TPR is written a second time right after IPH is asserted in Normal mode, this second write behaves as if EAC is still in Normal mode. Only in the next microcycle (after execution of a NOP, for instance) the TPR writes are buffered, acknowledging High Rate mode. MISSCNT and LAST can be written any value during High Rate mode, and the value that prevails for the next tooth is the one sampled when EAC goes back to Normal mode (or the value written in Normal or Halt mode thereafter). If MISSCNT and/or LAST are not zero when High Rate mode begins, they are sampled into the internal EAC logic and are effective while High Rate lasts (missing teeth count continues and TCR2 is reset at the end of High Rate if LAST = 1). However, their values in TPR are reset when High Rate mode starts. After that and until the end of High Rate mode, the value read by microcode is the same written. This behavior prevents read-modify-writes to TPR from unwillingly rewriting LAST or MISSCNT. IPH and LAST If both IPH and LAST are asserted in the same microinstruction, the EAC acts as if LAST was set first and then IPH right after, so that:

In Normal mode, it goes to High Rate with LAST = 1;
In Halt mode, it goes to Normal Mode resetting LAST (and TCR2);
In High Rate mode, IPH is ignored and LAST becomes effective in the next tooth (physical or inserted) after it goes back to Normal mode. IPH and TICKS Because of different results depending on the EAC mode at the time of TPR write, it is not advisable to write 1 to IPH and change TICKS at the same microinstruction. A consistent behavior is obtained if IPH is written fist and TICKS on the second microinstruction after (for instance with a NOP between them), making the new TICKS value valid for the next tooth regardless of the mode. The mode-dependent behavior is:
In Normal mode, the new TICKS value becomes valid before EAC goes High Rate due to the IPH;
In Halt mode, the EAC goes to Normal mode, and new TICKS is valid for the next tooth;
In High Rate mode, the new TICKS value is effective when EAC leaves High Rate mode, and IPH is ignored;

Enhanced Time Processing Unit (eTPU2) RM0029 938/1740 Doc ID 15177 Rev 8 IPH and MISSCNT If both IPH and MISSCNT are written non-zero values:

In Normal mode, at the next microcycle the EAC goes to High Rate mode, the MISSCNT field in TPR goes to 0, and the missing teeth are counted in High Rate mode.
In Halt mode, the EAC goes to Normal mode for one microcycle and then, yet another microcycle later, goes to High Rate mode, counting the missing teeth. The TPR fields IPH and MISSCNT are zeroed on the transition from Normal to High Rate mode.
In High Rate mode, IPH is ignored (resetting at the next microcycle) and MISSCNT is buffered (see Section , TPR buffering). IPH and HOLD If IPH and HOLD are asserted at once, IPH cancels the HOLD and both reset. The EAC is not frozen, regardless of the mode. LAST and HOLD If LAST and HOLD are written 1 at once, LAST asserts and EAC is frozen. When a physical tooth is detected or IPH is asserted, the EAC is unfrozen in the same state it was before, and LAST is kept asserted.

24.5.8 Microengine

Each eTPU engine has a microengine that fetches, decodes and executes microinstructions. The Microengine only works when there are service requests to be attended, otherwise it turns to idle state, controlled by Hardware Scheduler (see Section 24.5.3, Scheduler). Microcode is stored in Shared Code Memory (SCM) that is 32-bit wide. Microengine can access SPRAM using a different bus from the one used to accesses code memory, so that code and data can be accessed at the same time (Harvard Architecture). Some of eTPU functionality can only be made through the microengine, like configuring channels and interrupting host. Microengine gives eTPU a high degree of flexibility, since any desired treatment for channel’s events can be implemented; however, that flexibility comes at the cost of channel service’s latency. Latency is worsened when channels from a same eTPU engine contend for microengine service. In Figure 553 a block diagram of microengine architecture is shown. Microengine features are summarized as follows:

P, DIOB, A, B, C, D, SR, RAR, LINK, CHAN, MACL, MACH, ERTA, ERTB, TCR1, TCR2, TPR, TRR registers are accessible by microcode.
24-bit ALU and Post-ALU shifter performs basic arithmetic and logical operations described in Section , ALU and Post-ALU Shifter.
MDU (MAC/Divide Unit) performs integer MAC, multiply and divide operations.
Fixed Microinstruction Size of 32 bits.
Fixed-length instruction execution (2 system clocks)
Static superscalar operation

Figure 553. Microengine Block Diagram

Enhanced Time Processing Unit (eTPU2) RM0029 940/1740 Doc ID 15177 Rev 8 Registers eTPU microengine accesses a total of 18 registers. Fourteen of them are special purpose (registers A, B, C and D are for general use). Special purpose registers except CHAN and LINK can also be used as general use if the operation that use their contents are not performed. Register description is intended to just introduce their functionalities and not to provide detailed explanation of it since it will be described in Section 24.5.9, Microinstruction set. Registers less than 24 bits in size are right-justified. None of the registers have guaranteed reset values. However, some are initialized just before the thread starts (see Section , Time slot transition). P Register P register is the only one that is 32-bit wide. It can be used as source and destination for arithmetic/logical operation, and as source and destination for SPRAM read/write operations. For P source/destination possibilities in ALU/MDU microoperations, see Section , Selecting sources and destination. When P is used as SPRAM read/write operations source or destination there are only 3 possibilities of access: all 32 bits, lower 24 bits and upper 8 bits. SPRAM operations are explained in detail in Section , SPRAM microoperations. P is automatically loaded with one parameter before the thread starts (parameter preload). For more information see Section , Entry point format, and Section , Time slot transition. Upper 8 bits of P register can be used as application state, since these bits can be tested as branch conditions. P[31:24] is also used in dispatch microoperation (see Section , Dispatch microoperation), and bit pairs P[29:28], P[27:26], P[25:24] can be directly copied into Channel flags 1 and 0 using field FLC. Together with Entry Table Condition Encoding, it provides fast state resolution without code execution. DIOB – Data Input/Output Buffer Register The DIOB register is 24-bit wide and can be used as source and destination for arithmetic/logical operations as well as SPRAM data source and destination. The DIOB only can be accessed as 24 bits, both in arithmetic/logical and SPRAM read/write operations. When using the DIOB to perform an SPRAM access, only the lower 24 bits of SPRAM will be accessible (SPRAM upper 8 bits always remain unchanged). The DIOB can also be used as SPRAM addressing register, when the DIOB contents are used as absolute SPRAM address (14-bit wide). In this case the DIOB can also be pre- decremented or post-incremented (see Section , Indirect addressing mode). The DIOB is automatically loaded with one parameter before the thread starts (parameter preload). For more information see Section , Entry point format, and Section , Time slot transition. ERTA and ERTB Registers ERTA/B registers are 24-bit wide and can be used as source or destination in arithmetic/logical operations. ERTA/B are the only source for channel’s match registers write (see Section , Write Channel Match and UDCM Registers). ERTA can also be the source for UDCM write.

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 941/1740 When a thread starts to be executed, ERTA and ERTB are loaded with a copy of CaptureA and CaptureB registers respectively. ERTA/B can be used to receive a copy of MatchA and MatchB registers. ERTA/B are the only destination of MatchA/B read operation (see Section , Special T4ABS source operation: Read match registers). ERTA and ERTB also receive a copy of CaptureA and CaptureB registers when CHAN register is written (see Section , CHAN Register). For more information about Capture and Match registers see Section , MatchA and MatchB Registers, and Section , CaptureA and CaptureB Registers. SR – Shift Register The SR is a 24-bit wide register that can be used as source and destination register for arithmetic/logical operations. The SR can shift right its contents by 1 bit at time and, at the same time, receive in its bit 23 the lost bit of a shift-right operation in post-ALU shifter (Section , ALU and Post-ALU Shifter), allowing the SR to be used to perform 48-bit shift right (see Section , Shift operations). MACH and MACL Registers Both MACH and MACL are 24-bit registers, part of MAC/Divide unit (see Section , MAC and Divide Unit (MDU)). They can be used as source and destination in most arithmetic/logic operations. When multiply or divide operations are used (multiply-accumulate included), MACH and MACL have special purpose and some restrictions apply, see Section , MAC and Divide Unit (MDU), for more information. LINK Register Link Register is an 8-bit wide register and can be used only as destination in arithmetic operations. LINK is a write-only command register, which precludes its use as a source register for ALU operations. When LINK register is written, it issues a service request for the channel number and eTPU engine equal to the number written in LINK register (see Section 24.5.1, Functions and threads, and Section , Channel Link, for information about Link Service Request). RAR – Report Address Register The RAR is a 14-bit register and can be used as source and destination in arithmetic operations. The RAR also receives the contents of PC register when a subroutine call is executed. The contents of the RAR are loaded into PC when a return from subroutine is executed. The RAR is loaded with value 0x3FFF during TST. For more information about subroutine call and return see Section , Branch operations, and Section , Return from subroutine, respectively. CHAN Register CHAN is a 5-bit register that can be used as source and destination in arithmetic operations. The contents of CHAN register affects the execution of many channel-related microinstructions, because its number indicates the selected channel. CHAN register must not be used to store temporary values in arithmetic operations. For more details, refer to Section , Channel Selection Register – CHAN. Counter Registers: TCR1, TCR2, TPR and TRR All these registers are 24-bit wide except TPR, which is a 16-bit register. They can be read or written in arithmetic/logical operations, and have special-purpose uses for time base and

Enhanced Time Processing Unit (eTPU2) RM0029 942/1740 Doc ID 15177 Rev 8 angle mode operations. For more information about those registers see Section 24.5.6, Time Bases, and Section 24.5.7, EAC – eTPU angle counter. General Purpose Registers: A, B, C and D A, B, C and D are 24-bit general purpose registers, which can be used to store intermediate values and do not have other specific uses with any eTPU feature. ALU and Post-ALU Shifter The ALU executes 24-bit arithmetic and logical operations. ALU’s output goes directly to a 1-bit shifter, called post-ALU shifter, so it is possible, for example, to add and shift using only one microinstruction. In some microinstruction formats, it is not possible to specify the operation executed by ALU. In these cases ALU will always perform addition. In formats which have the field ALUOP for ALU operation selection, all of them can be performed, including add/subtract using C (carry) flag as ALU’s carry-in, bitwise AND/OR/NOT/XOR, and shift/rotate of 2, 4, 8 and 16 bits. See Section , ALU/MDU Operation Selection. Subtraction, inversion, increment and decrement can be performed by combinations of source inversion and setting ALU’s carry-in to 1. ALU always performs 24-bit operations on its inputs, called A-source and B-source, and outputs a 24-bit result. 8-, and 16-bit inputs are zero padded to 24 bits. Likewise, ALU 24-bit output is always truncated to the destination register size. ALU Flags Four flags—Carry, Negative, Overflow, Zero—described below, are related to ALU and post- ALU shift operations. Operation size and shifting affect flags generation logic. Operation size determines the result boundary to be used for flags generation. Operation size is determined by size of sources and destination (see Section , Flags sampling control). For more information about flag generation, see Section , Flags sampling control. ALU flags can be used as branch condition (see Section , Conditional/Unconditional branch) or conditional ALU/MDU operation (see Section , Conditional ALU/MDU operation execution). Field CCS/CCSV in microinstructions can force no update of all flags. Not all flags are updated in all ALU operations: Overflow is updated only on addition and absolute value operations, Carry flag is updated in most ALU operations, and only Zero and Negative are updated in all ALU operations. ALU flags are never updated when microinstruction starts an MDU operation, regardless of CCS/CCSV, but are updated normally afterwards, on ALU operations that are executed in parallel with an ongoing MDU operation (MDU has its own flags). Note: Operation size can be smaller than destination register. For example: 0xFFFF + 0x0001 (both 16-bit sources) stores 0x10000 in a 24-bit register and sets Zero and Carry flags because operation size is 16 bits. Carry Flag (C) In an unsigned addition without shifting, Carry Flag is the ALU carry from bit 7 to 8, 15 to 16, or 23 to 24 on 8, 16 and 24-bit operation sizes respectively. In an unsigned subtraction without shifting, Carry Flag represent the sign of ALU’s result considering operation size (Carry Flag equal to 0 means a negative result).

operation performed, as shown in Table 489. if it does not have the same size of the operation (see Section , Flags sampling control). This is always the case for registers RAR (14 bits) and CHAN (5 bits). Overflow is updated only on addition (with or without carry) and absolute value operations. output (that is, it is not affected by 1-bit shift/rotate operations). written. It depends on the operation size, as shown in Table 491. Table 489. Negative (N) flag behavior Table 490. Overflow flag on addition (1) – V

For V-flag definition on the absolute operation, see Section , Absolute value operation .
BS is taken after any inversi on by the BINV field, but not added to the carry bit (CIN field)

Table 491. Zero Flag – Z

ap. ALU operations only occur on formats where a destination field is found (T2ABD/T2D). Table 492. Types of ADD operations

bits 7:0 rotated, even though the operation size is 24 bits. Table 493 describes Carry flag behavior. updated according to the ADD operation only, the same way as without shift. selected. Table 494 describes how BINV change ADC operation behavior. Table 493. Carry flag update on ADD operation

BINV has no effect on carry-out when used to code max constant (see Section , Max constant generation with

Table 494. Types of ADC operations

Flags behave exactly the same way as for ADD operation without shift/rotate. operations. Table 495 Describes AND, OR and XOR bitwise operations. and BINV field inverts (bitwise NOT) BS. V flag is never updated on exchange bit operation. C flag is always updated, regardless of CCSV, unless BS[4:0] > 23. Table 495. Types of Bitwise Operations

BS[1:0]. Table 496 describes the number of shifted/rotated bits depending on BS[1:0] value. independently of the operation size. on Table 497. CIN is ignored in these operations, but BINV is effective. Table 496. Number of shifted/rotated bits for each BS[1:0] value Table 497. Carry flag value on multibit shift/rotate operations

16-bit, its sign is taken into account and copied to C only if sign-extension is performed. Table 498 summarizes flag updating for Absolute Value operation. operands are always 24-bit wide. destination does not have its value changed (Section , Selecting sources and destination).

CCS/CCSV can disable flag update on multibit shift/rotate, but the specified flag size in CCSV is ignored for the C flag.

Table 498. ALU Flags in Absolute Value operation

V, N can be 1 on 8- and 16-bit Absolute Value, because the operand sign is always taken from bit 23. V, N

already busy: the result is unpredictable for both the ongoing operation and the started one. MDU operations according to Table 499.

On 24-bit x 8 bit multiplies: 2 microcycles (one start-MDU plus one execution microcycle)
On 24-bit x 16 bit multiplies: 3 microcycles (one start-MDU plus two execution microcycles)
On 24 bit x 24 bit multiplies/macs: 4 microcycles (one start-MDU plus three execution microcycles) An internal pipeline in MDU allows multiply-accumulate (or even non-fractional multiply) operations to start one microinstruction before a multiplication or multiply-accumulate (signed or unsigned) has been completed (e.g., one can start one multiply or multiply- accumulate once every three microinstructions). However, by doing that it is not possible to read the result in MACH and MACL (although the MDU flags can be tested), so this is intended to be used in a multiply-accumulate sequence. It is also allowed to mix different sizes in multiply/mac sequences. Multiply-accumulate operations are similar to multiply operations, except that the contents of MACH and MACL registers are added to the multiplication result. When multiply or multiply accumulate operations finish, MACL and MACH hold the least and the most significant 24-bit words, respectively. Divide operation length The divide operation is always unsigned. The division completes in 13 microcycles, meaning that after the start divide microinstruction, one has to wait for 12 microcycles and then read the result and the remainder in MACH and MACL registers. During the 12 execution microcycles, microengine can execute microinstructions unrelated to the MDU.

Table 499. CIN and BINV with MDU operations

Includes the B-source (unsigned) in fmults (signed) operations.

Enhanced Time Processing Unit (eTPU2) RM0029 950/1740 Doc ID 15177 Rev 8 Signed multiplication (mults) MDU signed multiplication is defined as follows: (signed) MACH,MACL = (signed) AS * (signed) BS MC and MV flags are reset. MZ is set if result is 0, resets otherwise. MN is set if result is negative. Unsigned multiplication (multu) MDU unsigned multiplication is defined as follows: (unsigned) MACH|MACL = (unsigned) AS * (unsigned) BS MC and MV flags are reset. MZ is set if result is 0, resets otherwise. MN is a copy of the most significant bit of result. Signed multiply-accumulate (macs) MDU signed multiply-accumulate is defined as follows: (signed/unsigned) {MACH,MACL} += (signed) AS * (signed) BS MC is not altered. MV is set if result can not be represented by a 48-bit signed number. MACS never resets MV flag: it is left as is if no overflow occurs, or set it otherwise. This allows checking the overflow flag only once at the end of a series of multiply-accumulate operations in a scalar product calculation. if (({MACH,MACL} += AS * BS < -247) || ({MACH,MACL} += AS * BS > 247 - 1)) MV = 1 MZ is set if result is 0, resets otherwise. MN is a copy of the most significant bit of result. Note that only 24-bit multiply-accumulate is available. Unsigned multiply-accumulate (macu) MDU Unsigned Multiply-Accumulate is defined as follows: (signed/unsigned) {MACH,MACL} += (unsigned) AS * (unsigned) BS MC is set if result can not be represented by a 48-bit unsigned non-negative number. MACU never resets MC flag: MC flag is left as is if no carry occurs, or set otherwise. This allows checking the carry flag only once at the end of a series of multiply-accumulate operations in a scalar product calculation. if (({MACH,MACL} += AS * BS < 0) || ({MACH,MACL} += AS * BS > 248 - 1)) MC = 1 MV is not altered. MZ is set if result is 0, resets otherwise. MN is a copy of the most significant bit of result. Note that only 24-bit multiply-accumulate is available. Signed fractional multiplication (fmults) MDU Signed Fractional Multiplication takes the B-Source as an unsigned 8- or 16-bit fraction between 0 and (28 - 1)/28 (inclusive) for the 8-bit operation, or between 0 and (216- 1)/216 (inclusive) for the 16-bit operation. Only A-Source is taken as a signed number. The

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 951/1740 value of B-Source is considered the unsigned numerator of a fraction with denominator 28 or 216 for the 8- and 16-bit operations, respectively. The integer part of the result is stored in MACH, and the fractional part in MACL. The result is signed, so that the concatenation of MACH and MACL form a 48-bit fixed point number with a 24-bit mantissa, both for 8- and 16-bit operations. To calculate the unsigned numerator of the fractional part (with denominator 2 24) of the result, one must take the absolute value of MACL considering the signal of the result (not MACL alone), i.e.: if flag MN = 1, invert MACL and add 1. MDU flags are updated in the same way as in the Signed Multiplication. Unsigned Fractional Multiplication (fmultu) MDU Unsigned Fractional Multiplication takes both A-Source and B-Source as unsigned operands. B-Source is taken as an 8- or 16-bit fraction between 0 and (28 - 1)/28 (inclusive) for the 8-bit operation, or between 0 and (216-1)/216 (inclusive) for the 16-bit operation. The value of B-Source is considered the numerator of a fraction with denominator 2 8 or 216 for the 8 and 16-bit operations, respectively. The integer part of the result is stored in MACH, and the fractional part in MACL. The fractional part in MACL is the numerator of a fraction with denominator 224. The concatenation of MACH and MACL form a 48-bit fixed point number with a 24-bit mantissa, both for 8 and 16-bit operations. MDU flags are updated in the same way as in the Unsigned Multiplication. Unsigned Divide (div) At the end of a divide operation MACL holds the result of the division, taking A-source as numerator and B-source as denominator, while MACH holds the remainder. If a divide by 0 is executed, MACL holds the maximum unsigned number (0xFFFFFF) as result and flag MV is set to indicate division by 0 (otherwise reset). The contents of MACH become indetermined. MC flag is always reset. MZ flag is set if MACL equals 0, and reset otherwise. MN receives a copy of MACH bit 23 (msb from the remainder). Note that signed division is not available. MDU Flags MDU has its own flags to indicate the result and status of an MDU operation. They are: MC, MZ, MV, MN and MB. All MDU flags are updated with the final result at the end of the operation, and do not change until the next operation finishes. Therefore it is possible to start a new MDU operation and test the flags of the previous one in parallel, except for mult/mac with 8-bit operand (takes only 1 microcycle). MDU Negative Flag – MN MN flag is always a copy of MACH bit 23 at the end of the operation, either in signed or unsigned ones. Note that MACH holds the rest of a division operation, which is always unsigned.

and Unsigned Multiply Accumulates. It is reset in the other operations. asserted if MACL (result) is equal to 0. work in both signed and unsigned operations. In divide operations it is only asserted if a divide-by-zero operation was executed. the last microcycle of any MDU operation execution. When a thread starts to be executed, the values in MDU and ALU flags are not initialized. Flags. MDU and ALU flags are updated during execution of microinstructions. flags (see Section , P Register). Flags TDLA/B, MRLA/B, LSR, FM[1:0] and PSS, are sampled at the beginning of a thread. when their respective latches in channel are cleared by microcode. (initial value of CHAN register when a thread starts). Table 500. Channel flags as branch condition

condition tests as false until a new lock attempt on the same thread. Conditional/Unconditional branch).

24.5.9 Microinstruction set

ALU/MDU Operations
SPRAM Operations
Channel Configuration/Control Operations
Flow Control Operations Each microinstruction format is defined by a set of microinstruction fields, which determine the operations, each belonging to one of the groups above (there may be several in one group). Complete microinstruction formats are shown in Section , Microinstruction formats. Parallelism conflicts may arise when two operations are executed in the same microinstruction. These situations are explained in Section , Microinstruction parallelism issues. SPRAM microoperations The access to SPRAM is made by providing an address and a register to perform a data transfer, except semaphore operations, which are also classified in the SPRAM group. Only MRLA Match A Recognition Latch These flags reflect the selected channel (CHAN) see Section , MRLA/B – Match Recognition Latches, and Section , TDLA/B – Transition Detect Latches, for more information. MRLB Match B Recognition Latch TDLA Transition A Detection Latch TDLB Transition B Detection Latch LSR Link Service Request Reflects the serviced channel. PSS Sampled Input Pin State Reflects the selected channel (CHAN). Does not change if CHAN is not changed (see Section , Pin Control Registers). PSTI Current Input Pin State. Reflects the selected channel (CHAN). Changes any time. PSTO Current Output Pin State Reflects the selected channel (CHAN). Changes any time. FM[1:0] Function Mode Bits reflects the Function Mode for serviced channel (Section , ETPU_CxSCR – eTPU Channel x Status Control Register)

Table 500. Channel flags as branch condition (continued)

Enhanced Time Processing Unit (eTPU2) RM0029 954/1740 Doc ID 15177 Rev 8 P and DIOB registers can exchange data with SPRAM. Microengine always addresses SPRAM in 32-bit boundaries, for 8, 24, or 32-bit wide data. Direction is determined by the field RW in all addressing modes: RW = 0 selects read and RW = 1 selects write. SPRAM Addressing Modes The eTPU has four addressing modes:

Absolute
Selected Channel Relative
Indirect
Engine Relative The addressing modes Absolute and Selected Channel Relative use immediate bits to form the physical address of SPRAM, which is identified in microinstruction as a field called AID. AID field can be 3, 7, or 8-bit wide depending on the addressing mode. Absolute addressing mode In Absolute addressing mode, the address range is 256 parameters, addressed by field AID, which in this mode is 8-bit wide. These parameters are located in SPRAM addresses from 0 to 255. physical_address = AID[7:0] Selected channel relative addressing mode In Selected Channel Relative addressing mode, only the first 8 (with 3-bit AID) or 128 (with 7-bit AID) parameters of the selected channel are accessible, depending on the microinstruction format. Physical address is calculated using the channel parameter base address that is specified in field CPBA of ETPU_CxCR (see Section , ETPU_CxCR – eTPU Channel x Configuration Register). AID field is added to channel parameter base address to compose the physical address. The equation is: physical_address = selected_channel_parameter_base_address + AID[6:0], or physical_address = selected_channel_parameter_base_address + AID[2:0] Indirect addressing mode In Indirect Addressing mode the physical address is taken from DIOB register. Only DIOB bits 13 to 2 are relevant. Since the SPRAM word address is shifted two bits up in DIOB, its contents hold the same parameter address value used by Host. The equation is: physical_address = DIOB[13:2], or physical_address = (truncated) DIOB / 4 Indirect addressing mode can have post-increment or pre-decrement on DIOB, allowing stack operations. See Section , DIOB stack operation, for more information. Engine relative addressing mode In Engine Relative Addressing mode the physical address is the concatenation of the ETPU_ECR field ERBA (see Section , ETPU_ECR – eTPU Engine Configuration Register ) with the 7-bit AID instruction field. This allows the same function microcode, when running on distinct engines, to access different address spaces, global to the engine only.

is not available in microinstructions that support SPRAM access, the source/destination is P . microinstructions where RSIZ field is not available, SPRAM access will be 24 bits by default. source/destination registers). Table 501. SPRAM source/destination register selection

0 P access

1 DIOB access

Table 502. SPRAM P access size

11 RESERVED RESERVED

Table 503. SPRAM access direction

the data portion written in SPRAM or in P/DIOB (SPRAM read) registers will always be 0x0. conditions are summarized in Table 504. Note: When field STC is present, STC = 11 also disables Zero SPRAM operation (see Table 505). operations are resolved like a normal SPRAM operation (see Table 546). to 0 are left untouched by STC pre-decrement and post-increment. four semaphores, selected by field SMPR. Table 504. Zero SPRAM operation 0 0 0 Clear P register. Size is determined by RSIZ field. See Section , SPRAM operation size.

1 RW P/D Regular SPRAM operation

Table 505. DIOB Post-Increment / Pre-Decrement – STC

00 Post-Increment of DIOB

01 Pre-Decrement of DIOB

10 No Increment/Decrement (normal access)

11 No SPRAM Access

Also disables Zero SPRAM operation

necessary to specify its number. continues locked for the engine and the SMLCK branch condition resolves as true. register set selection for T4ABS and ABDE controls register set selection for T2ABD. Table 507 shows the meaning of values for ABSE and ABDE fields. Table 506. Semaphore operations fields Table 507. Register Set Selection by ABSE or ABDE

immediate data, it is used as B-source (see Section , Operations with immediate data). (see Section , Microinstruction parallelism issues, for details). Table 508. Register set selection by T4BBS w/o ABSE, ABDE

Refers to operations with immediate data as B-source, without ABSE, ABDE.

Table 509. B source selection – T4BBS 111 BS = 0, or Max const., if CIN = 0 and BINV = 0 (see Section , Generating “max” constant).

T4BBS also selects A-source and destination register set in this case, according to Table 508.

Section , A-Source size override). T4BBS control which set T2ABD field uses to select the destination. Table 510. A Source Selection – T4ABS

0101 AS[15:0] = P[15:0] 16 AS[7:0] = 0, read_match (1) 8

1010 AS[23:0] = SR[23:0] 24 AS[14:2] = CHAN_BASE

1011 AS[23:0] = DIOB[23:0] 24 AS[13:0] = ENGINE_BASE (3) 16

1100 AS[23:0] = TCR1[23:0] 24 Reserved -

1101 AS[23:0] = TCR2[23:0] 24 Reserved -

1110 AS[23:0] = ERTA[23:0] 24 Reserved -

1111 AS[23:0] = 0 24 Reserved -

T4ABS = 0101 with second register set also reads MatchA/B registers into ERTA/B (see Section , Special T4ABS source

operation: Read match registers ).

CHAN_BASE is the selected channel’s base SPRAM address in channel relative address mode (see Section ,
ENGINE_BASE is the ETPU_ECR field ERBA shifted left nine positions.

Table 511. Destination selection – T2ABD

not 0x0 as expected. See Section , Generating “max” constant, for a detailed explanation. T2ABD, a parallelism issue arises (see Section , ALU operations and read match registers). address of the selected channel (given by CHAN register).

1001 TCR2[23:0] = AD[23:0] 24 Reserved -

1010 P[31:24] = AD[7:0] 8 Reserved -

1011 P[23:16] = AD[7:0] 8 Reserved -

1100 P[15:8] = AD[7:0] 8 Reserved -

1101 P[7:0] = AD[7:0] 8 Reserved -

1110 TRR[23:0] = AD[23:0] 24 Reserved -

T2ABD = 0010 with first register set also writes to MatchA or UDCM registers of the selected channel if field ERWA = 0

(see Section , Write Channel Match and UDCM Registers ).

T2ABD = 0011 with first register set also writes to Ma tchB register of the selected channel if field ERWB = 0.
if no destination is selected, ALU flags are updated, although the result is lost.

Therefore, all operations with BS = (constant) 0 have their size determined by AS and

bit, 16-bit, or determined by the operation size. Table 512. Operation size determination Table 513. Flag Sampling Using CCSV field

When neither CCS nor CCSV are present in the microinstruction, flags are not sampled. Exchange bit), but does control the N and Z flags. for BINV activates B-source inversion. of 0x0. See Section , Generating “max” constant, for more details. CIN field (1 bit, Table 516) controls the carry-in for addition/subtraction operations. control in MDU operations, see Table 499. Table 514. Flag Sampling Using CCS field Table 515. B-Source Inversion – BINV

Except on max-constant selection, see Section , Generating

Table 516. ALU Carry-In Control

Except on max-constant selection, see Section , Generating “max” constant.
Selected by ALUOP = 11000 and BINV = 1
Selected by ALUOP = 11000 and BINV = 0

Section 24.5.5, Enhanced Channels, for more information. Register are covered in the following sections. same microinstruction format. Post-ALU shift can be selected by SHF field (2 bits) or by some specific ALUOP field values. Table 517. Shift Register Control – SRC Table 518. Post-ALU shift operation

ALU performs AS+BS before shift/rotate for all SHF values.

Section , ALU ADD Operation with and without shifting. Table 519. The same field can also be used for overriding the size of A-Source (see Section , A-Source size override). override for A-Source is selected, the ALU/MDU operation executes unconditionally.

The destination register is not updated. If the destination is CHAN, no actions associated with CHAN assignment occur (see Section , Channel Selection Register – CHAN).
The ALU and MDU flags are not updated.
MDU does not start any operation, i.e., MACH and MACL are not updated.
SR does not shift.
T4ABS-selected read-match does not occur. A-Source size override Some values if the AS/CE field are used for A-Source Size Override, as shown in Table 520. 2. Some ALUOP combinations perform shift/rotate, but not using the Post-ALU Shifter (see Table 523)

Table 519. ALU/MDU conditional execution Table 520. A-Source size override

000 A-source size override to 8 bits

001 A-source size override to 16 bits

performed, see Section , A-source sign extension) and affects operation size calculation. size is fully determined by the operation definition (fields ALUOP, ALUOPI). from the size-overridden value, not the original one. Table 520. A-Source size override (continued) Table 521. AS/CE field A source size override funcionality

All values are zero-padded to 24 bits

Table 522. A source Sign Extension

Table 523. ALU Operation Selection – ALUOP

00000 AS mults BS[7:0] signed multiplication

00001 AS multu BS[7:0] unsigned multiplication

00010 AS fmults BS[7:0] signed fractional multiplication

00011 AS fmultu BS[7:0] unsigned fractional multiplication

00100 AS mults BS[15:0] signed multiplication

00101 AS multu BS[15:0] unsigned multiplication

00110 AS fmults BS[15:0] signed fractional multiplication

00111 AS fmultu BS[15:0] unsigned fractional multiplication

01000 AS mults BS[23:0] signed multiplication

01001 AS multu BS[23:0] unsigned multiplication

01010 AS macs BS[23:0] signed multiply-accumulate

01011 AS macu BS[23:0] unsigned multiply-accumulate

01100 AS div BS[7:0] unsigned division by 8-bit value

01101 AS div BS[15:0] unsigned division by 16-bit value

01110 AS div BS [23:0] unsigned division by 24-bit value

10000 AS[23:0] | BS[23:0] 24 bit bitwise OR

10001 AS[23:0] ^ BS[23:0] 24 bit bitwise XOR

10010 AS[23:0] & BS[23:0] 24 bit bitwise AND

10100 AS + BS arithmetic addition

11000 AS adc/sbc BS

11001 AS shl (2^(BS[1:0]+1)) AS is shifted left: 2 bits for BS = 0; 4 for BS = 1; 8 for BS=2; 16 for BS=3

11010 AS shr (2^(BS[1:0]+1)) AS is shifted right: 2 bits for BS = 0; 4 for BS = 1; 8 for BS=2; 16 for BS=3

field that selects ALU operation in this case is ALUOPI. with an 8 bit immediate operand (see Table 525).

11011 AS ror (2^(BS[1:0]+1)) AS is rotated right: 2 bits for BS = 0; 4 for BS = 1; 8 for BS=2; 16 for BS=3

11100 AS exch BS[4:0] exchange C flag and AS bit determined by BS[4:0] ( Section , Exchange bit)

11101 AS setb BS[4:0] set bit in AS determined by BS[4:0] (2)

11110 AS clrb BS[4:0] clear bit in AS determined by BS[4:0] (2)

Addition/Subtraction is selected by field BINV (see Section , B-Source inversion)
In setb and clrb operations, the register that drives A source is not changed, unless se lected as destination of the

Table 523. ALU Operation Selection – ALUOP (continued) Table 524. 24-bit Immediate Destination – T2D

00 P[23:0]

01 A[23:0]

10 SR[23:0]

11 DIOB[23:0]

Table 525. ALU Operation Selection With Immediate Data – ALUOPI

00000 AS mults #imm8 signed multiplication

00001 AS multu #imm8 unsigned multiplication

00010 AS fmults #imm8 signed fractional multiplication

00011 AS fmultu #imm8 unsigned fractional multiplication

00100 AS div #imm8 unsigned division

10100 AS + #imm8 arithmetic addition

10101 (AS + #imm8) shl 1 arithmetic addition with 1-bit shift left.

11001 AS shl (2^(#imm8[1:0]+1)) AS is shifted left: 2 bits for #imm8 = 0; 4 for #imm8 = 1;

11010 AS shr (2^(#imm8[1:0]+1)) AS is shifted right: 2 bits for #imm8 = 0; 4 for #imm8 = 1;

11011 AS ror (2^(#imm8[1:0]+1)) AS is rotated right: 2 bits for #imm8 = 0; 4 for #imm8 = 1;

Table 525. ALU Operation Selection With Immediate Data – ALUOPI (continued)

channel selected by the CHAN register, except fields LSR and CIRC.

Microcode field FLC (3 bits) allows them to be set or cleared, as shown in Table 526.

also be used to control the Output Buffer Enable signal (See Table 475).

11100 AS exch #imm8[4:0] exchange C flag and AS bit determined by #imm8[4:0] (see Section ,

Table 526. P Flags Operation – FLC Table 527. Time Base Selection 1 – TBSA

same applies in analogue way to OPACA and OPACB. information. IPACA/B = 1xx also enables assertion of MRLA/B during Time Slot Transition. See Section , Match Recognition. Table 528. Time Base Selection 2 – TBSB Table 529. Input and Output Pin Action Control – IPACA/B and OPACA/B

001 Detect rising edge only Match

011 Detect both edges Match (1) toggles output signal

100 Detect input signal = 0 on Match (1) Transition detection sets output signal low

Match registers can have their values changed using ERWA and ERWB fields (1 bit each). They also set their respective MRLE register (see Section , Match Recognition). ERWA is active (see Table 531).

Match A is used for IPACA/OPACA, and Match B for IPACB/OPACB.

Table 530. Immediate Pin State Control – PSC and PSCS Table 531. Write MatchA/B – ERWA/B

channel flags, and also the ones sampled into the branch logic. Microinstruction formats). Two-bit TDL allows independent clearing of TDLA and/or TDLB. Table 533 defines the two-bit TDL field. register, for both MatchA and MatchB registers, by clearing their respective MRLE bits. Section , Write Channel Match and UDCM Registers). which allows independent disabling of Matches 1 and 2, as shown in Table 535. Table 532. Clear Transition/Match Event Registers – MRLA/B, TDL Table 533. Independent TDLA/B clear – two-bit TDL Table 534. Disable Matches – MRLE

0 Disable matches for Match A and Match B

Microcode PDCM field (4 bits) defines the channel mode (see Section , Channel Modes). Transition (PDCM[0] = 0) and Double Transition (PDCM[0] = 1) predefined modes. UDCM (see Section , UDCM – User Defined Channel Mode). Table 535. Two-bit MRLE Table 536. Disable Match and Transition Service Request – MTD

00 SRI = 0: enable service requests for match and transition TCCEA = 0: disable transition

10 SRI = 1: disable service requests for match and transition TCCEA = 1: enable transition

Disables only captur es on transition events specified by IPACA.
Enables only captures into CaptureA regi ster, on transition events specified by IPACA.

Table 537. Predefined Channel Modes

Table 538. Channel and Data Transfer Requests – CIRC

000 Channel Interrupt Request from selected channel

001 Data Transfer Request from selected channel

010 Channel Interrupt and Data Transfer requests from selected channel

011 Channel Interrupt and Data Transfer requests from serviced channel

100 Channel Interrupt Request from service channel

101 Data Transfer Request from service channel

110 Global Exception

the current thread execution, and to halt the microengine. Microcode END field (1 bit) finishes current thread and allows other channels to be serviced. incomplete. END also releases any semaphore locked by the engine. Microcode BAF field (14 bits) indicates the absolute address of a jump/call target. Table 539. Link Service Request Negation Control – LSR Table 540. Jump / Call Selection – J/C

PC+P[31:24] (unsigned). Dispatch is affected by FLS field (refer to Section , Flush pipeline). used to define return from sub-routine (see Section , Return from subroutine). Table 541. Branch Condition Inversion – BCF Table 542. Branch Condition Selection – BCC

001110 Flag 0 001111 Flag 1

100000 V ALU flag 110000 PSS channel flag

100001 N ALU flag 110001 PRSS channel flag

100010 C ALU flag 110010 “Less Than” ALU flag combination (signed)

100011 Z ALU flag 110011 “Lower or Equal” ALU flag combination

100100 MV MDU flag 110100 P[24]

100101 MN MDU flag 110101 P[25]

100110 MC MDU flag 110110 P[26]

100111 MZ MDU flag 110111 P[27]

101000 TDLA channel flag 111000 P[28]

101001 TDLB channel flag 111001 P[29]

101010 MRLA channel flag 111010 P[30]

101011 MRLB channel flag 111011 P[31]

101100 LSR channel flag 111100 PSTO channel flag

101101 MB flag MDU flag 111101 PSTI channel flag

101110 FM[1] channel flag 111110 SMLCK semaphore flag

101111 FM[0] channel flag 111111 false

“less than” is a signed comparison, equal to the xor between ALU flags V and N; e.g., 0 < 0xFFFFFF tests as false
“lower equal” is an unsigned comparison, equal to Z or C; e.g., 0 < 0xFFFFFF tests as true.

used to return from subroutine. For R/D field, see Table 543. when field R/D is used. Return execution through RTN always flushes the pipeline. maximizes execution performance. This feature is controlled by field FLS (1 bit, Table 545). branch is executed, either if the branch is taken or not, as shown in Figure 554.

First branch’s destination instruction
Second branch’s destination instruction, and the flow proceeds normally from then on

replacing the first branch, for instance. Table 543. Return and Dispatch – R/D Table 544. Return from Sub-routine – RTN

Figure 554. Flush Pipeline Table 545. Flush Pipeline – FLS

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 979/1740 instruction is exceptionally considered illegal when executed with software breakpoints disabled (see Section , HALT microinstruction). Global Exception may be issued up to two microcycles after instruction fetch. The execution results of an illegal instruction on the microengine, channel logic or host interface are unpredictable, except for the HALT case. If the microengine decodes an illegal instruction, the following actions are taken:

a Global Exception is issued.
flag ILF1/2 on register ETPU_MCR is set to indicate this occurrence to the Host.
a breakpoint occurs, if NDEDI is present and configured to do so. Microinstruction parallelism issues This section clarifies parallelism issues that arise when two non-commutative microoperations appear in the same microinstruction. ALU operations and read match registers ALU operations have only one destination register, but there is one case where source selection determines destination: read Match register in ERTA and ERTB registers. In this case if ALU destination is ERTA or ERTB a conflict arises. The ALU destination value overwrites the value read from the match registers. ALU and SPRAM operations P and DIOB registers can be selected as destination by both ALU and SPRAM (read) microoperations in the same microinstruction. Since P and DIOB update from SPRAM data happens after P and DIOB update for ALU/MDU microoperations, the data read from SPRAM remains in P or DIOB after an operation when one of them is specified as destination for both ALU and SPRAM microoperations In this case, the value loaded into P or DIOB is the one read from SPRAM However, the ALU operation is executed and its flags are updated accordingly When P or DIOB is destination of an SPRAM read and also an ALU source at the same microinstruction, the value before the read is used for the ALU operation If DIOB is the ALU destination and P is loaded from SPRAM or vice-versa, no conflict occurs, and the result is the same as if operations occurred separately. All the above also applies to Zero SPRAM operations. When using P or DIOB as destination for ALU operations and also as source for a SPRAM write operation, the data written in SPRAM is the one calculated by ALU, which means it is possible to calculate a value and write it in an SPRAM address using only one microinstruction. The old value of DIOB or the old value minus 4 (pre-decrement) is always used when DIOB is selected as address (indirect address mode), no matter if DIOB is selected as destination of either the SPRAM or ALU. For the value loaded into DIOB, refer to Table 546.

ALU/MDU microoperation, the value written in the Match registers is the ALU/MDU result. instruction fields ERWA and CMW are active. ALU/MDU operation, then UDCM and MatchA/B receives the ERTA/B value. MRLEA/B channel flags, regardless of MRLE. updated Match register(s) belong to the new selected channel. old MatchA/B values simultaneously, i.e.: ERTA/B and MatchA/B swap their values. being written still receives the old MatchA/B values. Table 546. DIOB load from SPRAM and ALU

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 981/1740 Note: Read match, ERWA/B and CHAN assignment can be active at the same instruction. Combining rules Section , CHAN assignment, Read Match and ERWA/B, and Section , Read Match and ERWA/B, the result is: ERTA/B receives the CaptureA/B values of the new CHAN value, and MatchA/B of the new channel receives the old ERTA/B value(s). Stack accesses and ALU operations Post-increment is ignored in a stack operation (field STC) if DIOB is loaded from SPRAM: DIOB keeps the value read from SPRAM. Pre-decrement is ignored in a stack operation (field STC) if DIOB is destination of an ALU operation, for DIOB load value, but not for DIOB as address. Post-increment/pre-decrement remains valid in all other situations. These rules can be summarized in the following equivalent C code, and in Table 546. DIOB = *DIOB[15:2]; // read without posinc/predec *DIOB[15:2] = DIOB; // write without posinc/predec DIOB = *(--DIOB[15:2]); // read with predec DIOB = *DIOB[15:2]; // read with posinc (ignored) *(--DIOB[15:2]) = DIOB; // write with predec *DIOB[15:2]++ = DIOB; // write with posinc (value written is before increment) SRC and ALU/MDU operations If operation SRC is active (field SRC = 0) and register SR is selected as destination of an ALU operation, the value of the ALU operation prevails over the shifted value. The value of SR used as source in the ALU/MDU operation is the one before the shift. Semaphore lock/free and SMLCK branch condition When the SMLCK branch condition is tested at the same microinstruction of a semaphore lock or free, the condition is evaluated after the semaphore action (either free or lock) is taken. Dispatch and SPRAM read When the most significant byte of P is read from SPRAM (read 8 msb bits or 32 bits) and a dispatch instruction is executed simultaneously, the dispatch target address is calculated upon the P value before the read. CHAN Assignment, PSC/PSCS, and clear MRLEA/B, MRLA/B, TDLA/B When clear MRLEs, MRLA/B or TDLs is done and a CHAN assignment is done at the same time, the flag selected by the old CHAN value is cleared in the channel, but the branch conditions receive the state of the flags selected by the new CHAN. When a pin action is commanded through PCS/PSCS and a CHAN assignment is done simultaneously, the output signal affected is selected with the old CHAN value. Microinstruction formats See Table 547.

Table 547. Microinstruction Formats

Table 547. Microinstruction Formats (continued)

Enhanced Time Processing Unit (eTPU2) RM0029 984/1740 Doc ID 15177 Rev 8

24.5.10 Test and Development Support

Following sections describe several features available to support development and test. Most debug features, described in Section , Development support features, are accessible through a separate debug bus, and are not available through registers in the standard eTPU memory map. The details of the access to this interface are MCU-dependent, but a separate IP block, called NDEDI, is provided so that these features are accessible by a Nexus interface. IP-bus Green line device debug request can also be used to put microengines in halt state. Conditions for the assertion of this line are also MCU-dependent. Section , Test support features, describes embedded test features: the Multiple Input Signature Calculator (MISC) is an SCM test feature accessible through registers ETPU_MCR and ETPU_MISCCMPR (see Section 24.4.2, System configuration registers). MISC allows SCM test “on the fly, that is, while eTPU is running, with no impact on eTPU functionality or performance. Development support features Internal Debug Interface and Nexus Class 3 support eTPU provides an Internal Debug Interface that exports real-time microengine states and values, including breakpoint/watchpoint information. It also provides inputs for breakpoint request from other blocks or outside MCU. NDEDI is an IP block designed to support Nexus functionality for the eTPU. When Internal Debug Interface is connected to an NDEDI block, the MCU can provide Nexus Class 3 debug interface. Nexus is a development support external interface defined by the IEEE standard ISTO 5001-1999. Some of the next subsections describe debug features provided by the Internal Debug Interface combined with the NDEDI block. NDEDI can be replaced by other block providing a different programming interface, such as a register debug interface, for instance. Microengine halt state Halt is a microengine state where it suspends execution during a thread, or does not start executing a scheduled thread from idle state. While Idle State is entered from END execution without any other scheduled thread, microengine enters Halt State by any of the following events:

Execution of the HALT microinstruction (software breakpoint).
External halt request through the Debug Interface (includes Nexus breakpoint request via EVTI input pin (see Section , Internal Debug Interface and Nexus Class 3 support).
The other engine enters halt state and they are configured to halt simultaneously (bit HTWIN is asserted via Nexus Interface).
IPI Green line device debug request assertion and NDEDI register NDEDIETPUx_DC field CBI = 1. If same register’s field CBT = 1, microengine halts at the next time-slot boundary, if CBT = 0 it halts immediately. As a particular case, microengines come halted out of reset if device debug request is asserted, since CBI reset value is 1. Microengine does not execute out of reset, either in halt (device debug request

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 985/1740 asserted) or idle state (device debug request negated), but halt enables several other features (see below).

Occurrence of any of the hardware breakpoint conditions. See Section , Hardware breakpoints, for details.
Execution of a single-step microinstruction: microengine returns to halt state after executing a single microinstruction while in halt state. See Section , Single-step execution, and Section , Forced microinstruction execution, for details. When microengine enters halt state, it automatically triggers the following actions:
Suspends input signal sampling and filters (respective engine channels only), if signal ndedi_stop_pins is asserted at the Debug Interface.
Releases the SPRAM arbitration for Host or CDC accesses, no matter if microengine was halted in the middle of a dual-parameter (back-to-back) access.
Stops TCR1/2 clocks of the respective engine, if signal ndedi_stop_tcr is asserted at the Debug Interface.
If the other engine is also in halt state or stopped, allows turning ETPU_MCR VIS bit to If all halt conditions are cleared when VIS = 1, microengine(s) keep on halt state until VIS = 0, when it automatically exits halt state, except on single-step (see Section , Single- step execution), so that single-step execution is ignored while VIS = 1. MDU continues executing until it finishes any ongoing operation even if microengine is in halt state, except when the halted instruction is an END. There are two kinds of halt state, depending on the previous microengine state when halted: 1. halt_idle, if the engine was not executing a thread when halted; the engine cannot leave halt_idle to fetch instructions, so one cannot single-step or follow a program flow; it can, however, execute forced instructions (see Section , Forced microinstruction execution). 2. halt_exec, if the engine was executing a thread when halted. The engine can single- step and continue a program flow from halt_exec. When microengine exits halt state, any dependable action is suspended and, if exiting halt_exec, the instruction pointed by the PC is fetched, while the instruction already fetched before halt is executed. Note that both the PC and the prefetched instructions can be modified during halt state, with a forced execution of a branch instruction (see Section , Forced microinstruction execution).

conditions, listed below. These conditions depend on NDEDI configuration.

CHAN register assignment (only by microcode, not by time slot transition).
SPRAM read and/or write to a given address and/or write data. The breakpoint is always qualified by the SPRAM address, but the following variations are allowed: – break on write only, read only, or read-and-write. – break on higher-byte write data value, lower 24-bit write value, full word (32-bit) write value, or regardless of data. Break on read data is not supported.
PC (program counter) value.
Beginning of a thread with a Host Service Request pending.
Beginning of a thread with a Link Service Request pending.
Beginning of a thread with a Match Service Request pending.
Beginning of a thread with a Transition Service Request pending.
End of a thread.
Illegal instruction execution. All these conditions can also be qualified by the value of the CHAN register. On any of these conditions, halt of one microengine does not depend on the halt of the other, unless the other engine is configured to do so, via Nexus Interface. Occurrence of any of these conditions halts the microengine, i.e., the conditions are logically “ORed” together, and they can be individually enabled. While in halt state, the microengine can also execute any forced microinstruction not in the normal program flow (see Section , Forced microinstruction execution) or, if in halt_exec, in single-step (see Section , Single-step execution). There are situations when requests for stopping an engine, breakpoint and service can occur simultaneously. Breakpoint requests always prevails over a stop request (ETPU_ECR bit MDIS = 1 or device debug request = 1). When the eTPU is idle: stop request prevails over Service Request if there is not a hardware breakpoint request; a hardware breakpoint request leads to debug mode immediately if there is no Service Request, and after TST if there is Service Request (regardless of stop requests). The rules above are summarized in the Table 548, showing the destination state of the microengine in each situation.

Table 548. Breakpoint, stop and service requests resolution from idle

Breaks after TST, if signal ndedi_sync_break is still asserted.

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 987/1740 When a thread is ending, it goes to Idle or TST only if there is neither a hardware breakpoint request (signal ndedi_thread_break negated) nor a request to stop (MDIS = 1 or device debug request = 1). When thread is ending and there are simultaneous hardware breakpoint (ndedi_thread_break active) and stop (MDIS = 1 or device debug request = 1) requests, hardware breakpoint prevails and the engine enters Debug mode (Halt_idle state). If the engine entered Debug mode after a thread finished (Halt_idle state) and a “go” command comes from the debug interface, the engine state machine goes to Idle and the rules above apply. It means that if a “go” is issued in Halt_idle state with MDIS = 1, the engine goes to Idle for one microcycle and then stops (if MDIS or device debug request keeps asserted and there is no other breakpoint request). Note: Hardware breakpoint requests are ignored for the first microinstruction executed when microengine leaves halt. Hardware watchpoints Debug Interface allows watchpoints on the same conditions available for hardware breakpoints (see Section , Hardware breakpoints). Software breakpoints A software breakpoint occurs when microengine executes a HALT microinstruction. Any number of software breakpoints can be set in code, usually replacing an active microinstruction. Like any other microinstruction, HALT increments the PC and pre-fetches the next instruction. So, before the halt state is suspended, if the original program flow must be followed, the original instruction at the HALT address must be executed, regardless if the software breakpoint is removed (replacing HALT by the original microinstruction) or not. The following is the procedure to resume execution from a software breakpoint: 1. Restore the original instruction in SCM (replace HALT). 2. Force a jump with flush to the original instruction (see Section , Forced microinstruction execution). 3. If the software breakpoint must be kept: single-step and replace the original instruction with a HALT. 4. Let the flow continue, issuing a GO command (leaving halt state). Special care must be taken if HALT is followed by another HALT, and the second HALT is removed when microengine was halted by the first one. In this case, replacing the second HALT with the original microinstruction is not enough to remove the second breakpoint, because the second HALT was already prefetched and would be executed anyway when halt was suspended. The debugger must also do a forced execution of unconditional branch with flush to the original microinstruction address. That will clear the pipeline, replacing the prefetched instruction with a NOP, and load PC with the address of the removed breakpoint. So, when halt state is suspended, the original microinstruction will be fetched while NOP is executed, and program flow continues normally from then on. Note: A HALT instruction placed after a no-flushing branch, dispatch or return may be a problem from the debugger application standpoint: after the HALT is executed, the eTPU debug interface informs the address of the branch/dispatch/return destination, and the debugger application has no direct way to identify which HALT instruction was executed, if multiple HALTs lead to the same address. This can be solved if the debug support block (NDEDI) has a register holding the address of the last instruction executed, otherwise one should forbid non-flushed HALT instructions.

Enhanced Time Processing Unit (eTPU2) RM0029 988/1740 Doc ID 15177 Rev 8 Software breakpoint setting and removal is possible only with SCM RAM implementations or ROM implementations with SCM RAM emulation (see Section , SCM emulation). There is only one way of inserting software breakpoints into SCM RAM: writing bit VIS = 1 in register ETPU_MCR, and then accessing SCM as an ordinary RAM from the slave bus. This can be done only if both engines are halted or stopped. Single-step execution When microengine is already in halt_exec state, it can run the next microinstruction in the normal program flow and get back to halt state. PC is incremented, or assigned the BAF value in a branch with satisfied condition. Note that the executed instruction was already prefetched in the instruction pipeline, and a new microinstruction is fetched during its execution. The prefetched instruction may be cleared during halt state by the forced execution of a branch with flush (see Section , Forced microinstruction execution), making single-step execute a NOP instead of the next instruction in the program flow. Single-step execution is controlled by the debug interface, and is a feature available from Nexus if eTPU is connected to the NDEDI block.The single-step execution of a NOP instruction can be useful to control input signal sampling and filtering, if signal ndedi_stop_pins = 1 at the Debug Interface. Single-step does not happen if VIS = 1. Forced microinstruction execution When microengine is already in halt state (either halt_idle or halt_exec), it can run forced microinstructions through the debug interface. This feature is available from Nexus if eTPU is connected to the NDEDI block. The microinstruction, specified by the user, is not fetched from SCM and comes directly from the debug interface. MDU start commands issued by forced instructions are executed, and the MDU runs the operation until the end, independently of the halt state. The microinstruction field END is ignored. During forced execution of any instruction except Branches, Returns and Dispatches, the PC does not change, and the prefetched instruction in the pipeline is bypassed, but not discarded. When halt state is suspended, the prefetched instruction is executed and the instruction pointed by the PC is prefetched in parallel (two-stage pipeline). Forced execution of a Branch, Dispatch or Return loads the PC with the BAF field (if branch condition is satisfied), PC+P or RAR, respectively. If branch condition is not satisfied, PC value stays unaltered. The flush control (field FLS) also works, so that a successful forced branch with flush replaces the prefetched instruction with a NOP. So, to clear the instruction pipeline during halt, all one has to do is an unconditional branch to the desired address with flush. HALT instructions must not be executed as forced. Forced operations that depend on the serviced channel are unpredictable when executed in halt_idle. Microengine register access eTPU provides no direct access to microengine and channel registers from the slave bus or any other interface. However, these registers can be read and written in halt state by executing forced microinstructions (see Section , Forced microinstruction execution). Immediate data microinstructions may be used to set register values. Some registers are not selectable for immediate data destination, so intermediary register(s)—notably P—may have to be used to carry the desired new value to the target register in two or more microinstructions. Usually the previous values of intermediary register(s) must be previously saved and restored after the whole operation.

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 989/1740 Similar procedures apply for register reads: their contents must be dumped to SPRAM, where they can be read from the slave bus. Microengine flag access Microengine halt state allows reading the branch conditions flags through forced microinstructions or, more easily, through the NDEDI register NDEDI_ENGINEx_CFSR. Flag conditions set by the user are seen by microengine for the next microinstruction execution. The flag set options are limited by the possibilities of forced microinstruction execution. If the eTPU runs (not single-stepping) after exiting the halted state, the conditions modified during halt may remain only for the first microcycle after the halted state. After the first microcycle, branch conditions are altered only according to their regular update scheme. Microengine stall Microengine can get into a stall state, attending a request from a debug interface signal assertion. The reason for a Stall request from NDEDI (or from any other debug support block) should be a temporary lack of resources, for instance queue full. During stall the microengine suspends execution, but all the other engine logic continues operating: time bases, angle logic, channel logic, input sampling and filters. Stall differs from Halt, not enabling any of the debug features that Halt enables (see Section , Microengine halt state). It also does not break an atomic microengine access, unlike halt. The Microengine can be stalled when idle and from the moment TST ends, before executing the first thread microinstruction, until just before the last thread microinstruction is executed. Stall requests are ignored in any other occasions. Microengines in a dual-engine system can be independently stalled. If a forced end is issued when microengine is in stall coming from execution, the END is executed only when the microengine resumes execution from stall. SCM emulation If SCM is implemented as ROM, an external RAM may be used to replace it, allowing code patching and software breakpoint setting for debugging purposes. SCM ROM replacement by Emulation RAM is MCU-dependent. The SCM may even be divided into a ROM part and a RAM part. In this case, both microengines can run code from both ROM and Emulation RAM. It is possible to make one engine run code from RAM and the other from ROM, by using different Entry Tables. The SCM visibility conditions also apply to Emulation RAM. All SCM implementations, either RAM, ROM or Emulation RAM, are external to the eTPU block. eTPU provides a signal to enable the switching between external SCM banks. The conditions for this switching are: 1. Both engines stopped 2. VIS bit = 0 Note that these conditions also stop the clocks of the SCM interface and MISC logic. Test support features SCM Test – Multiple input signature calculator The Multiple Input Signature Calculator (MISC) comprises special hardware that sequentially reads all SCM positions and calculates, in parallel, a 32-bit signature from a 32- input CRC signature calculator with the following polynomial:

Enhanced Time Processing Unit (eTPU2) RM0029 990/1740 Doc ID 15177 Rev 8 1 + x1 + x2 + x22 + x31 A complete description of the signature calculation procedure can be found in Section 24.7.4: MISC algorithm. Once started by the Host the MISC runs continuously, restarting after the completion of each cycle, when it sets the ETPU_MCR flag SCMMISC (see Section , ETPU_MCR – eTPU Module Configuration Register). The average time for a MISC calculation can be measured by checking SCMMISC state at regular intervals, incrementing a counter and clearing SCMMISC if it is set. MISC accesses to the SCM array are executed if none of the engines is accessing the SCM, to avoid degradation of the microengine performance: it happens while no channel is being serviced. An ongoing MISC operation can be aborted by writing 0 to SCMMISEN. The Host must load the register ETPU_MISCCMPR (see Section , ETPU_MISCCMPR – eTPU MISC Compare Register) with the expected value to be found at the end of the MISC cycle, and then start the signature calculation writing bit SCMMISEN = 1 in register ETPU_MCR (see Section , ETPU_MCR – eTPU Module Configuration Register). MISC zeroes the signature accumulator and starts reading SCM data and calculating the signature. After last SCM position is read, MISC compares the value in signature accumulator against the value in ETPU_MISCCMPR: if there is a mismatch MISC stops, a Global Exception is issued and the bit SCMMISF in register ETPU_MCR assumes value 1. If no mismatch is found, MISC repeats the procedure automatically. When signature is being calculated, SCM address starts at the last SCM address and counts down to 0. The conditions for executing a MISC operation are (see also Table 467):

Both microengines in idle state (no channel is being serviced) or stopped, in any combination (e.g., engine 1 idle with engine 2 stopped)
ETPU_MCR bit VIS = 0
ETPU_MCR bit SCMMISEN = 1 Note that MISC can run regardless of SCM implementation type (RAM or ROM). If SCMMISEN = 0 or VIS = 1, the MISC logic stays at its initial state, with address counter pointing to the last SCM position and accumulator reset. Performance monitoring features Idle Counter The Idle Counter Register ETPU_IDLE (see Section , ETPU_IDLE – eTPU Idle Register) continuously counts microcycles in which the microengine is not busy with channel service. It can be used to measure the microengine utilization by rating the count measured during a period of time to the number of microcycles contained in the period. The Idle counter does not count microcycles when the engine is stopped, or is in TST or halt states.

24.6 Initialization/Application information

24.6.1 Configuration sequence

After initial power-on reset the eTPU remains in an idle state(as), requiring initialization of several registers before any function can begin execution. Also, if the SCM is implemented

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 991/1740 in RAM, it should be initialized with the eTPU application code prior to configuring the eTPU. Configuration procedures are summarized as follows:

If SCM is implemented as RAM, load the eTPU application code (see Section , SCM access).
Initialize the SCM MISC logic (optional, see Section , SCM Test – Multiple input signature calculator).
Initialize the eTPU time base configuration registers (ETPU_TBCR) to setup: – TCR1 and TCR2 prescalers and clock sources. – Select digital filtering mode. – TCRCLK signal filter control. – Angle mode operation (if necessary).
Initialize the eTPU engine configuration register(s) (ETPU_ECR) to setup: – Entry table base. – Filter prescaler clock control.
Initialize eTPU STAC configuration register(s) (ETPU_REDCR), if one needs to setup TCR1/2 resource Client/Server operation.
Write to the Channel Configuration registers (ETPU_CxCR) to choose the Function to be performed by each channel, and its parameter base address.
Write to channel status control register (ETPU_CxSCR) to choose among the possible variations within the function flow (FM bits).
Write to SPRAM for parameter initialization of each configured channel.
Write to register(s) ETPU_WDTR if one needs to enable and setup the Watchdog(s) mode and timeout.
Write to channel x Host Service Request registers (ETPU_CxHSRR) to initialize the active channels. (at)
Write to the channel interrupt enable register (ETPU_CIER) if interrupts are to be enabled from the appropriate channels. Likewise for Data Transfer Requests (ETPU_CDTRER). This can also be done through ETPU_CxCR.
Write to channel x configuration registers (ETPU_CxCR) to enable each channel by assigning it a high, middle, or low priority (CPR field). at
Monitor the Host service request registers (ETPU_CxHSRR) for completion of initialization.
Write ETPU_MCR bit GTBE = 1 to start TCR1/TCR2 time base counting at same time in both engines (may be done before or never, depending on the particular application and use of Red Line bus). See Section 24.7.2, Initialization code example. as. Except when device debug request is asserted on power-on reset: in this case, the microengines wake-up in halt state. at. This operation is done before enabling active channels to avoid time events happening before the channel initialization.

Enhanced Time Processing Unit (eTPU2) RM0029 992/1740 Doc ID 15177 Rev 8

24.6.2 Reset options

Hardware reset is achieved by assertion of device synchronous reset. Both engines and common logic is reset, and even the System Configuration and Global Channel registers assume their reset values. Note: All eTPU input clocks must pulse during reset so that both engines are reset, even if they are in Module Disable or Stop mode. Software reset eTPU has no Software reset. To abort infinite microcode loops, the Force END mechanism must be used (see field FEND in Section , ETPU_ECR – eTPU Engine Configuration Register).

24.6.3 Multiple parameter coherency methods

Follows a description of two methods for coherent transfer of multiple parameters between Host and eTPU. Both methods involve the use of two parameter areas: the Transfer Parameter Area (hereafter called TPA), which is the SPRAM area directly accessed by the Host for reads and writes, and the Permanent Parameter Area (hereafter called PPA), which are the SPRAM positions where channel parameters are normally accessed by the Function microcode. Note that parameters in either TPA or PPA do not have to be in sequential addresses. TPAs and PPAs allocation are completely defined by the application, and there may be any number of them, independently of the channels. The methods described here are not the only solutions for the coherent transfer problem, and both can co-exist in eTPU and even used in combination. Also note that for transfers of a pair of parameters, the Coherent Dual-parameter Controller is faster and have less impact on both eTPU and Host performance. That said, the methods are:

Transfer Service A microengine thread transfers, upon Host Service Request, data from/to a TPA to/from a PPA. Coherency is guaranteed by the fact that a thread is atomic with respect to other threads in the same engine, and so are its transfers. If parameters in PPA are shared by both engines, hardware semaphores have to be used to access them.
Mailbox For Host to eTPU transfers, the microcode checks a flag, set by the host, indicating the existence of new parameter data in the TPA. It can, then, either access TPA data directly or copy it to the PPA. For eTPU to Host transfers, when microcode changes PPA, it copies them to the TPA and flags updated TPA data to Host, possibly using an Interrupt or a Data Transfer Request. The Mailbox flag is reset when data is copied: by the eTPU microcode, when it transfers TPA to PPA (possibly followed by an Interrupt); by the Host, when it reads data from the TPA. This indicates that TPA is free for another transfer. Transfer Service has the advantage of separating the task of data transfer from the functional service thread that accesses the parameters, with less impact to the latter. Compared to the Mailbox method, however, it has bigger average latency, because the Transfer Service thread has to contend for a time slot to execute. This latency can be minimized if Transfer Service thread is assigned to a separate channel with higher priority, but even so it does not guarantee that PPA is updated before the next execution of the functional thread that uses it.

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 993/1740 Mailbox method, on the other hand, makes the functional thread check for the existence of new data (Host to eTPU). It does not have to be responsible for the transfer, though: it may access the TPA directly, and a Transfer Service can then be used to copy data from TPA to PPA.

24.6.4 Programming hints and caveats

Atomic dual access after a call, return A dual, back-to-back parameter access is not atomic after a call, a jump, or a return if they occurred in parallel with an odd SPRAM access. It is safer to make a pair of parameter accesses that must be coherent begin at the second instruction after a call/jump/return. Resource polling The use of polling while waiting for a condition or a resource (except semaphore lock) should be avoided in order not to hang the microengine in long loops. This general programming guideline is greatly enforced in eTPU, as a thread cannot be preempted for any reason. Safer polling, albeit with long and indeterministic latency, can be obtained if one issues a channel link to itself and terminates the thread. The microengine is then free to other tasks, and the next poll happens at the next time the channel is serviced. This mechanism can be combined with finite (timed out) loops for better latency. Changing channel function, parameter base, or entry table scheme Channel Function, Parameter Base Address and Entry Table Scheme are determined by the ETPU_CxCR fields CFS, CPBA and ETCS. They cannot be changed when the channel is enabled. If the channel is disabled first, one may still have service requests from the previous function, so before the channel is enabled again one must be sure that:

The first thread executed in the new function is the initialization one.
The initialization thread of the new function clears any previously pending service request. Follows a safe procedure for function changing: 1. Disable the channel (write ETPU_CxCR field CPR = 00). 2. Change the function configuration (ETPU_CxCR fields CFS and/or CPBA and/or ETCS). 3. Request the initialization thread, writing ETPU_CxHSRR with the initialization HSR (channel still disabled). 4. Enable the channel (write ETPU_CxCR field CPR > 0); the initialization HSR is serviced before any other formerly pending service requests, clearing them. Checking and clearing interrupts of a stopped engine An engine may be stopped with interrupts (or DMA requests) pending. This includes the case when the engine’s MDIS bit is set and a thread is still running: the thread will complete execution, possibly issuing an interrupt or DMA request before the engine stops, setting the STF bit. As soon as the engine stops the channel registers become inaccessible, issuing bus errors when accessed. Interrupts and DMA requests can still be checked and cleared through the Global Channel Registers, though. DMA requests can also be cleared by the hardware handshaking with the DMA controller when the engine is stopped.

24.6.5 Estimating worst-case latency

Introduction to Worst-Case Latency
Using Worst-Case Latency Estimates to Evaluate Performance
Priority Scheme Details used in WCL Analyses
First-Pass WCL Analysis
Second-Pass WCL Analysis The first-pass WCL analysis is based on a deterministic, generalized formula that is easy to apply. Because of the generalizations in the formula, the first analysis result is almost always much worse than the real worst case. If the desired system performance is within the limits of this first analysis, then no further analysis is required; the system is well within the performance limits of the eTPU. If the desired system performance exceeds that indicated by the first analysis, the second-pass WCL analysis should be applied. The second-pass analysis is not a generalized formula, but rather uses specific system details for a realistic worst-case estimation. Introduction to worst-case latency Note: In this Appendix the latency calculation and examples refer to old TPU functions such as PWM, DIO etc. These functions use single action channels which have single transition and single match functionality. They are not optimized for the eTPU hardware enhancement which support various double action modes. These examples are for reference only. New eTPU functions which are optimized for the new hardware will impose different latency calculations. Worst-case latency for a channel is the longest amount of time that can elapse between the execution of any two function threads on that channel. For example, if in a particular system, channel 5 is running PWM, the worst-case latency for channel 5 is the longest possible time between the execution of two PWM threads. The worst-case time includes the time the execution unit takes to execute threads for other active channels, and other delays described later in this section. Refer to Figure 555.

Figure 555. Worst-case latency for PWM

change performance for a function even if the same set of functions are still active. Functions and threads). The eTPU Microengine executes one thread of a function at a time. hardware to do so beforehand. the details of the priority scheme that the scheduler uses (see Section 24.5.3, Scheduler). Figure 556. Function threads

Enhanced Time Processing Unit (eTPU2) RM0029 998/1740 Doc ID 15177 Rev 8 Channel number priority If more than one channel of a priority level is requesting service, the lowest numbered channel is granted service first. For example, if channels 0, 5, and 9 are all high-level channels requesting service during a high time slot, channel 0 is granted service first. Continuing this example, if channel 0 requests service again immediately after being serviced, it is not serviced again until channels 5 and 9 are serviced. This scheme is implemented so that continuously-requesting low numbered channels do not take all the time on the eTPU execution unit and leave no time for other channels. The scheduler uses registers to keep track of which channels have been serviced and which require servicing. Each channel has two register bit: a service request register (SRR) and a service grant register (SGR). The SRR is set when a channel requests service. After the channel has been granted service, the SGR is set and the SRR is cleared. SGRs are not cleared individually by channel, but rather as priority level groups. The clearing of a group of SGRs begins a new cycle for that priority level. An SGR group is cleared on the condition that a channel of that priority level has just been serviced, and no other channel of that priority level is requesting service (has a set SRR) and has not been granted service (has a clear SGR). For example, if a middle-priority channel has just been serviced (either in a middle-priority time slot or a high or low-priority time slot gained by priority passing), the SRRs and SGRs of all middle-priority channels are compared. If there is no middle-priority channel with its SRR set and SGR cleared, the scheduler clears all middle-level SGRs. If there is a middle- level channel with its SRR set and SGR cleared, the scheduler does not clear the SGR group, and the requesting middle-level channel is serviced on the next middle-level time slot (or possibly sooner by priority passing). SPRAM collision rate Most function threads read or write to the eTPU SPRAM at least once. Because both the eTPU Microengine and Host can access the SPRAM but not at the same time, the Microengine may suspend execution during the SPRAM access while waiting for the Host to finish accessing the SPRAM. At other times the Host may wait for the Microengine. Wait states can take up to two system clocks, when the Host accesses the SPRAM directly, without using CDC. Microengine(s) wait-states must be added into the worst-case latency calculation. The system designer should estimate the percentage of SPRAM accesses in the system that will result in Microengine wait-states. This percentage is called the RAM collision rate (RCR). In each collision with direct Host accesses to the SPRAM the Microengine(s) wait for two system clocks. In eTPU the Coherent Dual-parameter Controller (CDC) may also access the SPRAM for atomic transfers of two parameters. eTPU Microengine may wait on this operation (if it is in service time) until the transfer is complete. CDC always transfers two parameters, making four consecutive accesses (read, write, read, write) of one system clock each. The system designer should estimate the percentage of SPRAM accesses in the system that will result in a Microengine wait due to coherent transfer, and multiply it with the average number of system clocks the Microengine waits for each transfer. This percentage is called Coherent Parameter Collision Rate (CPCR). In addition, Microengine to Microengine multiple parameter coherent communication, using the hardware semaphores, may hold one Microengine which waits to lock the semaphore while the other Microengine is holding it. This waiting is due to a software loop, not hardware wait-states. Note that single parameter access of one Microengine does not affect the timing of the other Microengine due to SPRAM time interlace. This implies that single parameter

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 999/1740 Microengine to Microengine communication does not affect the performance. The Microengine which waits for the semaphore will loop until it is freed by the other Microengine. This time depends on the eTPU application. The system designer should estimate the percentage of Microengine to Microengine coherent parameter communication that will result in eTPU semaphore loops, and multiply it with the average number of system clocks the Microengine loops for each such transfer. This percentage is called CCR (Communication Collision Rate). A 100% collision rate for a system is the theoretical worst case. In many systems, however, the RCR, CPCR and CCR would be very low, sometimes even near 0%. This is because the eTPU is an independent processor capable of servicing most function needs, so that the Host rarely needs to access the eTPU parameter RAM. Also coherent Microengine to Microengine communication of more than one parameter may be rare. To find a realistic RCR, CPCR the system designer should evaluate the Host code and find the percentage of time it accesses the eTPU parameter RAM with or without using the CDC. This percentage gives a good RCR and CPCR. The eTPU application provides a good estimation of CCR. Note: The programming practice of polling a fl ag in the eTPU SPRAM causes a very high RCR and should be avoided in high-performance systems. After the collision rate for a system is found, it can be applied to the WCL calculations for each channel. The system designer can use the collision percentage and the number of SPRAM accesses (with and without semaphores) to estimate the eTPU loop time for a function. Note that in old TPU functions CPCR and CCR are both zero. The estimation of eTPU wait time is as follows: Variables: N1 = Number of simple RAM accesses in the longest thread RCRWait = Maximal system clocks wait time for simple RAM collision = 2 CPCRWait = Average System Clocks for Coherent Parameter Transfer (using CDC). N2 = Number of eTPU-eTPU semaphore RAM accesses in the longest thread CCRWait = Average System Clocks for Microengine-Microengine communication transfer. Estimated Wait Time: Function eTPU maximal wait time = N1 * (RCR * RCRWait + CPCR * CPCRWait) + N2 * CCR * CCRWait First-pass worst-case latency analysis Following is the first-pass calculation of worst-case latency for a channel. Remember that this analysis uses generalizations that usually produce a result much worse than the real worst case. If the worst-case result from the first analysis is too long for the desired performance, use the second analysis for a more realistic worst-case analysis. Worst-case assumptions and formula To estimate worst-case latency for a channel, assume this worst-case condition: the channel has just been serviced in a time slot of its priority level, and all other channels in the system are continuously requesting service and have cleared SGRs. The worst-case latency is the time from the end of the channel’s service until the end of the channel’s next service. See Figure 559.

Figure 559. First-pass worst-case latency

Find the worst-case service time for each active channel.
Using the H-M-H-L-H-M-H time-slot sequence, map the channels that are granted for each time slot.
Add time for six-clock time-slot transitions. Finding the worst-case service time for each active channel A table for eTPU functions should list the longest threads (not counting initialization threads) for the functions, and the number of eTPU SPRAM accesses in the longest thread (semaphored and non semaphored). These figures will be used for estimating Microengine wait time. Table 549 is an example for old TPU functions in which there are only simple parameter RAM accesses. It does not take into consideration the CDC operation and Microengine to Microengine communication. The worst-case service time for each channel is: (CPCR = CCR = 0) Longest thread + ((number of RAM accesses in longest thread+1) * RCR * 2 clocks). Note that the formula adds 1 RAM accesses for the parameter preload that occurs during TST. There are actually three accesses during TST, but only the first one can receive wait- states. Channel X Serviced Worst-Case Latency Channel X Other Channels Serviced Channel X Serviced Next

Table 549. Longest threads and RAM accesses for old TPU functions

requesting service and mapping the channels into the time-slot sequence. Add six system clocks for time-slot transitions which occur after each time slot. The examples in this section assume the system configuration shown in Table 550. The following shows how to find the WCL for PWM on channel 0.

Assumes one master and one slave. For each additional slave
With one channel linked. Add two clocks for each additional channel linked.

Table 549. Longest threads and RAM accesses for old TPU functions (continued) Table 550. System configuration example

9% RAM Collision Rate (RCR)
CPU clock rate = 40 MHz, or 25 ns per clock period

0 High PWM (driving a DC motor)

1 Middle PPWA (Mode 0, measuring the DC motor speed)

2 Low DIO (Input)

Find the worst-case service time for each active channel.

a) Longest thread of PWM is 24 CPU clocks with four RAM accesses. Channel 0 worst-case service time = 25 CPU clocks. b) Longest thread of PPWA in mode 0 is 44 CPU clocks with nine RAM accesses. Channel 1 worst-case service time = 46 CPU clocks. c) Longest thread of DIO is ten CPU clocks with four RAM accesses. Channel 2 worst-case service time = 11 CPU clocks.

Assume channel 0 has just been serviced and that channels 1 and 2 are continuously

that are granted for each time slot. See Figure 560. Figure 560. Next Servicing for Channel 0

Add time for the six-clock CPU time-slot transitions. See Figure 560 and Table 551.

serviced. Time-slot transitions occur after each time slot.

represent the minimum PWM period. The following shows how to find the WCL for PPWA on channel 1.

Find the worst-case service time for each active channel. See step 1 of previous
Assume channel 1 has just been serviced and that channels 0 and 2 are continuously

that are granted for each time slot. See Figure 561. Figure 561. Next servicing for channel 1

Add time for the six-clock CPU time-slot transitions. See Figure 561 and Table 552.

Table 551. Worst-case latency for channel 0

system performance and latency. a more realistic worst-case latency result than first-pass analysis. Multiphase Motor Commutation TPU Function (COMM)(TPUPN09/ D).

The first-pass analysis makes the assumption that all channels in the system are

slots can then be mapped to each channel at the real rate of request.

If a function is active during system initialization but not during the high-speed running

worst-case latency calculations.

Use a realistic SPRAM collision rate.
Be careful when assigning functions priority levels and channel numbers. Decide which

channel assignments to see how it affects the system. Table 553. Worst-case latency for channel 2

The seven-slot sequence of || H | M | H | L | H | M | H || is asymmetrical when put back-
Make sure that when mapping out channels to the sequence, you choose a worst-case
Instead of always using the longest thread in the function as the worst-case thread,

was correctly derived, but the low time is actually shorter than was estimated. violates the worst-case latency requirements. must measure periods of 5 kHz (200 ms/period). contains no polling of the parameter RAM. Therefore a realistic RCR = 0%. priority. Refer to Table 554. Table 554. First-Try system configuration

0 High PWM at 50 kHz (needs a 4-µs WCL)

1 High PWM at 50 kHz (needs a 4-µs WCL)

a) Longest thread of PWM is 24 CPU clocks with four RAM accesses. Channels 0-2 worst-case service time = 24 CPU clocks. b) Longest thread of PPWA in mode 0 is 44 CPU clocks with nine RAM accesses. Channel 8 worst-case service time = 44 CPU clocks. c) Longest thread of DIO is ten CPU clocks with four RAM accesses. Channel 15 worst-case service time = 10 CPU clocks. To find the WCL for channel 0, assume channel 0 has just finished service. Map the channels in the H-M-H-L-H-M-H sequence. See Figure 563. Figure 563. Worst-case latency for channel 0 (first try) different system configuration. The second-try system configuration is shown in Table 555.

2 High PWM at 5 kHz (needs a 40-µs WCL)

8 Middle PPWA at 5 kHz (needs an 80-µs WCL)

15 Low DIO as input at rate of 1 ms

CPU clock rate = 40 MHz, or 60 ns per clock period

channels in the H-M-H-L-H-M-H sequence. See Figure 564. Figure 564. Worst-case latency for channel 0 (second try) ms, which is within the limit of 4 ms needed for a 50-kHz PWM. channels in the H-M-H-L-H-M-H sequence. See Figure 565. Figure 565. Worst-case latency for channel 2 within the 40 and 80 ms WCL requirements. Table 555. Second-Try system configuration

CPU clock rate = 40 MHz, or 60 ns per clock period

2 Middle PWM at 5 kHz (needs a 40-µs WCL)

keeping channels 2, 8 and 15 within their WCL requirements.

24.6.6 Endianness

24.7 Appendices

24.7.1 Microcycle and I/O timing

Table 556. Second-try system with channel 0 and 1 reconfigured

CPU clock rate = 40 MHz, or 60 ns per clock period

0 High PWM at 50 kHz (needs a 10-µs WCL)

1 High PWM at 50 kHz (needs a 10-µs WCL)

8 Low PPWA at 5 kHz (needs an 80-µs WCL)

Table 557. Parameter addresses and endianness

Figure 566. Execution, Timebase and Channel T2 Timing

Figure 567. Execution, Timebase and Channel T2/T4 Timing edge-triggered design style. full); see Section , Development support features, for more details. associated with the clocks are unaffected. That is, no operation occurs during these states.

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 1013/1740 Input/Output signal delays The synchronizer, filter and edge detection logic delay the input signal transitions. The Filter Delay varies with the filter clock (ETPU_ECR field FPSCK) and the filter mode used, as shown in the Table 487. For any given transition, it depends on the phase of the filter clock when the input transition happens. In integration mode (TCRCLK filtering only), it also depends on the state of the integrator counter. The Total Delay is defined as the number of system clock rising edges between the input transition and the setting of TDLA/B, TCR1/2 incrementing, or EAC tooth sensing (TCRCLK) in angle mode. The synchronizer delay is 2 or 3 system clocks, depending on the phase of the synchronizer when the input transition happens. The edge detection takes 1 more system clock. The total delays are, thus: Min. Total Delay = Min. Synchronizer Delay + Min. Filter Delay + Edge Detection Delay Min. Total Delay = 3 + Min. Filter Delay Max. Total Delay = Max. Synchronizer Delay + Max. Filter Delay + Edge Detection Delay Max. Total Delay = 4 + Max. Filter Delay The channel filters can be bypassed, so nullifying the filter delays in the equations above. The channel output flip-flops drive the eTPU output signals directly, without any synchronous delays. Consult the MCU Reference Manual for information on additional delays added at the integration.

24.7.2 Initialization code example

The code example below initializes ETPU_1 engine and configures eTPU UART FUNCTION to perform the receiver at channel 1 and the transmitter at channel 0. The function works without parity and the data word is 8 bits in size. The initialization code assumes the microcode function previously loaded into SCM. // Initilization program for eTPU engine 1, function microcode previously loaded into SCM. // No angle mode, eTPU UART FUNCTION configured to perform at channels 0 and // Channel0 - Tx_UART // Channel1 - Rx_UART // UART Specifications: // Data word size: 8 bits // Parity: disabled //Bases #define ETPU_BASE 0x000 //MCU-dependent #define SPRAM_BASE 0x000 //MCU-dependent //General Configuration Registers #define ETPU_MCR_OFFSET 0x000 //Module Configuration Register

Enhanced Time Processing Unit (eTPU2) RM0029 1014/1740 Doc ID 15177 Rev 8 #define ETPU_TBCR_1_OFFSET 0x020 //Time Base Configuration Register #define ETPU_ECR_1_OFFSET 0x014 //Engine Configuration Register #define ETPU_CIER_1_OFFSET 0x240 //Channel Interrupt Enable Register #define ETPU_CDTRER_1_OFFSET 0x250 //Data TransF Interrupt Enable Register //channel0 configuration registers #define ETPU_C0CR_1_OFFSET 0x400 //Channel0 Configuration Register #define ETPU_C0SCR_1_OFFSET 0x404 //Channel0 Status Control Register #define ETPU_C0HSRR_1_OFFSET 0x408 //Channel0 Host Service Req. Register //channel1 configuration registers #define ETPU_C1CR_1_OFFSET 0x410 //Channel1 Configuration Register #define ETPU_C1SCR_1_OFFSET 0x414 //Channel1 Status Control Register #define ETPU_C1HSRR_1_OFFSET 0x418 //Channel1 Status Control Register // Tx_UART SPRAM parameters #define MATCH_RATE_TX_OFFSET 0x004 //Channel0 parameter 1 #define DATA_UART_TX_OFFSET 0x008 //Channel0 parameter 2 #define DATA_SIZE_TX_OFFSET 0x00C //Channel0 parameter 3 // Rx_UART SPRAM parameters #define MATCH_RATE_RX_OFFSET 0x024 //Channel1 parameter 1 #define DATA_UART_RX_OFFSET 0x028 //Channel1 parameter 2 #define DATA_SIZE_RX_OFFSET 0x02C //Channel1 parameter 3 #define ETPU_MCR (*((volatile unsigned int*)(ETPU_MCR_OFFSET + ETPU_BASE))) #define ETPU_TBCR_1 (*((volatile unsigned int*)(ETPU_TBCR_1_OFFSET + ETPU_BASE))) #define ETPU_ECR_1 (*((volatile unsigned int*)(ETPU_ECR_1_OFFSET + ETPU_BASE))) #define ETPU_CIER_1 (*((volatile unsigned int*)(ETPU_CIER_1_OFFSET + ETPU_BASE))) #define ETPU_CDTRER_1 (*((volatile unsigned int*)(ETPU_CDTRER_1_OFFSET + ETPU_BASE))) #define ETPU_C0CR_1 (*((volatile unsigned int*)(ETPU_C0CR_1_OFFSET + ETPU_BASE))) #define ETPU_C0SCR_1 (*((volatile unsigned int*)(ETPU_C0SCR_1_OFFSET + ETPU_BASE))) #define ETPU_C0HSRR_1 (*((volatile unsigned int*)(ETPU_C0HSRR_1_OFFSET + ETPU_BASE))) #define ETPU_C1CR_1 (*((volatile unsigned int*)(ETPU_C1CR_1_OFFSET + ETPU_BASE))) #define ETPU_C1SCR_1 (*((volatile unsigned int*)(ETPU_C1SCR_1_OFFSET + ETPU_BASE))) #define ETPU_C1HSRR_1 (*((volatile unsigned int*)(ETPU_C1HSRR_1_OFFSET + ETPU_BASE))) #define MATCH_RATE_TX (*((volatile unsigned int*)(MATCH_RATE_TX_OFFSET + SPRAM_BASE))) #define DATA_UART_TX (*((volatile unsigned int*)(DATA_UART_TX_OFFSET + SPRAM_BASE))) #define DATA_SIZE_TX (*((volatile unsigned int*)(DATA_SIZE_TX_OFFSET + SPRAM_BASE))) #define MATCH_RATE_RX (*((volatile unsigned int*)(MATCH_RATE_RX_OFFSET + SPRAM_BASE)))

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 1015/1740 #define DATA_UART_RX (*((volatile unsigned int*)(DATA_UART_RX_OFFSET + SPRAM_BASE))) #define DATA_SIZE_RX (*((volatile unsigned int*)(DATA_SIZE_RX_OFFSET + SPRAM_BASE))) // Macros #define TCR2_PRESCALER(x) ((x & 0x3F) << 8) #define TCR1_PRESCALER(x) (x & 0xFF) #define CHANNEL_FUNCTION(x) ((x & 0x1F) << 16) #define CHANNEL_PARAM_BASE_ADDR(x) (x & 0xFF) #define FUNCTION_MODE(x) (x & 0x3) #define MATCH_RATE_TRANS(x) (x & 0xFFFF) #define MATCH_RATE_REC(x) (x & 0xFFFF) #define DATA_WORD_Tx(x) (x & 0x3FFF) #define DATA_SIZE_TRANS(x) (x & 0xF) #define DATA_SIZE_REC(x) (x & 0xF) #define HOST_SERV_REQ(x) (x & 0x7) #define ENTRY_TABLE_BASE(x) (x & 0x1F) //ETPU_MCR fields - Module Configuration Register #define PSE 0x00000002 //Parameter sign extension #define SCMMISEN 0x00000200 //SCM MISC enable #define VIS 0x00000040 //SCM visibility #define GTBE 0x00000001 //Global time base enable //ETPU_TBCR_1 fields - Time Base Configuration Register #define TCRCLK_FILTER_TWOSAMPLE 0x00000000 //TCRCLK filter in Two sample mode #define TCRCLK_FILTER_INTEGRATOR 0x00800000 //TCRCLK filter in Integrator mode #define TCRCLK_FILTER_DIV2CLOCK 0x00000000 //TCRCLK filter uses system clock divided by 2 #define TCRCLK_FILTER_CHANNELCLOCK 0x00400000 //TCRCLK filter uses channel clock #define TCR2_RISE 0x00100000 //TCR2 inc rising edge #define TCR2_FALL 0x00200000 //TCR2 inc falling edge #define TCR2_RISEFALL 0x00300000 //TCR2 inc ris and fall #define TCR2_GATEDDIV8 0x00000000 //TCRCLK gates system clock/8 #define TCR1CLK_SOURCE_DIV2 0x00000000 //TCR1 source system clock/2 #define TRC1CLK_SOURCE_TCRCLK 0x00040000 //TCR1 source is TCRCLK pin #define CHANNEL_FILTER_TWOSAMPLEMODE 0x00000000 //Filter:two sample mode #define CHANNEL_FILTER_THREESAMPLEMODE 0x00008000 //Filter:three sample mode #define CHANNEL_FILTER_CONTMODE 0x0000C000 //Filter:continuous mode //ETPU_ECR fields - Engine Configuration Register #define FILTER_PRESCALER_CLOCK_DIV4 0x00010000 //System clock/4 //ETPU_CxCR fields - Channelx Configuration Register #define CHANNEL_INT_ENABLE 0x80000000 //Channel Interrupt enable #define CHANNEL_DATA_TRANSF_REQ_ENABLE 0x40000000 //Channel data transfer req. enable #define CHANNEL_PRIORITY_DISABLE 0x00000000 //Channel disable

Enhanced Time Processing Unit (eTPU2) RM0029 1016/1740 Doc ID 15177 Rev 8 #define CHANNEL_PRIORITY_LOW 0x10000000 //Low priority channel #define CHANNEL_PRIORITY_MIDDLE 0x20000000 //Middle priority channel #define CHANNEL_PRIORITY_HIGH 0x30000000 //High priority channel //DATA_UART - SPRAM #define CLEAR_TDRE 0x007FFFFF //TDRE must be zero to signal new valid //data to be transmitted void init_etpu( ){ volatile int temp; //Initialize eTPU module configuration register(ETPU_MCR) ETPU_MCR = 0x00070000; //SCMSIZE is 16K(7 2K blocks) //Initialize eTPU time base configuration register(ETPU_TBCR) ETPU_TBCR_1 = (TCR1CLK_SOURCE_DIV2 | CHANNEL_FILTER_TWOSAMPLEMODE | TCR1_PRESCALER(8)); //Initialize eTPU engine configuration register(ETPU_ECR) ETPU_ECR_1 = (ENTRY_TABLE_BASE(0x1F) | FILTER_PRESCALER_CLOCK_DIV4); //Write to the channel configuration Registers(ETPU_CxCR) to choose the //function to be performed by the channel and its parameter base address.Standard entry table //is selected. ETPU_C0CR_1 = (CHANNEL_INT_ENABLE | CHANNEL_FUNCTION(15) | CHANNEL_PARAM_BASE_ADDR(0x00)); ETPU_C1CR_1 = (CHANNEL_INT_ENABLE | CHANNEL_FUNCTION(15) | CHANNEL_PARAM_BASE_ADDR(0x02)); //Write to the channel status control registers(ETPU_CxSCR) to choose //variations within the function flow. ETPU_C0SCR_1 = (FUNCTION_MODE(0)); // no parity for transmitter ETPU_C1SCR_1 = (FUNCTION_MODE(0)); // no parity for receiver //write to spram for parameter initialization of each configured //channel MATCH_RATE_TX = MATCH_RATE_TRANS(0x412); //setup match rate for transmitter DATA_UART_TX = DATA_WORD_TX(0x000000AA); //load first byte to be transmitted=AA DATA_SIZE_TX = DATA_SIZE_TRANS(8); //8-bit data word for transmitter MATCH_RATE_RX = MATCH_RATE_REC(0x412); //setup match rate for receiver DATA_SIZE_RX = DATA_SIZE_REC(8); //8-bit data word for receiver //Write to Channel host service request registers(ETPU_CxHSRR) to //initialize active channels(Channel 0 and 1) ETPU_C0HSRR_1 = HOST_SERV_REQ(3); ETPU_C1HSRR_1 = HOST_SERV_REQ(2); //write to Channel priority field to enable each channel by //assigning it a high,middle or low priority ETPU_C0CR_1 =(ETPU_C0CR_1 | CHANNEL_PRIORITY_HIGH); ETPU_C1CR_1 =(ETPU_C1CR_1 | CHANNEL_PRIORITY_HIGH); //Monitor channel host service request register for completion //of initialization

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 1017/1740 //HSR should be zero in the end of initialization do temp = ETPU_C0HSRR_1; } while (temp != 0); do temp = ETPU_C1HSRR_1; } while (temp != 0); //Write GTBE bit to start TCR1 and TCR2 time bases counting //at the same time ETPU_MCR = (ETPU_MCR | GTBE); }// end of etpu_initialization routine

24.7.3 Predefined channel mode summary

Table 558 explains channel double match predefined submode functionality by showing all event sequence possibilities. The initial state considered for all submodes is channel flags MRLA, MRLB, TDLA and TDLB reset. From initial state one can follow the table and verify how each submode behaves in a determined sequence of events. Note that the actions performed by an event type depend on all previous events following the initial state, for a given channel submode. There are three columns for each event: one for event type, one for enable/disable actions and one for capture. Event type column can be matchA, matchB, transA and transB (for double transition modes). Enable/disable actions column (identified as “blocks” in column head) specifies which other events are enabled or disabled. Initially disabled events (specified in “initially blocked” column) are usually enabled by other events. In double transition submodes, the first transition detected is always considered transA and the second is considered transB. This means that transA event actually enables the detection of transB event. This is not explicit in the table, since it is a general behavior for all double transition submodes. A sequence of four events (two matches and two transitions) are necessary to describe the behavior of some channel submodes. When a determined sequence of events has less than four events, the other event columns are left blank. Cells in an “event type” column that have light-grayed background indicate that a service request is generated. More than one event in the same event sequence can issue service request. Note: The table does not exhaust all possibilities of channel logic event sequences, because it does not account for possible microcode interventions. For instance, if matches are blocked by first transition and microcode resets TDLA, the matches become enabled again, and from this point on the channel behaves as if the first transition had never occurred.

Table 558. Predefined channel mode summary

Table 558. Predefined channel mode summary (continued)

Transition A always enables Transition B
sm_st is compatible with TPU3 channel logic.
It is not possible to include all functionality of this submode in table. See Section , Single Match Enhanced Mode (sm_st_e) , for more details.

RM0029 Enhanced Time Processing Unit (eTPU2) Doc ID 15177 Rev 8 1021/1740

24.7.4 MISC algorithm

The MISC generator is based on the following polynomial: G(x) = 1 + x1 + x2 + x22 + x31 (equivalent to feedback mask = 0x80400007) The MISC signature generation starts by clearing the MISC Accumulator value to 0 and preloading the MISC Counter with the highest SCM address. It then steps through each address decrementing the counter, reading 32 bit values and following the algorithm below: If the least significant bit in MISC is 1 then MISC = MISC right shifted by 1 bit MISC = MISC XOR 0x80400007 else MISC = MISC right shifted by 1 bit end if MISC = MISC XOR RAM data The code example below shows an excerpt of C code that calculates the MISC signature for a given array of data, based on the previous algorithm: #define SCM_size (MAX_SCM_ADDRESS / 4) /* last byte address - converted to 32-bit word */ #define POLY 0x80400007 /* G(x) = 1 + x 1 + x2 + x22 + x31 */ FUNCTION : void calc_misc() PURPOSE : This function calculates the MISC value. INPUTS NOTES : none RETURNS NOTES : MISC value GENERAL NOTES : the array’unsigned int data[]’ represents the actual memory array, organized in 32-bit words. unsigned int calc_misc (void) int j; /* loop counter */ unsigned int misc = 0; for (j = (SCM_size-1); j >= 0 ; j--) { /* SCM_size has the number of 32- bit words in SCM */ if (misc & 0x1) { misc >>= 1; misc ^= POLY; else { misc >>= 1; misc ^= data[j]; /* data[j] is the actual 32-bit word taken from the SCM array */ return (misc); /* final signature calculated */

Enhanced Time Processing Unit (eTPU2) RM0029 1022/1740 Doc ID 15177 Rev 8 The value calculated by this algorithm must be loaded into register ETPU_MISCCMPR prior to activating the SCM MISC calculator in eTPU. Once the MISC calculator is activated (bit SCMMISEN in register ETPU_MCR is written to 1) eTPU itself will start this procedure (au) reading the SCM whenever allowed by microengine. At the end of the cycle, when all the array has been read and the SCM signature is calculated, the Host CPU can be notified via Global Exception if the MISC Accumulator does not match the value in ETPU_MISCCMPR. Equation 12 shows how the average time taken by MISC to complete the signature of the whole SCM can be calculated. Equation 12 Average MISC period = S / (4 * f * (1 - L)) In Equation 12, f = clock frequency S = SCM size in bytes L = eTPU load (as a percentage of execution clocks over a period of time, including TST clocks) Further detail on MISC calculation can be found on Section , SCM Test – Multiple input signature calculator. au. eTPU MISC hardware is optimized to read 32-bit words from memory and to calculate this CRC in parallel, rather than shifting one bit at a time. The actual implementation inside eTPU, although bringing to the same results, does not match exactly the algorithm shown here.

RM0029 Enhanced Queued Analog-to-Digital Converter (EQADC) Doc ID 15177 Rev 8 1023/1740

25 Enhanced Queued Analog-to-Digital Converter

(EQADC)

25.1 Information Specific to This Device

This section presents device-specific parameterization and customization information not specifically referenced in the remainder of this chapter.

25.1.1 Device-Specific Pin Configuration Features

The following eQADC pins are multiplexed and configuration of the corresponding Systems Integration Unit (SIU) registers is necessary. AN12/MA0/SDS These pins are configured by setting the Pad Configuration Register 215 (SIU_PCR215) on the SIU. Note: Attempts to convert the input voltage applied to this pin while the MA0 or the SDS functions are selected will result in an undefined conversion result. As this pin is also used by digital logic, it has reduced analog to digital conversion accuracy when compared to the AN[0:11,16:39] analog input pins. AN13/MA1/SDO These pins are configured by setting the Pad Configuration Register 216 (SIU_PCR216) on the SIU. Note: Attempts to convert the input voltage applied to this pin while the MA1 or the SDO functions are selected will result in an undefined conversion result. As this pin is also used by digital logic, it has reduced analog to digital conversion accuracy when compared to the AN[0:11,16:39] analog input pins. AN14/MA2/SDI These pins are configured by setting the Pad Configuration Register 217 (SIU_PCR217) on the SIU. Note: Attempts to convert the input voltage applied to this pin while the MA2 or the SDI functions are selected will result in an undefined conversion result. As this pin is also used by digital logic, it has reduced analog to digital conversion accuracy when compared to the AN[0:11,16:39] analog input pins. AN15/FCK These pins are configured by setting the Pad Configuration Register 218 (SIU_PCR218) on the SIU. Note: Attempts to convert the input voltage applied to this pin while the FCK function is selected will result in an undefined conversion result. As this pin is also used by digital logic, it has reduced analog to digital conversion accuracy when compared to the AN[0:11,16:39] analog input pins.

Enhanced Queued Analog-to-Digital Converter (EQADC) RM0029 1024/1740 Doc ID 15177 Rev 8 External Triggers The source of the eQADC external triggers can be the eTPU, the eMIOS, or an external signal. The source is selected by configuring the eQADC Trigger Input Select Register (SIU_ETISR) on the SIU.

25.1.2 Availability of Analog Inputs

Analog inputs ANR, ANS, ANT and ANU are not available on SPC564A74xx, SPC564A80xx devices.

25.2 Introduction

25.2.1 Module overview

The Enhanced Queued Analog-to-Digital Converter (EQADC) block provides accurate and fast conversions for a wide range of applications. The EQADC provides a parallel interface to two on-chip analog-to-digital converters (ADCs), a single master to single slave serial interface to an off-chip external device, and a parallel side interface to one or more on-chip digital signal processing (DSP) modules (for example, a decimation filter). The two on-chip ADCs are architected to allow access to all the analog channels. The EQADC transfers commands from multiple Command FIFOs (CFIFOs) to the on-chip ADCs or to the external device. The multiple Result FIFOs (RFIFOs) can receive data from the on-chip ADCs, from an off-chip external device or from an on-chip DSP module. Data from the on-chip ADCs can be routed to the side interface, processed by the on-chip DSP and then routed back through the side interface to the RFIFOs. The EQADC supports software and external hardware triggers from other blocks to initiate transfers of commands from the CFIFOs to the on-chip ADCs or to the external device. It also monitors the fullness of CFIFOs and RFIFOs, and accordingly generates DMA or interrupt requests to control data movement between the FIFOs and the system memory, which is external to the EQADC.

25.2.2 Block diagram

Figure 570 is the block diagram for the EQADC. Figure 570. EQADC Block Diagram

Enhanced Queued Analog-to-Digital Converter (EQADC) RM0029 1026/1740 Doc ID 15177 Rev 8 The FIFO Control Unit performs the following functions:

It prioritizes the CFIFOs to determine what CFIFOs will have their commands transferred.
Supports software and hardware triggers to start command transfers from a particular CFIFO.
Decodes command data from the CFIFOs, and accordingly, sends these commands to one of the two on-chip ADCs or to the external device.
Decodes result data from on-chip ADCs or from the external device, and transfers data to the appropriate RFIFO or to the parallel side interface. The ADC Control Logic manages the execution of commands bound for on-chip ADCs. It interfaces with the CFIFOs via two 2-entry command buffers (CBuffers) with abort control and with the RFIFOs and side interface via the Result Format and Calibration Sub-Block. The ADC Control Logic performs the following functions:
Buffers command data for execution.
Decodes command data and accordingly generates control signals for the two on-chip ADCs.
Detects abort request, stores aborted commands and buffers immediate conversion commands.
Formats and calibrates conversion result data coming from the on-chip ADCs.
Generates the internal multiplexer control signals and the select signals used by the external multiplexers. The EQADC SSI allows for a full duplex, synchronous, serial communication between the EQADC and an external device. The EQADC PSI allows for a full duplex, synchronous, parallel communication between the EQADC and decimation filters A and B and reaction modules. Figure 570 also depicts data flow through the EQADC. Commands are contained in system memory in a user defined data structure. The most likely data structure to be used is a queue as depicted in the Figure 570 (aw). Command data is moved from the command queue (CQueue) to the CFIFOs by either the host CPU or by the DMAC. Once a CFIFO is triggered and becomes the highest priority CFIFO using a certain CBuffer, command data is transferred from the CFIFO to the on-chip ADCs, or to the external device. The ADC executes the command, and the result is moved through the Result Format and Calibration Sub-Block to either the side interface or to the RFIFO. Data from the external device or on- chip companion module bypasses the Result Format and Calibration Sub-Block and is moved directly to its specified RFIFO. When data is stored in an RFIFO, data is moved from the RFIFO by the host CPU or by the DMAC to a data structure in system memory depicted in the Figure 570 as a result queue (RQueue). For users familiar with the QADC, the EQADC system upgrades the functionality provided by that block. Refer to Section 25.7.7, EQADC versus QADC, for a comparison between the EQADC and QADC. av. Decimation filters A and B and Reaction module aw. Command and result data can be stored in system memory in any user defined data structure. However, in this document it will be assumed that the data structure of choice is a queue, since it is the most likely data structure to be used and because queues are the only ty pe of data structure supported by the DMAC.

RM0029 Enhanced Queued Analog-to-Digital Converter (EQADC) Doc ID 15177 Rev 8 1027/1740

25.2.3 Features

The EQADC Block includes these distinctive features:

Two independent on-chip RSD Cyclic ADCs – 8, 10, and 12 bits AD Resolution – Targets up to 10 bit accuracy at 500KSample/s (ADC_CLK=7.5 MHz) and 8 bit accuracy at 1M Sample/s (ADC_CLK=15 MHz) for differential conversions – Selectable common mode conversion range (0 - 5V; 0 - 2.5V; 0 - 1.25V) – Differential conversions – Differential channels include variable gain amplifier for improved dynamic range (x1; x2; x4) – Differential channels include programmable pull-up and pull-down resistors for biasing and sensor diagnostics (200k ohms; 100k ohms; 5k ohms) – Sample times of 2 (default), 8, 64 or 128 ADC clock cycles – Provides time stamp information when requested – Parallel interface to EQADC CFIFOs and RFIFOs – Supports both right-justified unsigned and signed formats for conversion results – The REFBYPC pin stabilizes one of internal generated reference – Temperature sensor – Ability to measure directly Vdd
Automatic application of ADC calibration constants – Provision of reference voltages (25%VREF and 75%VREF) for ADC calibration purposes
40 input channels available to the two on-chip ADCs
4 pairs of differential analog input channels
Full duplex synchronous serial interface to an external device – Has a free-running clock for use by the external device – Supports a 26-bit message length – Transmits a null message when there are no triggered CFIFOs with commands bound for external CBuffers, or when there are triggered CFIFOs with commands bound for external CBuffers but the external CBuffers are full
Parallel Side Interface to communicate with several on-chip companion modules
STAC bus Client Interface to import an alternative timebase to the internal time stamp
Priority Based CFIFOs – Supports six CFIFOs with fixed priority. The lower the CFIFO number, the higher its priority. When commands of distinct CFIFOs are bound for the same CBuffer, the higher priority CFIFO is always served first. – Immediate conversion command feature with conversion abort control – Streaming mode operation of CFIFO0 to execute some commands several times – Supports software and several hardware trigger modes to arm a particular CFIFO – Generates interrupt when command coherency is not achieved
External Hardware Triggers – Supports rising edge, falling edge, high level and low level triggers – Supports configurable digital filter

Enhanced Queued Analog-to-Digital Converter (EQADC) RM0029 1028/1740 Doc ID 15177 Rev 8 – Supports controls to bypass the trigger digital filters

Two Triggers operation mode for queue0 – Additional internal trigger (not filtered) called Advance trigger that is used to enable the external trigger of queue0 and to control the loop behavior of CFIFO0
Supports 4 to 8 external 8-to-1 muxes which can expand the input channel number from 40 to 96
Upgrades the functionality provided by the QADC

25.3 Modes of operation

This section describes the operation modes of the EQADC.

25.3.1 Normal mode

This is the default operational mode when the EQADC is not in streaming mode or background debug or stop mode.

25.3.2 Streaming mode

This mode is characterized by two main aspects: the abort action by CFIFO0 in any current conversion process started from another queue, and the loop behavior of the CFIFO0. In some applications, there may be sequences of identical commands each spaced only by a few microseconds. To reduce the DMA data transfer, in this mode a short command queue can be stored in CFIFO0 and repeatedly be executed based on a timed trigger, but advance to the next (repeating) sequence of commands based on another device’s internal trigger. The CFIFO0 delivers commands to the ADC as before, but those commands are not ‘invalidated’ after they are sent (in fact, they are ‘invalidated’ only because the Transfer Next Data Pointer has moved on). When it encounters these repeated commands the CFIFO0 only fills once, using the DMA as usual, until either it is full or a command with End-of- Queue is encountered. Thereafter the sub-queue repeats/wraps. The number of commands loaded is unaffected by the delivery of commands once the streaming mode is configured, since no commands loaded are invalidated even if sent before all the queue is loaded. The number of entries in the CFIFO0 is extended to eight (configurable). This is to facilitate the targeted applications. The repeating subqueue must be contained within the eight CFIFO0 entries. To maintain compatibility, CFIFO0 by default operates as it does before, without streaming and with four entries. Streaming, and additional entries, can be enabled independently. Streaming mode is selected as another mode for queue 0 using the configuration bits in the EQADC_CFCR register. Streaming mode makes use of an additional bit in the Conversion Command Word (CCW); this bit is called ‘Repeat’. The purpose of this bit is to mark in the command queue, where to start a repeating sequence. Streaming mode requires two trigger inputs. The standard queue 0 trigger, in this mode referred to as ‘Repeat Trigger’ and a second internal trigger input to the eQADC called ‘Advance’ trigger.

RM0029 Enhanced Queued Analog-to-Digital Converter (EQADC) Doc ID 15177 Rev 8 1029/1740

25.3.3 Debug mode

Upon a debug mode entry request, EQADC behavior will vary according to the status of the DBG field in Section , EQADC Module Configuration Register (EQADC_MCR). If DBG is programmed to 0b00, the debug mode entry request is ignored. If DBG is programmed to 0b10 or to 0b11, the EQADC will enter debug mode. In case the EQADC SSI is enabled, the free running clock (FCK) output to external device will not stop when DBG is programmed to 0b11, but FCK will stop in low phase, when DBG is programmed to 0b10. During debug mode, the EQADC will not transfer commands from any CFIFOs, no null messages will be transmitted to the external device, no data will be returned to any RFIFO, no hardware trigger event will be captured, and all EQADC registers can be accessed as in Normal mode. The latter implies that CFIFOs can still be triggered using software triggers, since no scheme is implemented to write-protect registers during debug mode. DMA and interrupt requests continue to be generated as in Normal Mode. If at the time the debug mode entry request is detected, there are commands in the on-chip CBuffers that were already under execution, these commands will be completed but the generated results, if any, will not be sent to the RFIFOs until debug mode is exited. Commands whose execution has not started will not be executed until debug mode is exited.The clock associated with an on-chip ADC stops, during its low phase, after the ADC ceases executing commands. The time base counter will only stop after all on-chip ADCs cease executing commands. When exiting debug mode, the EQADC relies on the CFIFO operation modes and on the CFIFO status to determine the next command entry to transfer. The EQADC internal behavior after the debug mode entry request is detected differs depending on the status of command transfers.

No command transfer is in progress. The EQADC immediately halts future command transfers from any CFIFO. If a null message is being transmitted, EQADC will complete the serial transmission before halting future command transfers. If valid data (conversion result or data read from an ADC register) is received at the end of transmission, it will not be sent to an RFIFO until debug mode is exited. If the null message transmission is aborted, the EQADC will complete the abort procedure before halting future command transfers from any CFIFO. The message of the CFIFO that caused the abort of the previous serial transmission will only be transmitted after debug mode is exited.
Command transfer is in progress. EQADC will complete the transfer and update CFIFO status before halting future command transfers from any CFIFO. Command transfers to the internal CBuffers are considered completed when a command is written to the buffers. Command transfers to the external device are considered completed when the serial transmission of the command is completed. If valid data (conversion result or data read from an ADC register) is received at the end of a serial transmission, it will not be sent to an RFIFO until debug mode is exited. The CFIFO status bits will still be updated after the completion of the serial transmission, therefore, after debug mode entry request is detected, the EQADC status bits will only stop changing several system clock cycles after the on-going serial transmission completes. If the command message transmission is aborted, the EQADC will complete the abort procedure before halting future command transfers from any CFIFO. The message of

Enhanced Queued Analog-to-Digital Converter (EQADC) RM0029 1030/1740 Doc ID 15177 Rev 8 the CFIFO that caused the abort of the previous serial transmission will only be transmitted after debug mode is exited.

Command/Null message transfer through serial interface was aborted but next serial transmission did not start. If the debug mode entry request is detected between the time a previous serial transmission was aborted and the start of the next transmission, the EQADC will complete the abort procedure before halting future command transfers from any CFIFO. The message of the CFIFO that caused the abort of the previous serial transmission will only be transmitted after debug mode is exited.

25.3.4 Stop mode

Upon a stop mode entry request detection, the EQADC progressively halts its operations until it reaches a static, stable state from which it can recover when returning to Normal mode. EQADC then asserts an acknowledge signal, indicating that it is static and that the clock input can be stopped. In stop mode, the free running clock (FCK) output to external device will stop during its low phase if the EQADC SSI is enabled, and no hardware trigger events will be captured. The latter implies that, as long as the system clock is running, CFIFOs can still be triggered using software triggers, since no scheme is implemented to write-protect registers during stop mode. If at the time the stop mode entry request is detected, there are commands in the on-chip CBuffers that were already under execution, these commands will be completed but the generated results, if any, will not be sent to the RFIFOs until stop mode is exited. Commands whose execution has not started will not be executed until stop mode is exited. After these remaining commands are executed, the clock input to the ADCs is stopped. The ADC clock stops during its low phase. The time base counter will only stop after all on-chip ADCs cease executing commands. Only then, the stop acknowledge signal is asserted. When exiting stop mode, the EQADC relies on the CFIFO operation modes and on the CFIFO status to determine the next command entry to transfer. The EQADC internal behavior after the stop mode entry request is detected differs depending on the status of the command transfer.

No command transfer is in progress The EQADC immediately halts future command transfers from any CFIFO. If a null message is being transmitted, EQADC will complete the transmission before halting future command transfers. If valid data (conversion result or data read from an ADC register) is received at the end of the transmission, it will not be sent to an RFIFO until stop mode is exited. If the null message transmission is aborted, the EQADC will complete the abort procedure before halting future command transfers from any CFIFO. The message of the CFIFO that caused the abort of the previous serial transmission will only be transmitted after stop mode is exited.
Command transfer is in progress EQADC will complete the transfer and update CFIFO status before halting future command transfers from any CFIFO. Command transfers to the internal CBuffers are considered completed when a command is written to the buffers. Command transfers to the external device are considered completed when the serial transmission of the command is completed. If valid data (conversion result or data read from an ADC register) is received at the end of a serial transmission, it will not be sent to an RFIFO until stop mode is exited. The CFIFO status bits will still be updated after

after the on-going serial transmission completes. transmitted after stop mode is exited.

Command/Null message transfer through serial interface was aborted but next serial transmission did not start. If the stop mode entry request is detected between the time a previous serial transmission was aborted and the start of the next transmission, the EQADC will complete the abort procedure before halting future command transfers from any CFIFO. The message of the CFIFO that caused the abort of the previous serial transmission will only be transferred after stop mode is exited.

25.4 External signal description

25.4.1 Overview

The following is a list of external pins. or not be available external to the chip. Refer to the Signals chapter for details. Table 559. External Signals

Table 559. External Signals (continued)

25.4.2 Detailed signal descriptions

of the differential analog input DAN0 (DAN0+ - DAN0-). of the differential analog input DAN0 (DAN0+ - DAN0-).

Enhanced Queued Analog-to-Digital Converter (EQADC) RM0029 1034/1740 Doc ID 15177 Rev 8 AN2/DAN1+ — Single-ended analog input/Differential analog input positive terminal AN2 is a single-ended analog input to the two on-chip ADCs. DAN1+ is the positive terminal of the differential analog input DAN1 (DAN1+ - DAN1-). AN3/DAN1— — Single-ended analog input/Differential analog input negative terminal AN3 is a single-ended analog input to the two on-chip ADCs. DAN1- is the negative terminal of the differential analog input DAN1 (DAN1+ - DAN1-). AN4/DAN2+ — Single-ended analog input/Differential analog input positive terminal AN4 is a single-ended analog input to the two on-chip ADCs. DAN2+ is the positive terminal of the differential analog input DAN2 (DAN2+ - DAN2-). AN5/DAN2— — Single-ended analog input/Differential analog input negative terminal AN5 is a single-ended analog input to the two on-chip ADCs. DAN2- is the negative terminal of the differential analog input DAN2 (DAN2+ - DAN2-). AN6/DAN3+ — Single-ended analog input/Differential analog input positive terminal AN6 is a single-ended analog input to the two on-chip ADCs. DAN3+ is the positive terminal of the differential analog input DAN3 (DAN3+ - DAN3-). AN7/DAN3— — Single-ended analog input/Differential analog input negative terminal AN7 is a single-ended analog input to the two on-chip ADCs. DAN3- is the negative terminal of the differential analog input DAN3 (DAN3+ - DAN3-). AN8/ANW — Single-ended analog input/ Single-ended analog input from external multiplexers AN8 is a single-ended analog input to the two on-chip ADCs. ANW is a single-ended analog input to one of the on-chip ADCs in external multiplexed mode. AN9/ANX — Single-ended analog input/ Single-ended analog input from external multiplexers AN9 is a single-ended analog input to the two on-chip ADCs. ANX is a single-ended analog input to one of the on-chip ADCs in external multiplexed mode. AN10/ANY — Single-ended analog input/ Single-ended analog input from external multiplexers AN10 is a single-ended analog input to the two on-chip ADCs. ANY is a single-ended analog input to one of the on-chip ADCs in external multiplexed mode.

RM0029 Enhanced Queued Analog-to-Digital Converter (EQADC) Doc ID 15177 Rev 8 1035/1740 AN11/ANZ — Single-ended analog input/ Single-ended analog input from external multiplexers AN11 is a single-ended analog input to the two on-chip ADCs. ANZ is a single-ended analog input to one of the on-chip ADCs in external multiplexed mode. AN12 — Single-ended analog input AN12 is a single-ended analog input to the two on-chip ADCs. AN13 — Single-ended analog input/ AN13 is a single-ended analog input to the two on-chip ADCs. AN14 — Single-ended analog input AN14 is a single-ended analog input to the two on-chip ADCs. AN15 — Single-ended analog input AN15 is a single-ended analog inputs to the two on-chip ADCs. AN16 — Single-ended analog input/ AN16 is a single-ended analog input to the two on-chip ADCs. AN17 — Single-ended analog input AN17 is a single-ended analog input to the two on-chip ADCs. AN18 — Single-ended analog input AN18 is a single-ended analog input to the two on-chip ADCs. AN19 — Single-ended analog input AN19 is a single-ended analog input to the two on-chip ADCs. AN20-AN39 — Single-ended analog input AN20 through AN39 are single-ended analog inputs to the two on-chip ADCs. INA_ADC0_0 - INA_ADC0_9 — Single-ended analog input INA_ADC0_0 through INA_ADC0_9 are single-ended analog inputs to the on-chip ADC0. INA_ADC1_0 - INA_ADC1_9 — Single-ended analog input INA_ADC1_0 through INA_ADC1_9 are single-ended analog inputs to the on-chip ADC1. MA0-MA2 — External multiplexer control signals MA0, MA1, and MA2 combined form a select signal associated with external multiplexers. FCK — EQADC SSI free-running clock FCK is a free-running clock signal for synchronizing transmissions between the EQADC (master) and the external (slave) device.

SDI is the serial data input signal from the external (slave) device. SDO is the serial data output signal to the external (slave) device. while VRL is the lowest voltage reference. pin for the ADCs. Refer to electrical specifications. stable reference voltage for the ADC.

25.5 Memory Map/Register Definition

to or read from reserved areas of the memory map is undefined.

25.5.1 EQADC Memory Map

This section provides memory maps for the EQADC block. Table 560. EQADC Memory Map

Table 560. EQADC Memory Map (continued)

25.5.2 EQADC Register Descriptions

Figure 571. EQADC Module Configuration Register (EQADC_MCR)

Note: When disabling the EQADC SSI, the FCK will not stop until it reaches its low phase. undefined and written data is ignored. Table 561. EQADC Module Configuration Regi ster (EQADC_MCR) field description immediate conversion command from CFIFO0 in the requested ADCn. 1 Enable immediate conversion command request. 0 Disable immediate conversion command request. Table 562. EQADC SSI Enable Field Table 563. Debug Enable Field 0b00 Do not enter debug mode. stops while the EQADC is in debug mode. free running while the EQADC is in debug mode.

receive data. Refer to page 1099 for more information on the MESSAGE_TAG field. Register (EQADC_MCR)) is not recommended. bypass the digital filter when this is not needed. Figure 574. EQADC External Trigger Digital Filter Register (EQADC_ETDFR) Table 564. EQADC Null Message Send Format Register (EQADC_NMSFR) field description on the format of a null message.

Table 565. EQADC External Trigger Digital Filter Register (EQADC_ETDFR) field description more information on the digital filter. considered and the trigger input signal is not filtered. Table 566. Minimum Required Time to Valid ETRIG

EQADC, for a description on command message formats. Figure 575. EQADC CFIFO Push Register x (EQADC_CFPRx) Table 567. EQADC CFIFO Push Register x (EQADC_CFPRx) field description any write to the CF_PUSHx. Reading the EQADC_CFPRx always returns zero. target locations for the write.

Figure 576. EQADC RFIFO Pop Register x (EQADC_RFPRx) The EQADC CFIFO Control Registers (EQADC_CFCR) contain bits that affect CFIFOs. These bits specify the CFIFO operation mode and can invalidate all of the CFIFO contents. Table 568. EQADC RFIFO Pop Register x (EQADC_RFPRx) field description When RFIFOx is not empty, the RF_POPx contains the next unread entry value of RFIFOx. value. Writing to EQADC_RFPRx has no effect.

Figure 579. EQADC CFIFO Control Register 2 (EQADC_CFCR2) Table 569. EQADC CFIFO Control Register x (EQADC_CFCRx) field description extension. For more details, refer to Section , CFIFO0 Streaming Mode Description. 1 Enable the extension of CFIFO0 entries. 0 CFIFO0 has a normal value of entries. refer to Section , CFIFO0 Streaming Mode Description. 1 Enable the streaming mode of CFIFO0. 0 Streaming mode of CFIFO0 is disabled. FIFO and Interrupt Status Registers (EQADC_FISR), if the CFIFO is in single-scan mode. to SSEx has no effect. SSEx always is read as “0”.

read as “0”. Writing a “0” has no effect. Invalidate all of the entries in the corresponding CFIFO. and results generated by them will be stored in the appropriate RFIFO. Section , CFIFO Scan Trigger Modes, for more information on CFIFO trigger mode. disabled and the CFIFO status is IDLE , MODEx can be changed to any other mode. mode, see Table 571. The use of reserved values drives to unknown behavior of the block. advance the command queue, the normal mode of oper ation is external trigger single scan. Other settings are not fully tested. Table 569. EQADC CFIFO Control Register x (EQADC_CFCRx) field description (continued) Table 570. CFIFO Operation Mode Table

EQADC FIFO and Interrupt Status Registers (EQADC_FISR). Figure 580. EQADC Interrupt and DMA Control Register 0 (EQADC_IDCR0) Table 570. CFIFO Operation Mode Table (continued) Table 571. CFIFO0 Advance Trigger Operation Mode Table

0 CFFE

0000 RFOI

0 RFD

Figure 581. EQADC Interrupt and DMA Control Register 1 (EQADC_IDCR1) Figure 582. EQADC Interrupt and DMA Control Register 2 (EQADC_IDCR2)

0 CFF

Table 572. EQADC Interrupt and DMA Control Re gister x (EQADC_IDCRx) field description in Section , EQADC FIFO and Interrupt Status Registers (EQADC_FISR), is asserted. 1 Enable non-coherency interrupt request. 0 Disable non-coherency interrupt request. enabled). See Section 25.6.8, EQADC DMA/Interrupt request, for details. 1 Enable trigger overrun interrupt request. 0 Disable trigger overrun interrupt request. Section , EQADC FIFO and Interrupt Status Registers (EQADC_FISR), is asserted. 1 Enable pause interrupt request. 0 Disable pause interrupt request. 1 Enable End of Queue interrupt request. 0 Disable End of Queue interrupt request. Section 25.6.8, EQADC DMA/Interrupt request, for details. 1 Enable Underflow Interrupt request. 0 Disable Underflow Interrupt request.

Registers (EQADC_FISR), is asserted. 1 Enable CFIFO Fill DMA or Interrupt request. 0 Disable CFIFO Fill DMA or Interrupt request. CFFEx must not be negated while a DMA transaction is in progress. request if CFFSx is asserted. 1 Generate DMA request to move data from the system memory to CFIFOx. 0 Generate interrupt request to move data from the system memory to CFIFOx. CFFSx must not be negated while a DMA transaction is in progress. Section 25.6.8, EQADC DMA/Interrupt request, for details. 1 Enable Overflow Interrupt request. 0 Disable Overflow Interrupt request.

effect. Status bits are read only. These bits indicate the status of the FIFO itself. Registers (EQADC_FISR), is asserted. 1 Enable RFIFO Drain DMA or Interrupt request. 0 Disable RFIFO Drain DMA or Interrupt request. RFDEx must not be negated while a DMA transaction is in progress. request when RFDSx is asserted. 1 Generate DMA request to move data from RFIFOx to the system memory. 0 Generate interrupt request to move data from RFIFOx to the system memory. RFDSx must not be negated while a DMA transaction is in progress.

Figure 583. EQADC FIFO and Interrupt Status Register x (EQADC_FISRx)

00000 RFO

0 RFDF

Table 573. EQADC FIFO and Interrupt Status Re gister x (EQADC_FISRx) field description Sequence Non-Coherency Detection. 1 Command sequence being transferred by CFIFOx became non-coherent. 0 Command sequence being transferred by CFIFOx is coherent. (EQADC_IDCR), and TORFx are asserted, an interrupt request will be generated. enabled). See Section 25.6.8, EQADC DMA/Interrupt request, for details. Write “1” to clear the TORFx bit. Writing a “0” has no effect. 0 No trigger overrun occurred. The trigger overrun flag will not set for CFIFOs configured for software trigger mode.

of the entry is completed. In software trigger mode, PFx will never become asserted. effect. Refer to Section , Pause Status, for more information on the Pause Flag.

1 Entry with asserted PAUSE bit was transferred from CFIFOx (CFIFO in edge trigger

(CFIFO in level trigger mode).

0 Entry with asserted PAUSE bit was not transferred from CFIFOx (CFIFO in edge trigger

gate (CFIFO in level trigger mode). 1 Entry with asserted EOQ bit was transferred from CFIFOx. 0 Entry with asserted EOQ bit was not transferred from CFIFOx. for all previously transferred commands has been returned to the appropriate RFIFO.

underflowing CFIFO, nor will command transfers from lower priority CFIFOs be blocked. and CFUFx are both asserted, the EQADC generates an interrupt request. Section 25.6.8, EQADC DMA/Interrupt request, for details. Write “1” to clear CFUFx. Writing a “0” has no effect. 1 A CFIFO underflow event occurred. 0 No CFIFO underflow event occurred. single-scan software-trigger mode. Refer to Section , Single-Scan Mode, for further details. Section , EQADC CFIFO Control Registers (EQADC_CFCR), is changed to disabled. Writing to SSSx has no effect. SSSx has no effect in continuous-scan or in disabled mode. single-scan software-trigger mode is triggered. single-scan software-trigger mode is not triggered. automatically cleared by the EQADC when the CFIFO becomes full. Writing “1” to CFFFx when CFFSx is asserted (DMA requests selected) is not allowed. ISR after the CFIFOx push register is accessed.

both asserted, the EQADC generates an interrupt request. Section 25.6.8, EQADC DMA/Interrupt request, for details. Write “1” to clear RFOFx. Writing a “0” has no effect. 1 An RFIFO overflow event occurred. 0 No RFIFO overflow event occurred. cleared by the EQADC when the RFIFO becomes empty. 1 RFIFOx has at least one valid entry. Writing “1” to RFDFx when RFDSx is asserted (DMA requests selected) is not allowed. the ISR after the RFIFOx pop register is accessed. CFIFO Basic Functionality. Writing any value to TNXTPTRx has no effect.

command transfers from a CFIFO. Figure 584. EQADC CFIFO Transfer Counter Register 0 (EQADC_CFTCR0) mapped address inside RFIFOx. POPNXTPTRx is updated when EQADC_RFPRx is read. Functionality. Writing any value to POPNXTPTRx has no effect.

because of the transfer of the current command that is about to be popped from the CFIFO. Figure 587. EQADC CFIFO Status Snapshot Register 0 (EQADC_CFSSR0) Table 574. EQADC CFIFO Transfer Counter Regi ster x (EQADC_CFTCRx) field description resets to zero after EQADC completes transferring a command with an asserted EOQ bit. Writing any value to TC_CFx sets the counter to that written value.

Table 575. EQADC CFIFO Status Snapshot Regi ster x (EQADC_CFSSRx) field description CFSx_TCBn indicates the CFIFOx status of previously completed command transfer. from CFIFOx when a current command transfer from CFIFOx to CBuffern is initiated. transmission through the EQADC SSI is initiated. ECBNI indicates to which external CBuffer the previous command was transmitted. 1 Last command was transferred to CBuffer3. 0 Last command was transferred to CBuffer2. Last CFIFO to Transfer Commands through the EQADC SSI. transmission of null messages. Table 576. LCFTCB n Description

The EQADC CFIFO Status Register (EQADC_CFSR) contains the current CFIFO status. Figure 590. EQADC CFIFO Status Register (EQADC_CFSR) Table 576. LCFTCB n Description (continued) Table 577. LCFTSSI Description

The EQADC SSI Control Register (EQADC_SSICR) configures the SSI sub-block. Table 578. field description Table 579. Current CFIFO Status Reserved 0b01 Not applicable. CFIFO Mode is modified to continuous-scan edge or level trigger mode.

Figure 591. EQADC SSI Control Register (EQADC_SSICR) Table 580. EQADC SSI Control Register (EQADC_SSICR) field description according to how MDT is set. calculated by dividing the system clock by the clock divide factor specified with the BR field. Section , EQADC Module Configuration Register (EQADC_MCR). Table 581. Minimum Delay After Transmission (t MDT) Time

received from the external device. Table 582. System Clock Divide Factor for Baud Clock

If the system clock is divided by a odd number then t he serial clock will have a duty cycle different from

Figure 592. EQADC SSI Receive Data Register (EQADC_SSIRDR) to control which time slots the EQADC selects to obtain pre-defined external time bases. Table 583. EQADC SSI Receive Data Register (EQADC_SSIRDR) field description whenever the EQADC_SSIRDR register is read. Writes have no effect. 0 Receive data is not valid. will not be copied into EQADC_SSIRDR.

Figure 593. EQADC STAC Client Configuration Register (EQADC_REDLCCR) Table 584. EQADC STAC Client Configuration Register (EQADC_REDLCCR) field description the STAC server. It is possible to have up to 16 different sources to be selected. Table 585. STAC Bus Timebase Bits Selection

Figure 594. EQADC CFIFO0 Registers (EQADC_CF0Rw) (w=0, .., 3) Table 586. SRVm valid values

Figure 599. EQADC CFIFO5 Registers (EQADC_CF5Rw) (w=0, .., 3) EQADC Command FIFOs, for more information on CFIFOs. These registers are read only. Data written to these registers is ignored. Table 587. EQADC CFIFOx Registers (EQADC_CFxRw) (w=0, .., 3) field description smallest memory mapped address.

Figure 600. EQADC CFIFO0 Extension Regi sters (EQADC_CF0ERw) (w=0, .., 3) Table 588. field description smallest memory mapped address.

25.5.3 On-Chip ADC Registers

of the memory map is undefined.

Registers ADC0_CR, ADC0_GCCR, ADC0_OCCR, ADC0_AGR1/2 and ADC0_AOR1/2 can only be accessed by configuration commands sent to CBuffer0.
Registers ADC1_CR, ADC1_GCCR, ADC1_OCCR, ADC1_AGR1/2 and ADC1_AOR1/2 can only be accessed by configuration commands sent to CBuffer1.
Registers ADC_TSCR, ADC_TBCR, ADC_ACR1-8 and ADC_PUDCR0-7 can be accessed by configuration commands sent to CBuffer0 or to CBuffer1. A data write to any of these registers through a configuration command sent to CBuffer0 will write the same memory location as when writing to it through a configuration command sent to CBuffer1. Note: Simultaneous write accesses from CBuffer0 and CBuffer1 to any of the shared registers are not allowed.

Table 589. EQADC RFIFOx Registers (EQADC_RFxRw) (w=0, .., 3) field description smallest memory mapped address. Table 590. On-Chip ADC Memory Map

Table 590. On-Chip ADC Memory Map (continued)

Command Format for the Standard Configuration.

Throughout the table, ADC0/ADC1 indicates that if the command is stored in CBuffer0 it will be applied to ADC0 and if in

Figure 607. ADC0/1 Control Registers (ADC0/1_CR)

0 ADC0

0 ADC1

Table 591. ADC0/1 Control Registers (ADC0/1_CR) field description Disabling the On-chip ADCs, for details. 1 ADC is enabled and ready to perform A/D conversions. 0 ADC is disabled. Clock supply to ADC0/1 is stopped. until it reaches its low phase. number of the external channel being converted for selecting external multiplexer inputs. ADC0/1_EMUX affects channel number decoding. 1 External multiplexer enabled; external multiplexer channels can be selected. 0 External multiplexer disabled; no external multiplexer channels can be selected. Both ADC0/1_EMUX bits must not be asserted at the same time. can be set during the same write cycle used to set ADC0/1_EN. the alternate conversion command is used. clock cycles, therefore this field is used to select a clock duty higher or lower than 50%. 1 clock high pulse is longer 1 clock cycle than low portion. 0 clock low interval is longer 1 clock cycle than high pulse.

Low Power Active mode and system clock is around 1 MHz. 1 System clock is selected - maximum frequency. 0 Prescaler output clock is selected. The ADC0/1_CLK_SEL bits must only be wr itten when the ADC0/1_EN bit is negated. ADC0/1_CLK_SEL can be set during the same write cycle used to set ADC0/1_EN. can be configured during the same write cycle used to set ADC0/1_EN. Table 591. ADC0/1 Control Registers (ADC0/1_CR) field description (continued) Table 592. Timebase Selection 00 Selects internally generated time base as time stamp.

01 Selects imported time base 1 indicated by SRV1 bit field

10 Selects imported time base 2 indicated by SRV2 bit field

11 Reserved

Table 593. System Clock Divide Factor for ADC Clock

Note: Simultaneous write accesses from CBuffer0 and CBuffer1 to ADC_TSCR are not allowed. Table 593. System Clock Divide Factor for ADC Clock (continued)

disabled. If TBC_CLK_PS is set to disabled it can be changed to any other value. Figure 608. ADC Time Stamp Control Register (ADC_TSCR) Table 594. ADC Time Stamp Control Register (ADC_TSCR) field description Table 595. Clock Divide Factor for Time Stamp

Note: Simultaneous write accesses from CBuffer0 and CBuffer1 to ADC_TBCR are not allowed. ADC Calibration Feature, for details about the calibration scheme used in the EQADC. Figure 609. ADC Time Base Counter Register (ADC_TBCR) Table 596. ADC Time Base Counter Register (ADC_TBCR) field description and wraps when reaching 0xFFFF.

calibration scheme used in the EQADC. Figure 610. ADC0/1 Gain Calibration Constant Registers (ADC0/1_GCCR) Table 597. ADC0/1 Gain Calibration Constant Registers (ADC0/1_GCCR) field description GCC0/1 contains the gain calibration constant used to fine-tune ADC0/1 conversion results. Section , MAC Unit and Operand Data Format.

format) is written to an address in the range 0x08-0x0F of the on-chip ADC memory map. Refer to Section , Conversion Command Format for Alternate Configurations. Figure 611. ADC0/1 Offset Calibration Constant Registers (ADC0/1_OCCR) Table 598. ADC0/1 Offset Calibration Consta nt Registers (ADC0/1_OCCR) field description results. Negative values should be expressed using the two’s complement representation.

Figure 612. Alternate Configuration 1-8 Control Registers (ADC_ACR1-8) Table 599. Alternate Configuration 1-8 Cont rol Registers (ADC_ACR1-8) field description STAC bus master but not putting the result in the result queue.

1 No result transfer to result queue / Decimation Filter PRE-FILL mode

0 Result transfer to result queue / Decimation Filter in filtering mode

(see Section , Conversion Command Format for Alternate Configurations).

1 Right justified signed

0 Right justified unsigned

The RESSEL[0:1] field selects the resolution of the ADC according to Table 601.

when the alternate conversion command is used. iterations in the gain stage. The gain is selected according to Table 603. Table 599. Alternate Configuration 1-8 Contro l Registers (ADC_ACR1-8) field description Table 600. Conversion Destination Selection 0000 The conversion result is sent to the RFIFOs. The data format is specified by the FFMT bit in the conversion command. format is specified by the FMTA bit in the Alternate Configuration Control Register. format is specified by the FMTA bit in the Alternate Configuration Control Register. format is specified by the FMTA bit in the Alternate Configuration Control Register. Table 601. Resolution Selection

00 ADC set to 12-bits resolution

01 ADC set to 10-bits resolution

10 ADC set to 8-bits resolution

Table 602. Timebase Selection

00 Selects internally generated time base as time

01 Selects imported time base 1 indicated by SRV1 bit

field of EQADC_REDLCCR register.

10 Selects imported time base 2 indicated by SRV2 bit

field of EQADC_REDLCCR register.

format) is written to an address in the range 0x08-0x09 of the on-chip ADC memory map. Table 603. ADC Pre-Gain Control Bits

00 X1 gain

01 X2 gain

10 X4 gain

Figure 613. ADC0/1 Alternate x Gain Register (ADC0/1_AGRx, x=1-2) Figure 614. ADC0/1 Alternate x Gain Regist er (ADC0/1_AGRx, x=1-2) field description 15-bit unsigned fixed point numbers expressed in the GCC_INT.GCC_FRAC binary format. refer to Section , MAC Unit and Operand Data Format.

25.6 Functional Description

25.6.1 Overview

access to all the analog channels. Table 605. ADC Pull Up/Down Control Register x (ADC_PUDCRx, x=0-7) field description resistors, according to Table 607. Table 606. Channel x Pull Up/Down Field Definition

00 No Pull resistors connected to the channel

01 Pull Up resistor connected to the channel

10 Pull Down resistor connected to the channel

11 Pull Up and Pull Down resistors connected to the channel

Table 607. Pull Up/Down Strength Field Definition

This set is not av ailable for CH_PULL_x = 11.

structure to be used and because queues are the only ty pe of data structure supported by the DMAC.

RM0029 Enhanced Queued Analog-to-Digital Converter (EQADC) Doc ID 15177 Rev 8 1093/1740 hardware triggers from other blocks or external pins to initiate transfers of commands from the multiple CFIFOs to the on-chip ADCs or to the external device. CFIFOs can be configured in single-scan or continuous-scan mode. When a CFIFO is configured in single-scan mode, the EQADC scans the CQueue one time. The EQADC stops transferring commands from the triggered CFIFO after detecting the EOQ bit set in the last transfer. After an EOQ bit is detected, software involvement is required to rearm the CFIFO so that it can detect new trigger events. When a CFIFO is configured for continuous-scan mode, the whole CQueue is scanned multiple times. After the detection of an asserted EOQ bit in the last command transfer, command transfers can continue or not depending on the mode of operation of the CFIFO. CFIFO0 has a special configuration option to allow a repetitive sequence of conversion commands (streaming mode) with high priority characteristics (abort operation) or not. This feature is useful with the immediate conversion command feature that allows the immediate execution of a conversion command or a sequence of commands with critical timing even with the possibility of abortion of some current ADC conversion in progress. The aborted command is stored and executed again as soon as the critical timing commands have been finished. The multiple Result FIFOs (RFIFOs) can receive data from the on-chip ADCs, from an off- chip external device or from an on-chip companion module. Data from the on-chip ADCs can be routed to the side interface, processed by the on-chip companion module and then routed back through the side interface to the RFIFOs.

25.6.2 Data Flow in EQADC

Overview and Basic Terminology Figure 617 shows how command data flows inside the EQADC system. A Command Message is the predefined format at which command data is stored on the CQueues. A Command message has 32 bits and is composed of two parts: a CFIFO header and an ADC Command. Command messages are moved from the CQueues to the CFIFOs by the host CPU or by the DMAC as they respond to interrupt and DMA requests generated by the EQADC. The EQADC generates these requests whenever a CFIFO is not full. The FIFO Control Unit will only transfer to a CBuffer the ADC command part of the Command Message. Information in the CFIFO header together with the upper bit of the ADC command is used by the FIFO Control Unit to arbitrate which triggered CFIFO will be transferring the next command. Since command transfer through the serial interface can take significantly more time than a parallel transfer to the on-chip ADCs, command transfers for on-chip ADCs occur concurrently with the ones through the serial interface.

Figure 617. Command Flow during EQADC operation exception of unsolicited data like null messages for example. CFIFO0 when configured to operate in streaming mode for popping. Message format. Figure 618 shows how result data flows inside the EQADC system.

an RFIFO has at least one entry. results to and from an RFIFO can occur simultaneously. Figure 618. Result Flow during EQADC operation architecture of the external device are also described.

Enhanced Queued Analog-to-Digital Converter (EQADC) RM0029 1096/1740 Doc ID 15177 Rev 8 EQADC SSI Protocol Support The external device must fully support the EQADC SSI protocol as specified in Section 25.6.9, EQADC Synchronous Serial Interface (SSI) Sub-Block.. Support for the abort feature is optional. When aborts are not supported, all command messages bound for an external CBuffer must have the ABORT_ST bit negated - see Section , Command Message Format for External Device Operation. Number of Command Buffers and Result Buffers The external device should have a minimum of one and a maximum of two Command Buffers (CBuffer) to store command data sent from the EQADC. Even if more than two CBuffers are implemented in the external device, they are not recognized by the EQADC as valid destinations for commands. In this document, these two CBuffers will be referred as CBuffer2 and CBuffer3. The external device decides to which external CBuffer a command should go by decoding the upper bit (BN bit) of the ADC command - see Section , Command Message Format for External Device Operation. An external device that only implements one CBuffer can ignore the BN bit. The limit of two CBuffers does not limit the number of RBuffers in the slave device. Command Execution and Result Return Commands sent to an specific CBuffer should be executed in that order they were received. Results generated by the execution of commands of a CBuffer should be returned in the order the CBuffer received these commands. Null and Result Messages The external device must be capable of correctly processing null messages as specified in the Section , EQADC null message send format register (EQADC_NMSFR). In case no valid result data is available to be sent to the EQADC, the external device must send data in the format specified in Section , Null Message Format for External Device Operation. In case valid result data is available to sent to the EQADC, the external device must send data in the format specified in Section , Result Message Format for External Device Operation. The BUSY0/1 fields of all messages sent from the external device to the EQADC must be correctly encoded according to the latest information on the fullness state of the CBuffers. For example, if the CBuffer2 is empty before the end of the current serial transmission and if at the end of this transmission the external device receives a command to CBuffer2, then the BUSY0 field, that is to be sent to the EQADC on the next serial transmission, should be encoded assuming that CBuffer2 has one entry. Message Format in EQADC This section explains the command and result message formats used for on-chip ADC operation and for external device operation. A Command Message is the predefined format at which command data is stored on the CQueues. A Command message has 32 bits and is composed of two parts: a CFIFO header and an ADC Command. The size of the CFIFO header is fixed to 6 bits, and it works as inputs to the FIFO Control Unit. It controls when a CQueue ends, when it pauses, if commands are sent to internal or external buffers, and if it can abort a serial data

Table 608. Conversion Command Format for the Standard Configuration field description transferred command - see Section , CFIFO Scan Trigger Modes, for details. 0 Not the last entry of the CQueue. are set, but the CFIFO status changes as if only the EOQ bit were asserted. is configured to single or continuous-scan edge trigger mode. 1 Enter WAITING FOR TRIGGER state after transfer of the current Command Message.

0 Do not enter WAITING FOR TRIGGER state after transfer of the current Command

are set, but the CFIFO status changes as if only the EOQ bit were asserted. and the intermediary REP bits are ignored. 1 Indicates the start point of the sub-queue to be repeated. 0 It is not the start point of a loop. A negated EB bit indicates that the command is sent to an internal CBuffer. Command is sent to an internal buffer. or external depending on the EB bit setting. CAL indicates if the returning conversion result must be calibrated. Calibrate conversion result. Do not calibrate conversion result.

MESSAGE_TAG of the incoming data. These two bits determine the duration of the sampling time in ADC clock cycles. conversion result is sent to the RFIFOs. See Section , Time Stamp Feature, for details. Return conversion time stamp after the conversion result. Return conversion result only. for On-Chip ADC Operation, for details. converted. See Section , Channel assignment, for details. Table 609. MESSAGE_TAG Description

These messages are treated as null messages. Therefor e, they must obey the format for incoming null

configuration commands by a negated R/W bit. Table 611. Conversion Command Format for Al ternate Configurations field description companion module addressed by the DEST field. register is used to define the conversion result format. signal is sent through the side interface if DEST is not equal to 0b000. flush signal is sent through the side interface if DEST is not equal to 0b000. valid data for the filtering algorithm. This field selects one of the alternate configurations according to Table 612. Table 612. Alternate Configuration Selection

Figure 622. Read Configuration Command Format for On-Chip ADC Operation Table 614. Read Configuration Command Format for On-Chip ADC Operation field description Refer to Section , Conversion Command Format for the Standard Configuration.. An asserted R/W bit indicates a read configuration command. Refer to Section , Conversion Command Format for the Standard Configuration.. or read. Only half-word addresses can be used.

Table 615. ADC Result Format (Right Justified Signed) field description representation is used to express negative values. Table 616. Correspondence between analog voltages and digital values (1), (2)

1 LSB

formats used for external device operation. Figure 625 describes the command message format for external device operation. command message is transferred to the external device.

The two’s complement representation is used to express negative values.
Assuming uncalibrated conversion results.

Figure 625. Command Message Format for External Device Operation Table 617. Command Message Format for External Device Operation field description Refer to Section , Conversion Command Format for the Standard Configuration. ABORT_ST indicates whether an on-going serial transmission should be aborted or not. aborts see Section , CFIFO Common Prioritization and Command Transfer. Abort current serial transmission. Do not abort current serial transmission. An asserted EB bit indicates that the command is sent to an external CBuffer. Command is sent to an external CBuffer. Refer to Section , Conversion Command Format for the Standard Configuration. interfacing with the on-chip ADCs.

Figure 626. Result Message Format for External Device Operation Table 618. Result Message Format for External Device Operation field description Refer to Section , Conversion Command Format for the Standard Configuration. indicate the number of entries in a external CBuffer for example.

RM0029 Enhanced Queued Analog-to-Digital Converter (EQADC) Doc ID 15177 Rev 8 1111/1740

25.6.3 Command/Result Queues

The Command and Result queues (CQueues and RQueues) are actually part of the EQADC system although they are not hardware implemented inside the EQADC. Each CQueue entry is a 32-bit Command Message.The last entry of a CQueue has the EOQ bit asserted to indicate that it is the last entry of the CQueue. RQueue entry is a 16-bit data. See Section , Overview and Basic Terminology, for a description of the message formats and their flow in EQADC. Refer to Section 25.7.5, CQueue and RQueues usage, for examples of how CQueues and RQueues can be used.

25.6.4 EQADC Command FIFOs

There are six prioritized CFIFOs located in the EQADC. Each CFIFO is four entries deep, except CFIFO0 that can be configured to eight entries deep in extended mode, and each CFIFO entry is 32 bits long. A CFIFO serves as a temporary storage location for the command messages stored on the CQueues in the system memory. When a CFIFO is not full, the EQADC sets the corresponding CFFF bit in Section , EQADC FIFO and Interrupt Status Registers (EQADC_FISR). If CFFE is asserted in Section , EQADC Interrupt and DMA Control Registers (EQADC_IDCR), the EQADC generates requests for more commands from a CQueue. An interrupt request, served by the host CPU, is generated when CFFS is negated, and a DMA request, served by the DMAC, is generated when CFFS is asserted. The host CPU or the DMAC respond to these requests by writing to the Section , EQADC CFIFO Push Registers (EQADC_CFPR), to fill the CFIFO. Note: The DMAC should be configured to write a single command (32-bit data) to the CFIFO push registers for every asserted DMA request it acknowledges. Refer to Section 25.7.2, EQADC/DMAC Interface, for DMAC configuration guidelines. Note: CFIFO0 can be configured to work in an alternative way called Streaming Mode. This mode is very different from the mode described here because it maintains some stored commands to execute them several times in sequence and in loop. Note: Only whole words must be written to EQADC_CFPR. Writing half-words or bytes to EQADC_CFPR will still push the whole 32-bit CF_PUSH field into the corresponding CFIFO, but undefined data will fill the areas of CF_PUSH that were not specifically designated as target locations for writing. Figure 629 describes the important components in the CFIFO. Each CFIFO is implemented as a circular set of registers to avoid the need to move all entries at each push/pop operation. The Push Next Data Pointer points to the next available CFIFO location for storing data written into the EQADC Command FIFO Push Register. The Transfer Next Data Pointer points to the next entry to be removed from CFIFOx when it completes a transfer. The CFIFO Transfer Counter Control Logic counts the number of entries in the CFIFO and generates DMA or interrupt requests to fill the CFIFO. TNXTPTR in Section , EQADC FIFO and Interrupt Status Registers (EQADC_FISR), indicates the index of the entry that is currently being addressed by the Transfer Next Data Pointer, and CFCTR, in the same register, provides the number of entries stored in the CFIFO. Using TNXTPTR and CFCTR, the absolute addresses for the entries indicated by the Transfer Next Data Pointer and by the Push Next Data Pointer can be calculated using the following formulas:

Enhanced Queued Analog-to-Digital Converter (EQADC) RM0029 1112/1740 Doc ID 15177 Rev 8 Transfer Next Data Pointer Address = CFIFOx_BASE_ADDRESS + TNXTPTRx*4 Push Next Data Pointer Address = CFIFOx_BASE_ADDRESS + [(TNXTPTRx+CFCTRx) mod CFIFO_DEPTH] * 4 where

a mod b returns the remainder of the division of a by b.
CFIFOx_BASE_ADDRESS is the smallest memory mapped address allocated to a CFIFOx entry.
CFIFO_DEPTH is the number of entries contained in a CFIFO - four in this implementation. When CFSx in Section , EQADC CFIFO Status Register (EQADC_CFSR), is TRIGGERED, the EQADC generates the proper control signals for the transfer of the entry pointed by Transfer Next Data Pointer. CFUFx in Section , EQADC FIFO and Interrupt Status Registers (EQADC_FISR), is set when a CFIFOx underflow event occurs. A CFIFO underflow occurs when the CFIFO is in TRIGGERED state and it becomes empty. No commands will be transferred from an underflowing CFIFO, nor will command transfers from lower priority CFIFOs be blocked. CFIFOx is empty when the Transfer Next Data Pointer x equals the Push Next Data Pointer x and CFCTRx is zero. CFIFOx is full when the Transfer Next Data Pointer x equals the Push Next Data Pointer x and CFCTRx is not zero. When the EQADC completes the transfer of an entry from CFIFOx: the transferred entry is popped from CFIFOx, the CFIFO counter CFCTR in the Section , EQADC FIFO and Interrupt Status Registers (EQADC_FISR), is decremented by one, and Transfer Next Data Pointer x is incremented by one (or wrapped around) to point to the next entry in the CFIFO. The transfer of entries bound for the on-chip ADCs is considered completed when they are stored in the appropriate CBuffer. The transfer of entries bound for the external device is considered completed when the serial transmission of the entry is completed. When the EQADC_CFPRx is written and CFIFOx is not full, the CFIFO counter CFCTRx is incremented by one, and the Push Next Data Pointer x then is incremented by one (or wrapped around) to point to the next entry in the CFIFO. When the EQADC_CFPRx is written but CFIFOx is full, the EQADC will not increment the counter value and will not overwrite any entry in CFIFOx.

Figure 629. CFIFO Diagram

Figure 630. CFIFO Entry Pointer Example

RM0029 Enhanced Queued Analog-to-Digital Converter (EQADC) Doc ID 15177 Rev 8 1115/1740 command queue, where to start a repeating sequence. This location is stored in an additional pointer ‘Repeat Pointer’. Streaming mode requires 2 trigger inputs. The standard queue 0 trigger, in this mode referred to as Repeat Trigger and a new internal trigger input to the eQADC called Advance Trigger (no filter available). CFIFO0 is configured to operate in streaming mode by setting the bit STRME0 as described in Section , EQADC CFIFO Control Registers (EQADC_CFCR). CFIFO0 is eight entries deep in extended mode by setting the bit CFEEE0 in the same EQADC_CFCR register, and each entry is 32 bits long. This CFIFO0 serves as a local storage of a few commands that need to be executed sequentially as in a FIFO but can contain sub-queues that need to be executed several times. The CFFF0 bit in Section , EQADC FIFO and Interrupt Status Registers (EQADC_FISR), is used to assure the CFIFO0 is not full and command messages are stored from address 0x0 to 0x7. CFIFO0 Operation in Streaming Mode In Streaming mode, the CFIFO0 is filled with CCWs using the DMA exactly the same as existing modes. The CFIFO executes commands as per the existing modes until it executes a Conversion Command Word with the Repeat bit set. When this CCW is executed, the Repeat Pointer is set to point to this FIFO location and from this CCW onwards, CFIFO0 entries is not invalidated, that is, the Repeat Pointer prevents this and subsequent entries from being overwritten. The queue continues to execute until a CCW with an asserted Pause bit is completed; then the queue stops and enters the Pause state, waiting for a trigger. This is the same as normal behavior. The Pause state is exited in one of two ways: Repeat Trigger or Repeat Trigger with Advance Trigger. The Repeat trigger with no Advance trigger causes the Transfer Next Data Pointer to be loaded with the Repeat Pointer location and CCWs are then executed from the Repeat Pointer back to the Pause bit. This means that a section of the CFIFO0 is repeatedly executed every time a Repeat Trigger occurs. The Repeat trigger with the Advance trigger pending causes all CCWs from the Repeat pointer to the Pause bit to be invalidated and the CCW after the pause bit to be executed. This is achieved by invalidating the Repeat Pointer. The effect is that the queue advances beyond the repeating section of the CFIFO0 to execute new CCWs. Note that the Advance trigger can occur at any time between Repeat triggers, but is only actioned when the next Repeat trigger occurs. Prior to that it is pending. In a typical application, the queue is made of some configuration commands to the ADC (to flush the decimator or turn on pad pull-up/down) followed by a repeating section of ADC conversions on one or more ADC channels from one or more sensors; followed by a few more configuration commands; then more repeating ADC conversions, until the entire engine cycle is complete; when the queue is restarted. The mechanism described permits any number of repeating sub-queues to be loaded and executed, interspersed by configuration commands. Triggering Description in Streaming Mode The additional trigger signal ATRIG0 is detected by a separate circuit that is configured by the bit field AMODE0 as described in Section , EQADC CFIFO Control Registers (EQADC_CFCR). This trigger signal is used as an advance control of pop pointer of CFIFO0. In addition, it is used as the enable trigger for the Repeat trigger. This means it is

Enhanced Queued Analog-to-Digital Converter (EQADC) RM0029 1116/1740 Doc ID 15177 Rev 8 necessary to have an Advance trigger first to enable the detection of the Repeat trigger. When the Repeat trigger is enabled, the Advance trigger is used to advance the pop pointer beyond some loop sub-queue. And it is to disable the Repeat trigger by executing a Pause without a previous REP bit. A typical sequence of events is presented below to describe the relationship between the triggers. In Streaming mode, the CFIFO0 is filled with CCWs using the DMA as usual. The two triggers are configured to positive edge and single scan mode. The SSS bit is asserted and the trigger detector of the Repeat trigger is disabled in the start of the queue. It is necessary to receive the first Advance trigger to enable the detector of the other trigger. This enable is useful when the Repeat trigger is received all the time and the trigger signal can be disabled when it is not desired. The Advance trigger is received and detected and the Repeat trigger detector is enabled. No commands are executed until now. The Repeat trigger is detected and the commands start to be executed in sequence. If a REP bit is decoded with the PAUSE bit, the loop is configured and the CFIFO0 commands stop to be executed. The next Repeat trigger is waited to start the execution of the loop again, or the Advance trigger can be detected to break the loop and advance the queue in CFIFO0. The Repeat trigger detector remains enabled. If the Advance trigger is received and the next command in the CFIFO0 does not present the REP bit set, this means the CFIFO0 is not starting a new loop. In this case (outside a loop) if a PAUSE bit is decoded, this means to disable the Repeat trigger detector. This can be useful if the Repeat trigger is not required for some interval of time. The Repeat trigger detector is enabled again when the next Advance trigger event is detected. CFIFO0 Diagram Description in Streaming Mode Figure 631 represents the main components of CFIFO0 in streaming mode. However, some signals behave in a different way from the common operation. The Push Next Data Pointer points to the next available CFIFO0 location for storing data written into the EQADC Command FIFO Push Register. The Transfer Next Data Pointer points to the next entry to be transferred to Cbuffer. The Repeat Pointer points to the first entry of the repeating sub- queue. TNXTPTR in Section , EQADC FIFO and Interrupt Status Registers (EQADC_FISR), indicates the index of the entry that is currently being addressed by the Transfer Next Data Pointer, and CFCTR, in the same register, provides the number of entries stored in the CFIFO. When CFS0 in Section , EQADC CFIFO Status Register (EQADC_CFSR), is TRIGGERED, the EQADC generates the proper control signals for the transfer of the entry pointed by Transfer Next Data Pointer. CFUF0 in Section , EQADC FIFO and Interrupt Status Registers (EQADC_FISR), is set when CFIFO0 underflow event occurs. A CFIFO underflow occurs when the CFIFO is in TRIGGERED state and it is empty. No commands will be transferred from an underflowing CFIFO, nor will command transfers from lower priority CFIFOs be blocked. CFIFO0 is empty when CFCTR0 is zero. CFIFO0 is full when (CFCTR0 mod CFIFO_DEPTH) is zero but CFCTR0 is not zero. When the EQADC completes the transfer of an entry from CFIFO0 in loop condition: the transferred entry is not popped from CFIFO0, the CFIFO counter CFCTR in the Section , EQADC FIFO and Interrupt Status Registers (EQADC_FISR), is not decremented by one, and Transfer Next Data Pointer 0 is incremented by one (or wrapped around) to point to the next entry in the CFIFO0.

Figure 631. CFIFO0 in Streaming Mode Diagram

Figure 632. CFIFO0 in Streaming Mode Entry Pointer Example

Figure 633. CFIFO0 in Streaming Mode Entry Pointer Example (Cont.) Repeat with Advance trigger occurs, and there is no command in the CFIFO0 to execute. case the Pause bit takes precedence and a Repeat trigger causes the jump back described. A Repeat trigger with Advance trigger causes the queue to end.

Enhanced Queued Analog-to-Digital Converter (EQADC) RM0029 1120/1740 Doc ID 15177 Rev 8 destination (CBuffer), the higher priority CFIFO is always served first. A TRIGGERED, not- underflowing CFIFO will start the transfer of its commands when:

its commands are bound for an internal CBuffer that is not full, and it is the highest priority triggered CFIFO sending commands to that CBuffer.
its commands are bound for an external CBuffer that is not full, and it is the highest priority triggered CFIFO sending commands to an external CBuffer that is not full. A triggered CFIFO with commands bound for a certain CBuffer consecutively transfers its commands to it until:
an asserted End Of Queue bit is reached, or;
an asserted Pause bit is encountered and the CFIFO is configured for edge trigger mode, or;
CFIFO is configured for level trigger mode and a closed gate is detected, or;
in case its commands are bound for an internal CBuffer, a higher priority CFIFO that uses the same internal CBuffer is triggered, or;
in case its commands are bound for an external CBuffer, a higher priority CFIFO that uses an external CBuffer is triggered. The prioritization logic of the EQADC, depicted in Figure 634, is composed of three independent sub-blocks: one prioritizing CFIFOs with commands bound for CBuffer0, another prioritizing CFIFOs with commands for CBuffer1, and a last one prioritizing CFIFOs with commands for CBuffer2 and CBuffer3 which reside inside the external device. As these three sub-blocks are independent, simultaneous writes to CBuffer0, to CBuffer1, and to EQADC SSI transmit buffer are allowed. The hardware identifies the destination of a command by decoding the EB and BN bits in the command message - see Section , Message Format in EQADC, for details. Note: Triggered but empty CFIFOs, underflowing CFIFOs, are not considered for prioritization. No data from these CFIFOs will be sent to the CBuffers and nor will they stop lower priority CFIFOs from transferring commands. Whenever CBuffer0 is able to receive new entries, the prioritization sub-block selects the highest-priority triggered CFIFO with a command bound for CBuffer0, and writes its command into the buffer. In case CBuffer0 is able to receive new entries but there are no triggered CFIFOs with commands bound for it, nothing is written to the buffer. The sub-block prioritizing CBuffer1 usage behaves in the same way. When the EQADC SSI is enabled and ready to start serial transmissions, the sub-block prioritizing EQADC SSI usage writes command or null messages into the EQADC SSI transmit buffer, data written to the EQADC SSI transmit buffer is subsequently transmitted to the external device through the EQADC SSI link. The sub-block writes commands to the EQADC SSI transmit buffer when there are triggered CFIFOs with commands bound for not- full external CBuffers. The command written to the transmit buffer belongs to the highest priority CFIFO sending commands to a external CBuffer that is not full. This implies that a lower priority CFIFO can have its commands sent if a higher priority CFIFO cannot send its commands due to a full CBuffer. The sub-block writes null messages to the EQADC SSI transmit buffer when there are no triggered CFIFOs with commands bound for external CBuffers, or when there are triggered CFIFOs with commands bound for external CBuffers but the external CBuffers are full. The EQADC monitors the status of the external CBuffers by decoding the BUSY fields of the incoming result messages from the external device - see Section , Result Message Format for External Device Operation, for details.

RM0029 Enhanced Queued Analog-to-Digital Converter (EQADC) Doc ID 15177 Rev 8 1121/1740 Note: When a lower priority CFIFO is served first because a higher priority CFIFO cannot send its commands due to a full external CBuffer, there is a possibility that command transfers from the lower priority CFIFO will be interrupted and the CFIFO will become non-coherent, when the higher priority CFIFO again becomes ready to send commands. If the lower priority CFIFO becomes non-coherent or not depends on the rate at which commands on the external CBuffers are executed, on the rate at which commands are transmitted to the external CBuffers, and on the depth of those buffers. Once a serial transmission is started, the sub-block monitors triggered CFIFOs and manages the abort of serial transmissions. In case a null message is being transmitted, the serial transmission is aborted when all following conditions are met:

A not-underflowing CFIFO in TRIGGERED state has commands bound for an external CBuffer that is not full, and it is the highest priority CFIFO sending commands to an external CBuffer that is not full.
the ABORT_ST bit of the command to be transmitted is asserted.
the 26th bit of currently transmitting null message has not being shifted out. The command from the CFIFO is then written into EQADC SSI transmit buffer, allowing for a new serial transmission to initiate. In case a command is being transmitted, the serial transmission is aborted when all following conditions are met:
CFIFO0 is in TRIGGERED state, is not underflowing, and its current command is bound for an external CBuffer that is not full.
the ABORT_ST bit of the command to be transmitted is asserted.
the 26th bit of currently transmitting command has not being shifted out. The command from CFIFO0 is then written into EQADC SSI transmit buffer, allowing for a new serial transmission to initiate. Note: The aborted command is not popped from the preempted CFIFO and will be retransmitted as soon as its CFIFO becomes the highest priority CFIFO sending commands to an external CBuffer that is not full. After a serial transmission is completed, the EQADC prioritizes the CFIFOs and schedules a command or a null message to be sent in the next serial transmission. After the data for the next transmission has been defined and scheduled, the EQADC can, under certain conditions, stretch the SDS negation time in order to allow the schedule of new data for that transmission. This occurs when the EQADC acknowledges that the status of a higher- priority CFIFO changed to TRIGGERED and attempts to schedule that CFIFO command before SDS is asserted. Only commands of CFIFOs that have the ABORT_ST bit asserted can be scheduled in this manner. Under such conditions: 1. a CFIFO0 command is scheduled for the next transmission independently of the type of data that was previously scheduled. The time during which SDS is negated is stretched in order to allow the EQADC to load the CFIFO0 command and start its transmission. 2. CFIFO1-5 commands are only scheduled for the next transmission if the previously scheduled data was a null message. The time during which SDS is negated is stretched in order to allow the EQADC to load that command and start its transmission. However, if the previously scheduled data was a command, no rescheduling occurs and the next transmission starts without delays. If a CFIFO becomes TRIGGERED while SDS is negated, but the EQADC only attempts to reschedule that CFIFO command after SDS is asserted, then the current transmission is aborted depending on if the conditions for that are met or not.

Figure 634. CFIFO Prioritization Logic can be enabled to abort conversions. be configured to permit immediate conversion commands from CFIFO0 with abort function. established the normal process of prioritization of commands from CFIFOs.

signal is not filtered and the logic after the filter receives a copy of this input trigger signal. signals must be held at a logic level to be recognized as valid. All ETRIG signals are filtered. A counter for each queue trigger is implemented to detect a transition between logic levels. logic level to be valid and passes that new logic level to the rest of the EQADC. to the system clock and filtered, a trigger event is checked against the CFIFO trigger mode. CFIFO status. Refer to Figure 635 for an example. Figure 635. ETRIG Event Propagation Example

1: This delay is about 2 clocks when the filter bypass control is asserted.

Enhanced Queued Analog-to-Digital Converter (EQADC) RM0029 1124/1740 Doc ID 15177 Rev 8 detection of an asserted EOQ bit in the last transfer. Refer to Section , Message Format in EQADC, for details about command formats. CFIFOs can be configured in single-scan or continuous-scan mode. When a CFIFO is configured in single-scan mode, the EQADC scans the CQueue one time. The EQADC stops future command transfers from the triggered CFIFO after detecting the EOQ bit set in the last transfer. After a EOQ bit is detected, software involvement is required to rearm the CFIFO so that it can detect new trigger events. When a CFIFO is configured for continuous-scan mode, no software involvement is necessary to rearm the CFIFO to detect new trigger events after an asserted EOQ is detected. In continuous-scan mode the whole CQueue is scanned multiple times. The EQADC also supports different triggering mechanisms for each scan mode. The EQADC will not transfer commands from a CFIFO until the CFIFO is triggered. The combination of scan modes and triggering mechanisms allows the support of different requirements for scanning input channels. The scan mode and trigger mechanism are configured by programming the MODEx field in Section , EQADC CFIFO Control Registers (EQADC_CFCR). Enabled CFIFOs can be triggered by software or external trigger events. The elapsed time from detecting a trigger to transferring a command is a function of clock frequency, trigger synchronization, trigger filtering or not, programmable trigger events, command transfer, CFIFO prioritization, CBuffer availability, etc. Fast and predictable transfers can be achieved by ensuring that the CFIFO is not underflowing and that the target CBuffer is not full when the CFIFO is triggered. Disabled Mode The MODEx field in Section , EQADC CFIFO Control Registers (EQADC_CFCR), for all of the CFIFOs can be changed from any other mode to disabled at any time. No trigger event can initiate command transfers from an CFIFO which has its MODE field programmed to disabled. Note: If MODEx is not disabled, it must not be changed to any other mode besides disabled. If MODEx is disabled and the CFIFO status is IDLE, MODEx can be changed to any other mode. If MODEx is changed to disabled:

The CFIFO execution status will change to IDLE. The timing of this change depends on whether a command is being transferred or not: – When no command transfer is in progress, the EQADC switches the CFIFO to IDLE status immediately. – When a command transfer to an on-chip CBuffer is in progress, the EQADC will complete the transfer, update TC_CF, and switch CFIFO status to IDLE. Command transfers to the internal CBuffers are considered completed when a command is written to the buffers. – When a command transfer to an external CBuffer is in progress, the EQADC will abort the transfer and switch CFIFO status to IDLE. If the EQADC cannot abort the transfer, that is when the 26th bit of the serial message has being already shifted out, the EQADC will complete the transfer, update TC_CF and then switch CFIFO status to IDLE.

RM0029 Enhanced Queued Analog-to-Digital Converter (EQADC) Doc ID 15177 Rev 8 1125/1740

The CFIFOs are not invalidated automatically. The CFIFO still can be invalidated by writing a “1” to the CFINVx bit in Section , EQADC CFIFO Control Registers (EQADC_CFCR). Certify that CFS has changed to IDLE before setting CFINVx.
The TC_CFx value also is not reset automatically, but it can be reset by writing “0” to it.
The SSS bit in Section , EQADC FIFO and Interrupt Status Registers (EQADC_FISR), is negated. The SSS bit can be set even if a “1” is written to the SSE bit in Section , EQADC CFIFO Control Registers (EQADC_CFCR), in the same write that the MODEx field is changed to a value other than disabled.
The trigger detection hardware is reset. If MODEx is changed from disabled to an edge trigger mode, a new edge, matching that edge trigger mode, is needed to trigger the command transfers from the CFIFO. Note: CFIFO fill requests, which generated when CFFF is asserted, are not automatically halted when MODEx is changed to disabled. CFIFO fill requests will still be generated until CFFE is cleared in Section , EQADC Interrupt and DMA Control Registers (EQADC_IDCR). Single-Scan Mode In single-scan mode, a single pass through a sequence of command messages in a CQueue is performed. In single-scan software trigger mode, the CFIFO is triggered by an asserted Single-Scan Status bit (SSS) in Section , EQADC FIFO and Interrupt Status Registers (EQADC_FISR). The SSS bit is set by writing “1” to the Single-Scan Enable bit (SSE) in Section , EQADC CFIFO Control Registers (EQADC_CFCR). In single-scan edge- or level-trigger mode, the respective triggers are only detected when the SSS bit is asserted. When the SSS bit is negated, all trigger events for that CFIFO are ignored. Writing a “1” to the SSE bit can be done during the same write cycle that the CFIFO operation mode is configured. Only the EQADC can clear the SSS bit. Once SSS is asserted, it remains asserted until the EQADC completes the CQueue scan, or the CFIFO operation mode (MODEx) in Section , EQADC CFIFO Control Registers (EQADC_CFCR), is changed to disabled. The SSSx bit will be negated while MODEx is disabled. Single-Scan Software Trigger When single-scan software trigger mode is selected, the CFIFO is triggered by an asserted SSS bit. The SSS bit is asserted by writing “1” to the SSE bit. Writing to SSE while SSS is already asserted will not have any effect on the state of the SSS bit, nor will it cause a trigger overrun event. The CFIFO commands start to be transferred when the CFIFO becomes the highest priority CFIFO using a not-full on-chip CBuffer or an not-full external CBuffer. When an asserted EOQ bit is encountered, the EQADC will clear the SSS bit. Setting the SSS bit is required for the EQADC to start the next scan of the queue. The Pause bit has no effect in single-scan software trigger mode. Single-Scan Edge Trigger When SSS is asserted and an edge triggered mode is selected for a CFIFO, an appropriate edge on the associated trigger signal causes the CFIFO to become TRIGGERED. For example, if rising-edge trigger mode is selected, the CFIFO becomes TRIGGERED when a rising edge is sensed on the trigger signal. The CFIFO commands start to be transferred

Enhanced Queued Analog-to-Digital Converter (EQADC) RM0029 1126/1740 Doc ID 15177 Rev 8 when the CFIFO becomes the highest priority CFIFO using a not-full on-chip CBuffer or an not-full external CBuffer. When an asserted EOQ bit is encountered, the EQADC clears SSS and stops command transfers from the CFIFO. An asserted SSS bit and a subsequent edge trigger event are required to start the next scan for the CFIFO. When an asserted Pause bit is encountered, the EQADC stops command transfers from the CFIFO, but SSS remains set. Another edge trigger event is required for command transfers to continue. A trigger overrun happens when the CFIFO is in TRIGGERED state and an edge trigger event is detected. Single-Scan Level Trigger When SSS is asserted and a level gated trigger mode is selected, the input level on the associated trigger signal puts the CFIFO in TRIGGERED state. When the CFIFO is asserted to high-level gated trigger, a high level signal opens the gate, and a low level closes the gate. When the CFIFO is set to low-level gated trigger mode, a low level signal opens the gate, and a high level closes the gate. If the corresponding level is already present, setting the SSS bit triggers the CFIFO. The CFIFO commands start to be transferred when the CFIFO becomes the highest priority CFIFO using a not-full on-chip CBuffer or a not -full external CBuffer. The EQADC clears the SSS bit and stops transferring commands from a TRIGGERED CFIFO when an asserted EOQ bit is encountered or when CFIFO status changes from TRIGGERED due to the detection of a closed gate. If a closed gate is detected while no command transfers are taking place and the CFIFO status is TRIGGERED, the CFIFO status is immediately changed to IDLE, the SSS bit is negated, and the PF flag is asserted. If a closed gate is detected during the serial transmission of a command to the external device, it will have no effect on the CFIFO status until the transmission completes. Once the transmission is completed, the TC_CF counter is updated, the SSS bit is negated, the PF flag is asserted, and the CFIFO status is changed to IDLE. An asserted SSS bit and a level trigger are required to restart the CFIFO. Command transfers will restart from the point they have stopped. If the gate closes and opens during the same serial transmission of a command to the external device, it will have no effect on the CFIFO status or on the PF flag, but the TORF flag will become asserted as was exemplified in Figure 637. Therefore, closing the gate for a period less than a serial transmission time interval does not guarantee that the closure will affect command transfers from a CFIFO. The Pause bit has no effect in single-scan level-trigger mode. Continuous-Scan Mode In continuous-scan mode, multiple passes looping through a sequence of command messages in a CQueue are executed. When a CFIFO is programmed for a continuous-scan mode, the SSE bit in the Section , EQADC CFIFO Control Registers (EQADC_CFCR), does not have any effect. Continuous-Scan Software Trigger When a CFIFO is programmed to continuous-scan software trigger mode, the CFIFO is triggered immediately. The CFIFO commands start to be transferred when the CFIFO becomes the highest priority CFIFO using a not-full on-chip CBuffer or an not-full external CBuffer. When a CFIFO is programmed to run in continuous-scan software trigger mode, the EQADC will not halt transfers from the CFIFO until the CFIFO operation mode is modified to disabled or a higher priority CFIFO preempts it. Although command transfers will

RM0029 Enhanced Queued Analog-to-Digital Converter (EQADC) Doc ID 15177 Rev 8 1127/1740 not stop upon detection of an asserted EOQ bit, the EOQF is set and, if enabled, an EOQ interrupt request is generated. The Pause bit has no effect in continuous-scan software trigger mode. Continuous-Scan Edge Trigger When rising, falling, or either edge trigger mode is selected for a CFIFO, a corresponding edge on the associated ETRIG signal places the CFIFO in TRIGGERED state. The CFIFO commands start to be transferred when the CFIFO becomes the highest priority CFIFO using a not-full on-chip CBuffer or an not-full external CBuffer When an EOQ or a Pause is encountered, the EQADC halts command transfers from the CFIFO and, if enabled, the appropriate interrupt requests are generated. Another edge trigger event is required to resume command transfers but no software involvement is required to rearm the CFIFO in order to detect such event. A trigger overrun happens when the CFIFO is already in TRIGGERED state and a new edge trigger event is detected. Continuous-Scan Level Trigger When high or low level gated trigger mode is selected, the input level on the associated trigger signal places the CFIFO in TRIGGERED state. When high-level gated trigger is selected, a high-level signal opens the gate, and a low level closes the gate. The CFIFO commands start to be transferred when the CFIFO becomes the highest priority CFIFO using a not-full on-chip CBuffer or an not-full external CBuffer. Although command transfers will not stop upon detection of an asserted EOQ bit at the end of a command transfer, the EOQF is asserted and, if enabled, an EOQ interrupt request is generated. The EQADC stops transferring commands from a TRIGGERED CFIFO when CFIFO status changes from TRIGGERED due to the detection of a closed gate. If a closed gate is detected while no command transfers are taking place and the CFIFO status is TRIGGERED, the CFIFO status is immediately changed to WAITING FOR TRIGGER and the PF flag is asserted. If a closed gate is detected during the serial transmission of a command to the external device, it will have no effect on the CFIFO status until the transmission completes. Once the transmission is completed, the TC_CF counter is updated, the PF flag is asserted, and the CFIFO status is changed to WAITING FOR TRIGGER. Command transfers will restart as the gate opens. If the gate closes and opens during the same serial transmission of a command to the external device, it will have no effect on the CFIFO status or on the PF flag, but the TORF flag will become asserted as was exemplified in Figure 637. Therefore, closing the gate for a period less than a serial transmission time interval does not guarantee that the closure will affect command transfers from a CFIFO. The Pause bit has no effect in continuous-scan level-trigger mode. CFIFO Scan Trigger Mode Start/Stop Summary Table 621 summarizes the start and stop conditions of command transfers from CFIFOs for all of the single-scan and continuous-scan trigger modes.

CFIFO Status Snapshot Registers (EQADC_CFSSR). Table 621. CFIFO Scan Trigger Mode - Command Transfer Start/Stop Summary Software Don’t Care Asserted SSS bit. Yes No None.

Refer to Section , CQueue Completion Status , for more information on EOQ.
Refer to Section , Pause Status, for more information on Pause.
EQADC always stops command transfers from a CFIFO when the CFIFO operation mode is disabled.
EQADC always stops command transfers from a CFIFO when a higher priority CFIFO is triggered. Refer to

CFIFO Common Prioritization and Command Transfer , for information on CFIFO priority.

If a closed gate is detected while no command transfers are ta king place, it will have immediate effect on the CFIFO status.

CFIFO status until the transmission completes.

Figure 636. State Machine of CFIFO Status Table 622. Command FIFO Status Switching Condition trigger mode and SSS is negated.

2 WAITING FOR

3 TRIGGERED (0b11) — CFIFO Mode is programmed to continuous-scan software

IDLE (0b00) — CFIFO Mode is modified to disabled mode.

5 WAITING FOR

TRIGGER (0b10) — No trigger occurred.

6 TRIGGERED (0b11)

trigger mode and SSS bit is asserted.

the on-chip ADCs is considered completed when they are stored in the appropriate CBuffer. serial transmission of the entry is completed. EQADC will generate an End of Queue interrupt request. required to rearm the CFIFO so that it can detect new trigger events.

8 WAITING FOR

CFIFO Mode is not modified to disabled.

9 TRIGGERED (0b11) — No event to switch to IDLE or WAITING FOR TRIGGER

Table 622. Command FIFO Status Switching Condition (continued)

RM0029 Enhanced Queued Analog-to-Digital Converter (EQADC) Doc ID 15177 Rev 8 1131/1740 Note: An asserted EOQFx only implies that EQADC has finished transferring a command with an asserted EOQ bit from CFIFOx. It does not imply that result data for the current command and for all previously transferred commands has been returned to the appropriate RFIFO. Pause Status In edge trigger mode, when the EQADC completes the transfer of a CFIFO entry with an asserted Pause bit, the EQADC will stop future command transfers from the CFIFO and set the corresponding Pause Flag (PF) in Section , EQADC FIFO and Interrupt Status Registers (EQADC_FISR). Refer to Section , Message Format in EQADC, for information on command message formats. The EQADC ignores the Pause bit in command messages in any software and external level trigger mode. The EQADC sets the PF flag upon detection of an asserted Pause bit only in single or continuous-scan edge trigger mode. When the PF flag is set for a CFIFO in single-scan edge trigger mode, the SSS bit will not be cleared in Section , EQADC FIFO and Interrupt Status Registers (EQADC_FISR). In level trigger mode, the definition of the PF flag has been redefined. In level trigger mode, when CFIFOx is in TRIGGERED status, PFx is set when CFIFO status changes from TRIGGERED due to detection of a closed gate. The pause flag interrupt routine can be used to verify if the a complete scan of the CQueue was performed. If a closed gate is detected while no command transfers are taking place, it will have immediate effect on the CFIFO status. If a closed gate is detected during the serial transmission of a command to the external device, it will have no effect on the CFIFO status until the transmission completes. When PIE in Section , EQADC CFIFO Control Registers (EQADC_CFCR), and PF are asserted, the EQADC will generate a Pause interrupt request. Note: In edge trigger mode, an asserted PFx only implies that the EQADC finished transferring a command with an asserted PAUSE bit from CFIFOx. It does not imply that result data for the current command and for all previously transferred commands has been returned to the appropriate RFIFO. Note: In software or level trigger mode, when the EQADC completes the transfer of an entry from CFIFOx with an asserted Pause bit, PFx will not be set and command transfers will continues without pausing. Trigger Overrun Status When a CFIFO is configured for edge- or level-trigger mode and is in TRIGGERED state, an additional trigger occurring for the same CFIFO results in a trigger overrun. The trigger overrun bit for the corresponding CFIFO will be set (TORFx = 1) in Section , EQADC FIFO and Interrupt Status Registers (EQADC_FISR). When TORIE in Section , EQADC CFIFO Control Registers (EQADC_CFCR), and TORF are asserted, the EQADC generates a trigger overrun interrupt request. For CFIFOs configured for level-trigger mode, a trigger overrun event is only detected when the gate closes and opens during a single serial command transmission as shown in Figure 637.

Figure 638. Command Sequence Examples formed by commands 0, 1, 2, 3, and the other by commands 4, 5, 6. the EQADC would check for non-coherency of three command sequences. sequences, all containing a single command, but NCF would never get set.

Enhanced Queued Analog-to-Digital Converter (EQADC) RM0029 1134/1740 Doc ID 15177 Rev 8 A command sequence is non-coherent when, after transferring the first command of a sequence from a CFIFO to a CBuffer, it cannot successively send all the other commands of the sequence before any of the following conditions are true:

The CFIFO through which commands are being transferred is preempted by a higher priority CFIFO which sends commands to the same CBuffer. The NCF flag becomes asserted immediately after the first command transfer from the preempting CFIFO, that is the higher priority CFIFO, to the CBuffer in use is completed. See Figure 640.
The external CBuffer in use becomes empty(ba). This case happens when different CFIFOs attempt to use different external CBuffers and the higher priority CFIFO bars the lower priority one from sending new commands to its CBuffer - see Figure 641. An external CBuffer is considered empty when the corresponding BUSY field in the last result message received from external device is encoded as “Send available commands - CBuffer is empty”. Refer to Section , Result Message Format for External Device Operation. The NCF flag becomes asserted immediately after the EQADC detects that the external CBuffer in use becomes empty. Note: After the transfer of a command sequence to an external CBuffer starts, the EQADC ignores, for non-coherency detection purposes, the BUSY fields captured at the end of the first serial transmission. Thereafter, all BUSY fields captured at the end of consecutive serial transmissions are used to check the fullness of that external CBuffer. This is done because the EQADC only updates its external CBuffers status record when it receives a serial message, resulting that the record kept by the EQADC is always outdated by, at least, the length of one serial transmission. This prevents a CFIFO from immediately becoming non- coherent when it starts transferring commands to an empty external CBuffer. Refer to Figure 639 for an example. ba. Only the fullness of external CBuffers is monitored bec ause the fill rate for internal CBuffers is many times faster than the drain rate, and each has a dedicated priority engine.

Figure 639. External CBuffer Status Detection at Command Sequence Transfer Start conditions below becomes true.

The command sequence became non-coherent.
The CFIFO status changed from TRIGGERED.
The CFIFO underflowed. Note: The NCF flag still becomes asserted if an external CBuffer empty event is detected at the same time the EQADC stops checking for the coherency of a command sequence. Once command transfers restart/continue, the non-coherency hardware will behave as if the command sequence started from that point. Figure 642 depicts how the non-coherency hardware will behave when a non-coherency event is detected. Note: If MODEx is changed to disabled while a CFIFO is transferring commands, the NCF flag for that CFIFO will not become asserted. Note: When the EQADC enters debug or stop mode while a command sequence is being executed, the NCF will become asserted if an empty external CBuffer is detected after debug/stop mode is exited. Null Message 1st Command 2nd Command 3rd Command SDS Serial Data (a) (b) (c) External CBuffer Status Capture Point at EQADC CBuffer Status at External Device CBuffer Status as Captured by the EQADC Used for NCF detection on the EQADC? (a) EMPTY EMPTY Don’t care (b) 1 ENTRY EMPTY No (c) 2 ENTRY 1 ENTRY Yes Transmitted Assumptions: 1. The CFIFO starts sending commands to an empty external CBuffer when triggered. 2. Execution of a command on the external device takes longer than the time to complete three serial transmissions. External CBuffer status starts to be monitored here. Transfer of command sequence starts

Figure 640. Non-Coherency Event when Different CFIFOs use the same CBuffer CFIFO5 becomes non-coherent.

Figure 641. Non-Coherency Event when Different CFIFOs are using Different External CBuffers of first command of CFIFO5 is completed.

Figure 642. Non-coherency Detection when Transfers from a Command Sequence

25.6.5 EQADC Result FIFOs

EQADC Result FIFO Pop Registers (EQADC_RFPR), to retrieve data from the RFIFO. EQADC/DMAC Interface, for DMAC configuration guidelines. RFIFOx, and the RFCTRx field will be decremented by one. entries in RFIFO and generates interrupt or DMA requests to drain the RFIFO. will only check for coherency after command 4. will only check for coherency after command 11.

RM0029 Enhanced Queued Analog-to-Digital Converter (EQADC) Doc ID 15177 Rev 8 1139/1740 POPNXTPTR in Section , EQADC FIFO and Interrupt Status Registers (EQADC_FISR), indicates which entry is currently being addressed by the Pop Next Data Pointer, and RFCTR, in the same register, provides the number of entries stored in the RFIFO. Using POPNXTPTR and RFCTR, the absolute addresses for Pop Next Data Pointer and Receive Next Data Pointer can be calculated using the following formulas: Pop Next Data Pointer Address= RFIFOx_BASE_ADDRESS + POPNXTPTRx*4 Receive Next Data Pointer Address = RFIFOx_BASE_ADDRESS + [(POPNXTPTRx+RFCTRx) mod RFIFO_DEPTH] * 4 where

a mod b returns the remainder of the division of a by b.
RFIFOx_BASE_ADDRESS is the smallest memory mapped address allocated to an RFIFOx entry.
RFIFO_DEPTH is the number of entries contained in a RFIFO - four in this implementation. When a new message arrives and RFIFOx is not full, the EQADC copies its contents into the entry pointed by the Receive Next Data Pointer. The RFIFO counter RFCTRx in Section , EQADC FIFO and Interrupt Status Registers (EQADC_FISR), is incremented by one, and the Receive Next Data Pointer x is also incremented by one (or wrapped around) to point to the next empty entry in RFIFOx. However, if the RFIFOx is full, the EQADC sets the RFOF in Section , EQADC FIFO and Interrupt Status Registers (EQADC_FISR). The RFIFOx will not overwrite the older data in the RFIFO, the new data will be ignored, and the Receive Next Data Pointer x is not incremented or wrapped around. RFIFOx is full when the Receive Next Data Pointer x equals the Pop Next Data Pointer x and RFCTRx is not zero. RFIFOx is empty when the Receive Next Data Pointer x equals the Pop Next Data Pointer x and RFCTRx is zero. When the EQADC RFIFO Pop Register x is read and the RFIFOx is not empty, the RFIFO counter RFCTRx is decremented by one, and the POP Next Data Pointer is incremented by one (or wrapped around) to point to the next RFIFO entry. When the EQADC RFIFO Pop Register x is read and RFIFOx is empty, EQADC will not decrement the counter value and the POP Next Data Pointer x will not be updated. The read value will be undefined.

Figure 643. RFIFO Diagram example, RFIFOx with 16 entries is shown in sequence after popping or receiving entries.

Figure 644. RFIFO Entry Pointer Example

Enhanced Queued Analog-to-Digital Converter (EQADC) RM0029 1142/1740 Doc ID 15177 Rev 8 Distributing Result Data into RFIFOs Data to be moved into the RFIFOs can come from four sources: from ADC0, from ADC1, from the external device or from the decimation filter A or B, or reaction module through the PSI. All result data comes with a MESSAGE_TAG field and a DEST field defining what should be done with the received data. The EQADC hardware decodes the MESSAGE_TAG and DEST fields and:

stores the 16-bit data into the appropriate RFIFO if the MESSAGE_TAG indicates a valid RFIFO number, or;
sends the 16-bit data, the MESSAGE_TAG and the DEST data through the PSI to decimation filter A or B or reaction module, or;
ignores the data in case of a null or “reserved for customer use” MESSAGE_TAG. In general received data is moved into RFIFOs as they become available, while an exception happens when multiple results from different sources become available at the same time. In that case, result data from ADC0 is processed first, result data from ADC1 is only process after all ADC0 data is processed, result data from the external device is only processed after all data from ADC0/1 is processed, and finally returned data from companion module is only processed after all data from ADC0/1 and external device is processed. When time-stamped results return from the on-chip ADCs, the conversion result and the time stamp are always moved to the RFIFOs in consecutive clock cycles in order to guarantee they are always stored in consecutive RFIFO entries.

25.6.6 On-Chip ADC Configuration and Control

Enabling and Disabling the On-chip ADCs The on-chip ADCs have an enable bit (ADC0/1_EN) in the Section , , which allows the enabling of the ADCs only when necessary. When the enable bit for an ADC is negated, the clock input to that ADC is stopped. The ADCs are disabled out of reset - ADC0/1_EN bits are negated - to allow for their safe configuration. The ADC must only be configured when its enable bit is negated. Once the enable bit of an ADC is asserted, clock input to is started. Note: Conversion commands sent to the CBuffer of a disabled ADC are ignored by the ADC control hardware. Note: A 8ms wait time from VDDA power up to enabling ADC is required to pre-charge the external 100nf capacitor on REFBYPC pin. This time must be guaranteed by crystal startup time plus reset duration or user. Note: Due to legacy reasons, the EQADC will always wait 120 ADC clocks before issuing the first conversion command following the enabling of one of on-chip ADCs, or the exiting of stop mode. There are two independent counters checking for this delay: one clocked by ADC0_CLK and another by ADC1_CLK. Conversion commands can start to be executed whenever one of these counters completes counting 120 ADC clocks. ADC Clock and Conversion Speed The clock input to the ADCs is defined by setting the ADC0/1_ODD_PS, the ADC0/1_CLK_SEL and the ADC0/1_CLK_PS fields in the Section , ADC0/1 Control Registers (ADC0_CR and ADC1_CR). When the ADC0/1_CLK_SEL is set, the ADC clock frequency is the same as the system clock, but it has the inverted phase. When it is clear, the ADC0/1_ODD_PS and the ADC0/1_CLK_PS fields select the clock divide factor by

120 MHz system clock and the corresponding conversion speeds for all possible ADC clock

would result in a ADC clock frequency higher than the maximum one supported by the ADC. ADC clock frequency must not exceed 15 MHz. Table 623. ADC Clock Configuration Example (System Clock Frequency=120 MHz)

Table 623. ADC Clock Configuration Example (S ystem Clock Frequency=120 MHz) (continued)

on the eQADC if this delay is not implemented in software. the executed conversion command. details in Section , STAC Client Submodule (REDLC)) or by the internal time base counter. (ADC_TBCR), with a write configuration command.

Figure 647. Timing Diagram for the STAC Bus and Every time the selected time slot changes, the STAC client submodule output is updated. timebase to be used internal to the EQADC. gain 2 or gain 4, respectively. smaller. In this ADC, it is verified that there is 1 ADC clock cycle for each bit of resolution. as illustrated in Figure 650. The SRV bits are set to capture TS[01].

Maximum of 16 time slots (TSn)NOTES:
The SRV bits capture TS[01]

RM0029 Enhanced Queued Analog-to-Digital Converter (EQADC) Doc ID 15177 Rev 8 1149/1740 ADC Calibration Feature Overview There are three sets of calibration coefficients for each ADC. Each set is composed by a gain factor and an offset factor: GCCn/OCCn, ALTGCCn1/ALTGCCn1, and ALTGCCn2/ALTGCCn2, where n is the ADC number 0 or 1. The pair GCCn/OCCn is selected when it is used the normal configuration or the alternate configurations 3 to 8. The pair ALTGCCn1/ALTGCCn1 is used only when the alternate configuration 1 is selected. And the pair ALTGCCn2/ALTGCCn2 is for the alternate configuration 2. The description below is for a generic pair of gain/offset GCC/OCC. The EQADC provides a calibration scheme to remove the effects of gain and offset errors from the results generated by the on-chip ADCs. Only results generated by the on-chip ADCs are calibrated. The results generated by ADCs on the external device are directly sent to RFIFOs unchanged. The main component of calibration hardware is a Multiply-and- Accumulate (MAC) unit, one per on-chip ADC, that is used to calculate the following transfer function which relates a calibrated result to a raw, uncalibrated one. CAL_RES = GCC * RAW_RES + OCC+2; where:

CAL_RES is the calibrated result corresponding the input voltage Vi.
GCC is the gain calibration constant.
RAW_RES is the raw, uncalibrated result with resolution adjustment corresponding to an specific input voltage Vi.
OCC is the offset calibration constant.
The addition of two reduces the maximum quantization error of the ADC. See Section , Quantization Error Reduction During Calibration. Calibration constants GCC and OCC are determined by taking two samples of known reference voltages and using these samples to calculate the values for the constants. For details and an example about how to calculate the calibration constants and use them in result calibration refer to Section 25.7.6, ADC Result Calibration. Once calculated, GCC is stored in the Section , ADC0/1 Gain Calibration Constant Registers (ADC0_GCCR and ADC1_GCCR), and OCC in Section , ADC0/1 Offset Calibration Constant Registers (ADC0_OCCR and ADC1_OCCR), from where their values are fed to the MAC unit. The alternate gain values are stored in Section , ADC0/1 Alternate Gain Registers (ADC0_AGR1-2 and ADC1_AGR1-2), and the alternate offset values in Section , ADC0/1 Alternate Offset Register (ADC0_AOR1-2 and ADC1_AOR1-2). Since the analog characteristics of each on-chip ADCs differs, each ADC has an independent pair of calibration constants. A conversion result is calibrated according to the status of CAL bit in the command that initiated the conversion. If the CAL bit is asserted, the EQADC will automatically calculate the calibrated result before sending the result to the appropriate RFIFO or companion module. If the CAL bit is negated, the result is not calibrated, it bypasses the calibration hardware, and is directly sent to the appropriate RFIFO or companion module. MAC Unit and Operand Data Format The MAC unit diagram is shown in Figure 648. Each on-chip ADC has a separate MAC unit to fine-tune its conversion results. The description below considers the general calibration constant registers but it is the same for the alternate calibration constants.

Figure 650 shows the basic logic blocks involved in the ADC Control and how they interact. the calibration processing to use the calibration coefficients always with the same format. conversion results also take place inside this sub-block. Result Format and Calibration Sub-Block as time stamp information. Table 625. Binary and Decimal Representations of the Gain Constant

Enhanced Queued Analog-to-Digital Converter (EQADC) RM0029 1152/1740 Doc ID 15177 Rev 8 shift, ENTRY0 is always empty and ready to receive a new command. Execution of configuration commands only start when they reach ENTRY1. Consecutive conversion commands are pipelined and their execution can start while in ENTRY0. This is explained below. AD conversion accuracy can be affected by the settling time of the input channel multiplexers. Some time is required for the channel multiplexers internal capacitances to settle after the channel number is changed. If the time prior to sampling is not long enough to absorb this settling, then the settling time will take from ADC sampling time which may result in inaccurate sampling and ultimately compromise conversion result accuracy - see Figure 651 (a). This could be avoided by switching the multiplexers in preparation for the next command’s sampling during the AD conversion phase of the current command as showed in Figure 651 (b). In EQADC, this is done in the following way; when a conversion command is in buffer ENTRY1 and another conversion command is identified in ENTRY0, then the channel number of ENTRY0 is sent to the MUX Control Logic some cycles before the sampling phase of the command in ENTRY0 starts. In this way, sampling for the next command can promptly start after the current conversion finishes because the internal capacitance of the multiplexers will be settled by that time, allowing for more accurate sampling. This is specially important for applications that require high conversion speeds, that is with the ADC running at maximum clock frequency and with the analog input voltage sampling time set to a minimum (2 ADC clock cycles), when the short sampling time does not allow the multiplexers to completely settle. The second advantage of pipelining conversion commands is to provide precise conversion intervals, which means the time intervals between two consecutive conversions are the same. This is important for any digital signal process application. When the on-chip ADC abort feature is enabled, ADC Commands from CFIFO0 should be considered immediately, even stopping the execution of some command that is already in ENTRY1. When the abort request is sent to the ADC, the already stored commands in the CBuffers are copied in a temporary set of registers. The first ADC command from CFIFO0 is sent after the abort acknowledge indication from ADC. The process is the same as usual until the transfer of the last command from CFIFO0. Then the temporarily stored commands that were postponed by the abortion are recovered and they are pipelined for execution. After the last command from this temporary memory is transferred, the next commands are pipelined from the CFIFOs.

Figure 650. On-Chip ADC Control Scheme

Figure 651. Overlapping Consecutive Conversion Commands

25.6.7 Internal/External Multiplexing

each conversion command must be set to avoid channel selection conflicts. Table 628 for the channel numbers used to select differential conversions. inaccurate conversion results. more time for MUX internal capacitance to settle.

single-ended channels and 4 differential pairs are shared between the two ADCs. Table 626. ADC0/1_EMUX Bits Combinations

11 R e s e r v e d (1)

ADC0_EMUX and ADC1_EMUX must not be asserted at the same time.

Table 627. Non-multiplexed Channel Assignments (1)

explanation about how external multiplexing can be achieved.

The two on-chip ADCs can access the same analog input pi ns but simultaneous conversions are not allowed. Also, when
50% x VREF = 50% ref = (VRH / VRL)/2, but this only applies before calibration. After calibration, the 50% reference point

Table 627. Non-multiplexed Channel Assignments (1) (continued)

Table 628. Multiplexed Channel Assignments (1)

The two on-chip ADCs can access the same analog input pins but simultaneous conversions are not allowed. Also, when
Old version has reserved values for channel numbers 8 to 11 when EMUX =1. Therefore, now the behavior is different

because it is converted the signal at AN8 to AN11, respectively.

50% x VREF = 50% ref = (VRH / VRL)/2, but this only applies before calibration. After calibration, the 50% reference point

Section 25.7.6, ADC Result Calibration . Table 628. Multiplexed Channel Assignments (1) (continued)

ADC0/1_EMUX bit asserted at a time. creates the MA output signals from CHANNEL_NUMBER field of a Command Message. channels appear to the conversion queues as directly connected signals. Table 629. Encoding of MA Pins

‘0’ means pin is driven LOW and ‘1’ that pin is driven HIGH.

Figure 652. Example of External Multiplexing sharing of ADC inputs and mux outputs.

25.6.8 EQADC DMA/Interrupt request

Table 631 describes a list of methods to generate DMA requests in the EQADC. Table 630. EQADC FIFO Interrupt Summary (1) NCFx = 1 Clear NCFx bit by writing a “1” to the bit. RFOFx = 1 Clear RFOFx bit by writing a “1” to the bit. CFUFx = 1 Clear CFUFx bit by writing a “1” to the bit. Clear RFDFx bit by writing a “1” to the bit. Clear CFFFx bit by writing a “1” to the bit. EOQFx = 1 Clear EOQFx bit by writing a “1” to the bit. PFx =1 Clear PFx bit by writing a “1” to the bit. TORFx =1 Clear TORFx bit by writing a “1” to the bit.

For details refer to Section , EQADC FIFO and Interrupt Status Registers (EQADC_FISR) , and Section , EQADC Interrupt

and DMA Control Registers (EQADC_IDCR) .

Apart from generating an independent interrupt request for when a RFIFO Overflow Interrupt, a CFIFO Underflow Interrupt,

requests from ALL CFIFOs are ORed. Refer to Figure 653 for details. Table 631. EQADC FIFO DMA Summary (1) becomes empty. Writing “1” to the RFDFx bit is not allowed. becomes full. Writing “1” to the CFFFx bit is not allowed.

For details refer to Section , EQADC FIFO and Interrupt Status Registers (EQADC_FISR) , and Section , EQADC Interrupt

and DMA Control Registers (EQADC_IDCR) .

Figure 653. EQADC DMA and Interrupt Requests

25.6.9 EQADC Synchronous Serial Interface (SSI) Sub-Block

Figure 654. EQADC Synchronous Serial Interface Block Diagram

Free running Clock (FCK)
Serial Data Select (SDS)
Serial Data In (SDI)
Serial Data Out (SDO) The FCK clock signal times the shifting and sampling of the two serial data signals and it is free running between transmissions, allowing it to be used as the clock for the external device. The SDS signal will be asserted to indicate the start of a transmission, and negated to indicate the end or the abort of a transmission. SDI is the master serial data input and SDO the master serial data output. The EQADC SSI sub-block is enabled by setting the ESSIE field in the Section , EQADC Module Configuration Register (EQADC_MCR). When enabled, the EQADC SSI can be optionally capable of starting serial transmissions. When serial transmissions are disabled (ESSIE set to 0b10), no data will be transmitted to the external device but FCK will be free- running. This operation mode permits the control of the timing of the first serial transmission, and can be used to avoid the transmission of data to an unstable external device, for example, a device that is not fully reset. This mode of operation is specially important for the reset procedure of an external device that uses the FCK as its main clock. Master Slave In Out Pad Interface SDS FCK SDO SDI EQADC SSI Control Register FCK Clock System Transmit Shift Register EQADC SSI Control Logic Receive Shift Register BR CFIFO Data RFIFO Data EQADC FIFO Control Unit Control MDT Clock Divide by: 2, 3, 4, .. , 15, 16, 17 Baud Clock Generator Slave Bus interface

RM0029 Enhanced Queued Analog-to-Digital Converter (EQADC) Doc ID 15177 Rev 8 1165/1740 two consecutive serial transmissions, time during which SDS is negated. When ready to start of the next transmission, the slave must drive the MSB bit of the message on every positive edge of FCK regardless of the state of the SDS signal. On the next positive edge, the second bit of the message is conditionally driven according to if an asserted SDS was detected by the slave on the preceding FCK negative edge. This is an important requisite since the SDS and the FCK are not synchronous. The SDS signal is not generated by FCK, rather both are generated by the system clock, so that it is not guaranteed that FCK edges will precede SDS ones. While SDS is negated, the slave continuously drives its MSB bit on every positive edge of FCK until it detects an asserted SDS on the immediately next FCK negative edge. See Figure 657 for three situations showing how the slave should behave according to when SDS is asserted. Note: On the master, the FCK is not used as a clock. Although, the EQADC SSI behavior is described in terms of the FCK positive and negative edges, all EQADC SSI related signals (SDI, SDS, SDO, and FCK) are synchronized by the system clock on the master side. There are no restrictions regarding the use of the FCK as a clock on the slave device. Abort Feature The master indicates it is aborting the current transfer by negating SDS before the whole data frame has being shifted out, that is the 26th bit of data being transferred has not being shifted out. The EQADC ignores the incompletely received message. The EQADC resends the aborted message whenever the corresponding CFIFO becomes again the highest priority CFIFO with commands bound for not-full external CBuffer. Refer to Section , CFIFO Common Prioritization and Command Transfer, for more information on aborts and CFIFO priority. Baud clock generation As shown in Figure 654, the baud clock generator divides the system clock to produce the baud clock. The BR field in Section , EQADC SSI Control Register (EQADC_SSICR), selects the system clock divide factor as in Table 582. (bc) bc. Maximum FCK frequency is highly dependable on track delays, master pad delays, and slave pad delays. BaudClockFrequency SystemClockFrequency MHz()

Figure 656. Synchronous Serial Interface Protocol Timing

Figure 657. Slave Driving the MSB and Consecutive Bits in a Data Transmission SDS is asserted after positive edge of FCK.

25.6.10 EQADC Parallel Side Interface (PSI) Sub-Block

Figure 658. EQADC Parallel Side Interface Block Diagram

Figure 659. PSI Input and Output Data Buses Content Table 632. CTRL[0:1] field description put the filter em normal mode instead of prefill mode. returning back to the EQADC without any modification.

Enhanced Queued Analog-to-Digital Converter (EQADC) RM0029 1170/1740 Doc ID 15177 Rev 8 MESSAGE_TAG[0:3] — Message tag bits field This field indicates the RFIFO destination associated with the ADC_CONV_RESULT sample. This value is stored by the companion module and is used to address the destination RFIFO register when a RESULT_DATA is generated due to that ADC_CONV_RESULT sample. TAG[0:3] — Companion module tag bits This bit field is used to address the appropriate destination RFIFO in the EQADC for the accompanying RESULT_DATA bits. In eQADC application, this is used to address the appropriate RFIFO in the eQADC block. In this case, the possible values are only from 0000 to 0101. ADC_CONV_RESULT[0:15] — ADC Conversion Result Data This bit field is the ADC conversion result data after passing through the calibration and formatting block. RESULT_DATA[0:15] — Companion Module Result Data This bit field corresponds to the companion module data processing result to EQADC. PSI transmitter / Write section The transmission sub-block formats the data bus from RFIFO control sub-block to send to the PSI slave wdata bus. The transmission data is registered and its content is described in Section , Input / Output signals description. The transmission has higher priority than reception. This is done to avoid the use of memory to store transmission data and it is not used waiting time for transmission. The destination companion module for the transmission data is obtained by decoding the DEST[0:3] bits. The not null decimal value of DEST[0:3] is used to uniquely set the corresponding module enable signal. For example, DEST[0:3] value equal to 0xF that corresponds to the decimal value 15 is going to set only the module enable 15. All other module enable from 1 to 14 are not set. PSI Receiver / Read section The receiver sub-block receives data from some companion module using the PSI slave bus interface. The companion module sends a read request to EQADC using the DMA read request line. The PSI logic sends a read command if there is no transmission request. The received data has the structure described in item Section , Input / Output signals description.

25.6.11 Analog Sub-Block

Figure 660. RSD ADC Block Diagram times. For 10-bit and 8-bit resolution, the signal must pass 10 or 8 times through the RSD.

Figure 662. RSD Stage Transfer Function

Figure 663. RSD Adder described in Section , Alternate Configuration 1-8 Control Registers (ADC_ACR1-8).

25.7 Initialization/Application information

25.7.1 Multiple queues control setup example

device, and how to configure the CQueues and the EQADC. Table 633. Application of Each CQueue

0 Very fast burst time-

2 Injector current profiling

1 Fast hardware-

2 Fast repetitive time-

commands will be transferred through CFIFO0.

Load all required configuration commands in the RAM in such way that they form a
Select source driving EQADC hardware trigger ports (ETRIG). Before proceeding to

level before putting the CFIFOs into the WAITING FOR TRIGGER state.

3 Software-triggered

4 Repetitive angle-

5 Slow repetitive

signal with one clock width pulse is used.

Configure Section , EQADC External Trigger Digital Filter Register (EQADC_ETDFR).
Configure Section , EQADC null message send format register (EQADC_NMSFR) .
Configure Section , EQADC SSI Control Register (EQADC_SSICR), to communicate
Enable the EQADC SSI by programming the ESSIE field in the Section , EQADC

Module Configuration Register (EQADC_MCR). transmissions are not started. b) Wait until the external device becomes stable after reset. c) Write 0b11 to ESSIE field to enable the EQADC SSI to start serial transmissions.

Configure the DMAC to transfer data from CQueue0 to CFIFO0 in the EQADC.
Configure Section , EQADC Interrupt and DMA Control Registers (EQADC_IDCR) .

commands from CQueue 0 to the CFIFO0. CFIFO0 will start immediately. the commands of CQueue0 through CFIFO0.

Configure Section , EQADC CFIFO Control Registers (EQADC_CFCR).

b) Write “1” to SSE0 to assert SSS0 and trigger CFIFO0.

Since CFIFO0 is in single-scan software mode and it is also the highest priority CFIFO,
When all of the configuration commands have been transferred, CF0 in Section ,

generates a End of Queue interrupt. The initialization procedure is complete. Figure 664. Example of a CQueue Confi guring the On-Chip ADCs/External Device

RM0029 Enhanced Queued Analog-to-Digital Converter (EQADC) Doc ID 15177 Rev 8 1177/1740 to simultaneously set these bits so that in-phase ADC clocks are generated. In this example, ADC0/1_CLK are configured to the same frequency. 1. Push an ADC0_CR write configuration command in CFIFO0 that enables ADC0 (ADC0_EN=1) and that sets the ADC0_CLK_PS to an appropriate value. For example, 0x80800801. 2. Push an ADC1_CR write configuration command in CFIFO1 that enables ADC1 (ADC1_EN=1) and that sets the ADC1_CLK_PS to an appropriate value. For example, 0x82800801. 3. Configure CFIFO0 and CFIFO1 to single scan software trigger mode and simultaneously trigger them by writing 0x04100410 to the EQADC_CFCR0 register - see Section , EQADC CFIFO Control Registers (EQADC_CFCR). Configuring EQADC for applications This section provides an example based on the applications in Table 633. The example describes how to configure multiple CQueues to be used for those applications and provides a step-by-step procedure to configure the EQADC and the associated CQueue structures. In the example, the “Fast hardware-triggered CQueue”, described on the second row of Table 633, will have its commands transferred to CBuffer1; the conversion commands will be executed by ADC1. The generated results will be returned to RFIFO3 before being transferred to the RQueues in the RAM by the DMAC. Note: There is no fixed relationship between CFIFOs and RFIFOs with the same number. The results of commands being transferred through CFIFO1 can be returned to any RFIFO, regardless of its number. The destination of a result is determined by the MESSAGE_TAG field of the command that requested the result. See Section , Message Format in EQADC, for details. Step One: Setup the CQueues and RQueues. 1. Load the RAM with configuration and conversion commands. Table 634 is an example of how CQueue1 commands should be set. a) Each trigger event will cause four commands to be executed. When the EQADC detects the Pause bit asserted, it will wait for another trigger to restart transferring commands from the CFIFO. b) At the end of the CQueue, the “EOQ” bit is asserted as shown in Table 634. c) Results will be returned to RFIFO3 as specified in the MESSAGE_TAG field of commands. 2. Reserve memory space for storing results.

RAM and the CFIFOs/RFIFOs in the EQADC.

For transferring, set the source address of the DMAC to point to the start address of

to Section , EQADC CFIFO Push Registers (EQADC_CFPR).

For receiving, set the source address of the DMAC to point to EQADC_RFPR3. Refer

address of the DMAC to point to the starting address of RQueue1. Step Three: Configure the EQADC Control Registers. Table 634. Example of CQueue Commands

Fields LST, TSR, FMT, and CHANNEL_NUMBER are not showed for clarity. See Section , Conversion Command Format

for the Standard Configuration, for details.

MESSAGE_TAG field is only defined for read configuration commands.

RM0029 Enhanced Queued Analog-to-Digital Converter (EQADC) Doc ID 15177 Rev 8 1179/1740 1. Configure Section , EQADC Interrupt and DMA Control Registers (EQADC_IDCR) . a) Set EOQIE1 to enable the End of Queue Interrupt request. b) Set CFFS1 and RFDS3 to configure the EQADC to generate DMA requests to push commands into CFIFO1 and to pop result data from RFIF03. c) Set CFINV1 to invalidate the contents of CFIFO1. d) Set RFDE3 and CFFE1 to enable the EQADC to generate DMA requests. Command transfers from the RAM to the CFIFO1 will start immediately. e) Set RFOIE3 to indicate if RFIFO3 overflows. f) Set CFUIE1 to indicate if CFIFO1 underflows. 2. Configure MODE1 to continuous-scan rising edge external trigger mode in Section , EQADC CFIFO Control Registers (EQADC_CFCR). Step Four: Command transfer to ADCs and Result data reception. When an external rising edge event occurs for CFIFO1, the EQADC automatically will begin transferring commands from CFIFO1 when it becomes the highest priority CFIFO trying to send commands to CBuffer1. The received results will be placed in RFIFO3 and then moved to RQueue1 by the DMAC.

25.7.2 EQADC/DMAC Interface

This section provides an overview about the EQADC/DMAC interface and general guidelines about how the DMAC should be configured in order for it to correctly transfer data between the queues in system memory and the EQADC FIFOs. Note: Advanced DMACs provide more functionality then the ones discussed in this section. CQueue/CFIFO transfers In transfers involving CQueues and CFIFOs, the DMAC moves data from a queued source to a single destination as showed in Figure 665. The location of the data to be moved is indicated by the source address, and the final destination for that data, by the destination address. The DMAC contains a data structure containing these addresses and other parameters used in the control of data transfers. For every DMA request issued by the EQADC, the DMAC has to be configured to transfer a single command (32-bit data) from the CQueue, pointed to by the source address, to the CFIFO push register, pointed to by the destination address. After the service of a DMA request is completed, the source address has to be updated to point to the next valid command. The destination address remains unchanged. When the last command of a queue is transferred one of the following actions is recommended.

The corresponding DMA channel should be disabled. This might be desirable for CFIFOs in single scan mode.
The source address should be updated to pointed to a valid command which can be the first command in the queue that has just been transferred (cyclic queue), or the first command of any other CQueue. This is desirable for CFIFOs in continuous scan mode, and at some cases, for CFIFOs in single scan mode.

Figure 665. CQueue/CFIFO Interface

The corresponding DMA channel should be disabled.
The destination address should be updated pointed to the next location where new coming results are stored, which can be the first entry of the current RQueue (cyclic queue), or the beginning of a new RQueue. Source Address Command 1 Command 2 Command 3 Command n-1 Command n CFPRx CQueue in system memory CFIFO Push Register One command transfer per DMA request Destination Address

Figure 666. RQueue/RFIFO Interface

25.7.3 Sending immediate command setup example

Configure the Section , EQADC Interrupt and DMA Control Registers (EQADC_IDCR) .

a) Clear CFIFO Fill Enable5 (CFFE5 = 0) in EQADC_IDCR2. b) Clear CFIFO Underflow Interrupt Enable5 (CFUIE5 = 0) in EQADC_IDCR2. d) Set RFIFO Drain Enable5 (RFDE5 = 1) in EQADC_IDCR2.

Configure the Section , EQADC CFIFO Control Registers (EQADC_CFCR).

a) Write “1” to CFINV5 in EQADC_FCR2. This will invalidate the contents of CFIFO5. b) Set MODE5 to Continuous-Scan Software Trigger mode in EQADC_CFCR2.

To transfer a command, write it to EQADC CFIFO Push Register 5 (EQADC_CFPR5)
Up to four commands can be queued in CFIFO5. Check the CFCTR5 status in

EQADC_FISR5 before pushing another command to avoid overflowing the CFIFO. Refer to Section , EQADC FIFO and Interrupt Status Registers (EQADC_FISR).

When the EQADC receives a conversion result for RFIFO5, it generates an interrupt

request. RFIFO Pop Register 5 (EQADC_RFPR5) can be popped to read the result. Refer to Section , EQADC Result FIFO Pop Registers (EQADC_RFPR).

Enhanced Queued Analog-to-Digital Converter (EQADC) RM0029 1182/1740 Doc ID 15177 Rev 8

25.7.4 Modifying queues

More CQueues may be needed than the six supported by the EQADC. These additional CQueues can be supported by interrupting command transfers from a configured CFIFO, even if it is TRIGGERED and transferring, modifying the corresponding CQueue in the RAM or associating another CQueue to it, and restarting the CFIFO. More details on disabling a CFIFO are described in Section , Disabled Mode. 1. Determine the resumption conditions when later resuming the scan of the CQueue at the point before it was modified. a) Change MODEx in Section , EQADC CFIFO Control Registers (EQADC_CFCR), to Disabled. Refer to Section , Disabled Mode, for a description of what happens when MODEx is changed to Disabled. b) Poll CFSx until it becomes IDLE in Section , EQADC CFIFO Status Register (EQADC_CFSR). c) Read and save TC_CFx in Section , EQADC CFIFO Transfer Counter Registers (EQADC_CFTCR), for later resuming the scan of the queue. The TC_CFx provides the point of resumption. d) Since all result data may not have being stored in the appropriate RFIFO at the time MODEx is changed to disable, wait for all expected results to be stored in the RFIFO/RQueue before reconfiguring the DMAC to work with the modified RQueue. The number of results that must return can be estimated from the TC_CFx value obtained above. 2. Disable the DMAC from responding to the DMA request generated by CFFFx and RFDFx in Section , EQADC FIFO and Interrupt Status Registers (EQADC_FISR). 3. Write “0x0000” to the TC_CFx field. 4. Load the new configuration and conversion commands into RAM. Configure the DMAC to support the new CQueue/RQueue, but do not configure it yet to respond to DMA requests from CFIFOx/RFIFOx. 5. If necessary, modify Section , EQADC Interrupt and DMA Control Registers (EQADC_IDCR), to suit the modified CQueue. 6. Write “1” to CFINVx in Section , EQADC CFIFO Control Registers (EQADC_CFCR), to invalidate the entries of CFIFOx. Perform any other modifications to EQADC_CFCR except changing MODEx from Disabled. 7. Configure the DMAC to respond to DMA requests generated by CFFFx and RFDFx. 8. Change MODEx to the modified CFIFO operation mode. Write “1” to SSEx to trigger CFIFOx if MODEx is software trigger.

25.7.5 CQueue and RQueues usage

Figure 667 is an example of CQueue and RQueue usage. It shows the CQueue0 commands requesting results that will be stored in RQueue0 and RQueue1, and CQueue1 commands requesting results that will be stored only in RQueue1. Some Command Messages request data to be returned from the on-chip ADC/external device, but some only configure them and do not request returning data. When a CQueue contains both write and read commands like CQueue0, the CQueue and RQueue entries will not be aligned; as shown in Figure 667, the result for the second command of CQueue0 is the first entry of RQueue0. The figure also shows that CQueue and RQueue entries can also become unaligned even if all commands in a CQueue request data as CQueue1. CQueue1 entries became unaligned to RQueue1 entries because a result requested by the forth CQueue0

that several CQueues can have its results sent to a single RQueue. Figure 667. EQADC Command and Result Queues frequency, sampling time, and triggering time.

Enhanced Queued Analog-to-Digital Converter (EQADC) RM0029 1184/1740 Doc ID 15177 Rev 8

25.7.6 ADC Result Calibration

The ADC result calibration process consists of two steps: determining the gain and offset calibration constants, and calibrating the raw results generated by the on-chip ADCs by solving the following equation discussed in Section , ADC Calibration Feature. Equation 13 CAL_RES = GCC * RAW_RES + OCC+2; The calibration constants GCC and OCC can be calculated from equation Equation 13 provided that two pairs of expected (CAL_RES) and measured (RAW_RES) result values are available for two different input voltages. Most likely calibration points to be used are 25% VREF (bd) and 75% VREF since they are far apart but not too close to the end points of the full input voltage range. This allows for calculations of more representative calibration constants. The EQADC provides these voltages via channel numbers 43 and 44. The raw, uncalibrated results for these input voltages are obtained by converting these channels with conversion commands that have the CAL bit negated. The transfer equations for when sampling these reference voltages are: CAL_RES 75%VREF = GCC * RAW_RES75%VREF + OCC+2; CAL_RES25%VREF = GCC * RAW_RES25%VREF + OCC+2; Thus; Equation 14 GCC = (CAL_RES75%VREF – CAL_RES25%VREF) / (RAW_RES75%VREF – RAW_RES25%VREF); Equation 15 OCC = CAL_RES75%VREF – GCC*RAW_RES75%VREF – 2; or Equation 16 OCC = CAL_RES25%VREF – GCC*RAW_RES25%VREF – 2; After being calculated, the GCC and OCC values must be written to ADC registers: Section , ADC0/1 Gain Calibration Constant Registers (ADC0_GCCR and ADC1_GCCR), and Section , ADC0/1 Offset Calibration Constant Registers (ADC0_OCCR and ADC1_OCCR), using write configuration commands. The EQADC will automatically calibrate the results, according to equation Equation 13, of every conversion command that has its CAL bit asserted using the GCC and OCC values stored in the ADC calibration registers. Note: For accurate calibration, the 25% VREF channel must be converted using the Long Sample Time (LST) setting for either 64 or 128 ADC sample cycles in the ADC Conversion Command Message (LST = 0b10 or 0b11). MAC Configuration Procedure The following steps illustrate how to configure the calibration hardware, namely, determining the values of the gain and offset calibration constants, and the writing of these constants to the calibration registers. The procedure below should be performed for ADC0 and for ADC1. bd. VREF=VRH-VRL

Convert channel 44 with a command that has its CAL bit negated and obtain the raw,

uncalibrated result for 25%VREF (RAW_RES25%VREF).

Convert channel 43 with a command that has its CAL bit negated and obtain the raw,

uncalibrated result for 75%VREF (RAW_RES75%VREF).

Since the expected values for the conversion of these voltages are known

determined in steps 1 and 2.

Reformat GCC and OCC to the proper data formats as specified in Section , MAC Unit
Write GCC value to Section , ADC0/1 Gain Calibration Constant Registers

maximum absolute quantization error is reduced by half leading to an increase in accuracy. Table 635. Calibration example

For accurate calibration, the 25% VREF channel must be converted using the Long Sample Time (LST)

Figure 668. Quantization error reduction during calibration

25.7.7 EQADC versus QADC

QADC. Figure 670 is an overview of the EQADC system.

0 Input

Figure 669. QADC Overview

Figure 670. EQADC System Overview

A DMA or an MCU is required to move data between the EQADC’s FIFOs and Queues
A serial interface (EQADC Synchronous Serial Interface - EQADC SSI) is implemented

to transmit and receive data between the EQADC and the external device.

contents, and signals are related to QADC. Table 636. Terminology Comparison between QADC and EQADC some are configuration commands. command on CQueue x to be determined. command transfers from a CFIFO. is idle, active, paused, suspended, or trigger pending. LCFTCBz field on the EQADC_CFSSR registers. Table 637. Usage Comparison between QADC and EQADC System Queue Control Configuration Write to the QADC Control Registers. Write to the EQADC Control Registers.

Serial Interface Configuration Not Required. Write to the EQADC SSI Registers. events to start queue execution. Table 637. Usage Comparison between QADC and EQADC System (continued)

26 Decimation Filter

26.1 Information specific to this device

specifically referenced in the remainder of this chapter.

26.1.1 Device-specific features

destination for the conversion result.

26.1.2 Device-specific parameters

MDIS_DEFAULT resets MDIS bit in Decimation Filter Module Configuration Register to 0.

26.2 Introduction

26.2.1 Overview

parameters and read/write of the configuration registers. commands. The input information is decoded by the PSI RX and control logic sub-blocks. logic sub-blocks. Then the result is returned to the master block by the PSI TX sub-block. Table 638. Decimation Filter Parameters for SPC564A74xx, SPC564A80xx

26.2.2 Features

Selectable 4th order IIR filter, or an 8th order FIR filter – Input/output with 16-bit (fixed point) two’s complement signed values – Internal taps with 16-bit (feed-forward portion of first IIR) and 24-bit (feedback portion) resolutions (fixed point) for two’s complement signed value – 24-bit programmable filter coefficients (fixed point) for two’s complement signed value – MAC unit with 51-bit fixed point accumulator – Convergent rounding methodology – Two’s complement overflow or saturation selection – 58 clock cycles to process the input
Implements a local slave-bus interface to a master block (e.g. the eQADC block)
Input and output buffers with DMA capability
Slave-bus interface to device
Filter taps access for debug
Filter initialization (flush) and stabilization (prefill) commands
Timestamp support
Decimation controlled by an internal counter or from an on-chip independent trigger signal (triggered output result)
Integrator unit accumulates filter output values, signaled or absolute, with 32-bit resolution. The integrator can be controlled by software or hardware signals.
Cascade of 2 or more individual blocks to compose a more complex filter

26.2.3 Modes of operation

mode selection is summarized in Table 639. Table 639. Operation mode selection

Freeze mode can also be activated from outside the Decimation Filter, depending on the MCU, if FREN =

1194/1740 Doc ID 15177 Rev 8 Normal mode This is the default operational mode of the decimation filter block. It corresponds to the prefill/filter operation with input data supplied through the PSI slave-bus interface (i.e. its input data is the ADC conversion result), with output going to the same PSI interface. Standalone mode Standalone mode differs from normal mode because the input data is not supplied by the master block through the PSI slave-bus interface. In this case, the data is provided by the central processor using the device slave-bus interface or DMA interface signals. Once the data is filtered the decimated result is available in the Output Buffer register. The filter output is also consumed by a CPU or DMA mastering the same device slave-bus interface. This operation mode can be used to debug the filter stability or to decimate data in System RAM. PSI Input Mixed mode In this mode the input is selected from the PSI slave-bus interface, but the output is directed to the device slave-bus interface, where it can be read by the CPU or DMA. PSI Output Mixed mode This mode works inverted from the PSI Input Mixed Mode: the input is selected from the device slave-bus interface, fed either by the CPU or DMA, and the output is directed to the PSI slave-bus interface. If an eQADC is connected to the PSI interface, the output is directed to an RFIFO selected by the tag field in the DECFILTER_IB register (see Section , Decimation Filter Interface Input Buffer Register (DECFILTER_IB)). Cascade mode Cascade mode is a filter structure mode with two or more individual filter blocks connected in a chain to form a more complex filter function. The output result of the first block (head block) is connected to the input of the next block (middle or tail block) to be filtered again. More details in Section 26.5.16, Cascade mode description. Low Power mode Low power mode corresponds to the module disable mode or stop mode. In the module disable mode the PSI slave-bus line is disabled and it is not possible to enter Freeze mode. The system clock is stopped. And in stop mode, the system clock is also stopped. Freeze mode This mode is also known as debug mode. All filter action is frozen, either through software or by the hardware SoC debug request signal. If a freeze request comes when the filter is processing an input, it enters freeze mode only after the processing finishes.

26.3 External signal description

Note: The Decimation Filter does not provide metastability protection nor filtering for these signals.

26.3.1 Decimation trigger signal

This signal is used to control the output of the decimation filter, allowing decimation to be driven externally. For more details, see Section , Triggered output result description.

26.3.2 Integrator enable signal

Integrator enabling and halting.

26.3.3 Integrator halt signal

26.3.4 Integrator reset signal

26.3.5 Integrator output request signal

26.4 Memory map and register definition

26.4.1 Decimation filter device memory map

sufficient for a 4th order IIR filter implementation. Table 640. Decimation filter device memory map

Table 640. Decimation filter device memory map (continued)

26.4.2 Decimation filter register descriptions

All registers are 32-bit wide. the Decimation Filter internal logic. operation, it is advisable to set IDIS = 1 and wait for BSY = 0 beforehand.

The TAP register stores, on each filter node, the i nput sample data and, for the IIR type, the filter

Figure 672. Decimation Filter Module C onfiguration Register (DECFILTER_MCR)

Reset value is defined by the MDIS_DEFAULT parameter value.

Table 641. DECFILTER_MCR Register Field Descriptions once in disable mode. Once the module is disabled it no longer receives the system clock.

1 Low Power Mode

1 Decimation Filter Freeze mode enabled

0 Decimation Filter Freeze mode disabled

2 Reserved, should be cleared. are halted. See Section 26.5.13, Freeze mode description, for more details.

1 Decimation Filter in Freeze Mode

0 Decimation Filter in Normal Mode

Section 26.5.10, Soft-reset command description, for more details.

1 Software-Reset

Section 26.5.16, Cascade mode description. configuration change procedures .

1 Input Data Interrupt Enabled

0 Input Data Interrupt Disabled

Table 642. CASCD[1:0] – Filter Cascade mode configuration selection

00 No cascade mode (single block)

01 Cascade Mode, Head block configuration

10 Cascade Mode, Tail block configuration

11 Cascade Mode, Middle block configuration

1 Output Data Interrupt Enabled

0 Output Data Interrupt Disabled

1 Error Interrupts Enabled

0 Error Interrupts Disabled

10 Reserved, should be cleared. Filter Type Selection bits. The FTYPE[1:0] bits select the filter type according to Table 643. Bypass must not be configured in cascade mode (see field CASCD). 13 Reserved, should be cleared. algorithm according to Table 644. Table 641. DECFILTER_MCR Register Field Descriptions (continued) Table 643. FTYPE[1:0] – Filter type selection

00 Filter Bypass (1)

In Bypass configuration the filter is disabled.

01 IIR Filter - 1 x 4th order

10 FIR Filter - 1 x 8th order

Table 644. SCAL[1:0] – Filter scaling factor definition

00 Scaling Factor = 1

01 Scaling Factor = 4

10 Scaling Factor = 8

11 Scaling Factor = 16

cascade mode. See Section 26.5.16, Cascade mode description for more details.

1 Input disabled

0 Input enabled

the IDIS position (previously reserved). Saturation, for more details.

1 Enable Saturation

0 Disables Saturation

only read the output buffer by request of the decimation filter, in normal or input mixed modes. This behavior is outlined in detail in Table 645.

1 Filter input from the device slave-bus interface

0 Filter input from PSI slave-bus interface

1 Interface NOT selected by ISEL is used for output, configuring mixed mode.

0 Interface selected by ISEL is used for output, configuring normal or standalone mode

MIXM must be set to 0 (zero) when the filter is configured as cascade mode. Table 645. ISEL/MIXM definition — Read/Write from/to Input/Output buffers

Bit DSEL selects between interrupt or DMA request
Decimation filter issues a read request to the master block

1 PSI Input

0 Standalone

1 PSI Output

block that is required to generate one decimated result in the Decimation Filter output.

1 Integration ready causes an output interrupt

0 Integration ready does not cause an output interrupt. Section 26.5.14, Enhanced debug monitor description).

1 DMA requests are generated

0 Interrupt requests are generated

input buffer has data to be read by the device CPU.

1 Input Buffer Interrupt Request Enabled

0 Input Buffer Interrupt Request Disabled

device slave-bus (ISEL!= MIXM) and DMA is not selected (DSEL = 0).

1 Output Buffer Interrupt Request Enabled

0 Output Buffer Interrupt Request Disabled

The EDME bit defines the enhanced debug monitor when input selection is from PSI (ISEL = 0). generating and input interrupt or DMA request.

1 Enhanced debug monitor enabled (read requests of input data from master block enabled)

0 Enhanced debug monitor disabled

Table 646. DEC_RATE[3:0] definition

0000 No Decimation: one filter output for each sample input

see Section , Triggered output result description.

1 Output buffer update using an external signal is enabled

0 Output buffer update using an external signal is disabled

modes).TORE must not be asserted with the filter bypassed (FTYPE = 00). sampling function enabled by the TORE bit, as shown in Table 647. previous versions of the Decimation Filter. Table 647. TMODE[1:0] definition

00 Output is posted at the rising edge of the trigger signal

01 Output is posted whenever the trigger signal is a logical 0

10 Output is posted at the falling edge of the trigger signal

11 Output is posted whenever the trigger signal is a logical 1

Figure 673. Decimation Filter Status Register (DECFILTER_MSR)

Table 648. DECFILTER_MSR Register Field Descriptions asserted when the soft reset is executed.

1 Decimation Filter Busy

0 Decimation Filter Idle

1 Reserved, should be cleared. self negated, therefore it is always read as zero. is self negated, therefore it is always read as zero. 8 Reserved, should be cleared. Register. This bit is self negated, therefore it is always read as zero.

1 Clears IBIF

Register. This bit is self negated, therefore it is always read as zero. 11 Reserved, should be cleared. bit in the Status Register. This bit is self negated, therefore it is always read as zero. is self negated, therefore it is always read as zero. is self negated, therefore it is always read as zero.

Register. This bit is self negated, therefore it is always read as zero. 16–21 Reserved, should be cleared. soft reset of the decimation filter.

1 New Sample received

0 Sample not received

read / write request flag, refer to IBIF. ODFC Status bit or by a soft reset of the decimation filter.

1 New Decimated Output Sample available

0 No new Decimated Output Sample available

request flag, refer to OBIF. 24 Reserved, should be cleared. IBIC Status bit or by a soft reset of the decimation filter.

1 New Sample is requested (ISEL = 1, EDME = 0) or new sample is available in Enhanced

Debug Monitor (ISEL = 0, EDME = 1). Flag is cleared by the OBIC Status bit or by a soft reset of the decimation filter.

1 New Decimated Output available

0 No new Decimated Output available

27 Reserved, should be cleared.

1 Enhanced Debug Monitor Input Data Read Overrun occurred

0 Input Data Read Overrun did not occur in Enhanced Debug monitor

Table 648. DECFILTER_MSR Register Field Descriptions (continued)

1 Overflow occurred

0 No overflow

cleared by the OVRC Status bit or by a soft reset of the decimation filter.

1 Filter Output Overrun occurred

0 No Output Overrun

IVRC Status bit or by a soft reset of the decimation filter.

1 Input Buffer Overrun occurred

0 Input Buffer Overrun did not occur

IVR does not set due to input register writes wh en input is disabled (DECFILTER_MCR bit IDIS = 1). Figure 674. Decimation Filter Extended C onfiguration Register (DECFILTER_MXCR)

Table 649. DECFILTER_MXCR Register Field Descriptions requested (see Section , Integrator outputs). DMA requests from both of those sources is not allowed. behaves in case of an overflow. integration, therefore one must not configure SSIG = 1 and SSAT = 0. sample counter behaves in case of an overflow. 1 integrator sample counter saturates on an overflow, holding a value of 0xFFFFFFFF. 0 integrator sample counter holds a modulo 2 32 value on an overflow. 4–13 Reserved, should be cleared. details see Section , Integrator outputs. always return 0. For more details see Section , Integrator reset. DECFILTER_FINTVAL and DECFILTER_FINTCNT are updated. Section , Integrator inputs. 17 Reserved, should be cleared.

Table 650. For more details see Section , Integrator reset. 20–21 Reserved, should be cleared. 24 Reserved, should be cleared. Table 649. DECFILTER_MXCR Register Field Descriptions (continued) Table 650. SZROSEL – Integrator Zero mode

00 Hardware integrator zero request disabled

01 Integrator zero on toggle of hardware signal

10 Integrator zero on rising edge of hardware signal

11 Integrator zero on falling edge of hardware signal

Table 651. SHLTSEL – Integrator halt control selection

00 Hardware halt control signal disabled

01 Integrator halted, independently of the hardware signal

10 Integrator halted when signal is at logical 0

11 Integrator halted when signal is at logical 1

updates depend on the DECFILTER_MXCR bit SDMAE and DECFILTER_MCR bit SDIE. output is accumulated. For more details see Section , Integrator outputs. 28–29 Reserved, should be cleared. Integrator enabling and halting.

The hardware input signals are ZSELA for Decimation filter A and ZSELB for Decimation filter B, defined in

Section 16.6.24, IMUX Select Register 10 (SIU_ISEL10) .

The hardware input signals are HSELA for Decimation filter A and HSELB for Decimation filter B, defined in

Section 16.6.24, IMUX Select Register 10 (SIU_ISEL10) . Table 652. SRQSEL – Integrator output request mode

000 Hardware output request disabled

001 Integrator output request on toggle of hardware signal

010 Integrator output request on rising edge of hardware signal

011 Integrator output request on falling edge of hardware signal

101 Continuous output request on, independently of hardware signal

110 Continuous output request on when signal is at logical 0

111 Continuous output request on when signal is at logical 1

Table 653. SENSEL – Integrator enable control selection

00 Integrator disabled, independently of the hardware enable control

01 Integrator enabled, independently of the hardware signal

10 Integrator enabled when signal is at logical 0

11 Integrator enabled when signal is at logical 1

Figure 675. Decimation Filter Extended Status Register (DECFILTER_MXSR) Table 654. DECFILTER_MXSR Register Field Descriptions 0–6 Reserved, should be cleared. Register. This bit is self negated, therefore it is always read as zero. 8–9 Reserved, should be cleared. Integrator Sum Exception Clear bit. The SSEC bit clears the SSE flag bit in the Status Register. This bit is self negated, therefore it is always read as zero.

1 Clears SSE

Register. This bit is self negated, therefore it is always read as zero. 12 Reserved, should be cleared. Register. This bit is self negated, therefore it is always read as zero.

1 Clears SSOVF

1 Clears SVR

16–22 Reserved, should be cleared.

1 New integrator result available

0 No new integrator result available

24–25 Reserved, should be cleared. Section , Integrator exceptions. 1 Integrator accumulator exception. 0 No exception in the integrator accumulator. Section , Integrator exceptions. 1 Integrator counter exception. 0 No exception in the integrator counter. 28 Reserved, should be cleared. accumulator. This Flag is cleared by the SSOVFC bit or by a soft reset. 1 Integrator accumulator overflown. 0 No overflow in the integrator accumulator. Table 654. DECFILTER_MXSR Register Field Descriptions (continued)

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Product Information

RM0029 specifications and overview.

Summary

The primary objective of this document 24-Sep-2013

Description

The primary objective of this document 24-Sep-2013

Source title RM0029 Datasheet(PDF) - STMicroelectronics

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