Microcontroller

RM0008

STMicroelectronics

STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx advanced Arm-based 32-bit MCUs 14-Dec-2018

Manufacturer: STMicroelectronics

Document: 1134 Pages / 12Mb

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Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 1134

Technical content

Datasheet sections

1 Overview of the manual
2 Documentation conventions
2.1 General information
2.2 List of abbreviations for registers
2.3 Glossary
2.4 Peripheral availability
3 Memory and bus architecture
3.1 System architecture
3.2 Memory organization
3.3 Memory map
3.3.1 Embedded SRAM
3.3.2 Bit banding
3.3.3 Embedded Flash memory
3.4 Boot configuration
4 CRC calculation unit
4.1 CRC introduction
4.2 CRC main features
4.3 CRC functional description
4.4 CRC registers
4.4.1 Data register (CRC_DR)
4.4.2 Independent data register (CRC_IDR)
4.4.3 Control register (CRC_CR)
4.4.4 CRC register map
5 Power control (PWR)
5.1 Power supplies
5.1.1 Independent A/D and D/A converter supply and reference voltage
5.1.2 Battery backup domain
5.1.3 Voltage regulator
5.2 Power supply supervisor

Datasheet sections

7.2.3 PLL
7.2.4 LSE clock
7.2.5 LSI clock
7.2.6 System clock (SYSCLK) selection
7.2.7 Clock security system (CSS)
7.2.8 RTC clock
7.2.9 Watchdog clock
7.2.10 Clock-out capability
7.3 RCC registers
7.3.1 Clock control register (RCC_CR)
7.3.2 Clock configuration register (RCC_CFGR)
7.3.3 Clock interrupt register (RCC_CIR)
7.3.4 APB2 peripheral reset register (RCC_APB2RSTR)
7.3.5 APB1 peripheral reset register (RCC_APB1RSTR)
7.3.6 AHB peripheral clock enable register (RCC_AHBENR)
7.3.7 APB2 peripheral clock enable register (RCC_APB2ENR)
7.3.8 APB1 peripheral clock enable register (RCC_APB1ENR)
7.3.9 Backup domain control register (RCC_BDCR)
7.3.10 Control/status register (RCC_CSR)
7.3.11 RCC register map
8 Connectivity line devices: reset and cloc k control (RCC)
8.1 Reset
8.1.1 System reset
8.1.2 Power reset
8.1.3 Backup domain reset
8.2 Clocks
8.2.1 HSE clock
8.2.2 HSI clock
8.2.3 PLLs
8.2.4 LSE clock
8.2.5 LSI clock
8.2.6 System clock (SYSCLK) selection
8.2.7 Clock security system (CSS)
8.2.8 RTC clock
8.2.9 Watchdog clock
8.2.10 Clock-out capability

Datasheet sections

9.3 Alternate function I/O and debug configuration (AFIO)
9.3.1 Using OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15
9.3.2 Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1
9.3.3 CAN1 alternate function remapping
9.3.4 CAN2 alternate function remapping
9.3.5 JTAG/SWD alternate function remapping
9.3.6 ADC alternate function remapping
9.3.7 Timer alternate function remapping
9.3.8 USART alternate function remapping
9.3.9 I2C1 alternate function remapping
9.3.10 SPI1 alternate function remapping
9.3.11 SPI3/I2S3 alternate function remapping
9.3.12 Ethernet alternate function remapping
9.4 AFIO registers
9.4.1 Event control register (AFIO_EVCR)
9.4.2 AF remap and debug I/O configuration register (AFIO_MAPR)
9.4.3 External interrupt configuration register 1 (AFIO_EXTICR1)
9.4.4 External interrupt configuration register 2 (AFIO_EXTICR2)
9.4.5 External interrupt configuration register 3 (AFIO_EXTICR3)
9.4.6 External interrupt configuration register 4 (AFIO_EXTICR4)
9.4.7 AF remap and debug I/O configuration register2 (AFIO_MAPR2)
9.5 GPIO and AFIO register maps
10 Interrupts and events
10.1 Nested vectored interrupt controller (NVIC)
10.1.1 SysTick calibration value register
10.1.2 Interrupt and exception vectors
10.2 External interrupt/event controller (EXTI)
10.2.1 Main features
10.2.2 Block diagram
10.2.3 Wakeup event management
10.2.4 Functional description
10.2.5 External interrupt/event line mapping
10.3 EXTI registers
10.3.1 Interrupt mask register (EXTI_IMR)
10.3.2 Event mask register (EXTI_EMR)

Datasheet sections

11.11 ADC interrupts
11.12 ADC registers
11.12.1 ADC status register (ADC_SR)
11.12.2 ADC control register 1 (ADC_CR1)
11.12.3 ADC control register 2 (ADC_CR2)
11.12.4 ADC sample time register 1 (ADC_SMPR1)
11.12.5 ADC sample time register 2 (ADC_SMPR2)
11.12.7 ADC watchdog high threshold register (ADC_HTR)
11.12.8 ADC watchdog low threshold register (ADC_LTR)
11.12.9 ADC regular sequence register 1 (ADC_SQR1)
11.12.10 ADC regular sequence register 2 (ADC_SQR2)
11.12.11 ADC regular sequence register 3 (ADC_SQR3)
11.12.12 ADC injected sequence register (ADC_JSQR)
11.12.14 ADC regular data register (ADC_DR)
11.12.15 ADC register map
12 Digital-to-analog converter (DAC)
12.1 DAC introduction
12.2 DAC main features
12.3 DAC functional description
12.3.1 DAC channel enable
12.3.2 DAC output buffer enable
12.3.3 DAC data format
12.3.4 DAC conversion
12.3.5 DAC output voltage
12.3.6 DAC trigger selection
12.3.7 DMA request
12.3.8 Noise generation
12.3.9 Triangle-wave generation
12.4 Dual DAC channel conversion
12.4.1 Independent trigger without wave generation
12.4.2 Independent trigger with same LFSR generation
12.4.3 Independent trigger with different LFSR generation
12.4.4 Independent trigger with same triangle generation

Datasheet sections

13.3.4 Programmable data width, data alignment and endians
13.3.5 Error management
13.3.6 Interrupts
13.3.7 DMA request mapping
13.4 DMA registers
13.4.1 DMA interrupt status register (DMA_ISR)
13.4.2 DMA interrupt flag clear register (DMA_IFCR)
13.4.7 DMA register map
14 Advanced-control timers (TIM1 and TIM8)
14.1 TIM1 and TIM8 introduction
14.2 TIM1 and TIM8 main features
14.3 TIM1 and TIM8 functional description
14.3.1 Time-base unit
14.3.2 Counter modes
14.3.3 Repetition counter
14.3.4 Clock selection
14.3.5 Capture/compare channels
14.3.6 Input capture mode
14.3.7 PWM input mode
14.3.8 Forced output mode
14.3.9 Output compare mode
14.3.10 PWM mode
14.3.11 Complementary outputs and dead-time insertion
14.3.12 Using the break function
14.3.13 Clearing the OCxREF signal on an external event
14.3.15 One-pulse mode
14.3.16 Encoder interface mode
14.3.17 Timer input XOR function

Datasheet sections

15.3.7 Forced output mode
15.3.8 Output compare mode
15.3.9 PWM mode
15.3.10 One-pulse mode
15.3.11 Clearing the OCxREF signal on an external event
15.3.12 Encoder interface mode
15.3.13 Timer input XOR function
15.3.14 Timers and external trigger synchronization
15.3.15 Timer synchronization
15.3.16 Debug mode
15.4 TIMx registers
15.4.1 TIMx control register 1 (TIMx_CR1)
15.4.2 TIMx control register 2 (TIMx_CR2)
15.4.3 TIMx slave mode control register (TIMx_SMCR)
15.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER)
15.4.5 TIMx status register (TIMx_SR)
15.4.6 TIMx event generation register (TIMx_EGR)
15.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1)
15.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2)
15.4.9 TIMx capture/compare enable register (TIMx_CCER)
15.4.10 TIMx counter (TIMx_CNT)
15.4.11 TIMx prescaler (TIMx_PSC)
15.4.12 TIMx auto-reload register (TIMx_ARR)
15.4.13 TIMx capture/compare register 1 (TIM x_CCR1)
15.4.14 TIMx capture/compare register 2 (TIM x_CCR2)
15.4.15 TIMx capture/compare register 3 (TIM x_CCR3)
15.4.16 TIMx capture/compare register 4 (TIM x_CCR4)
15.4.17 TIMx DMA control register (TIMx_DCR)
15.4.18 TIMx DMA address for full transfer (TIMx_DMAR)
15.4.19 TIMx register map
16 General-purpose timers (TIM9 to TIM14)
16.1 TIM9 to TIM14 introduction
16.2 TIM9 to TIM14 main features
16.2.1 TIM9/TIM12 main features
16.2.2 TIM10/TIM11 and TIM13/TIM14 main features
16.3 TIM9 to TIM14 functional description

Datasheet sections

16.5.10 TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1)
16.5.11 TIM10/11/13/14 register map
17 Basic timers (TIM6 and TIM7)
17.1 TIM6 and TIM7 introduction
17.2 TIM6 and TIM7 main features
17.3 TIM6 and TIM7 functional description
17.3.1 Time-base unit
17.3.2 Counting mode
17.3.3 Clock source
17.3.4 Debug mode
17.4 TIM6 and TIM7 registers
17.4.1 TIM6 and TIM7 control register 1 (TIMx_CR1)
17.4.2 TIM6 and TIM7 control register 2 (TIMx_CR2)
17.4.3 TIM6 and TIM7 DMA/Interrupt enable register (TIMx_DIER)
17.4.4 TIM6 and TIM7 status register (TIMx_SR)
17.4.5 TIM6 and TIM7 event generation register (TIMx_EGR)
17.4.6 TIM6 and TIM7 counter (TIMx_CNT)
17.4.7 TIM6 and TIM7 prescaler (TIMx_PSC)
17.4.8 TIM6 and TIM7 auto-reload register (TIMx_ARR)
17.4.9 TIM6 and TIM7 register map
18 Real-time clock (RTC)
18.1 RTC introduction
18.2 RTC main features
18.3 RTC functional description
18.3.1 Overview
18.3.2 Resetting RTC registers
18.3.3 Reading RTC registers
18.3.4 Configuring RTC registers
18.3.5 RTC flag assertion
18.4 RTC registers
18.4.1 RTC control register high (RTC_CRH)
18.4.2 RTC control register low (RTC_CRL)
18.4.3 RTC prescaler load register (RTC_PRLH / RTC_PRLL)
18.4.4 RTC prescaler divider register (RTC_DIVH / RTC_DIVL)

Datasheet sections

21.4.1 NOR/PSRAM address mapping
21.4.2 NAND/PC Card address mapping
21.5 NOR Flash/PSRAM controller
21.5.1 External memory interface signals
21.5.2 Supported memories and transactions
21.5.3 General timing rules
21.5.4 NOR Flash/PSRAM controller asynchronous transactions
21.5.5 Synchronous transactions
21.5.6 NOR/PSRAM control registers
21.6 NAND Flash/PC Card controller
21.6.1 External memory interface signals
21.6.2 NAND Flash / PC Card supported me mories and transactions
21.6.3 Timing diagrams for NAND and PC Card
21.6.4 NAND Flash operations
21.6.5 NAND Flash prewait functionality
21.6.6 Computation of the error correction code (ECC)
21.6.7 PC Card/CompactFlash operations
21.6.8 NAND Flash/PC Card control registers
21.6.9 FSMC register map
22 Secure digital input/o utput interface (SDIO)
22.1 SDIO main features
22.2 SDIO bus topology
22.3 SDIO functional description
22.3.1 SDIO adapter
22.3.2 SDIO AHB interface
22.4 Card functional description
22.4.1 Card identification mode
22.4.2 Card reset
22.4.3 Operating voltage range validation
22.4.4 Card identification process
22.4.5 Block write
22.4.6 Block read
22.4.7 Stream access, stream write and stream read (MultiMediaCard only)
22.4.8 Erase: group erase and sector erase
22.4.9 Wide bus selection or deselection

Datasheet sections

22.9.11 SDIO status register (SDIO_STA)
22.9.12 SDIO interrupt clear register (SDIO_ICR)
22.9.13 SDIO mask register (SDIO_MASK)
22.9.14 SDIO FIFO counter register (SDIO_FIFOCNT)
22.9.15 SDIO data FIFO register (SDIO_FIFO)
22.9.16 SDIO register map
23 Universal serial bus fu ll-speed device interface (USB)
23.1 USB introduction
23.2 USB main features
23.3 USB functional description
23.3.1 Description of USB blocks
23.4 Programming considerations
23.4.1 Generic USB device programming
23.4.2 System and power-on reset
23.4.3 Double-buffered endpoints
23.4.4 Isochronous transfers
23.4.5 Suspend/Resume events
23.5 USB registers
23.5.1 Common registers
23.5.2 Endpoint-specific registers
23.5.3 Buffer descriptor table
23.5.4 USB register map
24 Controller area netwo rk (bxCAN)
24.3.2 Control, status and configuration registers
24.3.3 Tx mailboxes
24.3.4 Acceptance filters
24.4.1 Initialization mode
24.4.2 Normal mode
24.4.3 Sleep mode (low power)

Datasheet sections

25.3.10 Error flags
25.3.11 SPI interrupts
25.4 I 2S functional description
25.4.1 I 2S general description
25.4.2 Supported audio protocols
25.4.3 Clock generator
25.4.5 I 2S slave mode
25.4.6 Status flags
25.4.7 Error flags
25.4.9 DMA features
25.5 SPI and I 2S registers
25.5.1 SPI control register 1 (SPI_CR1) (not used in I 2S mode)
25.5.2 SPI control register 2 (SPI_CR2)
25.5.3 SPI status register (SPI_SR)
25.5.4 SPI data register (SPI_DR)
25.5.5 SPI CRC polynomial register (SPI_CRCPR) (not used in I
25.5.6 SPI RX CRC register ( SPI_RXCRCR) (not used in I2S mode)
25.5.7 SPI TX CRC register (S PI_TXCRCR) (not used in I2S mode)
25.5.8 SPI_I 2S configuration register (SPI_I2SCFGR)
25.5.9 SPI_I 2S prescaler register (SPI_I2SPR)
25.5.10 SPI register map
26 Inter-integrated circuit (I2C) interface
26.1 I 2C introduction
26.2 I 2C main features
26.3 I 2C functional description
26.3.1 Mode selection
26.3.2 I2C slave mode
26.3.3 I2C master mode
26.3.4 Error conditions
26.3.5 SDA/SCL line control
26.3.6 SMBus
26.3.7 DMA requests
26.3.8 Packet error checking

Datasheet sections

27.6.1 Status register (USART_SR)
27.6.2 Data register (USART_DR)
27.6.3 Baud rate register (USART_BRR)
27.6.4 Control register 1 (USART_CR1)
27.6.5 Control register 2 (USART_CR2)
27.6.6 Control register 3 (USART_CR3)
27.6.7 Guard time and prescaler register (USART_GTPR)
27.6.8 USART register map
28 USB on-the-go full-speed (OTG_FS)
28.1 OTG_FS introduction
28.2 OTG_FS main features
28.2.1 General features
28.2.2 Host-mode features
28.2.3 Peripheral-mode features
28.3 OTG_FS functional description
28.3.1 OTG pins
28.3.2 OTG full-speed core
28.3.3 Full-speed OTG PHY
28.4 OTG dual role device (DRD)
28.4.1 ID line detection
28.4.2 HNP dual role device
28.4.3 SRP dual role device
28.5 USB peripheral
28.5.1 SRP-capable peripheral
28.5.2 Peripheral states
28.5.3 Peripheral endpoints
28.6 USB host
28.6.1 SRP-capable host
28.6.2 USB host states
28.6.3 Host channels
28.6.4 Host scheduler
28.7 SOF trigger
28.7.1 Host SOFs
28.7.2 Peripheral SOFs
28.8 OTG low-power modes

Datasheet sections

29.2.2 DMA features
29.2.3 PTP features
29.3 Ethernet pins
29.4 Ethernet functional description: SMI, MII and RMII
29.4.1 Station management interface: SMI
29.4.2 Media-independent interface: MII
29.4.3 Reduced media-independent interface: RMII
29.4.4 MII/RMII selection
29.5.2 MAC frame transmission
29.5.3 MAC frame reception
29.5.4 MAC interrupts
29.5.5 MAC filtering
29.5.6 MAC loopback mode
29.5.7 MAC management counters: MMC
29.5.8 Power management: PMT
29.5.9 Precision time protocol (IEEE1588 PTP)
29.6 Ethernet functional description: DMA controller operation
29.6.1 Initialization of a transfer using DMA
29.6.2 Host bus burst access
29.6.3 Host data buffer alignment
29.6.4 Buffer size calculations
29.6.5 DMA arbiter
29.6.6 Error response to DMA
29.6.7 Tx DMA configuration
29.6.8 Rx DMA configuration
29.6.9 DMA interrupts
29.7 Ethernet interrupts
29.8 Ethernet register descriptions
29.8.1 MAC register description
29.8.2 MMC register description
29.8.3 IEEE 1588 time stamp registers
29.8.4 DMA register description
29.8.5 Ethernet register maps

Datasheet sections

31.14 ITM (instrumentation trace macrocell)
31.14.1 General description
31.14.2 Time stamp packets, synchronization and overflow packets
31.15 ETM (Embedded trace macrocell)
31.15.1 ETM general description
31.15.2 ETM signal protocol and packet types
31.15.3 Main ETM registers
31.15.4 ETM configuration example
31.16 MCU debug component (DBGMCU)
31.16.1 Debug support for low-power modes
31.16.2 Debug support for timers, watchdog, bxCAN and I 2C
31.16.3 Debug MCU configuration register
31.17 TPIU (trace port interface unit)
31.17.1 Introduction
31.17.2 TRACE pin assignment
31.17.3 TPUI formatter
31.17.4 TPUI frame synchronization packets
31.17.5 Transmission of the synchronization frame packet
31.17.6 Synchronous mode
31.17.7 Asynchronous mode
31.17.8 TRACECLKIN connection inside the STM32F10xxx
31.17.9 TPIU registers
31.17.10 Example of configuration
31.18 DBG register map
32 Revision history

December 2018 RM0008 Rev 20 1/1134 RM0008 Reference manual STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx advanced Arm®-based 32-bit MCUs Introduction This reference manual is addressed to application developers. It provides complete information on how to use the STM32F101xx, STM32F102xx, STM32F103xx and STM32F105xx/STM32F107xx microcontroller memory and peripherals. The STM32F101xx, STM32F102xx, STM32F103xx and STM32F105xx/STM32F107xx will be referred to as STM32F10xxx throughout the document, unless otherwise specified. The STM32F10xxx is a family of microcontrollers with different memory sizes, packages and peripherals. For ordering information, mechanical and electrical device characteristics refer to the low-, medium-, high- and XL-density STM32F101xx and STM32F103xx datasheets, to the low- and medium-density STM32F102xx datasheets and to the STM32F105xx/STM32F107xx connectivity line datasheet. For information on programming, erasing and protection of the internal Flash memory refer to:

PM0075, the Flash programming manual for low-, medium- high-density and connectivity line STM32F10xxx devices
PM0068, the Flash programming manual for XL-density STM32F10xxx devices. For information on the Arm ® Cortex®-M3 core, refer to the STM32F10xxx Cortex®-M3 programming manual (PM0056). Related documents Available from www.st.com:
STM32F101xx, STM32F102xx, STM32F103xx and STM32F105xx/STM32F107xx datasheets
STM32F10xxx Cortex®-M3 programming manual (PM0056)
STM32F10xxx Flash programming manual (PM0075)
STM32F10xxx XL-density Flash programming manual (PM0068)

7 Low-, medium-, high- and XL-density reset and clock

9 General-purpose and alte rnate-function I/Os

12.5.3 DAC channel1 12-bit right-aligned data holding register

12.5.4 DAC channel1 12-bit left aligned data holding register

12.5.5 DAC channel1 8-bit right aligned data holding register

12.5.6 DAC channel2 12-bit right aligned data holding register

12.5.7 DAC channel2 12-bit left aligned data holding register

12.5.8 DAC channel2 8-bit right-aligned data holding register

12.5.9 Dual DAC 12-bit right-aligned data holding register

12.5.10 DUAL DAC 12-bit left aligned data holding register

12.5.11 DUAL DAC 8-bit right aligned data holding register

14.4.7 TIM1 and TIM8 capture/compare mode register 1 (TIMx_CCMR1) . . 349 14.4.8 TIM1 and TIM8 capture/compare mode register 2 (TIMx_CCMR2) . . 351

16.5.5 TIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1) . . 462

27 Universal synchr onous asynchronous receiver

28.16.5 OTG_FS power and clock gating control register

29 Ethernet (ETH): media access control (MAC) with

31.4.4 Using serial wire and releasing the unused debug pins as GPIOs . . 1083

31.9 AHB-AP (AHB access port) - valid for both JTAG-DP

Table 83. Output control bits for complementary OCx and OCxN channels with Table 98. Minimum and maximum timeout values @36 MHz (f

Table 183. Audio-frequency precision using standard 8 MHz HSE Table 184. Audio-frequency precision using standard 25 MHz and PLL3 Table 185. Audio-frequency precision using standard 14.7456 MHz and PLL3 Table 186. I

Table 227. Cortex

1 Overview of the manual

Table 1. Sections related to each STM32F10xxx product

Note: (1) Available only on XL-density devices. Table 1. Sections related to each STM32F10xxx product (continued)

The section in this row must be read when using the peripherals in columns marked with “•" ◊ The section in this row can optionally be read when using the peripherals in columns marked with “◊"

Table 2. Sections related to each peripheral

Table 2. Sections related to each peripheral (continued)

RM0008 Documentation conventions

2 Documentation conventions

2.1 General information

The STM32F10xxx devices have an Arm®(a) Cortex®-M3 core.

2.2 List of abbrevia tions for registers

The following abbreviations are used in register descriptions: a. Arm is a registered trademark of Arm Limited (o r its subsidiaries) in the US and/or elsewhere. read/write (rw) Software can read and write to these bits. read-only (r) Software can only read these bits. write-only (w) Software can only write to this bit. Reading the bit returns the reset value. read/clear (rc_w1) Software can read as well as clear this bit by writing 1. Writing ‘0’ has no effect on the bit value. read/clear (rc_w0) Software can read as well as clear this bit by writing 0. Writing ‘1’ has no effect on the bit value. read/clear by read (rc_r) Software can read this bit. Reading this bit automatically clears it to ‘0’. Writing ‘0’ has no effect on the bit value. read/set (rs) Software can read as well as set this bit. Writing ‘0’ has no effect on the bit value. read-only write trigger (rt_w) Software can read this bit. Writing ‘0’ or ‘1’ triggers an event but has no effect on the bit value. toggle (t) Software can only toggle this bit by writing ‘1’. Writing ‘0’ has no effect. Reserved (Res.) Reserved bit, must be kept at reset value.

Documentation conventions RM0008 46/1134 RM0008 Rev 20

2.3 Glossary

Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
Word: data of 32-bit length.
Half-word: data of 16-bit length.
Byte: data of 8-bit length.

2.4 Peripheral availability

For peripheral availability and number across all STM32F10xxx sales types, refer to the low-, medium-, high- and XL-density STM32F101xx and STM32F103xx datasheets, to the low- and medium-density STM32F102xx datasheets and to the connectivity line devices, STM32F105xx/STM32F107xx.

3 Memory and bus architecture

3.1 System architecture

Four masters: –C o r t e x ®-M3 core DCode bus (D-bus) and System bus (S-bus) – GP-DMA1 & 2 (general-purpose DMA)
Four slaves: – Internal SRAM – Internal Flash memory –F S M C – AHB to APBx (APB1 or APB2), wh ich connect all the APB peripherals These are interconnected using a multilayer AHB bus architecture as shown in Figure 1:

Figure 1. System architecture (low-, medium-, XL-density devices)

Five masters: –C o r t e x ®-M3 core DCode bus (D-bus) and System bus (S-bus) – GP-DMA1 & 2 (general-purpose DMA) – Ethernet DMA
Three slaves: – Internal SRAM – Internal Flash memory – AHB to APB bridges (AHB to APBx), which connect all the APB peripherals These are interconnected using a multilayer AHB bus architecture as shown in Figure 2:

Figure 2. System architecture in connectivity line devices instruction interface. Prefetching is performed on this bus.

RM0008 Memory and bus architecture DCode bus This bus connects the DCode bus (literal load and debug access) of the Cortex®-M3 core to the Flash memory Data interface. System bus This bus connects the system bus of the Cortex®-M3 core (peripherals bus) to a BusMatrix which manages the arbitration between the core and the DMA. DMA bus This bus connects the AHB master interface of the DMA to the BusMatrix which manages the access of CPU DCode and DMA to SRAM, Flash memory and peripherals. BusMatrix The BusMatrix manages the access arbitration between the core system bus and the DMA master bus. The arbitration uses a Round Robin algorithm. In connectivity line devices, the BusMatrix is composed of five masters (CPU DCode, System bus, Ethernet DMA, DMA1 and DMA2 bus) and three slaves (FLITF, SRAM and AHB2APB bridges). In other devices, the BusMatrix is composed of four masters (CPU DCode, System bus, DMA1 bus and DMA2 bus) and four slaves (FLITF, SRAM, FSMC and AHB2APB bridges). AHB peripherals are connected on system bus through a BusMatrix to allow DMA access. AHB/APB bridges (APB) The two AHB/APB bridges provide full synchronous connections between the AHB and the 2 APB buses. APB1 is limited to 36 MHz, APB2 operates at full speed (up to 72 MHz depending on the device). Refer to Table 3 for the address mapping of the peripherals connected to each bridge. After each device reset, all peripheral clocks are disabled (except for the SRAM and FLITF). Before using a peripheral you have to enable its clock in the RCC_AHBENR, RCC_APB2ENR or RCC_APB1ENR register. Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.

3.2 Memory organization

Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space. The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant. For the detailed mapping of peripheral registers refer to the related sections. The addressable memory space is divided into 8 main blocks, each of 512 MB. All the memory areas that are not allocated to on-chip memories and peripherals are considered “Reserved”). Refer to the Memory map figure in the corresponding product datasheet.

3.3 Memory map

Table 3. Register boundary addresses

Table 3. Register boundary addresses (continued)

This shared SRAM can be fully accessed only in low-, medium-, high- and XL-density devices, not in connectivity line

RM0008 Memory and bus architecture

3.3.1 Embedded SRAM

The STM32F10xxx features up to 96 Kbytes of static SRAM. It can be accessed as bytes, half-words (16 bits) or full words (32 bits). The SRAM start address is 0x2000 0000.

3.3.2 Bit banding

The Cortex®-M3 memory map includes two bit-band regions. These regions map each word in an alias region of memory to a bit in a bit-band region of memory. Writing to a word in the alias region has the same effect as a read-modify-write operation on the targeted bit in the bit-band region. In the STM32F10xxx both peripheral registers and SRAM are mapped in a bit-band region. This allows single bit-band write and read operations to be performed. The operations are only available for Cortex ®-M3 accesses, not from other bus masters (e.g. DMA). A mapping formula shows how to reference each word in the alias region to a corresponding bit in the bit-band region. The mapping formula is: bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number × 4) where: bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit. bit_band_base is the starting address of the alias region byte_offset is the number of the byte in the bit-band region that contains the targeted bit bit_number is the bit position (0-7) of the targeted bit. Example: The following example shows how to map bit 2 of the byte located at SRAM address 0x20000300 in the alias region: 0x22006008 = 0x22000000 + (0x300*32) + (2*4). Writing to address 0x22006008 has the same effect as a read-modify-write operation on bit 2 of the byte at SRAM address 0x20000300. Reading address 0x22006008 returns the value (0x01 or 0x00) of bit 2 of the byte at SRAM address 0x20000300 (0x01: bit set; 0x00: bit reset). For more information on Bit-Banding refer to the Cortex ®-M3 Technical Reference Manual.

3.3.3 Embedded Flash memory

For XL-density devices: density of up to 1 Mbyte with dual bank architecture for read- while-write (RWW) capability: – bank 1: fixed size of 512 Kbytes – bank 2: up to 512 Kbytes
For other devices: density of up to 512 Kbytes
Memory organization: the Flash memory is organized as a main block and an information block: – Main memory block of size: up to 128 Kbytes × 64 bits divided into 512 pages of 2 Kbytes each (see Table 8) for XL-density devices up to 4 Kb × 64 bits divided into 32 pages of 1 Kbyte each for low-density devices (see Table 4) up to 16 Kb × 64 bits divided into 128 pages of 1 Kbyte each for medium-density devices (see Table 5) up to 64 Kb × 64 bits divided into 256 pages of 2 Kbytes each (see Table 6) for high-density devices up to 32 Kbit × 64 bits divided into 128 pages of 2 Kbytes each (see Table 7) for connectivity line devices – Information block of size: 770 × 64 bits for XL-density devices (see Table 8) 2360 × 64 bits for connectivity line devices (see Table 7) 258 × 64 bits for other devices (see Table 4, Table 5 and Table 6) The Flash memory interface (FLITF) features:
Read interface with prefetch buffer (2x64-bit words)
Option byte Loader
Flash Program / Erase operation
Read / Write protection

Table 4. Flash module organization (low-density devices)

Table 5. Flash module organization (medium-density devices) Table 4. Flash module organization (low-density devices) (continued)

Table 6. Flash module organization (high-density devices) Table 7. Flash module organization (connectivity line devices)

Table 8. XL-density Flash module organization Table 7. Flash module organization (connectivity line devices) (continued)

Flash programming manual” (PM0075) for other devices. in the Flash memory interface, and priority is given to data access on the DCode bus.

Latency: number of wait states for a read operation programmed on-the-fly
Prefetch buffer (2 x 64-bit blocks): it is enabled after reset; a whole block can be replaced with a single read from the Flash memory as the size of the block matches the bandwidth of the Flash memory. Thanks to the prefetch buffer, faster CPU execution is possible as the CPU fetches one word at a time with the next word readily available in the prefetch buffer
Half cycle: for power optimization Note: These options have to be used in accordance with the Flash memory access time. The wait states represent the ratio of the SYSCLK (system clock) period to the Flash memory access time: - 0 wait states, if 0 < SYSCLK ≤ 24 MHz - 1 wait state, if 24 MHz < SYSCLK ≤ 48 MHz - 2 wait states, if 48 MHz < SYSCLK ≤ 72 MHz Half cycle configuration is not available in combination with a prescaler on the AHB. The system clock (SYSCLK) should be equal to the HCLK clock. This feature can therefore be Flash memory interface registers FLASH_ACR 0x4002 2000 - 0x4002 2003 4 FLASH_KEYR 0x4002 2004 - 0x4002 2007 4 FLASH_OPTKEYR 0x4002 200 8 - 0x4002 200B 4 FLASH_SR 0x4002 200C - 0x4002 200F 4 FLASH_CR 0x4002 2010 - 0x4002 2013 4 FLASH_AR 0x4002 2014 - 0x4002 2017 4 Reserved 0x4002 2018 - 0x4002 201B 4 FLASH_OBR 0x4002 201C - 0x4002 201F 4 FLASH_WRPR 0x4002 2020 - 0x4002 2023 4 Reserved 0x4002 2024 - 0x4002 2043 32 FLASH_KEYR2 0x4002 2044 - 0x4002 2047 4 Reserved 0x4002 2048 - 0x4002 204B 4 FLASH_SR2 0x4002 204C - 0x4002 204F 4 FLASH_CR2 0x4002 2050 - 0x4002 2053 4 FLASH_AR2 0x4002 2054 - 0x4002 2057 4

Table 8. XL-density Flash module organization (continued)

RM0008 Memory and bus architecture used only with a low-frequency clock of 8 MHz or less. It can be generated from the HSI or the HSE but not from the PLL. The prefetch buffer must be kept on when using a prescaler different from 1 on the AHB clock. The prefetch buffer must be switched on/off only when SYSCLK is lower than 24 MHz and no prescaler is applied on the AHB clock (SYSCLK must be equal to HCLK). The prefetch buffer is usually switched on/off during the initialization routine, while the microcontroller is running on the internal 8 MHz RC (HSI) oscillator. Using DMA: DMA accesses Flash memory on the DCode bus and has priority over ICode instructions. The DMA provides one free cycle after each transfer. Some instructions can be performed together with DMA transfer. Programming and erasing the Flash memory The Flash memory can be programmed 16 bits (half words) at a time. For write and erase operations on the Flash memory (write/erase), the internal RC oscillator (HSI) must be ON. The Flash memory erase operation can be performed at page level or on the whole Flash area (mass-erase). The mass-erase does not affect the information blocks. To ensure that there is no over-programming, the Flash Programming and Erase Controller blocks are clocked by a fixed clock. The End of write operation (programming or erasing) can trigger an interrupt. This interrupt can be used to exit from WFI mode, only if the FLITF clock is enabled. Otherwise, the interrupt is served only after an exit from WFI. The FLASH_ACR register is used to enable/disable prefetch and half cycle access, and to control the Flash memory access time according to the CPU frequency. The tables below provide the bit map and bit descriptions for this register. For complete information on Flash memory operations and register configurations, refer to the STM32F10xxx Flash programming manual (PM0075) or to the XL STM32F10xxx Flash programming manual (PM0068).

Memory and bus architecture RM0008 60/1134 RM0008 Rev 20 Flash access control register (FLASH_ACR) Address offset: 0x00 Reset value: 0x0000 0030

3.4 Boot configuration

In the STM32F10xxx, 3 different boot modes can be selected through BOOT[1:0] pins as shown in Table 9. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PRFTBS PRFTBE HLFCYA LATENCY rr w r w r w r w r w Bits 31:6 Reserved, must be kept at reset value. Bit 5 PRFTBS: Prefetch buffer status This bit provides the status of the prefetch buffer. 0: Prefetch buffer is disabled 1: Prefetch buffer is enabled Bit 4 PRFTBE: Prefetch buffer enable 0: Prefetch is disabled 1: Prefetch is enabled Bit 3 HLFCYA: Flash half cycle access enable 0: Half cycle is disabled 1: Half cycle is enabled Bits 2:0 LATENCY: Latency These bits represent the ratio of the SYSCLK (system clock) period to the Flash access time.

000 Zero wait state, if 0 < SYSCLK≤ 24 MHz

001 One wait state, if 24 MHz < SYSCLK ≤ 48 MHz

010 Two wait states, if 48 MHz < SYSCLK ≤ 72 MHzTable 9. Boot modes Boot mode selection pins Boot mode Aliasing BOOT1 BOOT0 x 0 Main Flash memory Main Flash memory is selected as boot space 0 1 System memory System memory is selected as boot space 1 1 Embedded SRAM Embedded SRAM is selected as boot space

RM0008 Memory and bus architecture The values on the BOOT pins are latched on the 4th rising edge of SYSCLK after a reset. It is up to the user to set the BOOT1 and BOOT0 pins after Reset to select the required boot mode. The BOOT pins are also re-sampled when exiting from Standby mode. Consequently they must be kept in the required Boot mode configuration in Standby mode. After this startup delay has elapsed, the CPU fetches the top-of-stack value from address 0x0000 0000, then starts code execution from the boot memory starting from 0x0000 0004. Due to its fixed memory map, the code area starts from address 0x0000 0000 (accessed through the ICode/DCode buses) while the data area (SRAM) starts from address 0x2000 0000 (accessed through the system bus). The Cortex ®-M3 CPU always fetches the reset vector on the ICode bus, which implies to have the boot space available only in the code area (typically, Flash memory). STM32F10xxx microcontrollers implement a special mechanism to be able to boot also from SRAM and not only from main Flash memory and System memory. Depending on the selected boot mode, main Flash memory, system memory or SRAM is accessible as follows:

Boot from main Flash memory: the main Flash memory is aliased in the boot memory space (0x0000 0000), but still accessible from its original memory space (0x800 0000). In other words, the Flash memory contents can be accessed starting from address 0x0000 0000 or 0x800 0000.
Boot from system memory: the system memory is aliased in the boot memory space (0x0000 0000), but still accessible from its original memory space (0x1FFF B000 in connectivity line devices, 0x1FFF F000 in other devices).
Boot from the embedded SRAM: SRAM is accessible only at address 0x2000 0000. Note: When booting from SRAM, in the applicatio n initialization code, you have to relocate the vector table in SRAM using the NVIC exception table and offset register. For XL-density devices, when booting from the main Flash memory, you have an option to boot from any of two memory banks. By default, boot from Flash memory bank 1 is selected. You can choose to boot from Flash memory bank 2 by clearing the BFB2 bit in the user option bytes. When this bit is cleared and the boot pins are in the boot from main Flash memory configuration, the device boots from system memory, and the boot loader jumps to execute the user application programmed in Flash memory bank 2. For further details refer to AN2606. Note: When booting from Bank2 in the applications initialization code, relocate the vector table to the Bank2 base address. (0x0808 0000) using the NVIC exception table and offset register. Embedded boot loader The embedded boot loader is located in the System memory, programmed by ST during production. It is used to reprogram the Flash memory with one of the available serial interfaces:
In low-, medium- and high-density devices the bootoader is activated through the USART1 interface.
In XL-density devices the boot loader is activated through the following interfaces: USART1 or USART2 (remapped).
In connectivity line devices the boot loader can be activated through one of the following interfaces: USART1, USART2 (remapped), CAN2 (remapped) or USB OTG FS in Device mode (DFU: device firmware upgrade).

Memory and bus architecture RM0008 62/1134 RM0008 Rev 20 The USART peripheral operates with the internal 8 MHz oscillator (HSI). The CAN and USB OTG FS, however, can only function if an external 8 MHz, 14.7456 MHz or 25 MHz clock (HSE) is present. Note: For further deta ils refer to AN2606.

RM0008 CRC calculation unit

4 CRC calculation unit

4.1 CRC introduction

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location.

4.2 CRC main features

Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7 –X 32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +X8 + X7 + X5 + X4 + X2+ X + 1
Single input/output 32-bit data register
CRC computation done in 4 AHB clock cycles (HCLK)
General-purpose 8-bit register (can be used for temporary storage) The block diagram is shown in Figure 3.

Figure 3. CRC calculation unit block diagram

4.3 CRC functional description

is used as an input register to enter new data in the CRC calculator (when writing into the register)
holds the result of the previous CRC calculation (when reading the register) Each write operation into the data register creates a combination of the previous CRC value and the new one (CRC computation is done on the whole 32-bit data word, and not byte per byte). The write operation is stalled until the end of the CRC computation, thus allowing back-to- back write accesses or consecutive write and read accesses. The CRC calculator can be reset to 0xFFFF FFFF with the RESET control bit in the CRC_CR register. This operation does not affect the contents of the CRC_IDR register.

4.4 CRC registers

The CRC registers have to be accessed by words (32 bits).

4.4.1 Data register (CRC_DR)

4.4.2 Independent data register (CRC_IDR)

4.4.3 Control register (CRC_CR)

4.4.4 CRC register map

The following table provides the CRC register map and reset values. Used as an input register when writing new data into the CRC calculator. Holds the previous CRC calculation result when it is read. Bits 31:8 Reserved, must be kept at reset value. Can be used as a temporary storage location for one byte. Bits 31:1 Reserved, must be kept at reset value. Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF. This bit can only be set, it is automatically cleared by hardware. Table 10. CRC calculation unit register map and reset values

Table 10. CRC calculation unit register map and reset values (continued)

RM0008 Power control (PWR)

5 Power control (PWR)

5.1 Power supplies

The device requires a 2.0-to-3.6 V operating voltage supply (VDD). An embedded regulator is used to supply the internal 1.8 V digital power. The real-time clock (RTC) and backup registers can be powered from the VBAT voltage when the main VDD supply is powered off.

Figure 4. Power supply overview

V DDA and VSSA must be connected to VDD and VSS, respectively.

5.1.1 Independent A/D and D/A con verter supply and reference voltage

which can be separately filtered and shielded from noise on the PCB.

The ADC and DAC voltage supply input is available on a separate VDDA pin.
An isolated supply ground connection is provided on pin VSSA. When available (according to package), VREF- must be tied to VSSA. On 100-pin and 144-pin packages To ensure a better accuracy on low-voltage inputs and outputs, the user can connect a separate external reference voltage on VREF+. VREF+ is the highest voltage, represented by the full scale value, for an analog input (ADC) or output (DAC) signal. The voltage on VREF+ can range from 2.4 V to VDDA. On 64-pin packages and packages with less pins The VREF+ and VREF- pins are not available, they are internally connected to the ADC voltage supply (VDDA) and ground (VSSA). A/D converter VDDA VDD VSSA VREF+ VBAT VSS I/O Ring (VDD) (from 2.4 V up to VDDA) BKP registers Temp. sensor Reset block Standby circuitry PLL (Wakeup logic, IWDG) RTC Voltage Regulator Core Memories digital peripherals Low voltage detector VREF- VDDA domain VDD domain 1.8 V domain Backup domain LSE crystal 32K osc RCC BDCR register (VSSA) (VSS) D/A converter

RM0008 Power control (PWR)

5.1.2 Battery backup domain

To retain the content of the Backup registers and supply the RTC function when VDD is turned off, VBAT pin can be connected to an optional standby voltage supplied by a battery or by another source. The VBAT pin powers the RTC unit, the LSE oscillator and the PC13 to PC15 IOs, allowing the RTC to operate even when the main digital supply (VDD) is turned off. The switch to the VBAT supply is controlled by the Power Down Reset embedded in the Reset block. Warning: During tRSTTEMPO (temporization at VDD startup) or after a PDR is detected, the power switch between VBAT and VDD remains connected to VBAT. During the startup phase, if VDD is established in less than tRSTTEMPO (Refer to the datasheet for the value of tRSTTEMPO) and VDD > VBAT + 0.6 V, a current may be injected into VBAT through an internal diode connected between VDD and the power switch (VBAT). If the power supply/battery connected to the VBAT pin cannot support this current injection, it is strongly recommended to connect an external low-drop diode between this power supply and the VBAT pin. If no external battery is used in the application, it is recommended to connect VBAT externally to VDD with a 100 nF external ceramic decoupling capacitor (for more details refer to AN2586). When the backup domain is supplied by VDD (analog switch connected to VDD), the following functions are available:

PC14 and PC15 can be used as either GPIO or LSE pins
PC13 can be used as GPIO, TAMPER pin, RTC Calibration Clock, RTC Alarm or second output (refer to Section 6: Backup registers (BKP)) Note: Due to the fact that the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is restricted: the speed has to be limited to 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive a LED). When the backup domain is supplied by VBAT (analog switch connected to VBAT because VDD is not present), the following functions are available:
PC14 and PC15 can be used as LSE pins only
PC13 can be used as TAMPER pin, RTC Alarm or Second output (refer to Section 6.4.2: RTC clock calibration register (BKP_RTCCR)).

5.1.3 Voltage regulator

depending on the application modes.

In Run mode, the regulator supplies full power to the 1.8 V domain (core, memories and digital peripherals).
In Stop mode the regulator supplies low-power to the 1.8 V domain, preserving contents of registers and SRAM
In Standby Mode, the regulator is powered off. The contents of the registers and SRAM are lost except for the Standby circuitry and the Backup Domain.

5.2 Power supply supervisor

5.2.1 Power on reset (POR )/power down reset (PDR)

power on/power down reset threshold, refer to the electrical characteristics of the datasheet. Figure 5. Power on reset/power down reset waveform

5.2.2 Programmable volt age detector (PVD)

selected by the PLS[2:0] bits in the Power control register (PWR_CR). The PVD is enabled by setting the PVDE bit.

Figure 6. PVD thresholds

5.3 Low-power modes

Sleep mode (CPU clock off, all peripherals including Cortex ®-M3 core peripherals like NVIC, SysTick, etc. are kept running)
Stop mode (all clocks are stopped)
Standby mode (1.8V domain powered-off) In addition, the power consumption in Run mode can be reduce by one of the following means:
Slowing down the system clocks
Gating the clocks to the APB and AHB peripherals when they are unused.

5.3.1 Slowing dow n system clocks

down peripherals before entering Sleep mode. For more details refer to Section 7.3.2: Clock configuration register (RCC_CFGR). Table 11. Low-power mode summary

RM0008 Power control (PWR)

5.3.2 Peripheral clock gating

In Run mode, the HCLK and PCLKx for individual peripherals and memories can be stopped at any time to reduce power consumption. To further reduce power consumption in Sleep mode the peripheral clocks can be disabled prior to executing the WFI or WFE instructions. Peripheral clock gating is controlled by the AHB peripheral clock enable register (RCC_AHBENR), APB1 peripheral clock enable register (RCC_APB1ENR) and APB2 peripheral clock enable register (RCC_APB2ENR).

5.3.3 Sleep mode

The Sleep mode is entered by executing the WFI (Wait For Interrupt) or WFE (Wait for Event) instructions. Two options are available to select the Sleep mode entry mechanism, depending on the SLEEPONEXIT bit in the Cortex®-M3 System Control register:

Sleep-now: if the SLEEPONEXIT bit is cleared, the MCU enters Sleep mode as soon as WFI or WFE instruction is executed.
Sleep-on-exit: if the SLEEPONEXIT bit is set, the MCU enters Sleep mode as soon as it exits the lowest priority ISR. In the Sleep mode, all I/O pins keep the same state as in the Run mode. Refer to Table 12 and Table 13 for details on how to enter Sleep mode. Exiting Sleep mode If the WFI instruction is used to enter Sleep mode, any peripheral interrupt acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device from Sleep mode. If the WFE instruction is used to enter Sleep mode, the MCU exits Sleep mode as soon as an event occurs. The wakeup event can be generated either by:
enabling an interrupt in the peripheral control register but not in the NVIC, and enabling the SEVONPEND bit in the Cortex®-M3 System Control register. When the MCU resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.
or configuring an external or internal EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is not set. This mode offers the lowest wakeup time as no time is wasted in interrupt entry/exit. Refer to Table 12 and Table 13 for more details on how to exit Sleep mode.

5.3.4 Stop mode

clock gating. The voltage regulator can be configured either in normal or low-power mode. oscillators are disabled. SRAM and register contents are preserved. In the Stop mode, all I/O pins keep the same state as in the Run mode. Refer to Table 14 for details on how to enter the Stop mode. Table 12. Sleep-now ®-M3 System Control register. Table 13. Sleep-on-exit ®-M3 System Control register. Mode exit Interrupt: refer to Section 10.1.2: Interrupt and exception vectors.

Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a Reset. See Section 19.3: IWDG functional description.
Real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control register (RCC_BDCR)
Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status register (RCC_CSR).
External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the Backup domain control register (RCC_BDCR). The ADC or DAC can also consume power during the Stop mode, unless they are disabled before entering it. To disable them, the ADON bit in the ADC_CR2 register and the ENx bit in the DAC_CR register must both be written to 0. Note: If the application needs to disable the external clock before entering Stop mode, the HSEON bit must first be disabled and the system clock switched to HSI. Otherwise, if the HSEON bit remains enabled and the external clock (external oscillator) is removed when entering Stop mode, the clock security system (CSS) feature must be enabled to detect any external oscillator failure and avoid a malfunction behavior when entering stop mode. Exiting Stop mode Refer to Table 14 for more details on how to exit Stop mode. When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock. When the voltage regulator operates in low-power mode, an additional startup delay is incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop mode, the consumption is higher although the startup time is reduced.

Table 14. Stop mode program execution continues. Interrupt and exception vectors.

5.3.5 Standby mode

and Standby circuitry (see Figure 4). Refer to Table 15 for more details on how to enter Standby mode.

Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a reset. See Section 19.3: IWDG functional description.
Real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control register (RCC_BDCR)
Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status register (RCC_CSR).
External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the Backup domain control register (RCC_BDCR) Exiting Standby mode The microcontroller exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin or the rising edge of an RTC alarm occurs (see Figure 179: RTC simplified block diagram). All registers are reset after wakeup from Standby except for Power control/status register (PWR_CSR). After waking up from Standby mode, program execution restarts in the same way as after a Reset (boot pins sampling, vector reset is fetched, etc.). The SBF status flag in the Power control/status register (PWR_CSR) indicates that the MCU was in Standby mode. Refer to Table 15 for more details on how to exit Standby mode.

Table 15. Standby mode

RM0008 Power control (PWR) I/O states in Standby mode In Standby mode, all I/O pins are high impedance except:

Reset pad (still available)
TAMPER pin if configured for tamper or calibration out
WKUP pin, if enabled Debug mode By default, the debug connection is lost if the application puts the MCU in Stop or Standby mode while the debug features are used. This is due to the fact that the Cortex®-M3 core is no longer clocked. However, by setting some configuration bits in the DBGMCU_CR register, the software can be debugged even when using the low-power modes extensively. For more details, refer to Section 31.16.1: Debug support for low-power modes.

5.3.6 Auto-wakeup (AWU) from low-power mode

The RTC can be used to wakeup the MCU from low-power mode without depending on an external interrupt (Auto-wakeup mode). The RTC provides a programmable time base for waking up from Stop or Standby mode at regular intervals. For this purpose, two of the three alternative RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR):

Low-power 32.768 kHz external crystal oscillator (LSE OSC). This clock source provides a precise time base with very low-power consumption (less than 1µA added consumption in typical conditions)
Low-power internal RC Oscillator (LSI RC) This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This internal RC Oscillator is designed to add minimum power consumption. To wakeup from Stop mode with an RTC alarm event, it is necessary to:
Configure the EXTI Line 17 to be sensitive to rising edge
Configure the RTC to generate the RTC alarm To wakeup from Standby mode, there is no need to configure the EXTI Line 17.

5.4 Power control registers

The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

5.4.1 Power control register (PWR_CR)

Address offset: 0x00 Reset value: 0x0000 0000 (reset by wakeup from Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 Reserved DBP PLS[2:0] PVDE CSBF CWUF PDDS LPDS rw rw rw rw rw rc_w1 rc_w1 rw rw

Power control (PWR) RM0008 78/1134 RM0008 Rev 20 Bits 31:9 Reserved, must be kept at reset value.. Bit 8 DBP: Disable backup domain write protection. In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers. 0: Access to RTC and Backup registers disabled 1: Access to RTC and Backup registers enabled Note: If the HSE divided by 128 is used as the RTC clock, this bit must remain set to 1. Bits 7:5 PLS[2:0]: PVD level selection. These bits are written by software to select the voltage threshold detected by the Power Voltage Detector 000: 2.2V 001: 2.3V 010: 2.4V 011: 2.5V 100: 2.6V 101: 2.7V 110: 2.8V 111: 2.9V Note: Refer to the electrical characteristics of the datasheet for more details. Bit 4 PVDE: Power voltage detector enable. This bit is set and cleared by software. 0: PVD disabled 1: PVD enabled Bit 3 CSBF: Clear standby flag. This bit is always read as 0. 0: No effect 1: Clear the SBF Standby Flag (write). Bit 2 CWUF: Clear wakeup flag. This bit is always read as 0. 0: No effect 1: Clear the WUF Wakeup Flag after 2 System clock cycles. (write) Bit 1 PDDS: Power down deepsleep. This bit is set and cleared by software. It works together with the LPDS bit. 0: Enter Stop mode when the CPU enters Deepsleep. The regulator status depends on the LPDS bit. 1: Enter Standby mode when the CPU enters Deepsleep. Bit 0 LPDS: Low-power deepsleep. This bit is set and cleared by software. It works together with the PDDS bit. 0: Voltage regulator on during Stop mode 1: Voltage regulator in low-power mode during Stop mode

RM0008 Power control (PWR)

5.4.2 Power control/stat us register (PWR_CSR)

Address offset: 0x04 Reset value: 0x0000 0000 (not reset by wakeup from Standby mode) Additional APB cycles are needed to read this register versus a standard APB read. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 Reserved EWUP Reserved PVDO SBF WUF rw r r r Bits 31:9 Reserved, must be kept at reset value. Bit 8 EWUP: Enable WKUP pin This bit is set and cleared by software. 0: WKUP pin is used for general purpose I/O. An event on the WKUP pin does not wakeup the device from Standby mode. 1: WKUP pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin wakes-up the system from Standby mode). Note: This bit is reset by a system Reset. Bits 7:3 Reserved, must be kept at reset value. Bit 2 PVDO: PVD output This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit. 0: VDD/VDDA is higher than the PVD threshold selected with the PLS[2:0] bits. 1: VDD/VDDA is lower than the PVD threshold selected with the PLS[2:0] bits. Note: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after Standby or reset until the PVDE bit is set. Bit 1 SBF: Standby flag This bit is set by hardware and cleared only by a POR/PDR (power on reset/power down reset) or by setting the CSBF bit in the Power control register (PWR_CR) 0: Device has not been in Standby mode 1: Device has been in Standby mode Bit 0 WUF: Wakeup flag This bit is set by hardware and cleared by hardware, by a system reset or by setting the CWUF bit in the Power control register (PWR_CR) 0: No wakeup event occurred 1: A wakeup event was received from the WKUP pin or from the RTC alarm Note: An additional wakeup event is detected if the WKUP pin is enabled (by setting the EWUP bit) when the WKUP pin level is already high.

5.4.3 PWR register map

The following table summarizes the PWR registers. Refer to Table 3 on page 50 for the register boundary addresses. Table 16. PWR register map and reset values

RM0008 Backup registers (BKP)

6 Backup registers (BKP)

6.1 BKP introduction

The backup registers are forty two 16-bit registers for storing 84 bytes of user application data. They are implemented in the backup domain that remains powered on by VBAT when the VDD power is switched off. They are not reset when the device wakes up from Standby mode or by a system reset or power reset. In addition, the BKP control registers are used to manage the Tamper detection feature and RTC calibration. After reset, access to the Backup registers and RTC is disabled and the Backup domain (BKP) is protected against possible parasitic write access. To enable access to the Backup registers and the RTC, proceed as follows:

enable the power and backup interface clocks by setting the PWREN and BKPEN bits in the RCC_APB1ENR register
set the DBP bit the Power Control Register (PWR_CR) to enable access to the Backup registers and RTC.

6.2 BKP main features

20-byte data registers (in medium-density and low-density devices) or 84-byte data registers (in high-density, XL-density and connectivity line devices)
Status/control register for managing tamper detection with interrupt capability
Calibration register for storing the RTC calibration value
Possibility to output the RTC Calibration Clock, RTC Alarm pulse or Second pulse on TAMPER pin PC13 (when this pin is not used for tamper detection)

Backup registers (BKP) RM0008 82/1134 RM0008 Rev 20

6.3 BKP functional description

6.3.1 Tamper detection

The TAMPER pin generates a Tamper detection event when the pin changes from 0 to 1 or from 1 to 0 depending on the TPAL bit in the Backup control register (BKP_CR). A tamper detection event resets all data backup registers. However to avoid losing Tamper events, the signal used for edge detection is logically ANDed with the Tamper enable in order to detect a Tamper event in case it occurs before the TAMPER pin is enabled.

When TPAL=0: If the TAMPER pin is already high before it is enabled (by setting TPE bit), an extra Tamper event is detected as soon as the TAMPER pin is enabled (while there was no rising edge on the TAMPER pin after TPE was set)
When TPAL=1: If the TAMPER pin is already low before it is enabled (by setting the TPE bit), an extra Tamper event is detected as soon as the TAMPER pin is enabled (while there was no falling edge on the TAMPER pin after TPE was set) By setting the TPIE bit in the BKP_CSR register, an interrupt is generated when a Tamper detection event occurs. After a Tamper event has been detected and cleared, the TAMPER pin should be disabled and then re-enabled with TPE before writing to the backup data registers (BKP_DRx) again. This prevents software from writing to the backup data registers (BKP_DRx), while the TAMPER pin value still indicates a Tamper detection. This is equivalent to a level detection on the TAMPER pin. Note: Tamper detection is still active when V DD power is switched off. To avoid unwanted resetting of the data backup registers, the TAMPER pin should be externally tied to the correct level.

6.3.2 RTC calibration

For measurement purposes, the RTC clock with a frequency divided by 64 can be output on the TAMPER pin. This is enabled by setting the CCO bit in the RTC clock calibration register (BKP_RTCCR). The clock can be slowed down by up to 121 ppm by configuring CAL[6:0] bits. For more details about RTC calibration and how to use it to improve timekeeping accuracy, refer to AN2604 "STM32F101xx and STM32F103xx RTC calibration”.

RM0008 Backup registers (BKP)

6.4 BKP registers

Refer to Section 2.2 on page 45 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 6.4.1 Backup data register x (BKP_DRx) (x = 1 ..42) Address offset: 0x04 to 0x28, 0x40 to 0xBC Reset value: 0x0000 0000

6.4.2 RTC clock calibrati on register (BKP_RTCCR)

Address offset: 0x2C Reset value: 0x0000 0000 15 1 4 1 3 1 2 1 1 1 0 987654321 0 D[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 D[15:0] Backup data These bits can be written with user data. Note: The BKP_DRx registers are not reset by a System reset or Power reset or when the device wakes up from Standby mode. They are reset by a Backup Domain reset or by a TAMPER pin event (if the TAMPER pin function is activated).1 5 1 4 1 3 1 2 1 1 1 0 9876543210 Reserved ASOS ASOE CCO CAL[6:0] rw rw rw rw rw rw rw rw rw rw Bits 15:10 Reserved, must be kept at reset value. Bit 9 ASOS: Alarm or second output selection When the ASOE bit is set, the ASOS bit can be used to select whether the signal output on the TAMPER pin is the RTC Second pulse signal or the Alarm pulse signal: 0: RTC Alarm pulse output selected 1: RTC Second pulse output selected Note: This bit is reset only by a Backup domain reset.

Backup registers (BKP) RM0008 84/1134 RM0008 Rev 20

6.4.3 Backup control register (BKP_CR)

Address offset: 0x30 Reset value: 0x0000 0000 Note: Setting the TPAL and TPE bits at the same time is always safe, however resetting both at the same time can generate a spurious Tamper event. For this reason it is recommended to change the TPAL bit only when the TPE bit is reset.

6.4.4 Backup control/stat us register (BKP_CSR)

Address offset: 0x34 Reset value: 0x0000 0000 Bit 8 ASOE: Alarm or second output enable Setting this bit outputs either the RTC Alarm pulse signal or the Second pulse signal on the TAMPER pin depending on the ASOS bit. The output pulse duration is one RTC clock period. The TAMPER pin must not be enabled while the ASOE bit is set. Note: This bit is reset only by a Backup domain reset. Bit 7 CCO: Calibration clock output 0: No effect 1: Setting this bit outputs the RTC clock with a frequency divided by 64 on the TAMPER pin. The TAMPER pin must not be enabled while the CCO bit is set in order to avoid unwanted Tamper detection. Note: This bit is reset when the V DD supply is powered off. Bit 6:0 CAL[6:0]: Calibration value This value indicates the number of clock pulses that will be ignored every 2^20 clock pulses. This allows the calibration of the RTC, slowing down the clock by steps of 1000000/2^20 PPM. The clock of the RTC can be slowed down from 0 to 121PPM. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TPAL TPE rw rw Bits 15:2 Reserved, must be kept at reset value. Bit 1 TPAL: TAMPER pin active level 0: A high level on the TAMPER pin resets all data backup registers (if TPE bit is set). 1: A low level on the TAMPER pin resets all data backup registers (if TPE bit is set). Bit 0 TPE: TAMPER pin enable 0: The TAMPER pin is free for general purpose I/O 1: Tamper alternate I/O function is activated. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TIF TEF Reserved TPIE CTI CTE rr r w w w

6.4.5 BKP register map

Bits 15:10 Reserved, must be kept at reset value. Note: This bit is reset only by a system reset and wakeup from Standby mode. Bits 7:3 Reserved, must be kept at reset value. Note: A Tamper interrupt does not wake up the core from low-power modes. This bit is reset only by a system reset and wakeup from Standby mode. This bit is write only, and is always read as 0. 1: Clear the Tamper interrupt and the TIF Tamper interrupt flag. This bit is write only, and is always read as 0. Table 17. BKP register map and reset values

Table 17. BKP register map and reset values (continued)

Refer to Table 3 on page 50 for the register boundary addresses.

Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 90/1134 RM0008 Rev 20 control (RCC) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This Section applies to low-, medium-, high- and XL-density STM32F10xxx devices. Connectivity line devices are discussed in a separate section (refer to Connectivity line devices: reset and clock control (RCC)).

7.1 Reset

There are three types of reset, defined as system reset, power reset and backup domain reset.

7.1.1 System reset

A system reset sets all registers to their reset values except the reset flags in the clock controller CSR register and the registers in the Backup domain (see Figure 4). A system reset is generated when one of the following events occurs: 1. A low level on the NRST pin (external reset) 2. Window watchdog end of count condition (WWDG reset) 3. Independent watchdog end of count condition (IWDG reset) 4. A software reset (SW reset) (see Software reset) 5. Low-power management reset (see Low-power management reset) The reset source can be identified by checking the reset flags in the Control/Status register, RCC_CSR (see Section 7.3.10: Control/status register (RCC_CSR)). Software reset The SYSRESETREQ bit in Cortex®-M3 Application Interrupt and Reset Control Register must be set to force a software reset on the device. Refer to the STM32F10xxx Cortex®-M3 programming manual (see Related documents) for more details.

Reset generated when entering Standby mode:

is reset instead of entering Standby mode.

Reset when entering Stop mode:

reset instead of entering Stop mode.

7.1.2 Power reset

Power-on/power-down reset (POR/PDR reset)
When exiting Standby mode

0x0000_0004 in the memory map. the NRST pin is asserted low. Figure 7. Simplified diagram of the reset circuit

Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 92/1134 RM0008 Rev 20

7.1.3 Backup domain reset

The backup domain has two specific resets that affect only the backup domain (see Figure 4). A backup domain reset is generated when one of the following events occurs: 1. Software reset, triggered by setting the BDRST bit in the Backup domain control register (RCC_BDCR). 2. V DD or VBAT power on, if both supplies have previously been powered off.

7.2 Clocks

Three different clock sources can be used to drive the system clock (SYSCLK):

HSI oscillator clock
HSE oscillator clock
PLL clock The devices have the following two secondary clock sources:
40 kHz low speed internal RC (LSI RC), which drives the independent watchdog and optionally the RTC used for Auto-wakeup from Stop/Standby mode.
32.768 kHz low speed external crystal (LSE crystal), which optionally drives the real-time clock (RTCCLK) Each clock source can be switched on or off independently when it is not used, to optimize power consumption.

Figure 8. Clock tree

When the HSI is used as a PLL clock input, the maxi mum system clock frequency that can be achieved is
For full details about the internal and external cl ock source characteristics refer to the “Electrical

characteristics” section in your device datasheet. the clock of the High Speed domain (APB2) divided by 2, 4, 6 or 8. The Flash memory programming interface clock (FLITFCLK) is always the HSI clock.

if the APB prescaler is 1, the timer clock fr equencies are set to the same frequency as

that of the APB domain to which the timers are connected.

otherwise, they are set to twice (×2) the frequency of the APB domain to which the

Cortex-M3 r1p1 Technical Reference Manual (TRM).

7.2.1 HSE clock

HSE external crystal/ceramic resonator
HSE user external clock The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.

Figure 9. HSE/ LSE clock sources

RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) 122 External source (HSE bypass) In this mode, an external clock source must be provided. It can have a frequency of up to 25 MHz. You select this mode by setting the HSEBYP and HSEON bits in the Clock control register (RCC_CR). The external clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC_IN pin while the OSC_OUT pin should be left hi-Z. See Figure 9. External crystal/ceramic resonator (HSE crystal) The 4 to 16 MHz external oscillator has the advantage of producing a very accurate rate on the main clock. The associated hardware configuration is shown in Figure 9. Refer to the electrical characteristics section of the datasheet for more details. The HSERDY flag in the Clock control register (RCC_CR) indicates if the high-speed external oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt register (RCC_CIR). The HSE Crystal can be switched on and off using the HSEON bit in the Clock control register (RCC_CR).

7.2.2 HSI clock

The HSI clock signal is generated from an internal 8 MHz RC Oscillator and can be used directly as a system clock or divided by 2 to be used as PLL input. The HSI RC oscillator has the advantage of providing a clock source at low cost (no external components). It also has a faster startup time than the HSE crystal oscillator however, even with calibration the frequency is less accurate than an external crystal oscillator or ceramic resonator. Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at TA=25°C. After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the Clock control register (RCC_CR). If the application is subject to voltage or temperature variations this may affect the RC oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0] bits in the Clock control register (RCC_CR). The HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI RC is stable or not. At startup, the HSI RC output clock is not released until this bit is set by hardware. The HSI RC can be switched on and off using the HSION bit in the Clock control register (RCC_CR). The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal oscillator fails. Refer to Section 7.2.7: Clock security system (CSS).

Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 96/1134 RM0008 Rev 20

7.2.3 PLL

The internal PLL can be used to multiply the HSI RC output or HSE crystal output clock frequency. Refer to Figure 8 and Clock control register (RCC_CR). The PLL configuration (selection of HSI oscillator divided by 2 or HSE oscillator for PLL input clock, and multiplication factor) must be done before enabling the PLL. Once the PLL enabled, these parameters cannot be changed. An interrupt can be generated when the PLL is ready if enabled in the Clock interrupt register (RCC_CIR). If the USB interface is used in the application, the PLL must be programmed to output 48 or 72 MHz. This is needed to provide a 48 MHz USBCLK.

7.2.4 LSE clock

The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the advantage providing a low-power but highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions. The LSE crystal is switched on and off using the LSEON bit in Backup domain control register (RCC_BDCR). The LSERDY flag in the Backup domain control register (RCC_BDCR) indicates if the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt register (RCC_CIR). External source (LSE bypass) In this mode, an external clock source must be provided. It can have a frequency of up to 1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the Backup domain control register (RCC_BDCR). The external clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be left Hi-Z. See Figure 9.

7.2.5 LSI clock

RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) 122 LSI calibration The frequency dispersion of the Low Speed Internal RC (LSI) oscillator can be calibrated to have accurate RTC time base and/or IWDG timeout (when LSI is used as clock source for these peripherals) with an acceptable accuracy. This calibration is performed by measuring the LSI clock frequency with respect to TIM5 input clock (TIM5CLK). According to this measurement done at the precision of the HSE oscillator, the software can adjust the programmable 20-bit prescaler of the RTC to get an accurate time base or can compute accurate IWDG timeout. Use the following procedure to calibrate the LSI: 1. Enable TIM5 timer and configure channel4 in input capture mode 2. Set the TIM5CH4_IREMAP bit in the AFIO _MAPR register to connect the LSI clock internally to TIM5 channel4 input capture for calibration purpose. 3. Measure the frequency of LSI clock us ing the TIM5 Capture/compare 4 event or interrupt. 4. Use the measured LSI frequency to update the 20-bit prescaler of the RTC depending on the desired time base and/or to compute the IWDG timeout.

7.2.6 System clock (SYSCLK) selection

After a system reset, the HSI oscillator is selected as system clock. When a clock source is used directly or through the PLL as system clock, it is not possible to stop it. A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. Status bits in the Clock control register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently used as system clock.

7.2.7 Clock security system (CSS)

Clock Security System can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped. If a failure is detected on the HSE clock, the HSE oscillator is automatically disabled, a clock failure event is sent to the break input of the advanced-control timers (TIM1 and TIM8) and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex®-M3 NMI (Non-Maskable Interrupt) exception vector. Note: Once the CSS is enabled and if the HSE cloc k fails, the CSS interrupt occurs and an NMI is automatically generated. The NMI will be executed indefinitely unless the CSS interrupt pending bit is cleared. As a consequence, in the NMI ISR user must clear the CSS interrupt by setting the CSSC bit in the Clock interrupt register (RCC_CIR). If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is used as PLL input clock, and the PLL clock is used as system clock), a detected failure causes a switch of the system clock to the HSI oscillator and the disabling of the HSE oscillator. If the HSE clock (divided or not) is the clock entry of the PLL used as system clock when the failure occurs, the PLL is disabled too.

Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 98/1134 RM0008 Rev 20

7.2.8 RTC clock

The RTCCLK clock source can be either the HSE/128, LSE or LSI clocks. This is selected by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR). This selection cannot be modified without resetting the Backup domain. The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not. Consequently:

If LSE is selected as RTC clock: – The RTC continues to work even if the V DD supply is switched off, provided the VBAT supply is maintained.
If LSI is selected as Auto-Wakeup unit (AWU) clock: – The AWU state is not guaranteed if the V DD supply is powered off. Refer to Section 7.2.5: LSI clock for more details on LSI calibration.
If the HSE clock divided by 128 is used as the RTC clock: – The RTC state is not guaranteed if the V DD supply is powered off or if the internal voltage regulator is powered off (removing power from the 1.8 V domain). – The DPB bit (disable backup domain write protection) in the Power controller register must be set to 1 (refer to Section 5.4.1: Power control register (PWR_CR)).

7.2.9 Watchdog clock

If the Independent watchdog (IWDG) is started by either hardware option or software access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator temporization, the clock is provided to the IWDG.

7.2.10 Clock-out capability

The microcontroller clock output (MCO) capability allows the clock to be output onto the external MCO pin. The configuration registers of the corresponding GPIO port must be programmed in alternate function mode. One of 4 clock signals can be selected as the MCO clock.

SYSCLK
HSI
HSE
PLL clock divided by 2 The selection is controlled by the MCO[2:0] bits of the Clock configuration register (RCC_CFGR).

RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) 122

7.3 RCC registers

Refer to Section 2.2 on page 45 for a list of abbreviations used in register descriptions.

7.3.1 Clock control register (RCC_CR)

Address offset: 0x00 Reset value: 0x0000 XX83 where X is undefined. Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PLL RDY PLLON Reserved CSS ON HSE BYP HSE RDY HSE ON rr w r w r wrr w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HSICAL[7:0] HSITRIM[4:0] Res. HSI RDY HSION rrrrrrr r r w r w r w r w r w rr w Bits 31:26 Reserved, must be kept at reset value. Bit 25 PLLRDY: PLL clock ready flag Set by hardware to indicate that the PLL is locked. 0: PLL unlocked 1: PLL locked Bit 24 PLLON: PLL enable Set and cleared by software to enable PLL. Cleared by hardware when entering Stop or Standby mode. This bit can not be reset if the PLL clock is used as system clock or is selected to become the system clock. 0: PLL OFF 1: PLL ON Bits 23:20 Reserved, must be kept at reset value. Bit 19 CSSON: Clock security system enable Set and cleared by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. 0: Clock detector OFF 1: Clock detector ON (Clock detector ON if the HSE oscillator is ready , OFF if not). Bit 18 HSEBYP: External high-speed clock bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. 0: external 4-16 MHz oscillator not bypassed 1: external 4-16 MHz oscillator bypassed with external clock Bit 17 HSERDY: External high-speed clock ready flag Set by hardware to indicate that the HSE oscillator is stable. This bit needs 6 cycles of the HSE oscillator clock to fall down after HSEON reset. 0: HSE oscillator not ready 1: HSE oscillator ready

Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 100/1134 RM0008 Rev 20 Bit 16 HSEON: HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. 0: HSE oscillator OFF 1: HSE oscillator ON Bits 15:8 HSICAL[7:0]: Internal high-speed clock calibration These bits are initialized automatically at startup. Bits 7:3 HSITRIM[4:0]: Internal high-speed clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the internal HSI RC. The default value is 16, which, when added to the HSICAL value, should trim the HSI to 8 MHz ± 1%. The trimming step (F hsitrim) is around 40 kHz between two consecutive HSICAL steps. Bit 2 Reserved, must be kept at reset value. Bit 1 HSIRDY: Internal high-speed clock ready flag Set by hardware to indicate that internal 8 MHz RC oscillator is stable. After the HSION bit is cleared, HSIRDY goes low after 6 internal 8 MHz RC oscillator clock cycles. 0: internal 8 MHz RC oscillator not ready 1: internal 8 MHz RC oscillator ready Bit 0 HSION: Internal high-speed clock enable Set and cleared by software. Set by hardware to force the internal 8 MHz RC oscillator ON when leaving Stop or Standby mode or in case of failure of the external 4-16 MHz oscillator used directly or indirectly as system clock. This bit cannot be reset if the internal 8 MHz RC is used directly or indirectly as system clock or is selected to become the system clock. 0: internal 8 MHz RC oscillator OFF 1: internal 8 MHz RC oscillator ON

RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) 122

7.3.2 Clock configurati on register (RCC_CFGR)

Address offset: 0x04 Reset value: 0x0000 0000 Access: 0 ≤ wait state ≤ 2, word, half-word and byte access 1 or 2 wait states inserted only if the access occurs during clock source switch. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved MCO[2:0] Res. USB PRE PLLMUL[3:0] PLL XTPRE PLL SRC rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCPRE[1:0] PPRE2[2:0] PPRE1[2:0] HPRE[3:0] SWS[1:0] SW[1:0] rw rw rw rw rw rw rw rw rw rw rw rw r r rw rw Bits 31:27 Reserved, must be kept at reset value. Bits 26:24 MCO: Microcontroller clock output Set and cleared by software. 0xx: No clock 100: System clock (SYSCLK) selected 101: HSI clock selected 110: HSE clock selected 111: PLL clock divided by 2 selected Note: This clock output may have some trunca ted cycles at startup or during MCO clock source switching. When the System Clock is selected to output to the MCO pin, make sure that this clock does not exceed 50 MHz (the maximum IO speed). Bit 22 USBPRE: USB prescaler Set and cleared by software to generate 48 MHz USB clock. This bit must be valid before enabling the USB clock in the RCC_APB1ENR register. This bit can’t be reset if the USB clock is enabled. 0: PLL clock is divided by 1.5 1: PLL clock is not divided

Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 102/1134 RM0008 Rev 20 Bits 21:18 PLLMUL: PLL multiplication factor These bits are written by software to define the PLL multiplication factor. These bits can be written only when PLL is disabled. Caution: The PLL output frequency must not exceed 72 MHz. 0000: PLL input clock x 2 0001: PLL input clock x 3 0010: PLL input clock x 4 0011: PLL input clock x 5 0100: PLL input clock x 6 0101: PLL input clock x 7 0110: PLL input clock x 8 0111: PLL input clock x 9 1000: PLL input clock x 10 1001: PLL input clock x 11 1010: PLL input clock x 12 1011: PLL input clock x 13 1100: PLL input clock x 14 1101: PLL input clock x 15 1110: PLL input clock x 16 1111: PLL input clock x 16 Bit 17 PLLXTPRE: HSE divider for PLL entry Set and cleared by software to divide HSE before PLL entry. This bit can be written only when PLL is disabled. 0: HSE clock not divided 1: HSE clock divided by 2 Bit 16 PLLSRC: PLL entry clock source Set and cleared by software to select PLL clock source. This bit can be written only when PLL is disabled. 0: HSI oscillator clock / 2 selected as PLL input clock 1: HSE oscillator clock selected as PLL input clock Bits 15:14 ADCPRE: ADC prescaler Set and cleared by software to select the frequency of the clock to the ADCs. 00: PCLK2 divided by 2 01: PCLK2 divided by 4 10: PCLK2 divided by 6 11: PCLK2 divided by 8 Bits 13:11 PPRE2: APB high-speed prescaler (APB2) Set and cleared by software to control the division factor of the APB high-speed clock (PCLK2). 0xx: HCLK not divided 100: HCLK divided by 2 101: HCLK divided by 4 110: HCLK divided by 8 111: HCLK divided by 16

RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) 122 Bits 10:8 PPRE1: APB low-speed prescaler (APB1) Set and cleared by software to control the division factor of the APB low-speed clock (PCLK1). Warning: the software has to set correctly these bits to not exceed 36 MHz on this domain. 0xx: HCLK not divided 100: HCLK divided by 2 101: HCLK divided by 4 110: HCLK divided by 8 111: HCLK divided by 16 Bits 7:4 HPRE: AHB prescaler Set and cleared by software to control the division factor of the AHB clock. 0xxx: SYSCLK not divided 1000: SYSCLK divided by 2 1001: SYSCLK divided by 4 1010: SYSCLK divided by 8 1011: SYSCLK divided by 16 1100: SYSCLK divided by 64 1101: SYSCLK divided by 128 1110: SYSCLK divided by 256 1111: SYSCLK divided by 512 Note: The prefetch buffer must be kept on when using a prescaler different from 1 on the AHB clock. Refer to Reading the Flash memory section for more details. Bits 3:2 SWS: System clock switch status Set and cleared by hardware to indicate which clock source is used as system clock. 00: HSI oscillator used as system clock 01: HSE oscillator used as system clock 10: PLL used as system clock 11: not applicable Bits 1:0 SW: System clock switch Set and cleared by software to select SYSCLK source. Set by hardware to force HSI selection when leaving Stop and Standby mode or in case of failure of the HSE oscillator used directly or indirectly as system clock (if the Clock Security System is enabled). 00: HSI selected as system clock 01: HSE selected as system clock 10: PLL selected as system clock 11: not allowed

Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 104/1134 RM0008 Rev 20

7.3.3 Clock interrupt register (RCC_CIR)

Address offset: 0x08 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved CSSC Reserved PLL RDYC HSE RDYC HSI RDYC LSE RDYC LSI RDYC ww w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PLL RDYIE HSE RDYIE HSI RDYIE LSE RDYIE LSI RDYIE CSSF Reserved PLL RDYF HSE RDYF HSI RDYF LSE RDYF LSI RDYF rw rw rw rw rw r r r r r r Bits 31:24 Reserved, must be kept at reset value. Bit 23 CSSC: Clock security system interrupt clear This bit is set by software to clear the CSSF flag. 0: No effect 1: Clear CSSF flag Bits 22:21 Reserved, must be kept at reset value. Bit 20 PLLRDYC: PLL ready interrupt clear This bit is set by software to clear the PLLRDYF flag. 0: No effect 1: PLLRDYF cleared Bit 19 HSERDYC: HSE ready interrupt clear This bit is set by software to clear the HSERDYF flag. 0: No effect 1: HSERDYF cleared Bit 18 HSIRDYC: HSI ready interrupt clear This bit is set software to clear the HSIRDYF flag. 0: No effect 1: HSIRDYF cleared Bit 17 LSERDYC: LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag. 0: No effect 1: LSERDYF cleared Bit 16 LSIRDYC: LSI ready interrupt clear This bit is set by software to clear the LSIRDYF flag. 0: No effect 1: LSIRDYF cleared Bits 15:13 Reserved, must be kept at reset value. Bit 12 PLLRDYIE: PLL ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL lock. 0: PLL lock interrupt disabled 1: PLL lock interrupt enabled

RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) 122 Bit 11 HSERDYIE: HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the external 4-16 MHz oscillator stabilization. 0: HSE ready interrupt disabled 1: HSE ready interrupt enabled Bit 10 HSIRDYIE: HSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the internal 8 MHz RC oscillator stabilization. 0: HSI ready interrupt disabled 1: HSI ready interrupt enabled Bit 9 LSERDYIE: LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the external 32 kHz oscillator stabilization. 0: LSE ready interrupt disabled 1: LSE ready interrupt enabled Bit 8 LSIRDYIE: LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by internal RC 40 kHz oscillator stabilization. 0: LSI ready interrupt disabled 1: LSI ready interrupt enabled Bit 7 CSSF: Clock security system interrupt flag Set by hardware when a failure is detected in the external 4-16 MHz oscillator. Cleared by software setting the CSSC bit. 0: No clock security interrupt caused by HSE clock failure 1: Clock security interrupt caused by HSE clock failure Bits 6:5 Reserved, must be kept at reset value. Bit 4 PLLRDYF: PLL ready interrupt flag Set by hardware when the PLL locks and PLLRDYDIE is set. Cleared by software setting the PLLRDYC bit. 0: No clock ready interrupt caused by PLL lock 1: Clock ready interrupt caused by PLL lock Bit3 HSERDYF: HSE ready interrupt flag Set by hardware when External High Speed clock becomes stable and HSERDYDIE is set. Cleared by software setting the HSERDYC bit. 0: No clock ready interrupt caused by the external 4-16 MHz oscillator 1: Clock ready interrupt caused by the external 4-16 MHz oscillator

Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 106/1134 RM0008 Rev 20

7.3.4 APB2 peripheral rese t register (RCC_APB2RSTR)

Address offset: 0x0C Reset value: 0x00000 0000 Access: no wait state, word, half-word and byte access Bit 2 HSIRDYF: HSI ready interrupt flag Set by hardware when the Internal High Speed clock becomes stable and HSIRDYDIE is set. Cleared by software setting the HSIRDYC bit. 0: No clock ready interrupt caused by the internal 8 MHz RC oscillator 1: Clock ready interrupt caused by the internal 8 MHz RC oscillator Bit 1 LSERDYF: LSE ready interrupt flag Set by hardware when the External Low Speed clock becomes stable and LSERDYDIE is set. Cleared by software setting the LSERDYC bit. 0: No clock ready interrupt caused by the external 32 kHz oscillator 1: Clock ready interrupt caused by the external 32 kHz oscillator Bit 0 LSIRDYF: LSI ready interrupt flag Set by hardware when the internal low speed clock becomes stable and LSIRDYDIE is set. Cleared by software setting the LSIRDYC bit. 0: No clock ready interrupt caused by the internal RC 40 kHz oscillator 1: Clock ready interrupt caused by the internal RC 40 kHz oscillator 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved TIM11 RST TIM10 RST TIM9 RST Reserved rw rw rw 1 5 1 4 1 3 1 2 1 1 1 0 9 87654321 0 ADC3 RST USART1 RST TIM8 RST SPI1 RST TIM1 RST ADC2 RST ADC1 RST IOPG RST IOPF RST IOPE RST IOPD RST IOPC RST IOPB RST IOPA RST Res. AFIO RST rw rw rw rw rw rw rw rw rw rw rw rw rw rw Res. rw Bits 31:22 Reserved, must be kept at reset value. Bit 21 TIM11RST: TIM11 timer reset Set and cleared by software. 0: No effect 1: Reset TIM11 timer Bit 20 TIM10RST: TIM10 timer reset Set and cleared by software. 0: No effect 1: Reset TIM10 timer Bit 19 TIM9RST: TIM9 timer reset Set and cleared by software. 0: No effect 1: Reset TIM9 timer Bits 18:16 Reserved, always read as 0.

RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) 122 Bit 15 ADC3RST: ADC3 interface reset Set and cleared by software. 0: No effect 1: Reset ADC3 interface Bit 14 USART1RST: USART1 reset Set and cleared by software. 0: No effect 1: Reset USART1 Bit 13 TIM8RST: TIM8 timer reset Set and cleared by software. 0: No effect 1: Reset TIM8 timer Bit 12 SPI1RST: SPI1 reset Set and cleared by software. 0: No effect 1: Reset SPI1 Bit 11 TIM1RST: TIM1 timer reset Set and cleared by software. 0: No effect 1: Reset TIM1 timer Bit 10 ADC2RST: ADC 2 interface reset Set and cleared by software. 0: No effect 1: Reset ADC 2 interface Bit 9 ADC1RST: ADC 1 interface reset Set and cleared by software. 0: No effect 1: Reset ADC 1 interface Bit 8 IOPGRST: IO port G reset Set and cleared by software. 0: No effect 1: Reset IO port G Bit 7 IOPFRST: IO port F reset Set and cleared by software. 0: No effect 1: Reset IO port F Bit 6 IOPERST: IO port E reset Set and cleared by software. 0: No effect 1: Reset IO port E Bit 5 IOPDRST: IO port D reset Set and cleared by software. 0: No effect 1: Reset IO port D

Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 108/1134 RM0008 Rev 20 Bit 4 IOPCRST: IO port C reset Set and cleared by software. 0: No effect 1: Reset IO port C Bit 3 IOPBRST: IO port B reset Set and cleared by software. 0: No effect 1: Reset IO port B Bit 2 IOPARST: IO port A reset Set and cleared by software. 0: No effect 1: Reset IO port A Bit 1 Reserved, must be kept at reset value. Bit 0 AFIORST: Alternate function IO reset Set and cleared by software. 0: No effect 1: Reset Alternate Function

RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) 122

7.3.5 APB1 peripheral rese t register (RCC_APB1RSTR)

Address offset: 0x10 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved DAC RST PWR RST BKP RST Res. CAN RST Res. USB RST I2C2 RST I2C1 RST UART5 RST UART4 RST USART RST USART RST Res. rw rw rw rw rw rw rw rw rw rw rw 1 5 1 4 1 3 1 2 1 1 1 0 9 876543 2 1 0 SPI3 RST SPI2 RST Reserved WWDG RST Reserved TIM14 RST TIM13 RST TIM12 RST TIM7 RST TIM6 RST TIM5 RST TIM4 RST TIM3 RST TIM2 RST rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:30 Reserved, must be kept at reset value. Bit 29 DACRST: DAC interface reset Set and cleared by software. 0: No effect 1: Reset DAC interface Bit 28 PWRRST: Power interface reset Set and cleared by software. 0: No effect 1: Reset power interface Bit 27 BKPRST: Backup interface reset Set and cleared by software. 0: No effect 1: Reset backup interface Bit 26 Reserved, must be kept at reset value. Bit 25 CANRST: CAN reset Set and cleared by software. 0: No effect 1: Reset CAN Bit 24 Reserved, always read as 0. Bit 23 USBRST: USB reset Set and cleared by software. 0: No effect 1: Reset USB Bit 22 I2C2RST: I2C2 reset Set and cleared by software. 0: No effect 1: Reset I2C2 Bit 21 I2C1RST: I2C1 reset Set and cleared by software. 0: No effect 1: Reset I2C1

Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 110/1134 RM0008 Rev 20 Bit 20 UART5RST: USART5 reset Set and cleared by software. 0: No effect 1: Reset USART5 Bit 19 UART4RST: USART4 reset Set and cleared by software. 0: No effect 1: Reset USART4 Bit 18 USART3RST: USART3 reset Set and cleared by software. 0: No effect 1: Reset USART3 Bit 17 USART2RST: USART2 reset Set and cleared by software. 0: No effect 1: Reset USART2 Bit 16 Reserved, must be kept at reset value. Bit 15 SPI3RST: SPI3 reset Set and cleared by software. 0: No effect 1: Reset SPI3 Bit 14 SPI2RST: SPI2 reset Set and cleared by software. 0: No effect 1: Reset SPI2 Bits 13:12 Reserved, must be kept at reset value. Bit 11 WWDGRST: Window watchdog reset Set and cleared by software. 0: No effect 1: Reset window watchdog Bits 10:9 Reserved, must be kept at reset value. Bit 8 TIM14RST: TIM14 timer reset Set and cleared by software. 0: No effect 1: Reset TIM14 Bit 7 TIM13RST: TIM13 timer reset Set and cleared by software. 0: No effect 1: Reset TIM13 Bit 6 TIM12RST: TIM12 timer reset Set and cleared by software. 0: No effect 1: Reset TIM12

RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) 122

7.3.6 AHB peripheral clock en able register (RCC_AHBENR)

Address offset: 0x14 Reset value: 0x0000 0014 Access: no wait state, word, half-word and byte access Note: When the peripheral clock is not active, the peripheral register values may not be readable by software and the returned value is always 0x0. Bit 5 TIM7RST: TIM7 timer reset Set and cleared by software. 0: No effect 1: Reset TIM7 Bit 4 TIM6RST: TIM6 timer reset Set and cleared by software. 0: No effect 1: Reset TIM6 Bit 3 TIM5RST: TIM5 timer reset Set and cleared by software. 0: No effect 1: Reset TIM5 Bit 2 TIM4RST: TIM4 timer reset Set and cleared by software. 0: No effect 1: Reset TIM4 Bit 1 TIM3RST: TIM3 timer reset Set and cleared by software. 0: No effect 1: Reset TIM3 Bit 0 TIM2RST: TIM2 timer reset Set and cleared by software. 0: No effect 1: Reset TIM2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SDIO EN Res. FSMC EN Res. CRCE N Res. FLITF EN Res. SRAM EN DMA2 EN DMA1 EN rw rw rw rw rw rw rw Bits 31:11 Reserved, must be kept at reset value. Bit 10 SDIOEN: SDIO clock enable Set and cleared by software. 0: SDIO clock disabled 1: SDIO clock enabled Bits 9 Reserved, always read as 0.

Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 112/1134 RM0008 Rev 20

7.3.7 APB2 peripheral clock en able register (RCC_APB2ENR)

Address: 0x18 Reset value: 0x0000 0000 Access: word, half-word and byte access No wait states, except if the access occurs while an access to a peripheral in the APB2 domain is on going. In this case, wait states are inserted until the access to APB2 peripheral is finished. Note: When the peripheral clock is not active, the peripheral register values may not be readable by software and the returned value is always 0x0. Bit 8 FSMCEN: FSMC clock enable Set and cleared by software. 0: FSMC clock disabled 1: FSMC clock enabled Bit 7 Reserved, always read as 0. Bit 6 CRCEN: CRC clock enable Set and cleared by software. 0: CRC clock disabled 1: CRC clock enabled Bit 5 Reserved, must be kept at reset value. Bit 4 FLITFEN: FLITF clock enable Set and cleared by software to disable/enable FLITF clock during Sleep mode. 0: FLITF clock disabled during Sleep mode 1: FLITF clock enabled during Sleep mode Bit 3 Reserved, must be kept at reset value. Bit 2 SRAMEN: SRAM interface clock enable Set and cleared by software to disable/enable SRAM interface clock during Sleep mode. 0: SRAM interface clock disabled during Sleep mode. 1: SRAM interface clock enabled during Sleep mode Bit 1 DMA2EN: DMA2 clock enable Set and cleared by software. 0: DMA2 clock disabled 1: DMA2 clock enabled Bit 0 DMA1EN: DMA1 clock enable Set and cleared by software. 0: DMA1 clock disabled 1: DMA1 clock enabled

RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) 122 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved TIM11 EN TIM10 EN TIM9 EN Reserved rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADC3 EN USART 1EN TIM8 EN SPI1 EN TIM1 EN ADC2 EN ADC1 EN IOPG EN IOPF EN IOPE EN IOPD EN IOPC EN IOPB EN IOPA EN Res. AFIO EN rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:22 Reserved, must be kept at reset value. Bit 21 TIM11EN: TIM11 timer clock enable Set and cleared by software. 0: TIM11 timer clock disabled 1: TIM11 timer clock enabled Bit 20 TIM10EN: TIM10 timer clock enable Set and cleared by software. 0: TIM10 timer clock disabled 1: TIM10 timer clock enabled Bit 19 TIM9EN: TIM9 timer clock enable Set and cleared by software. 0: TIM9 timer clock disabled 1: TIM9 timer clock enabled Bits 18:16 Reserved, always read as 0. Bit 15 ADC3EN: ADC3 interface clock enable Set and cleared by software. 0: ADC3 interface clock disabled 1: ADC3 interface clock enabled Bit 14 USART1EN: USART1 clock enable Set and cleared by software. 0: USART1 clock disabled 1: USART1 clock enabled Bit 13 TIM8EN: TIM8 Timer clock enable Set and cleared by software. 0: TIM8 timer clock disabled 1: TIM8 timer clock enabled Bit 12 SPI1EN: SPI1 clock enable Set and cleared by software. 0: SPI1 clock disabled 1: SPI1 clock enabled Bit 11 TIM1EN: TIM1 timer clock enable Set and cleared by software. 0: TIM1 timer clock disabled 1: TIM1 timer clock enabled Bit 10 ADC2EN: ADC 2 interface clock enable Set and cleared by software. 0: ADC 2 interface clock disabled 1: ADC 2 interface clock enabled

Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 114/1134 RM0008 Rev 20 Bit 9 ADC1EN: ADC 1 interface clock enable Set and cleared by software. 0: ADC 1 interface disabled 1: ADC 1 interface clock enabled Bit 8 IOPGEN: IO port G clock enable Set and cleared by software. 0: IO port G clock disabled 1: IO port G clock enabled Bit 7 IOPFEN: IO port F clock enable Set and cleared by software. 0: IO port F clock disabled 1: IO port F clock enabled Bit 6 IOPEEN: IO port E clock enable Set and cleared by software. 0: IO port E clock disabled 1: IO port E clock enabled Bit 5 IOPDEN: IO port D clock enable Set and cleared by software. 0: IO port D clock disabled 1: IO port D clock enabled Bit 4 IOPCEN: IO port C clock enable Set and cleared by software. 0: IO port C clock disabled 1: IO port C clock enabled Bit 3 IOPBEN: IO port B clock enable Set and cleared by software. 0: IO port B clock disabled 1: IO port B clock enabled Bit 2 IOPAEN: IO port A clock enable Set and cleared by software. 0: IO port A clock disabled 1: IO port A clock enabled Bit 1 Reserved, must be kept at reset value. Bit 0 AFIOEN: Alternate function IO clock enable Set and cleared by software. 0: Alternate Function IO clock disabled 1: Alternate Function IO clock enabled

RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) 122

7.3.8 APB1 peripheral clock en able register (RCC_APB1ENR)

Address: 0x1C Reset value: 0x0000 0000 Access: word, half-word and byte access No wait state, except if the access occurs while an access to a peripheral on APB1 domain is on going. In this case, wait states are inserted until this access to APB1 peripheral is finished. Note: When the peripheral clock is not active, the peripheral register values may not be readable by software and the returned value is always 0x0. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved DAC EN PWR EN BKP EN Res. CAN EN Res. USB EN I2C2 EN I2C1 EN UART5 EN UART4 EN USART3 EN USART2 EN Res. rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPI3 EN SPI2 EN Reserved WWD GEN Reserved TIM14 EN TIM13 EN TIM12 EN TIM7 EN TIM6 EN TIM5 EN TIM4 EN TIM3 EN TIM2 EN rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:30 Reserved, must be kept at reset value. Bit 29 DACEN: DAC interface clock enable Set and cleared by software. 0: DAC interface clock disabled 1: DAC interface clock enable Bit 28 PWREN: Power interface clock enable Set and cleared by software. 0: Power interface clock disabled 1: Power interface clock enable Bit 27 BKPEN: Backup interface clock enable Set and cleared by software. 0: Backup interface clock disabled 1: Backup interface clock enabled Bit 26 Reserved, must be kept at reset value. Bit 25 CANEN: CAN clock enable Set and cleared by software. 0: CAN clock disabled 1: CAN clock enabled Bit 24 Reserved, always read as 0. Bit 23 USBEN: USB clock enable Set and cleared by software. 0: USB clock disabled 1: USB clock enabled

Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 116/1134 RM0008 Rev 20 Bit 22 I2C2EN: I2C2 clock enable Set and cleared by software. 0: I2C2 clock disabled 1: I2C2 clock enabled Bit 21 I2C1EN: I2C1 clock enable Set and cleared by software. 0: I2C1 clock disabled 1: I2C1 clock enabled Bit 20 UART5EN: USART5 clock enable Set and cleared by software. 0: USART5 clock disabled 1: USART5 clock enabled Bit 19 UART4EN: USART4 clock enable Set and cleared by software. 0: USART4 clock disabled 1: USART4 clock enabled Bit 18 USART3EN: USART3 clock enable Set and cleared by software. 0: USART3 clock disabled 1: USART3 clock enabled Bit 17 USART2EN: USART2 clock enable Set and cleared by software. 0: USART2 clock disabled 1: USART2 clock enabled Bits 16 Reserved, always read as 0. Bit 15 SPI3EN: SPI 3 clock enable Set and cleared by software. 0: SPI 3 clock disabled 1: SPI 3 clock enabled Bit 14 SPI2EN: SPI2 clock enable Set and cleared by software. 0: SPI2 clock disabled 1: SPI2 clock enabled Bits 13:12 Reserved, must be kept at reset value. Bit 11 WWDGEN: Window watchdog clock enable Set and cleared by software. 0: Window watchdog clock disabled 1: Window watchdog clock enabled Bits 10:9 Reserved, must be kept at reset value. Bit 8 TIM14EN: TIM14 timer clock enable Set and cleared by software. 0: TIM14 clock disabled 1: TIM14 clock enabled

RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) 122 Bit 7 TIM13EN: TIM13 timer clock enable Set and cleared by software. 0: TIM13 clock disabled 1: TIM13 clock enabled Bit 6 TIM12EN: TIM12 timer clock enable Set and cleared by software. 0: TIM12 clock disabled 1: TIM12 clock enabled Bit 5 TIM7EN: TIM7 timer clock enable Set and cleared by software. 0: TIM7 clock disabled 1: TIM7 clock enabled Bit 4 TIM6EN: TIM6 timer clock enable Set and cleared by software. 0: TIM6 clock disabled 1: TIM6 clock enabled Bit 3 TIM5EN: TIM5 timer clock enable Set and cleared by software. 0: TIM5 clock disabled 1: TIM5 clock enabled Bit 2 TIM4EN: TIM4 timer clock enable Set and cleared by software. 0: TIM4 clock disabled 1: TIM4 clock enabled Bit 1 TIM3EN: TIM3 timer clock enable Set and cleared by software. 0: TIM3 clock disabled 1: TIM3 clock enabled Bit 0 TIM2EN: TIM2 timer clock enable Set and cleared by software. 0: TIM2 clock disabled 1: TIM2 clock enabled

Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 118/1134 RM0008 Rev 20

7.3.9 Backup domain cont rol register (RCC_BDCR)

Address offset: 0x20 Reset value: 0x0000 0000, reset by Backup domain Reset. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access Wait states are inserted in case of successive accesses to this register. Note: The LSEON, LSEBYP, RTCSEL and RTCEN bits of the Backup domain control register (RCC_BDCR) are in the Backup domain. As a result, after Reset, these bits are write- protected and the DBP bit in the Power control register (PWR_CR) has to be set before these can be modified. Refer to Section 5: Power control (PWR) for further information. These bits are only reset after a Backup domain Reset (see Section 7.1.3: Backup domain reset). Any internal or external Reset will not have any effect on these bits. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved BDRST rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTC EN Reserved RTCSEL[1:0] Reserved LSE BYP LSE RDY LSEON rw rw rw rw r rw Bits 31:17 Reserved, must be kept at reset value. Bit 16 BDRST: Backup domain software reset Set and cleared by software. 0: Reset not activated 1: Resets the entire Backup domain Bit 15 RTCEN: RTC clock enable Set and cleared by software. 0: RTC clock disabled 1: RTC clock enabled Bits 14:10 Reserved, must be kept at reset value. Bits 9:8 RTCSEL[1:0]: RTC clock source selection Set by software to select the clock source for the RTC. Once the RTC clock source has been selected, it cannot be changed anymore unless the Backup domain is reset. The BDRST bit can be used to reset them. 00: No clock 01: LSE oscillator clock used as RTC clock 10: LSI oscillator clock used as RTC clock 11: HSE oscillator clock divided by 128 used as RTC clock Bits 7:3 Reserved, must be kept at reset value.

RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) 122

7.3.10 Control/status register (RCC_CSR)

Address: 0x24 Reset value: 0x0C00 0000, reset by system Reset, except reset flags by power Reset only. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access Wait states are inserted in case of successive accesses to this register. Bit 2 LSEBYP: External low-speed oscillator bypass Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled. 0: LSE oscillator not bypassed 1: LSE oscillator bypassed Bit 1 LSERDY: External low-speed oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles. 0: External 32 kHz oscillator not ready 1: External 32 kHz oscillator ready Bit 0 LSEON: External low-speed oscillator enable Set and cleared by software. 0: External 32 kHz oscillator OFF 1: External 32 kHz oscillator ON 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LPWR RSTF WWDG RSTF IWDG RSTF SFT RSTF POR RSTF PIN RSTF Res. RMVF Reserved rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LSI RDY LSION rr w

Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 120/1134 RM0008 Rev 20 Bit 31 LPWRRSTF: Low-power reset flag Set by hardware when a Low-power management reset occurs. Cleared by writing to the RMVF bit. 0: No Low-power management reset occurred 1: Low-power management reset occurred For further information on Low-power management reset, refer to Low-power management reset. Bit 30 WWDGRSTF: Window watchdog reset flag Set by hardware when a window watchdog reset occurs. Cleared by writing to the RMVF bit. 0: No window watchdog reset occurred 1: Window watchdog reset occurred Bit 29 IWDGRSTF: Independent watchdog reset flag Set by hardware when an independent watchdog reset from V DD domain occurs. Cleared by writing to the RMVF bit. 0: No watchdog reset occurred 1: Watchdog reset occurred Bit 28 SFTRSTF: Software reset flag Set by hardware when a software reset occurs. Cleared by writing to the RMVF bit. 0: No software reset occurred 1: Software reset occurred Bit 27 PORRSTF: POR/PDR reset flag Set by hardware when a POR/PDR reset occurs. Cleared by writing to the RMVF bit. 0: No POR/PDR reset occurred 1: POR/PDR reset occurred Bit 26 PINRSTF: PIN reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by writing to the RMVF bit. 0: No reset from NRST pin occurred 1: Reset from NRST pin occurred Bit 25 Reserved, must be kept at reset value. Bit 24 RMVF: Remove reset flag Set by software to clear the reset flags. 0: No effect 1: Clear the reset flags Bits 23:2 Reserved, must be kept at reset value. Bit 1 LSIRDY: Internal low-speed oscillator ready Set and cleared by hardware to indicate when the internal RC 40 kHz oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after 3 internal RC 40 kHz oscillator clock cycles. 0: Internal RC 40 kHz oscillator not ready 1: Internal RC 40 kHz oscillator ready Bit 0 LSION: Internal low-speed oscillator enable Set and cleared by software. 0: Internal RC 40 kHz oscillator OFF 1: Internal RC 40 kHz oscillator ON

7.3.11 RCC register map

The following table gives the RCC register map and the reset values. Table 18. RCC register map and reset values

Refer to Table 3 on page 50 for the register boundary addresses. Table 18. RCC register map and reset values (continued)

RM0008 Connectivity line devices: reset and clock control (RCC) 158

8 Connectivity line devices : reset and clock control

(RCC) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This Section applies to all connectivity line devices, unless otherwise specified.

8.1 Reset

There are three types of reset, defined as system reset, power reset and backup domain reset.

8.1.1 System reset

A system reset sets all registers to their reset values except the reset flags in the clock controller CSR register and the registers in the Backup domain (see Figure 4). A system reset is generated when one of the following events occurs: 1. A low level on the NRST pin (external reset) 2. Window watchdog end of count condition (WWDG reset) 3. Independent watchdog end of count condition (IWDG reset) 4. A software reset (SW reset) (see Software reset) 5. Low-power management reset (see Low-power management reset) The reset source can be identified by checking the reset flags in the Control/Status register, RCC_CSR (see Section 8.3.10: Control/status register (RCC_CSR)). Software reset The SYSRESETREQ bit in Cortex®-M3 Application Interrupt and Reset Control Register must be set to force a software reset on the device. Refer to the STM32F10xxx Cortex®-M3 programming manual (see Related documents) for more details.

Reset generated when entering Standby mode:

is reset instead of entering Standby mode.

Reset when entering Stop mode:

reset instead of entering Stop mode.

8.1.2 Power reset

Power-on/power-down reset (POR/PDR reset)
When exiting Standby mode

details, refer to Table 63: Vector table for other STM32F10xxx devices. the NRST pin is asserted low. Figure 10. Simplified diagram of the reset circuit

RM0008 Connectivity line devices: reset and clock control (RCC) 158

8.1.3 Backup domain reset

8.2 Clocks

Three different clock sources can be used to drive the system clock (SYSCLK):

HSI oscillator clock
HSE oscillator clock
PLL clock The devices have the following two secondary clock sources:
40 kHz low speed internal RC (LSI RC) which drives the independent watchdog and optionally the RTC used for Auto-wakeup from Stop/Standby mode.
32.768 kHz low speed external crystal (LSE crystal) which optionally drives the real- time clock (RTCCLK) Each clock source can be switched on or off independently when it is not used, to optimize power consumption.

Figure 11. Clock tree

When the HSI is used as a PLL clock input, the maxi mum system clock frequency that can be achieved is
For full details about the internal and external cl ock source characteristics, refer to the “Electrical

characteristics” section in your device datasheet. sampling frequencies from 8 kHz to 96 kHz with less than 0.5% accuracy.

8 MHz

48 MHz

36 MHz max PCLK1

72 MHz max PCLK2

14 MHz max

RM0008 Connectivity line devices: reset and clock control (RCC) 158 Several prescalers allow the configuration of the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB2 domains is 72 MHz. The maximum allowed frequency of the APB1 domain is 36 MHz. All peripheral clocks are derived from the system clock (SYSCLK) except:

The Flash memory programming interface clock (FLITFCLK) is always the HSI clock
The USB OTG FS 48 MHz clock which is derived from the PLL VCO clock (2 × PLLCLK), followed by a programmable prescaler (divide by 3 or 2). This selection is made through the OTGFSPRE bit in the RCC_CFGR register. For proper USB OTG FS operation, the PLL should be configured to output 72 MHz or 48 MHz.
The I2S2 and I2S3 clocks which can be derived from the system clock (SYSCLK) or the PLL3 VCO clock (2 × PLL3CLK). This selection is made through the I2SxSRC bit in the RCC_CFGR2 register. For more information on PLL3 and how to configure the I2S clock to achieve high-quality audio performance, refer to Section 25.4.3: Clock generator.
The Ethernet MAC clocks (TX, RX and RMII) which are provided from the external PHY. For further information on the Ethernet configuration, refer to Section 29.4.4: MII/RMII selection. When the Ethernet is used, the AHB clock frequency must be at least 25 MHz. The RCC feeds the Cortex ® System Timer (SysTick) external clock with the AHB clock (HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex® clock (HCLK), configurable in the SysTick Control and Status Register. The ADCs are clocked by the clock of the High Speed domain (APB2) divided by 2, 4, 6 or 8. The timer clock frequencies are automatically fixed by hardware. There are two cases: 1. if the APB prescaler is 1, the timer clock fr equencies are set to the same frequency as that of the APB domain to which the timers are connected. 2. otherwise, they are set to twice (×2) the frequency of the APB domain to which the timers are connected. FCLK acts as Cortex®-M3’s free-running clock. For more details refer to Arm® Cortex-M3 r1p1 Technical Reference Manual (TRM).

8.2.1 HSE clock

The high speed external clock signal (HSE) can be generated from two possible clock sources:

HSE external crystal/ceramic resonator
HSE user external clock The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.

characteristics section of the datasheet for more details.

8.2.2 HSI clock

directly as a system clock or divided by 2 to be used as PLL input. Figure 12. HSE/ LSE clock sources

RM0008 Connectivity line devices: reset and clock control (RCC) 158 Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at TA= 25 °C. After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the Clock control register (RCC_CR). If the application is subject to voltage or temperature variations this may affect the RC oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0] bits in the Clock control register (RCC_CR). The HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI RC is stable or not. At startup, the HSI RC output clock is not released until this bit is set by hardware. The HSI RC can be switched on and off using the HSION bit in the Clock control register (RCC_CR). The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal oscillator fails. Refer to Section 8.2.7: Clock security system (CSS).

8.2.3 PLLs

The main PLL provides a frequency multiplier starting from one of the following clock sources:

HSI clock divided by 2
HSE or PLL2 clock through a configurable divider Refer to Figure 11 and Clock control register (RCC_CR). PLL2 and PLL3 are clocked by HSE through a specific configurable divider. Refer to Figure 11 and Clock configuration register2 (RCC_CFGR2) The configuration of each PLL (selection of clock source, predivision factor and multiplication factor) must be done before enabling the PLL. Each PLL should be enabled after its input clock becomes stable (ready flag). Once the PLL is enabled, these parameters can not be changed. When changing the entry clock source of the main PLL, the original clock source must be switched off only after the selection of the new clock source (done through bit PLLSRC in the Clock configuration register (RCC_CFGR)). An interrupt can be generated when the PLL is ready if enabled in the Clock interrupt register (RCC_CIR).

8.2.4 LSE clock

Connectivity line devices: reset and clock control (RCC) RM0008 130/1134 RM0008 Rev 20 External source (LSE bypass) In this mode, an external clock source must be provided. It can have a frequency of up to 1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the Backup domain control register (RCC_BDCR). The external clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be left Hi-Z. See Figure 12.

8.2.5 LSI clock

The LSI RC acts as an low-power clock source that can be kept running in Stop and Standby mode for the independent watchdog (IWDG) and Auto-wakeup unit (AWU). The clock frequency is around 40 kHz (between 30 kHz and 60 kHz). For more details, refer to the electrical characteristics section of the datasheets. The LSI RC can be switched on and off using the LSION bit in the Control/status register (RCC_CSR). The LSIRDY flag in the Control/status register (RCC_CSR) indicates if the low-speed internal oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt register (RCC_CIR). LSI calibration The frequency dispersion of the Low Speed Internal RC (LSI) oscillator can be calibrated to have accurate RTC time base and/or IWDG timeout (when LSI is used as clock source for these peripherals) with an acceptable accuracy. This calibration is performed by measuring the LSI clock frequency with respect to TIM5 input clock (TIM5CLK). According to this measurement done at the precision of the HSE oscillator, the software can adjust the programmable 20-bit prescaler of the RTC to get an accurate time base or can compute accurate IWDG timeout. Use the following procedure to calibrate the LSI: 1. Enable TIM5 timer and configure channel4 in input capture mode 2. Set the TIM5CH4_IREMAP bit in the AFIO _MAPR register to connect the LSI clock internally to TIM5 channel4 input capture for calibration purpose. 3. Measure the frequency of LSI clock us ing the TIM5 Capture/compare 4 event or interrupt. 4. Use the measured LSI frequency to update the 20-bit prescaler of the RTC depending on the desired time base and/or to compute the IWDG timeout.

8.2.6 System clock (SYSCLK) selection

After a system reset, the HSI oscillator is selected as system clock. When a clock source is used directly or through the PLL as the system clock, it is not possible to stop it. A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. Status bits in the Clock control register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently used as system clock.

RM0008 Connectivity line devices: reset and clock control (RCC) 158

8.2.7 Clock security system (CSS)

Clock Security System can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped. a failure is detected on the HSE clock, the HSE Oscillator is automatically disabled, a clock failure event is sent to the break input of the TIM1 Advanced control timer and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex ®-M3 NMI (Non-Maskable Interrupt) exception vector. Note: Once the CSS is enabled and if the HSE cloc k fails, the CSS interrupt occurs and an NMI is automatically generated. The NMI will be executed indefinitely unless the CSS interrupt pending bit is cleared. As a consequence, in the NMI ISR user must clear the CSS interrupt by setting the CSSC bit in the Clock interrupt register (RCC_CIR). If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is used as PLL input clock directly or through PLL2, and the PLL clock is used as system clock), a detected failure causes a switch of the system clock to the HSI oscillator and the disabling of the external HSE oscillator. If the HSE oscillator clock (divided or not) is the clock entry of the PLL (directly or through PLL2) used as system clock when the failure occurs, the PLL is disabled too.

8.2.8 RTC clock

If LSE is selected as RTC clock: – The RTC continues to work even if the V DD supply is switched off, provided the VBAT supply is maintained.
If LSI is selected as Auto-Wakeup unit (AWU) clock: – The AWU state is not guaranteed if the V DD supply is powered off. Refer to Section 8.2.5: LSI clock for more details on LSI calibration.
If the HSE clock divided by 128 is used as RTC clock: – The RTC state is not guaranteed if the V DD supply is powered off or if the internal voltage regulator is powered off (removing power from the 1.8 V domain). – The DPB bit (Disable backup domain wr ite protection) in the Power controller register must be set to 1 (refer to Section 5.4.1: Power control register (PWR_CR)).

8.2.9 Watchdog clock

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8.2.10 Clock-out capability

SYSCLK
HSI
HSE
PLL clock divided by 2 selected
PLL2 clock selected
PLL3 clock divided by 2 selected
XT1 external 3-25 MHz oscillator clock selected (for Ethernet)
PLL3 clock selected (for Ethernet) The selected clock to output onto MCO must not exceed 50 MHz (the maximum I/O speed). The selection is controlled by the MCO[3:0] bits of the Clock configuration register (RCC_CFGR).

8.3 RCC registers

Refer to Section 2.2 on page 45 for a list of abbreviations used in register descriptions.

8.3.1 Clock control register (RCC_CR)

Address offset: 0x00 Reset value: 0x0000 XX83 where X is undefined. Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PLL3 RDY PLL3 ON PLL2 RDY PLL2 ON PLLRD Y PLLON Reserved CSSON HSEBY P HSERDY HSEON r rw r rw r rw rw rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HSICAL[7:0] HSITRIM[4:0] Res. HSIRDY HSION r r r r r r r r r wr wr wr w r w r r w Bits 31:30 Reserved, must be kept at reset value. Bit 29 PLL3RDY: PLL3 clock ready flag Set by hardware to indicate that the PLL3 is locked. 0: PLL3 unlocked 1: PLL3 locked Bit 28 PLL3ON: PLL3 enable Set and cleared by software to enable PLL3. Cleared by hardware when entering Stop or Standby mode. 0: PLL3 OFF 1: PLL3 ON

RM0008 Connectivity line devices: reset and clock control (RCC) 158 Bit 27 PLL2RDY: PLL2 clock ready flag Set by hardware to indicate that the PLL2 is locked. 0: PLL2 unlocked 1: PLL2 locked Bit 26 PLL2ON: PLL2 enable Set and cleared by software to enable PLL2. Cleared by hardware when entering Stop or Standby mode. This bit can not be cleared if the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock). 0: PLL2 OFF 1: PLL2 ON Bit 25 PLLRDY: PLL clock ready flag Set by hardware to indicate that the PLL is locked. 0: PLL unlocked 1: PLL locked Bit 24 PLLON: PLL enable Set and cleared by software to enable PLL. Cleared by hardware when entering Stop or Standby mode. This bit can not be reset if the PLL clock is used as system clock or is selected to become the system clock. Software must disable the USB OTG FS clock before clearing this bit. 0: PLL OFF 1: PLL ON Bits 23:20 Reserved, must be kept at reset value. Bit 19 CSSON: Clock security system enable Set and cleared by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. 0: Clock detector OFF 1: Clock detector ON (Clock detector ON if the HSE oscillator is ready, OFF if not) Bit 18 HSEBYP: External high-speed clock bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. 0: external 3-25 MHz oscillator not bypassed 1: external 3-25 MHz oscillator bypassed with external clock Bit 17 HSERDY: External high-speed clock ready flag Set by hardware to indicate that the HSE oscillator is stable. This bit needs 6 cycles of the HSE oscillator clock to fall down after HSEON reset. 0: HSE oscillator not ready 1: HSE oscillator ready Bit 16 HSEON: HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. 0: HSE oscillator OFF 1: HSE oscillator ON Bits 15:8 HSICAL[7:0]: Internal high-speed clock calibration These bits are initialized automatically at startup.

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8.3.2 Clock configurati on register (RCC_CFGR)

Address offset: 0x04 Reset value: 0x0000 0000 Access: 0 ≤ wait state ≤ 2, word, half-word and byte access 1 or 2 wait states inserted only if the access occurs during a clock source switch. Bits 7:3 HSITRIM[4:0]: Internal high-speed clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the internal HSI RC. The default value is 16, which, when added to the HSICAL value, should trim the HSI to 8 MHz ± 1%. The trimming step (Fhsitrim) is around 40 kHz between two consecutive HSICAL steps. Bit 2 Reserved, must be kept at reset value. Bit 1 HSIRDY: Internal high-speed clock ready flag Set by hardware to indicate that internal 8 MHz RC oscillator is stable. After the HSION bit is cleared, HSIRDY goes low after 6 internal 8 MHz RC oscillator clock cycles. 0: Internal 8 MHz RC oscillator not ready 1: Internal 8 MHz RC oscillator ready Bit 0 HSION: Internal high-speed clock enable Set and cleared by software. Set by hardware to force the internal 8 MHz RC oscillator ON when leaving Stop or Standby mode or in case of failure of the external 3-25 MHz oscillator used directly or indirectly as system clock. This bit can not be cleared if the internal 8 MHz RC is used directly or indirectly as system clock or is selected to become the system clock. 0: Internal 8 MHz RC oscillator OFF 1: Internal 8 MHz RC oscillator ON 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved MCO[3:0] Res. OTGFS PRE PLLMUL[3:0] PLL XTPRE PLL SRC rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADC PRE[1:0] PPRE2[2:0] PPRE1[2:0] HPRE[3:0] SWS[1:0] SW[1:0] rw rw rw rw rw rw rw rw rw rw rw rw r r rw rw

RM0008 Connectivity line devices: reset and clock control (RCC) 158 Bits 31:27 Reserved, must be kept at reset value. Bits 26:24 MCO[3:0]: Microcontroller clock output Set and cleared by software. 00xx: No clock 0100: System clock (SYSCLK) selected 0101: HSI clock selected 0110: HSE clock selected 0111: PLL clock divided by 2 selected 1000: PLL2 clock selected 1001: PLL3 clock divided by 2 selected 1010: XT1 external 3-25 MHz oscillator clock selected (for Ethernet) 1011: PLL3 clock selected (for Ethernet) Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. The selected clock to output onto the MCO pin must not exceed 50 MHz (the maximum I/O speed). Bit 22 OTGFSPRE: USB OTG FS prescaler Set and cleared by software to generate the 48 MHz USB OTG FS clock. This bit must be valid before enabling the OTG FS clock in the RCC_APB1ENR register. This bit can not be cleared if the OTG FS clock is enabled. 0: PLL VCO (2 × PLLCLK) clock is divided by 3 (PLL must be configured to output 72 MHz) 1: PLL VCO (2 × PLLCLK) clock is divided by 2 (PLL must be configured to output 48 MHz) Bits 21:18 PLLMUL[3:0]: PLL multiplication factor These bits are written by software to define the PLL multiplication factor. They can be written only when PLL is disabled. 000x: Reserved 0010: PLL input clock x 4 0011: PLL input clock x 5 0100: PLL input clock x 6 0101: PLL input clock x 7 0110: PLL input clock x 8 0111: PLL input clock x 9 10xx: Reserved 1100: Reserved 1101: PLL input clock x 6.5 111x: Reserved Caution: The PLL output frequency must not exceed 72 MHz. Bit 17 PLLXTPRE: LSB of division factor PREDIV1 Set and cleared by software to select the least significant bit of the PREDIV1 division factor. It is the same bit as bit(0) in the RCC_CFGR2 register, so modifying bit(0) in the RCC_CFGR2 register changes this bit accordingly. If bits[3:1] in register RCC_CFGR2 are not set, this bit controls if PREDIV1 divides its input clock by 2 (PLLXTPRE=1) or not (PLLXTPRE=0). This bit can be written only when PLL is disabled.

Connectivity line devices: reset and clock control (RCC) RM0008 136/1134 RM0008 Rev 20 Bit 16 PLLSRC: PLL entry clock source Set and cleared by software to select PLL clock source. This bit can be written only when PLL is disabled. 0: HSI oscillator clock / 2 selected as PLL input clock 1: Clock from PREDIV1 selected as PLL input clock Note: When changing the main PLL’s entry clock source, the original clock source must be switched off only after the selection of the new clock source. Bits 14:14 ADCPRE[1:0]: ADC prescaler Set and cleared by software to select the frequency of the clock to the ADCs. 00: PCLK2 divided by 2 01: PCLK2 divided by 4 10: PCLK2 divided by 6 11: PCLK2 divided by 8 Bits 13:11 PPRE2[2:0]: APB high-speed prescaler (APB2) Set and cleared by software to control the division factor of the APB High speed clock (PCLK2). 0xx: HCLK not divided 100: HCLK divided by 2 101: HCLK divided by 4 110: HCLK divided by 8 111: HCLK divided by 16 Bits 10:8 PPRE1[2:0]: APB Low-speed prescaler (APB1) Set and cleared by software to control the division factor of the APB Low speed clock (PCLK1). 0xx: HCLK not divided 100: HCLK divided by 2 101: HCLK divided by 4 110: HCLK divided by 8 111: HCLK divided by 16 Caution: Software must configure these bits ensure that the frequency in this domain does not exceed 36 MHz.

RM0008 Connectivity line devices: reset and clock control (RCC) 158

8.3.3 Clock interrupt register (RCC_CIR)

Address offset: 0x08 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Bits 7:4 HPRE[3:0]: AHB prescaler Set and cleared by software to control AHB clock division factor. 0xxx: SYSCLK not divided 1000: SYSCLK divided by 2 1001: SYSCLK divided by 4 1010: SYSCLK divided by 8 1011: SYSCLK divided by 16 1100: SYSCLK divided by 64 1101: SYSCLK divided by 128 1110: SYSCLK divided by 256 1111: SYSCLK divided by 512 Note: The prefetch buffer must be kept on when us ing a prescaler different from 1 on the AHB clock. Refer to the section Reading the Flash memory for more details. Caution: The AHB clock frequency must be at least 25 MHz when the Ethernet is used. Bits 3:2 SWS[1:0]: System clock switch status Set and cleared by hardware to indicate which clock source is used as system clock. 00: HSI oscillator used as system clock 01: HSE oscillator used as system clock 10: PLL used as system clock 11: Not applicable Bits 1:0 SW[1:0]: System clock Switch Set and cleared by software to select SYSCLK source. Set by hardware to force HSI selection when leaving Stop and Standby mode or in case of failure of the HSE oscillator used directly or indirectly as system clock (if the Clock Security System is enabled). 00: HSI selected as system clock 01: HSE selected as system clock 10: PLL selected as system clock 11: Not allowed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved CSSC PLL3 RDYC PLL2 RDYC PLL RDYC HSE RDYC HSI RDYC LSE RDYC LSI RDYC wwwwwww w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. PLL3 RDYIE PLL2 RDYIE PLL RDYIE HSE RDYIE HSI RDYIE LSE RDYIE LSI RDYIE CSSF PLL3 RDYF PLL2 RDYF PLL RDYF HSE RDYF HSI RDYF LSE RDYF LSI RDYF rw rw rw rw rw rw rw r r r r r r r r

Connectivity line devices: reset and clock control (RCC) RM0008 138/1134 RM0008 Rev 20 Bits 31:24 Reserved, must be kept at reset value. Bit 23 CSSC: Clock security system interrupt clear This bit is set by software to clear the CSSF flag. 0: No effect 1: Clear CSSF flag Bit 22 PLL3RDYC: PLL3 Ready Interrupt Clear This bit is set by software to clear the PLL3RDYF flag. 0: No effect 1: Clear PLL3RDYF flag Bit 21 PLL2RDYC: PLL2 Ready Interrupt Clear This bit is set by software to clear the PLL2RDYF flag. 0: No effect 1: Clear PLL2RDYF flag Bit 20 PLLRDYC: PLL ready interrupt clear This bit is set by software to clear the PLLRDYF flag. 0: No effect 1: Clear PLLRDYF flag Bit 19 HSERDYC: HSE ready interrupt clear This bit is set by software to clear the HSERDYF flag. 0: No effect 1: Clear HSERDYF flag Bit 18 HSIRDYC: HSI ready interrupt clear This bit is set by software to clear the HSIRDYF flag. 0: No effect 1: Clear HSIRDYF flag Bit 17 LSERDYC: LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag. 0: No effect 1: Clear LSERDYF flag Bit 16 LSIRDYC: LSI ready interrupt clear This bit is set by software to clear the LSIRDYF flag. 0: No effect 1: Clear LSIRDYF flag Bit 15 Reserved, must be kept at reset value. Bit 14 PLL3RDYIE: PLL3 Ready Interrupt Enable Set and cleared by software to enable/disable interrupt caused by PLL3 lock. 0: PLL3 lock interrupt disabled 1: PLL3 lock interrupt enabled Bit 13 PLL2RDYIE: PLL2 Ready Interrupt Enable Set and cleared by software to enable/disable interrupt caused by PLL2 lock. 0: PLL2 lock interrupt disabled 1: PLL2 lock interrupt enabled Bit 12 PLLRDYIE: PLL ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL lock. 0: PLL lock interrupt disabled 1: PLL lock interrupt enabled

RM0008 Connectivity line devices: reset and clock control (RCC) 158 Bit 11 HSERDYIE: HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the external 3-25 MHz oscillator stabilization. 0: HSE ready interrupt disabled 1: HSE ready interrupt enabled Bit 10 HSIRDYIE: HSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the internal 8 MHz RC oscillator stabilization. 0: HSI ready interrupt disabled 1: HSI ready interrupt enabled Bit 9 LSERDYIE: LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the external 32 kHz oscillator stabilization. 0: LSE ready interrupt disabled 1: LSE ready interrupt enabled Bit 8 LSIRDYIE: LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by internal RC 40 kHz oscillator stabilization. 0: LSI ready interrupt disabled 1: LSI ready interrupt enabled Bit 7 CSSF: Clock security system interrupt flag Set by hardware when a failure is detected in the external 3-25 MHz oscillator. It is cleared by software setting the CSSC bit. 0: No clock security interrupt caused by HSE clock failure 1: Clock security interrupt caused by HSE clock failure Bit 6 PLL3RDYF: PLL3 Ready Interrupt flag Set by hardware when the PLL3 locks and PLL3RDYIE is set. It is cleared by software setting the PLL3RDYC bit. 0: No clock ready interrupt caused by PLL3 lock 1: Clock ready interrupt caused by PLL3 lock Bit 5 PLL2RDYF: PLL2 Ready Interrupt flag Set by hardware when the PLL2 locks and PLL2RDYDIE is set. It is cleared by software setting the PLL2RDYC bit. 0: No clock ready interrupt caused by PLL2 lock 1: Clock ready interrupt caused by PLL2 lock Bit 4 PLLRDYF: PLL ready interrupt flag Set by hardware when the PLL locks and PLLRDYDIE is set. It is cleared by software setting the PLLRDYC bit. 0: No clock ready interrupt caused by PLL lock 1: Clock ready interrupt caused by PLL lock Bit3 HSERDYF: HSE ready interrupt flag Set by hardware when External High Speed clock becomes stable and HSERDYIE is set. It is cleared by software setting the HSERDYC bit. 0: No clock ready interrupt caused by the external 3-25 MHz oscillator 1: Clock ready interrupt caused by the external 3-25 MHz oscillator

Connectivity line devices: reset and clock control (RCC) RM0008 140/1134 RM0008 Rev 20 Bit 2 HSIRDYF: HSI ready interrupt flag Set by hardware when the Internal High Speed clock becomes stable and HSIRDYIE is set. It is cleared by software setting the HSIRDYC bit. 0: No clock ready interrupt caused by the internal 8 MHz RC oscillator 1: Clock ready interrupt caused by the internal 8 MHz RC oscillator Bit 1 LSERDYF: LSE ready interrupt flag Set by hardware when the External Low Speed clock becomes stable and LSERDYIE is set. It is cleared by software setting the LSERDYC bit. 0: No clock ready interrupt caused by the external 32 kHz oscillator 1: Clock ready interrupt caused by the external 32 kHz oscillator Bit 0 LSIRDYF: LSI ready interrupt flag Set by hardware when Internal Low Speed clock becomes stable and LSIRDYIE is set. It is cleared by software setting the LSIRDYC bit. 0: No clock ready interrupt caused by the internal RC 40 kHz oscillator 1: Clock ready interrupt caused by the internal RC 40 kHz oscillator

RM0008 Connectivity line devices: reset and clock control (RCC) 158

8.3.4 APB2 peripheral rese t register (RCC_APB2RSTR)

Address offset: 0x0C Reset value: 0x00000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 1 5 1 4 1 3 1 2 1 1 1 0 9 876543210 Res. USART1 RST Res. SPI1 RST TIM1 RST ADC2 RST ADC1 RST Reserved IOPE RST IOPD RST IOPC RST IOPB RST IOPA RST Res. AFIO RST rw rw rw rw rw rw rw rw rw rw rw Bits 31:15 Reserved, must be kept at reset value. Bit 14 USART1RST: USART1 reset Set and cleared by software. 0: No effect 1: Reset USART1 Bit 13 Reserved, must be kept at reset value. Bit 12 SPI1RST: SPI 1 reset Set and cleared by software. 0: No effect 1: Reset SPI 1 Bit 11 TIM1RST: TIM1 timer reset Set and cleared by software. 0: No effect 1: Reset TIM1 timer Bit 10 ADC2RST: ADC 2 interface reset Set and cleared by software. 0: No effect 1: Reset ADC 2 interface Bit 9 ADC1RST: ADC 1 interface reset Set and cleared by software. 0: No effect 1: Reset ADC 1 interface Bits 8:7 Reserved, must be kept at reset value. Bit 6 IOPERST: I/O port E reset Set and cleared by software. 0: No effect 1: Reset I:O port E Bit 5 IOPDRST: I/O port D reset Set and cleared by software. 0: No effect 1: Reset I/O port D

Connectivity line devices: reset and clock control (RCC) RM0008 142/1134 RM0008 Rev 20

8.3.5 APB1 peripheral rese t register (RCC_APB1RSTR)

Address offset: 0x10 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Bit 4 IOPCRST: IO port C reset Set and cleared by software. 0: No effect 1: Reset I/O port C Bit 3 IOPBRST: IO port B reset Set and cleared by software. 0: No effect 1: Reset I/O port B Bit 2 IOPARST: I/O port A reset Set and cleared by software. 0: No effect 1: Reset I/O port A Bit 1 Reserved, must be kept at reset value. Bit 0 AFIORST: Alternate function I/O reset Set and cleared by software. 0: No effect 1: Reset Alternate Function 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved DAC RST PWR RST BKP RST CAN2 RST CAN1 RST Reserved I2C2 RST I2C1 RST UART5 RST UART4 RST USART3 RST USART2 RST Res. rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPI3 RST SPI2 RST Reserved WWDG RST Reserved TIM7 RST TIM6 RST TIM5 RST TIM4 RST TIM3 RST TIM2 RST rw rw rw rw rw rw rw rw rw Bits 31:30 Reserved, must be kept at reset value. Bit 29 DACRST: DAC interface reset Set and cleared by software. 0: No effect 1: Reset DAC interface Bit 28 PWRRST: Power interface reset Set and cleared by software. 0: No effect 1: Reset power interface Bit 27 BKPRST: Backup interface reset Set and cleared by software. 0: No effect 1: Reset backup interface

RM0008 Connectivity line devices: reset and clock control (RCC) 158 Bit 26 CAN2RST: CAN2 reset Set and cleared by software. 0: No effect 1: Reset CAN2 Bit 25 CAN1RST: CAN1 reset Set and cleared by software. 0: No effect 1: Reset CAN1 Bits 24:23 Reserved, must be kept at reset value. Bit 22 I2C2RST: I2C 2 reset Set and cleared by software. 0: No effect 1: Reset I2C 2 Bit 21 I2C1RST: I2C1 reset Set and cleared by software. 0: No effect 1: Reset I2C 1 Bit 20 UART5RST: USART 5 reset Set and cleared by software. 0: No effect 1: Reset USART 5 Bit 19 UART4RST: USART 4 reset Set and cleared by software. 0: No effect 1: Reset USART 4 Bit 18 USART3RST: USART 3 reset Set and cleared by software. 0: No effect 1: Reset USART 3 Bit 17 USART2RST: USART 2 reset Set and cleared by software. 0: No effect 1: Reset USART 2 Bits 16 Reserved, must be kept at reset value. Bit 15 SPI3RST: SPI3 reset Set and cleared by software. 0: No effect 1: Reset SPI 3 Bit 14 SPI2RST: SPI2 reset Set and cleared by software. 0: No effect 1: Reset SPI2 Bits 13:12 Reserved, must be kept at reset value.

Connectivity line devices: reset and clock control (RCC) RM0008 144/1134 RM0008 Rev 20 Bit 11 WWDGRST: Window watchdog reset Set and cleared by software. 0: No effect 1: Reset window watchdog Bits 10:6 Reserved, must be kept at reset value. Bit 5 TIM7RST: Timer 7 reset Set and cleared by software. 0: No effect 1: Reset timer 7 Bit 4 TIM6RST: Timer 6 reset Set and cleared by software. 0: No effect 1: Reset timer 6 Bit 3 TIM5RST: Timer 5 reset Set and cleared by software. 0: No effect 1: Reset timer 5 Bit 2 TIM4RST: Timer 4 reset Set and cleared by software. 0: No effect 1: Reset timer 4 Bit 1 TIM3RST: Timer 3 reset Set and cleared by software. 0: No effect 1: Reset timer 3 Bit 0 TIM2RST: Timer 2 reset Set and cleared by software. 0: No effect 1: Reset timer 2

RM0008 Connectivity line devices: reset and clock control (RCC) 158

8.3.6 AHB Peripheral Clock en able register (RCC_AHBENR)

Address offset: 0x14 Reset value: 0x0000 0014 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved ETHMAC RXEN rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETHMAC TXEN ETHMA CEN Res. OTGFS EN Reserved CRCEN Res. FLITFEN Res. SRAM EN DMA2 EN DMA1 EN rw rw rw rw rw rw rw rw Bits 31:17 Reserved, must be kept at reset value. Bit 16 ETHMACRXEN: Ethernet MAC RX clock enable Set and cleared by software. 0: Ethernet MAC RX clock disabled 1: Ethernet MAC RX clock enabled Note: In the RMII mode, if this clock is enabled, the RMII clock of the MAC is also enabled. Bit 15 ETHMACTXEN: Ethernet MAC TX clock enable Set and cleared by software. 0: Ethernet MAC TX clock disabled 1: Ethernet MAC TX clock enabled Note: In the RMII mode, if this clock is enabled, the RMII clock of the MAC is also enabled. Bit 14 ETHMACEN: Ethernet MAC clock enable Set and cleared by software. Selection of PHY interface (MII/RMII) must be done before enabling the MAC clock. 0: Ethernet MAC clock disabled 1: Ethernet MAC clock enabled Bit 13 Reserved, must be kept at reset value. Bit 12 OTGFSEN: USB OTG FS clock enable Set and cleared by software. 0: USB OTG FS clock disabled 1: USB OTG FS clock enabled Bits 11:7 Reserved, must be kept at reset value. Bit 6 CRCEN: CRC clock enable Set and cleared by software. 0: CRC clock disabled 1: CRC clock enabled Bit 5 Reserved, must be kept at reset value. Bit 4 FLITFEN: FLITF clock enable Set and cleared by software to disable/enable FLITF clock during sleep mode. 0: FLITF clock disabled during Sleep mode 1: FLITF clock enabled during Sleep mode

Connectivity line devices: reset and clock control (RCC) RM0008 146/1134 RM0008 Rev 20

8.3.7 APB2 peripheral clock en able register (RCC_APB2ENR)

Address: 0x18 Reset value: 0x0000 0000 Access: word, half-word and byte access No wait states, except if the access occurs while an access to a peripheral in the APB2 domain is on going. In this case, wait states are inserted until the access to APB2 peripheral is finished. Bit 3 Reserved, must be kept at reset value. Bit 2 SRAMEN: SRAM interface clock enable Set and cleared by software to disable/enable SRAM interface clock during Sleep mode. 0: SRAM interface clock disabled during Sleep mode 1: SRAM interface clock enabled during Sleep mode Bit 1 DMA2EN: DMA2 clock enable Set and cleared by software. 0: DMA2 clock disabled 1: DMA2 clock enabled Bit 0 DMA1EN: DMA1 clock enable Set and cleared by software. 0: DMA1 clock disabled 1: DMA1 clock enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. USART 1EN Res. SPI1 EN TIM1 EN ADC2 EN ADC1 EN Reserved IOPE EN IOPD EN IOPC EN IOPB EN IOPA EN Res. AFIO EN rw rw rw rw rw rw rw rw rw rw rw Bits 31:15 Reserved, must be kept at reset value. Bit 14 USART1EN: USART1 clock enable Set and cleared by software. 0: USART1 clock disabled 1: USART1 clock enabled Bit 13 Reserved, must be kept at reset value. Bit 12 SPI1EN: SPI 1 clock enable Set and cleared by software. 0: SPI 1 clock disabled 1: SPI 1 clock enabled Bit 11 TIM1EN: TIM1 Timer clock enable Set and cleared by software. 0: TIM1 timer clock disabled 1: TIM1 timer clock enabled

RM0008 Connectivity line devices: reset and clock control (RCC) 158 Bit 10 ADC2EN: ADC 2 interface clock enable Set and cleared by software. 0: ADC 2 interface clock disabled 1: ADC 2 interface clock enabled Bit 9 ADC1EN: ADC 1 interface clock enable Set and cleared by software. 0: ADC 1 interface disabled 1: ADC 1 interface clock enabled Bits 8:7 Reserved, must be kept at reset value. Bit 6 IOPEEN: I/O port E clock enable Set and cleared by software. 0: I/O port E clock disabled 1: I/O port E clock enabled Bit 5 IOPDEN: I/O port D clock enable Set and cleared by software. 0: I/O port D clock disabled 1: I/O port D clock enabled Bit 4 IOPCEN: I/O port C clock enable Set and cleared by software. 0: I/O port C clock disabled 1:I/O port C clock enabled Bit 3 IOPBEN: I/O port B clock enable Set and cleared by software. 0: I/O port B clock disabled 1:I/O port B clock enabled Bit 2 IOPAEN: I/O port A clock enable Set and cleared by software. 0: I/O port A clock disabled 1:I/O port A clock enabled Bit 1 Reserved, must be kept at reset value. Bit 0 AFIOEN: Alternate function I/O clock enable Set and cleared by software. 0: Alternate Function I/O clock disabled 1:Alternate Function I/O clock enabled

Connectivity line devices: reset and clock control (RCC) RM0008 148/1134 RM0008 Rev 20

8.3.8 APB1 peripheral clock en able register (RCC_APB1ENR)

Address: 0x1C Reset value: 0x0000 0000 Access: word, half-word and byte access No wait state, except if the access occurs while an access to a peripheral on APB1 domain is on going. In this case, wait states are inserted until this access to APB1 peripheral is finished. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved DAC EN PWR EN BKP EN CAN2 EN CAN1 EN Reserved I2C2 EN I2C1 EN UART5E N UART4E N USART3 EN USART2 EN Res. rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPI3 EN SPI2 EN Reserved WWD GEN Reserved TIM7 EN TIM6 EN TIM5 EN TIM4 EN TIM3 EN TIM2 EN rw rw rw rw rw rw rw rw rw Bits 31:30 Reserved, must be kept at reset value. Bit 29 DACEN: DAC interface clock enable Set and cleared by software. 0: DAC interface clock disabled 1: DAC interface clock enable Bit 28 PWREN: Power interface clock enable Set and cleared by software. 0: Power interface clock disabled 1: Power interface clock enable Bit 27 BKPEN: Backup interface clock enable Set and cleared by software. 0: Backup interface clock disabled 1: Backup interface clock enabled Bit 26 CAN2EN: CAN2 clock enable Set and cleared by software. 0: CAN2 clock disabled 1: CAN2 clock enabled Bit 25 CAN1EN: CAN1 clock enable Set and cleared by software. 0: CAN1 clock disabled 1: CAN1 clock enabled Bits 24:23 Reserved, must be kept at reset value. Bit 22 I2C2EN: I2C 2 clock enable Set and cleared by software. 0: I2C 2 clock disabled 1: I2C 2 clock enabled

RM0008 Connectivity line devices: reset and clock control (RCC) 158 Bit 21 I2C1EN: I2C 1 clock enable Set and cleared by software. 0: I2C 1 clock disabled 1: I2C 1 clock enabled Bit 20 UART5EN: USART 5 clock enable Set and cleared by software. 0: USART 5 clock disabled 1: USART 5 clock enabled Bit 19 UART4EN: USART 4 clock enable Set and cleared by software. 0: USART 4 clock disabled 1: USART 4 clock enabled Bit 18 USART3EN: USART 3 clock enable Set and cleared by software. 0: USART 3 clock disabled 1: USART 3 clock enabled Bit 17 USART2EN: USART 2 clock enable Set and cleared by software. 0: USART 2 clock disabled 1: USART 2 clock enabled Bits 16 Reserved, must be kept at reset value. Bit 15 SPI3EN: SPI 3 clock enable Set and cleared by software. 0: SPI 3 clock disabled 1: SPI 3 clock enabled Bit 14 SPI2EN: SPI 2 clock enable Set and cleared by software. 0: SPI 2 clock disabled 1: SPI 2 clock enabled Bits 13:12 Reserved, must be kept at reset value. Bit 11 WWDGEN: Window watchdog clock enable Set and cleared by software. 0: Window watchdog clock disabled 1: Window watchdog clock enabled Bits 10:6 Reserved, must be kept at reset value. Bit 5 TIM7EN: Timer 7 clock enable Set and cleared by software. 0: Timer 7 clock disabled 1: Timer 7 clock enabled Bit 4 TIM6EN: Timer 6 clock enable Set and cleared by software. 0: Timer 6 clock disabled 1: Timer 6 clock enabled

Connectivity line devices: reset and clock control (RCC) RM0008 150/1134 RM0008 Rev 20

8.3.9 Backup domain cont rol register (RCC_BDCR)

Address: 0x20 Reset value: 0x0000 0000, reset by Backup domain Reset. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access Wait states are inserted in the case of successive accesses to this register. Note: LSEON, LSEBYP, RTCSEL and RTCEN bits of the Backup domain control register (RCC_BDCR) are in the Backup domain. As a result, after Reset, these bits are write- protected and the DBP bit in the Power control register (PWR_CR) has to be set before these can be modified. Refer to Section 6: Backup registers (BKP) for further information. These bits are only reset after a Backup domain Reset (see Section 8.1.3: Backup domain reset). Any internal or external Reset will not have any effect on these bits. Bit 3 TIM5EN: Timer 5 clock enable Set and cleared by software. 0: Timer 5 clock disabled 1: Timer 5 clock enabled Bit 2 TIM4EN: Timer 4 clock enable Set and cleared by software. 0: Timer 4 clock disabled 1: Timer 4 clock enabled Bit 1 TIM3EN: Timer 3 clock enable Set and cleared by software. 0: Timer 3 clock disabled 1: Timer 3 clock enabled Bit 0 TIM2EN: Timer 2 clock enable Set and cleared by software. 0: Timer 2 clock disabled 1: Timer 2 clock enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved BDRST rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTC EN Reserved RTCSEL[1:0] Reserved LSE BYP LSE RDY LSEON rw rw rw rw r rw

RM0008 Connectivity line devices: reset and clock control (RCC) 158 Bits 31:17 Reserved, must be kept at reset value. Bit 16 BDRST: Backup domain software reset Set and cleared by software. 0: Reset not activated 1: Resets the entire Backup domain Bit 15 RTCEN: RTC clock enable Set and cleared by software. 0: RTC clock disabled 1: RTC clock enabled Bits 14:10 Reserved, must be kept at reset value. Bits 9:8 RTCSEL[1:0]: RTC clock source selection Set by software to select the clock source for the RTC. Once the RTC clock source has been selected, it cannot be changed anymore unless the Backup domain is reset. The BDRST bit can be used to reset the RTCSEL[1:0] bits. 00: No clock 01: LSE oscillator clock used as RTC clock 10: LSI oscillator clock used as RTC clock 11: HSE oscillator clock divided by 128 used as RTC clock Bits 7:3 Reserved, must be kept at reset value. Bit 2 LSEBYP: External Low Speed oscillator bypass Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled. 0: LSE oscillator not bypassed 1: LSE oscillator bypassed Bit 1 LSERDY: External Low Speed oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after 6 external low speed oscillator clock cycles 0: External 32 kHz oscillator not ready 1: External 32 kHz oscillator ready Bit 0 LSEON: External Low Speed oscillator enable Set and cleared by software. 0: External 32 kHz oscillator OFF 1: External 32 kHz oscillator ON

Connectivity line devices: reset and clock control (RCC) RM0008 152/1134 RM0008 Rev 20

8.3.10 Control/status register (RCC_CSR)

Address: 0x24 Reset value: 0x0C00 0000, reset by system Reset, except reset flags by power Reset only. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access Wait states are inserted in the case of successive accesses to this register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LPWR RSTF WWDG RSTF IWDG RSTF SFT RSTF POR RSTF PIN RSTF Res. RMVF Reserved rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LSI RDY LSION rr w Bit 31 LPWRRSTF: Low-power reset flag Set by hardware when a Low-power management reset occurs. It is cleared by writing to the RMVF bit. 0: No Low-power management reset occurred 1: Low-power management reset occurred For further information on Low-power management reset, refer to Low-power management reset. Bit 30 WWDGRSTF: Window watchdog reset flag Set by hardware when a window watchdog reset occurs. It is cleared by writing to the RMVF bit. 0: No window watchdog reset occurred 1: Window watchdog reset occurred Bit 29 IWDGRSTF: Independent watchdog reset flag Set by hardware when an independent watchdog reset from V DD domain occurs. It is cleared by writing to the RMVF bit. 0: No watchdog reset occurred 1: Watchdog reset occurred Bit 28 SFTRSTF: Software reset flag Set by hardware when a software reset occurs. It is cleared by writing to the RMVF bit. 0: No software reset occurred 1: Software reset occurred Bit 27 PORRSTF: POR/PDR reset flag Set by hardware when a POR/PDR reset occurs. It is cleared by writing to the RMVF bit. 0: No POR/PDR reset occurred 1: POR/PDR reset occurred Bit 26 PINRSTF: PIN reset flag Set by hardware when a reset from the NRST pin occurs. It is cleared by writing to the RMVF bit. 0: No reset from NRST pin occurred 1: Reset from NRST pin occurred Bit 25 Reserved, must be kept at reset value.

RM0008 Connectivity line devices: reset and clock control (RCC) 158

8.3.11 AHB peripheral clock r eset register (RCC_AHBRSTR)

Address offset: 0x28 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Bit 24 RMVF: Remove reset flag Set by software to clear the reset flags. 0: No effect 1: Clear the reset flags Bits 23:2 Reserved, must be kept at reset value. Bit 1 LSIRDY: Internal low speed oscillator ready Set and cleared by hardware to indicate when the internal RC 40 kHz oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after 3 internal 40 kHz RC oscillator clock cycles. 0: Internal RC 40 kHz oscillator not ready 1: Internal RC 40 kHz oscillator ready Bit 0 LSION: Internal low speed oscillator enable Set and cleared by software. 0: Internal RC 40 kHz oscillator OFF 1: Internal RC 40 kHz oscillator ON 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. ETHMAC RST Res. OTGFSR ST Reserved rw rw Bits 31:15 Reserved, must be kept at reset value. Bit 14 ETHMACRST Ethernet MAC reset Set and cleared by software. 0: No effect 1: Reset ETHERNET MAC Bit 13 Reserved, must be kept at reset value. Bit 12 OTGFSRST USB OTG FS reset Set and cleared by software. 0: No effect 1: Reset USB OTG FS Bits 11:0 Reserved, must be kept at reset value.

Connectivity line devices: reset and clock control (RCC) RM0008 154/1134 RM0008 Rev 20

8.3.12 Clock configurati on register2 (RCC_CFGR2)

Address offset: 0x2C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved I2S3SR C I2S2SR C PREDIV 1SRC rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PLL3MUL[3:0] PLL2MUL[3:0] PREDIV2[3:0] PREDIV1[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:19 Reserved, must be kept at reset value. Bit 18 I2S3SRC: I2S3 clock source Set and cleared by software to select I2S3 clock source. This bit must be valid before enabling I2S3 clock. 0: System clock (SYSCLK) selected as I2S3 clock entry 1: PLL3 VCO clock selected as I2S3 clock entry Bit 17 I2S2SRC: I2S2 clock source Set and cleared by software to select I2S2 clock source. This bit must be valid before enabling I2S2 clock. 0: System clock (SYSCLK) selected as I2S2 clock entry 1: PLL3 VCO clock selected as I2S2 clock entry Bit 16 PREDIV1SRC: PREDIV1 entry clock source Set and cleared by software to select PREDIV1 clock source. This bit can be written only when PLL is disabled. 0: HSE oscillator clock selected as PREDIV1 clock entry 1: PLL2 selected as PREDIV1 clock entry Bits 15:12 PLL3MUL[3:0]: PLL3 Multiplication Factor Set and cleared by software to control PLL3 multiplication factor. These bits can be written only when PLL3 is disabled. 00xx: Reserved 010x: Reserved 0110: PLL3 clock entry x 8 0111: PLL3 clock entry x 9 1000: PLL3 clock entry x 10 1001: PLL3 clock entry x 11 1010: PLL3 clock entry x 12 1011: PLL3 clock entry x 13 1100: PLL3 clock entry x 14 1101: Reserved 1110: PLL3 clock entry x 16 1111: PLL3 clock entry x 20

RM0008 Connectivity line devices: reset and clock control (RCC) 158 Bits 11:8 PLL2MUL[3:0]: PLL2 Multiplication Factor Set and cleared by software to control PLL2 multiplication factor. These bits can be written only when PLL2 is disabled. 00xx: Reserved 010x: Reserved 0110: PLL2 clock entry x 8 0111: PLL2 clock entry x 9 1000: PLL2 clock entry x 10 1001: PLL2 clock entry x 11 1010: PLL2 clock entry x 12 1011: PLL2 clock entry x 13 1100: PLL2 clock entry x 14 1101: Reserved 1110: PLL2 clock entry x 16 1111: PLL2 clock entry x 20 Bits 7:4 PREDIV2[3:0]: PREDIV2 division factor Set and cleared by software to select PREDIV2 division factor. These bits can be written only when both PLL2 and PLL3 are disabled. 0000: PREDIV2 input clock not divided 0001: PREDIV2 input clock divided by 2 0010: PREDIV2 input clock divided by 3 0011: PREDIV2 input clock divided by 4 0100: PREDIV2 input clock divided by 5 0101: PREDIV2 input clock divided by 6 0110: PREDIV2 input clock divided by 7 0111: PREDIV2 input clock divided by 8 1000: PREDIV2 input clock divided by 9 1001: PREDIV2 input clock divided by 10 1010: PREDIV2 input clock divided by 11 1011: PREDIV2 input clock divided by 12 1100: PREDIV2 input clock divided by 13 1101: PREDIV2 input clock divided by 14 1110: PREDIV2 input clock divided by 15 1111: PREDIV2 input clock divided by 16

8.3.13 RCC register map

The following table gives the RCC register map and the reset values. RCC_CFGR register changes Bit(0) accordingly. Table 19. RCC register map and reset values

Table 19. RCC register map and reset values (continued)

Refer to Table 3 on page 50 for the register boundary addresses.

RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 196

9 General-purpose and al ternate-function I/Os

(GPIOs and AFIOs) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This section applies to the whole STM32F10xxx family, unless otherwise specified.

9.1 GPIO functional description

Each of the general-purpose I/O ports has two 32-bit configuration registers (GPIOx_CRL, GPIOx_CRH), two 32-bit data registers (GPIOx_IDR, GPIOx_ODR), a 32-bit set/reset register (GPIOx_BSRR), a 16-bit reset register (GPIOx_BRR) and a 32-bit locking register (GPIOx_LCKR). Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software in several modes:

Input floating
Input pull-up
Input-pull-down
Analog
Output open-drain
Output push-pull
Alternate function push-pull
Alternate function open-drain Each I/O port bit is freely programmable, however the I/O port registers have to be accessed as 32-bit words (half-word or byte accesses are not allowed). The purpose of the GPIOx_BSRR and GPIOx_BRR registers is to allow atomic read/modify accesses to any of the GPIO registers. This way, there is no risk that an IRQ occurs between the read and the modify access. Figure 13 shows the basic structure of an I/O Port bit.

9.1.1 General-purpose I/O (GPIO)

configured in Input Floating mode (CNFx[1:0]=01b, MODEx[1:0]=00b). mode (only the N-MOS is activated when outputting 0).

9.1.2 Atomic bit set or reset

Table 20. Port bit configuration table Table 21. Output MODE bits

00 Reserved

01 Maximum output speed 10 MHz

10 Maximum output speed 2 MHz

11 Maximum output speed 50 MHz

General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 162/1134 RM0008 Rev 20 or for reset only GPIOx_BRR) to select the bits to modify. The unselected bits will not be modified.

9.1.3 External interrupt/wakeup lines

All ports have external interrupt capability. To use external interrupt lines, the port must be configured in input mode. For more information on external interrupts, refer to Section 10.2: External interrupt/event controller (EXTI) and Section 10.2.3: Wakeup event management.

9.1.4 Alternate functions (AF)

It is necessary to program the Port Bit Configuration Register before using a default alternate function.

For alternate function inputs, the port must be configured in Input mode (floating, pull- up or pull-down) and the input pin must be driven externally. Note: It is also possible to emulate the AFI input pin by software by programming the GPIO controller. In this case, the port should be configured in Alternate Function Output mode. And obviously, the corresponding port should not be driven externally as it will be driven by the software using the GPIO controller.
For alternate function outputs, the port must be configured in Alternate Function Output mode (Push-Pull or Open-Drain).
For bidirectional Alternate Functions, the port bit must be configured in Alternate Function Output mode (Push-Pull or Open-Drain). In this case the input driver is configured in input floating mode If a port bit is configured as Alternate Function Output, this disconnects the output register and connects the pin to the output signal of an on-chip peripheral. If software configures a GPIO pin as Alternate Function Output, but peripheral is not activated, its output is not specified.

9.1.5 Software remapping of I/O alternate functions

To optimize the number of peripheral I/O functions for different device packages, it is possible to remap some alternate functions to some other pins. This is achieved by software, by programming the corresponding registers (refer to AFIO registers. In that case, the alternate functions are no longer mapped to their original assignations.

9.1.6 GPIO locking mechanism

The locking mechanism allows the IO configuration to be frozen. When the LOCK sequence has been applied on a port bit, it is no longer possible to modify the value of the port bit until the next reset.

9.1.7 Input configuration

The Output Buffer is disabled
The Schmitt Trigger Input is activated
The weak pull-up and pull-down resistors are activated or not depending on input configuration (pull-up, pull-down or floating):
The data present on the I/O pin is sampled into the Input Data Register every APB2 clock cycle
A read access to the Input Data Register obtains the I/O State. Figure 15 shows the Input Configuration of the I/O Port bit.

Figure 15. Input floating/pull up/pull down configurations

V DD_FT is a potential specific to 5-Volt tolerant I/Os, and different from VDD.

9.1.8 Output configuration

The Output Buffer is enabled: – Open Drain Mode: A “0” in the Output register activates the N-MOS while a “1” in the Output register leaves the port in Hi-Z (the P-MOS is never activated) – Push-Pull Mode: A “0” in the Output register activates the N-MOS while a “1” in the Output register activates the P-MOS
The Schmitt Trigger Input is activated.
The weak pull-up and pull-down resistors are disabled.
The data present on the I/O pin is sampled into the Input Data Register every APB2 clock cycle
A read access to the Input Data Register gets the I/O state in open drain mode
A read access to the Output Data register gets the last written value in Push-Pull mode Figure 16 shows the Output configuration of the I/O Port bit. I/O pin TTL Schmitt trigger VSS VDD or VDD_FT(1) protection diode protection diode on input driver output driver Input data register Output data registerRead/write Read Bit set/reset registers Write on/off on/off VDD VSS ai14783

Figure 16. Output configuration

V DD_FT is a potential specific to 5-Volt tolerant I/Os, and different from VDD.

9.1.9 Alternate function configuration

The Output Buffer is turned on in Open Drain or Push-Pull configuration
The Output Buffer is driven by the signal coming from the peripheral (alternate function out)
The Schmitt Trigger Input is activated
The weak pull-up and pull-down resistors are disabled.
The data present on the I/O pin is sampled into the Input Data Register every APB2 clock cycle
A read access to the Input Data Register gets the I/O state in open drain mode
A read access to the Output Data register gets the last written value in Push-Pull mode Figure 17 shows the Alternate Function Configuration of the I/O Port bit. Also, refer to Section 9.4: AFIO registers for further information. A set of Alternate Function I/O registers allows the user to remap some alternate functions to different pins. Refer to Section 9.3: Alternate function I/O and debug configuration (AFIO). Push-pull or Open-drain Output control I/O pin VDD VSS TTL Schmitt trigger VSS VDD or VDD_FT(1) Protection diode Protection diode on Input driver Output driver P-MOS N-MOS Input data register Output data registerRead/write Read Bit set/reset registers Write ai14784

Figure 17. Alternate function configuration

V DD_FT is a potential specific to 5-Volt tolerant I/Os, and different from VDD.

9.1.10 Analog configuration

The Output Buffer is disabled.
The Schmitt Trigger Input is de-activated providing zero consumption for every analog value of the I/O pin. The output of the Schmitt Trigger is forced to a constant value (0).
The weak pull-up and pull-down resistors are disabled.
Read access to the Input Data Register gets the value “0”. Figure 18 shows the high impedance-analog configuration of the I/O Port bit. Alternate Function Output Alternate Function Input push-pull or open-drainFrom on-chip peripheral To on-chip peripheral Output control I/O pin VDD VSS TTL Schmitt trigger VSS VDD or VDD_FT(1) Protection diode Protection diode on Input driver Output driver P-MOS N-MOS Input data register Output data registerRead/write Read Bit set/reset registers Write ai14785

Figure 18. High impedance-analog configuration

9.1.11 GPIO configurati ons for device peripherals

Table 22 to Table 33 give the GPIO configurations of the device peripherals. Table 22. Advanced timers TIM1 and TIM8 Table 23. General-purpose timers TIM2/3/4/5 Table 24. USARTs

The USART_TX pin can also be confi gured as alternate function open drain.

Table 25. SPI Table 26. I2S Table 24. USARTs (continued)

Table 27. I2C Table 28. bxCAN Table 29. USB(1)

This table applies to low-, medi um-, high and XL-density devices only.

the USB internal transceiver. Table 26. I2S (continued) Table 30. OTG_FS pin configuration(1)

The GPIO configuration of the ADC inputs should be analog.

This table applies to c onnectivity line devices only.
For the OTG_FS_VBUS pin (PA9) to be used by anot her shared peripheral or as a general-purpose IO, the

PHY Power-down mode has to be active (clear bit 16 in the OTG_FS_GCCFG register). Table 30. OTG_FS pin configuration(1) (continued) Table 31. SDIO Figure 19. ADC / DAC Table 32. FSMC

Table 33. Other IOs

RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 196

9.2 GPIO registers

Refer to Section 2.2 on page 45 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 9.2.1 Port configuration regi ster low (GPIOx_CRL) (x=A..G) Address offset: 0x00 Reset value: 0x4444 4444 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CNF7[1:0] MODE7[1:0] CNF6[1:0] MODE6[1:0] CNF5[1:0] MODE5[1:0] CNF4[1:0] MODE4[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 CNF3[1:0] MODE3[1:0] CNF2[1:0] MODE2[1:0] CNF1[1:0] MODE1[1:0] CNF0[1:0] MODE0[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:30, 27:26, 11:10, 7:6, 3:2 CNFy[1:0]: Port x configuration bits (y= 0 .. 7) These bits are written by software to configure the corresponding I/O port. Refer to Table 20: Port bit configuration table. In input mode (MODE[1:0]=00): 00: Analog mode 01: Floating input (reset state) 10: Input with pull-up / pull-down 11: Reserved In output mode (MODE[1:0] > 00): 00: General purpose output push-pull 01: General purpose output Open-drain 10: Alternate function output Push-pull 11: Alternate function output Open-drain Bits 29:28, 25:24, 9:8, 5:4, 1:0 MODEy[1:0]: Port x mode bits (y= 0 .. 7) These bits are written by software to configure the corresponding I/O port. Refer to Table 20: Port bit configuration table. 00: Input mode (reset state) 01: Output mode, max speed 10 MHz. 10: Output mode, max speed 2 MHz. 11: Output mode, max speed 50 MHz.

General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 172/1134 RM0008 Rev 20 9.2.2 Port configuration regist er high (GPIOx_CRH) (x=A..G) Address offset: 0x04 Reset value: 0x4444 4444 9.2.3 Port input data regi ster (GPIOx_IDR) (x=A..G) Address offset: 0x08h Reset value: 0x0000 XXXX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CNF15[1:0] MODE15[1:0] CNF14[1:0] MODE14[1:0] CNF13[1:0] MODE13[1:0] CNF12[1:0] MODE12[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 CNF11[1:0] MODE11[1:0] CNF10[1:0] MODE10[1:0] CNF9[1:0] MODE9[1:0] CNF8[1:0] MODE8[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:30, 27:26, 11:10, 7:6, 3:2 CNFy[1:0]: Port x configuration bits (y= 8 .. 15) These bits are written by software to configure the corresponding I/O port. Refer to Table 20: Port bit configuration table. In input mode (MODE[1:0]=00): 00: Analog mode 01: Floating input (reset state) 10: Input with pull-up / pull-down 11: Reserved In output mode (MODE[1:0] > 00): 00: General purpose output push-pull 01: General purpose output Open-drain 10: Alternate function output Push-pull 11: Alternate function output Open-drain Bits 29:28, 25:24, 9:8, 5:4, 1:0 MODEy[1:0]: Port x mode bits (y= 8 .. 15) These bits are written by software to configure the corresponding I/O port. Refer to Table 20: Port bit configuration table. 00: Input mode (reset state) 01: Output mode, max speed 10 MHz. 10: Output mode, max speed 2 MHz. 11: Output mode, max speed 50 MHz. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 IDR15 IDR14 IDR13 IDR12 IDR11 IDR10 IDR9 IDR8 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0 rrrrrrr r r r rrrrrr Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 IDRy: Port input data (y= 0 .. 15) These bits are read only and can be accessed in Word mode only. They contain the input value of the corresponding I/O port.

RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 196 9.2.4 Port output data register (GPIOx_ODR) (x=A..G) Address offset: 0x0C Reset value: 0x0000 0000 9.2.5 Port bit set/r eset register (GPIOx_BSRR) (x=A..G) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 ODR15 ODR14 ODR13 ODR12 ODR11 ODR10 ODR9 ODR8 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 ODRy: Port output data (y= 0 .. 15) These bits can be read and written by software and can be accessed in Word mode only. Note: For atomic bit set/reset, the ODR bits can be individually set and cleared by writing to the GPIOx_BSRR register (x = A .. G). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 wwwwwwwww w w w w www 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 BS15 BS14 BS13 BS12 BS11 BS10 BS9 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 BS0 wwwwwwwww w w w w www Bits 31:16 BRy: Port x Reset bit y (y= 0 .. 15) These bits are write-only and can be accessed in Word mode only. 0: No action on the corresponding ODRx bit 1: Reset the corresponding ODRx bit Note: If both BSx and BRx are set, BSx has priority. Bits 15:0 BSy: Port x Set bit y (y= 0 .. 15) These bits are write-only and can be accessed in Word mode only. 0: No action on the corresponding ODRx bit 1: Set the corresponding ODRx bit

General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 174/1134 RM0008 Rev 20 9.2.6 Port bit reset regi ster (GPIOx_BRR) (x=A..G) Address offset: 0x14 Reset value: 0x0000 0000 9.2.7 Port configuration lock re gister (GPIOx_LCKR) (x=A..G) This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit it is no longer possible to modify the value of the port bit until the next reset. Each lock bit freezes the corresponding 4 bits of the control register (CRL, CRH). Address offset: 0x18 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 wwwwwwwww w w w w www Bits 31:16 Reserved Bits 15:0 BRy: Port x Reset bit y (y= 0 .. 15) These bits are write-only and can be accessed in Word mode only. 0: No action on the corresponding ODRx bit 1: Reset the corresponding ODRx bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved LCKK rw 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 LCK15 LCK14 LCK13 LCK12 LCK11 LCK10 LCK9 LCK8 LCK7 LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 LCK0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 196

9.3 Alternate function I/O an d debug configuration (AFIO)

To optimize the number of peripherals available for the 64-pin or the 100-pin or the 144-pin package, it is possible to remap some alternate functions to some other pins. This is achieved by software, by programming the AF remap and debug I/O configuration register (AFIO_MAPR). In this case, the alternate functions are no longer mapped to their original assignations.

9.3.1 Using OSC32_IN/OS C32_OUT pins as GPIO ports PC14/PC15

The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general-purpose I/O PC14 and PC15, respectively, when the LSE oscillator is off. The LSE has priority over the GP IOs function. Note: The PC14/PC15 GPIO functionality is lost when the 1.8 V domain is powered off (by entering standby mode) or when the backup domain is supplied by VBAT (VDD no more supplied). In this case the IOs are set in analog mode. Refer to the note on IO usage restrictions in Section 5.1.2: Battery backup domain.

9.3.2 Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1

The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose I/O PD0/PD1 by programming the PD01_REMAP bit in the AF remap and debug I/O configuration register (AFIO_MAPR). This remap is available only on 36-, 48- and 64-pin packages (PD0 and PD1 are available on 100-pin and 144-pin packages, no need for remapping). Note: The external interrupt/eve nt function is not remapped. PD0 and PD1 cannot be used for external interrupt/event generation on 36-, 48- and 64-pin packages. Bits 31:17 Reserved Bit 16 LCKK[16]: Lock key This bit can be read anytime. It can only be modified using the Lock Key Writing Sequence. 0: Port configuration lock key not active 1: Port configuration lock key active. GPIOx_LCKR register is locked until the next reset. LOCK key writing sequence: Write 1 Write 0 Write 1 Read 0 Read 1 (this read is optional but confirms that the lock is active) Note: During the LOCK Key Writing sequence, the value of LCK[15:0] must not change. Any error in the lock sequence will abort the lock. Bits 15:0 LCKy: Port x Lock bit y (y= 0 .. 15) These bits are read write but can only be written when the LCKK bit is 0. 0: Port configuration not locked 1: Port configuration locked.

9.3.3 CAN1 alternate function remapping

D, remapping is not possible in devices delivered in 36-, 48- and 64-pin packages.

9.3.4 CAN2 alternate function remapping

9.3.5 JTAG/SWD alternate function remapping

The debug interface signals are mapped on the GPIO ports as shown in Table 36. Table 34. CAN1 alternate function remapping

CAN1_RX and CAN1_TX in connectivity line devices; CAN_RX and CAN_TX in other devices with a single
Remap not available on 36-pin package
This remapping is available onl y on 100-pin and 144-pin packages, when PD0 and PD1 are not remapped

Table 35. CAN2 alternate function remapping Table 36. Debug interface signals

configuration register (AFIO_MAPR). Refer to Table 37.

9.3.6 ADC alternate function remapping

Refer to AF remap and debug I/O configuration register (AFIO_MAPR). Table 37. Debug port mapping

000 Full SWJ (JTAG-DP + SW-DP)

001 Full SWJ (JTAG-DP + SW-DP)

010 JTAG-DP Disabled and

100 JTAG-DP Disabled and

Released only if not us ing asynchronous trace.

Table 38. ADC1 external trigger injected conversion alternate function remapping(1)

Remap available only for hi gh-density and XL-density devices.

Table 39. ADC1 external trigger regular conversion alternate function remapping(1)

Remap available only for hi gh-density and XL-density devices.

Table 40. ADC2 external trigger injected conversion alternate function remapping(1)

Remap available only for hi gh-density and XL-density devices.

9.3.7 Timer alternate function remapping

configuration register (AFIO_MAPR). Table 41. ADC2 external trigger regular conversion alternate function remapping(1)

Remap available only for high- density and XL-density devices.

Table 42. TIM5 alternate function remapping(1)

Remap available only for high-density, XL-density and connectivity line devices.

input for calibration purpose. Table 43. TIM4 alternate function remapping

Remap available only for 100-pin and for 144-pin package.

Table 44. TIM3 alternate function remapping

Remap available only for 64-pin, 100-pin and 144-pin packages.

Table 45. TIM2 alternate function remapping

Remap not available on 36-pin package.
TIM_CH1 and TIM_ETR share the same pin but cannot be used at the same time (which is why we have

this notation: TIM2_CH1_ETR). Table 46. TIM1 alternate function remapping

Remap available only for 100-pin and 144-pin packages.
Remap not available on 36-pin package.

Table 47. TIM9 remapping(1)

Refer to the AF remap and debug I/O configuration register Section 9.4.7: AF remap and debug I/O

configuration register2 (AFIO_MAPR2). Table 48. TIM10 remapping(1)

Refer to the AF remap and debug I/O configuration register Section 9.4.7: AF remap and debug I/O

configuration register2 (AFIO_MAPR2).

9.3.8 USART alternate function remapping

Refer to AF remap and debug I/O configuration register (AFIO_MAPR). Table 49. TIM11 remapping(1)

Refer to the AF remap and debug I/O configuration register Section 9.4.7: AF remap and debug I/O

configuration register2 (AFIO_MAPR2). Table 50. TIM13 remapping(1)

Refer to the AF remap and debug I/O configuration register Section 9.4.7: AF remap and debug I/O

configuration register2 (AFIO_MAPR2). Table 51. TIM14 remapping(1)

Refer to the AF remap and debug I/O configuration register Section 9.4.7: AF remap and debug I/O

configuration register2 (AFIO_MAPR2). Table 52. USART3 remapping

Remap available only for 64-pin, 100-pin and 144-pin packages
Remap available only for 100-pin and 144-pin packages.

Table 53. USART2 remapping

Remap available only for 100-pin and 144-pin packages.

9.3.9 I2C1 alternate function remapping

9.3.10 SPI1 alternat e function remapping

9.3.11 SPI3/I2S3 alternate function remapping

available only in connectivity line devices.

9.3.12 Ethernet alte rnate function remapping

only in connectivity line devices. Table 54. USART1 remapping Table 55. I2C1 remapping

Remap not available on 36-pin package.

Table 56. SPI1 remapping Table 57. SPI3/I2S3 remapping

Table 58. ETH remapping

RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 196

9.4 AFIO registers

Refer to Section 2.2 on page 45 for a list of abbreviations used in register descriptions. Note: To read/write the AFIO_EVCR, AFIO_MAPR and AFIO_EXTICRX registers, the AFIO clock should first be enabled. Refer to Section 7.3.7: APB2 peripheral clock enable register (RCC_APB2ENR). The peripheral registers have to be accessed by words (32-bit).

9.4.1 Event control register (AFIO_EVCR)

Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 Reserved EVOE PORT[2:0] PIN[3:0] rw rw rw rw rw rw rw rw Bits 31:8 Reserved Bit 7 EVOE: Event output enable Set and cleared by software. When set the EVENTOUT Cortex® output is connected to the I/O selected by the PORT[2:0] and PIN[3:0] bits. Bits 6:4 PORT[2:0]: Port selection Set and cleared by software. Select the port used to output the Cortex® EVENTOUT signal. Note: The EVENTOUT signal output capability is not extended to ports PF and PG. 000: PA selected 001: PB selected 010: PC selected 011: PD selected 100: PE selected Bits 3:0 PIN[3:0]: Pin selection (x = A .. E) Set and cleared by software. Select the pin used to output the Cortex ® EVENTOUT signal. 0000: Px0 selected 0001: Px1 selected 0010: Px2 selected 0011: Px3 selected ... 1111: Px15 selected

General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 184/1134 RM0008 Rev 20

9.4.2 AF remap and de bug I/O configuration register (AFIO_MAPR)

Address offset: 0x04 Reset value: 0x0000 0000 Memory map and bit definitions for low-, medium- high- and XL-density devices: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved SWJ_ CFG[2:0] Reserved ADC2_E TRGREG _REMAP ADC2_E TRGINJ_ REMAP ADC1_E TRGREG _REMAP ADC1_E TRGINJ_ REMAP TIM5CH4 _IREMAP www rw rw rw rw rw 1 51 4 1 31 21 1 1 0 98765 4 3210 PD01_ REMAP CAN_REMAP [1:0] TIM4_ REMAP TIM3_REMAP [1:0] TIM2_REMAP [1:0] TIM1_REMAP [1:0] USART3_ REMAP[1:0] USART2_ REMAP USART1_ REMAP I2C1_ REMAP SPI1_ REMAP rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:27 Reserved Bits 26:24 SWJ_CFG[2:0]: Serial wire JTAG configuration These bits are write-only (when read, the value is undefined). They are used to configure the SWJ and trace alternate function I/Os. The SWJ (Serial Wire JTAG) supports JTAG or SWD access to the Cortex® debug port. The default state after reset is SWJ ON without trace. This allows JTAG or SW mode to be enabled by sending a specific sequence on the JTMS / JTCK pin. 000: Full SWJ (JTAG-DP + SW-DP): Reset State 001: Full SWJ (JTAG-DP + SW-DP) but without NJTRST 010: JTAG-DP Disabled and SW-DP Enabled 100: JTAG-DP Disabled and SW-DP Disabled Other combinations: no effect Bits 23:21 Reserved. Bits 20 ADC2_ETRGREG_REMAP: ADC 2 external trigger regular conversion remapping Set and cleared by software. This bit controls the trigger input connected to ADC2 external trigger regular conversion. When this bit is reset, the ADC2 external trigger regular conversion is connected to EXTI11. When this bit is set, the ADC2 external event regular conversion is connected to TIM8_TRGO. Bits 19 ADC2_ETRGINJ_REMAP: ADC 2 external trigger injected conversion remapping Set and cleared by software. This bit controls the trigger input connected to ADC2 external trigger injected conversion. When this bit is reset, the ADC2 external trigger injected conversion is connected to EXTI15. When this bit is set, the ADC2 external event injected conversion is connected to TIM8_Channel4. Bits 18 ADC1_ETRGREG_REMAP: ADC 1 external trigger regular conversion remapping Set and cleared by software. This bit controls the trigger input connected to ADC1 External trigger regular conversion. When reset the ADC1 External trigger regular conversion is connected to EXTI11. When set the ADC1 External Event regular conversion is connected to TIM8 TRGO.

RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 196 Bits 17 ADC1_ETRGINJ_REMAP: ADC 1 External trigger injected conversion remapping Set and cleared by software. This bit controls the trigger input connected to ADC1 External trigger injected conversion. When reset the ADC1 External trigger injected conversion is connected to EXTI15. When set the ADC1 External Event injected conversion is connected to TIM8 Channel4. Bits 16 TIM5CH4_IREMAP: TIM5 channel4 internal remap Set and cleared by software. This bit controls the TIM5_CH4 internal mapping. When reset the timer TIM5_CH4 is connected to PA3. When set the LSI internal clock is connected to TIM5_CH4 input for calibration purpose. Note: This bit is available only in high density value line devices. Bit 15 PD01_REMAP: Port D0/Port D1 mapping on OSC_IN/OSC_OUT This bit is set and cleared by software. It controls the mapping of PD0 and PD1 GPIO functionality. When the HSE oscillator is not used (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and OSC_OUT. This is available only on 36-, 48- and 64-pin packages (PD0 and PD1 are available on 100-pin and 144-pin packages, no need for remapping). 0: No remapping of PD0 and PD1 1: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT, Bits 14:13 CAN_REMAP[1:0]: CAN alternate function remapping These bits are set and cleared by software. They control the mapping of alternate functions CAN_RX and CAN_TX in devices with a single CAN interface. 00: CAN_RX mapped to PA11, CAN_TX mapped to PA12 01: Not used 10: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package) 11: CAN_RX mapped to PD0, CAN_TX mapped to PD1 Bit 12 TIM4_REMAP: TIM4 remapping This bit is set and cleared by software. It controls the mapping of TIM4 channels 1 to 4 onto the GPIO ports. 0: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9) 1: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15) Note: TIM4_ETR on PE0 is not re-mapped. Bits 11:10 TIM3_REMAP[1:0]: TIM3 remapping These bits are set and cleared by software. They control the mapping of TIM3 channels 1 to 4 on the GPIO ports. 00: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) 01: Not used 10: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) 11: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) Note: TIM3_ETR on PE0 is not re-mapped. Bits 9:8 TIM2_REMAP[1:0]: TIM2 remapping These bits are set and cleared by software. They control the mapping of TIM2 channels 1 to 4 and external trigger (ETR) on the GPIO ports. 00: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) 01: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) 10: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) 11: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)

General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 186/1134 RM0008 Rev 20 Bits 7:6 TIM1_REMAP[1:0]: TIM1 remapping These bits are set and cleared by software. They control the mapping of TIM1 channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) on the GPIO ports. 00: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) 01: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) 10: not used 11: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) Bits 5:4 USART3_REMAP[1:0]: USART3 remapping These bits are set and cleared by software. They control the mapping of USART3 CTS, RTS,CK,TX and RX alternate functions on the GPIO ports. 00: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) 01: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) 10: not used 11: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) Bit 3 USART2_REMAP: USART2 remapping This bit is set and cleared by software. It controls the mapping of USART2 CTS, RTS,CK,TX and RX alternate functions on the GPIO ports. 0: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4) 1: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7) Bit 2 USART1_REMAP: USART1 remapping This bit is set and cleared by software. It controls the mapping of USART1 TX and RX alternate functions on the GPIO ports. 0: No remap (TX/PA9, RX/PA10) 1: Remap (TX/PB6, RX/PB7) Bit 1 I2C1_REMAP: I2C1 remapping This bit is set and cleared by software. It controls the mapping of I2C1 SCL and SDA alternate functions on the GPIO ports. 0: No remap (SCL/PB6, SDA/PB7) 1: Remap (SCL/PB8, SDA/PB9) Bit 0 SPI1_REMAP: SPI1 remapping This bit is set and cleared by software. It controls the mapping of SPI1 NSS, SCK, MISO, MOSI alternate functions on the GPIO ports. 0: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7) 1: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)

RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 196 Memory map and bit definitions for connectivity line devices: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. PTP_P PS_RE MAP TIM2IT R1_ IREMA P SPI3_ REMA P Res. SWJ_ CFG[2:0] MII_R MII_SE L CAN2_ REMA P ETH_R EMAP Reserved TIM5C H4_IRE MAP rw rw rw w w w rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD01_ REMA P CAN1_REMAP [1:0] TIM4_ REMA P TIM3_REMAP [1:0] TIM2_REMAP [1:0] TIM1_REMAP [1:0] USART3_ REMAP[1:0] USART2 REMAP USART1 REMAP I2C1_ REMA P SPI1_ REMA P rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 31 Reserved, must be kept at reset value. Bit 30 PTP_PPS_REMAP: Ethernet PTP PPS remapping This bit is set and cleared by software. It enables the Ethernet MAC PPS_PTS to be output on the PB5 pin. 0: PTP_PPS not output on PB5 pin. 1: PTP_PPS is output on PB5 pin. Note: This bit is available only in connectivity line devices and is reserved otherwise. Bit 29 TIM2ITR1_IREMAP: TIM2 internal trigger 1 remapping This bit is set and cleared by software. It controls the TIM2_ITR1 internal mapping. 0: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes. 1: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes. Note: This bit is available only in connectivity line devices and is reserved otherwise. Bit 28 SPI3_REMAP: SPI3/I2S3 remapping This bit is set and cleared by software. It controls the mapping of SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD alternate functions on the GPIO ports. 0: No remap (SPI_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5) 1: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12) Note: This bit is available only in connectivity line devices and is reserved otherwise. Bit 27 Reserved Bits 26:24 SWJ_CFG[2:0]: Serial wire JTAG configuration These bits are write-only (when read, the value is undefined). They are used to configure the SWJ and trace alternate function I/Os. The SWJ (Serial Wire JTAG) supports JTAG or SWD access to the Cortex ® debug port. The default state after reset is SWJ ON without trace. This allows JTAG or SW mode to be enabled by sending a specific sequence on the JTMS / JTCK pin. 000: Full SWJ (JTAG-DP + SW-DP): Reset State 001: Full SWJ (JTAG-DP + SW-DP) but without NJTRST 010: JTAG-DP Disabled and SW-DP Enabled 100: JTAG-DP Disabled and SW-DP Disabled Other combinations: no effect

General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 188/1134 RM0008 Rev 20 Bit 23 MII_RMII_SEL: MII or RMII selection This bit is set and cleared by software. It configures the Ethernet MAC internally for use with an external MII or RMII PHY. 0: Configure Ethernet MAC for connection with an MII PHY 1: Configure Ethernet MAC for connection with an RMII PHY Note: This bit is available only in connectivity line devices and is reserved otherwise. Bit 22 CAN2_REMAP: CAN2 I/O remapping This bit is set and cleared by software. It controls the CAN2_TX and CAN2_RX pins. 0: No remap (CAN2_RX/PB12, CAN2_TX/PB13) 1: Remap (CAN2_RX/PB5, CAN2_TX/PB6) Note: This bit is available only in connectivity line devices and is reserved otherwise. Bit 21 ETH_REMAP: Ethernet MAC I/O remapping This bit is set and cleared by software. It controls the Ethernet MAC connections with the PHY. 0: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1) 1: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12) Note: This bit is available only in connectivity line devices and is reserved otherwise. Bits 20:17 Reserved Bits 16 TIM5CH4_IREMAP: TIM5 channel4 internal remap Set and cleared by software. This bit controls the TIM5_CH4 internal mapping. When reset the timer TIM5_CH4 is connected to PA3. When set the LSI internal clock is connected to TIM5_CH4 input for calibration purpose. Bit 15 PD01_REMAP: Port D0/Port D1 mapping on OSC_IN/OSC_OUT This bit is set and cleared by software. It controls the mapping of PD0 and PD1 GPIO functionality. When the HSE oscillator is not used (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and OSC_OUT. This is available only on 36-, 48- and 64-pin packages (PD0 and PD1 are available on 100-pin and 144-pin packages, no need for remapping). 0: No remapping of PD0 and PD1 1: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT, Bits 14:13 CAN1_REMAP[1:0]: CAN1 alternate function remapping These bits are set and cleared by software. They control the mapping of alternate functions CAN1_RX and CAN1_TX. 00: CAN1_RX mapped to PA11, CAN1_TX mapped to PA12 01: Not used 10: CAN1_RX mapped to PB8, CAN1_TX mapped to PB9 (not available on 36-pin package) 11: CAN1_RX mapped to PD0, CAN1_TX mapped to PD1 Bit 12 TIM4_REMAP: TIM4 remapping This bit is set and cleared by software. It controls the mapping of TIM4 channels 1 to 4 onto the GPIO ports. 0: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9) 1: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15) Note: TIM4_ETR on PE0 is not re-mapped.

RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 196 Bits 11:10 TIM3_REMAP[1:0]: TIM3 remapping These bits are set and cleared by software. They control the mapping of TIM3 channels 1 to 4 on the GPIO ports. 00: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) 01: Not used 10: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) 11: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) Note: TIM3_ETR on PE0 is not re-mapped. Bits 9:8 TIM2_REMAP[1:0]: TIM2 remapping These bits are set and cleared by software. They control the mapping of TIM2 channels 1 to 4 and external trigger (ETR) on the GPIO ports. 00: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) 01: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) 10: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) 11: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) Bits 7:6 TIM1_REMAP[1:0]: TIM1 remapping These bits are set and cleared by software. They control the mapping of TIM1 channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) on the GPIO ports. 00: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) 01: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) 10: not used 11: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) Bits 5:4 USART3_REMAP[1:0]: USART3 remapping These bits are set and cleared by software. They control the mapping of USART3 CTS, RTS,CK,TX and RX alternate functions on the GPIO ports. 00: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) 01: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) 10: not used 11: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) Bit 3 USART2_REMAP: USART2 remapping This bit is set and cleared by software. It controls the mapping of USART2 CTS, RTS,CK,TX and RX alternate functions on the GPIO ports. 0: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4) 1: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)

General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 190/1134 RM0008 Rev 20 Bit 2 USART1_REMAP: USART1 remapping This bit is set and cleared by software. It controls the mapping of USART1 TX and RX alternate functions on the GPIO ports. 0: No remap (TX/PA9, RX/PA10) 1: Remap (TX/PB6, RX/PB7) Bit 1 I2C1_REMAP: I2C1 remapping This bit is set and cleared by software. It controls the mapping of I2C1 SCL and SDA alternate functions on the GPIO ports. 0: No remap (SCL/PB6, SDA/PB7) 1: Remap (SCL/PB8, SDA/PB9) Bit 0 SPI1_REMAP: SPI1 remapping This bit is set and cleared by software. It controls the mapping of SPI1 NSS, SCK, MISO, MOSI alternate functions on the GPIO ports. 0: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7) 1: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)

RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 196

9.4.3 External interrupt configur ation register 1 (AFIO_EXTICR1)

Address offset: 0x08 Reset value: 0x0000

9.4.4 External interrupt configur ation register 2 (AFIO_EXTICR2)

Address offset: 0x0C Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 0 to 3) These bits are written by software to select the source input for EXTIx external interrupt. Refer to Section 10.2.5: External interrupt/event line mapping 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin 0011: PD[x] pin 0100: PE[x] pin 0101: PF[x] pin 0110: PG[x] pin31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 4 to 7) These bits are written by software to select the source input for EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin 0011: PD[x] pin 0100: PE[x] pin 0101: PF[x] pin 0110: PG[x] pin

General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 192/1134 RM0008 Rev 20

9.4.5 External interrupt configur ation register 3 (AFIO_EXTICR3)

Address offset: 0x10 Reset value: 0x0000

9.4.6 External interrupt configur ation register 4 (AFIO_EXTICR4)

Address offset: 0x14 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 8 to 11) These bits are written by software to select the source input for EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin 0011: PD[x] pin 0100: PE[x] pin 0101: PF[x] pin 0110: PG[x] pin31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 12 to 15) These bits are written by software to select the source input for EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin 0011: PD[x] pin 0100: PE[x] pin 0101: PF[x] pin 0110: PG[x] pin

RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 196

9.4.7 AF remap and de bug I/O configuration register2 (AFIO_MAPR2)

Address offset: 0x1C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 1 5 1 4 1 3 1 2 1 1 1 0 98765 4 3210 Reserved FSM C_NA DV TIM14_ REMA P TIM13_ REMA P TIM11_ REMA P TIM10_ REMA P TIM9_ REMA P Reserved rw rw rw rw rw rw Bits 31:11 Reserved. Bit 10 FSMC_NADV: NADV connect/disconnect This bit is set and cleared by software. It controls the use of the optional FSMC_NADV signal. 0: The NADV signal is connected to the output (default) 1: The NADV signal is not connected. The I/O pin can be used by another peripheral. Bit 9 TIM14_REMAP: TIM14 remapping This bit is set and cleared by software. It controls the mapping of the TIM14_CH1 alternate function onto the GPIO ports. 0: No remap (PA7) 1: Remap (PF9) Bit 8 TIM13_REMAP: TIM13 remapping This bit is set and cleared by software. It controls the mapping of the TIM13_CH1 alternate function onto the GPIO ports. 0: No remap (PA6) 1: Remap (PF8) Bit 7 TIM11_REMAP: TIM11 remapping This bit is set and cleared by software. It controls the mapping of the TIM11_CH1 alternate function onto the GPIO ports. 0: No remap (PB9) 1: Remap (PF7) Bit 6 TIM10_REMAP: TIM10 remapping This bit is set and cleared by software. It controls the mapping of the TIM10_CH1 alternate function onto the GPIO ports. 0: No remap (PB8) 1: Remap (PF6) Bit 5 TIM9_REMAP: TIM9 remapping This bit is set and cleared by software. It controls the mapping of the TIM9_CH1 and TIM9_CH2 alternate functions onto the GPIO ports. 0: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3) 1: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6) Bits 4:0 Reserved.

9.5 GPIO and AFIO register maps

The following tables give the GPIO and AFIO register map and the reset values. Refer to Table 3 on page 50 for the register boundary addresses. Table 59. GPIO register map and reset values

Table 60. AFIO register map and reset values

2 Reserved

Table 60. AFIO register map and reset values (continued)

RM0008 Interrupts and events 214

10 Interrupts and events

10.1 Nested vectored in terrupt controller (NVIC)

Features

68 (not including the sixteen Cortex®-M3 interrupt lines)
16 programmable priority levels (4 bits of interrupt priority are used)
Low-latency exception and interrupt handling
Power management control
Implementation of System Control Registers The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to STM32F10xxx Cortex®-M3 programming manual (see Related documents on page 1).

10.1.1 SysTick calibr ation value register

The SysTick calibration value is set to 9000, which gives a reference time base of 1 ms with the SysTick clock set to 9 MHz (max HCLK/8).

10.1.2 Interrupt and exception vectors

Table 61. Vector table for connectivity line devices

Table 61. Vector table for connectivity line devices (continued)

Table 62. Vector table for XL-density devices

Table 62. Vector table for XL-density devices (continued)

Table 63. Vector table for other STM32F10xxx devices

Table 63. Vector table for other STM32F10xxx devices (continued)

10.2 External interrupt /event controller (EXTI)

line devices, or 19 edge detectors in other devices for generating event/interrupt requests.

10.2.1 Main features

Independent trigger and mask on each interrupt/event line
Dedicated status bit for each interrupt line
Generation of up to 20 software event/interrupt requests
Detection of external signal with pulse width lower than APB2 clock period. Refer to the electrical characteristics section of the datasheet for details on this parameter.

10.2.2 Block diagram

The block diagram is shown in Figure 20. Figure 20. External interrupt/event controller block diagram

Interrupts and events RM0008 208/1134 RM0008 Rev 20

10.2.3 Wakeup event management

The STM32F10xxx is able to handle external or internal events in order to wake up the core (WFE). The wakeup event can be generated either by:

enabling an interrupt in the peripheral control register but not in the NVIC, and enabling the SEVONPEND bit in the Cortex®-M3 System Control register. When the MCU resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.
or configuring an external or internal EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is not set. In connectivity line devices, Ethernet wakeup events also have the WFE wakeup capability. To use an external line as a wakeup event, refer to Section 10.2.4: Functional description.

10.2.4 Functional description

To generate the interrupt, the interrupt line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the interrupt request by writing a ‘1’ to the corresponding bit in the interrupt mask register. When the selected edge occurs on the external interrupt line, an interrupt request is generated. The pending bit corresponding to the interrupt line is also set. This request is reset by writing a ‘1’ in the pending register. To generate the event, the event line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the event request by writing a ‘1’ to the corresponding bit in the event mask register. When the selected edge occurs on the event line, an event pulse is generated. The pending bit corresponding to the event line is not set An interrupt/event request can also be generated by software by writing a ‘1’ in the software interrupt/event register. Hardware interrupt selection To configure the 20 lines as interrupt sources, use the following procedure:

Configure the mask bits of the 20 Interrupt lines (EXTI_IMR)
Configure the Trigger Selection bits of the Interrupt lines (EXTI_RTSR and EXTI_FTSR)
Configure the enable and mask bits that control the NVIC IRQ channel mapped to the External Interrupt Controller (EXTI) so that an interrupt coming from one of the 20 lines can be correctly acknowledged. Hardware event selection To configure the 20 lines as event sources, use the following procedure:
Configure the mask bits of the 20 Event lines (EXTI_EMR)
Configure the Trigger Selection bits of the Event lines (EXTI_RTSR and EXTI_FTSR)

RM0008 Interrupts and events 214 Software interrupt/event selection The 20 lines can be configured as software interrupt/event lines. The following is the procedure to generate a software interrupt.

Configure the mask bits of the 20 Interrupt/Event lines (EXTI_IMR, EXTI_EMR)
Set the required bit of the software interrupt register (EXTI_SWIER)

10.2.5 External interr upt/event line mapping

The 112 GPIOs are connected to the 16 external interrupt/event lines in the following manner:

Figure 21. External interrupt/event GPIO mapping

To configure the AFIO_EXTICRx for the mapping of external interrupt/event lines onto GPIOs, the AFIO

clock enable register (RCC_APB2ENR) for connectivity line devices.

EXTI line 16 is connected to the PVD output
EXTI line 17 is connected to the RTC Alarm event
EXTI line 18 is connected to the USB Wakeup event
EXTI line 19 is connected to the Ethernet Wakeup event (available only in connectivity line devices) EXTI0 PA0 PB0 PC0 PD0 PE0 EXTI0[3:0] bits in AFIO_EXTICR1 register PF0 PG0 EXTI1 PA1 PB1 PC1 PD1 PE1 EXTI1[3:0] bits in AFIO_EXTICR1 register PF1 PG1 EXTI15 PA15 PB15 PC15 PD15 PE15 EXTI15[3:0] bits in AFIO_EXTICR4 register PF15 PG15

RM0008 Interrupts and events 214

10.3 EXTI registers

Refer to Section 2.2 on page 45 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit).

10.3.1 Interrupt mask register (EXTI_IMR)

Address offset: 0x00 Reset value: 0x0000 0000

10.3.2 Event mask re gister (EXTI_EMR)

Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved MR19 MR18 MR17 MR16 rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:20 Reserved, must be kept at reset value (0). Bits 19:0 MRx: Interrupt Mask on line x 0: Interrupt request from Line x is masked 1: Interrupt request from Line x is not masked Note: Bit 19 is used in connectivity line devices only and is reserved otherwise. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved MR19 MR18 MR17 MR16 rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:20 Reserved, must be kept at reset value (0). Bits 19:0 MRx: Event mask on line x 0: Event request from Line x is masked 1: Event request from Line x is not masked Note: Bit 19 is used in connectivity line devices only and is reserved otherwise.

Interrupts and events RM0008 212/1134 RM0008 Rev 20

10.3.3 Rising trigger select ion register (EXTI_RTSR)

Address offset: 0x08 Reset value: 0x0000 0000 Note: The external wakeup lines are edge triggere d, no glitches must be generated on these lines. If a rising edge on external interrupt line occurs during writing of EXTI_RTSR register, the pending bit will not be set. Rising and Falling edge triggers can be set for the same interrupt line. In this configuration, both generate a trigger condition.

10.3.4 Falling trigger select ion register (EXTI_FTSR)

Address offset: 0x0C Reset value: 0x0000 0000 Note: The external wakeup lines are edge triggere d, no glitches must be generated on these lines. If a falling edge on external interrupt line occurs during writing of EXTI_FTSR register, the pending bit will not be set. Rising and Falling edge triggers can be set for the same interrupt line. In this configuration, both generate a trigger condition. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved TR19 TR18 TR17 TR16 rw rw rw rw 1 5 1 4 1 3 1 2 1 1 1 0 9 87654321 0 TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:20 Reserved, must be kept at reset value (0). Bits 19:0 TRx: Rising trigger event configuration bit of line x 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line. Note: Bit 19 is used in connectivity line devices only and is reserved otherwise. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved TR19 TR18 TR17 TR16 rw rw rw rw 1 5 1 4 1 3 1 2 1 1 1 0 9 87654321 0 TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:20 Reserved, must be kept at reset value (0). Bits 19:0 TRx: Falling trigger event configuration bit of line x 0: Falling trigger disabled (for Event and Interrupt) for input line 1: Falling trigger enabled (for Event and Interrupt) for input line. Note: Bit 19 used in connectivity line devices and is reserved otherwise.

RM0008 Interrupts and events 214

10.3.5 Software interrupt ev ent register (EXTI_SWIER)

Address offset: 0x10 Reset value: 0x0000 0000

10.3.6 Pending register (EXTI_PR)

Address offset: 0x14 Reset value: undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved SWIER SWIER SWIER SWIER rw rw rw rw 1 5 1 4 1 3 1 2 1 1 1 0 9 87654321 0 SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:20 Reserved, must be kept at reset value (0). Bits 19:0 SWIERx: Software interrupt on line x If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit when it is set to '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation. This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a 1 into the bit). Note: Bit 19 used in connectivity line devices and is reserved otherwise. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PR19 PR18 PR17 PR16 rc_w1 rc_w1 rc_w1 rc_w1 1 5 1 4 1 3 1 2 1 1 1 0 9 87654321 0 PR15 PR14 PR13 PR12 PR11 PR10 PR9 PR8 PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Bits 31:20 Reserved, must be kept at reset value (0). Bits 19:0 PRx: Pending bit 0: No trigger request occurred 1: selected trigger request occurred This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a ‘1’ into the bit. Note: Bit 19 is used in connectivity line devices only and is reserved otherwise.

10.3.7 EXTI register map

are used in connectivity line devices and reserved otherwise. Refer to Table 3 on page 50 for the register boundary addresses. Table 64. External interrupt/event controller register map and reset values

RM0008 Analog-to-digital converter (ADC) 253

11 Analog-to-digital converter (ADC)

11.1 ADC introduction

The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 18 multiplexed channels allowing it measure signals from sixteen external and two internal sources. A/D conversion of the various channels can be performed in single, continuous, scan or discontinuous mode. The result of the ADC is stored in a left-aligned or right-aligned 16-bit data register. The analog watchdog feature allows the application to detect if the input voltage goes outside the user-defined high or low thresholds. The ADC input clock is generated from the PCLK2 clock divided by a prescaler and it must not exceed 14 MHz, refer to Figure 8 for low-, medium-, high- and XL-density devices, and to Figure 11 for connectivity line devices.

Analog-to-digital converter (ADC) RM0008 216/1134 RM0008 Rev 20

11.2 ADC main features

12-bit resolution
Interrupt generation at End of Conversion, End of Injected conversion and Analog watchdog event
Single and continuous conversion modes
Scan mode for automatic conversion of channel 0 to channel ‘n’
Self-calibration
Data alignment with in-built data coherency
Channel by channel programmable sampling time
External trigger option for both regular and injected conversion
Discontinuous mode
Dual mode (on devices with 2 ADCs or more)
ADC conversion time: – STM32F103xx performance line devices: 1 µs at 56 MHz (1.17 µs at 72 MHz) – STM32F101xx access line devices: 1 µs at 28 MHz (1.55 µs at 36 MHz) – STM32F102xx USB access line devices: 1.2 µs at 48 MHz – STM32F105xx and STM32F107xx devices: 1 µs at 56 MHz (1.17 µs at 72 MHz)
ADC supply requirement: 2.4 V to 3.6 V
ADC input range: V REF- ≤ VIN ≤ VREF+
DMA request generation during regular channel conversion The block diagram of the ADC is shown in Figure 22. Note: V REF-,if available (depending on package), must be tied to VSSA.

11.3 ADC functional description

Figure 22 shows a single ADC block diagram and Table 65 gives the ADC pin description.

Figure 22. Single ADC block diagram

ADC3 has regular and injected conversion triggers different from those of ADC1 and ADC2.
TIM8_CH4 and TIM8_TRGO with their corresponding remap bits exist only in High-density and XL-density

11.3.1 ADC on-off control

ADON bit is set for the first time, it wakes up the ADC from Power Down mode. ADON bit. In this mode the ADC consumes almost no power (only a few µA).

11.3.2 ADC clock

refer to Low-, medium-, high- and XL-density reset and clock control (RCC) for more details.

11.3.3 Channel selection

following order: Ch3, Ch8, Ch2, Ch2, Ch0, Ch2, Ch2, Ch15.

The regular group is composed of up to 16 conversions. The regular channels and their order in the conversion sequence must be selected in the ADC_SQRx registers. The total number of conversions in the regular group must be written in the L[3:0] bits in the ADC_SQR1 register.
The injected group is composed of up to 4 conversions. The injected channels and their order in the conversion sequence must be selected in the ADC_JSQR register. The total number of conversions in the injected group must be written in the L[1:0] bits in the ADC_JSQR register. If the ADC_SQRx or ADC_JSQR registers are modified during a conversion, the current conversion is reset and a new start pulse is sent to the ADC to convert the new chosen group.

Table 65. ADC pins

2.4 V ≤ VREF+ ≤ VDDA

V DDA and VSSA have to be connected to VDD and VSS, respectively.
For full details about the ADC I/O pins, refer to the “Pinouts and pin descriptions” section of the

corresponding device datasheet.

RM0008 Analog-to-digital converter (ADC) 253 Temperature sensor/VREFINT internal channels The Temperature sensor is connected to channel ADCx_IN16 and the internal reference voltage VREFINT is connected to ADCx_IN17. These two internal channels can be selected and converted as injected or regular channels. Note: The sensor and V REFINT are only available on the master ADC1 peripheral.

11.3.4 Single conversion mode

In Single conversion mode the ADC does one conversion. This mode is started either by setting the ADON bit in the ADC_CR2 register (for a regular channel only) or by external trigger (for a regular or injected channel), while the CONT bit is 0. Once the conversion of the selected channel is complete:

If a regular channel was converted: – The converted data is stored in the 16-bit ADC_DR register – The EOC (End Of Conversion) flag is set – and an interrupt is generated if the EOCIE is set.
If an injected channel was converted: – The converted data is stored in the 16-bit ADC_DRJ1 register – The JEOC (End Of Conversi on Injected) flag is set – and an interrupt is generated if the JEOCIE bit is set. The ADC is then stopped.

11.3.5 Continuous conversion mode

In continuous conversion mode ADC starts another conversion as soon as it finishes one. This mode is started either by external trigger or by setting the ADON bit in the ADC_CR2 register, while the CONT bit is 1. After each conversion:

If a regular channel was converted: – The converted data is stored in the 16-bit ADC_DR register – The EOC (End Of Conversion) flag is set – An interrupt is generated if the EOCIE is set.
If an injected channel was converted: – The converted data is stored in the 16-bit ADC_DRJ1 register – The JEOC (End Of Conversi on Injected) flag is set – An interrupt is generated if the JEOCIE bit is set.

11.3.6 Timing diagram

As shown in Figure 23, the ADC needs a stabilization time of tSTAB before it starts converting accurately. After the start of ADC conversion and after 14 clock cycles, the EOC flag is set and the 16-bit ADC Data register contains the result of the conversion.

Figure 23. Timing diagram

11.3.7 Analog watchdog

enabled by using the AWDIE bit in the ADC_CR1 register. ADC_CR2 register. The comparison is done before the alignment (see Section 11.5). ADC_CR1 register as shown in Table 66. Figure 24. Analog watchdog guarded area Table 66. Analog watchdog channel selection

11.3.8 Scan mode

This mode is used to scan a group of analog channels. group channel but continues again from the first selected group channel. The injected channel converted data is always stored in the ADC_JDRx registers.

11.3.9 Injected channel management

Start conversion of a group of regular channels either by external trigger or by setting

the ADON bit in the ADC_CR2 register.

If an external injected trigger occurs during the regular group channel conversion, the
Then, the regular group channel conversi on is resumed from the last interrupted

interrupt it but the regular sequence is executed at the end of the injected sequence. Figure 25 shows the timing diagram. must be 29 ADC clock cycles.

Selected by AWDCH[4:0] bits

Table 66. Analog watchdog channel selection (continued)

programmed in the ADC_SQRx and ADC_JSQR registers. In this mode, external trigger on injected channels must be disabled. channels are continuously converted. inserted when switching from regular to injected sequence (respectively injected to regular). When the ADC clock prescaler is set to 2, the delay is 2 ADC clock periods. Note: It is not possible to use both auto-inj ected and discontinuous modes simultaneously. Figure 25. Injected conversion latency

The maximum latency value can be found in the el ectrical characteristics of the STM32F101xx and

11.3.10 Discontinuous mode

the DISCNUM[2:0] bits in the ADC_CR1 register. defined by the L[3:0] bits in the ADC_SQR1 register.

RM0008 Analog-to-digital converter (ADC) 253 conversion second trigger: sequence converted 3, 6, 7. An EOC event is generated at each conversion third trigger: sequence converted 9, 10. An EOC event is generated at each conversion fourth trigger: sequence converted 0, 1, 2. An EOC event is generated at each conversion Note: When a regular group is co nverted in discontinuous mode, no rollover will occur. When all sub groups are converted, the next trigger starts conversion of the first sub-group. In the example above, the fourth trigger reconverts the first sub-group channels 0, 1 and 2. Injected group This mode is enabled by setting the JDISCEN bit in the ADC_CR1 register. It can be used to convert the sequence selected in the ADC_JSQR register, channel by channel, after an external trigger event. When an external trigger occurs, it starts the next channel conversions selected in the ADC_JSQR registers until all the conversions in the sequence are done. The total sequence length is defined by the JL[1:0] bits in the ADC_JSQR register. Example: n = 1, channels to be converted = 1, 2, 3 first trigger: channel 1 converted second trigger: channel 2 converted third trigger: channel 3 converted and EOC and JEOC events generated fourth trigger: channel 1 Note: When all injected channels are converted, the next trigger starts the conversion of the first injected channel. In the example above, the fourth trigger reconverts the first injected channel 1. It is not possible to use both auto-injected and discontinuous modes simultaneously. The user must avoid setting discontinuous mode for both regular and injected groups together. Discontinuous mode must be enabled only for one group conversion.

11.4 Calibration

The ADC has an built-in self calibration mode. Calibration significantly reduces accuracy errors due to internal capacitor bank variations. During calibration, an error-correction code (digital word) is calculated for each capacitor, and during all subsequent conversions, the error contribution of each capacitor is removed using this code. Calibration is started by setting the CAL bit in the ADC_CR2 register. Once calibration is over, the CAL bit is reset by hardware and normal conversion can be performed. It is recommended to calibrate the ADC once at power-on. The calibration codes are stored in the ADC_DR as soon as the calibration phase ends. Note: It is recommended to perform a calibration after each power-up. Before starting a calibration, the ADC must have been in power-on state (ADON bit = ‘1’) for at least two ADC clock cycles.

Figure 26. Calibration timing diagram

11.5 Data alignment

ALIGN bit in the ADC_CR2 register selects the alignment of data stored after conversion. Data can be left or right aligned as shown in Figure 27. and Figure 28. For regular group channels no offset is subtracted so only twelve bits are significant. Figure 27. Right alignment of data Figure 28. Left alignment of data

11.6 Channel-by-channel programmable sample time

sampled with a different sample time.

11.7 Conversion on external trigger

possible events can trigger conversion for the regular and injected groups. edge of the signal can start the conversion. Table 67. External trigger for regular channels for ADC1 and ADC2

The TIM8_TRGO event exists only in high-density and XL-density devices.
The selection of the external trigger EXTI line11 or TIM8_TRGO event for regular channels is done through

Table 68. External trigger for injected channels for ADC1 and ADC2

The TIM8_CC4 event exists only in high-density and XL-density devices.
The selection of the external trigger EXTI line15 or TIM8_CC4 event for injected channels is done through

Table 69. External trigger for regular channels for ADC3 Table 70. External trigger for injected channels for ADC3

RM0008 Analog-to-digital converter (ADC) 253 The software source trigger events can be generated by setting a bit in a register (SWSTART and JSWSTART in ADC_CR2). A regular group conversion can be interrupted by an injected trigger.

11.8 DMA request

Since converted regular channels value are stored in a unique data register, it is necessary to use DMA for conversion of more than one regular channel. This avoids the loss of data already stored in the ADC_DR register. Only the end of conversion of a regular channel generates a DMA request, which allows the transfer of its converted data from the ADC_DR register to the destination location selected by the user. Note: Only ADC1 and ADC3 have this DMA capabilit y. ADC2-converted data can be transferred in dual ADC mode using DMA thanks to master ADC1.

Analog-to-digital converter (ADC) RM0008 228/1134 RM0008 Rev 20

11.9 Dual ADC mode

In devices with two ADCs or more, dual ADC mode can be used (see Figure 29). In dual ADC mode the start of conversion is triggered alternately or simultaneously by the ADC1 master to the ADC2 slave, depending on the mode selected by the DUALMOD[2:0] bits in the ADC1_CR1 register. Note: In dual mode, when configuring conversion to be triggered by an external event, the user must set the trigger for the master only and set a software trigger for the slave to prevent spurious triggers to start unwanted slave conversion. However, external triggers must be enabled on both master and slave ADCs. The following six possible modes are implemented: – Injected simultaneous mode – Regular simultaneous mode – Fast interleaved mode – Slow interleaved mode – Alternate trigger mode – Independent mode It is also possible to use the previous modes combined in the following ways: – Injected simultaneous mode + Regular simultaneous mode – Regular simultaneous mode + Alternate trigger mode – Injected simultaneous mode + Interleaved mode Note: In dual ADC mode, to read the slave conver ted data on the master data register, the DMA bit must be enabled even if it is not used to transfer converted regular channel data.

Figure 29. Dual ADC block diagram(1)

External triggers are present on ADC2 but ar e not shown for the purposes of this diagram.
In some dual ADC modes, the ADC1 data register (ADC1_DR) contains both ADC1 and ADC2 regular converted data over

11.9.1 Injected simultaneous mode

The converted data is stored in the ADC_JDRx registers of each ADC interface.
An JEOC interrupt is generated (if enabled on one of the two ADC interfaces) when the ADC1/ADC2 injected channels are all converted. Note: In simultaneous mode, exactly the same sampling time should be configured for the two channels that will be sampled simultaneously by ACD1 and ADC2.

Figure 30. Injected simultaneous mode on 4 channels

11.9.2 Regular simultaneous mode

ADC1_CR2 register). A simultaneous trigger is provided to the ADC2. two ADCs when converting the same channel).

A 32-bit DMA transfer request is generated (if DMA bit is set) which transfers to SRAM the ADC1_DR 32-bit register containing the ADC2 converted data in the upper halfword and the ADC1 converted data in the lower halfword.
An EOC interrupt is generated (if enabled on one of the two ADC interfaces) when ADC1/ADC2 regular channels are all converted. Note: In regular simultaneous mode, exactly the same sampling time should be configured for the two channels that will be sampled simultaneously by ACD1 and ADC2.

Figure 31. Regular simultaneous mode on 16 channels

11.9.3 Fast interleaved mode

ADC2 starts immediately and
ADC1 starts after a delay of 7 ADC clock cycles. If CONT bit is set on both ADC1 and ADC2 the selected regular channels of both ADCs are continuously converted. After an EOC interrupt is generated by ADC1 (if enabled through the EOCIE bit) a 32-bit DMA transfer request is generated (if the DMA bit is set) which transfers to SRAM the ADC1_DR 32-bit register containing the ADC2 converted data in the upper halfword and the ADC1 converted data in the lower halfword. Note: The maximum sampling time allowed is <7 ADCCLK cycles to avoid the overlap between ADC1 and ADC2 sampling phases in the event that they convert the same channel.

Figure 32. Fast interleaved mode on 1 channel in continuous conversion mode

11.9.4 Slow interleaved mode

ADC2 starts immediately and
ADC1 starts after a delay of 14 ADC clock cycles.
ADC2 starts after a second delay of 14 ADC cycles, and so on. Note: The maximum sampling time allowed is <14 ADCCLK cycles to avoid an overlap with the next conversion. After an EOC interrupt is generated by ADC1 (if enabled through the EOCIE bit) a 32-bit DMA transfer request is generated (if the DMA bit is set) which transfers to SRAM the ADC1_DR 32-bit register containing the ADC2 converted data in the upper halfword and the ADC1 converted data in the lower halfword. A new ADC2 start is automatically generated after 28 ADC clock cycles CONT bit can not be set in the mode since it continuously converts the selected regular channel. Note: The application must ensure that no exte rnal trigger for injected channel occurs when interleaved mode is enabled. $'& $'& 7ULJJHU $'&&/. F\\FOHV (QGRIFRQYHUVLRQRQ$'& &RQYHUVLRQ 6DPSOLQJ (QGRIFRQYHUVLRQRQ$'&

Figure 33. Slow interleaved mode on 1 channel

11.9.5 Alternate trigger mode

comes from the injected group mux of ADC1.

When the first trigger occurs, all injected group channels in ADC1 are converted.
When the second trigger arrives, all injected group channels in ADC2 are converted
and so on. A JEOC interrupt, if enabled, is generated after all injected group channels of ADC1 are converted. A JEOC interrupt, if enabled, is generated after all injected group channels of ADC2 are converted. If another external trigger occurs after all injected group channels have been converted then the alternate trigger process restarts by converting ADC1 injected group channels.

Figure 34. Alternate trigger: injected channel group of each ADC

When the first trigger occurs, the first injected channel in ADC1 is converted.
When the second trigger arrives, the first injected channel in ADC2 are converted
and so on.... A JEOC interrupt, if enabled, is generated after all injected group channels of ADC1 are converted. A JEOC interrupt, if enabled, is generated after all injected group channels of ADC2 are converted. CH0 ADC2 ADC1 Trigger End of conversion on ADC1 Conversion Sampling

14 ADCCLK

28 ADCCLK

the alternate trigger process restarts. Figure 35. Alternate trigger: 4 injected channels (each ADC) in discontinuous model

11.9.6 Independent mode

11.9.7 Combined regular/injected simultaneous mode

conversion of an injected group. configured for the two channels that will be sampled simultaneously by ACD1 and ADC2.

11.9.8 Combined regular simult aneous + alternate trigger mode

interrupting a regular simultaneous conversion. synchronously at the end of the injected conversion.

Figure 36. Alternate + Regular simultaneous will be ignored. Figure 37 shows the behavior in this case (the second trigger is ignored). Figure 37. Case of trigger occurring during injected conversion

11.9.9 Combined injected simultaneous + interleaved

ADC clock periods, instead of 7 clock periods followed by 7 clock periods.

Figure 38. Interleaved single channel with injected sequence CH11, CH12

11.10 Temperature sensor

time for the temperature sensor is 17.1 µs. The block diagram of the temperature sensor is shown in Figure 39. When not in use, this sensor can be put in power down mode. line varies from chip to chip due to process variation (up to 45 °C from one chip to another). an external temperature sensor part should be used. Figure 39. Temperature sensor and VREFINT channel block diagram

Select the ADCx_IN16 input channel.
Select a sample time of 17.1 µs
Set the TSVREFE bit in the ADC control register 2 (ADC_CR2) to wake up the

temperature sensor from power down mode.

Start the ADC conversion by setting the ADON bit (or by external trigger).
Obtain the temperature using the following formula:

Temperature (in °C) = {(V25 - VSENSE) / Avg_Slope} + 25. the delay, the ADON and TSVREFE bits should be set at the same time.

11.11 ADC interrupts

mapped onto a separate interrupt vector.

JSTRT (Start of conversion for injected group channels)
STRT (Start of conversion for regular group channels)

Table 71. ADC interrupts

RM0008 Analog-to-digital converter (ADC) 253

11.12 ADC registers

Refer to Section 2.2 on page 45 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit).

11.12.1 ADC status register (ADC_SR)

Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 Reserved STRT JSTRT JEOC EOC AWD rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 31:5 Reserved, must be kept at reset value. Bit 4 STRT: Regular channel Start flag This bit is set by hardware when regular channel conversion starts. It is cleared by software. 0: No regular channel conversion started 1: Regular channel conversion has started Bit 3 JSTRT: Injected channel Start flag This bit is set by hardware when injected channel group conversion starts. It is cleared by software. 0: No injected group conversion started 1: Injected group conversion has started Bit 2 JEOC: Injected channel end of conversion This bit is set by hardware at the end of all injected group channel conversion. It is cleared by software. 0: Conversion is not complete 1: Conversion complete Bit 1 EOC: End of conversion This bit is set by hardware at the end of a group channel conversion (regular or injected). It is cleared by software or by reading the ADC_DR. 0: Conversion is not complete 1: Conversion complete Bit 0 AWD: Analog watchdog flag This bit is set by hardware when the converted voltage crosses the values programmed in the ADC_LTR and ADC_HTR registers. It is cleared by software. 0: No Analog watchdog event occurred 1: Analog watchdog event occurred

Analog-to-digital converter (ADC) RM0008 238/1134 RM0008 Rev 20

11.12.2 ADC control register 1 (ADC_CR1)

Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved AWDE N JAWDE N Reserved DUALMOD[3:0] rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DISCNUM[2:0] JDISCE N DISC EN JAUTO AWD SGL SCAN JEOC IE AWDIE EOCIE AWDCH[4:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:24 Reserved, must be kept at reset value. Bit 23 AWDEN: Analog watchdog enable on regular channels This bit is set/reset by software. 0: Analog watchdog disabled on regular channels 1: Analog watchdog enabled on regular channels Bit 22 JAWDEN: Analog watchdog enable on injected channels This bit is set/reset by software. 0: Analog watchdog disabled on injected channels 1: Analog watchdog enabled on injected channels Bits 21:20 Reserved, must be kept at reset value. Bits 19:16 DUALMOD[3:0]: Dual mode selection These bits are written by software to select the operating mode. 0000: Independent mode. 0001: Combined regular simultaneous + injected simultaneous mode 0010: Combined regular simultaneous + alternate trigger mode 0011: Combined injected simultaneous + fast interleaved mode 0100: Combined injected simultaneous + slow Interleaved mode 0101: Injected simultaneous mode only 0110: Regular simultaneous mode only 0111: Fast interleaved mode only 1000: Slow interleaved mode only 1001: Alternate trigger mode only Note: These bits are reserved in ADC2 and ADC3. In dual mode, a change of channel configuration generates a restart that can produce a loss of synchronization. It is recommended to disable dual mode before any configuration change. Bits 15:13 DISCNUM[2:0]: Discontinuous mode channel count These bits are written by software to define the number of regular channels to be converted in discontinuous mode, after receiving an external trigger. 000: 1 channel 001: 2 channels 111: 8 channels

RM0008 Analog-to-digital converter (ADC) 253 Bit 12 JDISCEN: Discontinuous mode on injected channels This bit set and cleared by software to enable/disable discontinuous mode on injected group channels 0: Discontinuous mode on injected channels disabled 1: Discontinuous mode on injected channels enabled Bit 11 DISCEN: Discontinuous mode on regular channels This bit set and cleared by software to enable/disable Discontinuous mode on regular channels. 0: Discontinuous mode on regular channels disabled 1: Discontinuous mode on regular channels enabled Bit 10 JAUTO: Automatic Injected Group conversion This bit set and cleared by software to enable/disable automatic injected group conversion after regular group conversion. 0: Automatic injected group conversion disabled 1: Automatic injected group conversion enabled Bit 9 AWDSGL: Enable the watchdog on a single channel in scan mode This bit set and cleared by software to enable/disable the analog watchdog on the channel identified by the AWDCH[4:0] bits. 0: Analog watchdog enabled on all channels 1: Analog watchdog enabled on a single channel Bit 8 SCAN: Scan mode This bit is set and cleared by software to enable/disable Scan mode. In Scan mode, the inputs selected through the ADC_SQRx or ADC_JSQRx registers are converted. 0: Scan mode disabled 1: Scan mode enabled Note: An EOC or JEOC interrupt is generated onl y on the end of conversion of the last channel if the corresponding EOCIE or JEOCIE bit is set Bit 7 JEOCIE: Interrupt enable for injected channels This bit is set and cleared by software to enable/disable the end of conversion interrupt for injected channels. 0: JEOC interrupt disabled 1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set.

Analog-to-digital converter (ADC) RM0008 240/1134 RM0008 Rev 20

11.12.3 ADC control register 2 (ADC_CR2)

Address offset: 0x08 Reset value: 0x0000 0000 Bit 6 AWDIE: Analog watchdog interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. 0: Analog watchdog interrupt disabled 1: Analog watchdog interrupt enabled Bit 5 EOCIE: Interrupt enable for EOC This bit is set and cleared by software to enable/disable the End of Conversion interrupt. 0: EOC interrupt disabled 1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set. Bits 4:0 AWDCH[4:0]: Analog watchdog channel select bits These bits are set and cleared by software. They select the input channel to be guarded by the Analog watchdog. 00000: ADC analog Channel0 00001: ADC analog Channel1 .... 01111: ADC analog Channel15 10000: ADC analog Channel16 10001: ADC analog Channel17 Other values reserved. Note: ADC1 analog Channel16 and Channel17 are internally connected to the temperature sensor and to V REFINT, respectively. ADC2 analog inputs Channel16 and Channel17 are internally connected to VSS. ADC3 analog inputs Channel9, Channel14, Channel15, Channel16 and Channel17 are connected to VSS. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved TSVRE FE SWSTA RT JSWST ART EXTTR IG EXTSEL[2:0] Res. rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 JEXTT RIG JEXTSEL[2:0] ALIGN Reserved DMA Reserved RST CAL CAL CONT ADON rw rw rw rw rw Res. rw rw rw rw rw

RM0008 Analog-to-digital converter (ADC) 253 Bits 31:24 Reserved, must be kept at reset value. Bit 23 TSVREFE: Temperature sensor and VREFINT enable This bit is set and cleared by software to enable/disable the temperature sensor and VREFINT channel. In devices with dual ADCs this bit is present only in ADC1. 0: Temperature sensor and VREFINT channel disabled 1: Temperature sensor and VREFINT channel enabled Bit 22 SWSTART: Start conversion of regular channels This bit is set by software to start conversion and cleared by hardware as soon as conversion starts. It starts a conversion of a group of regular channels if SWSTART is selected as trigger event by the EXTSEL[2:0] bits. 0: Reset state 1: Starts conversion of regular channels Bit 21 JSWSTART: Start conversion of injected channels This bit is set by software and cleared by software or by hardware as soon as the conversion starts. It starts a conversion of a group of injected channels (if JSWSTART is selected as trigger event by the JEXTSEL[2:0] bits. 0: Reset state 1: Starts conversion of injected channels Bit 20 EXTTRIG: External trigger conversion mode for regular channels This bit is set and cleared by software to enable/disable the external trigger used to start conversion of a regular channel group. 0: Conversion on external event disabled 1: Conversion on external event enabled Bits 19:17 EXTSEL[2:0]: External event select for regular group These bits select the external event used to trigger the start of conversion of a regular group: For ADC1 and ADC2, the assigned triggers are: 000: Timer 1 CC1 event 001: Timer 1 CC2 event 010: Timer 1 CC3 event 011: Timer 2 CC2 event 100: Timer 3 TRGO event 101: Timer 4 CC4 event 110: EXTI line 11/TIM8_TRGO event (TIM8_TRGO is available only in high-density and XL- density devices) 111: SWSTART For ADC3, the assigned triggers are: 000: Timer 3 CC1 event 001: Timer 2 CC3 event 010: Timer 1 CC3 event 011: Timer 8 CC1 event 100: Timer 8 TRGO event 101: Timer 5 CC1 event 110: Timer 5 CC3 event 111: SWSTART Bit 16 Reserved, must be kept at reset value.

Analog-to-digital converter (ADC) RM0008 242/1134 RM0008 Rev 20 Bit 15 JEXTTRIG: External trigger conversion mode for injected channels This bit is set and cleared by software to enable/disable the external trigger used to start conversion of an injected channel group. 0: Conversion on external event disabled 1: Conversion on external event enabled Bits 14:12 JEXTSEL[2:0]: External event select for injected group These bits select the external event used to trigger the start of conversion of an injected group: For ADC1 and ADC2 the assigned triggers are: 000: Timer 1 TRGO event 001: Timer 1 CC4 event 010: Timer 2 TRGO event 011: Timer 2 CC1 event 100: Timer 3 CC4 event 101: Timer 4 TRGO event 110: EXTI line15/TIM8_CC4 event (TIM8_CC4 is available only in high-density and XL- density devices) 111: JSWSTART For ADC3 the assigned triggers are: 000: Timer 1 TRGO event 001: Timer 1 CC4 event 010: Timer 4 CC3 event 011: Timer 8 CC2 event 100: Timer 8 CC4 event 101: Timer 5 TRGO event 110: Timer 5 CC4 event 111: JSWSTART Bit 11 ALIGN: Data alignment This bit is set and cleared by software. Refer to Figure 27.and Figure 28. 0: Right Alignment 1: Left Alignment Bits 10:9 Reserved, must be kept at reset value. Bit 8 DMA: Direct memory access mode This bit is set and cleared by software. Refer to the DMA controller chapter for more details. 0: DMA mode disabled 1: DMA mode enabled Only ADC1 and ADC3 can generate a DMA request. Bits 7:4 Reserved, must be kept at reset value. Bit 3 RSTCAL: Reset calibration This bit is set by software and cleared by hardware. It is cleared after the calibration registers are initialized. 0: Calibration register initialized. 1: Initialize calibration register. Note: If RSTCAL is set when conversion is ongoing, additional cycles are required to clear the calibration registers.

RM0008 Analog-to-digital converter (ADC) 253 Bit 2 CAL: A/D Calibration This bit is set by software to start the calibration. It is reset by hardware after calibration is complete. 0: Calibration completed 1: Enable calibration Bit 1 CONT: Continuous conversion This bit is set and cleared by software. If set conversion takes place continuously till this bit is reset. 0: Single conversion mode 1: Continuous conversion mode Bit 0 ADON: A/D converter ON / OFF This bit is set and cleared by software. If this bit holds a value of zero and a 1 is written to it then it wakes up the ADC from Power Down state. Conversion starts when this bit holds a value of 1 and a 1 is written to it. The application should allow a delay of t STAB between power up and start of conversion. Refer to Figure 23. 0: Disable ADC conversion/calibration and go to power down mode. 1: Enable ADC and to start conversion Note: If any other bit in this register apart from ADON is changed at the same time, then conversion is not triggered. This is to prevent triggering an erroneous conversion.

Analog-to-digital converter (ADC) RM0008 244/1134 RM0008 Rev 20

11.12.4 ADC sample time register 1 (ADC_SMPR1)

Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved SMP17[2:0] SMP16[2:0] SMP15[2:1] rw rw rw rw rw rw rw rw 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 SMP 15_0 SMP14[2:0] SMP13[2:0] SMP12[2:0] SMP11[2:0] SMP10[2:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:24 Reserved, must be kept at reset value. Bits 23:0 SMPx[2:0]: Channel x Sample time selection These bits are written by software to select the sample time individually for each channel. During sample cycles channel selection bits must remain unchanged. 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles 011: 28.5 cycles 100: 41.5 cycles 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles Note: ADC1 analog Channel16 and Channel 17 are internally connected to the temperature sensor and to V REFINT, respectively. ADC2 analog input Channel16 and Channel17 are internally connected to VSS. ADC3 analog inputs Channel14, Channel15, Channel16 and Channel17 are connected to VSS.

RM0008 Analog-to-digital converter (ADC) 253

11.12.5 ADC sample time register 2 (ADC_SMPR2)

Address offset: 0x10 Reset value: 0x0000 0000 11.12.6 ADC injected channel data o ffset register x (ADC_JOFRx) (x=1..4) Address offset: 0x14-0x20 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved SMP9[2:0] SMP8[2:0] SMP7[2:0] SMP6[2:0] SMP5[2:1] Res. rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 SMP 5_0 SMP4[2:0] SMP3[2:0] SMP2[2:0] SMP1[2:0] SMP0[2:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:30 Reserved, must be kept at reset value. Bits 29:0 SMPx[2:0]: Channel x Sample time selection These bits are written by software to select the sample time individually for each channel. During sample cycles channel selection bits must remain unchanged. 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles 011: 28.5 cycles 100: 41.5 cycles 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles Note: ADC3 analog input Channel9 is connected to V SS. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 Reserved JOFFSETx[11:0] rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 JOFFSETx[11:0]: Data offset for injected channel x These bits are written by software to define the offset to be subtracted from the raw converted data when converting injected channels. The conversion result can be read from in the ADC_JDRx registers.

Analog-to-digital converter (ADC) RM0008 246/1134 RM0008 Rev 20

11.12.7 ADC watchdog high thr eshold register (ADC_HTR)

Address offset: 0x24 Reset value: 0x0000 0FFF Note: The software can write to these regist ers when an ADC conversion is ongoing. The programmed value will be effective when the next conversion is complete. Writing to this register is performed with a write delay that can create uncertainty on the effective time at which the new value is programmed.

11.12.8 ADC watchdog low thr eshold register (ADC_LTR)

Address offset: 0x28 Reset value: 0x0000 0000 Note: The software can write to these regist ers when an ADC conversion is ongoing. The programmed value will be effective when the next conversion is complete. Writing to this register is performed with a write delay that can create uncertainty on the effective time at which the new value is programmed. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 Reserved HT[11:0] rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 HT[11:0]: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 Reserved LT[11:0] rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 LT[11:0]: Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog.

RM0008 Analog-to-digital converter (ADC) 253

11.12.9 ADC regular sequenc e register 1 (ADC_SQR1)

Address offset: 0x2C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved L[3:0] SQ16[4:1] rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:24 Reserved, must be kept at reset value. Bits 23:20 L[3:0]: Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence. 0000: 1 conversion 0001: 2 conversions 1111: 16 conversions Bits 19:15 SQ16[4:0]: 16th conversion in regular sequence These bits are written by software with the channel number (0..17) assigned as the 16th in the conversion sequence. Bits 14:10 SQ15[4:0]: 15th conversion in regular sequence Bits 9:5 SQ14[4:0]: 1fourth conversion in regular sequence Bits 4:0 SQ13[4:0]: 13th conversion in regular sequence

Analog-to-digital converter (ADC) RM0008 248/1134 RM0008 Rev 20

11.12.10 ADC regular sequenc e register 2 (ADC_SQR2)

Address offset: 0x30 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 SQ10_ rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:30 Reserved, must be kept at reset value. Bits 29:26 SQ12[4:0]: 12th conversion in regular sequence These bits are written by software with the channel number (0..17) assigned as the 12th in the sequence to be converted. Bits 24:20 SQ11[4:0]: 11th conversion in regular sequence Bits 19:15 SQ10[4:0]: 10th conversion in regular sequence Bits 14:10 SQ9[4:0]: 9th conversion in regular sequence Bits 9:5 SQ8[4:0]: 8th conversion in regular sequence Bits 4:0 SQ7[4:0]: 7th conversion in regular sequence

RM0008 Analog-to-digital converter (ADC) 253

11.12.11 ADC regular seque nce register 3 (ADC_SQR3)

Address offset: 0x34 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 SQ4_0 SQ3[4:0] SQ2[4:0] SQ1[4:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:30 Reserved, must be kept at reset value. Bits 29:25 SQ6[4:0]: 6th conversion in regular sequence These bits are written by software with the channel number (0..17) assigned as the 6th in the sequence to be converted. Bits 24:20 SQ5[4:0]: 5th conversion in regular sequence Bits 19:15 SQ4[4:0]: fourth conversion in regular sequence Bits 14:10 SQ3[4:0]: third conversion in regular sequence Bits 9:5 SQ2[4:0]: second conversion in regular sequence Bits 4:0 SQ1[4:0]: first conversion in regular sequence

Analog-to-digital converter (ADC) RM0008 250/1134 RM0008 Rev 20

11.12.12 ADC injected seque nce register (ADC_JSQR)

Address offset: 0x38 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved JL[1:0] JSQ4[4:1] rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 JSQ4_0 JSQ3[4:0] JSQ2[4:0] JSQ1[4:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:22 Reserved, must be kept at reset value. Bits 21:20 JL[1:0]: Injected sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence. 00: 1 conversion 01: 2 conversions 10: 3 conversions 11: 4 conversions Bits 19:15 JSQ4[4:0]: fourth conversion in injected sequence (when JL[1:0] = 3)(1) These bits are written by software with the channel number (0..17) assigned as the fourth in the sequence to be converted. Note: Unlike a regular conversion sequence, if JL[1:0] length is less than four, the channels are converted in a sequence starting from (4-JL). Example: ADC_JSQR[21:0] = 10 00011 00011 00111 00010 means that a scan conversion will convert the following channel sequence: 7, 3, 3. (not 2, 7, 3) Bits 14:10 JSQ3[4:0]: third conversion in injected sequence (when JL[1:0] = 3) Bits 9:5 JSQ2[4:0]: second conversion in injected sequence (when JL[1:0] = 3) Bits 4:0 JSQ1[4:0]: first conversion in injected sequence (when JL[1:0] = 3) 1. When JL=3 ( 4 injected conversions in the sequence r), the ADC converts the channels in this order: JSQ1[4:0] >> JSQ2[4:0] >> JSQ3[4:0] >> JSQ4[4:0] When JL=2 ( 3 injected conversions in the sequencer), the ADC converts the channels in this order: JSQ2[4:0] >> JSQ3[4:0] >> JSQ4[4:0] When JL=1 ( 2 injected conversions in the sequencer), the ADC converts the channels in this order: JSQ3[4:0] >> JSQ4[4:0] When JL=0 (1 injected conversion in the sequencer), the ADC converts only JSQ4[4:0] channel

RM0008 Analog-to-digital converter (ADC) 253 11.12.13 ADC injected data re gister x (ADC_JDRx) (x= 1..4) Address offset: 0x3C - 0x48 Reset value: 0x0000 0000

11.12.14 ADC regular data register (ADC_DR)

Address offset: 0x4C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 JDATA[15:0] rrrrrrr r r r rrrrrr Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 JDATA[15:0]: Injected data These bits are read only. They contain the conversion result from injected channel x. The data is left or right-aligned as shown in Figure 27 and Figure 28. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADC2DATA[15:0] rrrrrrr r r r rrrrrr 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 DATA[15:0] rrrrrrr r r r rrrrrr Bits 31:16 ADC2DATA[15:0]: ADC2 data In ADC1: In dual mode, these bits contain the regular data of ADC2. Refer to Section 11.9: Dual ADC mode. In ADC2 and ADC3: these bits are not used. Bits 15:0 DATA[15:0]: Regular data These bits are read only. They contain the conversion result from the regular channels. The data is left or right-aligned as shown in Figure 27 and Figure 28.

11.12.15 ADC register map

The following table summarizes the ADC registers. Table 72. ADC register map and reset values

Refer to Table 3 on page 50 for the register boundary addresses. Table 72. ADC register map and reset values (continued)

Digital-to-analog converter (DAC) RM0008 254/1134 RM0008 Rev 20

12 Digital-to-analog converter (DAC)

12.1 DAC introduction

The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data could be left- or right-aligned. The DAC has two output channels, each with its own converter. In dual DAC channel mode, conversions could be done independently or simultaneously when both channels are grouped together for synchronous update operation. An input reference pin V REF+ (shared with ADC) is available for better resolution.

12.2 DAC main features

Two DAC converters: one output channel each
Left or right data alignment in 12-bit mode
Synchronized update capability
Noise-wave generation
Triangular-wave generation
Dual DAC channel independent or simultaneous conversions
DMA capability for each channel
External triggers for conversion
Input voltage reference VREF+ The block diagram of a DAC channel is shown in Figure 40 and the pin description is given in Table 73.

Figure 40. DAC channel block diagram

In connectivity line devic es, the TIM8_TRGO trigger is replaced by TIM3_TRGO.

PA4 or PA5 pin should first be configured to analog (AIN). Table 73. DAC pins

Digital-to-analog converter (DAC) RM0008 256/1134 RM0008 Rev 20

12.3 DAC functional description

12.3.1 DAC channel enable

Each DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR register. The DAC channel is then enabled after a startup time tWAKEUP. Note: The ENx bit enables the analog DAC Chan nelx macrocell only. The DAC Channelx digital interface is enabled even if the ENx bit is reset.

12.3.2 DAC output buffer enable

The DAC integrates two output buffers that can be used to reduce the output impedance, and to drive external loads directly without having to add an external operational amplifier. Each DAC channel output buffer can be enabled and disabled using the corresponding BOFFx bit in the DAC_CR register.

12.3.3 DAC data format

Depending on the selected configuration mode, the data has to be written in the specified register as described below:

Single DAC channelx, there are three possibilities: – 8-bit right alignment: user has to load data into DAC_DHR8Rx [7:0] bits (stored into DHRx[11:4] bits) – 12-bit left alignment: user has to load data into DAC_DHR12Lx [15:4] bits (stored into DHRx[11:0] bits) – 12-bit right alignment: user has to load data into DAC_DHR12Rx [11:0] bits (stored into DHRx[11:0] bits) Depending on the loaded DAC_DHRyyyx register, the data written by the user will be shifted and stored into the DHRx (Data Holding Registerx, that are internal non-memory-mapped registers). The DHRx register will then be loaded into the DORx register either automatically, by software trigger or by an external event trigger.

Figure 41. Data registers in single DAC channel mode

Dual DAC channels, there are three possibilities: – 8-bit right alignment: data for DAC channel1 to be loaded into DAC_DHR8RD [7:0] bits (stored into DHR1[11:4] bits) and data for DAC channel2 to be loaded into DAC_DHR8RD [15:8] bits (stored into DHR2[11:4] bits) – 12-bit left alignment: data for DAC channel1 to be loaded into DAC_DHR12LD [15:4] bits (stored into DHR1[11:0] bits) and data for DAC channel2 to be loaded into DAC_DHR12LD [31:20] bits (stored into DHR2[11:0] bits) – 12-bit right alignment: data for DAC channel1 to be loaded into DAC_DHR12RD [11:0] bits (stored into DHR1[11:0] bits) and data for DAC channel2 to be loaded into DAC_DHR12RD [27:16] bits (stored into DHR2[11:0] bits) Depending on the loaded DAC_DHRyyyD register, the data written by the user will be shifted and stored into the DHR1 and DHR2 (Data Holding Registers, that are internal non- memory-mapped registers). The DHR1 and DHR2 registers will then be loaded into the DOR1 and DOR2 registers, respectively, either automatically, by software trigger or by an external event trigger.

Figure 42. Data registers in dual DAC channel mode

12.3.4 DAC conversion

DAC_DHR12Rx, DAC_DHR8RD, DAC_DHR12LD or DAC_DHR12LD). register is set) and a trigger occurs, the transfer is performed three APB1 clock cycles later.

Figure 43. Timing diagram for conversion with trigger disabled TEN = 0

12.3.5 DAC output voltage

Digital inputs are converted to output voltages on a linear conversion between 0 and VREF+.

12.3.6 DAC trigger selection

possible events, will trigger conversion, as shown in Table 74. cycles after the trigger occurs. Table 74. External triggers

If the software trigger is selected, the conversion starts once the SWTRIG bit is set. Note: TSELx[2:0] bit cannot be changed when the ENx bit is set.

12.3.7 DMA request

12.3.8 Noise generation

after each trigger event, following a specific calculation algorithm. Figure 44. DAC LFSR register calculation algorithm value is then stored into the DAC_DORx register. If LFSR is 0x0000, a ‘1’ is injected into it (antilock-up mechanism). It is possible to reset LFSR wave generation by resetting the WAVEx[1:0] bits.

Figure 45. DAC conversion (SW trigger enabled) with LFSR wave generation

12.3.9 Triangle-wave generation

It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal. counter is decremented down to 0, then incremented again and so on. It is possible to reset triangle wave generation by resetting WAVEx[1:0] bits. Figure 46. DAC triangle wave generation

Figure 47. DAC conversion (SW trigger enabled) with triangle wave generation

12.4 Dual DAC channel conversion

unique register access is then required to drive both DAC channels at the same time. All modes are described in the paragraphs below.