RLP03N06CLE

RLD03N06CLE INTERSIL | Alldatasheet

Document overview

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Technical content

Features

• 0.30A, 60V
• r DS(ON) = 6.0Ω
• Built in Current Limit ILIMIT0.140 to 0.210A at 150oC
• Built in Voltage Clamp
• Temperature Compensating PSPICE ® Model
• 2kV ESD Protected
• Controlled Switching Limits EMI and RFI
• Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol Packaging

Ordering Information

RLD03N06CLE TO-251AA 03N06C RLD03N06CLESM TO-252AA 03N06C RLP03N06CLE TO-220AB 03N06CLE NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-252AA variant in tape and reel, i.e. RLD03N06CLESM9A. G S D JEDEC TO-251AA JEDEC TO-252AA JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) GATE SOURCE DRAIN (FLANGE) DRAIN (FLANGE) SOURCE DRAIN GATE Data Sheet July 1999

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE UNITS 0.2 W W/oC J, TSTG -55 to 175 oC Maximum Temperature for Soldering 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationo ft h e device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical SpecificationsTC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BV DSS ID = 250µA, VGS = 0V 60 - 85 V Gate Threshold Voltage V GS(TH) VGS = VDS , ID = 250µA 1 - 2.5 V Zero Gate Voltage Drain Current I DSS VDS = 45V, VGS = 0V TJ = 25oC- - 2 5 µA TJ = 150oC - - 250 µA Gate to Source Leakage Current I GSS VGS = 5V T J = 25oC- - 5 µA TJ = 150oC- - 2 0 µA Drain to Source On Resistance (Note 2) rDS(ON) ID = 0.100A, VGS = 5V TJ = 25oC - - 6.0 Ω TJ = 150oC - - 12.0 Ω Limiting Current I DS(LIMIT) VDS = 15V, VGS = 5V TJ = 25oC 280 - 420 mA TJ = 150oC 140 - 210 mA Turn-On Time t ON VDD = 30V, ID = 0.10A, R L = 300Ω , VGS = 5V, R GS = 25Ω - - 7.5 µs Turn-On Delay Time t d(ON) - - 2.5 µs Rise Time t r - - 5.0 µs Turn-Off Delay Time t d(OFF) - - 7.5 µs Fall Time t f - - 5.0 µs Turn-Off Time t OFF - - 12.5 µs Input Capacitance C ISS VDS = 25V, VGS = 0V, f = 1MHz - 100 - pF Output Capacitance C OSS -6 5-p F Reverse Transfer Capacitance C RSS - 3.0 - pF Thermal Resistance Junction to Case R θJC - - 5.0 oC/W Thermal Resistance Junction to Ambient R θJA TO-220 Package - - 80 oC/W TO-251 and TO-252 Packages - - 100 oC/W Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage V SD ISD = 0.1A - - 1.5 V Diode Reverse Recovery Time t rr ISD = 0.1A, dISD /dt = 100A/µs - - 1.0 ms NOTES: 2. Pulsed: pulse duration =≤ 300µs maximum, duty cycle =≤ 2%. 3. Repititive rating: pulse width limited by maximum junction temperature. RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE

dependence is shown in Figure 3. switching speed is very predictable. NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT. FIGURE 13. RESISTIVE SWITCHING TEST CIRCUIT FIGURE 14. RESISTIVE SWITCHING WAVEFORMS

0.75 BVDSS

0.50 BVDSS

0.25 BVDSS

ous heatsink thermal resistances. condition causing the current limiting to occur.

150 C T C–o

NOTE: Heat Sink Thermal Resistance = HSTR. FIGURE 15. DC OPERATION IN CURRENT LIMITING FIGURE 16. MAXIMUM V DS vs AMBIENT TEMPERATURE IN FIGURE 17. MAXIMUM V DS vs AMBIENT TEMPERATURE IN FIGURE 18. MAXIMUM V DS vs AMBIENT TEMPERATURE IN

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com SUBCKT RLD03N06CLE 2 1 3; rev 4/18/94 CA 12 8 0.547e-9 CB 15 14 0.547e-9 CIN 6 8 0.301e-9 DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DESD1 91 9 DESD1MOD DESD2 91 7 DESD2MOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 20 17 18 66.5 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 2.96e-9 LSOURCE 3 7 2.96e-9 MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 QCONTROL 20 70 7 QMOD 1 RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 1.123 RGATE 9 20 3200 RIN 6 8 1e9 RSOURCE1 8 70 RDSMOD 1.12 RSOURCE2 70 7 RSMOD 2.16 RVTO 18 19 RVTOMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 0.22 .MODEL DBKMOD D (RS = 3150 TRS1 =0 TRS2 = 0) .MODEL DESD1MOD D (BV = 13.54 TBV1 = 0 TBV2 = 0 RS = 45.5 TRS1 = 0 TRS2 = 0) .MODEL DESD2MOD D (BV = 11.46 TBV1 = -7.576e-4 TBV2 = -3.0e-6 RS = 0 TRS1 = 0 TRS2 = 0) .MODEL DPLCAPMOD D (CJO = 74.2e-12 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 1.67 KP = 3.40 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL QMOD NPN (BF =5) .MODEL RBKMOD RES (TC1 = 4e-4 TC2 = 1.13e-8) .MODEL RDSMOD RES (TC1 = 6.80e-3 TC2 = 6.5e-6) .MODEL RSMOD RES (TC1 = 2.95e-3 TC2 = -1e-6) .MODEL RVTOMOD RES (TC1 = -2.22e-3 TC2 = -1.95e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3 VOFF = -1) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1 VOFF = -3) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.85 VOFF = 2.15) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.15 VOFF = -2.85) .ENDS NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records 1991. GATE LGATE RGATE EVTO DESD1 DESD2 12 13 S1A S1B S2A S2B CA CB EGS EDS R IN C IN MOS1 MOS2 RDRAIN DBREAK EBREAK DBODY LDRAIN DRAIN RSOURCE2 LSOURCE SOURCE RBREAK RVTO VBAT IT VTO ESG DPLCAP 17 18 RSOURCE1 RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE