RL78I1D

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R01DS0244EJ0200 Rev. 2.00 Page 1 of 99 Jan 16, 2015 RL78/I1D RENESAS MCU Datasheet 1. OUTLINE

1.1 Features

Ultra-low power consumption technology

• V DD = 1.6 V to 3.6 V
• HALT mode
• S T O P m o d e
• SNOOZE mode RL78 CPU core
• CISC architecture with 3-stage pipeline
• Minimum instruction execution time: Can be changed from high speed (0.04167 s: @ 24 MHz operation with high-speed on-chip oscillator) to ultra-low speed (66.6 s: @ 15 kHz operation with low-speed on-chip oscillator clock)
• Multiply/divide/multiply & accumulate instructions are supported.
• Address space: 1 MB
• General-purpose registers: (8-bit register  8)  4 banks
• On-chip RAM: 0.7 to 3 KB Code flash memory
• Code flash memory: 8 to 32 KB
• Block size: 1 KB
• Prohibition of block erase and rewriting (security function)
• On-chip debug function
• Self-programming (with boot swap function/flash shield window function) Data flash memory
• Data flash memory: 2 KB
• Back ground operation (BGO): Instructions can be executed from the program memory while rewriting the data flash memory.
• Number of rewrites: 1,000,000 times (TYP.)
• Voltage of rewrites: V DD = 1.8 to 3.6 V High-speed on-chip oscillator
• Select from 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz
• High accuracy: ±1.0% (VDD = 1.8 to 3.6 V, TA = -20 to +85°C) Middle-speed on-chip oscillator
• Selectable from 4 MHz, 2 MHz, and 1 MHz. Operating ambient temperature
• TA = -40 to +105°C (G: Industrial applications) Power management and reset function
• On-chip power-on-reset (POR) circuit
• On-chip voltage detector (LVD) (Select interrupt and reset from 12 levels) Data transfer controller (DTC)
• Transfer modes: Normal transfer mode, repeat transfer mode, block transfer mode
• Activation sources: Activated by interrupt sources.
• Chain transfer function Event link controller (ELC)
• Event signals of 20 types can be linked to the specified peripheral function. Serial interfaces
• CSI: 2 channels
• UART: 1 channel 2C/simplified I2C: 2 channels Timers
• 16-bit timer: 4 channels
• 12-bit interval timer: 1 channel
• 8-bit interval timer: 4 channels
• Real-time clock: 1 channel (calendar for 99 years, alarm function, and clock correction function)
• Watchdog timer: 1 channel A/D converter
• 8/12-bit resolution A/D converter (VDD = 1.6 to 3.6 V)
• Analog input: 6 to 17 channels
• Internal reference voltage (1.45 V) and temperature sensor Comparator
• 2 channels
• Operating modes: Comparator high-speed mode, comparator low-speed mode, window mode Operational amplifier
• 4 channels I/O ports
• I/O port: 14 to 42 (N-ch open drain I/O [withstand voltage of 6 V]: 4, N-ch open drain I/O [VDD withstand voltage]: 3 to 7)
• Can be set to N-ch open drain, TTL input buffer, and on- chip pull-up resistor
• Different potential interface: Can connect to a 1.8/2.5 V device
• On-chip key interrupt function
• On-chip clock output/buzzer output controller Others
• On-chip BCD (binary-coded decimal) correction circuit
• On-chip data operation circuit Remark The functions mounted depend on the product. See 1.6 Outline of Functions. R01DS0244EJ0200 Rev. 2.00 Jan 16, 2015

RL78/I1D 1. OUTLINE R01DS0244EJ0200 Rev. 2.00 Page 2 of 99 Jan 16, 2015 ROM, RAM capacities Note The flash library uses RAM in self-programming and rewriting of the data flash memory. The target products and start address of the RAM areas used by the flash library are shown below. R5F117xC (x = A, B, G): Start address FF300H For the RAM areas used by the flash library, see Self RAM list of Flash Self-Programming Library for RL78 Family (R20UT2944). Flash ROM Data flash RAM RL78/I1D 20 pins 24 pins 30 pins 32 pins 48 pins

32 KB 2 KB 3 KB Note — — R5F117AC R5F117BC R5F117GC

16 KB 2 KB 2 KB R5F1176A R5F1177A R5F117AA R5F117BA R5F117GA

8 KB 2 KB 0.7 KB R5F11768 R5F11778 R5F117A8 — —

RL78/I1D 1. OUTLINE R01DS0244EJ0200 Rev. 2.00 Page 3 of 99 Jan 16, 2015

1.2 Ordering Information

Figure 1 - 1 Part Number, Memory Size, and Package of RL78/I1D Note 1. 24-pin products Note 2. 32-pin products Part No. R5F117GCGx x xFB#U0 Packaging specification #20: Tray (HVQFN) #30: Tray (LFQFP, LQFP, LSSOP) #U0: Tray (HWQFN) #40: Embossed Tape (HVQFN) #50: Embossed Tape (LFQFP, LQFP, LSSOP) #W0: Embossed Tape (HWQFN) Package type: SP: LSSOP, 0.65 mm pitch FP: LQFP, 0.80 mm pitch FB: LFQFP, 0.50 mm pitch NA: HWQFN, 0.50 mm pitch Note 1 NA: HVQFN, 0.50 mm pitch Note 2 ROM number (Omitted for blank products) Fields of application: G: Industrial applications, TA = -40 to +105 C ROM capacity: 8: 8 KB A: 16 KB C: 32 KB Pin count: 6: 20-pin 7: 24-pin A: 30-pin B: 32-pin G: 48-pin RL78/I1D Memory type: F : Flash memory Renesas MCU Renesas semiconductor product

RL78/I1D 1. OUTLINE R01DS0244EJ0200 Rev. 2.00 Page 4 of 99 Jan 16, 2015 Note For the fields of application, refer to Figure 1 - 1 Part Number, Memory Size, and Package of RL78/I1D. Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. Pin count Package Ordering Part Number 20 pins 20-pin plastic LSSOP (4.4  6.5 mm, 0.65 mm pitch) R5F11768GSP#30, R5F1176AGSP#30, R5F11768GSP#50, R5F1176AGSP#50 24 pins 24-pin plastic HWQFN (4  4 mm, 0.5 mm pitch) R5F11778GNA#U0, R5F1177AGNA#U0, R5F11778GNA#W0, R5F1177AGNA#W0 30 pins 30-pin plastic LSSOP (7.62 mm (300), 0.65 mm pitch) R5F117A8GSP#30, R5F117AAGSP#30, R5F117ACGSP#30, R5F117A8GSP#50, R5F117AAGSP#50, R5F117ACGSP#50 32 pins 32-pin plastic HVQFN (5  5 mm, 0.5 mm pitch) R5F117BAGNA#20, R5F117BCGNA#20, R5F117BAGNA#40, R5F117BCGNA#40 32-pin plastic LQFP (7  7 mm, 0.8 mm pitch) R5F117BAGFP#30, R5F117BCGFP#30, R5F117BAGFP#50, R5F117BCGFP#50 48 pins 48-pin plastic LFQFP (7  7 mm, 0.5 mm pitch) R5F117GAGFB#30, R5F117GCGFB#30, R5F117GAGFB#50, R5F117GCGFB#50

RL78/I1D 1. OUTLINE R01DS0244EJ0200 Rev. 2.00 Page 5 of 99 Jan 16, 2015

1.3 Pin Configuration (Top View)

1.3.1 20-pin products

• 20-pin plastic LSSOP (4.4  6.5 mm, 0.65 mm pitch) Caution 1. Connect the REGC pin to V SS pin via a capacitor (0.47 to 1 F). Caution 2. Make AV SS pin the same potential as VSS pin. Caution 3. Make AV DD pin the same potential as VDD pin. Remark For pin identification, see 1.4 Pin Identification. P13/ANI3/AMP0- P14/ANI4/IVCMP0/AMP0O AV SS AVDD P22/ANI11/AMP3+ P21/ANI12/AMP3- P20/ANI13/IVCMP1/AMP3O P31/TI01/TO00/PCLBUZ0/IVREF1 P30/SCK00/SCL00/TI00/TO01/IVREF0 P54/SO00/TxD0/INTP1/TOOLTXD P40/TOOL0 RESET P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P55/SI00/RxD0/SDA00/INTP2/TOOLRXD P12/ANI2/AMP0+

RL78/I1D 1. OUTLINE R01DS0244EJ0200 Rev. 2.00 Page 6 of 99 Jan 16, 2015 1.3.2 24-pin products

• 24-pin plastic HWQFN (4  4 mm, 0.5 mm pitch) Caution 1. Connect the REGC pin to V SS pin via a capacitor (0.47 to 1 F). Caution 2. Make AV SS pin the same potential as VSS pin. Caution 3. Make AV DD pin the same potential as VDD pin. Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. It is recommended to connect an exposed die pad to VSS. Remark 3. Functions in parentheses in the above fi gure can be assigned via settings in the peripheral I/O redirection register 0 (PIOR0). 1817 16 15 1413 1 234 56 AVSS P14/ANI4/IVCMP0/AMP0O P13/ANI3/AMP0- P12/ANI2/AMP0+ P40/TOOL0 RESET P51/KR0/SCK01/SCL01/TI02/TO02 P52/KR1/SI01/SDA01/TI03/TO03 P53/KR2/SO01/VCOUT0 P54/SO00/TxD0/INTP1/TOOLTXD P55/SI00/RxD0/SDA00/INTP2/TOOLRXD P56/SCK00/SCL00/INTP3 AVDD P22/ANI11/AMP3+ P21/ANI12/AMP3- P20/ANI13/IVCMP1/AMP3O P31/TI01/TO00/PCLBUZ0/IVREF1 P30/(SCK00)/(SCL00)/TI00/TO01/IVREF0 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD INDEX MARK Exposed die pad

RL78/I1D 1. OUTLINE R01DS0244EJ0200 Rev. 2.00 Page 7 of 99 Jan 16, 2015 1.3.3 30-pin products

• 30-pin plastic LSSOP (7.62 mm (300), 0.65 mm pitch) Caution 1. Connect the REGC pin to V SS pin via a capacitor (0.47 to 1 F). Caution 2. Make AV SS pin the same potential as VSS pin. Caution 3. Make AV DD pin the same potential as VDD pin. Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above fi gure can be assigned via settings in the peripheral I/O redirection register 0 (PIOR0). P15/ANI5/AMP1+ P16/ANI6/AMP1- P17/ANI7/AMP1O AV SS AVDD P25/ANI8/AMP2+ P24/ANI9/AMP2- P23/ANI10/AMP2O P22/ANI11/AMP3+ P21/ANI12/AMP3- P20/ANI13/IVCMP1/AMP3O P33/TI02/TO02/INTP5 P31/TI01/TO00/PCLBUZ0/IVREF1 P30/(SCK00)/(SCL00)/TI00/TO01/IVREF0 P54/SO00/TxD0/INTP1/TOOLTXD P13/ANI3/AMP0- P12/ANI2/AMP0+ P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P56/SCK00/SCL00/INTP3 P55/SI00/RxD0/SDA00/INTP2/TOOLRXD P14/ANI4/IVCMP0/AMP0O

RL78/I1D 1. OUTLINE R01DS0244EJ0200 Rev. 2.00 Page 8 of 99 Jan 16, 2015 1.3.4 32-pin products

• 32-pin plastic HVQFN (5  5 mm, 0.5 mm pitch) Caution 1. Connect the REGC pin to V SS pin via a capacitor (0.47 to 1 F). Caution 2. Make AV SS pin the same potential as VSS pin. Caution 3. Make AV DD pin the same potential as VDD pin. Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above fi gure can be assigned via settings in the peripheral I/O redirection register 0 (PIOR0). Remark 3. It is recommended to connect an exposed die pad to VSS. P31/TI01/TO00/PCLBUZ0/IVREF1 P30/(SCK00)/(SCL00)/TI00/TO01/IVREF0 P51/KR0/SCK01/SCL01/TI02/TO02 P52/KR1/SI01/SDA01/TI03/TO03 P53/KR2/SO01/VCOUT0 P54/SO00/TxD0/INTP1/TOOLTXD P55/SI00/RxD0/SDA00/INTP2/TOOLRXD P56/SCK00/SCL00/INTP3 Exposed die pad P17/ANI7/AMP1O P16/ANI6/AMP1- P15/ANI5/AMP1+ P13/ANI3/AMP0- P12/ANI2/AMP0+ P40/TOOL0 2345678 24 23 22 21 20 19 18 17P124/XT2/EXCLKS P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P123/XT1 P20/ANI13/IVCMP1/AMP3O P21/ANI12/AMP3- P22/ANI11/AMP3+ P23/ANI10/AMP2O P24/ANI9/AMP2- P25/ANI8/AMP2+ AVDD AVSS RESET P14/ANI4/IVCMP0/AMP0O INDEX MARK

RL78/I1D 1. OUTLINE R01DS0244EJ0200 Rev. 2.00 Page 9 of 99 Jan 16, 2015

• 32-pin plastic LQFP (7  7 mm, 0.5 mm pitch) Caution 1. Connect the REGC pin to V SS pin via a capacitor (0.47 to 1 F). Caution 2. Make AV SS pin the same potential as VSS pin. Caution 3. Make AV DD pin the same potential as VDD pin. Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above fi gure can be assigned via settings in the peripheral I/O redirection register 0 (PIOR0). P31/TI01/TO00/PCLBUZ0/IVREF1 P30/(SCK00)/(SCL00)/TI00/TO01/IVREF0 P51/KR0/SCK01/SCL01/TI02/TO02 P52/KR1/SI01/SDA01/TI03/TO03 P53/KR2/SO01/VCOUT0 P54/SO00/TxD0/INTP1/TOOLTXD P55/SI00/RxD0/SDA00/INTP2/TOOLRXD P56/SCK00/SCL00/INTP3 P17/ANI7/AMP1O P16/ANI6/AMP1- P15/ANI5/AMP1+ P13/ANI3/AMP0- P12/ANI2/AMP0+ P40/TOOL0 2345678 24 23 22 21 20 19 18 17P124/XT2/EXCLKS P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P123/XT1 P20/ANI13/IVCMP1/AMP3O P21/ANI12/AMP3- P22/ANI11/AMP3+ P23/ANI10/AMP2O P24/ANI9/AMP2- P25/ANI8/AMP2+ AVDD AVSS RESET P14/ANI4/IVCMP0/AMP0O

RL78/I1D 1. OUTLINE R01DS0244EJ0200 Rev. 2.00 Page 10 of 99 Jan 16, 2015 1.3.5 48-pin products

• 48-pin plastic LFQFP (7  7 mm, 0.5 mm pitch) Caution 1. Connect the REGC pin to V SS pin via a capacitor (0.47 to 1 F). Caution 2. Make AV SS pin the same potential as VSS pin. Caution 3. Make AV DD pin the same potential as VDD pin. Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above fi gure can be assigned via settings in the peripheral I/O redirection register 0 (PIOR0). P30/(SCK00)/(SCL00)/TI00/TO01/IVREF0 P50/(TI00/TO01)/RTC1HZ P51/KR0/SCK01/SCL01/TI02/TO02 P52/KR1/SI01/SDA01/TI03/TO03 P53/KR2/SO01/VCOUT0 P54/SO00/TxD0/INTP1/TOOLTXD P55/SI00/RxD0/SDA00/INTP2/TOOLRXD P56/SCK00/SCL00/INTP3 P57/(TI03/TO03)/INTP4/VCOUT1 P63/SSI00 P62 P61 P16/ANI6/AMP1- P15/ANI5/AMP1+ P14/ANI4/IVCMP0/AMP0O P13/ANI3/AMP0- P12/ANI2/AMP0+ P11/ANI1/AVREFM P10/ANI0/AVREFP P130 P40/TOOL0 P04/ANI18 P03/ANI17 P02/ANI16 123456789 1 0 1 1 1 2 36 35 34 33 32 31 30 29 28 27 26 25 P60 VDD VSS REGC P121/X1 P122/X2/EXCLK P137/INTP0 P123/XT1 P124/XT2/EXCLKS RESET P00 P01/PCLBUZ1 P17/ANI7/AMP1O AVSS AVDD P25/ANI8/AMP2+ P24/ANI9/AMP2- P23/ANI10/AMP2O P22/ANI11/AMP3+ P21/ANI12/AMP3- P20/ANI13/IVCMP1/AMP3O P33/(TI02/TO02)/INTP5 P32/KR3/(TI01/TO00)/INTP6 P31/TI01/TO00/PCLBUZ0/IVREF1

RL78/I1D 1. OUTLINE R01DS0244EJ0200 Rev. 2.00 Page 11 of 99 Jan 16, 2015

1.4 Pin Identification

ANI0 to ANI13, : Analog input PCLBUZ0, PCLBUZ1 : Programmable clock output/buzzer ANI16 to ANI18 output AVDD : Analog power supply REGC : Regulator capacitance AVREFM : A/D converter reference RESET : Reset potential (- side) input RTC1HZ : Real-t ime clock correction clock (1 Hz) AVREFP : A/D converter reference output potential (+ side) input RxD0 : Receive data AVSS : Analog ground SCK00, SCK01 : Serial clock input/output EXCLK : External clock input SCL00, SCL01 : Serial clock input/output (main system clock) SDA00, SDA01 : Serial data input/output EXCLKS : External clock input SI00, SI01 : Serial data input (subsystem clock) SO00, SO01 : Serial data output INTP0 to INTP6 : External interrupt input SSI00 : Serial interface chip select input IVCMP0, IVCMP1 : Comparator input TI00 to TI03 : Timer input IVREF0, IVREF1 : Comparator reference input TO00 to TO03 : Timer output KR0 to KR3 : Key return TOOL0 : Data input/output for tool P00 to P04 : Port 0 TOOLRXD, TOOLTXD : Data input/output for external device P10 to P17 : Port 1 TxD0 : Transmit data P20 to P25 : Port 2 VCOUT0, VCOUT1 : Comparator output P30 to P33 : Port 3 AMP0+, AMP1+, : Operational amplifier (+side) input P40 : Port 4 AMP2+, AMP3+ P50 to P57 : Port 5 AMP0-, AMP1-, : Operational amplifier (-side) input P60 to P63 : Port 6 AMP2-, AMP3- P121 to P124 : Port 12 AMP0O, AMP1O, : Operational amplifier output P130, P137 : Port 13 AMP2O, AMP3O V DD : Power supply VSS : Ground X1, X2 : Crystal oscillator (main system clock) XT1, XT2 : Crystal oscillator (subsystem clock)

RL78/I1D 1. OUTLINE R01DS0244EJ0200 Rev. 2.00 Page 12 of 99 Jan 16, 2015

1.5 Block Diagram

1.5.1 48-pin products Port 1 Port 2 4Port 3 Port 4 Port 5 Port 12 CLOCK GENERATOR RESET CIRCUIT A/D CONVERTER (16ch) IIC00 UART0 ch02 ch03 ch00 ch01 Port 13 ON-CHIP DEBUG IIC01 CSI00 POR/ LVD HIGH-SPEED ON-CHIP OSCILLATOR

24 MHz

4 MHz

32.768 kHz REGULATOR Port 0 5 REAL TIME CLOCK CLOCK OUTPUT/ BUZZER OUTPUT CONTROLLER KEY INTERRUPT 4ch EXTERNAL INTERRUPT 7ch 12-BIT INTERVAL TIMER CSI01 Port 6 4ch00 ch01 ch10 ch11 DATA TRANSFER CONTROLLER (DTC) RAM 3 KB INT WATCHDOG TIMER (WDT) CODE FLASH: 32 KB DATA FLASH: 2 KB EVENT LINK CONTROLLER (ELC) MULDIV OPERATIONAL AMPLIFIER 0 OPERATIONAL AMPLIFIER 1 OPERATIONAL AMPLIFIER 2 OPERATIONAL AMPLIFIER 3 TI00 TO00 TI01 TO01 TI02 TO02 TI03 TO03 TIMER ARRAY UNIT 0 (4ch) 8-BIT INTERVAL TIMER 0 8-BIT INTERVAL TIMER 1 SERIAL ARRAY UNIT0 (2ch) RxD0 TxD0 SCK00 SI00 SO00 SSI00 SCK01 SI01 SO01 SCL00 SDA00 SCL01 SDA01 RL78 CPU CORE RESET X1 X2/EXCLK XT1 XT2/EXCLK REGC VDD VSS TOOLRXD/P55, TOOLTXD/P54 P00 to P04 P10 to P17 P20 to P25 P30 to P33 P40 P50 to P57 P60 to P63 P121 to P124 P130 P137 TOOL0/P40 COMPARATOR (2ch) COMPARATOR 0 COMPARATOR 1 OPERATIONAL AMPLIFIER (4ch) PCLBUZ0 PCLBUZ1 KR0 to KR3 INTP0 to INTP6 RTC1HZ ANI2 to ANI13, ANI16 to ANI18 ANI0/AVREFP ANI1/AVREFM VCOUT0 IVCMP0 IVREF0 VCOUT1 IVCMP1 IVREF1 AMP0+ AMP0- AMP0O AMP1+ AMP1- AMP1O AMP2+ AMP2- AMP2O AMP3+ AMP3- AMP3O BCD CORRECTION CIRCUIT DATA OPERATION CIRCUIT (DOC) CRC FREQUENCY MEASUREMENT CIRCUIT

RL78/I1D 1. OUTLINE R01DS0244EJ0200 Rev. 2.00 Page 13 of 99 Jan 16, 2015

1.6 Outline of Functions

Remark This outline describes the functions at the time when Peripheral I/O redirection register 0 (PIOR0) are set to 00H. Note The flash library uses RAM in self-programming and rewriting of the data flash memory. The target products and start address of the RAM areas used by the flash library are shown below. R5F117xC (x = A, B, G): Start address FF300H For the RAM areas used by the flash library, see Self RAM list of Flash Self-Programming Library for RL78 Family (R20UT2944). (1/2) Item 20-pin 24-pin 30-pin 32-pin 48-pin R5F1176x (x = 8, A) R5F1177x (x = 8, A) R5F117Ax (x = 8, A, C) R5F117Bx (x = A, C) R5F117Gx (x = A, C) Code flash memory (KB) 8 to 16 KB 8 to 16 KB 8 to 32 KB 16 to 32 KB 16 to 32 KB Data flash memory (KB) 2 KB 2 KB 2 KB 2 KB 2 KB Address space 1 MB Main system clock High-speed system clock (fMX) X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) High-speed on-chip oscillator clock (fIH) Max: 24 MHz HS (High-speed main) mode: 1 to 24 MHz (V DD = 2.7 to 3.6 V), HS (High-speed main) mode: 1 to 16 MHz (V DD = 2.4 to 3.6 V), LS (Low-speed main) mode: 1 to 8 MHz (V DD = 1.8 to 3.6 V), LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 3.6 V), LP (Low-power main) mode: 1 MHz (V DD = 1.8 to 3.6 V) Middle-speed on-chip oscillator clock (f IM) Max: 4 MHz Subsystem clock Subsystem clock oscillator SX, fSXR) — XT1 (crystal) oscillation 32.768 kHz (TYP.): VDD = 1.6 to 3.6 V Low-speed on-chip oscillator clock (fIL) 15 kHz (TYP.): VDD = 1.6 to 3.6 V General-purpose register 8 bits  32 registers (8 bits  8 registers  4 banks) Minimum instruction execution time 0.04167 s (High-speed on-chip oscillator clock: fIH = 24 MHz operation) 0.05 s (High-speed system clock: fMX = 20 MHz operation) —3 0 . 5 s (Subsystem clock oscillator clock: fSX = 32.768 kHz operation) Instruction set • Data transfer (8/16 bits)

• Adder and subtractor/logical operation (8/16 bits)
• Multiplication (8 bits  8 bits, 16 bits  16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
• Multiplication and Accumulation (16 bits  16 bits + 32 bits)
• Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. I/O port Total 14 18 24 26 42 C M O S I / O 1 11 51 92 13 3 C M O S i n p u t 33555 N-ch open-drain I/O (6 V tolerance) ———— 4 Timer 16-bit timer 4 channels Watchdog timer 1 channel Real-time clock 1 channel 12-bit interval timer 1 channel 8/16-bit interval timer 4 channels (8 bit) / 2 channels (16 bit) T i m e r o u t p u t 24344 RTC output — 1 channel
• 1 H z (subsystem clock generator and RTC/other clock: f SX = 32.768 kHz)

RL78/I1D 1. OUTLINE R01DS0244EJ0200 Rev. 2.00 Page 14 of 99 Jan 16, 2015 The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution not is issued by emulation with the in-circuit emulator or on-chip debug emulator. (2/2) Item 20-pin 24-pin 30-pin 32-pin 48-pin R5F1176x (x = 8, A) R5F1177x (x = 8, A) R5F117Ax (x = 8, A, C) R5F117Bx (x = A, C) R5F117Gx (x = A, C) Clock output/buzzer output 1 1 1 1 2 [20-pin, 24-pin products] (Main system clock: fMAIN = 20 MHz operation) [30-pin, 32-pin, 48-pin products] (Main system clock: fMAIN = 20 MHz operation) (subsystem clock generator and RTC/other clock: fSXR = 32.768 kHz operation) 12-bit resolution A/D converter 6 channels 6 channels 12 channels 12 channels 17 channels Comparator (Window Comparator) 2 channels Operational amplifier 2 channels 4 channels Data Operation Circuit (DOC) Comparison, addition, and subtraction of 16-bit data Serial interface [20-pin, 30-pin products]

• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel [24-pin, 32-pin, 48-pin products]
• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels Data transfer controller (DTC) 16 sources 20 sources 19 sources 20 sources 23 sources Event link controller (ELC) Event input: 13 Event trigger output: 5 Event input: 17 Event trigger output: 5 Event input: 16 Event trigger output: 7 Event input: 17 Event trigger output: 7 Event input: 20 Event trigger output: 7 Vectored interrupt sources Internal 22 22 24 24 24 External 35558 Key interrupt — 3 — 3 4 Reset • Reset by RESET pin
• Internal reset by watchdog timer
• Internal reset by power-on-reset
• Internal reset by voltage detector
• Internal reset by illegal instruction execution Note
• Internal reset by RAM parity error
• Internal reset by illegal-memory access Power-on-reset circuit • Power-on-reset: 1.51 ± 0.04V (T A = -40 to +85°C)
• Power-down-reset: 1.50 ± 0.04 V (TA = -40 to +85°C) Voltage detector Power on 1.67 V to 3.13 V (12 stages) Power down 1.63 V to 3.06 V (12 stages) On-chip debug function Provided (Enable to tracing) Power supply voltage VDD = 1.6 to 3.6 V Operating ambient temperature T A = -40 to +105°C

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 15 of 99 Jan 16, 2015 2. ELECTRICAL SPECIFICATIONS Caution 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. product in the RL78/I1D User’s Manual. Caution 3. Please contact Renesas Electronics sales office for derating of operation under T A = +85 to +105°C. Derating is the systematic reduction of load for the sake of improved reliability. Caution 4. When operating temperature exceeds 85°C, only HS (high-speed main) mode can be used as the flash operation mode. Regulator mode should be used with the normal setting (MCSEL = 0).

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 16 of 99 Jan 16, 2015

2.1 Absolute Maximum Ratings

Note 1. Connect the REGC pin to V SS via a capacitor (0.47 to 1 F). This value regulates the absolute maximum rating of the REGC pin. Do not use this pin with voltage applied to it. Note 2. Must be 4.6 V or lower. Note 3. Do not exceed AVREF (+) + 0.3 V in case of A/D conversion target pin. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. Remark 2. AVREF (+): + side reference voltage of the A/D converter. Remark 3. VSS: Reference voltage Absolute Maximum Ratings (1/2) Parameter Symbols Conditions Ratings Unit Supply voltage VDD, AVDD VDD = AVDD -0.3 to + 4.6 V AVREFP 0.3 to AVDD + 0.3 Note 2 V AVSS -0.5 to + 0.3 V AVREFM -0.3 to AVDD + 0.3 Note 2 and AVREFM  AVREFP V REGC pin input voltage V IREGC REGC -0.3 to + 2.8 and -0.3 to VDD + 0.3 Note 1 V Input voltage V I1 P00 to P04, P30 to P33, P40, P50 to P57, P121 to P124, P130, P137, EXCLK, EXCLKS, RESET -0.3 to VDD + 0.3 Note 2 V VI2 P60 to P63 (N-ch open-drain) -0.3 to + 6.5 V VI3 P10 to P17, P20 to P25 -0.3 to AVDD + 0.3 Note 2 V Output voltage V O1 P00 to P04, P30 to P33, P40, P50 to P57, P60 to P63, P130 -0.3 to V DD + 0.3 Note 2 V VO2 P10 to P17, P20 to P25 -0.3 to AVDD + 0.3 Note 2 V Analog input voltage V AI1 ANI16 to ANI18 -0.3 to VDD + 0.3 and -0.3 to AVREF(+) + 0.3 Note 2 V VAI2 ANI0 to ANI13 -0.3 to AVDD + 0.3 and -0.3 to AVREF(+) + 0.3 Note 2 V VAI3 Operational amplifier input pin -0.3 to AVDD + 0.3 Note 2 V

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 17 of 99 Jan 16, 2015 Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. Absolute Maximum Ratings (2/2) Parameter Symbols Conditions Ratings Unit Output current, high I OH1 Per pin P00 to P04, P30 to P33, P40, P50 to P57, P130 -40 mA Total of all pins -170 mA P00 to P04, P40, P130 -70 mA P30 to P33, P50 to P57 -100 mA IOH2 Per pin P10 to P17, P20 to P25 -0.1 mA Total of all pins -1.4 mA Output current, low I OL1 Per pin P00 to P04, P30 to P33, P40, P50 to P57, P60 to P63, P130 40 mA Total of all pins 170 mA P00 to P04, P40, P130 70 mA P30 to P33, P50 to P57, P60 to P63 100 mA IOL2 Per pin P10 to P17, P20 to P25 0.4 mA Total of all pins 5.6 mA Operating ambient temperature TA In normal operation mode -40 to +105 C In flash memory programming mode Storage temperature T stg -65 to +150 C

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 18 of 99 Jan 16, 2015

2.2 Oscillator Characteristics

2.2.1 X1, XT1 characteristics

Note Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time. Request evaluation by the manufacturer of the oscilla tor circuit mounted on a boa rd to check the oscillator characteristics. Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. Remark When using the X1 oscillator and XT1 oscillator, refer to 6.4 System Clock Oscillator in the RL78/I1D User’s Manual.

2.2.2 On-chip oscillator characteristics

Note 1. High-speed on-chip oscillator fr equency is selected with bits 0 to 3 of the option byte (000C2H) and bits 0 to 2 of the HOCODIV register. Note 2. This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time. (TA = -40 to +85°C, 1.6 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Resonator Resonator Conditions MIN. TYP . MAX. Unit X1 clock oscillation frequency (fX) Note Ceramic resonator/ crystal resonator 2.7 V  VDD  3.6 V 1.0 20.0 MHz 2.4 V  VDD  2.7 V 1.0 16.0 1.8 V  VDD  2.4 V 1.0 8.0 1.6 V  VDD  1.8 V 1.0 4.0 XT1 clock oscillation frequency (fXT) Note Crystal resonator 32 32.768 35 kHz (TA = -40 to +85°C, 1.6 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Oscillators Parameters Conditions MIN. TYP. MAX. Unit High-speed on-chip oscillator clock frequency Notes 1, 2 fIH 12 4 M Hz High-speed on-chip oscillator clock frequency accuracy -20 to +85°C 1.8 V  VDD  3.6 V -1.0 +1.0 % Middle-speed on-chip oscillator oscillation frequency Note 2 fIM 14 M Hz Middle-speed on-chip oscillator oscillation frequency accuracy 1.8V  VDD  3.6V -12 +12 % Low-speed on-chip oscillator clock frequency Note 2 fIL 15 kHz Low-speed on-chip oscillator clock frequency accuracy -15 +15 %

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 19 of 99 Jan 16, 2015

2.3 DC Characteristics

2.3.1 Pin characteristics

Note 1. Value of current at which the device operation is guaranteed even if the current flows from the VDD pin to an output pin. Note 2. Do not exceed the total current value. Note 3. Specification under conditions where the duty factor  70%. The output current value that has changed to the duty factor  70% the duty ratio can be calc ulated with the following expression (when changing the duty factor from 70% to n%).

• Total output current of pins = (IOH × 0.7)/(n × 0.01) <Example> Where n = 80% and I OH = -10.0 mA Total output current of pins = (-10.0 × 0.7)/(80 × 0.01)  -8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Caution P30 and P51 to P56 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. (TA = -40 to +85°C, 1.6 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Items Symbol Conditions MIN. TYP . MAX. Unit Output current, high Note 1 IOH1 Per pin for P00 to P04, P30 to P33, P40, P50 to P57, P130 Note 2 mA Note 2 mA Total of P00 to P04, P40, P130 (When duty  70% Note 3) 2.7 V  VDD  3.6 V -10.0 mA 1.8 V  VDD < 2.7 V -5.0 mA 1.6 V  VDD < 1.8 V -2.5 mA Total of P30 to P33, P50 to P57 (When duty  70% Note 3) 2.7 V  VDD  3.6 V -19.0 mA 1.8 V  VDD < 2.7 V -10.0 mA 1.6 V  VDD < 1.8 V -5.0 mA Total of all pins (When duty  70% Note 3) -29.0 mA IOH2 Per pin for P10 to P17, P20 to P25 -0.1 Note 2 mA Total of all pins (When duty  70% Note 3) 1.6 V  VDD  3.6 V -1.4 mA (1/5)

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 20 of 99 Jan 16, 2015 Note 1. Value of current at which the device operation is guaranteed even if the current flows from an output pin to the VSS pin. Note 2. Do not exceed the total current value. Note 3. Specification under conditions where the duty factor  70%. The output current value that has changed to the duty factor  70% the duty ratio can be calc ulated with the following expression (when changing the duty factor from 70% to n%).

• Total output current of pins = (IOL × 0.7)/(n × 0.01) <Example> Where n = 80% and I OL = 10.0 mA Total output current of pins = (10.0 × 0.7)/(80 × 0.01)  8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. (TA = -40 to +85°C, 1.6 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (2/5) Items Symbol Conditions MIN. TYP. MAX. Unit Output current, low Note 1 IOL1 Per pin for P00 to P04, P30 to P33, P40, P50 to P57, P130 TA = -40 to +85°C 20.0 Note 2 mA TA = +85 to +105°C 8.5 Note 2 mA Per pin for P60 to P63 15.0 Note 2 mA Total of P00 to P04, P40, P130 (When duty  70% Note 3) 2.7 V  VDD  3.6 V 15.0 mA 1.8 V  VDD < 2.7 V 9.0 mA 1.6 V  VDD < 1.8 V 4.5 mA Total of P30 to P33, P50 to P57, P60 to P63 (When duty  70% Note 3) 2.7 V  VDD  3.6 V 35.0 mA 1.8 V  VDD < 2.7 V 20.0 mA 1.6 V  VDD < 1.8 V 10.0 mA Total of all pins (When duty  70% Note 3) 50.0 mA IOL2 Per pin for P10 to P17, P20 to P25 0.4 Note 2 mA Total of all pins (When duty  70% Note 3) 1.6 V  VDD  3.6 V 5.6 mA

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 21 of 99 Jan 16, 2015 Caution The maximum value of V IH of pins P30 and P51 to P56 is VDD, even in the N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. (TA = -40 to +85°C, 1.6 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (3/5) Items Symbol Conditions MIN. TYP . MAX. Unit Input voltage, high V IH1 P00 to P04, P30 to P33, P40, P50 to P57, P130 Normal input buffer 0.8 V DD VDD V VIH2 P30, P32, P33, P51, P52, P54 to P57 TTL input buffer 3.3 V  VDD  3.6 V

2.0 V DD V

1.6 V  VDD < 3.3 V

1.5 V DD V

VIH3 P10 to P17, P20 to P25 0.7 AVDD AVDD V VIH4 P60 to P63 0.7 VDD 6.0 V VIH5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0.8 VDD VDD V Input voltage, low V IL1 P00 to P04, P30 to P33, P40, P50 to P57, P130 Normal input buffer 0 0.2 V DD V VIL2 P30, P32, P33, P51, P52, P54 to P57 TTL input buffer 3.3 V  VDD  3.6 V 00 . 5 V TTL input buffer 1.6 V  VDD < 3.3 V 00 . 3 2 V VIL3 P10 to P17, P20 to P25 0 0.3 AVDD V VIL4 P60 to P63 0 0.3 VDD V VIL5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0 0.2 VDD V

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 22 of 99 Jan 16, 2015 Note 1. Only TA = -40 to +85°C is guaranteed. Note 2. The condition that 2.4 V  AVDD  3.6 V is guaranteed when +85°C  TA  +105°C. Note 3. The condition that 2.4 V  VDD  3.6 V is guaranteed when +85°C  TA  +105°C. Caution P30 and P51 to P56 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. (TA = -40 to +85°C, 1.6 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (4/5) Items Symbol Conditions MIN. TYP . MAX. Unit Output voltage, high V OH1 P00 to P04, P30 to P33, P40, P50 to P57, P130 2.7 V  VDD  3.6 V, IOH = -2.0 mA VDD - 0.6 V 1.8 V  VDD  3.6 V, IOH = -1.5 mA VDD - 0.5 V 1.6 V  VDD  3.6 V Note 1, IOH = -1.0 mA VDD - 0.5 V VOH2 P10 to P17, P20 to P25 1.6 V  AVDD  3.6 V Note 2, IOH = -100 A AVDD - 0.5 V Output voltage, low V OL1 P00 to P04, P30 to P33, P40, P50 to P57, P130 2.7 V  VDD  3.6 V, IOL = 3.0 mA 0.6 V 2.7 V  VDD  3.6 V, IOL = 1.5 mA 0.4 V 1.8 V  VDD  3.6 V Note 3, IOL = 0.6 mA 0.4 V 1.6 V  AVDD  3.6 V Note 1, IOL = 0.3 mA 0.4 V VOL2 P10 to P17, P20 to P25 1.6 V  AVDD  3.6 V Note 2, IOL = 400 A 0.4 V VOL3 P60 to P63 2.7 V  VDD  3.6 V, IOL = 3.0 mA 0.4 V 1.8 V  VDD  3.6 V Note 3, IOL = 2.0 mA 0.4 V 1.6 V  AVDD  3.6 V Note 1, IOL = 1.0 mA 0.4 V

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 23 of 99 Jan 16, 2015 Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. (TA = -40 to +85°C, 1.6 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (5/5) Items Symbol Conditions MIN. TYP. MAX. Unit Input leakage current, high ILIH1 P00 to P04, P30 to P33, P40, P50 to P57, P60 to P63, P130, P137 V I = VDD 1 A ILIH2 RESET VI = VDD 1 A ILIH3 P121 to P124 (X1, X2, EXCLK, XT1, XT2, EXCLKS) V I = VDD In input port or external clock input In resonator connection ILIH4 P10 to P17, P20 to P25 VI = AVDD 1 A Input leakage current, low I LIL1 P00 to P04, P30 to P33, P40, P50 to P57, P60 to P63, P130, P137 V I = VSS -1 A ILIL2 RESET VI = VSS -1 A ILIL3 P121 to P124 (X1, X2, EXCLK, XT1, XT2, EXCLKS) V I = VSS In input port or external clock input In resonator connection -10 ILIL4 P10 to P17, P20 to P25 VI = AVSS -1 A On-chip pull-up resistance R U P00 to P04, P30 to P33, P40, P50 to P57, P130 V I = VSS, In input port 10 20 100 k 

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 24 of 99 Jan 16, 2015

2.3.2 Supply current characteristics

(Notes and Remarks are listed on the next page.) (TA = -40 to +85°C, 1.6 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP . MAX. Unit Supply current Note 1 IDD1 Operating mode HS (high-speed main) mode f IH = 24 MHz Note 3, TA = -40 to +105°C Basic operation V DD = 3.0 V 1.4 mA HS (high-speed main) mode f IH = 24 MHz Note 3, TA = -40 to +85°C Normal operation V DD = 3.0 V 3.2 6.3 mA fIH = 24 MHz Note 3, TA = +85 to +105°C Normal operation V DD = 3.0 V 6.7 fIH = 16 MHz Note 3, TA = -40 to +85°C Normal operation V DD = 3.0 V 2.4 4.6 fIH = 16 MHz Note 3, TA = +85 to +105°C Normal operation V DD = 3.0 V 4.9 LS (low-speed main) mode (MCSEL = 0) f IH = 8 MHz Note 3, TA = -40 to +85°C Normal operation V DD = 3.0 V 1.1 2.0 mA VDD = 2.0 V 1.1 2.0 LS (low-speed main) mode (MCSEL = 1) f IH = 4 MHz Note 3, TA = -40 to +85°C Normal operation V DD = 3.0 V 0.72 1.30 mA VDD = 2.0 V 0.72 1.30 fIM = 4 MHz Note 7, TA = -40 to +85°C Normal operation V DD = 3.3 V 0.58 1.10 VDD = 3.0 V 0.58 1.10 LV (low-voltage main) mode f IH = 4 MHz Note 3, TA = -40 to +85°C Normal operation V DD = 3.0 V 1.2 1.8 mA VDD = 2.0 V 1.2 1.8 LP (low-power main) mode Note 5 (MCSEL = 1) fIH = 1 MHz Note 3, TA = -40 to +85°C Normal operation VDD = 3.0 V 290 480 A VDD = 2.0 V 290 480 fIM = 1 MHz Note 5, TA = -40 to +85°C Normal operation V DD = 3.0 V 124 230 VDD = 2.0 V 124 230 HS (high-speed main) mode f MX = 20 MHz Note 2, TA = -40 to +85°C Normal operation V DD = 3.0 V Square wave input 2.7 5.3 mA Resonator connection 2.8 5.5 fMX = 20 MHz Note 2, TA = +85 to +105°C Normal operation V DD = 3.0 V Square wave input 5.7 Resonator connection 5.8 fMX = 10 MHz Note 2, TA = -40 to +85°C Normal operation V DD = 3.0 V Square wave input 1.8 3.1 Resonator connection 1.9 3.2 fMX = 10 MHz Note 2, TA = +85 to +105°C Normal operation V DD = 3.0 V Square wave input 3.4 Resonator connection 3.5 LS (low-speed main) mode (MCSEL = 0) f MX = 8 MHz Note 2, TA = -40 to +85°C Normal operation V DD = 3.0 V Square wave input 0.9 1.9 mA Resonator connection 1.0 2.0 fMX = 8 MHz Note 2, TA = -40 to +85°C Normal operation V DD = 2.0 V Square wave input 0.9 1.9 Resonator connection 1.0 2.0 LS (low-speed main) mode (MCSEL = 1) f MX = 4 MHz Note 3, TA = -40 to +85°C Normal operation VDD = 3.0 V Square wave input 0.6 1.1 mA Resonator connection 0.6 1.2 fMX = 4 MHz Note 3, TA = -40 to +85°C Normal operation V DD = 2.0 V Square wave input 0.6 1.1 Resonator connection 0.6 1.2 LP (low-power main) mode (MCSEL = 1) f MX = 1 MHz Note 2, TA = -40 to +85°C Normal operation V DD = 3.0 V Square wave input 100 190 A Resonator connection 136 250 fMX = 1 MHz Note 2, TA = -40 to +85°C Normal operation V DD = 2.0 V Square wave input 100 190 Resonator connection 136 250 (1/4) <R> <R> <R> <R> <R>

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 25 of 99 Jan 16, 2015 Note 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The MAX values include the peripheral operating current. Ho wever, these values do not include the current flowing into the A/D converter, comparator, LVD circuit, I/O ports, and on-chip pull-up/pull-down resistors, and the current flowing during data flash rewrite. Note 2. When the high-speed on-chip oscillator clock, middle-speed on-ch ip oscillator clock, low-sp eed on-chip oscillator clock, and sub clock are stopped. Note 3. When the high-speed system clock, middle-s peed on-chip oscillator clock, low-s peed on-chip oscillator clock, and sub clock are stopped. Note 4. When the high-speed system clock, high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock, low-speed on-chip oscillator clock, and sub clock are stopped. When ultra-low-power consumption oscillation is set (AMPHS1, AMPHS0) = (1, 0). The values do not include the current flowing into the real-time clock, 12-bit interval timer, and watchdog timer. Note 5. When the high-speed system clock, high-speed on-chip oscillator clock, sub clock, and low-speed on-chip oscillator clock are stopped. The MAX values include the current of peripher al operation except BGO operation, and the STOP leakage current. However, the real time clock, watchdog timer, LVD circuit, and A/D converter are stopped. Note 6. When the high-speed system clock, high-s peed on-chip oscillator clock, middle-s peed on-chip oscillator clock, and sub clock are stopped. Note 7. When the high-speed system clock, high-speed on-chip oscillator clock, low-speed on-chip oscillator clock, and sub clock are stopped. Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 2. fIH: High-speed on-chip oscillator clock frequency (24 MHz max.) Remark 3. fIM: Middle-speed on-chip oscillator clock frequency (4 MHz max.) Remark 4. fIL: Low-speed on-chip oscillator clock frequency Remark 5. fSX: Sub clock frequency (XT1 clock oscillation frequency) Remark 6. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency or low-speed on-chip oscillator clock frequency) Remark 7. Except subsystem clock operation, temperature condition of the TYP . value is TA = 25°C (TA = -40 to +85°C, 1.6 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (2/4) Parameter Symbol Conditions MIN. TYP . MAX. Unit Supply current Note 1 IDD1 Operating mode Subsystem clock operation f SX = 32.768 kHz, TA = -40°C Note 4 Normal operation Square wave input 3.2 6.1 A Resonator connection 3.3 6.1 fSX = 32.768 kHz, TA = +25°C Note 4 Normal operation Square wave input 3.4 6.1 Resonator connection 3.6 6.1 fSX = 32.768 kHz, TA = +50°C Note 4 Normal operation Square wave input 3.5 6.7 Resonator connection 3.7 6.7 fSX = 32.768 kHz, TA = +70°C Note 4 Normal operation Square wave input 3.7 7.5 Resonator connection 3.9 7.5 fSX = 32.768 kHz, TA = +85°C Note 4 Normal operation Square wave input 4.0 8.9 Resonator connection 4.2 8.9 fSX = 32.768 kHz, TA = +105°C Note 4 Normal operation Square wave input 4.5 21.0 Resonator connection 4.7 21.1 fIL = 15 kHz, TA = -40°C Note 6 Normal operation 1.8 5.9 fIL = 15 kHz, TA = +25°C Note 6 Normal operation 1.9 5.9 fIL = 15 kHz, TA = +85°C Note 6 Normal operation 2.3 8.7 fIL = 15 kHz, TA = +105°C Note 6 Normal operation 3.0 20.9 <R>

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 26 of 99 Jan 16, 2015 (Notes and Remarks are listed on the next page.) (TA = -40 to +85°C, 1.6 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (3/4) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply current Note 1 IDD2 Note 2 HALT mode HS (high-speed main) mode fIH = 24 MHz Note 4, TA = -40 to +85°C VDD = 3.0 V 0.37 1.83 mA fIH = 24 MHz Note 4, TA = +85 to +105°C VDD = 3.0 V 2.85 fIH = 16 MHz Note 4, TA = -40 to +85°C VDD = 3.0 V 0.36 1.38 fIH = 16 MHz Note 4, TA = +85 to +105°C VDD = 3.0 V 2.08 LS (low-speed main) mode (MCSEL = 0) f IH = 8 MHz Note 4, TA = -40 to +85°C VDD = 3.0 V 250 710 A VDD = 2.0 V 250 710 LS (low-speed main) mode (MCSEL = 1) fIH = 4 MHz Note 4, TA = -40 to +85°C VDD = 3.0 V 204 400 A VDD = 2.0 V 204 400 fIM = 4 MHz Note 7, TA = -40 to +85°C VDD = 3.0 V 40 250 VDD = 2.0 V 40 250 LV (low-voltage main) mode fIH = 4 MHz Note 4, TA = -40 to +85°C VDD = 3.0 V 425 800 mA VDD = 2.0 V 425 800 LP (low-power main) mode (MCSEL = 1) fIH = 1 MHz Note 4, TA = -40 to +85°C VDD = 3.0 V 192 400 A VDD = 2.0 V 192 400 fIM = 1 MHz Note 6, TA = -40 to +85°C VDD = 3.0 V 27 100 VDD = 2.0 V 27 100 HS (high-speed main) mode fMX = 20 MHz Note 3, TA = -40 to +85°C VDD = 3.0 V Square wave input 0.20 1.55 mA Resonator connection 0.40 1.74 fMX = 20 MHz Note 3, TA = +85 to +105°C VDD = 3.0 V Square wave input 2.45 Resonator connection 2.57 fMX = 10 MHz Note 3, TA = -40 to +85°C VDD = 3.0 V Square wave input 0.15 0.86 Resonator connection 0.30 0.93 fMX = 10 MHz Note 3, TA = +85 to +105°C VDD = 3.0 V Square wave input 1.28 Resonator connection 1.36 LS (low-speed main) mode (MCSEL = 0) f MX = 8 MHz Note 3, TA = -40 to +85°C VDD = 3.0 V Square wave input 68 550 A Resonator connection 120 590 fMX = 8 MHz Note 3, TA = -40 to +85°C VDD = 2.0 V Square wave input 68 550 Resonator connection 120 590 LS (low-speed main) mode (MCSEL = 1) fMX = 4 MHz Note 3, TA = -40 to +85°C VDD = 3.0 V Square wave input 23 128 A Resonator connection 65 200 fMX = 1 MHz Note 3, TA = -40 to +85°C VDD = 2.0 V Square wave input 23 128 Resonator connection 65 200 LP (low-power main) mode (MCSEL = 1) fMX = 4 MHz Note 3, TA = -40 to +85°C VDD = 3.0 V Square wave input 10 64 A Resonator connection 48 150 fMX = 1 MHz Note 3, TA = -40 to +85°C VDD = 2.0 V Square wave input 10 64 Resonator connection 48 150 Subsystem clock operation f SX = 32.768 kHz, TA = -40°C Note 5 Square wave input 0.24 0.57 A Resonator connection 0.42 0.76 fSX = 32.768 kHz, TA = +25°C Note 5 Square wave input 0.30 0.57 Resonator connection 0.54 0.76 fSX = 32.768 kHz, TA = +50°C Note 5 Square wave input 0.35 1.17 Resonator connection 0.60 1.36 fSX = 32.768 kHz, TA = +70°C Note 5 Square wave input 0.42 1.97 Resonator connection 0.70 2.16 fSX = 32.768 kHz, TA = +85°C Note 5 Square wave input 0.80 3.37 Resonator connection 0.95 3.56 fSX = 32.768 kHz, TA = +105°C Note 5 Square wave input 1.80 17.10 Resonator connection 2.20 17.50 fIL = 15 kHz, TA = -40°C Note 6 0.40 1.22 A fIL = 15 kHz, TA = +25°C Note 6 0.47 1.22 fIL = 15 kHz, TA = +85°C Note 6 0.80 3.30 fIL = 15 kHz, TA = +105°C Note 6 2.00 17.30 <R> <R> <R> <R> <R> <R>

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 27 of 99 Jan 16, 2015 Note 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The MAX values include the peripheral operating current. Ho wever, these values do not include the current flowing into the A/D converter, comparator, LVD circuit, I/O ports, and on-chip pull-up/pull-down resistors, and the current flowing during data flash rewrite. Note 2. When the HALT instruction is executed in the flash memory. Note 3. When the high-speed on-chip oscillator clock, middle-speed on-ch ip oscillator clock, low-sp eed on-chip oscillator clock, and sub clock are stopped. Note 4. When the high-speed system clock, middle-s peed on-chip oscillator clock, low-s peed on-chip oscillator clock, and sub clock are stopped. Note 5. When the high-speed system clock, middle-speed on-chip oscillator clock, low-speed on-chip oscillator clock, and high- speed on-chip oscillator clock are stopped. When RTCLPC = 1 and ultra-low-power consumption oscillation is set (AMPHS1, AMPHS0) = (1, 0). The values include the current flowing into the real-time clock. However, the values do not include the current flowing into the 12-bit interval timer and watchdog timer. Note 6. When the high-speed on-chip oscillator clock, middle-speed on -chip oscillator clock, high-speed system clock, and sub clock are stopped. Note 7. When the high-speed system clock, high-speed on-chip oscillator clock, low-speed on-chip oscillator clock, and sub clock are stopped. Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 2. fIH: High-speed on-chip oscillator clock frequency (24 MHz max.) Remark 3. fIM: Middle-speed on-chip oscillator clock frequency (4 MHz max.) Remark 4. fIL: Low-speed on-chip oscillator clock frequency Remark 5. fSX: Sub clock frequency (XT1 clock oscillation frequency) Remark 6. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency or low-speed on-chip oscillator clock frequency) Remark 7. Except subsystem clock operation, temperature condition of the TYP . value is TA = 25°C <R>

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 28 of 99 Jan 16, 2015 Note 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The MAX values include the peripheral operating current. Ho wever, these values do not include the current flowing into the A/D converter, comparator, LVD circuit, I/O ports, and on-chip pull-up/pull-down resistors, and the current flowing during data flash rewrite. Note 2. The values do not include the current flowing into the real-time clock, 12-bit interval timer, and watchdog timer. Note 3. For the setting of the current values when operating the s ubsystem clock in STOP mode, see the current values when operating the subsystem clock in HALT mode. (TA = -40 to +85°C, 1.6 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (4/4) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply current Note 1 IDD3 Note 2 STOP mode Note 3 TA = +25°C 0.22 0.51 TA = +50°C 0.27 1.10 TA = +70°C 0.37 1.90 TA = +85°C 0.60 3.30 TA = +105°C 1.50 17.00 <R> <R>

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 29 of 99 Jan 16, 2015 Peripheral Functions (Common to all products) (Notes and Remarks are listed on the next page.) (TA = -40 to +85°C, 1.6 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Low-speed on-chip oscillator operating current IFIL Note 1 0.20 A RTC operating current IRTC Notes 1, 2, 3 fSX = 32.768 kHz 0.02 A 12-bit interval timer operating current ITMKA Notes 1, 2, 4 fSX = 32.768 kHz 0.04 A 8-bit interval timer operating current Notes 1, 12 ITMT fSX = 32.768 kHz fMAIN stopped (per unit) 8-bit counter mode  2-channel operation 0.12 A 16-bit counter mode operation 0.10 A Watchdog timer operating current IWDT Notes 1, 2, 5 fIL = 15 kHz 0.22 A A/D converter operating current IADC Notes 6, 13 During maximum-speed conversion AV DD = 3.0 V 420 720 A AVREF(+) current IAVREF AVREFP = 3.0 V, ADREFP1 = 0, ADREFP0 = 1 Note 15 14.0 25.0 A Internal reference voltage (1.45 V) current Notes 1, 16 IADREF 85.0 A Temperature sensor operating current ITMPS Note 1 85.0 A Comparator operating current ICMP Notes 11, 13 AVDD = 3.6 V, Regulator output voltage = 2.1 V Comparator high-speed mode Window mode 12.5 A Comparator low-speed mode Window mode 3.0 Comparator high-speed mode Standard mode 6.5 Comparator low-speed mode Standard mode 1.7 AV DD = 3.6 V, Regulator output voltage = 1.8 V Comparator high-speed mode Window mode 8.0 Comparator low-speed mode Window mode 2.2 Comparator high-speed mode Standard mode 4.0 Comparator low-speed mode Standard mode 1.3 Operational amplifier operating current Notes 13, 17 IAMP Low-power consumption mode One operational amplifier unit operates Note 18 2.5 4.0 A Two operational amplifier units operate Note 18 4.5 8.0 Three operational amplifier units operate Note 18 6.5 11.0 Four operational amplifier units operate Note 18 8.5 14.0 High-speed mode One operational amplifier unit operates Note 18 140 220 Two operational amplifier units operate Note 18 280 410 Three operational amplifier units operate Note 18 420 600 Four operational amplifier units operate Note 18 560 780 LVD operating current ILVD Notes 1, 7 0.10 A (1/2)

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 30 of 99 Jan 16, 2015 Note 1. Current flowing to VDD. Note 2. When the high-speed on-chip oscillator cloc k, middle-speed on-chip oscillator clock, and high-speed system clock are stopped. Note 3. Current flowing only to the real-time clock (RTC) (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either I DD1 or IDD2, and IRTC, when the real-time clock operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock operation includes the operational current of the real-time clock. Note 4. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IIT, when the 12-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. Note 5. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). The supply current of the RL78 microcontrollers is the sum of I DD1, IDD2 or IDD3 and IWDT when the watchdog timer is in operation. Note 6. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode. Note 7. Current flowing only to the LVD circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ILVD when the LVD circuit is in operation. Note 8. Current flowing during programming of the data flash. Note 9. Current flowing during self-programming. Note 10. For shift time to the SNOOZE mode, see 23.3.3 SNOOZE mode in the RL78/I1D User’s Manual. Note 11. Current flowing only to the comparator circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2, or IDD3 and ICMP when the comparator circuit is in operation. Note 12. Current flowing only to the 8-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supply current of the RL78 microc ontrollers is the sum of the values of either I DD1 or IDD2, and IIT, when the 8-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, I FIL should be added. Note 13. Current flowing to AVDD. Note 14. Current flowing from the internal reference voltage (1.45 V). Note 15. Current flowing into AVREFP. Note 16. Current consumed by generating the internal reference voltage (1.45 V). Note 17. Current flowing only to the operational am plifier. The current value of the RL78 microcontrollers is the sum of I DD1, IDD2, or IDD3 and IAMP when the operational amplifier is operating in operating mode, HALT mode, or STOP mode. Note 18. The values include the operating current of the operational amplifier reference current circuit. Remark 1. fIL: Low-speed on-chip oscillator clock frequency Remark 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 3. fCLK: CPU/peripheral hardware clock frequency Remark 4. Temperature condition of the TYP . value is TA = 25°C

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 31 of 99 Jan 16, 2015 Note 1. Current flowing to VDD. Note 2. Current flowing during programming of the data flash. Note 3. Current flowing during self-programming. Note 4. Current flowing to AVDD. Remark 1. fIL: Low-speed on-chip oscillator clock frequency Remark 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 3. fCLK: CPU/peripheral hardware clock frequency Remark 4. Temperature condition of the TYP . value is TA = 25°C (TA = -40 to +85°C, 1.6 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (2/2) Parameter Symbol Conditions MIN. TYP . MAX. Unit Self-programming operating current IFSP Notes 1, 3 2.0 12.20 mA BGO current IBGO Notes 1, 2 2.0 12.20 mA SNOOZE operating current ISNOZ Note 1 ADC operation AVREFP = VDD =3.0 V TA = -40 to +85°C The mode is performed Note 1 0.50 0.60 mA The A/D conversion operations are performed Note 1 0.60 0.75 mA The A/D conversion operations are performed Note 4 420 720 A ADC operation AV REFP = VDD =3.0 V TA = +85 to +105°C The mode is performed Note 1 0.50 1.10 mA The A/D conversion operations are performed Note 1 0.60 1.34 mA The A/D conversion operations are performed Note 4 420 720 A CSI/UART operation T A = -40 to +85°C 0.70 0.84 mA TA = +85 to +105°C 0.70 1.54 mA

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 32 of 99 Jan 16, 2015

2.4 AC Characteristics

Remark fMCK: Timer array unit operation clock frequency (Operation clock to be set by the CKSmn bit of timer mode register mn (TMRmn). m: Unit number (m = 0), n: Channel number (n = 0 to 3)) (TA = -40 to +85°C, 1.6 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Items Symbol Conditions MIN. TYP. MAX. Unit Instruction cycle (minimum instruction execution time) T CY Main system clock MAIN) operation HS (high-speed main) mode 2.7 V  VDD  3.6 V 0.04167 1 s 2.4 V  VDD < 2.7 V 0.0625 1 s LS (low-speed main) mode 1.8 V  VDD  3.6 V PMMC. MCSEL = 0 0.125 1 s 1.8 V  VDD  3.6 V PMMC. MCSEL = 1 0.25 1 LP (low-power main) mode 1.8 V  VDD  3.6 V 1 s LV (low-voltage main) mode 1.8 V  VDD  3.6 V 0.25 1 s 1.6 V  VDD < 1.8 V 0.34 1 Subsystem clock SUB) operation fIL 1.8 V  VDD  3.6 V 66.7 In the self- programming mode HS (high-speed main) mode 2.7 V  VDD  3.6 V 0.04167 1 s 2.4 V  VDD < 2.7 V 0.0625 1 s LS (low-speed main) mode 1.8 V  VDD  3.6 V 0.125 1 s LV (low-voltage main) mode 1.8 V  VDD  3.6 V 0.25 1 s External system clock frequency f EX 2.7 V  VDD  3.6 V 1.0 20.0 MHz 2.4 V  VDD <2.7 V 1.0 16.0 MHz 1.8 V  VDD <2.4 V 1 8 MHz 1.6 V  VDD <1.8 V 1 4 MHz fEXS 32 35 kHz External system clock input high-level width, low-level width t EXH, tEXL 2.7 V  VDD  3.6 V 24 ns 2.4 V  VDD <2.7 V 30 ns 1.8 V  VDD <2.4 V 60 ns 1.6 V  VDD <1.8 V 120 ns tEXHS, tEXLS 13.7 s TI00 to TI03 input high-level width, low-level width t TIH, tTIL 1/fMCK + ns (1/2)

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 33 of 99 Jan 16, 2015 (TA = -40 to +85°C, 1.6 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (2/2) Items Symbol Conditions MIN. TYP. MAX. Unit TO00 to TO03 output frequency f TO HS (high-speed main) mode 2.7 V  VDD  3.6 V 8 MHz 2.4 V  VDD < 2.7 V 4 LS (low-speed main) mode 1.8 V  VDD  3.6 V 4 LP (low-power main) mode 1.8 V  VDD  3.6 V 0.5 LV (low-voltage main) mode 1.6 V  VDD  3.6 V 2 PCLBUZ0, PCLBUZ1 output frequency fPCL HS (high-speed main) mode 2.7 V  VDD  3.6 V 8 MHz 2.4 V  VDD < 2.7 V 4 LS (low-speed main) mode 1.8 V  VDD  3.6 V 4 LP (low-power main) mode 1.8 V  VDD  3.6 V 1 LV (low-voltage main) mode 1.8 V  VDD  3.6 V 4 1.6 V  VDD < 1.8 V 2 Interrupt input high-level width, low-level width t INTH, tINTL INTP0 to INTP6 1.6 V  VDD  3.6 V 1 s Key interrupt input low-level width t KR KR0 to KR3 1.8 V  VDD  3.6 V 250 ns 1.6 V  VDD < 1.8 V 1 s RESET low-level width tRSL 10 s

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 34 of 99 Jan 16, 2015 AC Timing Test Points External System Clock Timing TI/TO Timing VIH/VOH VIL/VOL VIH/VOHTest points VIL/VOL EXCLK/EXCLKS 1/fEX 1/fEXS tEXL tEXLS tEXH tEXHS tTIL tTIH 1/fTO TI00 to TI03 TO00 to TO03

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 35 of 99 Jan 16, 2015 Interrupt Request Input Timing Key Interrupt Input Timing RESET Input Timing INTP0 to INTP6 tINTL tINTH tKR KR0 to KR3 tRSL RESET

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 36 of 99 Jan 16, 2015

2.5 Peripheral Functions Characteristics

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 37 of 99 Jan 16, 2015

2.5.1 Serial array unit

Note 1. Transfer rate in the SNOOZE mode is 4800 bps only. Note 2. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 24 MHz (2.7 V  VDD  3.6 V) 16 MHz (2.4 V  VDD  3.6 V) LS (low-speed main) mode: 8 MHz (1.8 V  VDD  3.6 V) LP (low-power main) mode: 1 MHz (1.8 V  VDD  3.6 V) LV (low-voltage main) mode: 4 MHz (1.6 V  VDD  3.6 V) Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). Note 1. Transfer rate in the SNOOZE mode is 4800 bps only. Note 2. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 24 MHz (2.7 V  VDD  3.6 V) 16 MHz (2.4 V  VDD  3.6 V) Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). (1) During communication at same potential (UART mode) (TA = -40 to +85°C, 1.6 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LP (Low-power main) mode LV (low-voltage main) Mode Unit Transfer rate Note 1 2.4 V  VDD  3.6 V fMCK/6 fMCK/6 fMCK/6 fMCK/6 bps Theoretical value of the maximum transfer rate fMCK = fCLK Note 2 4.01 .30 .10 .6 Mbps 1.8 V  VDD  3.6 V — fMCK/6 fMCK/6 fMCK/6 bps Theoretical value of the maximum transfer rate fMCK = fCLK Note 2 —1 .3 0 .1 0 .6 Mbps 1.7 V  VDD  3.6 V — — — fMCK/6 bps Theoretical value of the maximum transfer rate fMCK = fCLK Note 2 ——— 0 .6 Mbps 1.6 V  VDD  3.6 V — — — fMCK/6 bps Theoretical value of the maximum transfer rate fMCK = fCLK Note 2 ——— 0 .6 Mbps (TA = +85 to +105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. Transfer rate Note 1 2.4 V  VDD  3.6 V fMCK/12 bps Theoretical value of the maximum transfer rate fMCK = fCLK Note 2

2.0 Mbps

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 38 of 99 Jan 16, 2015 UART mode connection diagram (during communication at same potential) UART mode bit width (during communication at same potential) (reference) Remark 1. q: UART number (q = 0), g: PIM and POM number (g = 5) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)) TxDq RxDq User’s device Rx Tx RL78 microcontroller Baud rate error tolerance TxDq RxDq High-/Low-bit width 1/Transfer rate

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 39 of 99 Jan 16, 2015 Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 4. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 5) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) (2) During communication at same potential (CSI mo de) (master mode, SCKp... internal clock output, corresponding CSI00 only) (TA = -40 to +85°C, 2.7 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LP (Low-power main) mode LV (low-voltage main) Mode Unit SCKp cycle time t KCY1 tKCY1 fCLK/2 83.3 250 2000 500 ns SCKp high-/low-level width t KL1 tKCY1/2 - 10 tKCY1/2 - 50 tKCY1/2 - 50 tKCY1/2 - 50 ns SIp setup time (to SCKp↑) Note 1 tSIK1 33 110 110 110 ns SIp hold time (from SCKp↑) Note 2 tKSI1 10 10 10 10 ns Delay time from SCKp↓ to SOp output Note 3 tKSO1 C = 20 pF Note 4 10 20 20 20 ns

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 40 of 99 Jan 16, 2015 Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 4. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 5) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)) (3) During communication at same potential (CSI mo de) (master mode, SCKp... internal clock output) (TA = -40 to +85°C, 1.6 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LP (Low-power main) mode LV (low-voltage main) Mode Unit SCKp cycle time tKCY1 tKCY1  fCLK/4 2.7 V  VDD  3.6 V 167 500 4000 1000 ns 2.4 V  VDD  3.6 V 250 1.8 V  VDD  3.6 V — SCKp high-/ low-level width t KH1, tKL1 2.7 V  VDD  3.6 V tKCY1/2 - tKCY1/2 - tKCY1/2 - tKCY1/2 - ns 2.4 V  VDD  3.6 V tKCY1/2 - 1.8 V  VDD  3.6 V — 1.7 V  VDD  3.6 V — — — tKCY1/2 - 1001.6 V  VDD  3.6 V — — — SIp setup time (to SCKp↑) Note 1 tSIK1 2.7 V  VDD  3.6 V 58 110 110 110 ns 2.4 V  VDD  3.6 V 75 1.8 V  VDD  3.6 V — 1.7 V  VDD  3.6 V — — — 220 SIp hold time (from SCKp↑) Note 2 tKSI1 2.4 V  VDD  3.6 V 19 19 19 19 ns 1.8 V  VDD  3.6 V — Delay time from SCKp↓ to SOp output Note 3 tKSO1 C = 30 pF Note 4 1.8 V  VDD  3.6 V —

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 41 of 99 Jan 16, 2015 Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 4. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 5) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)) (3) During communication at same potential (CSI mo de) (master mode, SCKp... internal clock output) (TA = +85 to +105°C, 2.7 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCKp cycle time tKCY1 tKCY1  fCLK/4 2.7 V  VDD  3.6 V 250 ns 2.4 V  VDD  3.6 V 500 ns SCKp high-/low-level width tKH1, tKL1 2.7 V  VDD  3.6 V tKCY1/2 - 36 ns 2.4 V  VDD  3.6 V tKCY1/2 - 76 ns SIp setup time (to SCKp↑) Note 1 tSIK1 2.7 V  VDD  3.6 V 66 ns 2.4 V  VDD  3.6 V 133 ns SIp hold time (from SCKp↑) Note 2 tKSI1 38 ns Delay time from SCKp↓ to SOp output Note 3 tKSO1 C = 30 pF Note 4 50 ns

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 42 of 99 Jan 16, 2015 Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 4. C is the load capacitance of the SOp output lines. Note 5. The maximum transfer rate when using the SNOOZE mode is 1 Mbps. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 5) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)) (4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +85°C, 1.6 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LP (Low-power main) mode LV (low-voltage main) Mode Unit SCKp cycle time Note 5 tKCY2 2.7 V  VDD  3.6 V fMCK > 16 MHz 8/fMCK —————— n s fMCK  16 MHz 6/fMCK 6/fMCK 6/fMCK 6/fMCK 2.4 V  VDD  3.6 V 6/f MCK and 500 6/fMCK 6/fMCK 6/fMCK 1.8 V  VDD  3.6 V — 6/f MCK 6/fMCK 6/fMCK SCKp high-/ low-level width tKH2, tKL2 2.7 V  VDD  3.6 V t KCY2/2 - tKCY2/2 - tKCY2/2 - tKCY2/2 - ns 2.4 V  VDD  3.6 V t KCY2/2 - 18 tKCY2/2 - 18 tKCY2/2 - 18 tKCY2/2 - 18 1.8 V  VDD  3.6 V — 1.7 V  VDD  3.6 V — — — t KCY2/2 SIp setup time (to SCKp↑) Note 1 tSIK2 2.7 V  VDD  3.6 V 1/f MCK + 20 1/fMCK + 30 1/fMCK + 30 1/fMCK + 30 ns 2.4 V  VDD  3.6 V 1/f MCK + 30 1.8 V  VDD  3.6 V — 1.7 V  VDD  3.6 V — — — 1/f MCK SIp hold time (from SCKp↑) Note 2 tKSI2 2.4 V  VDD  3.6 V 1/f MCK + 31 1/fMCK + 31 1/fMCK + 31 1/fMCK + 31 ns 1.8 V  VDD  3.6 V — 1.7 V  VDD  3.6 V — — — 1/f MCK Delay time from SCKp↓ to SOp output Note 3 tKSO2 C = 30 pF Note 4 2.7 V  VDD  3.6 V 2/f MCK + 44 2/fMCK + 110 2/fMCK + 110 2/fMCK + 110 ns 2.4 V  VDD  3.6 V 2/f MCK + 75 1.8 V  VDD  3.6 V — 1.7 V  VDD  3 . 6 V ——— 2 / f MCK (1/2)

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 43 of 99 Jan 16, 2015 Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 5) CSI mode connection diagram (during communication at same potential) CSI mode connection diagram (during communication at same potential) (Slave Transmission of slave select input function (CSI00)) Remark 1. p: CSI number (p = 00, 01) Remark 2. m: Unit number, n: Channel number (mn = 00, 01) (4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +85°C, 1.6 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (2/2) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LP (Low-power main) mode LV (low-voltage main) Mode Unit SSI00 setup time t SSIK DAPmn = 0 2.7 V  VDD  3.6 V 120 120 120 120 ns 2.4 V  VDD < 2.7 V 200 200 200 200 1.8 V  VDD < 2.4 V — 1.6 V  VDD < 1.8 V — — — 400 DAPmn = 1 2.7 V  VDD  3.6 V 1/f MCK + 120 1/fMCK + 120 1/fMCK + 120 1/fMCK + 120 ns 2.4 V  VDD < 2.7 V 1/f MCK + 200 1/fMCK + 200 1/fMCK + 200 1/fMCK + 200 1.8 V  VDD < 2.4 V — 1.6 V  VDD < 1.8 V — — — 1/fMCK + 400 SSI00 hold time t KSSI DAPmn = 0 2.7 V  VDD  3.6 V 1/f MCK + 120 1/fMCK + 120 1/fMCK + 120 1/fMCK + 120 ns 2.4 V  VDD < 2.7 V 1/f MCK + 200 1/fMCK + 200 1/fMCK + 200 1/fMCK + 200 1.8 V  VDD < 2.4 V — 1.6 V  VDD < 1.8 V — — — 1/fMCK + 400 DAPmn = 1 2.7 V  VDD  3.6 V 120 120 120 120 ns 2.4 V  VDD < 2.7 V 200 200 200 200 1.8 V  VDD < 2.4 V — 1.6 V  VDD < 1.8 V — — — 400 SCKp SOp User's device SCK SI SIp SO RL78 microcontroller SCK00 SO00 User's device SCK SI SI00 SO SSI00 SSO RL78 microcontroller

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 44 of 99 Jan 16, 2015 Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 4. C is the load capacitance of the SOp output lines. Note 5. The maximum transfer rate when using the SNOOZE mode is 1 Mbps. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 5) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)) (4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (TA = +85 to +105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCKp cycle time Note 5 tKCY2 2.7 V  VDD  3.6 V f MCK  16 MHz 16/fMCK ns fMCK  16 MHz 12/fMCK ns 2.4 V  VDD  2.7 V 12/fMCK and 1000 ns SCKp high-/low-level width tKH2, tKL2 2.7 V  VDD  3.6 V tKCY2/2 - 16 ns 2.4 V  VDD  2.7 V tKCY2/2 - 36 ns SIp setup time (to SCKp↑) Note 1 tSIK2 2.7 V  VDD  3.6 V 1/fMCK + 40 ns 2.4 V  VDD  2.7 V 1/fMCK + 60 ns SIp hold time (from SCKp↑) Note 2 tKSI2 1/fMCK + 62 ns Delay time from SCKp↓ to SOp output Note 3 tKSO2 C = 30 pF Note 4 2.7 V  VDD  3.6 V 2/fMCK + 66 ns 2.4 V  VDD  2.7 V 2/fMCK + 113 ns (1/2)

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 45 of 99 Jan 16, 2015 Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 5) CSI mode connection diagram (during communication at same potential) CSI mode connection diagram (during communication at same potential) (Slave Transmission of slave select input function (CSI00)) Remark 1. p: CSI number (p = 00, 01) Remark 2. m: Unit number, n: Channel number (mn = 00, 01) (4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (TA = +85 to +105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (2/2) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SSI00 setup time tSSIK DAPmn = 0 2.7 V  VDD  3.6 V 240 ns 2.4 V  VDD  2.7 V 400 ns DAPmn = 1 2.7 V  VDD  3.6 V 1/fMCK + 240 ns 2.4 V  VDD  2.7 V 1/fMCK + 400 ns SSI00 hold time tKSSI DAPmn = 0 2.7 V  VDD  3.6 V 1/fMCK + 240 ns 2.4 V  VDD  2.7 V 1/fMCK + 400 ns DAPmn = 1 2.7 V  VDD  3.6 V 240 ns 2.4 V  VDD  2.7 V 400 ns SCKp SOp User's device SCK SI SIp SO RL78 microcontroller SCK00 SO00 User's device SCK SI SI00 SO SSI00 SSO RL78 microcontroller

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 46 of 99 Jan 16, 2015 CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) Remark 1. p: CSI number (p = 00, 01) Remark 2. m: Unit number, n: Channel number (mn = 00, 01) SIp SOp tKCY1, 2 Input data Output data SCKp tKL1, 2 tKH1, 2 tSIK1, 2 tKSI1, 2 tKSO1, 2 Input data Output data tKCY1, 2 tKH1, 2 tSIK1, 2 tKSI1, 2 tKSO1, 2 SIp SOp SCKp tKL1, 2

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 47 of 99 Jan 16, 2015 (Notes and Caution are listed on the next page.) (5) During communication at sa me potential (simplified I2C mode) (TA = -40 to +85°C, 1.6 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LP (Low-power main) mode LV (low-voltage main) Mode Unit SCLr clock frequency f SCL 2.7 V  VDD  3.6 V, Cb = 50 pF, Rb = 2.7 k 1000 Note 1 400 Note 1 250 Note 1 400 Note 1 kHz 1.8 V  VDD  3.6 V, Cb = 100 pF, Rb = 3 k 1.8 V  VDD < 2.7 V, Cb = 100 pF, Rb = 5 k — 300 Note 1 250 Note 1 300 Note 1 1.7 V  VDD < 1.8 V, Cb = 100 pF, Rb = 5 k ——— 250 Note 1 1.6 V  VDD < 1.8 V, Cb = 100 pF, Rb = 5 k ——— Hold time when SCLr = “L” tLOW 2.7 V  VDD  3.6 V, Cb = 50 pF, Rb = 2.7 k 475 1150 1150 1150 ns 1.8 V  VDD  3.6 V, Cb = 100 pF, Rb = 3 k 1.8 V  VDD < 2.7 V, Cb = 100 pF, Rb = 5 k — 1550 1550 1550 1.7 V  VDD < 1.8 V, Cb = 100 pF, Rb = 5 k ——— 1 850 1.6 V  VDD < 1.8 V, Cb = 100 pF, Rb = 5 k ——— Hold time when SCLr = “H” t HIGH 2.7 V  VDD  3.6 V, Cb = 50 pF, Rb = 2.7 k 475 1150 1150 1150 ns 1.8 V  VDD  3.6 V, Cb = 100 pF, Rb = 3 k 1.8 V  VDD < 2.7 V, Cb = 100 pF, Rb = 5 k — 1550 1550 1550 1.7 V  VDD < 1.8 V, Cb = 100 pF, Rb = 5 k ——— 1 850 1.6 V  VDD < 1.8 V, Cb = 100 pF, Rb = 5 k ——— Data setup time (reception) t SU: DAT 2.7 V  VDD  3.6 V, Cb = 50 pF, Rb = 2.7 k 1/fMCK + 85 Note 2 1/fMCK + 145 Note 2 1/fMCK + 145 Note 2 1/fMCK + 145 Note 2 ns 1.8 V  VDD  3.6 V, Cb = 100 pF, Rb = 3 k 1.8 V  VDD < 2.7 V, Cb = 100 pF, Rb = 5 k —1 /fMCK + 230 Note 2 1/fMCK + 230 Note 2 1/fMCK + 230 Note 2 1.7 V  VDD < 1.8 V, Cb = 100 pF, Rb = 5 k ——— 1 /fMCK + 290 Note 2 1.6 V  VDD < 1.8 V, Cb = 100 pF, Rb = 5 k ——— Data hold time (transmission) t HD: DAT 2.7 V  VDD  3.6 V, Cb = 50 pF, Rb = 2.7 k 03 0 503 0 503 0 503 0 5 n s 1.8 V  VDD  3.6 V, Cb = 100 pF, Rb = 3 k — — 355 355 355 1.8 V  VDD < 2.7 V, Cb = 100 pF, Rb = 5 k 1.7 V  VDD < 1.8 V, Cb = 100 pF, Rb = 5 k 1.6 V  VDD < 1.8 V, Cb = 100 pF, Rb = 5 k

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 48 of 99 Jan 16, 2015 Note 1. The value must also be equal to or less than fMCK/4. Note 2. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”. Caution Select the normal input buffer and the N-ch open drain output (V DD tolerance) mode for the SDAr pin and the normal output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register h (POMh).

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 49 of 99 Jan 16, 2015 Note 1. The value must also be equal to or less than fMCK/4. Note 2. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”. Caution Select the normal input buffer and the N-ch open drain output (V DD tolerance) mode for the SDAr pin and the normal output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register h (POMh). (5) During communication at sa me potential (simplified I2C mode) (TA = +85 to +105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCLr clock frequency fSCL 2.7 V  VDD  3.6 V, Cb = 50 pF, Rb = 2.7 k

400 Note 1 kHz

2.4 V  VDD  3.6 V, Cb = 100 pF, Rb = 3 k

100 Note 1 kHz

Hold time when SCLr = “L” t LOW 2.7 V  VDD  3.6 V, Cb = 50 pF, Rb = 2.7 k 1200 ns 2.4 V  VDD  3.6 V, Cb = 100 pF, Rb = 3 k 4600 ns Hold time when SCLr = “H” tHIGH 2.7 V  VDD  3.6 V, Cb = 50 pF, Rb = 2.7 k 1200 ns 2.4 V  VDD  3.6 V, Cb = 100 pF, Rb = 3 k 4600 ns Data setup time (reception) tSU: DAT 2.7 V  VDD  3.6 V, Cb = 50 pF, Rb = 2.7 k 1/fMCK + 220 Note 2 ns 2.4 V  VDD  3.6 V, Cb = 100 pF, Rb = 3 k 1/fMCK + 580 Note 2 ns Data hold time (transmission) t HD: DAT 2.7 V  VDD  3.6 V, Cb = 50 pF, Rb = 2.7 k 07 70 n s 2.4 V  VDD  3.6 V, Cb = 100 pF, Rb = 3 k 0 1420 ns

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 50 of 99 Jan 16, 2015 Simplified I2C mode connection diagram (during communication at same potential) Simplified I2C mode serial transfer timing (during communication at same potential) Remark 1. Rb[]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance Remark 2. r: IIC number (r = 00, 01), g: PIM number (g = 5), h: POM number (h = 5) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0), n: Channel number (n = 0, 1), mn = 00, 01) SDAr SCLr User’s device SDA SCL VDD Rb RL78 microcontroller SDAr SCLr 1/fSCL tLOW tHIGH tSU: DATtHD: DAT

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 51 of 99 Jan 16, 2015 Note 1. Transfer rate in the SNOOZE mode is 4,800 bps only. Note 2. Use it with VDD  Vb. Note 3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 24 MHz (2.7 V  VDD  3.6 V) 16 MHz (2.4 V  VDD  3.6 V) LS (low-speed main) mode: 8 MHz (1.8 V  VDD  3.6 V) LP (low-power main) mode: 1 MHz (1.8 V  VDD  3.6 V) LV (low-voltage main) mode: 4 MHz (1.6 V  VDD  3.6 V) Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (V DD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For V IH and VIL, see the DC characteristics with TTL input buffer selected. Remark 1. Vb[V]: Communication line voltage Remark 2. q: UART number (q = 0), g: PIM and POM number (g = 5) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01) (6) Communication at different potent ial (1.8 V, 2.5 V) (UART mode) (dedicated baud rate generator output) (TA = -40 to +85°C, 1.8 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LP (Low-power main) mode LV (low-voltage main) Mode Unit Transfer rate Notes 1, 2 reception 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V fMCK/6 Note 1 fMCK/6 Note 1 fMCK/6 Note 1 fMCK/6 Note 1 bps Theoretical value of the maximum transfer rate f MCK = fCLK Note 3 4.0 1.3 0.1 0.6 Mbps 1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V fMCK/6 Notes 1, 2 fMCK/6 Notes 1, 2 fMCK/6 Notes 1, 2 fMCK/6 Notes 1, 2 bps Theoretical value of the maximum transfer rate f MCK = fCLK Note 3 4.0 1.3 0.1 0.6 Mbps (1/2)

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 52 of 99 Jan 16, 2015 Note 1. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V  VDD  3.6 V and 2.3 V  Vb  2.7 V Note 2. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer. Note 3. Use it with VDD  Vb. Note 4. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 1.8 V  VDD < 3.3 V and 1.6 V  Vb  2.0 V Note 5. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 4 above to calculate the maximum transfer rate under conditions of the customer. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (V DD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For V IH and VIL, see the DC characteristics with TTL input buffer selected. (6) Communication at di fferent potential (1.8 V, 2.5V) (UART mode) (dedicated baud rate generator output) (TA = -40 to +85°C, 1.8 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (2/2) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LP (Low-power main) mode LV (low-voltage main) Mode Unit Transfer rate Note 2 Transmission 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V Note 1N ote 1N ote 1N ote 1 bps Theoretical value of the maximum transfer rate C b = 50 pF, Rb = 2.7 k, Vb = 2.3 V 1.2 Note 2 1.2 Note 2 1.2 Note 2 1.2 Note 2 Mbps 1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Notes 3, 4 Notes 3, 4 Notes 3, 4 Notes 3, 4 bps Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 5.5 k, Vb = 1.6 V 0.43 Note 5 0.43 Note 5 0.43 Note 5 0.43 Note 5 Mbps Maximum transfer rate = [bps] Baud rate error (theoretical value) = Transfer rate  2 {-Cb  Rb  In (1 - )} ( )  Number of transferred bits1 Transfer rate  100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 2.0 Vb 2.0 Vb Maximum transfer rate = [bps] Baud rate error (theoretical value) = Transfer rate  2 {-Cb  Rb  In (1 - )} ( )  Number of transferred bits1 Transfer rate  100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 1.5 Vb 1.5 Vb

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 53 of 99 Jan 16, 2015 Note 1. Transfer rate in the SNOOZE mode is 4,800 bps only. Note 2. Use it with VDD  Vb. Note 3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 24 MHz (2.7 V  VDD  3.6 V) 16 MHz (2.4 V  VDD  3.6 V) Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (V DD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For V IH and VIL, see the DC characteristics with TTL input buffer selected. Remark 1. Vb[V]: Communication line voltage Remark 2. q: UART number (q = 0), g: PIM and POM numbers (g = 5) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01) (6) Communication at different potent ial (1.8 V, 2.5 V) (UART mode) (dedicated baud rate generator output) (TA = +85 to +105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. Transfer rate Notes 1, 2 Reception 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V fMCK/12 Note 1 bps Theoretical value of the maximum transfer rate fMCK = fCLK Note 3 2.4 V  VDD  3.3 V, 1.6 V  Vb  2.0 V fMCK/12 Notes 1, 2 bps Theoretical value of the maximum transfer rate fMCK = fCLK Note 3

0.66 Mbps

(1/2)

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 54 of 99 Jan 16, 2015 Note 1. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V  VDD  3.6 V and 2.3 V  Vb  2.7 V Note 2. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer. Note 3. Use it with VDD  Vb. Note 4. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.4 V  VDD < 3.3 V and 1.6 V  Vb  2.0 V Note 5. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 4 above to calculate the maximum transfer rate under conditions of the customer. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (V DD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For V IH and VIL, see the DC characteristics with TTL input buffer selected. (6) Communication at different potential (1.8 V, 2.5V ) (UART mode) (dedicated baud rate generator output) (TA = +85 to +105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (2/2) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. Transfer rate Note 2 Transmission 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V Note 1 bps Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 2.7 k, Vb = 2.3 V

1.2 Note 2 Mbps

2.4 V  VDD  3.3 V, 1.6 V  Vb  2.0 V Notes 3, 4 bps Theoretical value of the maximum transfer rate C b = 50 pF, Rb = 5.5 k, Vb = 1.6 V

0.43 Note 5 Mbps

Maximum transfer rate = [bps] Baud rate error (theoretical value) = Transfer rate  2 {-Cb  Rb  In (1 - )} ( )  Number of transferred bits1 Transfer rate  100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 2.0 Vb 2.0 Vb Maximum transfer rate = [bps] Baud rate error (theoretical value) = Transfer rate  2 {-Cb  Rb  In (1 - )} ( )  Number of transferred bits1 Transfer rate  100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 1.5 Vb 1.5 Vb

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 55 of 99 Jan 16, 2015 UART mode connection diagram (during communication at different potential) UART mode bit width (during communication at different potential) (reference) Remark 1. Rb[]: Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage Remark 2. q: UART number (q = 0), g: PIM and POM number (g = 5) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)) TxDq RxDq User’s device Rx Tx Vb Rb RL78 microcontroller Baud rate error tolerance High-/Low-bit width 1/Transfer rate Baud rate error tolerance High-bit width Low-bit width 1/Transfer rate TxDq RxDq

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 56 of 99 Jan 16, 2015 Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. Note 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (V DD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (P IMg) and port output mode register g (POMg). For V IH and VIL, see the DC characteristics with TTL input buffer selected. Remark 1. Rb[ι]: Communication line (SCKp, SOp) pull-up resistance, C b[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM number (g = 5) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) (7) Communication at differe nt potential (2.5 V) (CSI mode) (maste r mode, SCKp... internal clock output, corresponding CSI00 only) (TA = -40 to +85°C, 2.7 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Parameter Sym bol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LP (Low-power main) mode LV (low-voltage main) Mode Unit SCKp cycle time t KCY1 tKCY1  fCLK/2 2.7 V  VDD  3.6 V, Cb = 20 pF, Rb = 2.7 k 300 1500 1500 1500 ns SCKp high-level width tKH1 2.7 V  VDD  3.6 V, Cb = 20 pF, Rb = 2.7 k tKCY1/2 - 120 tKCY1/2 - 120 tKCY1/2 - 120 tKCY1/2 - 120 ns SCKp low-level width tKL1 2.7 V  VDD  3.6 V, Cb = 20 pF, Rb = 1.4 k tKCY1/2 - 10 tKCY1/2 - 50 tKCY1/2 - 50 tKCY1/2 - 50 ns SIp setup time (to SCKp↑) Note 1 tSIK1 2.7 V  VDD  3.6 V, Cb = 20 pF, Rb = 2.7 k 121 479 479 479 ns SIp hold time (from SCKp↑) Note 1 tKSI1 2.7 V  VDD  3.6 V, Cb = 20 pF, Rb = 2.7 k 10 10 10 10 ns Delay time from SCKp↓ to SOp output Note 1 tKSO1 2.7 V  VDD  3.6 V, Cb = 20 pF, Rb = 2.7 k 130 130 130 130 ns SIp setup time (to SCKp↓) Note 2 tSIK1 2.7 V  VDD  3.6 V, Cb = 20 pF, Rb = 2.7 k 33 110 110 110 ns SIp hold time (from SCKp↓) Note 2 tKSI1 2.7 V  VDD  3.6 V, Cb = 20 pF, Rb = 2.7 k 10 10 10 10 ns Delay time from SCKp↑ to SOp output Note 2 tKSO1 2.7 V  VDD  3.6 V, Cb = 20 pF, Rb = 2.7 k 10 10 10 10 ns

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 57 of 99 Jan 16, 2015 Note Use it with VDD  Vb. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (V DD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (P IMg) and port output mode register g (POMg). For V IH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the page after the next page.) output) (TA = -40 to +85°C, 1.8 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Parameter Sym bol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LP (Low-power main) mode LV (low-voltage main) Mode Unit SCKp cycle time tKCY1 tKCY1  fCLK/4 2.7V  VDD  3.6 V, Cb = 30 pF, Rb = 2.7 k 500 1150 1150 1150 ns 1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note, Cb = 30 pF, Rb = 5.5 k 1150 1150 1150 1150 ns SCKp high- level width tKH1 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k tKCY1/2 - 170 tKCY1/2 - 170 tKCY1/2 - 170 tKCY1/2 - 170 ns 1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note, Cb = 30 pF, Rb = 5.5 k tKCY1/2 - 458 tKCY1/2 - 458 tKCY1/2 - 458 tKCY1/2 - 458 ns SCKp low-level width t KL1 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k tKCY1/2 - 18 tKCY1/2 - 50 tKCY1/2 - 50 tKCY1/2 - 50 ns 1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note, Cb = 30 pF, Rb = 5.5 k tKCY1/2 - 50 tKCY1/2 - 50 tKCY1/2 - 50 tKCY1/2 - 50 ns (1/2)

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 58 of 99 Jan 16, 2015 Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. Note 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 3. Use it with VDD  Vb. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (V DD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (P IMg) and port output mode register g (POMg). For V IH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) output) (TA = -40 to +85°C, 1.8 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (2/2) Parameter Sym bol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LP (Low-power main) mode LV (low-voltage main) Mode Unit SIp setup time (to SCKp↑) Note 1 tSIK1 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k 177 479 479 479 ns 1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 3, Cb = 30 pF, Rb = 5.5 k 479 479 479 479 ns SIp hold time (from SCKp↑) Note 1 tKSI1 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k 19 19 19 19 ns 1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 3, Cb = 30 pF, Rb = 5.5 k 19 19 19 19 ns Delay time from SCKp↓ to SOp output Note 1 tKSO1 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k 195 195 195 195 ns 1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 3, Cb = 30 pF, Rb = 5.5 k 483 483 483 483 ns SIp setup time (to SCKp↓) Note 2 tSIK1 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k 44 110 110 110 ns 1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 3, Cb = 30 pF, Rb = 5.5 k 110 110 110 110 ns SIp hold time (from SCKp↓) Note 2 tKSI1 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k 19 19 19 19 ns 1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 3, Cb = 30 pF, Rb = 5.5 k 19 19 19 19 ns Delay time from SCKp↑ to SOp output Note 2 tKSO1 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k 25 25 25 25 ns 1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 3, Cb = 30 pF, Rb = 5.5 k 25 25 25 25 ns

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 59 of 99 Jan 16, 2015 CSI mode connection diagram (during communication at different potential) Remark 1. Rb[]: Communication line (SCKp, SOp) pull-up resistance, C b[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM numbers (g = 5) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)) SCKp SOp User’s device SCK SI SIp SO <Master> Vb Rb Vb Rb RL78 microcontroller

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 60 of 99 Jan 16, 2015 CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) Remark p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM numbers (g = 5) Input dataSIp SOp tKCY1 tKL1 tKH1 tSIK1 tKSI1 tKSO1 Output data SCKp Input data Output data SIp SOp SCKp tKCY1 tKH1 tKL1 tSIK1 tKSI1 tKSO1

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 61 of 99 Jan 16, 2015 Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (V DD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (P IMg) and port output mode register g (POMg). For V IH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the page after the next page.) output) (TA = +85 to 105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCKp cycle time t KCY1 tKCY1  fCLK/4 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k 1000 ns 2.4 V  VDD  3.3 V, 1.6 V  Vb  2.0 V, Cb = 30 pF, Rb = 5.5 k 2300 ns SCKp high-level width t KH1 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k tKCY1/2 - 340 ns 2.4 V  VDD  3.3 V, 1.6 V  Vb  2.0 V, Cb = 30 pF, Rb = 5.5 k tKCY1/2 - 916 ns SCKp low-level width t KL1 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k tKCY1/2 - 36 ns 2.4 V  VDD  3.3 V, 1.6 V  Vb  2.0 V, Cb = 30 pF, Rb = 5.5 k tKCY1/2 - 100 ns (1/2)

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 62 of 99 Jan 16, 2015 Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. Note 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 3. Use it with VDD  Vb. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (V DD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (P IMg) and port output mode register g (POMg). For V IH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) output) (TA = +85 to 105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (2/2) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SIp setup time (to SCKp↑) Note 1 tSIK1 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k 354 ns 2.4 V  VDD  3.3 V, 1.6 V  Vb  2.0 V Note 3, Cb = 30 pF, Rb = 5.5 k 958 ns SIp hold time (from SCKp↑) Note 1 tKSI1 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k 38 ns 2.4 V  VDD  3.3 V, 1.6 V  Vb  2.0 V Note 3, Cb = 30 pF, Rb = 5.5 k 38 ns Delay time from SCKp↓ to SOp output Note 1 tKSO1 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k 390 ns 2.4 V  VDD  3.3 V, 1.6 V  Vb  2.0 V Note 3, Cb = 30 pF, Rb = 5.5 k 966 ns SIp setup time (to SCKp↓) Note 2 tSIK1 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k 88 ns 2.4 V  VDD  3.3 V, 1.6 V  Vb  2.0 V Note 3, Cb = 30 pF, Rb = 5.5 k 220 ns SIp hold time (from SCKp↓) Note 2 tKSI1 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k 38 ns 2.4 V  VDD  3.3 V, 1.6 V  Vb  2.0 V Note 3, Cb = 30 pF, Rb = 5.5 k 38 ns Delay time from SCKp↑ to SOp output Note 2 tKSO1 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k 50 ns 2.4 V  VDD  3.3 V, 1.6 V  Vb  2.0 V Note 3, Cb = 30 pF, Rb = 5.5 k 50 ns

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 63 of 99 Jan 16, 2015 CSI mode connection diagram (during communication at different potential) Remark 1. Rb[]: Communication line (SCKp, SOp) pull-up resistance, C b[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM numbers (g = 5) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)) SCKp SOp User’s device SCK SI SIp SO <Master> Vb Rb Vb Rb RL78 microcontroller

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 64 of 99 Jan 16, 2015 CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) Remark p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM numbers (g = 5) Input dataSIp SOp tKCY1 tKL1 tKH1 tSIK1 tKSI1 tKSO1 Output data SCKp Input data Output data SIp SOp SCKp tKCY1 tKH1 tKL1 tSIK1 tKSI1 tKSO1

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 65 of 99 Jan 16, 2015 (Notes and Caution are listed on the next page. Remarks are listed on the page after the next page.) (TA = -40 to 85°C, 1.8 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Parameter Symb ol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LP (Low-power main) mode LV (low-voltage main) Mode Unit SCKp cycle time Note 1 tKCY2 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V

20 MHz < fMCK  24 MHz 16/f MCK ——— n s

16 MHz < fMCK  20 MHz 14/f MCK ——— n s

8 MHz < fMCK  16 MHz 12/f MCK ——— n s

4 MHz < fMCK  8 MHz 8/f MCK 16/fMCK —— n s

fMCK  4 MHz 6/fMCK 10/fMCK 10/fMCK 10/fMCK ns 1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 2

20 MHz < fMCK  24 MHz 36/f MCK ——— n s

16 MHz < fMCK  20 MHz 32/f MCK ——— n s

8 MHz < fMCK  16 MHz 26/f MCK ——— n s

4 MHz < fMCK  8 MHz 16/f MCK 16/fMCK —— n s

fMCK  4 MHz 10/fMCK 10/fMCK 10/fMCK 10/fMCK ns SCKp high-/ low-level width t KH2, tKL2 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V tKCY2/2 - 18 tKCY2/2 - 50 tKCY2/2 - 50 tKCY2/2 - ns 1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 2 tKCY2/2 - 50 tKCY2/2 - 50 tKCY2/2 - 50 tKCY2/2 - ns SIp setup time (to SCKp↑) Note 3 tSIK2 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V 1/fMCK + 20 1/fMCK + 30 1/fMCK + 30 1/fMCK + ns 1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 2 1/fMCK + 30 1/fMCK + 30 1/fMCK + 30 1/fMCK + ns SIp hold time (from SCKp↑) Note 4 tKSI2 1/fMCK + 31 1/fMCK + 31 1/fMCK + 31 1/fMCK + ns Delay time from SCKp↓ to SOp output Note 5 tKSO2 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k 2/fMCK + 214 2/fMCK + 573 2/fMCK + 573 2/fMCK + 573 ns 1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 2, Cb = 30 pF, Rb = 5.5 k 2/fMCK + 573 2/fMCK + 573 2/fMCK + 573 2/fMCK + 573 ns

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 66 of 99 Jan 16, 2015 Note 1. Transfer rate in the SNOOZE mode: MAX. 1 Mbps Note 2. Use it with VDD  Vb. Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓ ” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (V DD tolerance) mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.)

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 67 of 99 Jan 16, 2015 CSI mode connection diagram (during communication at different potential) Remark 1. Rb[]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM numbers (g = 5) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)) SCKp SOp User’s device SCK SI SIp SO Vb Rb <Slave> RL78 microcontroller

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 68 of 99 Jan 16, 2015 CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) Remark p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM numbers (g = 5) SIp SOp SCKp Input data Output data tKCY2 tKH2tKL2 tSIK2 tKSI2 tKSO2 Input data Output data SIp SOp SCKp tKCY2 tKL2tKH2 tSIK2 tKSI2 tKSO2

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 69 of 99 Jan 16, 2015 (Notes and Caution are listed on the next page. Remarks are listed on the page after the next page.) (TA = +85 to 105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCKp cycle time Note 1 tKCY2 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V

20 MHz  fMCK  24 MHz 32/f MCK ns

16 MHz  fMCK  20 MHz 28/f MCK ns

8 MHz  fMCK  16 MHz 24/f MCK ns

4 MHz  fMCK  8 MHz 16/f MCK ns

fMCK  4 MHz 12/fMCK ns 2.4 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 2

20 MHz  fMCK  24 MHz 72/f MCK ns

16 MHz  fMCK  20 MHz 64/f MCK ns

8 MHz  fMCK  16 MHz 52/f MCK ns

4 MHz  fMCK  8 MHz 32/f MCK ns

fMCK  4 MHz 20/fMCK ns SCKp high-/low-level width tKH2, tKL2 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V tKCY2/2 - 36 ns 2.4 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 2 tKCY2/2 - 100 ns SIp setup time (to SCKp↑) Note 3 tSIK2 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V 1/fMCK + 40 ns 2.4 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 2 1/fMCK + 60 ns SIp hold time (from SCKp↑) Note 4 tKSI2 1/fMCK + 62 ns Delay time from SCKp↓ to SOp output Note 5 tKSO2 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V Cb = 30 pF, Rb = 2.7 k 2/fMCK + 428 ns 2.4 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 2 Cb = 30 pF, Rb = 5.5 k 2/fMCK + 1146 ns

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 70 of 99 Jan 16, 2015 Note 1. Transfer rate in the SNOOZE mode: MAX. 1 Mbps Note 2. Use it with VDD  Vb. Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (V DD tolerance) mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.)

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 71 of 99 Jan 16, 2015 CSI mode connection diagram (during communication at different potential) Remark 1. Rb[]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM numbers (g = 5) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01)) SCKp SOp User’s device SCK SI SIp SO Vb Rb <Slave> RL78 microcontroller

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 72 of 99 Jan 16, 2015 CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) Remark p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM numbers (g = 5) SIp SOp SCKp Input data Output data tKCY2 tKH2tKL2 tSIK2 tKSI2 tKSO2 Input data Output data SIp SOp SCKp tKCY2 tKL2tKH2 tSIK2 tKSI2 tKSO2

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 73 of 99 Jan 16, 2015 Note 1. The value must also be equal to or less than fMCK/4. Note 2. Use it with VDD  Vb. Note 3. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”. Caution Select the TTL input buffer and the N-ch open drain output (V DD tolerance) mode for the SDAr pin and the N-ch open drain output (V DD tolerance) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) (10) Communication at different potential (1.8 V, 2.5 V) (simplified I2C mode) (TA = -40 to 85°C, 1.8 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Parameter Sym bol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LP (Low-power main) mode LV (low-voltage main) Mode Unit SCLr clock frequency fSCL 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 50 pF, Rb = 2.7 k 1000 Note 1 300 Note 1 250 Note 1 300 Note 1 kHz 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 100 pF, Rb = 2.7 k 400 Note 1 300 Note 1 250 Note 1 300 Note 1 kHz 1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k 300 Note 1 300 Note 1 250 Note 1 300 Note 1 kHz Hold time when SCLr = “L” t LOW 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 50 pF, Rb = 2.7 k 475 1550 1550 1550 ns 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 100 pF, Rb = 2.7 k 1150 1550 1550 1550 ns 1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k 1550 1550 1550 1550 ns Hold time when SCLr = “H” tHIGH 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 50 pF, Rb = 2.7 k 200 610 610 610 ns 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 100 pF, Rb = 2.7 k 600 610 610 610 ns 1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k 610 610 610 610 ns Data setup time (reception) t SU: DAT 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 50 pF, Rb = 2.7 k 1/fMCK + 135 Note 3 1/fMCK + 190 Note 2 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 ns 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 100 pF, Rb = 2.7 k 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 ns 1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 ns Data hold time (transmission) tHD: DAT 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 50 pF, Rb = 2.7 k 03 0 503 0 503 0 503 0 5 n s 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 100 pF, Rb = 2.7 k 03 5 503 5 503 5 503 5 5 n s 1.8 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k 04 0 504 0 504 0 504 0 5 n s

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 74 of 99 Jan 16, 2015 Simplified I2C mode connection diagram (during communication at different potential) Simplified I2C mode serial transfer timing (during communication at different potential) Remark 1. Rb[]: Communication line (SDAr, SCLr) pull-up resistance, C b[F]: Communication line (SDAr, SCLr) load capacitance, Vb[V]: Communication line voltage Remark 2. r: IIC number (r = 00, 01), g: PIM, POM number (g = 5) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0), n: Channel number (n = 0, 1), mn = 00, 01) SDAr SCLr User’s device SDA SCL Vb Rb Vb Rb RL78 microcontroller SDAr SCLr 1/fSCL tLOW tHIGH tSU: DATtHD: DAT

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 75 of 99 Jan 16, 2015 Note 1. The value must also be equal to or less than fMCK/4. Note 2. Use it with VDD  Vb. Note 3. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”. Caution Select the TTL input buffer and the N-ch open drain output (V DD tolerance) mode for the SDAr pin and the N-ch open drain output (V DD tolerance) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) (10) Communication at different potential (1.8 V, 2.5 V) (simplified I2C mode) (TA = +85 to 105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCLr clock frequency f SCL 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 50 pF, Rb = 2.7 k 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 100 pF, Rb = 2.7 k 2.4 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k Hold time when SCLr = “L” t LOW 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 50 pF, Rb = 2.7 k 1200 ns 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 100 pF, Rb = 2.7 k 4600 ns 2.4 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k 4650 ns Hold time when SCLr = “H” t HIGH 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 50 pF, Rb = 2.7 k 500 ns 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 100 pF, Rb = 2.7 k 2400 ns 2.4 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k 1830 ns Data setup time (reception) t SU:DAT 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 50 pF, Rb = 2.7 k 1/fMCK + 340 Note 3 ns 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 100 pF, Rb = 2.7 k 1/fMCK + 760 Note 3 ns 2.4 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k 1/fMCK + 570 Note 3 ns Data hold time (transmission) tHD:DAT 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 50 pF, Rb = 2.7 k 0 770 ns 2.7 V  VDD  3.6 V, 2.3 V  Vb  2.7 V, Cb = 100 pF, Rb = 2.7 k 0 1420 ns 2.4 V  VDD < 3.3 V, 1.6 V  Vb  2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k 0 1215 ns

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 76 of 99 Jan 16, 2015 Simplified I2C mode connection diagram (during communication at different potential) Simplified I2C mode serial transfer timing (during communication at different potential) Remark 1. Rb[]: Communication line (SDAr, SCLr) pull-up resistance, C b[F]: Communication line (SDAr, SCLr) load capacitance, Vb[V]: Communication line voltage Remark 2. r: IIC number (r = 00, 01), g: PIM and POM numbers (g = 5) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0), n: Channel number (n = 0, 1), mn = 00, 01) SDAr SCLr User’s device SDA SCL Vb Rb Vb Rb RL78 microcontroller SDAr SCLr 1/fSCL tLOW tHIGH tSU: DATtHD: DAT

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 77 of 99 Jan 16, 2015

2.6 Analog Characteristics

2.6.1 A/D converte r characteristics

Classification of A/D converter characteristics Reference Voltage Input Channel Reference voltage (+) = AVREFP Reference voltage (-) = AVREFM Reference voltage (+) = AVDD Reference voltage (-) = AVSS Reference voltage (+) = Internal reference voltage Reference voltage (-) = AVSS High-accuracy channel; ANI0 to ANI13 (input buffer power supply: AVDD) Refer to 2.6.1 (1). Refer to 2.6.1 (7). Refer to 2.6.1 (2). Refer to 2.6.1 (7). Refer to 2.6.1 (5). Refer to 2.6.1 (10). Standard channel; ANI16 to ANI18 (input buffer power supply: VDD) Refer to 2.6.1 (3). Refer to 2.6.1 (8). Refer to 2.6.1 (4). Refer to 2.6.1 (9). Internal reference voltage, Temperature sensor output voltage Refer to 2.6.1 (3). Refer to 2.6.1 (8). Refer to 2.6.1 (4). Refer to 2.6.1 (9).

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 78 of 99 Jan 16, 2015 Note 1. Cannot be used for lower 2 bit of ADCR register Note 2. Cannot be used for lower 4 bit of ADCR register Note 3. Excludes quantization error (1/2 LSB). Caution Always use AV DD pin with the same potential as the VDD pin. (1) When reference voltage (+) = AV REFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), conversion target: ANI2 to ANI13 (TA = -40 to +85°C, 1.6 V  AVREFP  AVDD = VDD  3.6 V, VSS = 0 V, AVSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 2.4 V  AVREFP  AVDD  3.6 V 8 12 bit 1.8 V  AVREFP  AVDD  3.6 V 8 10 Note 1 1.6 V  AVREFP  AVDD  3.6 V 8 Note 2 Overall error Note 3 AINL 12-bit resolution 2.4 V  AVREFP  AVDD  3.6 V 6.0 LSB 10-bit resolution 1.8 V  AVREFP  AVDD  3.6 V 5.0 8-bit resolution 1.6 V  AVREFP  AVDD  3.6 V 2.5 Conversion time t CONV ADTYP = 0, 12-bit resolution 2.4 V  AVREFP  AVDD  3.6 V 3.375 s ADTYP = 0, 10-bit resolution Note 1 1.8 V  AVREFP  AVDD  3.6 V 6.75 ADTYP = 0, 8-bit resolution Note 2 1.6 V  AVREFP  AVDD  3.6 V 13.5 ADTYP = 1, 8-bit resolution 2.4 V  AVREFP  AVDD  3.6 V 2.5625 1.8 V  AVREFP  AVDD  3.6 V 5.125 1.6 V  AVREFP  AVDD  3.6 V 10.25 Zero-scale error Note 3 EZS 12-bit resolution 2.4 V  AVREFP  AVDD  3.6 V 4.5 LSB 10-bit resolution 1.8 V  AVREFP  AVDD  3.6 V 4.5 8-bit resolution 1.6 V  AVREFP  AVDD  3.6 V 2.0 Full-scale error Note 3 EFS 12-bit resolution 2.4 V  AVREFP  AVDD  3.6 V 4.5 LSB 10-bit resolution 1.8 V  AVREFP  AVDD  3.6 V 4.5 8-bit resolution 1.6 V  AVREFP  AVDD  3.6 V 2.0 Integral linearity error Note 3 ILE 12-bit resolution 2.4 V  AVREFP  AVDD  3.6 V 2.0 LSB 10-bit resolution 1.8 V  AVREFP  AVDD  3.6 V 1.5 8-bit resolution 1.6 V  AVREFP  AVDD  3.6 V 1.0 Differential linearity error Note 3 DLE 12-bit resolution 2.4 V  AVREFP  AVDD  3.6 V 1.5 LSB 10-bit resolution 1.8 V  AVREFP  AVDD  3.6 V 1.5 8-bit resolution 1.6 V  AVREFP  AVDD  3.6 V 1.0 Analog input voltage V AIN 0A VREFP V

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 79 of 99 Jan 16, 2015 Note 1. Cannot be used for lower 2 bit of ADCR register Note 2. Cannot be used for lower 4 bit of ADCR register Note 3. Excludes quantization error (1/2 LSB). Caution Always use AV DD pin with the same potential as the VDD pin. (2) When reference voltage (+) = AV DD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (-) = AVSS (ADREFM = 0), conversion target: ANI0 to ANI13 (TA = -40 to +85°C, 1.6 V  AVDD = VDD  3.6 V, VSS = 0 V, AVSS = 0 V, Reference voltage (+) = AVDD, Reference voltage (-) = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP . MAX. Unit Resolution RES 2.4 V  AVDD  3.6 V 8 12 bit 1.8 V  AVDD  3.6 V 8 10 Note 1 1.6 V  AVDD  3.6 V 8 Note 2 Overall error Note 3 AINL 12-bit resolution 2.4 V  AVDD  3.6 V 7.5 LSB 10-bit resolution 1.8 V  AVDD  3.6 V 5.5 8-bit resolution 1.6 V  AVDD  3.6 V 3.0 Conversion time t CONV ADTYP = 0, 12-bit resolution 2.4 V  AVDD  3.6 V 3.375 s ADTYP = 0, 10-bit resolution Note 1 1.8 V  AVDD  3.6 V 6.75 ADTYP = 0, 8-bit resolution Note 2 1.6 V  AVDD  3.6 V 13.5 ADTYP = 1, 8-bit resolution 2.4 V  AVDD  3.6 V 2.5625 1.8 V  AVDD  3.6 V 5.125 1.6 V  AVDD  3.6 V 10.25 Zero-scale error Note 3 EZS 12-bit resolution 2.4 V  AVDD  3.6 V 6.0 LSB 10-bit resolution 1.8 V  AVDD  3.6 V 5.0 8-bit resolution 1.6 V  AVDD  3.6 V 2.5 Full-scale error Note 3 EFS 12-bit resolution 2.4 V  AVDD  3.6 V 6.0 LSB 10-bit resolution 1.8 V  AVDD  3.6 V 5.0 8-bit resolution 1.6 V  AVDD  3.6 V 2.5 Integral linearity error Note 3 ILE 12-bit resolution 2.4 V  AVDD  3.6 V 3.0 LSB 10-bit resolution 1.8 V  AVDD  3.6 V 2.0 8-bit resolution 1.6 V  AVDD  3.6 V 1.5 Differential linearity error Note 3 DLE 12-bit resolution 2.4 V  AVDD  3.6 V 2.0 LSB 10-bit resolution 1.8 V  AVDD  3.6 V 2.0 8-bit resolution 1.6 V  AVDD  3.6 V 1.5 Analog input voltage V AIN ANI0 to ANI6 0 AVDD V

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 80 of 99 Jan 16, 2015 Note 1. Cannot be used for lower 2 bits of ADCR register Note 2. Cannot be used for lower 4 bits of ADCR register Note 3. Excludes quantization error (1/2 LSB). Note 4. Refer to 2.6.2 Temperature sensor, internal reference voltage output characteristics. Caution Always use AV DD pin with the same potential as the VDD pin. (3) When reference voltage (+) = AV REFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), conversion target: ANI16 to AN I18, internal reference voltage, temperature sensor output voltage (TA = -40 to +85°C, 1.6 V  VDD  3.6 V, 1.6 V  AVREFP  AVDD = VDD  3.6 V, VSS = 0 V, AVSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM = 0 V) Parameter Symbol Conditions MIN. TYP . MAX. Unit Resolution RES 2.4 V  AVREFP  AVDD  3.6 V 8 12 bit 1.8 V  AVREFP  AVDD  3.6 V 8 10 Note 1 1.6 V  AVREFP  AVDD  3.6 V 8 Note 2 Overall error Note 3 AINL 12-bit resolution 2.4 V  AVREFP  AVDD  3.6 V 7.0 LSB 10-bit resolution 1.8 V  AVREFP  AVDD  3.6 V 5.5 8-bit resolution 1.6 V  AVREFP  AVDD  3.6 V 3.0 Conversion time t CONV ADTYP = 0, 12-bit resolution 2.4 V  AVREFP  AVDD  3.6 V 4.125 s ADTYP = 0, 10-bit resolution Note 1 1.8 V  AVREFP  AVDD  3.6 V 9.5 ADTYP = 0, 8-bit resolution Note 2 1.6 V  AVREFP  AVDD  3.6 V 57.5 ADTYP = 1, 8-bit resolution 2.4 V  AVREFP  AVDD  3.6 V 3.3125 1.8 V  AVREFP  AVDD  3.6 V 7.875 1.6 V  AVREFP  AVDD  3.6 V 54.25 Zero-scale error Note 3 EZS 12-bit resolution 2.4 V  AVREFP  AVDD  3.6 V 5.0 LSB 10-bit resolution 1.8 V  AVREFP  AVDD  3.6 V 5.0 8-bit resolution 1.6 V  AVREFP  AVDD  3.6 V 2.5 Full-scale error Note 3 EFS 12-bit resolution 2.4 V  AVREFP  AVDD  3.6 V 5.0 LSB 10-bit resolution 1.8 V  AVREFP  AVDD  3.6 V 5.0 8-bit resolution 1.6 V  AVREFP  AVDD  3.6 V 2.5 Integral linearity error Note 3 ILE 12-bit resolution 2.4 V  AVREFP  AVDD  3.6 V 3.0 LSB 10-bit resolution 1.8 V  AVREFP  AVDD  3.6 V 2.0 8-bit resolution 1.6 V  AVREFP  AVDD  3.6 V 1.5 Differential linearity error Note 3 DLE 12-bit resolution 2.4 V  AVREFP  AVDD  3.6 V 2.0 LSB 10-bit resolution 1.8 V  AVREFP  AVDD  3.6 V 2.0 8-bit resolution 1.6 V  AVREFP  AVDD  3.6 V 1.5 Analog input voltage V AIN 0A VREFP V Internal reference voltage (1.8 V  VDD  3.6 V) VBGR Note 4 Temperature sensor output voltage (1.8 V  VDD  3.6 V) VTMP25 Note 4

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 81 of 99 Jan 16, 2015 Note 1. Cannot be used for lower 2 bits of ADCR register Note 2. Cannot be used for lower 4 bits of ADCR register Note 3. Excludes quantization error (1/2 LSB). Note 4. Refer to 2.6.2 Temperature sensor, internal reference voltage output characteristics. Caution Always use AV DD pin with the same potential as the VDD pin. (4) When reference voltage (+) = AV DD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (-) = AVSS (ADREFM = 0), conversion target: ANI16 to ANI18, internal reference voltage, temperature sensor output voltage (TA = -40 to +85°C, 1.6 V  AVDD = VDD  3.6 V, VSS = 0 V, AVSS = 0 V, Reference voltage (+) = AVDD, Reference voltage (-) = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP . MAX. Unit Resolution RES 2.4 V  AVDD  3.6 V 8 12 bit 1.8 V  AVDD  3.6 V 8 10 Note 1 1.6 V  AVDD  3.6 V 8 Note 2 Overall error Note 3 AINL 12-bit resolution 2.4 V  AVDD  3.6 V 8.5 LSB 10-bit resolution 1.8 V  AVDD  3.6 V 6.0 8-bit resolution 1.6 V  AVDD  3.6 V 3.5 Conversion time t CONV ADTYP = 0, 12-bit resolution 2.4 V  AVDD  3.6 V 4.125 s ADTYP = 0, 10-bit resolution Note 1 1.8 V  AVDD  3.6 V 9.5 ADTYP = 0, 8-bit resolution Note 2 1.6 V  AVDD  3.6 V 57.5 ADTYP = 1, 8-bit resolution 2.4 V  AVDD  3.6 V 3.3125 1.8 V  AVDD  3.6 V 7.875 1.6 V  AVDD  3.6 V 54.25 Zero-scale error Note 3 EZS 12-bit resolution 2.4 V  AVDD  3.6 V 8.0 LSB 10-bit resolution 1.8 V  AVDD  3.6 V 5.5 8-bit resolution 1.6 V  AVDD  3.6 V 3.0 Full-scale error Note 3 EFS 12-bit resolution 2.4 V  AVDD  3.6 V 8.0 LSB 10-bit resolution 1.8 V  AVDD  3.6 V 5.5 8-bit resolution 1.6 V  AVDD  3.6 V 3.0 Integral linearity error Note 3 ILE 12-bit resolution 2.4 V  AVDD  3.6 V 3.5 LSB 10-bit resolution 1.8 V  AVDD  3.6 V 2.5 8-bit resolution 1.6 V  AVDD  3.6 V 1.5 Differential linearity error Note 3 DLE 12-bit resolution 2.4 V  AVDD  3.6 V 2.5 LSB 10-bit resolution 1.8 V  AVDD  3.6 V 2.5 8-bit resolution 1.6 V  AVDD  3.6 V 2.0 Analog input voltage V AIN 0A VDD V Internal reference voltage (1.8 V  VDD  3.6 V) VBGR Note 4 Temperature sensor output voltage (1.8 V  VDD  3.6 V) VTMP25 Note 4

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 82 of 99 Jan 16, 2015 Note Excludes quantization error (±1/2 LSB). Caution Always use AV DD pin with the same potential as the VDD pin. Note Excludes quantization error (1/2 LSB). Caution Always use AV DD pin with the same potential as the VDD pin. (5) When reference voltage (+) = Internal reference vo ltage (1.45 V) (ADREFP1 = 1, ADREFP0 = 0), reference voltage (-) = AVSS (ADREFM = 0), conversion target: ANI0 to ANI13, ANI16 to ANI18 (TA = -40 to +85°C, 1.8 V  AVDD = VDD  3.6 V, VSS = 0 V, AVSS = 0 V, Reference voltage (+) = internal reference voltage, Reference voltage (-) = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 8b it Conversion time tCONV 8-bit resolution 16 s Zero-scale error Note EZS 8-bit resolution 4.0 LSB Integral linearity error Note ILE 8-bit resolution 2.0 LSB Differential linearity error Note DLE 8-bit resolution 2.5 LSB Analog input voltage V AIN 0V BGR V (6) When reference voltage (+) = AV REFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), conversion target: ANI2 to ANI13 (TA = +85 to +105°C, 2.4 V  AVREFP  AVDD = VDD  3.6 V, VSS = 0 V, AVSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM = 0 V) Parameter Symbol Conditions MIN. TYP . MAX. Unit Resolution RES 2.4 V  AVREFP  AVDD  3.6 V 8 12 bit Overall error Note AINL 12-bit resolution 2.4 V  AVREFP  AVDD  3.6 V 6.0 LSB Conversion time t CONV ADTYP = 0, 12-bit resolution 2.4 V  AVREFP  AVDD  3.6 V 3.375 s Zero-scale error Note EZS 12-bit resolution 2.4 V  AVREFP  AVDD  3.6 V 4.5 LSB Full-scale error Note EFS 12-bit resolution 2.4 V  AVREFP  AVDD  3.6 V 4.5 LSB Integral linearity error Note ILE 12-bit resolution 2.4 V  AVREFP  AVDD  3.6 V 2.0 LSB Differential linearity error Note DLE 12-bit resolution 2.4 V  AVREFP  AVDD  3.6 V 1.5 LSB Analog input voltage V AIN 0A VREFP V

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 83 of 99 Jan 16, 2015 Note Excludes quantization error (1/2 LSB). Caution Always use AV DD pin with the same potential as the VDD pin. (7) When reference voltage (+) = AV DD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (-) = AVSS (ADREFM = 0), conversion target: ANI0 to ANI13 (TA = +85 to +105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = 0 V, AVSS = 0 V, Reference voltage (+) = AVDD, Reference voltage (-) = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP . MAX. Unit Resolution RES 2.4 V  AVDD  3.6 V 8 12 bit Overall error Note AINL 12-bit resolution 2.4 V  AVDD  3.6 V 7.5 LSB Conversion time t CONV ADTYP = 0, 12-bit resolution 2.4 V  AVDD  3.6 V 3.375 s Zero-scale error Note EZS 12-bit resolution 2.4 V  AVDD  3.6 V 6.0 LSB Full-scale error Note EFS 12-bit resolution 2.4 V  AVDD  3.6 V 6.0 LSB Integral linearity error Note ILE 12-bit resolution 2.4 V  AVDD  3.6 V 3.0 LSB Differential linearity error Note DLE 12-bit resolution 2.4 V  AVDD  3.6 V 2.0 LSB Analog input voltage V AIN 0A VDD V

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 84 of 99 Jan 16, 2015 Note 1. Excludes quantization error (1/2 LSB). Note 2. Refer to 2.6.2 Temperature sensor, internal reference voltage output characteristics. Caution Always use AV DD pin with the same potential as the VDD pin. (8) When reference voltage (+) = AV REFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), conversion target ANI16 to ANI18, internal reference voltage, temperature sensor output voltage (TA = +85 to +105°C, 2.4 V  AVREFP  AVDD = VDD  3.6 V, VSS = 0 V, AVSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 2.4 V  AVREFP  AVDD  3.6 V 8 12 bit Overall error Note 1 AINL 12-bit resolution 2.4 V  AVREFP  AVDD  3.6 V 7.0 LSB Conversion time t CONV ADTYP = 0, 12-bit resolution 2.4 V  AVREFP  AVDD  3.6 V 4.125 s Zero-scale error Note 1 EZS 12-bit resolution 2.4 V  AVREFP  AVDD  3.6 V 5.0 LSB Full-scale error Note 1 EFS 12-bit resolution 2.4 V  AVREFP  AVDD  3.6 V 5.0 LSB Integral linearity error Note 1 ILE 12-bit resolution 2.4 V  AVREFP  AVDD  3.6 V 3.0 LSB Differential linearity error Note 1 DLE 12-bit resolution 2.4 V  AVREFP  AVDD  3.6 V 2.0 LSB Analog input voltage V AIN 0A VREFP V Internal reference voltage (2.4 V  VDD  3.6 V) VBGR Note 2 Temperature sensor output voltage (2.4 V  VDD  3.6 V) VTMP25 Note 2

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 85 of 99 Jan 16, 2015 Note 1. Excludes quantization error (1/2 LSB). Note 2. Refer to 2.6.2 Temperature sensor, internal reference voltage output characteristics. Caution Always use AV DD pin with the same potential as the VDD pin. (9) When reference voltage (+) = AV DD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (-) = AVSS (ADREFM = 0), conversion target: ANI16 to ANI18, internal reference voltage, temperature sensor output voltage (TA = +85 to +105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = 0 V, AVSS = 0 V, Reference voltage (+) = AVDD, Reference voltage (-) = AVSS = 0) Parameter Symbol Conditions MIN. TYP . MAX. Unit Resolution RES 2.4 V  AVDD  3.6 V 8 12 bit Overall error Note 1 AINL 12-bit resolution 2.4 V  AVDD  3.6 V 8.5 LSB Conversion time t CONV ADTYP = 0, 12-bit resolution 2.4 V  AVDD  3.6 V 4.125 s Zero-scale error Note 1 EZS 12-bit resolution 2.4 V  AVDD  3.6 V 8.0 LSB Full-scale error Note 1 EFS 12-bit resolution 2.4 V  AVDD  3.6 V 8.0 LSB Integral linearity error Note 1 ILE 12-bit resolution 2.4 V  AVDD  3.6 V 3.5 LSB Differential linearity error Note 1 DLE 12-bit resolution 2.4 V  AVDD  3.6 V 2.5 LSB Analog input voltage V AIN 0A VDD V Internal reference voltage (2.4 V  VDD  3.6 V) VBGR Note 2 Temperature sensor output voltage (2.4 V  VDD  3.6 V) VTMP25 Note 2

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 86 of 99 Jan 16, 2015 Note Excludes quantization error (±1/2 LSB). Caution Always use AV DD pin with the same potential as the VDD pin.

2.6.2 Temperature sensor, internal re ference voltage output characteristics

(10) When reference voltage (+) = Internal reference vo ltage (1.45 V) (ADREFP1 = 1, ADREFP0 = 0), reference voltage (-) = AVSS (ADREFM = 0), conversion target: ANI0 to ANI13, ANI16 to ANI18 (TA = +85 to +105°C, 2.4 V  VDD, 2.4 V  AVDD = VDD  3.6 V, VSS = 0 V, AVSS = 0 V, Reference voltage (+) = internal reference voltage, Reference voltage (-) = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 8b it Conversion time tCONV 8-bit resolution 16.0 s Zero-scale error Note EZS 8-bit resolution 4.0 LSB Integral linearity error Note ILE 8-bit resolution 2.0 LSB Differential linearity error Note DLE 8-bit resolution 2.5 LSB Analog input voltage V AIN 0V BGR V (TA = -40 to 85°C, 1.8 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (TA = +85 to 105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP . MAX. Unit Temperature sensor output voltage V TMPS25 Setting ADS register = 80H, TA = +25C1 .05 V Internal reference voltage V BGR Setting ADS register = 81H 1.38 1.45 1.50 V Temperature coefficient FVTMPS Temperature sensor output voltage that depends on the temperature -3.6 mV/°C Operation stabilization wait time t AMP 2.4 V  VDD  3.6 V 5 s 1.8 V  VDD < 2.4 V 10

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 87 of 99 Jan 16, 2015

2.6.3 Comparator

Note In window mode, make sure that Vref1 - Vref0  0.2 V. (TA = -40 to +85°C, 1.6 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input voltage range Ivref0 IVREF0 pin 0 VDD - 1.4 Note V Ivref1 IVREF1 pin 1.4 Note VDD V Ivcmp IVCMP0, IVCMP1 pins -0.3 V DD + 0.3 V Output delay td AV DD = 3.0 V Input slew rate > 50 mV/s Comparator high-speed mode, standard mode 1.2 s Comparator high-speed mode, window mode 2.0 Comparator low-speed mode, standard mode 3.0 s Comparator low-speed mode, window mode 4 s Operation stabilization wait time t CMP 100 s

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 88 of 99 Jan 16, 2015

2.6.4 Operational ampl ifier characteristics

Note When the operational amplifier reference current circuit is activated in advance. (TA = -40 to +85°C, 1.8 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Common mode input range Vicm1 Low-power consumption mode 0.2 AV DD - 0.5 V Vicm2 High-speed mode 0.3 AV DD - 0.6 V Output voltage range Vo1 Low-power consumption mode 0.1 AV DD - 0.1 V Vo2 High-speed mode 0.1 AV DD - 0.1 V Input offset voltage Vioff -10 10 mV Open gain Av 60 120 dB Gain-bandwidth (GB) product GBW1 Low-power consumption mode 0.04 MHz GBW2 High-speed mode 1.7 MHz Phase margin PM CL = 20 pF 50 deg Gain margin GM CL = 20 pF 10 dB Equivalent input noise Vnoise1 f = 1 kHz Low-power consumption mode 230 nV/ √Hz Vnoise2 f = 10 kHz 200 nV/ √Hz Vnoise3 f = 1 kHz High-speed mode 90 nV/ √Hz Vnoise4 f = 2 kHz 70 nV/√ Hz Power supply reduction ratio PSRR 90 dB Common mode signal reduction ratio CMRR 90 dB Operation stabilization wait time Tstd1 CL = 20 pF Only operational amplifier is activated Note Low-power consumption mode 650 s Tstd2 High-speed mode 13 s Tstd3 CL = 20 pF Operational amplifier and reference current circuit are activated simultaneously Low-power consumption mode 650 Tstd4 High-speed mode 13 s Settling time Tset1 CL = 20 pF Low-power consumption mode 750 s Tset2 High-speed mode 13 s Slew rate Tslew1 CL = 20 pF Low-power consumption mode

0.02 V/ s

Tslew2 High-speed mode 1.1 V/ s Load current Iload1 Low-power consumption mode -100 100 A Iload2 High-speed mode -100 100 A Load capacitance CL 20 pF

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 89 of 99 Jan 16, 2015

2.6.5 POR circuit characteristics

Note 1. However, when the operating voltage falls while the LVD is off, enter STOP mode, or enable the reset status using the external reset pin before the voltage falls below the operating voltage range shown in 2.4 AC Characteristics. Note 2. Minimum time required for a POR reset when V DD exceeds below V PDR. This is also the minimum time required for a POR reset from when V DD exceeds below 0.7 V to when V DD exceeds VPOR while STOP mode is entered or the main system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register (CSC). (TA = -40 to +105°C, VSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP . MAX. Unit Detection voltage VPOR Power supply rise time T A = -40 to +85°C 1.47 1.51 1.55 V TA = +85 to +105°C 1.45 1.51 1.57 V VPDR Power supply fall time Note 1 TA = -40 to +85°C 1.46 1.50 1.54 V TA = +85 to +105°C 1.44 1.50 1.56 V Minimum pulse width Note 2 TPW1 Other than STOP/SUB HALT/SUB RUN T A = +40 to +105°C 300 s TPW2 STOP/SUB HALT/SUB RUN T A = +40 to +105°C 300 s VDD VPDR 0.7 V VPOR TPW2 TPW1

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 90 of 99 Jan 16, 2015

2.6.6 LVD circuit characteristics

(1) LVD Detection Voltage of Reset Mode and Interrupt Mode (TA = -40 to +85°C, VPDR  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage Supply voltage level V LVD2 Power supply rise time 3.07 3.13 3.19 V Power supply fall time 3.00 3.06 3.12 V VLVD3 Power supply rise time 2.96 3.02 3.08 V Power supply fall time 2.90 2.96 3.02 V VLVD4 Power supply rise time 2.86 2.92 2.97 V Power supply fall time 2.80 2.86 2.91 V VLVD5 Power supply rise time 2.76 2.81 2.87 V Power supply fall time 2.70 2.75 2.81 V VLVD6 Power supply rise time 2.66 2.71 2.76 V Power supply fall time 2.60 2.65 2.70 V VLVD7 Power supply rise time 2.56 2.61 2.66 V Power supply fall time 2.50 2.55 2.60 V VLVD8 Power supply rise time 2.45 2.50 2.55 V Power supply fall time 2.40 2.45 2.50 V VLVD9 Power supply rise time 2.05 2.09 2.13 V Power supply fall time 2.00 2.04 2.08 V VLVD10 Power supply rise time 1.94 1.98 2.02 V Power supply fall time 1.90 1.94 1.98 V VLVD11 Power supply rise time 1.84 1.88 1.91 V Power supply fall time 1.80 1.84 1.87 V VLVD12 Power supply rise time 1.74 1.77 1.81 V Power supply fall time 1.70 1.73 1.77 V VLVD13 Power supply rise time 1.64 1.67 1.70 V Power supply fall time 1.60 1.63 1.66 V Minimum pulse width tLW 300 s Detection delay time 300 s (TA = +85 to +105°C, VPDR  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage Supply voltage level V LVD2 Power supply rise time 3.01 3.13 3.25 V Power supply fall time 2.94 3.06 3.18 V VLVD3 Power supply rise time 2.90 3.02 3.14 V Power supply fall time 2.85 2.96 3.07 V VLVD4 Power supply rise time 2.81 2.92 3.03 V Power supply fall time 2.75 2.86 2.97 V VLVD5 Power supply rise time 2.71 2.81 2.92 V Power supply fall time 2.64 2.75 2.86 V VLVD6 Power supply rise time 2.61 2.71 2.81 V Power supply fall time 2.55 2.65 2.75 V VLVD7 Power supply rise time 2.51 2.61 2.71 V Power supply fall time 2.45 2.55 2.65 V Minimum pulse width tLW 300 s Detection delay time 300 s

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 91 of 99 Jan 16, 2015

2.6.7 Power supply voltage rising slope characteristics

Caution Make sure to keep the internal reset state by the LVD circuit or an external reset until V DD reaches the operating voltage range shown in 2.4 AC Characteristics. (2) LVD Detection Voltage of Interrupt & Reset Mode (TA = -40 to +85°C, VPDR  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Interrupt and reset mode VLVDA0 VPOC0, VPOC1, VPOC2 = 0, 0, 0, falling reset voltage 1.60 1.63 1.66 V VLVDA1 LVIS0, LVIS1 = 1, 0 Rising release reset voltage 1.74 1.77 1.81 V Falling interrupt voltage 1.70 1.73 1.77 V VLVDA2 LVIS0, LVIS1 = 0, 1 Rising release reset voltage 1.84 1.88 1.91 V Falling interrupt voltage 1.80 1.84 1.87 V VLVDA3 LVIS0, LVIS1 = 0, 0 Rising release reset voltage 2.86 2.92 2.97 V Falling interrupt voltage 2.80 2.86 2.91 V VLVDB0 VPOC0, VPOC1, VPOC2 = 0, 0, 1, falling reset voltage 1.80 1.84 1.87 V VLVDB1 LVIS0, LVIS1 = 1, 0 Rising release reset voltage 1.94 1.98 2.02 V Falling interrupt voltage 1.90 1.94 1.98 V VLVDB2 LVIS0, LVIS1 = 0, 1 Rising release reset voltage 2.05 2.09 2.13 V Falling interrupt voltage 2.00 2.04 2.08 V VLVDB3 LVIS0, LVIS1 = 0, 0 Rising release reset voltage 3.07 3.13 3.19 V Falling interrupt voltage 3.00 3.06 3.12 V VLVDC0 VPOC0, VPOC1, VPOC2 = 0, 1, 0, falling reset voltage 2.40 2.45 2.50 V VLVDC1 LVIS0, LVIS1 = 1, 0 Rising release reset voltage 2.56 2.61 2.66 V Falling interrupt voltage 2.50 2.55 2.60 V VLVDC2 LVIS0, LVIS1 = 0, 1 Rising release reset voltage 2.66 2.71 2.76 V Falling interrupt voltage 2.60 2.65 2.70 V VLVDD0 VPOC0, VPOC1, VPOC2 = 0, 1, 1, falling reset voltage 2.70 2.75 2.81 V VLVDD1 LVIS0, LVIS1 = 1, 0 Rising release reset voltage 2.86 2.92 2.97 V Falling interrupt voltage 2.80 2.86 2.91 V VLVDD2 LVIS0, LVIS1 = 0, 1 Rising release reset voltage 2.96 3.02 3.08 V Falling interrupt voltage 2.90 2.96 3.02 V (TA = +85 to +105°C, VPDR  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Interrupt and reset mode V LVDD0 VPOC0, VPOC1, VPOC2 = 0, 1, 1, falling reset voltage 2.64 2.75 2.86 V VLVDD1 LVIS0, LVIS1 = 1, 0 Rising release reset voltage 2.81 2.92 3.03 V Falling interrupt voltage 2.75 2.86 2.97 V VLVDD2 LVIS0, LVIS1 = 0, 1 Rising release reset voltage 2.90 3.02 3.14 V Falling interrupt voltage 2.85 2.96 3.07 V (TA = -40 to +105°C, VSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Power supply voltage rising slope SVDD 54 V/ms

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 92 of 99 Jan 16, 2015

2.7 RAM Data Retention Characteristics

Note The value depends on the POR detection voltage. When the vo ltage drops, the data is retained before a POR reset is effected, but data is not retained when a POR reset is effected.

2.8 Flash Memory Programming Characteristics

Note 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. Note 2. When using flash memory programmer and Renesas Electronics self-programming library Note 3. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation. (TA = -40 to +85°C, 1.8 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention supply voltage V DDDR TA = -40 to +85°C 1.46 Note 3.6 V TA = +85 to +105°C 1.44 Note 3.6 V (TA = -40 to +85°C, 1.8 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP . MAX. Unit System clock frequency fCLK 12 4 MHz Number of code flash rewrites Notes 1, 2, 3 Cerwr Retained for 20 years T A = 85°C 1,000 Times Number of data flash rewrites Notes 1, 2, 3 Retained for 1 year T A = 25°C 1,000,000 Retained for 5 years T A = 85°C 100,000 Retained for 20 years T A = 85°C 10,000 VDD STOP instruction execution Standby release signal (interrupt request) STOP mode RAM data retention Operation mode VDDDR

RL78/I1D 2. ELECTRICAL SPECIFICATIONS R01DS0244EJ0200 Rev. 2.00 Page 93 of 99 Jan 16, 2015

2.9 Dedicated Flash Memory Programmer Communication (UART)

2.10 Timing of Entry to Flash Memory Programming Modes

Note 1. Deassertion of the POR and LVD reset signals must precede deassertion of the pin reset signal. Note 2. This excludes the flash firmware processing time (723 µs). <1> The low level is input to the TOOL0 pin. <2> The external reset ends (POR and LVD reset must end before the external reset ends). <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from when the external resets end. tSU: How long from when the TOOL0 pin is plac ed at the low level until a pin reset ends tHD: How long to keep the TOOL0 pin at the low level from when the external resets end (excluding the processing time of the firmware to control the flash memory) (TA = -40 to +85°C, 1.8 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP . MAX. Unit Transfer rate During serial programming 115,200 1,000,000 bps (TA = -40 to +85°C, 1.8 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) (TA = +85 to +105°C, 2.4 V  AVDD = VDD  3.6 V, VSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit How long from when an external reset ends until the initial communication settings are specified Note 1 tSUINIT POR and LVD reset must end before the external reset ends. 100 ms How long from when the TOOL0 pin is placed at the low level until an external reset ends Note 1 tSU POR and LVD reset must end before the external reset ends. 10 s How long the TOOL0 pin must be kept at the low level after an external reset ends (excluding the processing time of the firmware to control the flash memory) Notes 1, 2 tHD POR and LVD reset must end before the external reset ends. 1m s RESET TOOL0 tSU <4> tSUINIT 723 µs + tHD processing time 00H reception (TOOLRxD, TOOLTxD mode)

RL78/I1D 3. PACKAGE DRAWINGS R01DS0244EJ0200 Rev. 2.00 Page 94 of 99 Jan 16, 2015 3. PACKAGE DRAWINGS 3.1 20-pin products R5F1176AGSP, R5F11768GSP 2012 Renesas Electronics Corporation. All rights reserved. P-LSSOP20-4.4x6.5-0.65 PLSP0020JB-A P20MA-65-NAA-1 0.1 1 10 detail of lead end ITEM DIMENSIONS D E e A L c y bp 0.10 0.10 0 to 10 (UNIT:mm) A A1 ey HE c 6.50 4.40 0.20 0.10 6.40 0.100.10 1.45 MAX. 1.15 0.65 0.12 0.10 0.050.22 0.05 0.020.15 0.50 0.20 bp HE E D L NOTE 1.Dimensions “ 1” and “ 2” 2.Dimension “ ” does not include tr

RL78/I1D 3. PACKAGE DRAWINGS R01DS0244EJ0200 Rev. 2.00 Page 95 of 99 Jan 16, 2015 3.2 24-pin products R5F1177AGNA, R5F11778GNA <R> 2013 Renesas Electronics Corporation. All rights reserved. Sy e Lp S xbA B M A D E A S B A D E DETAIL OF A PART EXPOSED DIE PAD P-HWQFN24-4x4-0.50 PWQN0024KE-A P24K8-50-CAB-3 0.04 18 13 1219 INDEX AREA D A Lp 0.20 2.50 0.40 4.00 4.00 2.50 Referance Symbol Min Nom Max Dimension in Millimeters 0.30 0.30 0.50 b 0.18 x A 0.80 y 0.05 0.00 0.25 e Z Z c D E D E E 0.50 0.05 0.75 0.75 0.15 0.25 A1 c2 4.053.95 4.053.95 Z Z D E

RL78/I1D 3. PACKAGE DRAWINGS R01DS0244EJ0200 Rev. 2.00 Page 96 of 99 Jan 16, 2015 3.3 30-pin products R5F117ACGSP , R5F117AAGSP , R5F117A8GSP P-LSSOP30-0300-0.65 PLSP0030JB-B S30MC-65-5A4-3 0.18 S S H J T I G D E F C B K P L U N ITEM B C I L M N A K D E F G H J P 30 16 115 A detail of lead end MM T MILLIMETERS 0.65 (T.P .) 0.45 MAX. 0.13 0.5 6.1 0.2 0.10 9.85 0.15 0.17 0.03 0.1 0.05 0.24 1.3 0.1 8.1 0.2 1.2 0.08 0.07 1.0 0.2 3 5 0.25 0.6 0.15U NOTE Each lead centerline is located within 0.13 mm of its true position (T.P .) at maximum material condition.

RL78/I1D 3. PACKAGE DRAWINGS R01DS0244EJ0200 Rev. 2.00 Page 97 of 99 Jan 16, 2015 3.4 32-pin products R5F117BCGNA, R5F117BAGNA P-HVQFN32-5x5-0.50 PVQN0032KE-A P32K9-50B-BAH 0.058 D A Lp H 0.20 3.30 0.40 4.75 4.75 3.30 Referance Symbol Min Nom Max Dimension in Millimeters 0.30 0.30 0.50 b 0.20 x A 0.90 y 0.05 H 5.004.95 5.05 DETAIL OF A PART Sy eLp S xbA B M A D E 25 16 H S EXPOSED DIE PADD E B A 0.00 0.25 H INDEX MARKZZ 1 8 1724 e Z Z c D E D E D E E 0.50 0.10 5.004.95 5.05 0.75 0.75 0.19 0.21 A A1 c 2 E D D E

RL78/I1D 3. PACKAGE DRAWINGS R01DS0244EJ0200 Rev. 2.00 Page 98 of 99 Jan 16, 2015 R5F117BAGFP, R5F117BCGFP 0.145 ±0.055 (UNIT:mm) ITEM DIMENSIONS D E HD HE A 7.00±0.10 7.00±0.10 9.00±0.20 9.00±0.20 1.70 MAX. 0.10±0.10 1.40 c θ e x y 0.80 0.20 0.10 L 0.50±0.20 0° to 8° 0.37±0.05b NOTE 1.Dimensions “ 1” and “ 2” do not include mold flash. 2.Dimension “ 3” does not include trim offset. y e x bM θ L c HD HE A D E detail of lead end 32 9 P-LQFP32-7x7-0.80 PLQP0032GB-A P32GA-80-GBT -1 0.2

RL78/I1D 3. PACKAGE DRAWINGS R01DS0244EJ0200 Rev. 2.00 Page 99 of 99 Jan 16, 2015 3.5 48-pin products R5F117GCGFB, R5F117GAGFB P-LFQFP48-7x7-0.50 PLQP0048KB-A 48P6Q-A 0.2 D A 0.27 7.00 7.00 Referance Symbol Min Nom Max Dimension in Millimeters 0.00 0.17 1.70 x y 0.10 9.00 e b c p E 9.00 0.20 0.22 0.125 0.35 0.65 1.40 H EH D A 0.1750.105 θ 0° 8° 0.50 0.08 0.10 6.90 6.90 7.10 7.10 8.80 8.80 9.20 9.20 L 0.50 detail of lead end θ L p y e x bM H H A A A D E 48 13 NOTE 1.Dimensions “ 1” and “ 2” do not include mold flash. 2.Dimension “ 3” does not include trim offset. D E c

SuperFlash is a registered trademar k of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Rev. Date

Description

1.00 Aug 29, 2014 — First Edition issued

2.00 Jan 16, 2015 24, 25, 27 Addition of note 7 in 2.3.2 Supply current characteristics 24, 26 Addition of description in 2. 3.2 Supply current characteristics 26, 28 Modification of description in 2.3.2 Supply current characteristics 28 Correction of error in 2.3.2 Supply current characteristics 95 Modification of package drawing in 3.2 24-pin products All trademarks and registered trademarks are the property of their respective owners. Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.

REVISION HISTORY

(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). (2) HANDLING OF UNUSED INPUT PINS: Unconnected CM OS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an in ternal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resist or if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) PRECAUTION AGAINST ESD: A strong electric fi eld, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade t he device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequat e. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be gr ounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touc hed with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. (4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the in itial status of a MOS device. Immediately after the power source is turn ed ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O setti ngs or contents of registers. A device is not initialized un til the reset signal is received. A re set operation must be executed immediately after power-on for devices with reset functions. (5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the po wer supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal cu rrent that passes in the device at this time may cause degradation of internal elem ents. Input of signals during th e power off state must be judged separately for each device and according to related specifications governing the device.

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