RL78

Renesas Technology Corp

True Low Power Platform (as low as 66 ?쵡/MHz, and 0.60 ?쵡 for RTC + LVD), 1.6 V to 5.5 V operation

Manufacturer: Renesas Technology Corp

Document: 100 Pages / 854Kb

Request Quote Download Datasheet Read online HTML view

More from Renesas Technology Corp Browse R parts

Online Datasheet

Read RL78 online.

RL78 RENESAS | Alldatasheet

Document overview

Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 100

Technical content

R01DS0053EJ0100 Rev. 1.00 Page 1 of 97 Feb 21, 2012 RL78/G14 RENESAS MCU True Low Power Platform (as low as 66 A/MHz, and 0.60 A for RTC + LVD), 1.6 V to 5.5 V operation, 16 to 256 Kbyte Flash, 44 DMIPS at 32 MHz, for General Purpose Applications Datasheet 1. OUTLINE

1.1 Features

Ultra-Low Power Technology

1.6 V to 5.5 V operation from a single supply
Stop (RAM retained): 0.24 A, (LVD enabled): 0.32 A
Halt (RTC + LVD): 0.60 A
Snooze: T.B.D
Operating: 66 A/MHz 16-bit RL78 CPU Core
Delivers 44 DMIPS at maximum operating frequency of

32 MHz

Instruction execution: 86% of instructions can be executed in 1 to 2 clock cycles
CISC architecture (Harvard) with 3-stage pipeline
Multiply signed & unsigned: 16 x 16 to 32-bit result in 1 clock cycle
MAC: 16 x 16 to 32-bit result in 2 clock cycles
16-bit barrel shifter for shift & rotate in 1 clock cycle
1-wire on-chip debug function Code Flash Memory
Density: 16 KB to 256 KB
Block size: 1KB
On-chip single voltage flash memory with protection from block erase/writing
Self-programming with secure boot swap function and flash shield window function Data Flash Memory
Data flash with background operation
Data flash size: 4 KB to 8 KB size options
Erase cycles: 1 Million (typ.)
Erase/programming voltage: 1.8 V to 5.5 V RAM
2.5 KB to 24 KB size options
Supports operands or instructions
Back-up retention in all modes High-speed On-chip Oscillator
32 MHz with +/- 1% accuracy over voltage (1.8 V to

5.5 V) and temperature (-20°C to 85°C)

Pre-configured settings: 64 MHz,48 MHz,32 MHz,

24 MHz, 16 MHz, 12 MHz, 8 MHz, 4 MHz & 1 MHz

64 MHz, 48 MHz for timer RD Reset and Supply Management
Power-on reset (POR) monitor/generator
Low voltage detection (LVD) with 14 setting options (Interrupt and/or reset function) General Purpose I/O
5 V tolerant, high-current (up to 20 mA per pin)
Open-drain, on-chip pull-up resistor Data Transfer Controller (DTC)
39 sources & 24 different settings
Transfer data: 8 bits/16 bits
Normal mode and repeat mode Event Link Controller (ELC)
Reduce interrupt intervention
Link 26 events to specified peripheral function Multiple Communication Interfaces
Up to 8 x I2C master
Up to 2 x I2C multi-master
Up to 8 x CSI/SPI (7-, 8-bit)
Up to 4 x UART (7-, 8-, 9-bit)
Up to 1 x LIN Extended-Function Timers
Multi-function 16-bit timers: Up to 8 channels
Motor control timer (3 ph - complementary mode)
Timer with encoder function: 16-bit, 1 channel
Real-time clock (RTC): 1 channel (full calendar and alarm function with watch correction function)
Interval timer: 12-bit, 1 channel
15 kHz watchdog timer: 1 channel (window function) Rich Analog
ADC: Up to 20 channels, 10-bit resolution, 2.1 s conversion time
Supports 1.6 V
2 x window comparators, with ELC connection
D/A converter: 2 channels, 8-bit resolution
Internal voltage reference (1.45 V)
On-chip temperature sensor Safety Features (IEC or UL 60730 compliance)
Flash memory CRC calculation
RAM parity error check
RAM write protection
SFR write protection
Illegal memory access detection
Clock stop/frequency detection
ADC self-test
I/O port read back function (echo) Operating Ambient Temperature
Standard: -40°C to + 85°C
Extended: -40°C to + 105°C <under planning> Package Type and Pin Count From 4 mm x 4 mm to 14 mm x 20 mm QFP: 32, 44, 48, 52, 64, 80,100 QFN: 32, 40, 48 SSOP: 30 LGA: 36, 64 R01DS0053EJ0100 Rev. 1.00 Feb 21, 2012

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 2 of 97 Feb 21, 2012 ROM, RAM capacities Note 1. This is about 4.5 KB when the self-programming function and data flash function are used. Note 2. This is about 23 KB when the self-programming function and data flash function are used. Flash ROM Data flash RAM RL78/G14 30 pins 32 pins 36 pins 40 pins

192 KB 8 KB 20 KB — — — R5F104EH

128 KB 8 KB 16 KB R5F104AG R5F104BG R5F104CG R5F104EG

96 KB 8 KB 12 KB R5F104AF R5F104BF R5F104CF R5F104EF

64 KB 4 KB 5.5 KB Note 1 R5F104AE R5F104BE R5F104CE R5F104EE 48 KB 4 KB 5.5 KB Note 1 R5F104AD R5F104BD R5F104CD R5F104ED

32 KB 4 KB 4 KB R5F104AC R5F104BC R5F104CC R5F104EC

16 KB 4 KB 2.5 KB R5F104AA R5F104BA R5F104CA R5F104EA Flash ROM Data flash RAM RL78/G14 44 pins 48 pins 52 pins 64 pins

256 KB 8 KB 24 KB Note 2 R5F104FJ R5F104GJ R5F104JJ R5F104LJ

192 KB 8 KB 20 KB R5F104FH R5F104GH R5F104JH R5F104LH

128 KB 8 KB 16 KB R5F104FG R5F104GG R5F104JG R5F104LG

96 KB 8 KB 12 KB R5F104FF R5F104GF R5F104JF R5F104LF

64 KB 4 KB 5.5 KB Note 1 R5F104FE R5F104GE R5F104JE R5F104LE 48 KB 4 KB 5.5 KB Note 1 R5F104FD R5F104GD R5F104JD R5F104LD

32 KB 4 KB 4 KB R5F104FC R5F104GC R5F104JC R5F104LC

16 KB 4 KB 2.5 KB R5F104FA R5F104GA — — Flash ROM Data flash RAM RL78/G14 80 pins 100 pins

256 KB 8 KB 24 KB Note 2 R5F104MJ R5F104PJ

192 KB 8 KB 20 KB R5F104MH R5F104PH

128 KB 8 KB 16 KB R5F104MG R5F104PG

96 KB 8 KB 12 KB R5F104MF R5F104PF

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 3 of 97 Feb 21, 2012

1.2 Ordering Information

(1/2) Pin count Package Part Number 30 pins 30-pin plastic SSOP (7.62 mm (300)) R5F104 AAASP, R5F104ACASP, R5F104ADASP, R5F104AEASP, R5F104AFASP , R5F104AGASP R5F104AADSP , R5F104ACDSP, R5F104ADDSP, R5F104AEDSP , R5F104AFDSP, R5F104AGDSP 32 pins 32-pin plastic WQFN (fine pitch) (5 × 5) R5F104BAANA, R5F 104BCANA, R5F104BDANA, R5F104BEANA, R5F104BFANA, R5F104BGANA R5F104BADNA, R5F104BCDNA, R5F104BDDNA, R5F104BEDNA, R5F104BFDNA, R5F104BGDNA 32-pin plastic LQFP (7 × 7) R5F104BAAFP, R5F104BCAFP, R5F104BDAFP, R5F104BEAFP, R5F104BFAFP, R5F104BGAFP R5F104BADFP, R5F104BCDFP, R5F104BDDFP, R5F104BEDFP , R5F104BFDFP, R5F104BGDFP 36 pins 36-pin plastic FLGA (4 × 4) R5F104CAALA, R5F104CCALA, R5F104CDALA, R5F104CEALA, R5F104CFALA, R5F104CGALA R5F104CADLA, R5F104CCDLA, R5F104CDDLA, R5F104CEDLA, R5F104CFDLA, R5F104CGDLA 40 pins 40-pin plastic WQFN (fine pitch) (6 × 6) R5F104EAANA, R5F 104ECANA, R5F104EDANA, R5F104EEANA, R5F104EFANA, R5F104EGANA, R5F104EHANA R5F104EADNA, R5F104ECDNA, R5F104EDDNA, R5F104EEDNA, R5F104EFDNA, R5F104EGDNA, R5F104EHDNA 44 pins 44-pin plastic LQFP (10 × 10) R5F104FAAFP, R5F104FCAFP, R5F104FDAFP , R5F104FEAFP, R5F104FFAFP , R5F104FGAFP, R5F104FHAFP , R5F104FJAFP R5F104FADFP , R5F104FCDFP , R5F104FDDFP , R5F104FEDFP , R5F104FFDFP, R5F104FGDFP, R5F104FHDFP, R5F104FJDFP 48 pins 48-pin plastic LQFP (fine pitch) (7 × 7) R5F104GAAFB, R5F104GCAFB, R5F104GDAFB, R5F104GEAFB, R5F104GFAFB, R5F104GGAFB, R5F104GHAFB, R5F104GJAFB R5F104GADFB, R5F104GCDFB, R5F104GDDFB, R5F104GEDFB, R5F104GFDFB, R5F104GGDFB, R5F104GHDFB, R5F104GJDFB 48-pin plastic WQFN (7 × 7) R5F104GAANA, R5F104GCANA, R5F104GDANA, R5F104GEANA, R5F104GFANA, R5F104GGANA, R5F104GHANA, R5F104GJANA R5F104GADNA, R5F104GCDNA, R5F104GDDNA, R5F104GEDNA, R5F104GFDNA, R5F104GGDNA, R5F104GHDNA, R5F104GJDNA 52 pins 52-pin plastic LQFP (10 × 10) R5F104JCAFA, R5F104JDAFA, R5F104JEAFA, R5F104JFAFA, R5F104JGAFA, R5F104JHAFA, R5F104JJAFA R5F104JCDFA, R5F104JDDFA, R5F104JEDFA, R5F104JFDFA, R5F104JGDFA, R5F104JHDFA, R5F104JJDFA

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 4 of 97 Feb 21, 2012 (2/2) Pin count Package Part Number 64 pins 64-pin plastic LQFP (12 × 12) R5F104LCAFA, R5F104LDAFA, R5F104LEAFA, R5F104LFAFA, R5F104LGAFA, R5F104LHAFA, R5F104LJAFA R5F104LCDFA, R5F104LDDFA, R5F104LEDFA, R5F104LFDFA, R5F104LGDFA, R5F104LHDFA, R5F104LJDFA 64-pin plastic LQFP (fine pitch) (10 × 10) R5F104LCAFB, R5F104LDAFB, R5F104LEAFB, R5F104LFAFB, R5F104LGAFB, R5F104LHAFB, R5F104LJAFB R5F104LCDFB, R5F104LDDFB, R5F104LEDFB, R5F104LFDFB, R5F104LGDFB, R5F104LHDFB, R5F104LJDFB 64-pin plastic FLGA (5 × 5) R5F104LCALA, R5F104LDALA, R5F104LEALA, R5F104LFALA, R5F104LGALA, R5F104LHALA, R5F104LJALA R5F104LCDLA, R5F104LDDLA, R5F104LEDLA, R5F104LFDLA, R5F104LGDLA, R5F104LHDLA, R5F104LJDLA 64-pin plastic LQFP (14 × 14) R5F104LCAFP , R5F104LDAFP, R5F104LEAFP, R5F104LFAFP, R5F104LGAFP, R5F104LHAFP, R5F104LJAFP R5F104LCDFP, R5F104LDDFP , R5F104LEDFP, R5F104LFDFP, R5F104LGDFP, R5F104LHDFP, R5F104LJDFP 80 pins 80-pin plastic LQFP (fine pitch) (12 × 12) R5F104MFAFB, R5F104MGAFB, R5F104MHAFB, R5F104MJAFB R5F104MFDFB, R5F104MGDFB, R5F104MHDFB, R5F104MJDFB 80-pin plastic LQFP (14 × 14) R5F104MFAFA, R5F104MGAFA, R5F104MHAFA, R5F104MJAFA R5F104MFDFA, R5F104MGDFA, R5F104MHDFA, R5F104MJDFA 100 pins 100-pin plastic LQFP (fine pitch) (14 × 14) R5F104PFAFB, R5F104PGAFB, R5F104PHAFB, R5F104PJAFB R5F104PFDFB, R5F104PGDFB, R5F104PHDFB, R5F104PJDFB 100-pin plastic LQFP (14 × 20) R5F104PFAFA, R5F104PGAFA, R5F104PHAFA, R5F104PJAFA R5F104PFDFA, R5F104PGDFA, R5F104PHDFA, R5F104PJDFA

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 5 of 97 Feb 21, 2012 Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G14 Part No. R 5 F 1 0 4 L E A x x x F B Package type: SP: SSOP, 0.65 mm pitch FP: LQFP, 0.80 mm pitch FA: LQFP, 0.65 mm pitch FB: LQFP, 0.50 mm pitch NA: WQFN, 0.50 mm pitch LA: LGA, 0.50 mm pitch ROM number (Omitted with blank products) Classification: A: Consumer applications, operating ambient temperature: -40°C to 85°C D: Industrial applications, operating ambient temperature: -40°C to 85°C ROM capacity: A: 16 KB C: 32 KB D: 48 KB E: 64 KB F: 96 KB G: 128 KB H: 192 KB J: 256 KB Pin count: A: 30-pin B: 32-pin C: 36-pin E: 40-pin F: 44-pin G: 48-pin J: 52-pin L: 64-pin M: 80-pin P: 100-pin RL78/G14 Memory type: F : Flash memory Renesas MCU Renesas semiconductor product

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 6 of 97 Feb 21, 2012

1.3 Pin Configuration (Top View)

1.3.1 30-pin products

30-pin plastic SSOP (7.62 mm (300)) Note Mounted on the 96 KB or more code flash memory products. Caution Connect the REGC pin to V SS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the per ipheral I/O redirection register 0, 1 (PIOR0, 1). P21/ANI1/AVREFM P22/ANI2/ANO0 Note P23/ANI3 P147/ANI18/VCOUT1 Note P10/SCK11/SCL11/TRDIOD1 P11/SI11/SDA11/TRDIOC1 P12/SO11/TRDIOB1/IVREF1 Note P13/TxD2/SO20/TRDIOA1/IVCMP1 Note P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P15/PCLBUZ1/SCK20 /SCL20/TRDIOB0/(SDAA0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0) P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0 Note/(TXD0) P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0) P30/INTP3/SCK00 /SCL00/TRJO0 P01/ANI16/TO00/RxD1/TRGCLKB/TRJIO0 P00/ANI17/TI00/TxD1/TRGCLKA/(TRJO0) P120/ANI19/VCOUT0 Note P40/TOOL0 RESET P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P60/SCLA0 P61/SDAA0 P31/TI03/TO03/INTP4/PCLBUZ0/SSI00/(TRJIO0) P20/ANI0/AVREFP

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 7 of 97 Feb 21, 2012 1.3.2 32-pin products

32-pin plastic WQFN (fine pitch) (5 × 5)
32-pin plastic LQFP (7 × 7) Note Mounted on the 96 KB or more code flash memory products. Caution Connect the REGC pin to V SS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the per ipheral I/O redirection register 0, 1 (PIOR0, 1). P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0) P30/INTP3/SCK00/SCL00/TRJO0 P70 P31/TI03/TO03/INTP4/PCLBUZ0/(TRJIO0) P62/SSI00 P61/SDAA0 P60/SCLA0 exposed die pad P147/ANI18/VCOUT1 Note P23/ANI3/ANO1 Note P22/ANI2/ANO0 Note P20/ANI0/AVREFP P01/ANI16/TO00/RxD1/TRGCLKB/TRJIO0 P00/ANI17/TI00/TxD1/TRGCLKA/(TRJO0) 23456 78 24 23 22 21 20 19 18 17P40/TOOL0 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD RESET P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0 Note/(TXD0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0) P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0) P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P13/TxD2/SO20/TRDIOA1/IVCMP1 Note P12/SO11/TRDIOB1/IVREF1 Note P11/SI11/SDA11/TRDIOC1 P10/SCK11/SCL11/TRDIOD1 P120/ANI19/VCOUT0 Note P21/ANI1/AVREFM

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 8 of 97 Feb 21, 2012 1.3.3 36-pin products

36-pin plastic FLGA (4 × 4) Note Mounted on the 96 KB or more code flash memory products. Caution Connect the REGC pin to V SS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the per ipheral I/O redirection register 0, 1 (PIOR0, 1). ABCDEF P60/SCLA0 V DD P121/X1 P122/X2/EXCLK P137/INTP0 P40/TOOL0 P62/SSI00 P61/SDAA0 V SS REGC RESET P120/ANI19/ VCOUT0 Note 5 P72/SO21 P71/SI21/ SDA21 P14/RxD2/SI20/ SDA20/TRDIOD0/ (SCLA0) P31/TI03/TO03/ INTP4/PCLBUZ0/ (TRJIO0) P00/TI00/TxD1/ TRGCLKA/ (TRJO0) P01/TO00/ RxD1/TRGCLKB/ TRJIO0 P50/INTP1/ SI00/RxD0/ TOOLRxD/ SDA00/TRGIOA/ (TRJO0) P70/SCK21 SCL21 P15/PCLBUZ1/ SCK20 /SCL20/ TRDIOB0/ (SDAA0) P22/ANI2/ ANO0 Note P20/ANI0/ AVREFP P21/ANI1/ AV REFM P30/INTP3/ SCK00 /SCL00/ TRJO0 P16/TI01/TO01/ INTP5/TRDIOC0/ IVREF0 Note/ (RXD0) P12/SO11/ TRDIOB1/ IVREF1 Note P11/SI11/ SDA11/ TRDIOC1 P24/ANI4 P23/ANI3/ ANO1 Note P51/INTP2/ SO00/TxD0/ TOOLTxD/ TRGIOB P17/TI02/TO02/ TRDIOA0/ TRDCLK0/ IVCMP0 Note/ (TXD0) P13/TxD2/ SO20/TRDIOA1/ IVCMP1 Note P10/SCK11/ SCL11/ TRDIOD1 P147/ANI18/ VCOUT1 Note P25/ANI5 ABCDEF Top View Bottom View INDEX MARK A BCDE F F EDCB A

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 9 of 97 Feb 21, 2012 1.3.4 40-pin products

40-pin plastic WQFN (fine pitch) (6 × 6) Note Mounted on the 96 KB or more code flash memory products. Caution Connect the REGC pin to V SS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the per ipheral I/O redirection register 0, 1 (PIOR0, 1). exposed die pad P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3/ANO1 Note P22/ANI2/ANO0 Note P21/ANI1/AVREFM P20/ANI0/AVREFP P01/TO00/RxD1/TRGCLKB/TRJIO0 P00/TI00/TxD1/TRGCLKA/(TRJO0) P120/ANI19/VCOUT0 Note P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0) P30/INTP3/RTC1HZ/SCK00 /SCL00/TRJO0 P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3 P31/TI03/TO03/INTP4/PCLBUZ0/(TRJIO0) P62/SSI00 P61/SDAA0 P60/SCLA0123456 789 1 0 3029 28 27 26 2524 23 22 21 VDD VSS REGC P121/X1 P137/INTP0 P123/XT1 P124/XT2/EXCLKS RESET P40/TOOL0 P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0 Note/(TXD0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0) P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0) P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P13/TxD2/SO20/TRDIOA1/IVCMP1 Note P12/SO11/TRDIOB1/IVREF1 Note P11/SI11/SDA11/TRDIOC1 P10/SCK11/SCL11/TRDIOD1 P147/ANI18/VCOUT1 Note P122/X2/EXCLK

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 10 of 97 Feb 21, 2012 1.3.5 44-pin products

44-pin plastic LQFP (10 × 10) Note Mounted on the 96 KB or more code flash memory products. Caution Connect the REGC pin to V SS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the per ipheral I/O redirection register 0, 1 (PIOR0, 1). P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3/ANO1 Note P22/ANI2/ANO0 Note P21/ANI1/AVREFM P20/ANI0/AVREFP P01/TO00/RxD1/TRGCLKB/TRJIO0 P00/TI00/TxD1/TRGCLKA/(TRJO0) P120/ANI19/VCOUT0 Note P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0) P30/INTP3/RTC1HZ/SCK00 /SCL00/TRJO0 P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3 P31/TI03/TO03/INTP4/PCLBUZ0/(TRJIO0) P63 P62/SSI00 P61/SDAA0 P60/SCLA0 33 3231 30 29 28 27 26 25 24 1 23 45 6 789 1 0 1 1 P41 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0 Note/(TXD0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0) P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0) P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P13/TxD2/SO20/TRDIOA1/IVCMP1 Note P12/SO11/TRDIOB1/IVREF1 Note P11/SI11/SDA11/TRDIOC1 P10/SCK11 /SCL11/TRDIOD1 P146 P147/ANI18/VCOUT1 Note P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 11 of 97 Feb 21, 2012 1.3.6 48-pin products

48-pin plastic LQFP (fine pitch) (7 × 7) Note Mounted on the 96 KB or more code flash memory products. Caution Connect the REGC pin to V SS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the per ipheral I/O redirection register 0, 1 (PIOR0, 1). P147/ANI18/VCOUT1 Note P146 P10/SCK11/SCL11/TRDIOD1 P11/SI11/SDA11/TRDIOC1 P12/SO11/TRDIOB1/IVREF1 Note P13/TxD2/SO20/TRDIOA1/IVCMP1 Note P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P15/PCLBUZ1/SCK20 /SCL20/TRDIOB0/(SDAA0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0) P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0 Note/(TXD0) P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0) P120/ANI19/VCOUT0 Note P41/(TRJIO0) P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD 123456789 1 0 1 1 1 2 36 35 34 33 32 31 30 29 28 27 26 25 P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0 P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3/SO01 P74/KR4/INTP8/SI01/SDA01 P75/KR5/INTP9/SCK01/SCL01 P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0) P63 P62/SSI00 P61/SDAA0 P60/SCLA0 P140/PCLBUZ0/INTP6 P00/TI00/TxD1/TRGCLKA/(TRJO0) P01/TO00/RxD1/TRGCLKB/TRJIO0 P130 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2/ANO0 Note P23/ANI3/ANO1 Note P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 12 of 97 Feb 21, 2012

48-pin plastic WQFN (7 × 7) Note Mounted on the 96 KB or more code flash memory products. Caution Connect the REGC pin to V SS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the per ipheral I/O redirection register 0, 1 (PIOR0, 1). P147/ANI18/VCOUT1 Note P146 P10/SCK11/SCL11/TRDIOD1 P11/SI11/SDA11/TRDIOC1 P12/SO11/TRDIOB1/IVREF1 Note P13/TxD2/SO20/TRDIOA1/IVCMP1 Note P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P15/PCLBUZ1/SCK20 /SCL20/TRDIOB0/(SDAA0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0) P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0 Note/(TXD0) P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0) P120/ANI19/VCOUT0 Note P41/(TRJIO0) P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD 123456789 1 0 1 1 1 2 36 35 34 33 32 31 30 29 28 27 26 25 P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0 P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3/SO01 P74/KR4/INTP8/SI01/SDA01 P75/KR5/INTP9/SCK01/SCL01 P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0) P63 P62/SSI00 P61/SDAA0 P60/SCLA0 P140/PCLBUZ0/INTP6 P00/TI00/TxD1/TRGCLKA/(TRJO0) P01/TO00/RxD1/TRGCLKB/TRJIO0 P130 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2/ANO0 Note P23/ANI3/ANO1 Note P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7 exposed die pad

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 13 of 97 Feb 21, 2012 1.3.7 52-pin products

52-pin plastic LQFP (10 × 10) Note Mounted on the 96 KB or more code flash memory products. Caution Connect the REGC pin to V SS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the per ipheral I/O redirection register 0, 1 (PIOR0, 1). P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3/SO01 P74/KR4/INTP8/SI01/SDA01 P75/KR5/INTP9/SCK01 /SCL01 P76/KR6/INTP10/(RXD2) P77/KR7/INTP11/(TXD2) P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0) P63 P62/SSI00 P61/SDAA0 P60/SCLA0 P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3/ANO1 Note P22/ANI2/ANO0 Note P21/ANI1/AVREFM P20/ANI0/AVREFP P130 P03/ANI16/RxD1 P02/ANI17/TxD1 P01/TO00/TRGCLKB/TRJIO0 P00/TI00/TRGCLKA/(TRJO0) P140/PCLBUZ0/INTP6 RESET P41/(TRJIO0) P40/TOOL0 P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P147/ANI18/VCOUT1 Note P146 P10/SCK11/SCL11/TRDIOD1 P11/SI11/SDA11/TRDIOC1 P12/SO11/TRDIOB1/IVREF1 Note P13/TxD2/SO20/TRDIOA1/IVCMP1 Note P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0) P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0 Note/(TXD0) P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0) P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0 123 456 789 1 0 1 3 12 11 39 38 37 36 35 34 33 32 31 30 27 28 29 P120/ANI19/VCOUT0 Note

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 14 of 97 Feb 21, 2012 1.3.8 64-pin products

64-pin plastic LQFP (14 × 14)
64-pin plastic LQFP (12 × 12)
64-pin plastic LQFP (fine pitch) (10 × 10) Note Mounted on the 96 KB or more code flash memory products. Caution 1. Make EV SS0 pin the same potential as VSS pin. Caution 2. Make V DD pin the same potential as EVDD0 pin, or the potential that is higher than the EVDD0 pin. Caution 3. Connect the REGC pin to V SS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the V DD and EV DD0 pins and connect the V SS and EV SS0 pins to separate ground lines. Remark 3. Functions in parentheses in the above figure can be assigned via settings in the per ipheral I/O redirection register 0, 1 (PIOR0, 1). P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3/ANO1 Note P22/ANI2/ANO0 Note P21/ANI1/AVREFM P20/ANI0/AVREFP P130 P04/SCK10/SCL10 P03/ANI16/SI10/RxD1/SDA10 P02/ANI17/SO10/TxD1 P01/TO00/TRGCLKB/TRJIO0 P00/TI00/TRGCLKA/(TRJO0) P141/PCLBUZ1/INTP7 P140/PCLBUZ0/INTP6 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P147/ANI18/VCOUT1 Note P146 P10/SCK11 /SCL11/TRDIOD1 P11/SI11/SDA11/TRDIOC1 P12/SO11/TRDIOB1/IVREF1 Note/(INTP5) P13/TxD2/SO20/TRDIOA1/IVCMP1 Note P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P15/SCK20/SCL20/TRDIOB0/(SDAA0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(SI00)/(RXD0) P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0 Note/(SO00)/(TXD0) P55/(PCLBUZ1)/(SCK00)/(INTP4) P54/(INTP3) P53/(INTP2) P52/(INTP1) P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0) P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0 P05/(INTP10) P06/(INTP11)/(TRJIO0) P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3/SO01 P74/KR4/INTP8/SI01/SDA01 P75/KR5/INTP9/SCK01/SCL01 P76/KR6/INTP10/(RXD2) P77/KR7/INTP11/(TXD2) P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0) P63 P62/SSI00 P61/SDAA0 P60/SCLA0 123456 7 8 9 1 01 11 21 31 41 51 6 P120/ANI19/VCOUT0 Note P43/(INTP9) P42/(INTP8) P41/(TRJIO0) P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS EVSS0 VDD EVDD0

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 15 of 97 Feb 21, 2012

64-pin plastic FLGA (5 × 5) Note Mounted on the 96 KB or more code flash memory products. Caution 1. Make EV SS0 pin the same potential as VSS pin. Caution 2. Make V DD pin the same potential as EVDD0 pin, or the potential that is higher than the EVDD0 pin. Caution 3. Connect the REGC pin to V SS pin via a capacitor (0.47 to 1 F). (Remarks are listed on the next page.) ABCDEFGH EVDD0 EVSS0 P121/X1 P122/X2/ EXCLK P137/INTP0 P123/XT1 P124/XT2/ EXCLKS P120/ANI19/ VCOUT0 Note 8 P60/SCLA0 V DD VSS REGC RESET P01/TO00/ TRGCLKB/ TRJIO0 P00/TI00/ TRGCLKA/ (TRJO0) P140/ PCLBUZ0/ INTP6 P61/SDAA0 P62/SSI00 P63 P40/TOOL0 P41/(TRJIO0) P43/(INTP9) P02/ANI17/ SO10/TxD1 P141/ PCLBUZ1/ INTP7 P77/KR7/ INTP11/(TXD2) P31/TI03/ TO03/INTP4/ (PCLBUZ0)/ (TRJIO0) P53/(INTP2) P42/(INTP8) P03/ANI16/ SI10/RxD1/ SDA10 P04/SCK10 SCL10 P130 P20/ANI0/ AVREFP P75/KR5/ INTP9/ SCK01 SCL01 P76/KR6/ INTP10/ (RXD2) P52/(INTP1) P54/(INTP3) P16/TI01/ TO01/INTP5/ TRDIOC0/ IVREF0 Note/ (SI00)/(RXD0) P21/ANI1/ AVREFM P22/ANI2/ ANO0 Note P23/ANI3/ ANO1 Note P70/KR0/ SCK21/ SCL21 P73/KR3/ SO01 P74/KR4/ INTP8/SI01/ SDA01 P17/TI02/TO02/ TRDIOA0/ TRDCLK0/ IVCMP0 Note/ (SO00)/(TXD0) P15/SCK20/ SCL20/ TRDIOB0/ (SDAA0) P12/SO11/ TRDIOB1/ IVREF1 Note/ (INTP5) P24/ANI4 P26/ANI6 P30/INTP3/ RTC1HZ/ SCK00/ SCL00/TRJO0 P72/KR2/ SO21 P71/KR1/ SI21/SDA21 P06/(INTP11)/ (TRJIO0) P14/RxD2/ SI20/SDA20/ TRDIOD0/ (SCLA0) P11/SI11/ SDA11/ TRDIOC1 P25/ANI5 P27/ANI7 P05/(INTP10) P50/INTP1/ SI00/RxD0/ TOOLRxD/ SDA00/ TRGIOA/ (TRJO0) P51/INTP2/ SO00/TxD0/ TOOLTxD/ TRGIOB P55/ (PCLBUZ1)/ (SCK00 (INTP4) P13/TxD2/ SO20/ TRDIOA1/ IVCMP1 Note P10/SCK11/ SCL11/ TRDIOD1 P146 P147/ANI18/ VCOUT1 Note ABCDEFGH HGFEDCBA ABC D EFG H Top View Bottom View INDEX MARK

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 16 of 97 Feb 21, 2012 Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the V DD and EV DD0 pins and connect the V SS and EV SS0 pins to separate ground lines. Remark 3. Functions in parentheses in the above figure can be assigned via settings in the per ipheral I/O redirection register 0, 1 (PIOR0, 1).

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 17 of 97 Feb 21, 2012 1.3.9 80-pin products

80-pin plastic LQFP (14 × 14)
80-pin plastic LQFP (fine pitch) (12 × 12) Caution Make EV SS0 pin the same potential as VSS pin. Caution 1. Make V DD pin the same potential as EVDD0 pin, or the potential that is higher than the EVDD0 pin. Caution 2. Connect the REGC pin to V SS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the V DD and EV DD0 pins and connect the V SS and EV SS0 pins to separate ground lines. Remark 3. Functions in parentheses in the above figure can be assigned via settings in the per ipheral I/O redirection register 0, 1 (PIOR0, 1). P152/ANI10 P151/ANI9 P150/ANI8 P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3/ANO1 P22/ANI2/ANO0 P21/ANI1/AV REFM P20/ANI0/AVREFP P130 P04/SCK10/SCL10 P03/ANI16/SI10/RxD1/SDA10 P02/ANI17/SO10/TxD1 P01/TO00/TRGCLKB/TRJIO0 P00/TI00/TRGCLKA/(TRJO0) P144/SO30/TxD3 P143/SI30/RxD3/SDA30 P142/SCK30/SCL30 P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0 P05 P06/(TRJIO0) P70/KR0/SCK21 /SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3 P74/KR4/INTP8 P75/KR5/INTP9 P76/KR6/INTP10/(RXD2) P77/KR7/INTP11/(TXD2) P67/TI13/TO13 P66/TI12/TO12 P65/TI11/TO11 P64/TI10/TO10 P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0) P63/SDAA1 P62/SSI00 /SCLA1 P61/SDAA0 P60/SCLA0 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P141/PCLBUZ1/INTP7 P140/PCLBUZ0/INTP6 P120/ANI19/VCOUT0 P45/SO01 P44/SI01/SDA01 P43/SCK01/SCL01/(INTP9) P42/(INTP8) P41/(TRJIO0) P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS EVSS0 VDD EVDD0 P153/ANI11 P100/ANI20/(INTP10) P147/ANI18/VCOUT1 P146 P111 P110/(INTP11) P10/SCK11 /SCL11/TRDIOD1 P11/SI11/SDA11/TRDIOC1 P12/SO11/TRDIOB1/IVREF1/(INTP5) P13/TxD2/SO20/TRDIOA1/IVCMP1 P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P15/SCK20 /SCL20/TRDIOB0/(SDAA0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0/(SI00)/(RXD0) P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0/(SO00)/(TXD0) P55/(PCLBUZ1)/(SCK00)/(INTP4) P54/SCK31/SCL31/(INTP3) P53/SI31/SDA31/(INTP2) P52/SO31/(INTP1) P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 18 of 97 Feb 21, 2012 1.3.10 100-pin products

100-pin plastic LQFP (fine pitch) (14 × 14) Caution Make EV SS0, EVSS1 pins the same potential as VSS pin. Caution 1. Make V DD pin the same potential as EVDD0 pin, or the potential that is higher than the EVDD0 pin. Make EVDD1 pin the same potential as EVDD0 pin. Caution 2. Connect the REGC pin to V SS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the V DD, EVDD0 and EVDD1 pins and connect the VSS, EVSS0 and EVSS1 pins to separate ground lines. Remark 3. Functions in parentheses in the above figure can be assigned via settings in the per ipheral I/O redirection register 0, 1 (PIOR0, 1). 123456 78 9 1 0 11 12 13 14 15 16 17 18 19 20 P142/SCK30/SCL30 P141/PCLBUZ1/INTP7 P140/PCLBUZ0/INTP6 P120/ANI19/VCOUT0 P47/INTP2 P46/INTP1 P45/SO01 P44/SI01/SDA01 P43/SCK01 /SCL01 P42 P41/(TRJIO0) P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS 21 22 23 24 25 EVSS0 VDD EVDD0 P60/SCLA0 P61/SDAA0 P81/(SI10)/(RXD1)/(SDA10) P80/(SCK10)/(SCL10) EVSS1 P05 P06/(TRJIO0) P70/KR0/SCK21 /SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3 P74/KR4/INTP8 P75/KR5/INTP9 P76/KR6/INTP10/(RXD2) P77/KR7/INTP11/(TXD2) P67/TI13/TO13 P66/TI12/TO12 P65/TI11/TO11 P64/TI10/TO10 P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0) P63/SDAA1 P62/SSI00 /SCLA1 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 5857 P100/ANI20/(INTP10) P147/ANI18/VCOUT1 P146/(INTP4) P111 P110/(INTP11) P101 P10/SCK11/SCL11/TRDIOD1 P11/SI11/SDA11/TRDIOC1 P12/SO11/TRDIOB1/IVREF1/(INTP5) P13/TxD2/SO20/TRDIOA1/IVCMP1 P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P15/SCK20/SCL20/TRDIOB0/(SDAA0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0/(SI00)/(RXD0) P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0/(SO00)/(TXD0) P57/(INTP3) P56/(INTP1) P55/(PCLBUZ1)/(SCK00 P54/SCK31/SCL31 P53/SI31/SDA31 P150/ANI8 P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3/ANO1 P22/ANI2/ANO0 P21/ANI1/AVREFM P20/ANI0/AVREFP P130 P102 P04/SCK10/SCL10 P03/ANI16/SI10/RxD1/SDA10 P02/ANI17/SO10/TxD1 P01/TO00/TRGCLKB/TRJIO0 P00/TI00/TRGCLKA/(TRJO0) P145 P144/SO30/TxD3 P143/SI30/RxD3/SDA30 100 P151/ANI9 P152/ANI10 80 P153/ANI11 79 P154/ANI12 78 P155/ANI13 77 P156/ANI14 76

56 P52/SO31

55 P51/SO00/TxD0/TOOLTxD/TRGIOB

54 P50/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)

53 EVDD1

P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0

51 P87/(INTP9)

P86/(INTP8) P85/(INTP7) P84/(INTP6) P83 P82/(SO10)/(TXD1)

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 19 of 97 Feb 21, 2012

100-pin plastic LQFP (fine pitch) (14 × 20) Caution Make EV SS0, EVSS1 pins the same potential as VSS pin. Caution 1. Make V DD pin the same potential as EVDD0 pin, or the potential that is higher than the EVDD0 pin. Make EVDD1 pin the same potential as EVDD0 pin Caution 2. Connect the REGC pin to V SS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the V DD, EVDD0 and EVDD1 pins and connect the VSS, EVSS0 and EVSS1 pins to separate ground lines. Remark 3. Functions in parentheses in the above figure can be assigned via settings in the per ipheral I/O redirection register 0, 1 (PIOR0, 1). P146/(INTP4) P111 P110/(INTP11) P101 P10/SCK11 /SCL11/TRDIOD1 P11/SI11/SDA11/TRDIOC1 P12/SO11/TRDIOB1/IVREF1/(INTP5) P13/TxD2/SO20/TRDIOA1/IVCMP1 P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0) P15/SCK20 /SCL20/TRDIOB0/(SDAA0) P16/TI01/TO01/INTP5/TRDIOC0/IVREF0/(SI00)/(RXD0) P17/TI02/TO02/TRDIOA0/TRDCLK0/IVCMP0/(SO00)/(TXD0) P57/(INTP3) P56/(INTP1) P55/(PCLBUZ1)/(SCK00 P54/SCK31/SCL31 P53/SI31/SDA31 P52/SO31 P51/SO00/TxD0/TOOLTxD/TRGIOB P50/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)31 123456 789 1 0 11 12 13 14 15 1617 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P60/SCLA0 P61/SDAA0 P62/SSI00/SCLA1 P63/SDAA1 P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0) P64/TI10/TO10 P65/TI11/TO11 P66/TI12/TO12 P67/TI13/TO13 P77/KR7/INTP11/(TXD2) P76/KR6/INTP10/(RXD2) P75/KR5/INTP9 P74/KR4/INTP8 P73/KR3 P72/KR2/SO21 P71/KR1/SI21/SDA21 P70/KR0/SCK21 /SCL21 P06/(TRJIO0) P05 EVSS1 P80/(SCK10)/(SCL10) P81/(SI10)/(RXD1)/(SDA10) P82/(SO10)/(TXD1) P83 P84/(INTP7) P85/(INTP7) P86/(INTP8) P87/(INTP9) P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0 EVDD1 P140/PCLBUZ0/INTP6 P141/PCLBUZ1/INTP7 P142/SCK30 /SCL30 P143/SI30/RxD3/SDA30 P144/SO30/TxD3 P145 P00/TI00/TRGCLKA/(TRJO0) P01/TO00/TRGCLKB/TRJIO0 P02/ANI17/SO10/TxD1 P03/ANI16/SI10/RxD1/SDA10 P04/SCK10 /SCL10 P102 P130 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2/ANO0 P23/ANI3/ANO1 P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7 P150/ANI8 P151/ANI9 P152/ANI10 P153/ANI11 P154/ANI12 P155/ANI13 P156/ANI14 P100/ANI20/(INTP10) P147/ANI18/VCOUT1 100 P120/ANI19/VCOUT0 P47/INTP2 P46/INTP1 P45/SO01 P44/SI01/SDA01 P43/SCK01/SCL01 P42 P41/(TRJIO0) P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS EVSS0 VDD EVDD0

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 20 of 97 Feb 21, 2012

1.4 Pin Identification

ANI0 to ANI14,: Analog input ANI16 to ANI20 ANO0, ANO1: Analog output AV REFM: A/D converter reference potential ( side) input AV REFP: A/D converter reference potential (+ side) input EV DD0, EVDD1: Power supply for port EVSS0, EVSS1: Ground for port EXCLK: External clock input (main system clock) EXCLKS: External clock input (sub system clock) INTP0 to INTP11: External interrupt input IVCMP0, IVCMP1: Comparator input IVREF0, IVREF1: Comparator reference input KR0 to KR7: Key return P00 to P06: Port 0 P10 to P17: Port 1 P20 to P27: Port 2 P30, P31: Port 3 P40 to P47: Port 4 P50 to P57: Port 5 P60 to P67: Port 6 P70 to P77: Port 7 P80 to P87: Port 8 P100 to P102: Port 10 P110, P111: Port 11 P120 to P124: Port 12 P130, P137: Port 13 P140 to P147: Port 14 P150 to P156: Port 15 PCLBUZ0, PCLBUZ1: Programmable clock output/buzzer output REGC: Regulator capacitance RESET : Reset RTC1HZ: Real-time clock correction clock (1 Hz) output RxD0 to RxD3: Receive data SCK00, SCK01, SCK10,: Serial clock input/output SCK11, SCK20, SCK21, SCK30, SCK31 SCLA0, SCLA1, SCL00,: Serial clock input/output SCL01, SCL10, SCL11, SCL20, SCL21, SCL30, SCL31 SDAA0, SDAA1, SDA00,: Serial data input/output SDA01, SDA10, SDA11, SDA20, SDA21, SDA30, SDA31 SI00, SI01, SI10, SI11,: Serial data input SI20, SI21, SI30, SI31 SO00, SO01, SO10,: Serial data output SO11, SO20, SO21, SO30, SO31 SSI00 : Serial interface chip select input TI00 to TI03,: Timer input TI10 to TI13 TO00 to TO03,: Timer output TO10 to TO13, TRJO0 TOOL0: Data input/output for tool TOOLRxD, TOOLTxD: Data input/output for external device TRDCLK0, TRGCLKA,: Timer external input clock TRGCLKB TRDIOA0, TRDIOB0,: Timer input/output TRDIOC0, TRDIOD0, TRDIOA1, TRDIOB1, TRDIOC1, TRDIOD1, TRGIOA, TRGIOB, TRJIO0 TxD0 to TxD3: Transmit data VCOUT0, VCOUT1: Comparator output V DD: Power supply VSS: Ground X1, X2: Crystal oscillator (main system clock) XT1, XT2: Crystal oscillator (subsystem clock)

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 21 of 97 Feb 21, 2012

1.5 Block Diagram

1.5.1 30-pin products Note Mounted on the 96 KB or more code flash memory products. VOLTAGE REGULATOR REGC INTERRUPT CONTROL RAM SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR RxD0/P50 TxD0/P51 UART1 RxD1/P01 TxD1/P00 SCL00/P30 SDA00/P50 TI02/TO02/P17 TI03/TO03/P31 INTP0/P137 INTP3/P30, INTP4/P31 INTP1/P50, INTP2/P51 RxD0/P50 (LINSEL)

4 ANI0/P20 to

VSS TOOLRxD/P50, TOOLTxD/P51 V DD SDAA0/P61 SCLA0/P60 SERIAL INTERFACE IICA0 INTP5/P16 BUZZER OUTPUT CLOCK OUTPUT CONTROL RxD2/P14 TxD2/P13 SCL20/P15 SDA20/P14 SCK20/P15 SO20/P13 SI20/P14 TI01/TO01/P16 TRDIOA0/TRDCLK0/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 4TRDIOA1/P13 toTRDIOD1/P10 TIMER RJ TRJIO0/P01 TRJO0/P30 INTERVAL TIMER SSI00/P31 ch0 TIMER ARRAY UNIT (4ch) ch1 ch2 ch3 TIMER RD (2ch) ch0 ch1 WINDOW WATCHDOG TIMER REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) UART0 LINSEL CSI11 IIC00 IIC11 TO00/P01 RxD0/P50 (LINSEL) SERIAL ARRAY UNIT1 (2ch) UART2 CSI20 IIC20 PORT 1 P10 to P178 PORT 2 P20 to P234 PORT 3 P30, P312 PORT 0 P00, P012 PORT 5 P50, P512 PORT 6 P60, P612 PORT 4 P40 P120 PORT 12 P121, P122 P137 PORT 13 P147PORT 14 A/D CONVERTER ANI16/P01, ANI17/P00 ANI18/P147, ANI19/P1204 AVREFP/P20 AVREFM/P21 POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL TOOL0/P40ON-CHIP DEBUG X2/EXCLK/P122 X1/P121 RESET ANO0/P22 D/A CONVERTERNote COMPARATORNote (2ch) COMPARATOR0 IVCMP0/P17 IVREF0/P16 VCOUT0/P120 COMPARATOR1 IVCMP1/P13 IVREF1/P12 VCOUT1/P147 TIMER RG TRGIOA/P50, TRGIOB/P512

2 TRGCLKA/P00,

MULTIPLIER & DIVIDER, MULITIPLY- ACCUMULATOR RL78 CPU CORE CODE FLASH MEMORY DATA FLASH MEMORY PCLBUZ0/P31, PCLBUZ1/P15 BCD ADJUSTMENT DATA TRANSFER CONTROL EVENT LINK CONTROLLER

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 22 of 97 Feb 21, 2012 1.5.2 32-pin products Note Mounted on the 96 KB or more code flash memory products. VOLTAGE REGULATOR REGC INTERRUPT CONTROL RAM SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR RxD0/P50 TxD0/P51 UART1 RxD1/P01 TxD1/P00 SCL00/P30 SDA00/P50 TI02/TO02/P17 TI03/TO03/P31 INTP0/P137 INTP3/P30, INTP4/P31 INTP1/P50, INTP2/P51 RxD0/P50 (LINSEL) VSS TOOLRxD/P50, TOOLTxD/P51 V DD SDAA0/P61 SCLA0/P60 SERIAL INTERFACE IICA0 INTP5/P16 RxD2/P14 TxD2/P13 SCL20/P15 SDA20/P14 SCK20/P15 SO20/P13 SI20/P14 TI01/TO01/P16 TRDIOA0/TRDCLK0/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 4TRDIOA1/P13 toTRDIOD1/P10 TIMER RJ TRJIO0/P01 TRJO0/P30 INTERVAL TIMER SSI00/P62 ch0 TIMER ARRAY UNIT (4ch) ch1 ch2 ch3 TIMER RD (2ch) ch0 ch1 WINDOW WATCHDOG TIMER REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) UART0 LINSEL CSI11 IIC00 IIC11 TO00/P01 RxD0/P50 (LINSEL) SERIAL ARRAY UNIT1 (2ch) UART2 CSI20 IIC20 PORT 1 P10 to P178 PORT 2 P20 to P234 PORT 3 P30, P312 PORT 0 P00, P012 PORT 5 P50, P512 PORT 6 P60 to P623 P120 PORT 12 P121, P122 P137 PORT 13 P147PORT 14 A/D CONVERTER ANI16/P01, ANI17/P00 ANI18/P147, ANI19/P1204 AVREFP/P20 AVREFM/P21 POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL TOOL0/P40ON-CHIP DEBUG X2/EXCLK/P122 X1/P121 RESET ANO0/P22 D/A CONVERTERNote COMPARATORNote (2ch) COMPARATOR0 IVCMP0/P17 IVREF0/P16 VCOUT0/P120 COMPARATOR1 IVCMP1/P13 IVREF1/P12 VCOUT1/P147 LOW-SPEED ON-CHIP OSCILLATOR TIMER RG TRGIOA/P50, TRGIOB/P512 MULTIPLIER & DIVIDER, MULITIPLY- ACCUMULATOR RL78 CPU CORE CODE FLASH MEMORY DATA FLASH MEMORY BUZZER OUTPUT CLOCK OUTPUT CONTROL PCLBUZ0/P31, PCLBUZ1/P15 BCD ADJUSTMENT DATA TRANSFER CONTROL EVENT LINK CONTROLLER

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 23 of 97 Feb 21, 2012 1.5.3 36-pin products Note Mounted on the 96 KB or more code flash memory products. VOLTAGE REGULATOR REGC INTERRUPT CONTROL RAM SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR RxD0/P50 TxD0/P51 UART1 RxD1/P01 TxD1/P00 SCL00/P30 SDA00/P50 TI02/TO02/P17 TI03/TO03/P31 INTP0/P137 INTP3/P30, INTP4/P31 INTP1/P50, INTP2/P51 RxD0/P50 (LINSEL)

6 ANI0/P20 to

VSS TOOLRxD/P50, TOOLTxD/P51 V DD SDAA0/P61 SCLA0/P60 SERIAL INTERFACE IICA0 INTP5/P16 RxD2/P14 TxD2/P13 TI01/TO01/P16 TRDIOA0/TRDCLK0/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 4TRDIOA1/P13 toTRDIOD1/P10 TIMER RJ TRJIO0/P01 TRJO0/P30 INTERVAL TIMER SSI00/P62 ch0 TIMER ARRAY UNIT (4ch) ch1 ch2 ch3 TIMER RD (2ch) ch0 ch1 WINDOW WATCHDOG TIMER REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) UART0 LINSEL CSI11 IIC00 IIC11 TO00/P01 RxD0/P50 (LINSEL) SERIAL ARRAY UNIT1 (2ch) UART2 PORT 1 P10 to P178 PORT 2 P20 to P256 PORT 3 P30, P312 PORT 0 P00, P012 PORT 5 P50, P512 PORT 6 P120 PORT 12 P121, P122 P137 PORT 13 P147PORT 14 A/D CONVERTER ANI18/P147, ANI19/P1202 AVREFP/P20 AVREFM/P21 POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL TOOL0/P40ON-CHIP DEBUG X2/EXCLK/P122 X1/P121 RESET ANO0/P22 D/A CONVERTERNote COMPARATORNote (2ch) COMPARATOR0 IVCMP0/P17 IVREF0/P16 VCOUT0/P120 COMPARATOR1 IVCMP1/P13 IVREF1/P12 VCOUT1/P147 LOW-SPEED ON-CHIP OSCILLATOR TIMER RG TRGIOA/P50, TRGIOB/P512 MULTIPLIER & DIVIDER, MULITIPLY- ACCUMULATOR RL78 CPU CORE CODE FLASH MEMORY DATA FLASH MEMORY BUZZER OUTPUT PCLBUZ0/P31, PCLBUZ1/P15CLOCK OUTPUT CONTROL BCD ADJUSTMENT DATA TRANSFER CONTROL EVENT LINK CONTROLLER

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 24 of 97 Feb 21, 2012 1.5.4 40-pin products Note Mounted on the 96 KB or more code flash memory products. VOLTAGE REGULATOR REGC INTERRUPT CONTROL RAM SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR RxD0/P50 TxD0/P51 UART1 RxD1/P01 TxD1/P00 SCL00/P30 SDA00/P50 TI02/TO02/P17 TI03/TO03/P31 INTP0/P137 INTP3/P30, INTP4/P31 INTP1/P50, INTP2/P51 RxD0/P50 (LINSEL) SCK11/P10 SO11/P12 SI11/P11 SCL11/P10 SDA11/P11 TI00/P00 CSI00 SCK00/P30 SO00/P51 SI00/P50 VSS TOOLRxD/P50, TOOLTxD/P51 VDD SDAA0/P61 SCLA0/P60 SERIAL INTERFACE IICA0 INTP5/P16 RxD2/P14 TxD2/P13 TI01/TO01/P16 TRDIOA0/TRDCLK0/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 4TRDIOA1/P13 toTRDIOD1/P10 TIMER RJ TRJIO0/P01 TRJO0/P30 INTERVAL TIMER SSI00/P62 ch0 TIMER ARRAY UNIT (4ch) ch1 ch2 ch3 TIMER RD (2ch) ch0 ch1 WINDOW WATCHDOG TIMER REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) UART0 LINSEL CSI11 IIC00 IIC11 TO00/P01 RxD0/P50 (LINSEL) SERIAL ARRAY UNIT1 (2ch) UART2 PORT 1 P10 to P178 PORT 2 P20 to P267 PORT 3 P30, P312 PORT 0 P00, P012 PORT 5 P50, P512 PORT 6 P120 PORT 12 P121 to P124 P137 PORT 13 P147PORT 14 POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL TOOL0/P40ON-CHIP DEBUG ANO0/P22 D/A CONVERTERNote COMPARATORNote (2ch) COMPARATOR0 IVCMP0/P17 IVREF0/P16 VCOUT0/P120 COMPARATOR1 IVCMP1/P13 IVREF1/P12 VCOUT1/P147 LOW-SPEED ON-CHIP OSCILLATOR TIMER RG TRGIOA/P50, TRGIOB/P512 A/D CONVERTER ANI18/P147, ANI19/P1202 AVREFP/P20 AVREFM/P21 KEY RETURN KR0/P70 to KR3/P73 X1/P121 RESET X2/EXCLK/P122 XT1/P123 XT2/EXCLKS/P124 MULTIPLIER & DIVIDER, MULITIPLY- ACCUMULATOR RL78 CPU CORE CODE FLASH MEMORY DATA FLASH MEMORY BUZZER OUTPUT PCLBUZ0/P31, PCLBUZ1/P15CLOCK OUTPUT CONTROL BCD ADJUSTMENT DATA TRANSFER CONTROL EVENT LINK CONTROLLER

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 25 of 97 Feb 21, 2012 1.5.5 44-pin products Note Mounted on the 96 KB or more code flash memory products. VOLTAGE REGULATOR REGC INTERRUPT CONTROL RAM SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR RxD0/P50 TxD0/P51 UART1 RxD1/P01 TxD1/P00 SCL00/P30 SDA00/P50 TI02/TO02/P17 TI03/TO03/P31 INTP0/P137 INTP3/P30, INTP4/P31 INTP1/P50, INTP2/P51 RxD0/P50 (LINSEL) SCK11/P10 SO11/P12 SI11/P11 SCL11/P10 SDA11/P11 TI00/P00 CSI00 SCK00/P30 SO00/P51 SI00/P50 VSS TOOLRxD/P50, TOOLTxD/P51 VDD SDAA0/P61 SCLA0/P60 SERIAL INTERFACE IICA0 INTP5/P16 RxD2/P14 TxD2/P13 TI01/TO01/P16 TRDIOA0/TRDCLK0/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 4TRDIOA1/P13 toTRDIOD1/P10 TIMER RJ TRJIO0/P01 TRJO0/P30 INTERVAL TIMER SSI00/P62 ch0 TIMER ARRAY UNIT (4ch) ch1 ch2 ch3 TIMER RD (2ch) ch0 ch1 WINDOW WATCHDOG TIMER REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) UART0 LINSEL CSI11 IIC00 IIC11 TO00/P01 RxD0/P50 (LINSEL) SERIAL ARRAY UNIT1 (2ch) UART2 PORT 1 P10 to P178 PORT 2 P20 to P278 PORT 3 P30, P312 PORT 0 P00, P012 PORT 5 P50, P512 PORT 6 P120 PORT 12 P121 to P124 P137 PORT 13 PORT 14 POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL TOOL0/P40ON-CHIP DEBUG ANO0/P22 D/A CONVERTERNote COMPARATORNote (2ch) COMPARATOR0 IVCMP0/P17 IVREF0/P16 VCOUT0/P120 COMPARATOR1 IVCMP1/P13 IVREF1/P12 VCOUT1/P147 LOW-SPEED ON-CHIP OSCILLATOR TIMER RG TRGIOA/P50, TRGIOB/P512 PORT 4 P40, P41 PORT 7 P70 to P73 P60 to P634 SCK20/P15 SO20/P13 SI20/P14 CSI20 SCL20/P15 SDA20/P14 IIC20 SCK21/P70 SO21/P72 SI21/P71 CSI21 SCL21/P70 SDA21/P71 IIC21 RTC1HZ/P30 8 ANI0/P20 to ANI7/P27 A/D CONVERTER ANI18/P147, ANI19/P1202 AVREFP/P20 AVREFM/P21 KEY RETURN KR0/P70 to KR3/P73 X1/P121 RESET X2/EXCLK/P122 XT1/P123 XT2/EXCLKS/P124 P146, P1472 MULTIPLIER & DIVIDER, MULITIPLY- ACCUMULATOR RL78 CPU CORE CODE FLASH MEMORY DATA FLASH MEMORY BUZZER OUTPUT PCLBUZ0/P31, PCLBUZ1/P15CLOCK OUTPUT CONTROL BCD ADJUSTMENT DATA TRANSFER CONTROL EVENT LINK CONTROLLER

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 26 of 97 Feb 21, 2012 1.5.6 48-pin products Note Mounted on the 96 KB or more code flash memory products. VOLTAGE REGULATOR REGC INTERRUPT CONTROL RAM SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR RxD0/P50 TxD0/P51 UART1 RxD1/P01 TxD1/P00 TI02/TO02/P17 TI03/TO03/P31 TI00/P00 CSI00 SCK00/P30 SO00/P51 SI00/P50 VSS TOOLRxD/P50, TOOLTxD/P51 VDD SDAA0/P61 SCLA0/P60 SERIAL INTERFACE IICA0 TI01/TO01/P16 TRDIOA0/TRDCLK0/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 4TRDIOA1/P13 toTRDIOD1/P10 TIMER RJ TRJIO0/P01 TRJO0/P30 INTERVAL TIMER SSI00/P62 ch0 TIMER ARRAY UNIT (4ch) ch1 ch2 ch3 TIMER RD (2ch) ch0 ch1 WINDOW WATCHDOG TIMER REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) UART0 LINSEL TO00/P01 RxD0/P50 (LINSEL) PORT 1 P10 to P178 PORT 2 P20 to P278 PORT 3 P30, P312 PORT 0 P00, P012 PORT 5 P50, P512 PORT 6 P120 PORT 12 P121 to P124 P137 PORT 13 PORT 14 POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL TOOL0/P40ON-CHIP DEBUG ANO0/P22 D/A CONVERTERNote COMPARATORNote (2ch) COMPARATOR0 IVCMP0/P17 IVREF0/P16 VCOUT0/P120 COMPARATOR1 IVCMP1/P13 IVREF1/P12 VCOUT1/P147 LOW-SPEED ON-CHIP OSCILLATOR TIMER RG TRGIOA/P50, TRGIOB/P512 PORT 4 P40, P41 PORT 7 P70 to P75 P60 to P634 RTC1HZ/P30 8 ANI0/P20 to ANI7/P27 A/D CONVERTER ANI18/P147, ANI19/P1202 AVREFP/P20 AVREFM/P21 X1/P121 RESET X2/EXCLK/P122 XT1/P123 XT2/EXCLKS/P124 P140, P146, P147 SCL00/P30 SDA00/P50 IIC00 SCL01/P75 SDA01/P74 IIC01 SCL11/P10 SDA11/P11 IIC11 SCK11/P10 SO11/P12 SI11/P11 CSI11 SCK01/P75 SO01/P73 SI01/P74 CSI01 RxD2/P14 TxD2/P13 SERIAL ARRAY UNIT1 (2ch) UART2 SCK20/P15 SO20/P13 SI20/P14 CSI20 SCL20/P15 SDA20/P14 IIC20 SCK21/P70 SO21/P72 SI21/P71 CSI21 SCL21/P70 SDA21/P71 IIC21 P130 KEY RETURN KR0/P70 to KR5/P75 INTP0/P137 INTP3/P30, INTP4/P31 INTP1/P50, INTP2/P51 RxD0/P50 (LINSEL) INTP5/P16 INTP6/P140

2 INTP8/P74,

MULTIPLIER & DIVIDER, MULITIPLY- ACCUMULATOR RL78 CPU CORE CODE FLASH MEMORY DATA FLASH MEMORY BUZZER OUTPUT PCLBUZ0/P140, PCLBUZ1/P15CLOCK OUTPUT CONTROL BCD ADJUSTMENT DATA TRANSFER CONTROL EVENT LINK CONTROLLER

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 27 of 97 Feb 21, 2012 1.5.7 52-pin products Note Mounted on the 96 KB or more code flash memory products. VOLTAGE REGULATOR REGC INTERRUPT CONTROL RAM SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR RxD0/P50 TxD0/P51 UART1 RxD1/P03 TxD1/P02 TI02/TO02/P17 TI03/TO03/P31 TI00/P00 CSI00 SCK00/P30 SO00/P51 SI00/P50 VSS TOOLRxD/P50, TOOLTxD/P51 VDD SDAA0/P61 SCLA0/P60 SERIAL INTERFACE IICA0 TI01/TO01/P16 TRDIOA0/TRDCLK0/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 4TRDIOA1/P13 toTRDIOD1/P10 TIMER RJ TRJIO0/P01 TRJO0/P30 INTERVAL TIMER SSI00/P62 ch0 TIMER ARRAY UNIT (4ch) ch1 ch2 ch3 TIMER RD (2ch) ch0 ch1 WINDOW WATCHDOG TIMER REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) UART0 LINSEL TO00/P01 RxD0/P50 (LINSEL) PORT 1 P10 to P178 PORT 2 P20 to P278 PORT 3 P30, P312 PORT 0 P00 to P034 PORT 5 P50, P512 PORT 6 P120 PORT 12 P121 to P124 P137 PORT 13 PORT 14 POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL TOOL0/P40ON-CHIP DEBUG ANO0/P22 D/A CONVERTERNote COMPARATORNote (2ch) COMPARATOR0 IVCMP0/P17 IVREF0/P16 VCOUT0/P120 COMPARATOR1 IVCMP1/P13 IVREF1/P12 VCOUT1/P147 LOW-SPEED ON-CHIP OSCILLATOR TIMER RG TRGIOA/P50, TRGIOB/P512 PORT 4 P40, P41 PORT 7 P70 to P77 P60 to P634 RTC1HZ/P30 8 ANI0/P20 to ANI7/P27 A/D CONVERTER ANI16/P03, ANI17/P02, ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21 X1/P121 RESET X2/EXCLK/P122 XT1/P123 XT2/EXCLKS/P124 P140, P146, P147 SCL00/P30 SDA00/P50 IIC00 SCL01/P75 SDA01/P74 IIC01 SCL11/P10 SDA11/P11 IIC11 SCK11/P10 SO11/P12 SI11/P11 CSI11 SCK01/P75 SO01/P73 SI01/P74 CSI01 RxD2/P14 TxD2/P13 SERIAL ARRAY UNIT1 (2ch) UART2 SCK20/P15 SO20/P13 SI20/P14 CSI20 SCL20/P15 SDA20/P14 IIC20 SCK21/P70 SO21/P72 SI21/P71 CSI21 SCL21/P70 SDA21/P71 IIC21 P130 KEY RETURN KR0/P70 to KR7/P77 INTP0/P137 INTP3/P30, INTP4/P31 INTP1/P50, INTP2/P51 RxD0/P50 (LINSEL) INTP5/P16 INTP6/P140

4 INTP8/P74 to

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 28 of 97 Feb 21, 2012 1.5.8 64-pin products Note Mounted on the 96 KB or more code flash memory products. VOLTAGE REGULATOR REGC INTERRUPT CONTROL RAM SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR RxD0/P50 TxD0/P51 UART1 RxD1/P03 TxD1/P02 TI02/TO02/P17 TI03/TO03/P31 TI00/P00 CSI00 SCK00/P30 SO00/P51 SI00/P50 TI01/TO01/P16 TRDIOA0/TRDCLK0/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 4TRDIOA1/P13 toTRDIOD1/P10 TIMER RJ TRJIO0/P01 TRJO0/P30 INTERVAL TIMER SSI00/P62 ch0 TIMER ARRAY UNIT (4ch) ch1 ch2 ch3 TIMER RD (2ch) ch0 ch1 WINDOW WATCHDOG TIMER REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) UART0 LINSEL TO00/P01 RxD0/P50 (LINSEL) PORT 1 P10 to P178 PORT 2 P20 to P278 PORT 3 P30, P312 PORT 0 P00 to P067 PORT 5 P50 to P556 PORT 6 P120 PORT 12 P121 to P124 P137 PORT 13 PORT 14 POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL TOOL0/P40ON-CHIP DEBUG ANO0/P22 D/A CONVERTERNote COMPARATORNote (2ch) COMPARATOR0 IVCMP0/P17 IVREF0/P16 VCOUT0/P120 COMPARATOR1 IVCMP1/P13 IVREF1/P12 VCOUT1/P147 LOW-SPEED ON-CHIP OSCILLATOR TIMER RG TRGIOA/P50, TRGIOB/P512 A/D CONVERTER ANI16/P03, ANI17/P02, ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21 X1/P121 RESET X2/EXCLK/P122 XT1/P123 XT2/EXCLKS/P124 P140, P141, P146, P147 SCL00/P30 SDA00/P50 IIC00 SCL01/P75 SDA01/P74 IIC01 SCL11/P10 SDA11/P11 IIC11 SCK11/P10 SO11/P12 SI11/P11 CSI11 SCK01/P75 SO01/P73 SI01/P74 CSI01 RxD2/P14 TxD2/P13 SERIAL ARRAY UNIT1 (2ch) UART2 SCK20/P15 SO20/P13 SI20/P14 CSI20 SCL20/P15 SDA20/P14 IIC20 SCK21/P70 SO21/P72 SI21/P71 CSI21 SCL21/P70 SDA21/P71 IIC21 P130 KEY RETURN KR0/P70 to KR7/P77 INTP0/P137 INTP3/P30, INTP4/P31 INTP1/P50, INTP2/P51 RxD0/P50 (LINSEL) INTP5/P16 INTP6/P140, INTP7/P141 /P04 SO10/P02 SI10/P03 CSI10 SCL10/P04 SDA10/P03 IIC10 SDAA0/P61 SCLA0/P60 SERIAL INTERFACE IICA0 VDD, EVDD0 VSS, EVSS0 TOOLRxD/P50, TOOLTxD/P51 MULTIPLIER & DIVIDER, MULITIPLY- ACCUMULATOR RL78 CPU CORE CODE FLASH MEMORY DATA FLASH MEMORY BUZZER OUTPUT PCLBUZ0/P140, PCLBUZ1/P141CLOCK OUTPUT CONTROL BCD ADJUSTMENT DATA TRANSFER CONTROL EVENT LINK CONTROLLER

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 29 of 97 Feb 21, 2012 1.5.9 80-pin products VOLTAGE REGULATOR REGC INTERRUPT CONTROL RAM SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR RxD0/P50 TxD0/P51 UART1 RxD1/P03 TxD1/P02 TI02/TO02/P17 TI03/TO03/P31 TI00/P00 CSI00 SCK00/P30 SO00/P51 SI00/P50 TI01/TO01/P16 TRDIOA0/TRDCLK0/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 4TRDIOA1/P13 toTRDIOD1/P10 SSI00/P62 TIMER RD (2ch) ch0 ch1 WINDOW WATCHDOG TIMER REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) UART0 LINSEL TO00/P01 RxD0/P50 (LINSEL) PORT 1 P10 to P178 PORT 2 P20 to P278 PORT 3 P30, P312 PORT 0 P00 to P067 PORT 5 P50 to P556 PORT 6 P120 PORT 12 P121 to P124 P137 PORT 13 POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL TOOL0/P40ON-CHIP DEBUG ANO0/P22 D/A CONVERTER COMPARATOR (2ch) COMPARATOR0 IVCMP0/P17 IVREF0/P16 VCOUT0/P120 COMPARATOR1 IVCMP1/P13 IVREF1/P12 VCOUT1/P147 LOW-SPEED ON-CHIP OSCILLATOR 4 ANO1/P23 PORT 4 P40 to P45 P60 to P678 RTC1HZ/P30 X1/P121 RESET X2/EXCLK/P122 XT1/P123 XT2/EXCLKS/P124 SCL00/P30 SDA00/P50 IIC00 SCL01/P43 SDA01/P44 IIC01 SCL11/P10 SDA11/P11 IIC11 SCK11/P10 SO11/P12 SI11/P11 CSI11 SCK01/P43 SO01/P45 SI01/P44 CSI01 SERIAL ARRAY UNIT1 (4ch) P130 INTP0/P137 INTP3/P30, INTP4/P31 INTP1/P50, INTP2/P51 RxD0/P50 (LINSEL) INTP5/P16 INTP6/P140, INTP7/P141 /P04 SO10/P02 SI10/P03 CSI10 SCL10/P04 SDA10/P03 IIC10 VDD, EVDD0 VSS, EVSS0 TOOLRxD/P50, TOOLTxD/P51 RxD2/P14 TxD2/P13 UART2 RxD3/P143 TxD3/P144 UART3 SCK20/P15 SO20/P13 SI20/P14 CSI20 SCL20/P15 SDA20/P14 IIC20 SCL21/P70 SDA21/P71 IIC21 SCK21/P70 SO21/P72 SI21/P71 CSI21 SCK30/P142 SO30/P144 SI30/P143 CSI30 SCK31/P54 SO31/P52 SI31/P53 CSI31 SCL30/P142 SDA30/P143 IIC30 SCL31/P54 SDA31/P53 IIC31 ch0 TIMER ARRAY UNIT0 (4ch) ch1 ch2 ch3 ch0 TIMER ARRAY UNIT1 (4ch) ch1 ch2 ch3 TI10/TO10/P64 TI11/TO11/P65 TI12/TO12/P66 TI13/TO13/P67 A/D CONVERTER AVREFP/P20 AVREFM/P21

8 ANI0/P20 to ANI7/P27

ANI16/P03, ANI17/P02, ANI18/P147, ANI19/P120, ANI20/P100 INTERVAL TIMER TIMER RJ TRJIO0/P01 TRJO0/P30 TIMER RG TRGIOA/P50, TRGIOB/P512 PCLBUZ0/P140, PCLBUZ1/P141CLOCK OUTPUT CONTROL SDAA0/P61 SCLA0/P60 SERIAL INTERFACE IICA0 SDAA1/P63 SCLA1/P62 SERIAL INTERFACE IICA1 PORT 7 P70 to P778 PORT 10 P100 PORT 11 P110, P1112 PORT 14 P140 to P144, P146, P1477 PORT 15 P150 to P1534 KEY RETURN KR0/P70 to KR7/P77 MULTIPLIER & DIVIDER, MULITIPLY- ACCUMULATOR RL78 CPU CORE CODE FLASH MEMORY DATA FLASH MEMORY BCD ADJUSTMENT DATA TRANSFER CONTROL EVENT LINK CONTROLLER

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 30 of 97 Feb 21, 2012 1.5.10 100-pin products RAM RxD0/P50 TxD0/P51 UART1 RxD1/P03 TxD1/P02 TI02/TO02/P17 TI03/TO03/P31 TI00/P00 CSI00 SCK00/P30 SO00/P51 SI00/P50 TI01/TO01/P16 TRDIOA0/TRDCLK0/P17 TRDIOB0/P15, TRDIOC0/P16, TRDIOD0/P14 4TRDIOA1/P13 toTRDIOD1/P10 SSI00/P62 TIMER RD (2ch) ch0 ch1 WINDOW WATCHDOG TIMER REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) UART0 LINSEL TO00/P01 RxD0/P50 (LINSEL) PORT 1 P10 to P178 PORT 2 P20 to P278 PORT 3 P30, P312 PORT 0 P00 to P067 PORT 5 P50 to P578 PORT 6 LOW-SPEED ON-CHIP OSCILLATOR PORT 4 P40 to P47 P60 to P678 RTC1HZ/P30 SCL00/P30 SDA00/P50 IIC00 SCL01/P43 SDA01/P44 IIC01 SCL11/P10 SDA11/P11 IIC11 SCK11/P10 SO11/P12 SI11/P11 CSI11 SCK01/P43 SO01/P45 SI01/P44 CSI01 SERIAL ARRAY UNIT1 (4ch) SCK10/P04 SO10/P02 SI10/P03 CSI10 SCL10/P04 SDA10/P03 IIC10 TOOLRxD/P50, TOOLTxD/P51 RxD2/P14 TxD2/P13 UART2 RxD3/P143 TxD3/P144 UART3 SCK20/P15 SO20/P13 SI20/P14 CSI20 SCL20/P15 SDA20/P14 IIC20 SCL21/P70 SDA21/P71 IIC21 SCK21/P70 SO21/P72 SI21/P71 CSI21 SCK30/P142 SO30/P144 SI30/P143 CSI30 SCK31/P54 SO31/P52 SI31/P53 CSI31 SCL30/P142 SDA30/P143 IIC30 SCL31/P54 SDA31/P53 IIC31 ch0 TIMER ARRAY UNIT0 (4ch) ch1 ch2 ch3 ch0 TIMER ARRAY UNIT1 (4ch) ch1 ch2 ch3 TI10/TO10/P64 TI11/TO11/P65 TI12/TO12/P66 TI13/TO13/P67 A/D CONVERTER AVREFP/P20 AVREFM/P21 ANI16/P03, ANI17/P02, ANI18/P147, ANI19/P120, ANI20/P100 INTERVAL TIMER TIMER RJ TRJIO0/P01 TRJO0/P30 TIMER RG TRGIOA/P50, TRGIOB/P512 PCLBUZ0/P140, PCLBUZ1/P141CLOCK OUTPUT CONTROL SDAA0/P61 SCLA0/P60 SERIAL INTERFACE IICA0 SDAA1/P63 SCLA1/P62 SERIAL INTERFACE IICA1 VSS, EVSS0, EVSS1 VDD, EVDD0, EVDD1 VOLTAGE REGULATOR REGC INTERRUPT CONTROL SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR P120 PORT 12 P121 to P124 P137 PORT 13 POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL TOOL0/P40ON-CHIP DEBUG ANO0/P22 D/A CONVERTER COMPARATOR (2ch) COMPARATOR0 IVCMP0/P17 IVREF0/P16 VCOUT0/P120 COMPARATOR1 IVCMP1/P13 IVREF1/P12 VCOUT1/P147 ANO1/P23 X1/P121 RESET X2/EXCLK/P122 XT1/P123 XT2/EXCLKS/P124 P130 INTP0/P137 INTP3/P30, INTP4/P31 INTP1/P47, INTP2/P46 RxD0/P50 (LINSEL) INTP5/P16 INTP6/P140, INTP7/P141 PORT 11 P110, P1112 PORT 14 P140 to P1478 PORT 15 P150 to P1567 KEY RETURN KR0/P70 to KR7/P77 PORT 7 P70 to P778 PORT 8 P80 to P878 MULTIPLIER & DIVIDER, MULITIPLY- ACCUMULATOR RL78 CPU CORE CODE FLASH MEMORY DATA FLASH MEMORY BCD ADJUSTMENT DATA TRANSFER CONTROL EVENT LINK CONTROLLER

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 31 of 97 Feb 21, 2012

1.6 Outline of Functions

[30-pin, 32-pin, 36-pin, 40-pin products (code flash memory 16 KB to 64 KB)] Caution This outline describes the fu nctions at the time when Peripheral I/O redirection register 0, 1 (PIOR0, 1) are set to 00H. (1/2) Note In the case of the 5.5 KB, this is about 4.5 KB when the self-programming function and data flash function are used. Item 30-pin 32-pin 36-pin 40-pin R5F104Ax (x = A, C to E) R5F104Bx (x = A, C to E) R5F104Cx (x = A, C to E) R5F104Ex (x = A, C to E) Code flash memory (KB) 16 to 64 16 to 64 16 to 64 16 to 64 D a t a f l a s h m e m o r y ( K B ) 4444 Memory space 1 MB Main system clock High-speed system clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) 1 to 20 MHz: V High-speed on-chip oscillator clock (f IH) High-speed operation: 1 to 32 MHz (VDD = 2.7 to 5.5 V), High-speed operation: 1 to 16 MHz (VDD = 2.4 to 5.5 V), Low-speed operation: 1 to 8 MHz (VDD = 1.8 to 5.5 V), Low-voltage operation: 1 to 4 MHz (VDD = 1.6 to 5.5 V) Subsystem clock — XT1 (crystal) oscillation 32.768 kHz (TYP.): V DD = 1.6 to 5.5 V Low-speed on-chip oscillator clock 15 kHz (TYP.): V DD = 1.6 to 5.5 V General-purpose register 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Minimum instruction execution time 0.03125 s (High-speed on-chip oscillator clock: fIH = 32 MHz operation) 0.05 s (High-speed system clock: fMX = 20 MHz operation) — 30.5 s (Subsystem clock: fSUB = 32.768 kHz operation) Instruction set • Data transfer (8/16 bits)

Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits, 16 bits × 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
Multiplication and Accumulation (16 bits × 16 bits + 32 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. I/O port Total 26 28 32 36 CMOS I/O 21 22 26 28 C M O S i n p u t3335 C M O S o u t p u t ———— N-ch open-drain I/O (6 V tolerance) 2333 Timer 16-bit timer 8 channels (TAU: 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1 channel) Watchdog timer 1 channel Real-time clock (RTC) 1 channel 12-bit interval timer 1 channel Timer output 16 (TAU: 4, Timer RJ: 2, Timer RD: 8, Timer RG: 2) PWM outputs: 10 (TAU: 3, Timer RD: 6, Timer RG: 1) RTC output —
1 H z (subsystem clock: fSUB = 32.768 kHz)

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 32 of 97 Feb 21, 2012 (2/2) Note The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction executi on not is issued by emulation with t he in-circuit emulator or on-chip debug emulator. Item 30-pin 32-pin 36-pin 40-pin R5F104Ax (x = A, C to E) R5F104Bx (x = A, C to E) R5F104Cx (x = A, C to E) R5F104Ex (x = A, C to E) C l o c k o u t p u t / b u z z e r o u t p u t 2222 [30-pin, 32-pin, 36-pin products] (Main system clock: fMAIN = 20 MHz operation) [40-pin products] (Main system clock: f MAIN = 20 MHz operation) (Subsystem clock: fSUB = 32.768 kHz operation) 8/10-bit resolution A/D converter 8 channels 8 channels 8 channels 9 channels Serial interface [30-pin, 32-pin products]

CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel
CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel [36-pin, 40-pin products]
CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel
CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels I2C bus 1 channel 1 channel 1 channel 1 channel Data transfer controller (DTC) 28 sources 29 sources Event link controller (ELC) Event input: 20 Event trigger output: 7 Vectored interrupt sources Internal 24 24 24 24 External 6667 Key interrupt ——— 4 Reset • Reset by RESET pin
Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detector
Internal reset by illegal instruction execution Note
Internal reset by RAM parity error
Internal reset by illegal-memory access Power-on-reset circuit • Power-on-reset: 1.51 ±0.03 V
Power-down-reset: 1.50 ±0.03 V Voltage detector 1.63 V to 4.06 V (14 stages) On-chip debug function Provided Power supply voltage V DD = 1.6 to 5.5 V Operating ambient temperature T A = 40 to +85 °C

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 33 of 97 Feb 21, 2012 [30-pin, 32-pin, 36-pin, 40-pin products (code flash memory 96 KB to 256 KB)] Caution This outline describes the fu nctions at the time when Peripheral I/O redirection register 0, 1 (PIOR0, 1) are set to 00H. (1/2) Item 30-pin 32-pin 36-pin 40-pin R5F104Ax (x = F, G) R5F104Bx (x = F, G) R5F104Cx (x = F, G) R5F104Ex (x = F to H) Code flash memory (KB) 96 to 128 96 to 128 96 to 128 96 to 192 D a t a f l a s h m e m o r y ( K B ) 8888 RAM (KB) 12 to 16 12 to 16 12 to 16 12 to 20 Memory space 1 MB Main system clock High-speed system clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) 1 to 20 MHz: V High-speed on-chip oscillator clock (f IH) High-speed operation: 1 to 32 MHz (VDD = 2.7 to 5.5 V), High-speed operation: 1 to 16 MHz (VDD = 2.4 to 5.5 V), Low-speed operation: 1 to 8 MHz (VDD = 1.8 to 5.5 V), Low-voltage operation: 1 to 4 MHz (VDD = 1.6 to 5.5 V) Subsystem clock — XT1 (crystal) oscillation 32.768 kHz (TYP.): V DD = 1.6 to 5.5 V Low-speed on-chip oscillator clock 15 kHz (TYP.): V DD = 1.6 to 5.5 V General-purpose register 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Minimum instruction execution time 0.03125 s (High-speed on-chip oscillator clock: fIH = 32 MHz operation) 0.05 s (High-speed system clock: fMX = 20 MHz operation) — 30.5 s (Subsystem clock: fSUB = 32.768 kHz operation) Instruction set • Data transfer (8/16 bits)

Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits, 16 bits × 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
Multiplication and Accumulation (16 bits × 16 bits + 32 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. I/O port Total 26 28 32 36 CMOS I/O 21 22 26 28 C M O S i n p u t3335 C M O S o u t p u t ———— N-ch open-drain I/O (6 V tolerance) 2333 Timer 16-bit timer 8 channels (TAU: 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1 channel) Watchdog timer 1 channel Real-time clock (RTC) 1 channel 12-bit interval timer 1 channel Timer output 16 (TAU: 4, Timer RJ: 2, Timer RD: 8, Timer RG: 2) PWM outputs: 10 (TAU: 3, Timer RD: 6, Timer RG: 1) RTC output — 1
1 H z (subsystem clock: f SUB = 32.768 kHz)

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 34 of 97 Feb 21, 2012 (2/2) Note The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction executi on not is issued by emulation with t he in-circuit emulator or on-chip debug emulator. Item 30-pin 32-pin 36-pin 40-pin R5F104Ax (x = F, G) R5F104Bx (x = F, G) R5F104Cx (x = F, G) R5F104Ex (x = F to H) Clock output/buzzer output 2222 [30-pin, 32-pin, 36-pin products] (Main system clock: fMAIN = 20 MHz operation) [40-pin products] (Main system clock: fMAIN = 20 MHz operation) (Subsystem clock: fSUB = 32.768 kHz operation) 8/10-bit resolution A/D converter 8 channels 8 channels 8 channels 9 channels D/A converter 1 channel 2 channels Comparator 2 channels Serial interface [30-pin, 32-pin products]

CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel
CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel [36-pin, 40-pin products]
CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel
CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels I2C bus 1 channel 1 channel 1 channel 1 channel Data transfer controller (DTC) 28 sources 29 sources Event link controller (ELC) Event input: 20 Event trigger output: 7 Vectored interrupt sources Internal 24 24 24 24 External 6667 Key interrupt ——— 4 Reset • Reset by RESET pin
Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detector
Internal reset by illegal instruction execution Note
Internal reset by RAM parity error
Internal reset by illegal-memory access Power-on-reset circuit • Power-on-reset: 1.51 ±0.03 V
Power-down-reset: 1.50 ±0.03 V Voltage detector 1.63 V to 4.06 V (14 stages) On-chip debug function Provided Power supply voltage V DD = 1.6 to 5.5 V Operating ambient temperature T A = 40 to +85 °C

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 35 of 97 Feb 21, 2012 [44-pin, 48-pin, 52-pin, 64-pin products (code flash memory 16 KB to 64 KB)] Caution This outline describes the fu nctions at the time when Peripheral I/O redirection register 0, 1 (PIOR0, 1) are set to 00H. (1/2) Note In the case of the 5.5 KB, this is about 4.5 KB when the self-programming function and data flash function are used. Item 44-pin 48-pin 52-pin 64-pin R5F104Fx (x = A, C to E) R5F104Gx (x = A, C to E) R5F104Jx (x = C to E) R5F104Lx (x = C to E) Code flash memory (KB) 16 to 64 16 to 64 32 to 64 32 to 64 Data flash memory (KB) 4 4 4 4 RAM (KB) 2.5 to 5.5 Note 2.5 to 5.5 Note 4 to 5.5 Note 4 to 5.5 Note Memory space 1 MB Main system clock High-speed system clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) High-speed on-chip oscillator clock (f IH) High-speed operation: 1 to 32 MHz (VDD = 2.7 to 5.5 V), High-speed operation: 1 to 16 MHz (VDD = 2.4 to 5.5 V), Low-speed operation: 1 to 8 MHz (VDD = 1.8 to 5.5 V), Low-voltage operation: 1 to 4 MHz (VDD = 1.6 to 5.5 V) Subsystem clock XT1 (crystal) oscillation 32.768 kHz (TYP .): VDD = 1.6 to 5.5 V Low-speed on-chip oscillator clock 15 kHz (TYP.): V DD = 1.6 to 5.5 V General-purpose register 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Minimum instruction execution time 0.03125 s (High-speed on-chip oscillator clock: fIH = 32 MHz operation) 0.05 s (High-speed system clock: fMX = 20 MHz operation) 30.5 s (Subsystem clock: fSUB = 32.768 kHz operation) Instruction set • Data transfer (8/16 bits)

Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits, 16 bits × 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
Multiplication and Accumulation (16 bits × 16 bits + 32 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. I/O port Total 4 04 44 85 8 CMOS I/O 31 34 38 48 CMOS input 5 5 5 5 CMOS output — 1 1 1 N-ch open-drain I/O (6 V tolerance) 4444 Timer 16-bit timer 8 channels (TAU: 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1 channel) Watchdog timer 1 channel Real-time clock (RTC) 1 channel 12-bit interval timer 1 channel Timer output 16 (TAU: 4, Timer RJ: 2, Timer RD: 8, Timer RG: 2) PWM outputs: 10 (TAU: 3, Timer RD: 6, Timer RG: 1) RTC output 1
1 Hz (subsystem clock: f SUB = 32.768 kHz)

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 36 of 97 Feb 21, 2012 (2/2) Note The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution is not issued by emulation with t he in-circuit emulator or on-chip debug emulator. Item 44-pin 48-pin 52-pin 64-pin R5F104Fx (x = A, C to E) R5F104Gx (x = A, C to E) R5F104Jx (x = C to E) R5F104Lx (x = C to E) Clock output/buzzer output 2 2 2 2 (Main system clock: fMAIN = 20 MHz operation) (Subsystem clock: fSUB = 32.768 kHz operation) 8/10-bit resolution A/D converter 10 channels 10 channels 12 channels 12 channels Serial interface [44-pin products]

CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel
CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels [48-pin, 52-pin products]
CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 2 channels
CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels [64-pin products]
CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 2 channels
CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels I2C bus 1 channel 1 channel 1 channel 1 channel Data transfer controller (DTC) 29 sources 30 sources 31 sources Event link controller (ELC) Event input: 20 Event trigger output: 7 Vectored interrupt sources Internal 24 24 24 24 External 7 1 01 21 3 Key interrupt 4 6 8 8 Reset • Reset by RESET pin
Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detector
Internal reset by illegal instruction execution Note
Internal reset by RAM parity error
Internal reset by illegal-memory access Power-on-reset circuit • Power-on-reset: 1.51 ±0.03 V
Power-down-reset: 1.50 ±0.03 V Voltage detector 1.63 V to 4.06 V (14 stages) On-chip debug function Provided Power supply voltage VDD = 1.6 to 5.5 V Operating ambient temperature T A = 40 to +85 °C

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 37 of 97 Feb 21, 2012 [44-pin, 48-pin, 52-pin, 64-pin products (code flash memory 96 KB to 256 KB)] Caution This outline describes the fu nctions at the time when Peripheral I/O redirection register 0, 1 (PIOR0, 1) are set to 00H. (1/2) Note In the case of the 24 KB, this is about 23 KB when the self-programming function and data flash function are used. Item 44-pin 48-pin 52-pin 64-pin R5F104Fx (x = F to H, J) R5F104Gx (x = F to H, J) R5F104Jx (x = F to H, J) R5F104Lx (x = F to H, J) Code flash memory (KB) 96 to 256 96 to 256 96 to 256 96 to 256 Data flash memory (KB) 8 8 8 8 RAM (KB) 12 to 24 Note 12 to 24 Note 12 to 24 Note 12 to 24 Note Memory space 1 MB Main system clock High-speed system clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) High-speed on-chip oscillator clock (f IH) High-speed operation: 1 to 32 MHz (VDD = 2.7 to 5.5 V), High-speed operation: 1 to 16 MHz (VDD = 2.4 to 5.5 V), Low-speed operation: 1 to 8 MHz (VDD = 1.8 to 5.5 V), Low-voltage operation: 1 to 4 MHz (VDD = 1.6 to 5.5 V) Subsystem clock XT1 (crystal) oscillation 32.768 kHz (TYP .): VDD = 1.6 to 5.5 V Low-speed on-chip oscillator clock 15 kHz (TYP.): V DD = 1.6 to 5.5 V General-purpose register 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Minimum instruction execution time 0.03125 s (High-speed on-chip oscillator clock: fIH = 32 MHz operation) 0.05 s (High-speed system clock: fMX = 20 MHz operation) 30.5 s (Subsystem clock: fSUB = 32.768 kHz operation) Instruction set • Data transfer (8/16 bits)

Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits, 16 bits × 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
Multiplication and Accumulation (16 bits × 16 bits + 32 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. I/O port Total 4 04 44 85 8 CMOS I/O 31 34 38 48 CMOS input 5 5 5 5 CMOS output — 1 1 1 N-ch open-drain I/O (6 V tolerance) 4444 Timer 16-bit timer 8 channels (TAU: 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1 channel) Watchdog timer 1 channel Real-time clock (RTC) 1 channel 12-bit interval timer 1 channel Timer output 16 (TAU: 4, Timer RJ: 2, Timer RD: 8, Timer RG: 2) PWM outputs: 10 (TAU: 3, Timer RD: 6, Timer RG: 1) RTC output 1
1 Hz (subsystem clock: f SUB = 32.768 kHz)

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 38 of 97 Feb 21, 2012 (2/2) Note The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution is not issued by emulation with t he in-circuit emulator or on-chip debug emulator. Item 44-pin 48-pin 52-pin 64-pin R5F104Fx (x = F to H, J) R5F104Gx (x = F to H, J) R5F104Jx (x = F to H, J) R5F104Lx (x = F to H, J) Clock output/buzzer output 2 2 2 2 (Main system clock: fMAIN = 20 MHz operation) (Subsystem clock: fSUB = 32.768 kHz operation) 8/10-bit resolution A/D converter 10 channels 10 channels 12 channels 12 channels D/A converter 2 channels Comparator 2 channels Serial interface [44-pin products]

CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel
CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels [48-pin, 52-pin products]
CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 2 channels
CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels [64-pin products]
CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 2 channels
CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels I2C bus 1 channel 1 channel 1 channel 1 channel Data transfer controller (DTC) 29 sources 30 sources 31 sources Event link controller (ELC) Event input: 20 Event trigger output: 7 Vectored interrupt sources Internal 24 24 24 24 External 7 1 01 21 3 Key interrupt 4 6 8 8 Reset • Reset by RESET pin
Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detector
Internal reset by illegal instruction execution Note
Internal reset by RAM parity error
Internal reset by illegal-memory access Power-on-reset circuit • Power-on-reset: 1.51 ±0.03 V
Power-down-reset: 1.50 ±0.03 V Voltage detector 1.63 V to 4.06 V (14 stages) On-chip debug function Provided Power supply voltage VDD = 1.6 to 5.5 V Operating ambient temperature T A = 40 to +85 °C

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 39 of 97 Feb 21, 2012 [80-pin, 100-pin products (code flash memory 96 KB to 256 KB)] Caution This outline describes the fu nctions at the time when Peripheral I/O redirection register 0, 1 (PIOR0, 1) are set to 00H. (1/2) Note In the case of the 24 KB, this is about 23 KB when the self-programming function and data flash function are used. Item 80-pin 100-pin R5F104Mx (x = F to H, J) R5F104Px (x = F to H, J) Code flash memory (KB) 96 to 256 96 to 256 Data flash memory (KB) 8 8 RAM (KB) 12 to 24 Note 12 to 24 Note Memory space 1 MB Main system clock High-speed system clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) High-speed on-chip oscillator clock (f IH) High-speed operation: 1 to 32 MHz (VDD = 2.7 to 5.5 V), High-speed operation: 1 to 16 MHz (VDD = 2.4 to 5.5 V), Low-speed operation: 1 to 8 MHz (VDD = 1.8 to 5.5 V), Low-voltage operation: 1 to 4 MHz (VDD = 1.6 to 5.5 V) Subsystem clock XT1 (crystal) oscillation 32.768 kHz (TYP .): VDD = 1.6 to 5.5 V Low-speed on-chip oscillator clock 15 kHz (TYP.): V DD = 1.6 to 5.5 V General-purpose register 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Minimum instruction execution time 0.03125 s (High-speed on-chip oscillator clock: fIH = 32 MHz operation) 0.05 s (High-speed system clock: fMX = 20 MHz operation) 30.5 s (Subsystem clock: fSUB = 32.768 kHz operation) Instruction set • Data transfer (8/16 bits)

Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits, 16 bits × 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
Multiplication and Accumulation (16 bits × 16 bits + 32 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. I/O port Total 74 92 CMOS I/O 64 82 CMOS input 5 5 CMOS output 1 1 N-ch open-drain I/O (6 V tolerance) Timer 16-bit timer 12 channels (TAU: 8 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1 channel) Watchdog timer 1 channel Real-time clock (RTC) 1 channel 12-bit interval timer 1 channel Timer output 20 (TAU: 8, Timer RJ: 2, Timer RD: 8, Timer RG: 2) PWM outputs: 13 (TAU: 6, Timer RD: 6, Timer RG: 1) RTC output 1
1 Hz (subsystem clock: f SUB = 32.768 kHz)

RL78/G14 1. OUTLINE R01DS0053EJ0100 Rev. 1.00 Page 40 of 97 Feb 21, 2012 (2/2) Note The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution is not issued by emulation with t he in-circuit emulator or on-chip debug emulator. Item 80-pin 100-pin R5F104Mx (x = F to H, J) R5F104Px (x = F to H, J) Clock output/buzzer output 2 2 (Main system clock: fMAIN = 20 MHz operation) (Subsystem clock: fSUB = 32.768 kHz operation) 8/10-bit resolution A/D converter 17 channels 20 channels D/A converter 2 channels 2 channels Comparator 2 channels 2 channels Serial interface [80-pin, 100-pin products]

CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 2 channels
CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels I2C bus 2 channels 2 channels Data transfer controller (DTC) 39 sources 39 sources Event link controller (ELC) Event input: 26 Event trigger output: 9 Vectored interrupt sources Internal 32 32 External 13 13 Key interrupt 8 8 Reset • Reset by RESET pin
Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detector
Internal reset by illegal instruction execution Note
Internal reset by RAM parity error
Internal reset by illegal-memory access Power-on-reset circuit • Power-on-reset: 1.51 ±0.03 V
Power-down-reset: 1.50 ±0.03 V Voltage detector 1.63 V to 4.06 V (14 stages) On-chip debug function Provided Power supply voltage VDD = 1.6 to 5.5 V Operating ambient temperature T A = 40 to +85 °C

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 41 of 97 Feb 21, 2012 2. ELECTRICAL SPECIFICATIONS Caution 1. The RL78/G14 has an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be gua ranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used.

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 42 of 97 Feb 21, 2012

2.1 Absolute Maximum Ratings

Note 1. Connect the REGC pin to V SS via a capacitor (0.47 to 1 F). This value regulates the absolute maximum rating of the REGC pin. Do not use this pin with voltage applied to it. Note 2. Must be 6.5 V or lower. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. Absolute Maximum Ratings (TA = 25 C) (1/2) (1/2) Parameter Symbols Conditions Ratings Unit Supply voltage VDD -0.5 to +6.5 V EVDD0, EVDD1 EVDD0 = EVDD1 -0.5 to +6.5 V VSS -0.5 to +0.3 V EVSS0, EVSS1 EVSS0 = EVSS1 -0.5 to +0.3 V REGC pin input voltage V IREGC REGC -0.3 to +2.8 and -0.3 to VDD +0.3 Note 1 V Input voltage V I1 P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P140 to P147 -0.3 to EV DD0 +0.3 and -0.3 to VDD +0.3 Note 2 V VI2 P60 to P63 (N-ch open-drain) -0.3 to +6.5 V VI3 P20 to P27, P121 to P124, P137, P150 to P156, EXCLK, EXCLKS, RESET -0.3 to VDD +0.3 Note 2 V Output voltage V O1 P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P130, P140 to P147 -0.3 to EV DD0 +0.3 Note 2 V VO2 P20 to P27, P150 to P156 -0.3 to VDD +0.3 V Analog input voltage V AI1 ANI16 to ANI20 -0.3 to EVDD0 +0.3 Note 2 V VAI2 ANI0 to ANI14 -0.3 to VDD +0.3 Note 2 V

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 43 of 97 Feb 21, 2012 Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. Absolute Maximum Ratings (TA = 25 C) (2/2) (2/2) Parameter Symbols Conditions Ratings Unit Output current, high I OH1 Per pin P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P130, P140 to P147 -40 mA Total of all pins -170 mA P00 to P04, P40 to P47, P102, P120, P130, P140 to P145 -70 mA P05, P06, P10 to P17, P30, P31, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100, P101, P110, P111, P146, P147 -100 mA I OH2 Per pin P20 to P27, P150 to P156 -0.5 mA Total of all pins -2 mA Output current, low I OL1 Per pin P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P130, P140 to P147 40 mA Total of all pins 170 mA P00 to P04, P40 to P47, P102, P120, P130, P140 to P145 70 mA P05, P06, P10 to P17, P30, P31, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P100, P101, P110, P111, P146, P147 100 mA I OL2 Per pin P20 to P27, P150 to P156 1 mA Total of all pins 5m A Operating ambient temperature T A In normal operation mode -40 to +85 C In flash memory programming mode Storage temperature T stg -65 to +150 C

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 44 of 97 Feb 21, 2012

2.2 Oscillator Characteristics

2.2.1 Main system clock osci llator characteristics

Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Caution 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance.

Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as V SS.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator. Caution 2. Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. (TA = -40 to +85 °C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit Ceramic resonator X1 clock oscillation frequency X) Note 2.7 V VDD 5.5 V 1.0 20.0 MHz Crystal resonator X1 cloc k oscillation frequency (fX) Note 2.7 V VDD 5.5 V 1.0 20.0 MHz X2 X1 Rd VSS X2 X1 Rd VSS

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 45 of 97 Feb 21, 2012

2.2.2 On-chip oscillator characteristics

Note 1. High-speed on-chip oscillator frequency is selected with bits 0 to 4 of the option byte (000C2H/010C2H) and bits 0 to 2 of the HOCODIV register. Note 2. This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time. When SSOP (30-pin), WQFN (32-, 40-, 48- pin), FLGA (36-pin), LQFP (7 × 7) (48-pin), LQFP (10 × 10) (52-pin), LQFP (12 × 12) (64-, 80-pin), LQFP (14 × 14) (80-, 100-pin), LQFP (14 × 20) (100-pin) products, these specifications show target values, which may change after device evaluation. (TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Oscillators Parameters Conditions MIN. TYP. MAX. Unit High-speed on-chip oscillator clock frequency Note 1 fIH 13 2 M Hz High-speed on-chip oscillator clock frequency accuracy Note 2 -20 to +85 C 1.8 V  VDD  5.5 V -1 +1 % Low-speed on-chip oscillator clock frequency fIL 15 kHz Low-speed on-chip oscillator clock frequency accuracy -15 +15 %

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 46 of 97 Feb 21, 2012

2.2.3 Subsystem clock osci llator characteristics

Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Caution 1. When using the XT1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance.

Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as V SS.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator. Caution 2. The XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the X1 oscillator. Particular care is therefore required with the wiring method when the XT1 clock is used. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. (TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Resonator Recommended Circuit Items Conditions MIN. TYP . MAX. Unit Crystal resonator XT1 clock oscillation frequency XT) Note 32 32.768 35 kHz XT1XT2 Rd VSS

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 47 of 97 Feb 21, 2012

2.3 DC Characteristics

2.3.1 Pin characteristics

Note 1. Value of current at which the device operation is guaranteed even if the current flows from the EVDD0, EVDD1, VDD pins to an output pin. Note 2. However, do not exceed the total current value. Note 3. Specification under conditions where the duty factor is 70%. The output current value that has changed the duty ratio can be calculated with the following expression (when changing the duty factor from 70 % to n %).

Total output current of pins = (IOH × 0.7)/(n × 0.01) <Example> Where n = 50 % and I OH = -10.0 mA Total output current of pins = (-10.0 × 0.7)/(50 × 0.01) = -14.0 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Note 4. The applied current for the products of industrial application (R5F104xxDxx) is -100 mA. Caution P00, P02 to P04, P10, P11, P13 to P15, P17, P30, P43 to P45, P50 to P55, P71, P74, P80 to P82, and P142 to P144 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. (TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Symbol Conditions MIN. TYP. MAX. Unit Output current, high Note 1 IOH1 Per pin for P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P130, P140 to P147

1.6 V  EV

DD0  5.5 V -10.0 Note 2 mA Total of P00 to P04, P40 to P47, P102, P120, P130, P140 to P145 (When duty = 70% Note 3) 4.0 V  EVDD0  5.5 V -55.0 mA 2.7 V  EVDD0 < 4.0 V -10.0 mA 1.8 V  EVDD0 < 2.7 V -5.0 mA 1.6 V  EVDD0 < 1.8 V -2.5 mA Total of P05, P06, P10 to P17, P30, P31, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100, P101, P110, P111, P146, P147 (When duty = 70% Note 3) 4.0 V  EVDD0  5.5 V -80.0 mA 2.7 V  EVDD0 < 4.0 V -19.0 mA 1.8 V  EVDD0 < 2.7 V -10.0 mA 1.6 V  EVDD0 < 1.8 V -5.0 mA Total of all pins (When duty = 70% Note 3) 1.6 V  EVDD0  5.5 V -135.0 Note 4 mA IOH2 Per pin for P20 to P27, P150 to P156 1.6 V  VDD  5.5 V -0.1 Note 2 mA Total of all pins (When duty = 70% Note 3) 1.6 V  VDD  5.5 V -1.5 mA

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 48 of 97 Feb 21, 2012 Note 1. Value of current at which the device operation is guarant eed even if the current flows from an output pin to the EV SS0, EVSS1, and VSS pins. Note 2. However, do not exceed the total current value. Note 3. Specification under conditions where the duty factor is 70 %. The output current value that has changed the duty ratio can be calculated with the following expression (when changing the duty factor from 70 % to n %).

Total output current of pins = (IOL × 0.7)/(n × 0.01) <Example> Where n = 50 % and I OL = 10.0 mA Total output current of pins = (10.0 × 0.7)/(50 × 0.01) = 14.0 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. (TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Symbol Conditions MIN. TYP. MAX. Unit Output current, low Note 1 IOL1 Per pin for P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P130, P140 to P147 20.0 Note 2 mA Per pin for P60 to P63 15.0 Note 2 mA Total of P00 to P04, P40 to P47, P102, P120, P130, P140 to P145 (When duty = 70% Note 3) 4.0 V  EVDD0  5.5 V 70.0 mA 2.7 V  EVDD0 < 4.0 V 15.0 mA 1.8 V  EVDD0 < 2.7 V 9.0 mA 1.6 V  EVDD0 < 1.8 V 4.5 mA Total of P05, P06, P10 to P17, P30, P31, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P100, P101, P110, P111, P146, P147 (When duty = 70% Note 3) 4.0 V  EVDD0  5.5 V 80.0 mA 2.7 V  EVDD0 < 4.0 V 35.0 mA 1.8 V  EVDD0 < 2.7 V 20.0 mA 1.6 V  EVDD0 < 1.8 V 10.0 mA Total of all pins (When duty = 70% Note 3) 150.0 mA IOL2 Per pin for P20 to P27, P150 to P156 0.4 Note 2 mA Total of all pins (When duty = 70% Note 3) 1.6 V  VDD  5.5 V 5.0 mA

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 49 of 97 Feb 21, 2012 Caution The maximum value of V IH of pins P00, P02 to P04, P10, P11, P13 to P15, P17, P30, P43 to P45, P50 to P55, P71, P74, P80 to P82, and P142 to P144 is EVDD0, even in the N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. (TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Symbol Conditions MIN. TYP . MAX. Unit Input voltage, high V IH1 P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P140 to P147 Normal input buffer 0.8 EV DD0 EVDD0 V VIH2 P01, P03, P04, P10, P14 to P17, P30, P31, P43, P44, P50, P53 to P55, P80, P81, P142, P143 TTL input buffer

4.0 V  EV

DD0  5.5 V

2.2 EV DD0 V

3.3 V  EV

DD0 < 4.0 V

2.0 EV DD0 V

DD0 < 3.3 V

1.50 EV DD0 V

VIH3 P20 to P27, P150 to P156 0.7 VDD VDD V VIH4 P60 to P63 0.7 EVDD0 6.0 V VIH5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0.8 VDD VDD V Input voltage, low V IL1 P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P140 to P147 Normal input buffer 0 0.2 EV DD0 V VIL2 P01, P03, P04, P10, P14 to P17, P30, P31, P43, P44, P50, P53 to P55, P80, P81, P142, P143 TTL input buffer DD0  5.5 V 00 . 8 V TTL input buffer

2.7 V  EV

DD0 < 4.0 V 00 . 5 V TTL input buffer DD0 < 2.7 V 00 . 3 2 V VIL3 P20 to P27, P150 to P156 0 0.3 VDD V VIL4 P60 to P63 0 0.3 EVDD0 V VIL5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0 0.2 VDD V

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 50 of 97 Feb 21, 2012 Caution P00, P02 to P04, P10, P11, P13 to P15, P17, P30, P43 to P45, P50 to P55, P71, P74, P80 to P82, P142 to P144 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. (TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Symbol Conditions MIN. TYP. MAX. Unit Output voltage, high V OH1 P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P130, P140 to P147 DD0  5.5 V, IOH1 = -10.0 mA EVDD0 - 1.5 V 4.0 V  EVDD0  5.5 V, IOH1 = -3.0 mA EVDD0 - 0.7 V 1.8 V  EVDD0  5.5 V, IOH1 = -1.5 mA EVDD0 - 0.5 V 1.6 V  EVDD0 < 1.8 V, IOH1 = -1.0 mA EVDD0 - 0.5 V VOH2 P20 to P27, P150 to P156 1.6 V  V DD  5.5 V, IOH2 = -100 A VDD - 0.5 V Output voltage, low V OL1 P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P130, P140 to P147 DD0  5.5 V, IOL1 = 20.0 mA 1.3 V 4.0 V  EVDD0  5.5 V, IOL1 = 8.5 mA 0.7 V 4.0 V  EVDD0  5.5 V, IOL1 = 4.0 mA 0.4 V 2.7 V  EVDD0  5.5 V, IOL1 = 1.5 mA 0.4 V 1.8 V  EVDD0  5.5 V, IOL1 = 0.6 mA 0.4 V 1.6 V  EVDD0 < 1.8 V, IOL1 = 0.3 mA 0.4 V VOL2 P20 to P27, P150 to P156 1.6 V  V DD  5.5 V, IOL2 = 400 A 0.4 V VOL3 P60 to P63 4.0 V  EVDD0  5.5 V, IOL3 = 15.0 mA 2.0 V 4.0 V  EVDD0  5.5 V, IOL3 = 5.0 mA 0.4 V 2.7 V  EVDD0  5.5 V, IOL3 = 3.0 mA 0.4 V 1.8 V  EVDD0  5.5 V, IOL3 = 2.0 mA 0.4 V 1.6 V  EVDD0  5.5 V, IOL3 = 1.0 mA 0.4 V

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 51 of 97 Feb 21, 2012 Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. (TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Symbol Conditions MIN. TYP. MAX. Unit Input leakage current, high ILIH1 P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P140 to P147 V I = EVDD0 1 A ILIH2 P20 to P27, P137, P150 to P156, RESET VI = VDD 1 A ILIH3 P121 to P124 (X1, X2, EXCLK, XT1, XT2, EXCLKS) V I = VDD In input port or external clock input 1 A In resonator connection 10 A Input leakage current, low I LIL1 P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P140 to P147 V I = EVSS0 -1 A ILIL2 P20 to P27, P137, P150 to P156, RESET VI = VSS -1 A ILIL3 P121 to P124 (X1, X2, EXCLK, XT1, XT2, EXCLKS) V I = VSS In input port or external clock input -1 A In resonator connection -10 A On-chip pll-up resistance R U P00 to P06, P10 to P17, P30, P31, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P100 to P102, P110, P111, P120, P140 to P147 V I = EVSS0, In input port 10 20 100 k 

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 52 of 97 Feb 21, 2012

2.3.2 Supply current characteristics

(Notes and Remarks are listed on the next page.) (1) Flash ROM: 16 to 64 KB of 30- to 64-pin products (TA = -40 to +85 C, 1.6 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V) (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply current Note 1 IDD1 Operating mode High-speed operation Notes 3, 5 fHOCO = 64 MHz, fIH = 32 MHz Basic operation VDD = 5.0 V 2.4 mA VDD = 3.0 V 2.4 fHOCO = 32 MHz, fIH = 32 MHz Basic operation V DD = 5.0 V 2.1 VDD = 3.0 V 2.1 High-speed operation Notes 3, 5 fHOCO = 64 MHz, fIH = 32 MHz Normal operation VDD = 5.0 V 5.2 8.7 mA VDD = 3.0 V 5.2 8.7 fHOCO = 32 MHz, fIH = 32 MHz Normal operation V DD = 5.0 V 4.8 8.1 VDD = 3.0 V 4.8 8.1 fHOCO = 48 MHz, fIH = 24 MHz Normal operation V DD = 5.0 V 4.1 6.9 VDD = 3.0 V 4.1 6.9 fHOCO = 24 MHz, fIH = 24 MHz Normal operation V DD = 5.0 V 3.8 6.3 VDD = 3.0 V 3.8 6.3 fHOCO = 16 MHz, fIH = 16 MHz Normal operation V DD = 5.0 V 2.8 4.6 VDD = 3.0 V 2.8 4.6 Low-speed operation Notes 3, 5 fHOCO = 8 MHz, fIH = 8 MHz Normal operation VDD = 3.0 V 1.3 2.0 mA VDD = 2.0 V 1.3 2.0 Low-voltage operation Notes 3, 5 fHOCO = 4 MHz, fIH = 4 MHz Normal operation VDD = 3.0 V 1.3 1.8 mA VDD = 2.0 V 1.3 1.8 High-speed operation Notes 2, 5 fMX = 20 MHz, VDD = 5.0 V Normal operation Square wave input 3.3 5.3 mA Resonator connection 3.5 5.5 fMX = 20 MHz, VDD = 3.0 V Normal operation Square wave input 3.3 5.3 Resonator connection 3.5 5.5 fMX = 10 MHz, VDD = 5.0 V Normal operation Square wave input 2.0 3.1 Resonator connection 2.1 3.2 fMX = 10 MHz, VDD = 3.0 V Normal operation Square wave input 2.0 3.1 Resonator connection 2.1 3.2 Low-speed operation Notes 2, 5 fMX = 8 MHz, VDD = 3.0 V Normal operation Square wave input 1.2 1.9 mA Resonator connection 1.2 2.0 fMX = 8 MHz, VDD = 2.0 V Normal operation Square wave input 1.2 1.9 Resonator connection 1.2 2.0 Subsystem clock operation Note 4 fSUB = 32.768 kHz TA = -40 C Normal operation Square wave input 4.7 A Resonator connection 4.7 fSUB = 32.768 kHz TA = +25 C Normal operation Square wave input 4.7 6.1 Resonator connection 4.7 6.1 fSUB = 32.768 kHz TA = +50 C Normal operation Square wave input 4.8 6.7 Resonator connection 4.8 6.7 fSUB = 32.768 kHz TA = +70 C Normal operation Square wave input 4.8 7.5 Resonator connection 4.8 7.5 fSUB = 32.768 kHz TA = +85 C Normal operation Square wave input 5.4 8.9 Resonator connection 5.4 8.9

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 53 of 97 Feb 21, 2012 Note 1. Total current flowing into V DD and EV DD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current (except for background operation (BGO)). However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors. Note 2. When high-speed on-chip oscillator and subsystem clock are stopped. Note 3. When high-speed system clock and subsystem clock are stopped. Note 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When real-time counter and watchdog timer is stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation). Note 5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. High speed operation: VDD = 2.7 V to 5.5 V@1 MHz to 32 MHz VDD = 2.4 V to 5.5 V@1 MHz to 16 MHz Low speed operation: VDD = 1.8 V to 5.5 V@1 MHz to 8 MHz Low voltage operation: VDD = 1.6 V to 5.5 V@1 MHz to 4 MHz Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.) Remark 3. fIH: High-speed on-chip oscillator clock frequency (32 MHz max.) Note Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 5. Except subsystem clock operation, temperature condition of the TYP . value is TA = 25°C Note fIH is controlled by hardware to be set to two frequency division of fHOCO when fHOCO is set to 64 MHz or 48 MHz, and the same clock frequency as fHOCO when fHOCO is set to 32 MHz or less. When supplying 64 MHz or 48 MHz to timer RD, set fCLK to fIH.

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 54 of 97 Feb 21, 2012 (Notes and Remarks are listed on the next page.) (1) Flash ROM: 16 to 64 KB of 30- to 64-pin products (TA = -40 to +85 C, 1.6 V  EVDD0  VDD  5.5 V, VSS = EVSS0 = 0 V) (2/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply current Note 1 IDD2 Note 2 HALT mode High-speed operation Notes 4, 7 fHOCO = 64 MHz, fIH = 32 MHz VDD = 5.0 V 0.80 3.09 mA VDD = 3.0 V 0.80 3.09 fHOCO = 32 MHz, fIH = 32 MHz VDD = 5.0 V 0.54 2.40 VDD = 3.0 V 0.54 2.40 fHOCO = 48 MHz, fIH = 24 MHz VDD = 5.0 V 0.62 2.40 VDD = 3.0 V 0.62 2.40 fHOCO = 24 MHz, fIH = 24 MHz VDD = 5.0 V 0.44 1.83 VDD = 3.0 V 0.44 1.83 fHOCO = 16 MHz, fIH = 16 MHz VDD = 5.0 V 0.40 1.38 VDD = 3.0 V 0.40 1.38 Low-speed operation Notes 4, 7 fHOCO = 8 MHz, fIH = 8 MHz VDD = 3.0 V 260 710 A VDD = 2.0 V 260 710 Low-voltage operation Notes 4, 7 fHOCO = 4 MHz, fIH = 4 MHz VDD = 3.0 V 420 700 A VDD = 2.0 V 420 700 High-speed operation Notes 3, 7 fMX = 20 MHz, VDD = 5.0 V Square wave input 0.28 1.55 mA Resonator connection 0.53 1.74 fMX = 20 MHz, VDD = 3.0 V Square wave input 0.28 1.55 Resonator connection 0.49 1.74 fMX = 10 MHz, VDD = 5.0 V Square wave input 0.19 0.86 Resonator connection 0.30 0.93 fMX = 10 MHz, VDD = 3.0 V Square wave input 0.19 0.86 Resonator connection 0.30 0.93 Low-speed operation Notes 3, 7 fMX = 7 MHz, VDD = 3.0 V Square wave input 95 550 A Resonator connection 145 590 fMX = 8 MHz, VDD = 2.0 V Square wave input 95 550 Resonator connection 145 590 Subsystem clock operation Note 5 fSUB = 32.768 kHz, TA = -40 C Square wave input 0.25 A Resonator connection 0.44 fSUB = 32.768 kHz, TA = +25 C Square wave input 0.30 0.57 Resonator connection 0.49 0.76 fSUB = 32.768 kHz, TA = +50 C Square wave input 0.33 1.17 Resonator connection 0.52 1.36 fSUB = 32.768 kHz, TA = +70 C Square wave input 0.36 1.97 Resonator connection 0.55 2.16 fSUB = 32.768 kHz, TA = +85 C Square wave input 0.97 3.37 Resonator connection 0.16 3.56 IDD3 STOP mode Note 6 TA = -40 C0 . 1 8 A TA = +25 C 0.24 0.51 TA = +50 C 0.26 1.10 TA = +70 C 0.29 1.90 TA = +85 C 0.90 3.30

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 55 of 97 Feb 21, 2012 Note 1. Total current flowing into V DD and EV DD0, including the input leakage current flowing when the level of the input pin is fixed to V DD, EV DD0 or V SS, EV SS0. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D conv erter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors. Note 2. During HALT instruction execution by flash memory. Note 3. When high-speed on-chip oscillator and subsystem clock are stopped. Note 4. When high-speed system clock and subsystem clock are stopped. Note 5. When operating real-time clock (RTC) and setting ultra-low current consumpt ion (AMPHS1 = 1). When high-speed on- chip oscillator and high-speed system clock are stopped. When watchdog timer is stopped. The values below the MAX. column include the leakage current. Note 6. When high-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. When watchdog timer is stopped. The values below the MAX. column include the leakage current. Note 7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. High speed operation: VDD = 2.7 V to 5.5 V@1 MHz to 32 MHz VDD = 2.4 V to 5.5 V@1 MHz to 16 MHz Low speed operation: VDD = 1.8 V to 5.5 V@1 MHz to 8 MHz Low voltage operation: VDD = 1.6 V to 5.5 V@1 MHz to 4 MHz Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.) Remark 3. fIH: High-speed on-chip oscillator clock frequency (32 MHz max.) Note Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 5. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25 °C Note fIH is controlled by hardware to be set to two frequency division of fHOCO when fHOCO is set to 64 MHz or 48 MHz, and the same clock frequency as fHOCO when fHOCO is set to 32 MHz or less. When supplying 64 MHz or 48 MHz to timer RD, set fCLK to fIH.

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 56 of 97 Feb 21, 2012 (Notes and Remarks are listed on the next page.) (2) Flash ROM: 96 to 256 KB of 30- to 100-pin products (TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply current Note 1 IDD1 Operating mode High-speed operation Notes 3, 5 fHOCO = 64 MHz, fIH = 32 MHz Basic operation VDD = 5.0 V 2.6 mA VDD = 3.0 V 2.6 fHOCO = 32 MHz, fIH = 32 MHz Basic operation V DD = 5.0 V 2.3 VDD = 3.0 V 2.3 High-speed operation Notes 3, 5 fHOCO = 64 MHz, fIH = 32 MHz Normal operation VDD = 5.0 V 5.8 10.2 mA VDD = 3.0 V 5.8 10.2 fHOCO = 32 MHz, fIH = 32 MHz Normal operation V DD = 5.0 V 5.4 9.6 VDD = 3.0 V 5.4 9.6 fHOCO = 48 MHz, fIH = 24 MHz Normal operation V DD = 5.0 V 4.5 7.8 VDD = 3.0 V 4.5 7.8 fHOCO = 24 MHz, fIH = 24 MHz Normal operation V DD = 5.0 V 4.2 7.4 VDD = 3.0 V 4.2 7.4 fHOCO = 16 MHz, fIH = 16 MHz Normal operation V DD = 5.0 V 3.1 5.3 VDD = 3.0 V 3.1 5.3 Low-speed operation Notes 3, 5 fHOCO = 8 MHz, fIH = 8 MHz Normal operation VDD = 3.0 V 1.4 2.3 mA VDD = 2.0 V 1.4 2.3 Low-voltage operation Notes 3, 5 fHOCO = 4 MHz, fIH = 4 MHz Normal operation VDD = 3.0 V 1.4 1.9 mA VDD = 2.0 V 1.4 1.9 High-speed operation Notes 2, 5 fMX = 20 MHz, VDD = 5.0 V Normal operation Square wave input 3.7 6.2 mA Resonator connection 3.9 6.4 fMX = 20 MHz, VDD = 3.0 V Normal operation Square wave input 3.7 6.2 Resonator connection 3.9 6.4 fMX = 10 MHz, VDD = 5.0 V Normal operation Square wave input 2.2 3.6 Resonator connection 2.3 3.7 fMX = 10 MHz, VDD = 3.0 V Normal operation Square wave input 2.2 3.6 Resonator connection 2.3 3.7 Low-speed operation Notes 2, 5 fMX = 8 MHz, VDD = 3.0 V Normal operation Square wave input 1.3 2.2 mA Resonator connection 1.3 2.3 fMX = 8 MHz, VDD = 2.0 V Normal operation Square wave input 1.3 2.2 Resonator connection 1.3 2.3 Subsystem clock operation Note 4 fSUB = 32.768 kHz TA = -40 C Normal operation Square wave input 5.0 A Resonator connection 5.0 fSUB = 32.768 kHz TA = +25 C Normal operation Square wave input 5.0 7.1 Resonator connection 5.0 7.1 fSUB = 32.768 kHz TA = +50 C Normal operation Square wave input 5.1 8.8 Resonator connection 5.1 8.8 fSUB = 32.768 kHz TA = +70 C Normal operation Square wave input 5.5 10.5 Resonator connection 5.5 10.5 fSUB = 32.768 kHz TA = +85 C Normal operation Square wave input 6.5 14.5 Resonator connection 6.5 14.5

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 57 of 97 Feb 21, 2012 Note 1. Total current flowing into VDD, EVDD0 and EVDD1, including the input leakage current flowing when the level of the input pin is fixed to V DD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current (except for background operation (BGO)). However, not including the current flowing into the A/D converter, D/A converter, comparator, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors. Note 2. When high-speed on-chip oscillator and subsystem clock are stopped. Note 3. When high-speed system clock and subsystem clock are stopped. Note 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When real-time counter and watchdog timer is stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation). Note 5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. High speed operation: V DD = 2.7 V to 5.5 V@1 MHz to 32 MHz VDD = 2.4 V to 5.5 V@1 MHz to 16 MHz Low speed operation: VDD = 1.8 V to 5.5 V@1 MHz to 8 MHz Low voltage operation: VDD = 1.6 V to 5.5 V@1 MHz to 4 MHz Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.) Remark 3. fIH: High-speed on-chip oscillator clock frequency (32 MHz max.) Note Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 5. Except subsystem clock operation, temperature condition of the TYP . value is TA = 25 °C Note fIH is controlled by hardware to be set to two frequency division of fHOCO when fHOCO is set to 64 MHz or 48 MHz, and the same clock frequency as fHOCO when fHOCO is set to 32 MHz or less. When supplying 64 MHz or 48 MHz to timer RD, set fCLK to fIH.

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 58 of 97 Feb 21, 2012 (Notes and Remarks are listed on the next page.) (2) Flash ROM: 96 to 256 KB of 30- to 100-pin products (TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply current Note 1 IDD2 HALT mode Note 2 High-speed operation Notes 4, 7 fHOCO = 64 MHz, fIH = 32 MHz VDD = 5.0 V 0.88 3.32 mA VDD = 3.0 V 0.88 3.32 fHOCO = 32 MHz, fIH = 32 MHz VDD = 5.0 V 0.62 2.63 VDD = 3.0 V 0.62 2.63 fHOCO = 48 MHz, fIH = 24 MHz VDD = 5.0 V 0.68 2.57 VDD = 3.0 V 0.68 2.57 fHOCO = 24 MHz, fIH = 24 MHz VDD = 5.0 V 0.50 2.00 VDD = 3.0 V 0.50 2.00 fHOCO = 16 MHz, fIH = 16 MHz VDD = 5.0 V 0.44 1.49 VDD = 3.0 V 0.44 1.49 Low-speed operation Notes 4, 7 fHOCO = 8 MHz, fIH = 8 MHz VDD = 3.0 V 290 800 A VDD = 2.0 V 290 800 Low-voltage operation Notes 4, 7 fHOCO = 4 MHz, fIH = 4 MHz VDD = 3.0 V 440 755 A VDD = 2.0 V 440 755 High-speed operation Notes 3, 7 fMX = 20 MHz, VDD = 5.0 V Square wave input 0.31 1.63 mA Resonator connection 0.50 1.85 fMX = 20 MHz, VDD = 3.0 V Square wave input 0.31 1.63 Resonator connection 0.50 1.85 fMX = 10 MHz, VDD = 5.0 V Square wave input 0.21 0.89 Resonator connection 0.30 0.97 fMX = 10 MHz, VDD = 3.0 V Square wave input 0.21 0.89 Resonator connection 0.30 0.97 Low-speed operation Notes 3, 7 fMX = 8 MHz, VDD = 3.0 V Square wave input 110 580 A Resonator connection 160 630 fMX = 8 MHz, VDD = 2.0 V Square wave input 110 580 Resonator connection 160 630 Subsystem clock operation Note 5 fSUB = 32.768 kHz, TA = -40 C Square wave input 0.28 A Resonator connection 0.47 fSUB = 32.768 kHz, TA = +25 C Square wave input 0.34 0.66 Resonator connection 0.53 0.85 fSUB = 32.768 kHz, TA = +50 C Square wave input 0.37 2.35 Resonator connection 0.56 2.54 fSUB = 32.768 kHz, TA = +70 C Square wave input 0.61 4.08 Resonator connection 0.80 4.27 fSUB = 32.768 kHz, TA = +85 C Square wave input 1.55 8.09 Resonator connection 1.74 8.28 IDD3 STOP mode Note 6 TA = -40 C0 . 1 9 A TA = +25 C0 .25 0.57 TA = +50 C0 .28 2.26 TA = +70 C0 .52 3.99 TA = +85 C1 .46 8.00

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 59 of 97 Feb 21, 2012 Note 1. Total current flowing into VDD, EVDD0 and EVDD1, including the input leakage current flowing when the level of the input pin is fixed to V DD, EVDD0, EVDD1 or V SS, EVSS0, EVSS1. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, D/A converter, comparator, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors. Note 2. During HALT instruction execution by flash memory. Note 3. When high-speed on-chip oscillator and subsystem clock are stopped. Note 4. When high-speed system clock and subsystem clock are stopped. Note 5. When operating real-time clock (RTC) and setting ultra-low current consumpt ion (AMPHS1 = 1). When high-speed on- chip oscillator and high-speed system clock are stopped. When watchdog timer is stopped. The values below the MAX. column include the leakage current. Note 6. When high-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. When watchdog timer is stopped. The values below the MAX. column include the leakage current. Note 7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. High speed operation: VDD = 2.7 V to 5.5 V@1 MHz to 32 MHz VDD = 2.4 V to 5.5 V@1 MHz to 16 MHz Low speed operation: VDD = 1.8 V to 5.5 V@1 MHz to 8 MHz Low voltage operation: VDD = 1.6 V to 5.5 V@1 MHz to 4 MHz Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.) Remark 3. fIH: High-speed on-chip oscillator clock frequency (32 MHz max.) Note Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 5. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25 °C Note fIH is controlled by hardware to be set to two frequency division of fHOCO when fHOCO is set to 64 MHz or 48 MHz, and the same clock frequency as fHOCO when fHOCO is set to 32 MHz or less. When supplying 64 MHz or 48 MHz to timer RD, set fCLK to fIH.

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 60 of 97 Feb 21, 2012 Note 1. Current flowing only to the real-time cloc k (excluding the operating current of the XT 1 oscillator). The TYP. value of the current value of the RL78/G14 is the sum of the TYP. values of either I DD1 or IDD2, and IRTC, when the real-time clock operates in operation mode or HALT mode. The I DD1 and IDD2 MAX. values also include the real-time clock operating current. However, IDD2 subsystem clock operation includes the operational current of the real-time clock. Note 2. When high speed on-chip oscillator and high-speed system clock are stopped. Note 3. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). The current value of the RL78/G14 is the sum of I DD1, IDD2 or IDD3 and IWDT when the watchdog timer operates in STOP mode. Note 4. Current flowing only to the A/D converter. The current value of the RL78/G14 is the sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode. Note 5. Current flowing only to the D/A converter. The current value of the RL78/G14 is the sum of IDD1 or IDD2 and IADC when the D/A converter operates in an operation mode or the HALT mode. Note 6. Current flowing only to the comparator circuit. The current value of the RL78/G14 is the sum of IDD1, IDD2 or IDD3 and ICMP when the comparator circuit operates in the Operating, HALT or STOP mode. Note 7. Current flowing only to the LVD circuit. The cu rrent value of the RL78/G14 is the sum of I DD1, IDD2 or IDD3 and ILVI when the LVD circuit operates in the Operating, HALT or STOP mode. Note 8. Current flowing only to the BGO. The current value of the RL78/G14 is the sum of I DD1 or IDD2 and IBGO when the BGO operates in an operation mode. Note 9. A comparator and D/A converter are provided in products with 96 KB or more code flash memory. Remark 1. fIL: Low-speed on-chip oscillator clock frequency Remark 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) Remark 3. fCLK: CPU/peripheral hardware clock frequency Remark 4. Temperature condition of the TYP . value is TA = 25 °C (3) Common to RL78/G14 all products (TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit RTC operating current I RTC Notes 1, 2 fSUB = 32.768 kHz Real-time clock operation 0.02 A 12-bit interval timer operation 0.02 Watchdog timer operating current IWDT Notes 2, 3 fIL = 15 kHz 0.22 A A/D converter operating current I ADC Note 4 When conversion at maximum speed Normal mode, AV REFP = VDD = 5.0 V 1.3 1.7 mA Low voltage mode, AVREFP = VDD = 3.0 V 0.5 0.7 mA A/D converter reference voltage current I ADREF 75 A D/A converter operating current I DAC Notes 5, 9 Per D/A converter channel 1.5 mA Comparator operating current I CMP Notes 6, 9 VDD = 5.0 V, Regulator output voltage = 2.1 V Window comparator mode 12.5 A High-speed comparator mode 6.5 A Low-speed comparator mode 1.7 A V DD = 5.0 V, Regulator output voltage = 1.8 V Window comparator mode 8.0 A High-speed comparator mode 4.0 A Low-speed comparator mode 1.3 A Temperature sensor operating current I TMPS 75 A LVD operating current ILVI Note 7 0.08 A BGO operating current I BGO Note 8 2.50 12.20 mA

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 61 of 97 Feb 21, 2012

2.4 AC Characteristics

2.4.1 Basic operation

Note The following conditions are required for low voltage interface when EVDD0 < VDD 1.8 V  EVDD0 < 2.7 V : MIN. 125 ns 1.6 V  EVDD0 < 1.8 V : MIN. 250 ns Remark fMCK: Timer array unit operation clock frequency (Operation clock to be set by the CKSmn bit of timer mode register mn (TMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)) (TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Items Symbol Conditions MIN. TYP. MAX. Unit Instruction cycle (minimum instruction execution time) T CY Main system clock (f MAIN) operation High-speed main mode

2.7 V  V

DD  5.5 V 0.03125 1 s 2.4 V  VDD < 2.7 V 0.0625 1 s Low voltage main mode

1.6 V  V

DD  5.5 V 0.25 1 s Low-speed main mode

1.8 V  V

DD  5.5 V 0.125 1 s In the self programming mode High-speed main mode DD  5.5 V 0.03125 1 s 2.4 V  VDD < 2.7 V 0.0625 1 s Low voltage main mode DD  5.5 V 0.25 1 s Low-speed main mode DD  5.5 V 0.125 1 s External main system clock frequency f EX 2.7 V  VDD  5.5 V 1.0 20.0 MHz 1.8 V  VDD < 2.7 V 1.0 8.0 MHz 1.6 V  VDD < 1.8 V 1.0 4.0 MHz fEXS 32 35 kHz External main system clock input high-level width, low-level width t EXH, tEXL 2.7 V  VDD  5.5 V 24 ns 1.8 V  VDD < 2.7 V 60 ns 1.6 V  VDD < 1.8 V 120 ns tEXHS, tEXLS 13.7 s TI00 to TI03, TI10 to TI13 input high-level width, low-level width t TIH, tTIL 1/fMCK + 10 Note ns Timer RJ input cycle f C TRJIO 2.7 V  EVDD0  5.5 V 100 ns 1.8 V  EVDD0 < 2.7 V 300 ns 1.6 V  EVDD0 < 1.8 V 500 ns Timer RJ input high- level width, low-level width f WH, fWL TRJIO 2.7 V  EVDD0  5.5 V 40 ns 1.8 V  EVDD0 < 2.7 V 120 ns 1.6 V  EVDD0 < 1.8 V 200 ns

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 62 of 97 Feb 21, 2012 (TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Items Symbol Conditions MIN. TYP. MAX. Unit TO00 to TO03, TO10 to T13 output frequency fTO High-speed main mode 4.0 V  EVDD0  5.5 V 16 MHz 2.7 V  EVDD0 < 4.0 V 8 MHz 1.8 V  EVDD0 < 2.7 V 4 MHz 1.6 V  EVDD0 < 1.8 V 2 MHz Low voltage main mode 1.6 V  EVDD0  5.5 V 2 MHz Low-speed main mode 1.8 V  EVDD0  5.5 V 4 MHz 1.6 V  EVDD0 < 1.8 V 2 MHz PCLBUZ0, PCLBUZ1 output frequency f PCL High-speed main mode 4.0 V  EVDD0  5.5 V 16 MHz 2.7 V  EVDD0 < 4.0 V 8 MHz 1.8 V  EVDD0 < 2.7 V 4 MHz 1.6 V  EVDD0 < 1.8 V 2 MHz Low voltage main mode 1.8 V  EVDD0  5.5 V 4 MHz 1.6 V  EVDD0 < 1.8 V 2 MHz Low-speed main mode 1.8 V  EVDD0  5.5 V 4 MHz 1.6 V  EVDD0 < 1.8 V 2 MHz Interrupt input high-level width, low-level width t INTH, tINTL INTP0 1.6 V  VDD  5.5 V 1 s INTP1 to INTP11 1.6 V  EVDD0  5.5 V 1 s Key interrupt input low-level width t KR 1.8 V  EVDD0  5.5 V 250 ns 1.6 V  EVDD0 < 1.8 V 1 s RESET low-level width tRSL 10 s

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 63 of 97 Feb 21, 2012

2.5 Peripheral Functions Characteristics

2.5.1 Serial array unit

UART mode connection diagram (during communication at same potential) UART mode bit width (during communication at same potential) (reference) Note 1. Transfer rate in the SNOOZE mode is MAX. 9600 bps and MIN. 4800 bps. Note 2. The following conditions are required for low voltage interface when EVDD0 < VDD. 2.4 V  EVDD0 < 2.7 V : MAX. 2.6 Mbps 1.8 V  EVDD0 < 2.4 V : MAX. 1.3 Mbps 1.6 V  EVDD0 < 1.8 V : MAX. 0.6 Mbps Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 5, 14) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) (1) During communication at same potential (UART mode) (dedicated baud rate generator output) (TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate Note 1 fMCK/6 Note 2 bps Theoretical value of the maximum transfer rate fCLK = 32 MHz, fMCK = fCLK

5.3 Mbps

User’s device Rx Tx RL78/G14 Baud rate error tolerance TxDq RxDq High-/Low-bit width 1/Transfer rate

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 64 of 97 Feb 21, 2012 Note 1. The value must also be 2/fCLK or more. Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 5. Using the fMCK within 24 MHz. Note 6. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. This specification is valid only when CSI00’s peripheral I/O redirect function is not used. Remark 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 1) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) (2) During communication at same potential (CSI mode) (master mode (f MCK/2), SCKp... internal clock output) (TA = -40 to +85 C, 2.7 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time tKCY1 2.7 V  EVDD0  5.5 V 62.5 Note 1 ns SCKp high-/low-level width tKH1, tKL1 4.0 V  EVDD0  5.5 V tKCY1/2 - 7 ns 2.7 V  EVDD0  5.5 V tKCY1/2 - 10 ns SIp setup time (to SCKp↑) Note 2 tSIK1 4.0 V  EVDD0  5.5 V 23 ns 2.7 V  EVDD0  5.5 V 33 Note 5 ns SIp hold time (from SCKp↑) Note 3 tKSI1 2.7 V  EVDD0  5.5 V 10 ns Delay time from SCKp↓ to SOp output Note 4 tKSO1 C = 20 pF Note 6 10 ns

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 65 of 97 Feb 21, 2012 Note 1. The value must also be 4/fCLK or more. Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 5. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM number (g = 0, 1, 3 to 5, 14) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) (3) During communication at same potential (CSI mode) (master mode (f MCK/4), SCKp... internal clock output) (TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time tKCY1 2.7 V  EVDD0  5.5 V 125 Note 1 ns 2.4 V  EVDD0  5.5 V 250 Note 1 ns 1.8 V  EVDD0  5.5 V 500 Note 1 ns 1.6 V  EVDD0  5.5 V 1000 Note 1 ns SCKp high-/low-level width tKH1, tKL1 4.0 V  EVDD0  5.5 V tKCY1/2 - 12 ns 2.7 V  EVDD0  5.5 V tKCY1/2 - 18 ns 2.4 V  EVDD0  5.5 V tKCY1/2 - 38 ns 1.8 V  EVDD0  5.5 V tKCY1/2 - 50 ns 1.6 V  EVDD0  5.5 V tKCY1/2 - 100 ns SIp setup time (to SCKp↑) Note 2 tSIK1 4.0 V  EVDD0  5.5 V 44 ns 2.7 V  EVDD0  5.5 V 44 ns 2.4 V  EVDD0  5.5 V 75 ns 1.8 V  EVDD0  5.5 V 110 ns 1.6 V  EVDD0  5.5 V 220 ns SIp hold time (from SCKp↑) Note 3 tKSI1 19 ns Delay time from SCKp↓ to SOp output Note 4 tKSO1 C = 30 pF Note 5 25 ns

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 66 of 97 Feb 21, 2012 Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 4. C is the load capacitance of the SOp output lines. Note 5. The maximum transfer rate when using the SNOOZE mode is 1 Mbps. Caution Select the TTL input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM number (g = 0, 1, 3 to 5, 14) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) (4) During communication at same pote ntial (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time Note 5 tKCY2 4.0 V  EVDD0  5.5 V 20 MHz < f MCK 8/fMCK ns fMCK  20 MHz 6/fMCK ns 2.7 V  EVDD0 < 4.0 V 16 MHz < f MCK 8/fMCK ns fMCK  16 MHz 6/fMCK ns 1.8 V  EVDD0 < 2.7 V 16 MHz < f MCK 8/fMCK ns fMCK  16 MHz 6/fMCK ns 1.6 V  EVDD0 < 1.8 V 6/fMCK ns SCKp high-/low-level width tKH2, tKL2 1.6 V  EVDD0  5.5 V tKCY2/2 ns SIp setup time (to SCKp↑) Note 1 tSIK2 2.7 V  EVDD0  5.5 V 1/fMCK + 20 ns 1.8 V  EVDD0 < 2.7 V 1/fMCK + 30 ns 1.6 V  EVDD0 < 1.8 V 1/fMCK + 40 ns SIp hold time (from SCKp ↑) Note 2 tKSI2 2.7 V  EVDD0  5.5 V 1/fMCK + 31 ns 2.4 V  EVDD0 < 2.7 V 1/fMCK + 31 ns 1.8 V  EVDD0 < 2.4 V 1/fMCK + 31 ns 1.6 V  EVDD0 < 1.8 V 1/fMCK + 250 ns Delay time from SCKp↓ to SOp output Note 3 tKSO2 C = 30 pF Note 4 4.0 V  EVDD0  5.5 V 2/fMCK + 44 ns 2.7 V  EVDD0 < 4.0 V 2/fMCK + 44 ns 2.4 V  EVDD0 < 2.7 V 2/fMCK + 75 ns 1.8 V  EVDD0 < 2.4 V 2/fMCK + 110 ns 1.6 V  EVDD0 < 1.8 V 2/fMCK + 220 ns

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 67 of 97 Feb 21, 2012 Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM number (g = 3, 5) CSI mode connection diagram (during communication at same potential) CSI mode connection diagram (during communication at same potential) (Slave Transmission of slave select input function (CSI00)) Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31) Remark 2. m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13) (4) During communication at same pote ntial (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit SSI00 setup time tSSIK DAPmn = 0 2.7 V  EVDD0  5.5 V 120 ns 1.8 V  EVDD0 < 2.7 V 200 ns 1.6 V  EVDD0 < 1.8 V 400 ns DAPmn = 1 2.7 V  EVDD0  5.5 V 1/f MCK + 120 ns 1.8 V  EVDD0 < 2.7 V 1/f MCK + 200 ns 1.6 V  EVDD0 < 1.8 V 1/f MCK + 400 ns SSI00 hold time tKSSI DAPmn = 0 2.7 V  EVDD0  5.5 V 1/f MCK + 120 ns 1.8 V  EVDD0 < 2.7 V 1/f MCK + 200 ns 1.6 V  EVDD0 < 1.8 V 1/f MCK + 400 ns DAPmn = 1 2.7 V  EVDD0  5.5 V 120 ns 1.8 V  EVDD0 < 2.7 V 200 ns 1.6 V  EVDD0 < 1.8 V 400 ns SCKp SOp User's device SCK SI SIp SORL78/G14 SCK00 SO00 User's device SCK SI SI00 SO SSI00 SS0 RL78/G14

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 68 of 97 Feb 21, 2012 CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31) Remark 2. m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13) SIp SOp tKCY1, 2 Input data Output data SCKp tKL1, 2 tKH1, 2 SSI00 (CSI00 only) tSIK1, 2 tKSI1, 2 tKSO1, 2 tSSIK tKSSI Input data Output data tKCY1, 2 tKH1, 2 tSIK1, 2 tKSI1, 2 tKSO1, 2 tSSIK tKSSI SIp SOp SCKp SSI00 (CSI00 only) tKL1, 2

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 69 of 97 Feb 21, 2012 Note Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”. (Caution and Remarks are listed on the next page.) (5) During communication at sa me potential (simplified I2C mode) (TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. MAX. Unit SCLr clock frequency fSCL 2.7 V  EVDD0  5.5 V, Cb = 50 pF, Rb = 2.7 k 1000 kHz 1.8 V  EVDD0  5.5 V, Cb = 100 pF, Rb = 3 k 400 kHz 1.8 V  EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 k 300 kHz 1.6 V  EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 k 250 kHz Hold time when SCLr = “L” tLOW 2.7 V  EVDD0  5.5 V, Cb = 50 pF, Rb = 2.7 k 475 ns 1.8 V  VDD0  5.5 V, Cb = 100 pF, Rb = 3 k 1150 ns 1.8 V  EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 k 1550 ns 1.6 V  EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 k 1850 ns Hold time when SCLr = “H” tHIGH 2.7 V  EVDD0  5.5 V, Cb = 50 pF, Rb = 2.7 k 475 ns 1.8 V  EVDD0  5.5 V, Cb = 100 pF, Rb = 3 k 1150 ns 1.8 V  EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 k 1550 ns 1.6 V  EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 k 1850 ns Data setup time (reception) tSU:DAT 2.7 V  EVDD0  5.5 V, Cb = 50 pF, Rb = 2.7 k 1/fMCK + 85 Note ns 1.8 V  EVDD0  5.5 V, Cb = 100 pF, Rb = 3 k 1/fMCK + 145 Note ns 1.8 V  EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 k 1/fMCK + 230 Note ns 1.6 V  EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 k 1/fMCK + 290 Note ns Data hold time (transmission) t HD:DAT 2.7 V  EVDD0  5.5 V, Cb = 50 pF, Rb = 2.7 k 0 305 ns 1.8 V  EVDD0  5.5 V, Cb = 100 pF, Rb = 3 k 0 355 ns 1.8 V  EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 k 0 405 ns 1.6 V  EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 k 0 405 ns

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 70 of 97 Feb 21, 2012 Simplified I2C mode mode connection diagram (during communication at same potential) Simplified I2C mode serial transfer timing (during communication at same potential) Caution Select the TTL input buffer and the N-ch open drain output (EV DD0 tolerance) mode for the SDAr pin and the N-ch open drain output (EVDD0 tolerance) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register h (POMh). Remark 1. Rb[]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance Remark 2. r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), g: PIM number (g = 0, 1, 3 to 5, 14), h: POM number (h = 0, 1, 3 to 5, 7, 14) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), mn = 00 to 03, 10 to 13) SDAr SCLr User’s device SDA SCL VDD Rb RL78/G14 SDAr SCLr 1/fSCL tLOW tHIGH tSU: DATtHD: DAT

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 71 of 97 Feb 21, 2012 Note 1. Transfer rate in the SNOOZE mode : MAX. 9600 bps, MIN. 4800 bps Note 2. Use it with EVDD0  Vb. Note 3. The following conditions are required for low voltage interface when EVDD0 < VDD. 2.4 V  EVDD0 < 2.7 V : MAX. 2.6 Mbps 1.8 V  EVDD0 < 2.4 V : MAX. 1.3 Mbps 1.6 V  EVDD0 < 1.8 V : MAX. 0.6 Mbps Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (EV DD0 tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. Vb[V]: Communication line voltage Remark 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 5, 14) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13) Remark 4. VIH and V IL below are observation points for the AC characteri stics of the serial array unit when communicating at different potentials in UART mode. Remark 5. UART2 cannot communicate at different potential when bit 1 (PIO R01) of peripheral I/O redirection register 0 (PIOR0) is (6) Communication at different potential (2.5 V, 3 V) (UART mode) (dedicated baud rate generator output) (TA = -40 to +85 C, 1.8 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate Notes 1, 2 reception 4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V fMCK/6 Note 1 bps Theoretical value of the maximum transfer rate f CLK = 32 MHz, fMCK = fCLK 2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V fMCK/6 Note 1 bps Theoretical value of the maximum transfer rate f CLK = 32 MHz, fMCK = fCLK 1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V fMCK/6 Note 1 to Note 3 bps Theoretical value of the maximum transfer rate f CLK = 8 MHz, fMCK = fCLK

1.3 Mbps

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 72 of 97 Feb 21, 2012 Note 1. The smaller maximum transfer rate derived by using f MCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V  EVDD0  5.5 V and 2.7 V  Vb  4.0 V Note 2. Transfer rate in the SNOOZE mode: MAX. 9600 bps, MIN. 4800 bps Note 3. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer. Note 4. The smaller maximum transfer rate derived by using f MCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V  EVDD0 < 4.0 V and 2.3 V  Vb  2.7 V Note 5. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 4 above to calculate the maximum transfer rate under conditions of the customer. Note 6. Use it with EVDD0  Vb. (6) Communication at different potential (2.5 V, 3 V) (UART mode) (dedicated baud rate generator output) (TA = -40 to +85 C, 1.8 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate transmission 4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V Notes 1, 2 bps Theoretical value of the maximum transfer rate C b = 50 pF, Rb = 1.4 k, Vb = 2.7 V 2.8 Note 3 Mbps 2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V Notes 2, 4 bps Theoretical value of the maximum transfer rate C b = 50 pF, Rb = 2.7 k, Vb = 2.3 V 1.2 Note 5 Mbps 1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V Notes 2, 6, 7 bps Theoretical value of the maximum transfer rate C b = 50 pF, Rb = 5.5 k, Vb = 1.6 V 0.40 Note 8 Mbps Maximum transfer rate = [bps] Baud rate error (theoretical value) = Transfer rate  2 Vb Vb ( )  Number of transferred bits1 Transfer rate  100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. Maximum transfer rate = [bps] Baud rate error (theoretical value) = Transfer rate  2 Vb Vb ( )  Number of transferred bits1 Transfer rate  100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides.

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 73 of 97 Feb 21, 2012 Note 7. The smaller maximum transfer rate derived by using f MCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 1.8 V  EVDD0 < 3.3 V and 1.6 V  Vb  2.0 V Note 8. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 7 above to calculate the maximum transfer rate under conditions of the customer. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (EV DD0 tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. Rb[]: Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage Remark 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 5, 14) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) Remark 4. VIH and V IL below are observation points for the AC characteri stics of the serial array unit when communicating at different potentials in UART mode. 4.0 V Remark 5. UART2 cannot communicate at different potential when bit 1 (PIO R01) of peripheral I/O redirection register 0 (PIOR0) is UART mode connection diagram (during communication at different potential) Maximum transfer rate = [bps] Baud rate error (theoretical value) = Transfer rate  2 Vb Vb ( )  Number of transferred bits1 Transfer rate  100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. TxDq RxDq User’s device Rx Tx Vb Rb RL78/G14

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 74 of 97 Feb 21, 2012 UART mode bit width (during communication at different potential) (reference) Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (EV DD0 tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. Rb[]: Communication line (TxDq) pull-up resistance, Vb[V]: Communication line voltage Remark 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 5, 14) Baud rate error tolerance High-/Low-bit width 1/Transfer rate Baud rate error tolerance High-bit width Low-bit width 1/Transfer rate TxDq RxDq

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 75 of 97 Feb 21, 2012 (Notes, Caution and Remarks are listed on the next page.) (7) Communication at different potential (2.5 V, 3 V) (f MCK/2) (CSI mode) (master mode, SCKp... internal clock output) (TA = -40 to +85 C, 2.7 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time tKCY1 4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V, Cb = 20 pF, Rb = 1.4 k

200 Note 1 ns

2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 20 pF, Rb = 2.7 k

300 Note 1 ns

SCKp high-level width tKH1 4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V, Cb = 20 pF, Rb = 1.4 k tKCY1/2 - 50 ns 2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 20 pF, Rb = 2.7 k tKCY1/2 - 120 ns SCKp low-level width tKL1 4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V, Cb = 20 pF, Rb = 1.4 k tKCY1/2 - 7 ns 2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 20 pF, Rb = 2.7 k tKCY1/2 - 10 ns SIp setup time (to SCKp↑) Note 2 tSIK1 4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V, Cb = 20 pF, Rb = 1.4 k 58 ns 2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 20 pF, Rb = 2.7 k 121 ns SIp hold time (from SCKp ↑) Note 2 tKSI1 4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V, Cb = 20 pF, Rb = 1.4 k 10 ns 2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 20 pF, Rb = 2.7 k 10 ns Delay time from SCKp↓ to SOp output Note 2 tKSO1 4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V, Cb = 20 pF, Rb = 1.4 k 60 ns 2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 20 pF, Rb = 2.7 k 130 ns SIp setup time (to SCKp ↓) Note 3 tSIK1 4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V, Cb = 20 pF, Rb = 1.4 k 23 ns 2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 20 pF, Rb = 2.7 k 33 ns SIp hold time (from SCKp ↓) Note 3 tKSI1 4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V, Cb = 20 pF, Rb = 1.4 k 10 ns 2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 20 pF, Rb = 2.7 k 10 ns Delay time from SCKp↑ to SOp output Note 3 tKSO1 4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V, Cb = 20 pF, Rb = 1.4 k 10 ns 2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 20 pF, Rb = 2.7 k 10 ns

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 76 of 97 Feb 21, 2012 CSI mode connection diagram (during communication at different potential) Note 1. The value must also be 2/fCLK or more. Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. Note 3. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (EV DD0 tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. Rb[]: Communication line (SCKp , SOp) pull-up resistance, C b[F]: Communication line (SCKp , SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM and POM number (g = 0, 1, 3 to 5, 14) Remark 3. VIH and V IL below are observation points for the AC characteri stics of the serial array unit when communicating at different potentials in CSI mode. 4.0 V Remark 4. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. Remark 5. This specification is valid only when CSI00’s peripheral I/O redirect function is not used. SCKp SOp User’s device SCK SI SIp SO Vb Rb <Master> Vb Rb RL78/G14

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 77 of 97 Feb 21, 2012 Note 1. The value must also be 4/fCLK or more. Caution 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (EVDD0 tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Caution 2. Use it with EV DD0  Vb. Remark 1. Rb[]: Communication line (SCKp , SOp) pull-up resistance, C b[F]: Communication line (SCKp , SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM and POM number (g = 0, 1, 3 to 5, 14) Remark 3. VIH and V IL below are observation points for the AC characteri stics of the serial array unit when communicating at different potentials in CSI mode. Remark 4. 4. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. (8) Communication at different potential (2.5 V, 3 V) (fMCK/4) (CSI mode) (master mode, SCKp... internal clock output) (TA = -40 to +85 C, 1.8 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time tKCY1 4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V, Cb = 30 pF, Rb = 1.4 k

300 Note ns

2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k

500 Note ns

1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V, Cb = 30 pF, Rb = 5.5 k

1150 Note ns

SCKp high-level width tKH1 4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V, Cb = 30 pF, Rb = 1.4 k tKCY1/2 - 75 ns 2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k tKCY1/2 - 170 ns 1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V, Cb = 30 pF, Rb = 5.5 k tKCY1/2 - 458 ns SCKp low-level width tKL1 4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V, Cb = 30 pF, Rb = 1.4 k tKCY1/2 - 12 ns 2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k tKCY1/2 - 18 ns 1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V, Cb = 30 pF, Rb = 5.5 k tKCY1/2 - 50 ns

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 78 of 97 Feb 21, 2012 (Notes, Caution and Remarks are listed on the next page.) (8) Communication at different potential (2.5 V, 3 V) (f MCK/4) (CSI mode) (master mode, SCKp... internal clock output) (TA = -40 to +85 C, 1.8 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit SIp setup time (to SCKp↑) Note 1 tSIK1 4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V, Cb = 30 pF, Rb = 1.4 k 81 ns 2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k 177 ns 1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V, Cb = 30 pF, Rb = 5.5 k 479 ns SIp hold time (from SCKp ↑) Note 1 tKSI1 4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V, Cb = 30 pF, Rb = 1.4 k 19 ns 2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k 19 ns 1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V, Cb = 30 pF, Rb = 5.5 k 19 ns Delay time from SCKp↓ to SOp output Note 1 tKSO1 4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V, Cb = 30 pF, Rb = 1.4 k 100 ns 2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k 195 ns 1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V, Cb = 30 pF, Rb = 5.5 k 483 ns SIp setup time (to SCKp↓) Note 2 tSIK1 4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V, Cb = 30 pF, Rb = 1.4 k 44 ns 2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k 44 ns 1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V, Cb = 30 pF, Rb = 5.5 k 110 ns SIp hold time (from SCKp ↓) Note 2 tKSI1 4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V, Cb = 30 pF, Rb = 1.4 k 19 ns 2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k 19 ns 1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V, Cb = 30 pF, Rb = 5.5 k 19 ns Delay time from SCKp↑ to SOp output Note 2 tKSO1 4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V, Cb = 30 pF, Rb = 1.4 k 25 ns 2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k 25 ns 1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V, Cb = 30 pF, Rb = 5.5 k 25 ns

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 79 of 97 Feb 21, 2012 CSI mode connection diagram (during communication at different potential Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. Note 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (EVDD0 tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Caution 2. Use it with EV DD0  Vb. Remark 1. Rb[]: Communication line (SCKp , SOp) pull-up resistance, C b[F]: Communication line (SCKp , SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM and POM number (g = 0, 1, 3 to 5, 14) Remark 3. VIH and V IL below are observation points for the AC characteri stics of the serial array unit when communicating at different potentials in CSI mode. Remark 4. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. SCKp SOp User’s device SCK SI SIp SO Vb Rb <Master> Vb Rb RL78/G14

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 80 of 97 Feb 21, 2012 CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (EV DD0 tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM and POM number (g = 0, 1, 3 to 5, 14) Remark 2. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. Input dataSIp SOp tKCY1 tKL1 tKH1 tSIK1 tKSI1 tKSO1 Output data SCKp Input data Output data SIp SOp SCKp tKCY1 tKH1 tKL1 tSIK1 tKSI1 tKSO1

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 81 of 97 Feb 21, 2012 (Notes, Caution and Remarks are listed on the next page.) (9) Communication at different potential (2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +85 C, 1.8 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time Note 1 tKCY2 4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V

24 MHz  fMCK 14/fMCK ns

20 MHz < fMCK  24 MHz 12/f MCK ns

8 MHz < fMCK  20 MHz 10/f MCK ns

4 MHz < fMCK  8 MHz 8/f MCK ns

fMCK  4 MHz 6/fMCK ns 2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V

24 MHz < fMCK 20/fMCK ns

20 MHz < fMCK  24 MHz 16/f MCK ns

16 MHz < fMCK  20 MHz 14/f MCK ns

8 MHz < fMCK  16 MHz 12/f MCK ns

fMCK  4 MHz 6/fMCK ns 1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V Note 2

24 MHz  fMCK 48/fMCK ns

20 MHz < fMCK  24 MHz 36/f MCK ns

16 MHz < fMCK  20 MHz 32/f MCK ns

8 MHz < fMCK  16 MHz 26/f MCK ns

4 MHz < fMCK  8 MHz 16/f MCK ns

fMCK  4 MHz 10/fMCK ns SCKp high-/low-level width tKH2, tKL2 4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V tKCY2/2 - 12 ns 2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V tKCY2/2 - 18 ns 1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V Note 2 tKCY2/2 - 50 ns SIp setup time (to SCKp↑) Note 3 tSIK2 2.7 V  EVDD0 < 5.5 V 1/fMCK + 20 ns 1.8 V  EVDD0 < 3.3 V 1/fMCK + 30 ns SIp hold time (from SCKp ↑) Note 4 tKSI2 1/fMCK + 31 ns Delay time from SCKp↓ to SOp output Note 5 tKSO2 4.0 V  EVDD0  5.5 V, 2.7 V  Vb  4.0 V, Cb = 30 pF, Rb = 1.4 k 1/fMCK + 250 2/f MCK + 120 ns 2.7 V  EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V, Cb = 30 pF, Rb = 2.7 k 2/fMCK + 214 ns 1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V Note 2, Cb = 30 pF, Rb = 5.5 k 2/fMCK + 573 ns

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 82 of 97 Feb 21, 2012 CSI mode connection diagram (during communication at different potential) Note 1. Transfer rate in the SNOOZE mode: MAX. 1 Mbps Note 2. Use it with EVDD0  Vb. Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (EVDD0 tolerance) mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. Rb[]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM and POM number (g = 0, 1, 3 to 5, 14) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 02, 10)) Remark 4. VIH and V IL below are observation points for the AC characteri stics of the serial array unit when communicating at different potentials in CSI mode. Remark 5. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. Also, communication at different potential cannot be performed during clock synchronous serial communication with the slave select function. SCKp SOp User’s device SCK SI SIp SO Vb Rb <Slave> RL78/G14

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 83 of 97 Feb 21, 2012 CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (EVDD0 tolerance) mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM and POM number (g = 0, 1, 3 to 5, 14) Remark 2. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. Also, communication at different potential cannot be performed during clock synchronous serial communication with the slave select function. SIp SOp SCKp Input data Output data tKCY2 tKH2tKL2 tSIK2 tKSI2 tKSO2 Input data Output data SIp SOp SCKp tKCY2 tKL2tKH2 tSIK2 tKSI2 tKSO2

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 84 of 97 Feb 21, 2012 (Notes, Caution and Remarks are listed on the next page.) (10) Communication at different potential (2.5 V, 3 V) (simplified I2C mode) (TA = -40 to +85 C, 1.8 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Parameter Symbol Conditions MIN. MAX. Unit SCLr clock frequency fSCL 4.0 V  EVDD0  5.5 V, Cb = 50 pF, Rb = 2.7 k 1000 kHz 2.7 V  EVDD0 < 4.0 V, Cb = 50 pF, Rb = 2.7 k 1000 kHz 4.0 V  EVDD0  5.5 V, Cb = 100 pF, Rb = 2.8 k 400 kHz 2.7 V  EVDD0 < 4.0 V, Cb = 100 pF, Rb = 2.7 k 400 kHz 1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V Note 1, Cb = 100 pF, Rb = 5.5 k 300 kHz Hold time when SCLr = “L” t LOW 4.0 V  EVDD0  5.5 V, Cb = 50 pF, Rb = 2.7 k 475 ns 2.7 V  EVDD0 < 4.0 V, Cb = 50 pF, Rb = 2.7 k 475 ns 4.0 V  EVDD0  5.5 V, Cb = 100 pF, Rb = 2.8 k 1150 ns 2.7 V  EVDD0 < 4.0 V, Cb = 100 pF, Rb = 2.7 k 1150 ns 1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V Note 1, Cb = 100 pF, Rb = 5.5 k 1550 ns Hold time when SCLr = “H” t HIGH 4.0 V  EVDD0  5.5 V, Cb = 50 pF, Rb = 2.7 k 245 ns 2.7 V  EVDD0 < 4.0 V, Cb = 50 pF, Rb = 2.7 k 200 ns 4.0 V  EVDD0  5.5 V, Cb = 100 pF, Rb = 2.8 k 675 ns 2.7 V  EVDD0 < 4.0 V, Cb = 100 pF, Rb = 2.7 k 600 ns 1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V Note 1, Cb = 100 pF, Rb = 5.5 k 610 ns

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 85 of 97 Feb 21, 2012 Note 1. Use it with EVDD0  Vb. Note 2. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”. Caution Select the TTL input buffer and the N-ch open drain output (EV DD0 tolerance) mode for the SDAr pin and the N-ch open drain output (EVDD0 tolerance) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). (Remarks are listed on the next page.) (10) Communication at different potential (2.5 V, 3 V) (simplified I2C mode) (TA = -40 to +85 C, 1.8 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Parameter Symbol Conditions MIN. MAX. Unit Data setup time (reception) tSU:DAT 4.0 V  EVDD0  5.5 V, Cb = 50 pF, Rb = 2.7 k 1/fMCK + 135 Note 2 ns 2.7 V  EVDD0 < 4.0 V, Cb = 50 pF, Rb = 2.7 k 1/fMCK + 135 Note 2 ns 4.0 V  EVDD0  5.5 V, Cb = 100 pF, Rb = 2.8 k 1/fMCK + 190 Note 2 ns 2.7 V  EVDD0 < 4.0 V, Cb = 100 pF, Rb = 2.7 k 1/fMCK + 190 Note 2 ns 1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V Note 1, Cb = 100 pF, Rb = 5.5 k 1/fMCK + 190 Note 2 ns Data hold time (transmission) tHD:DAT 4.0 V  EVDD0  5.5 V, Cb = 50 pF, Rb = 2.7 k 0 305 ns 2.7 V  EVDD0 < 4.0 V, Cb = 50 pF, Rb = 2.7 k 0 305 ns 4.0 V  EVDD0  5.5 V, Cb = 100 pF, Rb = 2.8 k 0 355 ns 2.7 V  EVDD0 < 4.0 V, Cb = 100 pF, Rb = 2.7 k 0 355 ns 1.8 V  EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V Note 1, Cb = 100 pF, Rb = 5.5 k 0 405 ns

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 86 of 97 Feb 21, 2012 Simplified I2C mode connection diagram (during communication at different potential) Simplified I2C mode serial transfer timing (during communication at different potential) Caution Select the TTL input buffer and the N-ch open drain output (EV DD0 tolerance) mode for the SDAr pin and the N-ch open drain output (EVDD0 tolerance) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. Rb[]: Communication line (SDAr, SCLr) pull-up resistance, C b[F]: Communication line (SDAr, SCLr) load capacitance, Vb[V]: Communication line voltage Remark 2. r: IIC number (r = 00, 01, 10, 11, 20, 30, 31), g: PIM, POM number (g = 0, 1, 3 to 5, 14) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0, 3), mn = 00 to 03, 10, 12, 13) Remark 4. VIH and V IL below are observation points for the AC characteri stics of the serial array unit when communicating at different potentials in simplified I2C mode. SDAr SCLr User’s device SDA SCL Vb Rb Vb Rb RL78/G14 SDAr SCLr 1/fSCL tLOW tHIGH tSU: DATtHD: DAT

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 87 of 97 Feb 21, 2012

2.5.2 Serial interface IICA

Note 1. The first clock pulse is generated after this period when the start/restart condition is detected. Note 2. The maximum value (MAX.) of t HD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Remark The maximum value of Cb (communication line capacitance) and the value of R b (communication line pull-up resistor) at that time in each mode are as follows. Standard mode: Cb = 400 pF, Rb = 2.7 k Fast mode: Cb = 320 pF, Rb = 1.1 k Fast mode plus: Cb = 120 pF, Rb = 1.1 k IICA serial transfer timing (TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions Standard Mode Fast Mode Fast Mode Plus Unit SCLA0 clock frequency f SCL Fast mode plus: f CLK  10 MHz 2.7 V  EVDD0  5.5 V 0 1000 kHz Fast mode: f CLK  3.5 MHz 1.8 V  EVDD0  5.5 V 0 400 kHz Normal mode: f CLK  1 MHz 1.6 V  EVDD0  5.5 V 0 100 kHz Setup time of restart condition Note 1 tSU:STA 4.7 0.6 0.26 s Hold time t HD:STA 4.0 0.6 0.26 s Hold time when SCLA0 = “L” t LOW 4.7 1.3 0.5 s Hold time when SCLA0 = “H” t HIGH 4.0 0.6 0.26 s Data setup time (reception) t SU:DAT 250 100 50 ns Data hold time (transmission) Note 2 tHD:DAT 03 . 4 50 0 . 9 0 s Setup time of stop condition t SU:STO 4.0 0.6 0.26 s Bus-free time t BUF 4.7 1.3 0.5 s tSU: DATtHD: STA Restart condition SCL0 SDA0 tLOW tHIGH tSU: STA tHD: STA tSU: STO Stop condition Stop condition Start condition tHD: DAT tLOW

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 88 of 97 Feb 21, 2012

2.5.3 On-chip debug (UART)

2.6 Analog Characteristics

2.6.1 A/D converte r characteristics

Note 1. Excludes quantization error (±1/2 LSB). Note 2. This value is indicated as a ratio (% FSR) to the full-scale value. (TA = -40 to +85 C, 1.8 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate 115.2 k 1 M bps (1) When AV REF (+) = AV REFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), AV REF (-) = AV REFM/ANI1 (ADREFM = 1), target ANI pin: ANI2 to ANI14 (supply ANI pin to VDD) (TA = -40 to +85  C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = AVREFP , Reference voltage (-) = AVREFM = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 81 0 bit Overall error Notes 1, 2 AINL 10-bit resolution AVREFP = VDD 1.8 V  VDD  5.5 V 1.2 3.5 LSB 1.6 V  VDD  5.5 V 1.2 7.0 LSB Conversion time t CONV 10-bit resolution AVREFP = VDD 3.6 V  VDD  5.5 V 2.125 39 s 2.7 V  VDD  5.5 V 3.1875 39 s 1.8 V  VDD  5.5 V 17 39 s 1.6 V  VDD  5.5 V 57 95 s Zero-scale error Notes 1, 2 EZS 10-bit resolution AVREFP = VDD 1.8 V  VDD  5.5 V 0.25 % FSR 1.6 V  VDD < 5.5 V 0.50 % FSR Full-scale error Notes 1, 2 EFS 10-bit resolution AVREFP = VDD 1.8 V  VDD  5.5 V 0.25 % FSR 1.6 V  VDD  5.5 V 0.50 % FSR Integral linearity error Note 1 ILE 10-bit resolution AVREFP = VDD 1.8 V  VDD  5.5 V 2.5 LSB 1.6 V  VDD  5.5 V 5.0 LSB Differential linearity error Note 1 DLE 10-bit resolution AVREFP = VDD 1.8 V  VDD  5.5 V 1.5 LSB 1.6 V  VDD  5.5V 2.0 LSB Reference voltage (+) AV REFP 1.6 VDD V Analog input voltage V AIN 0A VREFP V VBGR 2.4 V  VDD < 5.5 V, HS (high-speed main) mode 1.38 1.45 1.5 V

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 89 of 97 Feb 21, 2012 Note 1. Excludes quantization error (±1/2 LSB). Note 2. This value is indicated as a ratio (% FSR) to the full-scale value. (2) When AV REF (+) = AV REFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), AV REF (-) = AV REFM/ANI1 (ADREFM = 1), target ANI pin: ANI16 to ANI20 (supply ANI pin to EVDD0) (TA = -40 to +85  C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = AVREFP , Reference voltage (-) = AVREFM = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 81 0 bit Overall error Notes 1, 2 AINL 10-bit resolution AVREFP = VDD 1.8 V  VDD  5.5 V 1.2 5.0 LSB 1.6 V  VDD  5.5 V 1.2 8.5 LSB Conversion time t CONV 10-bit resolution AVREFP = VDD 3.6 V  VDD  5.5 V 2.125 39 s 2.7 V  VDD  5.5 V 3.1875 39 s 1.8 V  VDD  5.5 V 17 39 s 1.6 V  VDD  5.5 V 57 95 s Zero-scale error Notes 1, 2 EZS 10-bit resolution AVREFP = VDD 1.8 V  VDD  5.5 V 0.35 % FSR 1.6 V  VDD  5.5 V 0.60 % FSR Full-scale error Notes 1, 2 EFS 10-bit resolution AVREFP = VDD 1.8 V  VDD  5.5 V 0.35 % FSR 1.6 V  VDD  5.5 V 0.60 % FSR Integral linearity error Note 1 ILE 10-bit resolution AVREFP = VDD 1.8 V  VDD  5.5 V 3.5 LSB 1.6 V  VDD  5.5 V 6.0 LSB Differential linearity error Note 1 DLE 10-bit resolution AVREFP = VDD 1.8 V  VDD  5.5 V 2.0 LSB 1.6 V  VDD  5.5 V 2.5 LSB Reference voltage (+) AV REFP 1.6 VDD V Analog input voltage V AIN AVREFP and EVDD0 V VBGR 2.4 V  VDD  5.5 V, HS (high-speed main) mode 1.38 1.45 1.5 V

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 90 of 97 Feb 21, 2012 Note 1. Excludes quantization error (±1/2 LSB). Note 2. This value is indicated as a ratio (% FSR) to the full-scale value. (3) When AV REF (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), AVREF (-) = VSS (ADREFM = 0), target ANI pin: ANI0 to ANI14, ANI16 to ANI20 (TA = -40 to +85 °C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = VDD, Reference voltage (-) = VSS) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 81 0 bit Overall error Notes 1, 2 AINL 10-bit resolution 1.8 V  VDD  5.5 V 1.2 7.0 LSB 1.6 V  VDD  5.5 V 1.2 10.5 LSB Conversion time t CONV 10-bit resolution 3.6 V  VDD  5.5 V 2.125 39 s 2.7 V  VDD  5.5 V 3.1875 39 s 1.8 V  VDD  5.5 V 17 39 s 1.6 V  VDD  5.5 V 57 95 s Zero-scale error Notes 1, 2 EZS 10-bit resolution 1.8 V  VDD  5.5 V 0.60 % FSR 1.6 V  VDD  5.5 V 0.85 % FSR Full-scale error Notes 1, 2 EFS 10-bit resolution 1.8 V  VDD  5.5 V 0.60 % FSR 1.6 V  VDD  5.5 V 0.85 % FSR Integral linearity error Note 1 ILE 10-bit resolution 1.8 V  VDD  5.5 V 4.0 LSB 1.6 V  VDD  5.5 V 6.5 LSB Differential linearity error Note 1 DLE 10-bit resolution 1.8 V  VDD  5.5 V 2.0 LSB 1.6 V  VDD  5.5 V 2.5 LSB Analog input voltage V AIN ANI0 to ANI14 0 VDD V ANI16 to ANI20 0 EV DD0 V VBGR 2.4 V  VDD  5.5 V, HS (high-speed main) mode 1.38 1.45 1.5 V

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 91 of 97 Feb 21, 2012 Note 1. Excludes quantization error (±1/2 LSB). Note 2. This value is indicated as a ratio (% FSR) to the full-scale value. (4) When AV REF (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), AV REF (-) = AV REFM/ANI1 (ADREFM = 1), target ANI pin: ANI0 to ANI14, ANI16 to ANI20 (TA = -40 to +85 °C, 2.4 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = VBGR, Reference voltage (-) = AVREFM = 0 V, HS (high-speed main) mode) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 8b it Conversion time tCONV 8-bit resolution 2.4 V  VDD  5.5 V 17 39 s Zero-scale error Notes 1, 2 EZS 8-bit resolution 2.4 V  VDD  5.5 V 0.60 % FSR Integral linearity error Note 1 ILE 8-bit resolution 2.4 V  VDD  5.5 V 2.0 LSB Differential linearity error Note 1 DLE 8-bit resolution 2.4 V  VDD  5.5 V 1.0 LSB Reference voltage (+) V BGR 1.38 1.45 1.5 V Reference voltage (-) AV REFM VSS V Analog input voltage V AIN 0V BGR V

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 92 of 97 Feb 21, 2012

2.6.2 Temperature sens or characteristics

2.6.3 D/A converter characteristics

(TA = -40 to +85 °C, 2.4 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V, HS (high-speed main) mode) Parameter Symbol Conditions MIN. TYP . MAX. Unit Temperature sensor output voltage V TMPS25 Setting ADS register = 80H, TA = +25 C1 .05 V Reference output voltage V CONST Setting ADS register = 81H 1.38 1.45 1.5 V Temperature coefficient FVTMPS Temperature sensor that depends on the temperature -3.6 mV/C Operation stabilization wait time t AMP 5 s (TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 8b i t Overall error AINL Rload = 4 M  1.8 V  VDD  5.5 V 2.5 LSB Rload = 8 M 1.8 V  VDD  5.5 V 2.5 LSB Settling time t SET Cload = 20 pF 2.7 V  VDD  5.5 V 3 s 1.6 V  VDD < 2.7 V 6 s

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 93 of 97 Feb 21, 2012

2.6.4 Comparator

2.6.5 POR circuit characteristics

(TA = -40 to +85 C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP . MAX. Unit Input voltage range Ivref 0 EVDD0 - 1.4 V Ivcmp -0.3 EVDD0 + 0.3 V Output delay td V DD = 3.0 V Input slew rate > 50 mV/s High-speed comparator mode, standard mode 1.2 s High-speed comparator mode, window mode 2.0 Low-speed comparator mode, standard mode High-electric-potential judgment voltage VTW+ High-speed comparator mode, window mode 0.76 V DD V Low-electric-potential judgment voltage VTW- High-speed comparator mode, window mode 0.24 V DD V (TA = -40 to +85 C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage VPOR Power supply rise time 1.51 1.54 V VPDR Power supply fall time 1.50 1.53 V Minimum pulse width T PW 300 s Detection delay time 350 s

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 94 of 97 Feb 21, 2012

2.6.6 LVD circuit characteristics

Caution Set the detection voltage (V LVI) to be within the operating voltage range. The operating voltage range depends on the setting of the user option byte (000C2H/010C2H). The following shows the operating voltage range. HS (high-speed main) mode: V DD = 2.7 to 5.5 V@1 MHz to 32 MHz VDD = 2.4 to 5.5 V@1 MHz to 16 MHz LS (low-speed main) mode: V DD = 1.8 to 5.5 V@1 MHz to 8 MHz LV (low voltage main) mode: V DD = 1.6 to 5.5 V@1 MHz to 4 MHz Remark VLVI (n - 1) > VLVIn: n = 1 to 13 (TA = -40 to +85 C, VPDR  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage Supply voltage level V LVI0 Power supply rise time 3.98 4.06 4.14 V Power supply fall time 3.90 3.98 4.06 V VLVI1 Power supply rise time 3.68 3.75 3.82 V Power supply fall time 3.60 3.67 3.74 V VLVI2 Power supply rise time 3.07 3.13 3.19 V Power supply fall time 3.00 3.06 3.12 V VLVI3 Power supply rise time 2.96 3.02 3.08 V Power supply fall time 2.90 2.96 3.02 V VLVI4 Power supply rise time 2.86 2.92 2.97 V Power supply fall time 2.80 2.86 2.91 V VLVI5 Power supply rise time 2.76 2.81 2.87 V Power supply fall time 2.70 2.75 2.81 V VLVI6 Power supply rise time 2.66 2.71 2.76 V Power supply fall time 2.60 2.65 2.70 V VLVI7 Power supply rise time 2.56 2.61 2.66 V Power supply fall time 2.50 2.55 2.60 V VLVI8 Power supply rise time 2.45 2.50 2.55 V Power supply fall time 2.40 2.45 2.50 V VLVI9 Power supply rise time 2.05 2.09 2.13 V Power supply fall time 2.00 2.04 2.08 V VLVI10 Power supply rise time 1.94 1.98 2.02 V Power supply fall time 1.90 1.94 1.98 V VLVI11 Power supply rise time 1.84 1.88 1.91 V Power supply fall time 1.80 1.84 1.87 V VLVI12 Power supply rise time 1.74 1.77 1.81 V Power supply fall time 1.70 1.73 1.77 V VLVI13 Power supply rise time 1.64 1.67 1.70 V Power supply fall time 1.60 1.63 1.66 V Minimum pulse width tLW 300 s Detection delay time t LD 300 s

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 95 of 97 Feb 21, 2012 Caution Set the detection voltage (V LVI) to be within the operating voltage range. The operating voltage range depends on the setting of the user option byte (000C2H/010C2H). The following shows the operating voltage range. HS (high-speed main) mode: V DD = 2.7 to 5.5 V@1 MHz to 32 MHz VDD = 2.4 to 5.5 V@1 MHz to 16 MHz LS (low-speed main) mode: V DD = 1.8 to 5.5 V@1 MHz to 8 MHz LV (low voltage main) mode: V DD = 1.6 to 5.5 V@1 MHz to 4 MHz LVD Detection Voltage of Interrupt & Reset Mode (TA = -40 to +85 C, VPDR  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Interrupt and reset mode VLVI13 VPOC0, VPOC1, VPOC2 = 0, 0, 0, falling reset voltage: 1.6 V 1.60 1.63 1.66 V VLVI12 LVIS0, LVIS1 = 1, 0 (+0.1 V) Rising release reset voltage 1.74 1.77 1.81 V Falling interrupt voltage 1.70 1.73 1.77 V V LVI11 LVIS0, LVIS1 = 0, 1 (+0.2 V) Rising release reset voltage 1.84 1.88 1.91 V Falling interrupt voltage 1.80 1.84 1.87 V VLVI4 LVIS0, LVIS1 = 0, 0 (+1.2 V) Rising release reset voltage 2.86 2.92 2.97 V Falling interrupt voltage 2.80 2.86 2.91 V VLVI11 VPOC0, VPOC1, VPOC2 = 0, 0, 1, falling reset voltage: 1.8 V 1.80 1.84 1.87 V VLVI10 LVIS0, LVIS1 = 1, 0 (+0.1 V) Rising release reset voltage 1.94 1.98 2.02 V Falling interrupt voltage 1.90 1.94 1.98 V VLVI9 LVIS0, LVIS1 = 0, 1 (+0.2 V) Rising release reset voltage 2.05 2.09 2.13 V Falling interrupt voltage 2.00 2.04 2.08 V VLVI2 LVIS0, LVIS1 = 0, 0 (+1.2 V) Rising release reset voltage 3.07 3.13 3.19 V Falling interrupt voltage 3.00 3.06 3.12 V VLVI8 VPOC0, VPOC1, VPOC2 = 0, 1, 0, falling reset voltage: 2.4 V 2.40 2.45 2.50 V VLVI7 LVIS0, LVIS1 = 1, 0 (+0.1 V) Rising release reset voltage 2.56 2.61 2.66 V Falling interrupt voltage 2.50 2.55 2.60 V VLVI6 LVIS0, LVIS1 = 0, 1 (+0.2 V) Rising release reset voltage 2.66 2.71 2.76 V Falling interrupt voltage 2.60 2.65 2.70 V VLVI1 LVIS0, LVIS1 = 0, 0 (+1.2 V) Rising release reset voltage 3.68 3.75 3.82 V Falling interrupt voltage 3.60 3.67 3.74 V V LVI5 VPOC0, VPOC1, VPOC2 = 0, 1, 1, falling reset voltage: 2.7 V 2.70 2.75 2.81 V VLVI4 LVIS0, LVIS1 = 1, 0 (+0.1 V) Rising release reset voltage 2.86 2.92 2.97 V Falling interrupt voltage 2.80 2.86 2.91 V VLVI3 LVIS0, LVIS1 = 0, 1 (+0.2 V) Rising release reset voltage 2.96 3.02 3.08 V Falling interrupt voltage 2.90 2.96 3.02 V VLVI0 LVIS0, LVIS1 = 0, 0 (+1.2 V) Rising release reset voltage 3.98 4.06 4.14 V Falling interrupt voltage 3.90 3.98 4.06 V

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 96 of 97 Feb 21, 2012

2.7 Power Supply Rise Time

2.8 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics

Note The value depends on the POR detection voltage. When the vo ltage drops, the data is retained before a POR reset is effected, but data is not retained when a POR reset is effected.

2.9 Flash Memory Programming Characteristics

Note When using flash memory programmer and Renesas Electronics self programming library. Remark When updating data multiple times, use the flash memory as one for updating data. (TA = -40 to +85 C, VSS = EVSS0 = EVSS1 = 0 V) Parameter Conditions MIN. TYP. MAX. Unit VDD rise inclination T PUP 53.0 V/ms (TA = -40 to +85 C) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention supply voltage VDDDR 1.5 Note 5.5 V (TA = -40 to +85 C, 1.8 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP . MAX. Unit CPU/peripheral hardware clock frequency f CLK 1.8 V  VDD  5.5 V 13 2 M H z Number of code flash rewrites C erwr 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. Retained for 20 years (Self/serial programming) Note 1,000 Times Number of data flash rewrites Retained for 1 years (Self/serial programming) Note 1,000,000 Retained for 5 years (Self/serial programming) Note 100,000 VDD STOP instruction execution Standby release signal (interrupt request) STOP mode Data retention mode Operation mode VDDDR

RL78/G14 2. ELECTRICAL SPECIFICATIONS R01DS0053EJ0100 Rev. 1.00 Page 97 of 97 Feb 21, 2012

2.10 Timing Specs for Switching Modes

<1> The low level is input to the TOOL0 pin. <2> The pins reset ends (POR and LVD reset must end before the pin reset ends.). <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from when the external and internal resets end. t SU: How long from when the TOOL0 pin is placed at the low level until a pin reset ends tHD: How long to keep the TOOL0 pin at the low level from when the external and internal resets end Parameter Symbol Conditions MIN. TYP. MAX. Unit How long from when a pin reset ends until the initial communication settings are specified t SUINIT POR and LVD reset must end before the pin reset ends. 100 ms How long from when the TOOL0 pin is placed at the low level until a pin reset ends t SU POR and LVD reset must end before the pin reset ends. How long the TOOL0 pin must be kept at the low level after a reset ends tHD POR and LVD reset must end before the pin reset ends. 1m s RESET TOOL0 tSU <4> tSUINIT tHD+ software processing time

SuperFlash is a registered trademar k of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Rev. Date

Description

0.01 Feb 10, 2011 — First Edition issued

0.02 May 01, 2011 1 to 2 1.1 Features revised 3 1.2 Ordering Information revised 4 to 13 1.3 Pin Configuration (Top View) revised 14 1.4 Pin Identif ication revised 15 to 17 1.5.1 30-pin products to 1.5.3 36-pin products revised 23 to 26 1.6 Outline of Functions revised 0.03 Jul 28, 2011 1 1.1 Features revised 1.00 Feb 21, 2012 1 to 40 1. OUTLINE revised 41 to 97 2. ELECTRICAL SPECIFICATIONS added All trademarks and registered trademarks are the property of their respective owners. Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.

REVISION HISTORY

(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). (2) HANDLING OF UNUSED INPUT PINS: Unconnected CM OS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an in ternal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resist or if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) PRECAUTION AGAINST ESD: A strong electric fi eld, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade t he device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequat e. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be gr ounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touc hed with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. (4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the in itial status of a MOS device. Immediately after the power source is turn ed ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O setti ngs or contents of registers. A device is not initialized un til the reset signal is received. A re set operation must be executed immediately after power-on for devices with reset functions. (5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the po wer supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal cu rrent that passes in the device at this time may cause degradation of internal elem ents. Input of signals during th e power off state must be judged separately for each device and according to related specifications governing the device.

All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. 2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part . 4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics. The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc. "Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically designed for life support. "Specific": Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. 8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. 9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. 12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. http://www.renesas.com Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A. Renesas Electronics Canada Limited

1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada

Renesas Electronics Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K Tel: +44-1628-585-100, Fax: +44-1628-585-900 Renesas Electronics Europe GmbH Arcadiastrasse 10, 40472 Düsseldorf, Germany Tel: +49-211-65030, Fax: +49-211-6503-1327 Renesas Electronics (China) Co., Ltd. 7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China Tel: +86-10-8235-1155, Fax: +86-10-8235-7679 Renesas Electronics (Shanghai) Co., Ltd. Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898 Renesas Electronics Hong Kong Limited Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong Tel: +852-2886-9318, Fax: +852 2886-9022/9044 Renesas Electronics Taiwan Co., Ltd. 13F, No. 363, Fu Shing North Road, Taipei, Taiwan Tel: +886-2-8175-9600, Fax: +886 2-8175-9670 Renesas Electronics Singapore Pte. Ltd. 1 harbourFront Avenue, #06-10, keppel Bay Tower, Singapore 098632 Tel: +65-6213-0200, Fax: +65-6278-8001 Renesas Electronics Malaysia Sdn.Bhd. Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Renesas Electronics Korea Co., Ltd. 11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea SALES OFFICES © 2012 Renesas Electronics Corporation. All rights reserved. Colophon 1.1

Product Information

RL78 specifications and overview.

Summary

True Low Power Platform (as low as 66 ?쵡/MHz, and 0.60 ?쵡 for RTC + LVD), 1.6 V to 5.5 V operation

Description

True Low Power Platform (as low as 66 ?쵡/MHz, and 0.60 ?쵡 for RTC + LVD), 1.6 V to 5.5 V operation

Source title RL78 Datasheet(PDF) - Renesas Technology Corp

Related Parts

More parts from the same family.

Browse manufacturer