RL78-G12

RL78-G12_V01 RENESAS | Alldatasheet

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Technical content

True low-power platform (63 μA/MHz) for the general-purpose applications, with 1.8-V to 5.5-V operation, 2- to 16-Kbyte code flash memory, and 31 DMIPS at 24 MHz R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 1 of 109 R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 1. OUTLINE

1.1 Features

Ultra-low power consumption technology  V DD = single power supply voltage of 1.8 to 5.5 V which can operate at a low voltage  HALT mode  STOP mode  SNOOZE mode RL78 CPU core  CISC architecture with 3-stage pipeline  Minimum instruction execution time: Can be changed from high speed (0.04167 s: @ 24 MHz operation with high-speed on-chip oscillator) to ultra-low speed (1 s: @ 1 MHz operation)  Address space: 1 MB  General-purpose registers: (8 -bit register x 8) x 4 banks  On-chip RAM: 256 B to 2 KB Code flash memory  Code flash memory: 2 to 16 KB  Block size: 1 KB  Prohibition of block erase and rewriting (security function)  On-chip debug function  Self-programming (with flash shield window function) Data flash memory Note2  Data flash memory: 2 KB  Back ground operation (BGO): Instructions are executed from the program memory while rewriting the data flash memory.  Number of rewrites: 1,000,000 times (TYP.)  Voltage of rewrites: V DD = 1.8 to 5.5 V High-speed on-chip oscillator  Select from 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz,

4 MHz, 3 MHz, 2 MHz, and 1 MHz

 High accuracy: +/- 1.0 % (V DD = 1.8 to 5.5 V, TA = -20 to +85 °C) Operating ambient temperature  T A = -40 to +85 °C (A: Consumer applications, D: Industrial applications)  T A = -40 to +105 °C (G: Industrial applications) Note2 Power management and reset function  On-chip power-on-reset (POR) circuit  On-chip voltage detector (LVD) (Select interrupt and reset from 12 levels) DMA (Direct Memory Access) controller Note2  2 channels  Number of clocks during transfer between 8/16-bit SFR and internal RAM: 2 clocks Multiplier and divider/multiply-accumulator  16 bits x 16 bits = 32 bits (Unsigned or signed)  32 bits x 32 bits = 32 bits (Unsigned)  16 bits x 16 bits + 32 bits = 32 bits (Unsigned or signed) Serial interface  Simplified SPI (CSI Note1): : 1 to 3 channels  UART : 1 to 3 channels  Simplified I 2C communication : 0 to 3 channels  I 2C communication : 1 channel Timer  16-bit timer : 4 to 8 channels  12-bit interval timer : 1 channel  Watchdog timer : 1 channel (operable with the dedicated low-speed on-chip oscillator) A/D converter  8/10-bit resolution A/D converter (V DD = 1.8 to 5.5 V)  8 to 11 channels, internal reference voltage (1.45 V), and temperature sensor Note2 I/O port  I/O port: 18 to 26 (N-ch open drain I/O [withstand voltage of 6 V]: 2, N-ch open drain I/O [VDD withstand voltage]: 4 to 9)  Can be set to N-ch open drain, TTL input buffer, and on-chip pull-up resistor  Different potential interface: Can connect to a 1.8/2.5/3 V device  On-chip key interrupt function  On-chip clock output/buzzer output controller Others  On-chip BCD (binary-coded decimal) correction circuit Note 1. Although the CSI function is generally called SPI, it is also called CSI in this product, so it is referred to as such in this manual. Note 2. Can be selected only in HS (high-speed main) mode. Remark The functions mounted depend on the product. See 1.7 Outline of Functions.

RL78/G12 1. OUTLINE R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 2 of 109 Օ ROM, RAM capacities Code flash Data flash RAM 20 pins 24 pins 30 pins

16 KB 2 KB 2 KB – – R5F102AA

– – – R5F103AA 2 KB 1.5 KB R5F1026A Note 1 R5F1027A Note 1 – – R5F1036A Note 1 R5F1037A Note 1 –

12 KB 2KB 1 KB R5F10269 Note 1 R5F10279 Note 1 R5F102A9

– R5F10369 Note 1 R5F10379 Note 1 R5F103A9

8 KB 2 KB 768 B R5F10268 Note 1 R5F10278 Note 1 R5F102A8

– R5F10368 Note 1 R5F10378 Note 1 R5F103A8

4 KB 2KB 512 B R5F10267 R5F10277 R5F102A7

– R5F10367 R5F10377 R5F103A7

2 KB 2 KB 256 B R5F10266 Note 2 – –

– R5F10366 Note 2 – – Notes 1. This is 640 bytes when the self-programming functi on or data flash function is used. (For details, see CHAPTER 3 CPU ARCHITECTURE in the RL78/G12 User’s Manual.) 2. The self-programming function cannot be used for R5F10266 and R5F10366. Caution When the flash memory is rewritten via a user program, the code flash area and RAM area are used because each library is used. When using the library, refer to RL78 Family Flash Self Programming Library Type01 User's Manual and RL78 Family Data Flash Library Type04 User's Manual.

RL78/G12 1. OUTLINE R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 3 of 109

1.2 List of Part Numbers

Figure 1-1. Part Number, Memory Size, and Package of RL78/G12 R 5 F 1 0 2 A A A x x x S P #V0 Package type: ROM number (Omitted with blank products) ROM capacity: RL78/G12 group Renesas MCU Renesas semiconductor product SM: TSSOP, 0.65-mm pitch SP: LSSOP, 0.65-mm pitch NA: HWQFN, 0.50-mm pitch #U5, #05, #25, #65: Tray (HWQFN) #V0, #10, #30 #70: Tray (LSSOP30) #V5: Tube (LSSOP20) #15, #75: Tray (TSSOP20) #35: Tray (TSSOP20), Tube (LSSOP20) #W5, #45: Embossed Tape (HWQFN) #X0, #50: Embossed Tape (LSSOP30) #X5: Embossed Tape (LSSOP20) #55: Embossed Tape (LSSOP20, TSSOP20) #5F: Embossed Tape (TSSOP20) #9F: Tube (TSSOP20) 6: 2 KB 7: 4 KB 8: 8 KB 9: 12 KB A: 16 KB Pin count: 6: 20-pin 7: 24-pin A: 30-pin Fields of application: A: Consumer applications, T A = -40°C to +85°C D: Industrial applications, T A = -40°C to +85°C G: Industrial applications, T A = -40°C to +105°C Memory type: F: Flash memory Packaging specifications: 102 Note 1 103 Notes 1, 2 Ordering part number Product name Notes 1. For details about the differences between the R5 F102 products and the R5F103 products of RL78/G12, see 1.3 Differences between the R5F102 Products and the R5F103 Products. 2. Products only for “A: Consumer applications (TA = -40 to +85°C)” and “D: Industrial applications (TA = -40 to +85°C)” <R>

RL78/G12 1. OUTLINE R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 4 of 109 Table 1-1. List of Ordering Part Numbers Pin count Package Data flash Fields of Application Note Ordering Part Number RENESAS Code Product Name Packaging Specifications pins 20-pin plastic LSSOP (4.4 × 6.5 mm, 0.65- mm pitch) Mounted A R5F1026AASP, R5F10269ASP, R5F10268ASP, R5F10267ASP, R5F10266ASP #V5, #35, #X5, #55 PLSP0020JB-A D R5F1026ADSP, R5F10269DSP, R5F10268DSP, R5F10267DSP, R5F10266DSP G R5F1026AGSP, R5F10269GSP, R5F10268GSP, R5F10267GSP, R5F10266GSP Not mounted A R5F1036AASP, R5F10369ASP, R5F10368ASP, R5F10367ASP, R5F10366ASP #V5, #35, #X5, #55 PLSP0020JB-A D R5F1036ADSP, R5F10369DSP, R5F10368DSP, R5F10367DSP, R5F10366DSP 20-pin plastic TSSOP (4.4 x 6.5 mm, 0.65- mm pitch) Mounted A R5F10269ASM, R5F10268ASM, R5F10267ASM, R5F10266ASM #15, #35, #55, #75 PTSP0020JI-A R5F1026AASM #15, #35, #55, #5F, #75, #9F PTSP0020JI-A G R5F10269GSM, R5F10268GSM, R5F10267GSM, R5F10266GSM #15, #35, #55, #75 PTSP0020JI-A R5F1026AGSM #15, #35, #55, #5F, #75, #9F PTSP0020JI-A Not mounted A R5F1036AASM, R5F10369ASM, R5F10368ASM, R5F10367ASM, R5F10366ASM #15, #35, #55, #75 PTSP0020JI-A pins 24-pin plastic HWQFN (4 × 4 mm, 0.5-mm pitch) Mounted A R5F1027AANA, R5F10279ANA, R5F10278ANA, R5F10277ANA #U5, #W5 PWQN0024KE-A R5F1027AANA, R5F10279ANA, R5F10278ANA, R5F10277ANA #05, #25, #45, #65 PWQN0024KF-A PWQN0024KH-A D R5F1027ADNA, R5F10279DNA, R5F10278DNA, R5F10277DNA #U5, #W5 PWQN0024KE-A G R5F1027AGNA, R5F10279GNA, R5F10278GNA, R5F10277GNA R5F1027AGNA, R5F10279GNA, R5F10278GNA, R5F10277GNA #05, #25, #45, #65 PWQN0024KF-A PWQN0024KH-A Not mounted A R5F1037AANA, R5F10379ANA, R5F10378ANA, R5F10377ANA #U5, #W5 PWQN0024KE-A R5F1037AANA, R5F10379ANA, R5F10378ANA, R5F10377ANA #05, #25, #45, #65 PWQN0024KF-A PWQN0024KH-A D R5F1037ADNA, R5F10379DNA, R5F10378DNA, R5F10377DNA #U5, #W5 PWQN0024KE-A pins 30-pin plastic LSSOP (7.62 mm (300), 0.65- mm pitch) Mounted A R5F102AAASP, R5F102A9ASP, R5F102A8ASP, R5F102A7ASP #V0, #10, #30, #X0, #50, #70 PLSP0030JB-B D R5F102AADSP, R5F102A9DSP, R5F102A8DSP, R5F102A7DSP G R5F102AAGSP, R5F102A9GSP, R5F102A8GSP, R5F102A7GSP Not mounted A R5F103AAASP, R5F103A9ASP, R5F103A8ASP, R5F103A7ASP #V0, #10, #30, #X0, #50, #70 PLSP0030JB-B D R5F103AADSP, R5F103A9DSP, R5F103A8DSP, R5F103A7DSP Note For fields of application, see Figure 1-1 Part Number, Memory Size, and Package of RL78/G12. Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. <R> <R> <R> <R>

RL78/G12 1. OUTLINE R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 5 of 109

1.3 Differences between the R5F102 Products and the R5F103 Products

The following are differences between the R5F102 products and the R5F103 products. Օ Whether the data flash memory is mounted or not Օ High-speed on-chip oscillator oscillation frequency accuracy Օ Number of channels in serial interface Օ Whether the DMA function is mounted or not Օ Whether a part of the safety functions are mounted or not

1.3.1 Data Flash

The data flash memory of 2 KB is mounted on the R5F102 products, but not on the R5F103 products. Product Data Flash R5F102 products R5F1026A, R5F1027A, R5F102AA, R5F10269, R5F10279, R5F102A9, R5F10268, R5F10278, R5F102A8, R5F10267, R5F10277, R5F102A7, R5F10266 Note 2 KB R5F103 products R5F1036A, R5F1037A, R5F103AA, R5F10369, R5F10379, R5F103A9, R5F10368, R5F10378 R5F103A8, R5F10367, R5F10377, R5F103A7, R5F10366 Not mounted Note The RAM in the R5F10266 has capacity as small as 256 bytes. Depending on the customer's program specification, the stack area to execute the data flash library may not be kept and data may not be written to or erased from the data flash memory. Caution When the flash memory is rewritten via a user program, the code flash area and RAM area are used because each library is used. When using the library, refer to RL78 Family Flash Self Programming Library Type01 User's Manual and RL78 Family Data Flash Library Type04 User's Manual.

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1.3.2 On-chip oscillator characteristics

(1) High-speed on-chip oscillator oscillation frequency of the R5F102 products Oscillator Condition MIN MAX Unit High-speed on-chip oscillator oscillation frequency accuracy (2) High-speed on-chip oscillator oscillation frequency of the R5F103 products Oscillator Condition MIN MAX Unit High-speed on-chip oscillator oscillation frequency accuracy

1.3.3 Peripheral Functions

The following are differences in peripheral functions between the R5F102 products and the R5F103 products. RL78/G12 R5F102 product R5F103 product 20, 24 pin product 30 pin product 20, 24 pin product 30 pin product Serial interface UART 1 channel 3 channels 1 channel Simplified SPI (CSI) 2 channels 3 channels 1 channel Simplified I2C 2 channels 3 channels None DMA function 2 channels None Safety function CRC operation Yes None RAM guard Yes None SFR guard Yes None

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1.4 Pin Configuration (Top View)

1.4.1 20-pin products

• 20-pin plastic LSSOP (4.4 × 6.5 mm, 0.65-mm pitch)
• 20-pin plastic TSSOP (4.4 × 6.5 mm, 0.65-mm pitch) P21/ANI1/AVREFM P22/ANI2 P23/ANI3 P10/ANI16/PCLBUZ0/SCK00/SCL00 P11/ANI17/SI00/RxD0/SDA00 /TOOLRxD P12/ANI18/SO00/TxD0/TOOLTxD P13/ANI19/TI00/TO00/INTP2 P14/ANI20/TI01/TO01/INTP3 P61/KR5/SDAA0/(RxD0) P60/KR4/SCLA0/(TxD0) P20/ANI0/AV REFP P40/KR0/TOOL0 P137/INTP0 P122/KR2/X2/EXCLK/(TI02)/(INTP2) P121/KR3/X1/(TI03)/(INTP3) VSS VDD P42/ANI21/SCK01 /SCL01 NoteNote /TI03/TO03 P41/ANI22/SO01 /SDA01 NoteNote /TI02/TO02/INTP1 P125/KR1/SI01 /RESETNote Note Note RL78/G12 (Top View) Note Provided only in the R5F102 products. Remarks 1. For pin identification, see 1.5 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G12 User’s Manual.

RL78/G12 1. OUTLINE R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 8 of 109 1.4.2 24-pin products

• 24-pin plastic HWQFN (4 × 4 mm, 0.5-mm pitch) 12 34 5 6 18 17 16 15 14 13 P61/KR5/SDAA0/(RxD0) P60/KR4/SCLA0/(TxD0) P03/KR9 P02/KR8/(SCK01) Note /(SCL01) Note P01/KR7/(SO01) Note /(SDA01) Note P00/KR6/(SI01) Note P22/ANI2 P21/ANI1/AVREFM P20/ANI0/AVREFP P42/ANI21/SCK01 Note /SCL01 Note /TI03/TO03 P41/ANI22/SO01 Note /SDA01 Note /TI02/TO02/INTP1 P40/KR0/TOOL0 INDEX MARK exposed die pad VDD VSS P122/KR2/X2/EXCLK/(TI02)/(INTP2) P121/KR3/X1/(TI03)/(INTP3) P137/INTP0 P125/KR1/SI01 Note /RESET P14/ANI20/TO01/INTP3 P13/ANI19/TO00/INTP2 P11/ANI17/SI00/RxD0/SDA00 Note /TOOLRxD P12/ANI18/SO00/TxD0/TOOLTxD P10/ANI16/PCLBUZ0/SCK00/SCL00 Note P23/ANI3 RL78/G12 (Top View) Note Provided only in the R5F102 products. Remarks 1. For pin identification, see 1.5 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G12 User’s Manual. 3. It is recommended to connect an exposed die pad to Vss.

RL78/G12 1. OUTLINE R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 9 of 109 1.4.3 30-pin products

• 30-pin plastic LSSOP (7.62 mm (300), 0.65-mm pitch) P20/ANI0/AVREFP P01/ANI16/TO00/RxD1Note P00/ANI17/TI00/TxD1Note P120/ANI19 P40/TOOL0 RESET P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P60/SCLA0 P61/SDAA0 P31/TI03/TO03/INTP4/PCLBUZ0 P21/ANI1/AVREFM P22/ANI2 P23/ANI3 P147/ANI18 P10/SCK00/SCL00Note/(TI07/TO07) P11/SI00/RxD0/TOOLRxD/SDA00Note/(TI06/TO06) P13/TxD2Note/SO20Note/(SDAA0)Note/(TI04/TO04) P14/RxD2Note/SI20Note/SDA20Note/(SCLA0)Note/(TI03/TO03) P15/PCLBUZ1/SCK20Note/SCL20Note/(TI02/TO02) P12/SO00/TxD0/TOOLTxD/(TI05/TO05) P16/TI01/TO01/INTP5/(RxD0) P17/TI02/TO02/(TxD0) P30/INTP3/SCK11Note/SCL11Note P50/INTP1/SI11Note/SDA11Note P51/INTP2/SO11Note RL78/G12 (Top View) Note Provided only in the R5F102 products. Caution Connect the REGC pin to V SS via capacitor (0.47 to 1 µF). Remarks 1. For pin identification, see 1.5 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G12 User’s Manual.

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1.5 Pin Identification

ANI0 to ANI3, ANI16 to ANI22: Analog input REGC: RESET: Regulator Capacitance Reset AVREFM: Analog Reference Voltage Minus RxD0 to RxD2: SCK00, SCK01, SCK11, Receive Data AVREFP: Analog reference voltage plus EXCLK: External Clock Input (Main System Clock) SCK20: SCL00, SCL01, Serial Clock Input/Output INTP0 to INTP5 Interrupt Request From Peripheral SCL11, SCL20, SCLA0: SDA00, SDA01, SDA11, Serial Clock Input/Output KR0 to KR9: Key Return P00 to P03: Port 0 SDA20, SDAA0: Serial Data Input/Output P10 to P17: Port 1 SI00, SI01, SI11, SI20: Serial Data Input P20 to P23: Port 2 SO00, SO01, SO11, P30 to P31: Port 3 SO20: Serial Data Output P40 to P42: Port 4 TI00 to TI07: Timer Input P50, P51: Port 5 TO00 to TO07: Timer Output P60, P61: Port 6 TOOL0: Data Input/Output for Tool P120 to P122, P125: Port 12 TOOLRxD, TO OLTxD: Data Input/Output for External Device P137: Port 13 P147: Port 14 TxD0 to TxD2: Transmit Data PCLBUZ0, PCLBUZ1: Programmable Clock Output/ Buzzer Output V DD: Power supply V SS: Ground X1, X2: Crystal Oscillator (Main System Clock)

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1.6 Block Diagram

1.6.1 20-pin products PORT 1 P10 to P14 PORT 2 P20 to P234 PORT 4 P40 to P42 2PORT 6 PORT 12 CRCNote PCLBUZ0 P60, P61 P121, P122, P125 RESET Low Speed On-chip oscillator 15 kHz KR0 to KR5 INTP0 to INTP3 ANI2, ANI3, ANI16 to ANI22 ANI0/AVREFP ANI1/AVREFM PORT 13 P137 Multiplier & divider multiply- accumulator On-chip debug BCD adjustment IICA0 TOOL0 SCLA0 SDAA0 Power-on reset/voltage detector Clock Generator Reset Generator High-Speed on-chip oscillator 1 to 24 MHz TOOL TxD TOOL RxD RL78 CPU core Buzzer/clock output control Key return 6ch Interrupt control 4ch Window watchdog timer 12-bit interval timer 10-bit A/D converter 11ch RAM 1.5 KB Interrupt control DMANote 2ch Code flash: 16 KB Data flash: 2 KBNote SAU0 (2ch) UART0 CSI00 CSI01Note IIC00Note IIC01Note TI00/TO00 TAU0 (4ch) ch00 ch01 ch02 ch03 TI01/TO01 TI02/TO02 TI03/TO03 RxD0 TxD0 SCK00 SI00 SO00 SCK01 SI01 SO01 SCL00 SDA00 SCL01 SDA01 Main OSC 1 to 20 MHz VDD VSS X1 X2/EXCLK Note Provided only in the R5F102 products.

RL78/G12 1. OUTLINE R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 12 of 109 1.6.2 24-pin products Code flash: 16 KB Data flash: 2 KB Note TAU0 (4ch) ch01 ch00 Interrupt control RL78 CPU core Low Speed On-chip oscillator

15 KHz

1.5 KB Poer-on reset/voltage detector High-Speed On-chip oscillator 1 to 24 MHz Clock Generator Reset Generator ch02 ch03 UART0 SAU0 (2ch) CSI00 IICA0 On-chip debug Multiplier & divider/ multiply- accumulator BCD adjustment CSI01 Note IIC00 Note IIC01 Note TI00/TO00 TI01/TO01 TI02/TO02 TI03/TO03 RxD0 TxD0 SCK00 SI00 SO00 SCK01 SI01 SO01 SCL00 SDA00 SCL01 SDA01 SCLA0 SDAA0 TOOL0 VDD VSS Port 0 P00 to P03 P10 to P14 P20 to P23 P40 to P42 P60, P61 P137 PCLBUZ0 KR0 to KR9 INTP0 to INTP3 ANI2, ANI3, ANI16 to ANI2210-bit A/D converter 11ch 12-bit Interval timer Window watchdog timer CRC Note ANI0/AVREFP ANI1/AVREFM P121, P122, 125 Port 1 Port 2 Port 4 Port 6 Port 12 Key return 10ch Interrupt control 4ch Buzzer/clock output control Port 13 RESET Main OSC 1to 20 MHz X1 X2/EXCLK TOOL TxD TOOL RxD IICA0 Note Provided only in the R5F102 products.

RL78/G12 1. OUTLINE R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 13 of 109 1.6.3 30-pin products VOLTAGE REGULATOR REGC ANI0/AVREFP ANI1/AVREFM ANI2, ANI3, ANI16 to ANI19 TAU (8ch) TI00 TO00 RxD0 TxD0 RxD2 TxD2 TOOL0 IICA0 On-chip debug BCD adjustment SCLA0 SDAA0 SCL20 SDA20 SCK20 SI20 SO20 SCL00 SDA00 SCL11 SDA11 RxD1 TxD1 SCK00 SI00 SO00 SCK11 SI11 SO11 TI01/TO01 TI02/TO02 TI03/TO03 (TI04/TO04) (TI05/TO05) (TI06/TO06) (TI07/TO07) ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 SAU0 (4ch) SAU0 (2ch) Note UART2 CSI20 IIC20 UART0 UART1Note CSI00 CSI11 Note IIC00 Note IIC11 Note Low Speed On-chip oscillator P00, P01 P10 to P17 P20 to P23 P30, P31 P40 P50, P51 P60, P61 P120 P121, P122 P137 P147 PCLBUZ0, PCLBUZ1 INTP0 to INTP5 Port 1 Port 0 Port 2 Port 3 Port 4 Port 5 Port 6 Port 12 Port 13 Port 14 Multiplier & divider/ multiply- accumulator Code flash: 16 KB Data flash: 2 KBNote Interrupt control RL78 CPU core DMA Note 2ch RAM 2 KB Poer-on reset/voltage detector High-Speed On-chip oscillator 1 to 24 MHz Clock Generator Reset Generator VDD VSS RESET Main OSC 1 to 20 MHz X1 X2/EXCLK TOOL TxD TOOL RxD 10-bit A/D converter 8ch 12-bit Interval timer Window watchdog timer CRC Note Interrupt control 6ch Buzzer/clock output control Note Provided only in the R5F102 products. Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G12 User’s Manual.

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1.7 Outline of Functions

This outline describes the function at the time when Peripheral I/O redirection register (PIOR) is set to 00H. (1/2) Item 20-pin 24-pin 30-pin R5F1026x R5F1036x R5F1027x R5F1037x R5F102Ax R5F103Ax Code flash memory 2 to 16 KB Note 1 4 to 16 KB Data flash memory 2 KB – 2 KB – 2 KB – RAM 256 B to 1.5 KB 512 B to 1.5 KB 512 B to 2KB Address space 1 MB Main system clock High-speed system clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) HS (High-speed main) mode : 1 to 20 MHz (V DD = 2.7 to 5.5 V), HS (High-speed main) mode : 1 to 16 MHz (VDD = 2.4 to 5.5 V), LS (Low-speed main) mode : 1 to 8 MHz (VDD = 1.8 to 5.5 V) High-speed on-chip oscillator clock HS (High-speed main) mode : 1 to 24 MHz (V DD = 2.7 to 5.5 V), HS (High-speed main) mode : 1 to 16 MHz (VDD = 2.4 to 5.5 V), LS (Low-speed main) mode : 1 to 8 MHz (VDD = 1.8 to 5.5 V) Low-speed on-chip oscillator clock 15 kHz (TYP) General-purpose register (8-b it register × 8) × 4 banks Minimum instruction execution time 0.04167 µs (High-speed on-chip oscillator clock: fIH = 24 MHz operation) 0.05 µs (High-speed system clock: fMX = 20 MHz operation) Instruction set ● Data transfer (8/16 bits)

• Adder and subtractor/logical operation (8/16 bits)
• Multiplication (8 bits × 8 bits)
• Rotate, barrel shift, and bit manipulation (set, reset, test, and Boolean operation), etc. I/O port Total 18 22 26 CMOS I/O 12 (N-ch O.D. I/O [VDD withstand voltage]: 4) (N-ch O.D. I/O [VDD withstand voltage]: 5) (N-ch O.D. I/O [VDD withstand voltage]: 9) CMOS input 4 4 3 N-ch open-drain I/O (6 V tolerance) Timer 16-bit timer 4 channels 8 channels Watchdog timer 1 channel 12-bit Interval timer 1 channel Timer output 4 channels (PWM outputs: 3 Note 3) 8 channels (PWM outputs: 7 Notes 2, 3) Notes 1. The self-programming function cannot be used in the R5F10266 and R5F10366. 2. The maximum number of channels when PIOR0 is set to 1. 3. The number of PWM outputs varies depending on the se tting of channels in use (the number of masters and slaves). (See 6.9.3 Operation as multiple PWM output function in the RL78/G12 User’s Manual.) Caution When the flash memory is rewritten via a user program, the code flash area and RAM area are used because each library is used. When using the library, refer to RL78 Family Flash Self Programming Library Type01 User's Manual and RL78 Family Data Flash Library Type04 User's Manual.

RL78/G12 1. OUTLINE R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 15 of 109 (2/2) Item 20-pin 24-pin 30-pin R5F1026x R5F1036x R5F1027x R5F1037x R5F102Ax R5F103Ax Clock output/buzzer output 1 2 2.44 kHz to 10 MHz: (Peripheral hardware clock: fMAIN = 20 MHz operation) 8/10-bit resolution A/D converter 11 channels 8 channels Serial interface [R5F1026x ( 20-pin), R5F1027x (24-pin)]

• Simplified SPI (CSI): 2 channels/Simplified I2C: 2 channels/UART: 1 channel [R5F102Ax (30-pin)]
• Simplified SPI (CSI): 1 channel/Simplified I2C: 1 channel/UART: 1 channel
• Simplified SPI (CSI): 1 channel/Simplified I2C: 1 channel/UART: 1 channel
• Simplified SPI (CSI): 1 channel/Simplified I2C: 1 channel/UART: 1 channel [R5F1036x (20-pin), R5F1037x (24-pin)]
• Simplified SPI (CSI): 1 channel/Simplified I2C: 0 channel/UART: 1 channel [R5F103Ax (30-pin)]
• Simplified SPI (CSI): 1 channel/Simplified I2C: 0 channel/UART: 1 channel I 2C bus 1 channel Multiplier and divider/multiply- accumulator
• 16 bits × 16 bits = 32 bits (unsigned or signed)
• 32 bits × 32 bits = 32 bits (unsigned)
• 16 bits × 16 bits + 32 bits = 32 bits (unsigned or signed) DMA controller 2 channels – 2 channels – 2 channels – Vectored interrupt sources Internal 18 16 18 16 26 19 External 5 6 Key interrupt 6 10 – Reset ● Reset by RESET pin
• Internal reset by watchdog timer
• Internal reset by power-on-reset
• Internal reset by voltage detector
• Internal reset by illegal instruction execution Note
• Internal reset by RAM parity error
• Internal reset by illegal-memory access Power-on-reset circuit ● Power-on-reset: 1.51 V (TYP)
• Power-down-reset: 1.50 V (TYP) Voltage detector ● Rising edge : 1.88 to 4.06 V (12 stages)
• Falling edge : 1.84 to 3.98 V (12 stages) On-chip debug function Provided Power supply voltage V DD = 1.8 to 5.5 V Operating ambient temperature T A = –40 to +85°C (A: Consumer applications, D: Industrial applications), TA = –40 to +105°C (G: Industrial applications) Note The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator.

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 16 of 109 2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C) This chapter describes the following electrical specifications. Target products A: Consumer applications T A = -40 to +85°C R5F102xxAxx, R5F103xxAxx D: Industrial applications TA = -40 to +85°C R5F102xxDxx, R5F103xxDxx G: Industrial applications when T A = -40 to +105°C products is used in the range of TA = -40 to +85°C R5F102xxGxx Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. product in the RL78/G12 User’s Manual.

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 17 of 109

2.1 Absolute Maximum Ratings

Absolute Maximum Ratings (TA = 25°C) Parameter Symbols Condi tions Ratings Unit Supply Voltage V DD –0.5 to + 6.5 V REGC terminal input voltageNote1 VIREGC REGC –0.3 to +2 and –0.3 to VDD + 0.3 Note 2 V Input Voltage V I1 Other than P60, P61 –0.3 to V DD + 0.3Note 3 V VI2 P60, P61 (N-ch open drain) –0.3 to 6.5 V Output Voltage V O –0.3 to V DD + 0.3Note 3 V Analog input voltage V AI 20-, 24-pin products: ANI0 to ANI3, ANI16 to ANI22 30-pin products: ANI0 to ANI3, ANI16 to ANI19 –0.3 to VDD + 0.3 and –0.3 to AVREF(+)+0.3 Notes 3, 4 V Output current, high IOH1 Per pin Other than P20 to P23 –40 mA Total of all pins All the terminals other than P20 to P23 –170 mA 20-, 24-pin products: P40 to P42 30-pin products: P00, P01, P40, P120 –70 mA 20-, 24-pin products: P00 to P03Note 5, P10 to P14 30-pin products: P10 to P17, P30, P31, P50, P51, P147 –100 mA IOH2 Per pin P20 to P23 –0.5 mA Total of all pins –2 mA Output current, low I OL1 Per pin Other than P20 to P23 40 mA Total of all pins All the terminals other than P20 to P23 170 mA 20-, 24-pin products: P40 to P42 30-pin products: P00, P01, P40, P120 70 mA 20-, 24-pin products: P00 to P03Note 5, P10 to P14, P60, P61 30-pin products: P10 to P17, P30, P31, P50, P51, P60, P61, P147 100 mA IOL2 Per pin P20 to P23 1 mA Total of all pins 5 mA Operating ambient temperature TA –40 to +85 °C Storage temperature T stg –65 to +150 °C Notes 1. 30-pin product only. 2. Connect the REGC pin to VSS via a capacitor (0.47 to 1 µF). Th is value determines the absolute maximum rating of the REGC pin. Do not use it with voltage applied. 3. Must be 6.5 V or lower. 4. Do not exceed AV REF (+) + 0.3 V in case of A/D conversion target pin . 5. 24-pin products only. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remarks 1. Unless specified otherwise, the characteristics of alter nate-function pins are the same as those of the port pins. 2. AV REF(+) : + side reference voltage of the A/D converter. 3. V SS : Reference voltage

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 18 of 109

2.2 Oscillator Characteristics

2.2.1 X1 oscillator characteristics

(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Resonator Conditions MIN. TYP. MAX. Unit X1 clock oscillation frequency (fX)Note Ceramic resonator / crystal oscillator 2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz 1.8 V ≤ VDD < 2.7 V 1.0 8.0 Note Indicates only permissible oscillator frequency ranges. Re fer to AC Characteristics for instruction execution time. Request evaluation by the manufacturer of t he oscillator circuit mounted on a board to check the oscillator characteristics. Caution Since the CPU is started by the high-speed on-chip o scillator clock after a r eset release, check the X1 clock oscillation stabilization ti me using the oscillation stabilizati on time counter status register (OSTC) by the user. Determine th e oscillation stabilization time of the OSTC register and the oscillation stabilization time select register (OST S) after sufficiently ev aluating the oscillation stabilization time with the resonator to be used. Remark When using the X1 oscillator, refer to 5.4 System Clock Oscillator in the RL78/G12 User’s Manual.

2.2.2 On-chip oscillator characteristics

(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Oscillators Parameters Conditions MIN. TYP. MAX. Unit High-speed on-chip oscillator clock frequency Notes 1, 2 fIH 1 24 MHz High-speed on-chip oscillator clock frequency accuracy R5F102 products T A = –20 to +85°C -1.0 +1.0 % R5F103 products -5.0 +5.0 % Low-speed on-chip oscillator clock frequency fIL 15 kHz Low-speed on-chip oscillator clock frequency accuracy -15 +15 % Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H) and bits 0 to 2 of HOCODIV register. 2. This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time.

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 19 of 109

2.3 DC Characteristics

2.3.1 Pin characteristics

Parameter Symbol Conditions MIN. TYP. MAX. Unit Output current, highNote 1 I OH1 20-, 24-pin products: Per pin for P00 to P03Note 4, P10 to P14, P40 to P42 30-pin products: Per pin for P00, P01, P10 to P17, P30, P31, P40, P50, P51, P120, P147 –10.0 Note 2 mA 20-, 24-pin products: Total of P40 to P42 30-pin products: Total of P00, P01, P40, P120 (When duty ≤ 70% Note 3) 4.0 V ≤ VDD ≤ 5.5 V –30.0 mA 2.7 V ≤ VDD < 4.0 V –6.0 mA 1.8 V ≤ VDD < 2.7 V –4.5 mA 20-, 24-pin products: Total of P00 to P03Note 4, P10 to P14 30-pin products: Total of P10 to P17, P30, P31, P50, P51, P147 (When duty ≤ 70% Note 3) 4.0 V ≤ VDD ≤ 5.5 V –80.0 mA 2.7 V ≤ VDD < 4.0 V –18.0 mA 1.8 V ≤ VDD < 2.7 V –10.0 mA Total of all pins (When duty ≤ 70%Note 3) –100 mA IOH2 Per pin for P20 to P23 –0.1 mA Total of all pins –0.4 mA Notes 1 . value of current at which the device operation is guaranteed even if the current flows from the VDD pin to an output pin. 2. However, do not exceed the total current value. 3. The output current value under conditions where the duty factor ≤ 70%. If duty factor > 70%: The output current value c an be calculated with the following expression (where n represents the duty factor as a percentage).

• Total output current of pins = (IOH × 0.7)/(n × 0.01) <Example> Where n = 80% and I OH = –10.0 mA Total output current of pins = (–10.0 × 0.7)/(80 × 0.01)  –8.7 mA However, the current that is allowed to flow into one pin does not vary depe nding on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. 4. 24-pin products only. Caution P10 to P12 and P41 for 20-pin products, P01, P 10 to P12, and P41 for 24-pin products, and P00, P10 to P15, P17, and P50 for 30-pin products do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the charac teristics of alternate-function pins are the same as those of the port pins.

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 20 of 109 Parameter Symbol Conditions MIN. TYP. MAX. Unit Output current, lowNote 1 I OL1 20-, 24-pin products: Per pin for P00 to P03Note 4, P10 to P14, P40 to P42 30-pin products: Per pin for P00, P01, P10 to P17, P30, P31, P40, P50, P51, P120, P147 20.0 Note 2 mA Per pin for P60, P61 15.0 Note 2 mA 20-, 24-pin products: Total of P40 to P42 30-pin products: Total of P00, P01, P40, P120 (When duty ≤ 70% Note 3) 4.0 V ≤ VDD ≤ 5.5 V 60.0 mA 2.7 V ≤ VDD < 4.0 V 9.0 mA 1.8 V ≤ VDD < 2.7 V 1.8 mA 20-, 24-pin products: Total of P00 to P03Note 4, P10 to P14, P60, P61 30-pin products: Total of P10 to P17, P30, P31, P50, P51, P60, P61, P147 (When duty ≤ 70% Note 3) 4.0 V ≤ VDD ≤ 5.5 V 80.0 mA 2.7 V ≤ VDD < 4.0 V 27.0 mA 1.8 V ≤ VDD < 2.7 V 5.4 mA Total of all pins (When duty ≤ 70%Note 3) 140 mA IOL2 Per pin for P20 to P23 0.4 mA Total of all pins 1.6 mA Notes 1 . Value of current at which the devic e operation is guaranteed even if the current flows from an output pin to the VSS pin. 2. However, do not exceed the total current value. 3. The output current value under conditions where the duty factor ≤ 70%. If duty factor > 70%: The output current value c an be calculated with the following expression (where n represents the duty factor as a percentage).

• Total output current of pins = (IOL × 0.7)/(n × 0.01) <Example> Where n = 80% and I OL = 10.0 mA Total output current of pins = (10.0 × 0.7)/(80 × 0.01)  8.7 mA However, the current that is allowed to flow in to one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. 4. 24-pin products only. Remark Unless specified otherwise, the charac teristics of alternate-function pins are the same as those of the port pins.

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 21 of 109 Parameter Symbol Conditions MIN. TYP. MAX. Unit Input voltage, high V IH1 Normal input buffer 20-, 24-pin products: P00 to P03Note 2, P10 to P14, P40 to P42 30-pin products: P00, P01, P10 to P17, P30, P31, P40, P50, P51, P120, P147 0.8VDD V DD V VIH2 TTL input buffer 20-, 24-pin products: P10, P11 30-pin products: P01, P10, P11, P13 to P17 4.0 V ≤ VDD ≤ 5.5 V 2.2 V DD V 3.3 V ≤ VDD < 4.0 V 2.0 V DD V 1.8 V ≤ VDD < 3.3 V 1.5 V DD V VIH3 P20 to P23 0.7V DD V DD V VIH4 P60, P61 0.7V DD 6.0 V VIH5 P121, P122, P125 Note 1, P137, EXCLK, RESET 0.8V DD V DD V Input voltage, low V IL1 Normal input buffer 20-, 24-pin products: P00 to P03Note 2, P10 to P14, P40 to P42 30-pin products: P00, P01, P10 to P17, P30, P31, P40, P50, P51, P120, P147 0 0.2V DD V VIL2 TTL input buffer 20-, 24-pin products: P10, P11 30-pin products: P01, P10, P11, P13 to P17

4.0 V ≤ V

DD ≤ 5.5 V 0 0.8 V 3.3 V ≤ VDD < 4.0 V 0 0.5 V 1.8 V ≤ VDD < 3.3 V 0 0.32 V VIL3 P20 to P23 0 0.3V DD V VIL4 P60, P61 0 0.3V DD V VIL5 P121, P122, P125 Note 1, P137, EXCLK, RESET 0 0.2V DD V Output voltage, high V OH1 20-, 24-pin products: P00 to P03Note 2, P10 to P14, P40 to P42 30-pin products: P00, P01, P10 to P17, P30, P31, P40, P50, P51, P120, P147 DD ≤ 5.5 V, IOH1 = –10.0 mA VDD–1.5 V 4.0 V ≤ VDD ≤ 5.5 V, IOH1 = –3.0 mA VDD–0.7 V 2.7 V ≤ VDD ≤ 5.5 V, IOH1 = –2.0 mA VDD–0.6 V 1.8 V ≤ VDD ≤ 5.5 V, IOH1 = –1.5 mA VDD–0.5 V VOH2 P20 to P23 I OH2 = –100 µA V DD–0.5 V Notes 1. 20, 24-pin products only. 2. 24-pin products only. Caution The maximum value of V IH of pins P10 to P12 and P41 for 20-pin products, P01, P10 to P12, and P41 for 24-pin products, and P00, P10 to P15, P17, and P50 for 30-pin products is V DD even in N-ch open- drain mode. High level is not output in the N-ch open-drain mode. Remark Unless specified otherwise, the charac teristics of alternate-function pins are the same as those of the port pins.

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 22 of 109 Parameter Symbol Conditions MIN. TYP. MAX. Unit Output voltage, low V OL1 20-, 24-pin products: P00 to P03Note, P10 to P14, P40 to P42 30-pin products: P00, P01, P10 to P17, P30, P31, P40, P50, P51, P120, P147 DD ≤ 5.5 V, IOL1 = 20.0 mA 1.3 V 4.0 V ≤ VDD ≤ 5.5 V, IOL1 = 8.5 mA 0.7 V 2.7 V ≤ VDD ≤ 5.5 V, IOL1 = 3.0 mA 0.6 V 2.7 V ≤ VDD ≤ 5.5 V, IOL1 = 1.5 mA 0.4 V 1.8 V ≤ VDD ≤ 5.5 V, IOL1 = 0.6 mA 0.4 V VOL2 P20 to P23 I OL2 = 400 µA 0.4 V VOL3 P60, P61 4.0 V ≤ VDD ≤ 5.5 V, IOL1 = 15.0 mA 2.0 V 4.0 V ≤ VDD ≤ 5.5 V, IOL1 = 5.0 mA 0.4 V 2.7 V ≤ VDD ≤ 5.5 V, IOL1 = 3.0 mA 0.4 V 1.8 V ≤ VDD ≤ 5.5 V, IOL1 = 2.0 mA 0.4 V Input leakage current, high ILIH1 Other than P121, P122 VI = VDD 1 µA ILIH2 P121, P122 (X1, X2/EXCLK) VI = VDD Input port or external clock input 1 µA When resonator connected 10 µA Input leakage current, low ILIL1 Other than P121, P122 VI = VSS –1 µA ILIL2 P121, P122 (X1, X2/EXCLK) VI = VSS Input port or external clock input –1 µA When resonator connected –10 µA On-chip pull-up resistance RU 20-, 24-pin products: P00 to P03Note, P10 to P14, P40 to P42, P125, RESET 30-pin products: P00, P01, P10 to P17, P30, P31, P40, P50, P51, P120, P147 V I = VSS, input port 10 20 100 k Ω Note 24-pin products only. Remark Unless specified otherwise, the charac teristics of alternate-function pins are the same as those of the port pins.

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 23 of 109

2.3.2 Supply current characteristics

(1) 20-, 24-pin products Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply currentNote 1 IDD1 Operating mode HS(High-speed main) modeNote 4 fIH = 24 MHzNote 3 Basic operation VDD = 5.0 V 1.5 mA VDD = 3.0 V 1.5 Normal operation VDD = 5.0 V 3.3 5.0 mA VDD = 3.0 V 3.3 5.0 fIH = 16 MHzNote 3 V DD = 5.0 V 2.5 3.7 mA VDD = 3.0 V 2.5 3.7 LS(Low-speed main) mode Note 4 fIH = 8 MHzNote 3 V DD = 3.0 V 1.2 1.8 mA VDD = 2.0 V 1.2 1.8 HS(High-speed main) modeNote4 fMX = 20 MHzNote 2, VDD = 5.0 V Square wave input 2.8 4.4 mA Resonator connection 3.0 4.6 fMX = 20 MHzNote 2, VDD = 3.0 V Square wave input 2.8 4.4 mA Resonator connection 3.0 4.6 fMX = 10 MHzNote 2, VDD = 5.0 V Square wave input 1.8 2.6 mA Resonator connection 1.8 2.6 fMX = 10 MHzNote 2, VDD = 3.0 V Square wave input 1.8 2.6 mA Resonator connection 1.8 2.6 LS(Low-speed main) modeNote 4 fMX = 8 MHzNote 2, VDD = 3.0 V Square wave input 1.1 1.7 mA Resonator connection 1.1 1.7 fMX = 8 MHzNote 2, VDD = 2.0 V Square wave input 1.1 1.7 mA Resonator connection 1.1 1.7 Notes 1. Total current flowing into V DD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. When high-speed on-chip oscillator clock is stopped. 3. When high-speed system clock is stopped 4. Relationship between operation voltage width, oper ation frequency of CPU and operation mode is as follows. HS (High speed main) mode: V DD = 2.7 V to 5.5 V @1 MHz to 24 MHz V DD = 2.4 V to 5.5 V @1 MHz to 16 MHz LS (Low speed main) mode: V DD = 1.8 V to 5.5 V @1 MHz to 8 MHz Remarks 1. f MX: High-speed system clock frequency (X1 clock oscilla tion frequency or external main system clock frequency) 2. f IH: high-speed on-chip oscillator clock frequency 3. Temperature condition of the TYP. value is T A = 25°C.

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 24 of 109 (1) 20-, 24-pin products Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply current Note 1 IDD2Note 2 HALT mode HS (High-speed main) modeNote 6 fIH = 24 MHzNote 4 VDD = 5.0 V 440 1210 µA VDD = 3.0 V 440 1210 fIH = 16 MHzNote 4 V DD = 5.0 V 400 950 µA VDD = 3.0 V 400 950 LS (Low-speed main) modeNote 6 fIH = 8 MHzNote 4 V DD = 3.0 V 270 542 µA VDD = 2.0 V 270 542 HS (High-speed main) modeNote 6 fMX = 20 MHzNote 3, VDD = 5.0 V Square wave input 280 1000 µA Resonator connection 450 1170 fMX = 20 MHzNote 3, VDD = 3.0 V Square wave input 280 1000 µA Resonator connection 450 1170 fMX = 10 MHzNote 3, VDD = 5.0 V Square wave input 190 590 µA Resonator connection 260 660 fMX = 10 MHzNote 3, VDD = 3.0 V Square wave input 190 590 µA Resonator connection 260 660 LS (Low-speed main) modeNote 6 fMX = 8 MHzNote 3, VDD = 3.0 V Square wave input 110 360 µA Resonator connection 150 416 fMX = 8 MHzNote 3, VDD = 2.0 V Square wave input 110 360 µA Resonator connection 150 416 IDD3Note 5 STOP mode TA = –40°C 0.19 0.50 µA TA = +25°C 0.24 0.50 TA = +50°C 0.32 0.80 TA = +70°C 0.48 1.20 TA = +85°C 0.74 2.20 Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. During HALT instruction execution by flash memory. 3. When high-speed on-chip oscillator clock is stopped. 4. When high-speed system clock is stopped. 5. Not including the current flowing into the 12-bit interval timer and watchdog timer. 6. Relationship between operation voltage width, oper ation frequency of CPU and operation mode is as follows. HS (High speed main) mode: V DD = 2.7 V to 5.5 V @1 MHz to 24 MHz V DD = 2.4 V to 5.5 V @1 MHz to 16 MHz LS (Low speed main) mode: V DD = 1.8 V to 5.5 V @1 MHz to 8 MHz Remarks 1. f MX: High-speed system clock frequency (X1 clock oscilla tion frequency or external main system clock frequency) 2. f IH: high-speed on-chip oscillator clock frequency 3. Except temperature conditi on of the TYP. value is TA = 25°C, other than STOP mode

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 25 of 109 (2) 30-pin products Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply currentNote 1 IDD1 Operating mode HS (High-speed main) modeNote 4 fIH = 24 MHzNote 3 Basic operation VDD = 5.0 V 1.5 mA VDD = 3.0 V 1.5 Normal operation VDD = 5.0 V 3.7 5.5 mA VDD = 3.0 V 3.7 5.5 fIH = 16 MHzNote 3 VDD = 5.0 V 2.7 4.0 mA VDD = 3.0 V 2.7 4.0 LS (Low-speed main) mode Note 4 fIH = 8 MHzNote 3 VDD = 3.0 V 1.2 1.8 mA VDD = 2.0 V 1.2 1.8 HS (High-speed main) mode Note 4 fMX = 20 MHzNote 2, VDD = 5.0 V Square wave input 3.0 4.6 mA Resonator connection 3.2 4.8 fMX = 20 MHzNote 2, VDD = 3.0 V Square wave input 3.0 4.6 mA Resonator connection 3.2 4.8 fMX = 10 MHzNote 2, VDD = 5.0 V Square wave input 1.9 2.7 mA Resonator connection 1.9 2.7 fMX = 10 MHzNote 2, VDD = 3.0 V Square wave input 1.9 2.7 mA Resonator connection 1.9 2.7 LS (Low-speed main) mode Note 4 fMX = 8 MHzNote 2, VDD = 3.0 V Square wave input 1.1 1.7 mA Resonator connection 1.1 1.7 fMX = 8 MHzNote 2, VDD = 2.0 V Square wave input 1.1 1.7 mA Resonator connection 1.1 1.7 Notes 1. Total current flowing into V DD, including the input leakage current flowin g when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D c onverter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. When high-speed on-chip oscillator clock is stopped. 3. When high-speed system clock is stopped 4. Relationship between operation voltage width, oper ation frequency of CPU and operation mode is as follows. HS (High speed main) mode: V DD = 2.7 V to 5.5 V @1 MHz to 24 MHz V DD = 2.4 V to 5.5 V @1 MHz to 16 MHz LS (Low speed main) mode: V DD = 1.8 V to 5.5 V @1 MHz to 8 MHz Remarks 1. f MX: High-speed system clock frequency (X1 clock oscilla tion frequency or external main system clock frequency) 2. f IH: high-speed on-chip oscillator clock frequency 3. Temperature condition of the TYP. value is T A = 25°C.

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 26 of 109 (2) 30-pin products Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply currentNote 1 IDD2Note 2 HALT mode HS (High-speed main) mode Note 6 fIH = 24 MHzNote 4 VDD = 5.0 V 440 1280 µA VDD = 3.0 V 440 1280 fIH = 16 MHzNote 4 V DD = 5.0 V 400 1000 µA VDD = 3.0 V 400 1000 LS (Low-speed main) modeNote 6 fIH = 8 MHzNote 4 V DD = 3.0 V 260 530 µA VDD = 2.0 V 260 530 HS (High-speed main) modeNote 6 fMX = 20 MHzNote 3, VDD = 5.0 V Square wave input 280 1000 µA Resonator connection 450 1170 fMX = 20 MHzNote 3, VDD = 3.0 V Square wave input 280 1000 µA Resonator connection 450 1170 fMX = 10 MHzNote 3, VDD = 5.0 V Square wave input 190 600 µA Resonator connection 260 670 fMX = 10 MHzNote 3, VDD = 3.0 V Square wave input 190 600 µA Resonator connection 260 670 LS (Low-speed main) modeNote 6 fMX = 8 MHzNote 3, VDD = 3.0 V Square wave input 95 330 µA Resonator connection 145 380 fMX = 8 MHz Note 3, VDD = 2.0 V Square wave input 95 330 µA Resonator connection 145 380 IDD3Note 5 STOP mode TA = –40°C 0.18 0.50 µA TA = +25°C 0.23 0.50 TA = +50°C 0.30 1.10 TA = +70°C 0.46 1.90 TA = +85°C 0.75 3.30 Notes 1. Total current flowing into V DD, including the input leakage current flowin g when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D c onverter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. During HALT instruction execution by flash memory. 3. When high-speed on-chip oscillator clock is stopped. 4. When high-speed system clock is stopped. 5. Not including the current flowing into the 12-bit interval timer and watchdog timer. 6. Relationship between operation voltage width, oper ation frequency of CPU and operation mode is as follows. HS (High speed main) mode: V DD = 2.7 V to 5.5 V @1 MHz to 24 MHz V DD = 2.4 V to 5.5 V @1 MHz to 16 MHz LS (Low speed main) mode: V DD = 1.8 V to 5.5 V @1 MHz to 8 MHz Remarks 1. f MX: High-speed system clock frequency (X1 clock oscilla tion frequency or external main system clock frequency) 2. f IH: high-speed on-chip oscillator clock frequency 3. Except STOP mode, temperature c ondition of the TYP. value is TA = 25°C.

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 27 of 109 (3) Peripheral functions (Common to all products) (TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Low-speed onchip oscillator operating current I FIL Note 1 0.20 µA 12-bit interval timer operating current I TMKA Notes 1, 2, 3 0.02 µA Watchdog timer operating current IWDT Notes 1, 2, 4 fIL = 15 kHz 0.22 µA A/D converter operating current IADCNotes 1, 5 When conversion at maximum speed Normal mode, AVREFP = VDD = 5.0 V 1.30 1.70 mA Low voltage mode, AVREFP = VDD = 3.0 V 0.50 0.70 mA A/D converter reference voltage operating current IADREF Note 1 75.0 µA Temperature sensor operating current ITMPS Note 1 75.0 µA LVD operating current ILVD Notes 1, 6 0.08 µA Self- programming operating current I FSP Notes 1, 8 2.00 12.20 mA BGO operating current IBGO Notes 1, 7 2.00 12.20 mA SNOOZE operating current ISNOZ Note 1 ADC operation The mode is performed Note 9 0.50 0.60 mA The A/D conversion operations are performed, Low voltage mode, AV REFP = VDD = 3.0 V 1.20 1.44 mA Simplified SPI (CSI)/UART operation 0.70 0.84 mA Notes 1. Current flowing to the V DD. 2. When high speed on-chip oscillator and high-speed system clock are stopped. 3. Current flowing only to the 12-bit interval timer (e xcluding the operating current of the low-speed on-chip oscillator). The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3, and IFIL and ITMKA when the 12-bit interval timer operates. 4. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer operates. 5. Current flowing only to the A/D conver ter. The current value of the R L78 microcontrollers is the sum of I DD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode. 6. Current flowing only to the LVD circuit. The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ILVD when the LVD circuit operates. 7. Current flowing only during data flash rewrite. 8. Current flowing only during self programming. 9. For shift time to the SNOOZE mode, see 17.3.3 SNOOZE mode in the RL78/G12 User’s Manual. Remarks 1. f IL: Low-speed on-chip oscillator clock frequency 2. Temperature condition of the TYP. value is T A = 25°C

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 28 of 109

2.4 AC Characteristics

(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Items Symbol Conditions MIN. TYP. MAX. Unit Instruction cycle (minimum instruction execution time) TCY Main system clock (fMAIN) operation HS (High- speed main) mode 2.7 V ≤ VDD ≤ 5.5 V 0.04167 1 µs 2.4 V ≤ VDD < 2.7 V 0.0625 1 µs LS (Low- speed main) mode

1.8 V ≤ V

DD ≤ 5.5 V 0.125 1 µs During self programming HS (High- speed main) mode 2.7 V ≤ VDD ≤ 5.5 V 0.04167 1 µs 2.4 V ≤ VDD < 2.7 V 0.0625 1 µs LS (Low- speed main) mode DD ≤ 5.5 V 0.125 1 µs External main system clock frequency fEX 2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz 2.4 V ≤ VDD < 2.7 V 1.0 16.0 MHz 1.8 V ≤ VDD < 2.4 V 1.0 8.0 MHz External main system clock input high-level width, low- level width t EXH, tEXL 2.7 V ≤ VDD ≤ 5.5 V 24 ns 2.4 V ≤ VDD < 2.7 V 30 ns 1.8 V ≤ VDD < 2.4 V 60 ns TI00 to TI07 input high-level width, low-level width tTIH, tTIL 1/fMCK + ns TO00 to TO07 output frequency fTO 4.0 V ≤ VDD ≤ 5.5 V 12 MHz 2.7 V ≤ VDD < 4.0 V 8 MHz 1.8 V ≤ VDD < 2.7 V 4 MHz PCLBUZ0, or PCLBUZ1 output frequency fPCL 4.0 V ≤ VDD ≤ 5.5 V 16 MHz 2.7 V ≤ VDD < 4.0 V 8 MHz 1.8 V ≤ VDD < 2.7 V 4 MHz INTP0 to INTP5 input high- level width, low-level width tINTH, tINTL 1 µs KR0 to KR9 input available width tKR 250 ns RESET low-level width t RSL 10 µs Remark f MCK: Timer array unit operation clock frequency (Operation clock to be set by the ti mer clock select register 0 (TPS0) and the CKS0n bit of timer mode register 0n (TMR0n). n: Channel number (n = 0 to 7))

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 29 of 109 Minimum Instruction Execution Time during Main System Clock Operation TCY vs VDD (HS (high-speed main) mode) When the high-speed on-chip oscillator clock is selected During self programming When high-speed system clock is selected Supply voltage VDD [V] 1.0 0.1 5.52.7 0.01 2.4 0.04167 0.0625 Cycle time TCY [µs] TCY vs VDD (LS (low-speed main) mode) 1.0 0.1 0.01 1.8

0.125 Cycle time TCY [µs]

Supply voltage VDD [V] When the high-speed on-chip oscillator clock is selected During self programming When high-speed system clock is selected

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 30 of 109 AC Timing Test Point VIH/VOH VIL/VOL Test points VIH/VOH VIL/VOL External Main System Clock Timing EXCLK 1/fEX tEXL tEXH TI/TO Timing TI00 to TI07 tTIL tTIH TO00 to TO07 1/fTO Interrupt Request Input Timing INTP0 to INTP5 tINTL tINTH Key Interrupt Input Timing KR0 to KR9 tKR RESET Input Timing RESET tRSL

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 31 of 109

2.5 Peripheral Functions Characteristics

2.5.1 Serial array unit

(1) During communication at sam e potential (UART mode) (TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Condi tions HS (high-speed main) Mode LS (low-speed main) Mode Unit MIN. MAX. MIN. MAX. Transfer rate Note 1 f MCK/6 f MCK/6 bps Theoretical value of the maximum transfer rate fCLK = fMCKNote 2 4.0 1.3 Mbps Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only. 2. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main ) mode: 24 MHz (2.7 V ≤ VDD ≤ 5.5 V) 16 MHz (2.4 V ≤ VDD ≤ 5.5 V) LS (low-speed main) mode: 8 MHz (1.8 V ≤ VDD ≤ 5.5 V) Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). UART mode connection diagram (during communication at same potential) RL78 microcontroller TxDq RxDq Rx Tx User's device UART mode bit width (during communication at same potential) (reference) TxDq RxDq Baud rate error tolerance High-/Low-bit width 1/Transfer rate Remarks 1. q: UART number (q = 0 to 2), g: PIM, POM number (g = 0, 1) 2. f MCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock se lect register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10, 11))

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 32 of 109 (2) During communication at same potential (simplified SP I (CSI) mode) (master mode, SCK00... internal clock output, corresponding CSI00 only) (TA = –40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditi ons HS (high-speed main) Mode LS (low-speed main) Mode Unit MIN. MAX. MIN. MAX. SCK00 cycle time t KCY1 t KCY1 ≥ 2/fCLK 83.3 250 ns SCK00 high-/low- level width tKH1, tKL1 4.0 V ≤ VDD ≤ 5.5 V t KCY1/2–7 t KCY1/2–50 ns 2.7 V ≤ VDD ≤ 5.5 V t KCY1/2–10 t KCY1/2–50 ns SI00 setup time (to SCK00↑) Note 1 tSIK1 4.0 V ≤ VDD ≤ 5.5 V 23 110 ns 2.7 V ≤ VDD ≤ 5.5 V 33 110 ns SI00 hold time (from SCK00↑) Note 2 tKSI1 10 10 ns Delay time from SCK00↓ to SO00 output Note 3 tKSO1 C = 20 pF Note 4 10 10 ns Notes 1. When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1. The SI00 setup time becomes “to SCK00↓” when DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0. 2. When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1. The SI00 hold time becomes “from SCK00↓” when DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0. 3. When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP 00 = 1. The delay time to SO00 output becomes “from SCK00↑” when DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0. 4. C is the load capacitance of the SCK00 and SO00 output lines. Caution Select the normal input buffer for the SI00 pi n and the normal output mode for the SO00 and SCK00 pins by using port input mode register 1 (PIM1) and port output mode register 1 (POM1). Remarks 1. This specification is valid only when CSI00’s peripheral I/O redirect function is not used. 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register 0 (SPS0 ) and the CKS00 bit of serial mode register 00 (SMR00).)

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 33 of 109 (3) During communication at same potential (simplified SPI (CSI) mode) (master m ode, SCKp... internal clock output) (TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Condi tions HS (high-speed main) Mode LS (low-speed main) Mode Unit MIN. MAX. MIN. MAX. SCKp cycle time t KCY1 t KCY1 ≥ 4/fCLK 2.7 V ≤ VDD ≤ 5.5 V 167 500 ns 2.4 V ≤ VDD ≤ 5.5 V 250 500 ns 1.8 V ≤ VDD ≤ 5.5 V – 500 ns SCKp high-/low-level width t KH1, tKL1 4.0 V ≤ VDD ≤ 5.5 V t KCY1/2–12 t KCY1/2–50 ns 2.7 V ≤ VDD ≤ 5.5 V t KCY1/2–18 t KCY1/2–50 ns 2.4 V ≤ VDD ≤ 5.5 V t KCY1/2–38 t KCY1/2–50 ns 1.8 V ≤ VDD ≤ 5.5 V – t KCY1/2–50 ns SIp setup time (to SCKp↑) Note 1 tSIK1 4.0 V ≤ VDD ≤ 5.5 V 44 110 ns 2.7 V ≤ VDD ≤ 5.5 V 44 110 ns 2.4 V ≤ VDD ≤ 5.5 V 75 110 ns 1.8 V ≤ VDD ≤ 5.5 V – 110 ns SIp hold time (from SCKp↑) Note 2 tKSI1 19 19 ns Delay time from SCKp↓ to SOp output Note 3 tKSO1 C = 30 pF Note 4 25 25 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp and SCKp pins by using port input mode register 1 (PIM1) and port output mode registers 0, 1, 4 (POM0, POM1, POM4). Remarks 1. p: CSI number (p = 00, 01, 11, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3: “1, 3” is only for the R5F102 products) 2. f MCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock sele ct register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3: “1, 3” is only for the R5F102 products.))

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 34 of 109 (4) During communication at same potential (simplified SPI (CSI) mode) (slave mode, SCKp... external clock input) (TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Condi tions HS (high-speed main) Mode LS (low-speed main) Mode Unit MIN. MAX. MIN. MAX. SCKp cycle time Note 5 t KCY2 4.0 V ≤ VDD ≤ 5.5 V 20 MHz < f MCK 8/f MCK – ns fMCK ≤ 20 MHz 6/f MCK 6/f MCK ns 2.7 V ≤ VDD ≤ 5.5 V 16 MHz < f MCK 8/f MCK – ns fMCK ≤ 16 MHz 6/f MCK 6/f MCK ns 2.4 V ≤ VDD ≤ 5.5 V 6/f MCK and 500 6/f MCK and 500 ns 1.8 V ≤ VDD ≤ 5.5 V – 6/f MCK and 750 ns SCKp high-/low-level width tKH2, tKL2 4.0 V ≤ VDD ≤ 5.5 V t KCY2/2–7 t KCY2/2–7 ns 2.7 V ≤ VDD ≤ 5.5 V t KCY2/2–8 t KCY2/2–8 ns 2.4 V ≤ VDD ≤ 5.5 V t KCY2/2–18 t KCY2/2–18 ns 1.8 V ≤ VDD ≤ 5.5 V – t KCY2/2–18 ns SIp setup time (to SCKp↑) Note 1 tSIK2 2.7 V ≤ VDD ≤ 5.5 V 1/f MCK + 20 1/f MCK + 30 ns 2.4 V ≤ VDD ≤ 5.5 V 1/f MCK + 30 1/f MCK + 30 ns 1.8 V ≤ VDD ≤ 5.5 V – 1/f MCK + 30 ns SIp hold time (from SCKp↑) Note 2 tKSI2 1/f MCK + 31 1/f MCK + 31 ns Delay time from SCKp↓ to SOp output Note 3 tKSO2 C = 30 pF Note 4 2.7 V ≤ VDD ≤ 5.5 V 2/f MCK + 2/f MCK + 110 ns 2.4 V ≤ VDD ≤ 5.5 V 2/f MCK + 2/f MCK + 110 ns 1.8 V ≤ VDD ≤ 5.5 V – 2/fMCK + 110 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SOp output lines. 5. Transfer rate in the SNOOZE mode: MAX. 1 Mbps. Caution Select the normal input buffer for the SIp and SCKp pins and the normal output mode for the SOp pin by using port input mode register 1 (PIM1) and port output mode registers 0, 1, 4 (POM0, POM1, POM4).

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 35 of 109 Simplified SPI (CSI) mode connection diagram (during communication at same potential) RL78 microcontroller SCKp SOp SCK SI User's deviceSIp SO Simplified SPI (CSI) mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) SIp SOp tKCY1, 2 tKL1, 2 tKH1, 2 tSIK1, 2 tKSI1, 2 tKSO1, 2 SCKp Input data Output data Simplified SPI (CSI) mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) SIp SOp tKCY1, 2 tKH1, 2 tKL1, 2 tSIK1, 2 tKSI1, 2 tKSO1, 2 SCKp Input data Output data (Remarks are listed on the next page.)

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 36 of 109 Remarks 1. p: CSI number (p = 00, 01, 11, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3: “1, 3” is only for the R5F102 products.) 2. f MCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3: “1, 3” is only for the R5F102 products.)) (5) During communication at same potential (simplified I2C mode) (TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode Unit MIN. MAX. SCLr clock frequency f SCL 1.8 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ

400 Note 1 kHz

1.8 V ≤ VDD < 2.7 V, Cb = 100 pF, Rb = 5 kΩ

300 Note 1 kHz

Hold time when SCLr = “L” t LOW 1.8 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1150 ns 1.8 V ≤ VDD < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1550 ns Hold time when SCLr = “H” t HIGH 1.8 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1150 ns 1.8 V ≤ VDD < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1550 ns Data setup time (reception) t SU:DAT 1.8 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1/fMCK + 145 Note 2 ns 1.8 V ≤ VDD < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1/fMCK + 230 Note 2 ns Data hold time (transmission) t HD:DAT 1.8 V ≤ VDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 0 355 ns 1.8 V ≤ VDD < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 0 405 ns Notes 1. The value must be equal to or less than f MCK/4. 2. Set t SU:DAT so that it will not exceed the hold time when SCLr = “L” or SCLr = “H”. Caution Select the N-ch open drain output (V DD tolerance) mode for SDAr by using port output mode register h (POMh). (Remarks are listed on the next page.)

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 37 of 109 Simplified I2C mode connection diagram (during communication at same potential) RL78 microcontroller SDAr SCLr SDA SCL User's device VDD Rb Simplified I2C mode serial transfer timing (during communication at same potential) SDAr tLOW tHIGH tHD:DAT SCLr tSU:DAT 1/fSCL Remarks 1. R b [Ω]:Communication line (SDAr) pull-up resistance C b [F]: Communication line (SCLr, SDAr) load capacitance 2. r: IIC number (r = 00, 01, 11, 20), h: = POM number (h = 0, 1, 4, 5) 3. f MCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock se lect register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (0, 1, 3)) 4. Simplified I 2C mode is supported only by the R5F102 products.

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 38 of 109 (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode Unit MIN. MAX. MIN. MAX. Transfer rate Note4 Reception 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V f MCK/6 Note1 f MCK/6 Note1 bps Theoretical value of the maximum transfer rate f MCK = fCLKNote3 4.0 1.3 Mbps 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V f MCK/6 Note1 f MCK/6 Note1 bps Theoretical value of the maximum transfer rate fMCK = fCLKNote3 4.0 1.3 Mbps 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V f MCK/6 Notes1, 2 f MCK/6 Notes1, 2 bps Theoretical value of the maximum transfer rate fMCK = fCLKNote3 4.0 1.3 Mbps Transmission 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V Note4 Note4 bps Theoretical value of the maximum transfer rate C b = 50 pF, Rb = 1.4 kΩ, Vb = 2.7 V 2.8 Note5 2.8 Note5 Mbps 2.7 V ≤ VDD < 4.0 V, Note6 Note6 bps Theoretical value of the maximum transfer rate C b = 50 pF, Rb = 2.7 kΩ, Vb = 2.3 V 1.2 Note7 1.2 Note7 Mbps 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Notes 2, 8 Notes 2, 8 bps Theoretical value of the maximum transfer rate C b = 50 pF, Rb = 5.5 kΩ, Vb = 1.6 V 0.43 Note9 0.43 Note9 Mbps Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only. 2. Use it with VDD ≥ Vb. 3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main ) mode: 24 MHz (2.7 V ≤ VDD ≤ 5.5 V) 16 MHz (2.4 V ≤ VDD ≤ 5.5 V) LS (low-speed main ) mode: 8 MHz (1.8 V ≤ VDD ≤ 5.5 V) 4. The smaller maximum transfer rate derived by using f MCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V ≤ VDD ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V Maximum transfer rate = [bps] Vb )} × 3 Transfer rate × 2 – {–Cb × Rb × ln (1 – 2.2 Vb )} Baud rate error (theoretical value) = × 100 [%] ( 1 Transfer rate ) × Number of transferred bits * This value is the theoretical value of the relative difference between the transmission and reception sides.

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 39 of 109 5. This value as an example is calcul ated when the conditions described in the “Conditions” column are met. Refer to Note 4 above to calculate the maximum transfer rate under conditions of the customer. 6. The smaller maximum transfer rate derived by using f MCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V ≤ VDD < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V Maximum transfer rate = [bps] Vb )} × 3 Transfer rate × 2 – {–Cb × Rb × ln (1 – 2.0 Vb )} Baud rate error (theoretical value) = × 100 [%] ( 1 Transfer rate ) × Number of transferred bits * This value is the theoretical value of the relative difference between the transmission and reception sides. 7. This value as an example is calcul ated when the conditions described in the “Conditions” column are met. Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer. 8. The smaller maximum transfer rate derived by using f MCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Maximum transfer rate = [bps] Vb )} × 3 Transfer rate × 2 – {–Cb × Rb × ln (1 – 1.5 Vb )} Baud rate error (theoretical value) = × 100 [%] ( 1 Transfer rate ) × Number of transferred bits * This value is the theoretical value of the relative difference between the transmission and reception sides. 9. This value as an example is calculated when the condi tions described in the “Conditions” column are met. Refer to Note 8 above to calculate the maximum transfer rate under conditions of the customer. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (V DD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 40 of 109 UART mode connection diagram (during communication at different potential) RL78 microcontroller TxDq RxDq Rx Tx User's device Vb Rb UART mode bit width (during communication at different potential) (reference) TxDq RxDq Baud rate error tolerance High-/Low-bit width 1/Transfer rate Baud rate error tolerance High-bit width Low-bit width 1/Transfer rate Remarks 1. R b[Ω]: Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage 2. q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock sele ct register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10, 11)) 4. UART0 of the 20- and 24-pin products supports communication at different potential only when the peripheral I/O redirection function is not used.

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 41 of 109 (7) Communication at different potential (2.5 V, 3 V) (s implified SPI (CSI) mode) (mast er mode, SCK00... internal clock output, corresponding CSI00 only) (TA = –40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Condi tions HS (high-speed main) Mode LS (low-speed main) Mode Unit MIN. MAX. MIN. MAX. SCK00 cycle time t KCY1 t KCY1 ≥ 2/fCLK 4.0 V ≤ VDD ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ 200 1150 ns 2.7 V ≤ VDD < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ 300 1150 ns SCK00 high-level width t KH1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ tKCY1/2 – t KCY1/2 – ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ tKCY1/2 – 120 t KCY1/2 – 120 ns SCK00 low-level width t KL1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ tKCY1/2 – tKCY1/2 – ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ tKCY1/2 – t KCY1/2 – ns SI00 setup time (to SCK00↑) Note 1 tSIK1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ 58 479 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ 121 479 ns SI00 hold time (from SCK00↑) Note 1 tKSI1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ 10 10 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ 10 10 ns Delay time from SCK00↓ to SO00 output Note 1 tKSO1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ 60 60 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ 130 130 ns SI00 setup time (to SCK00↓) Note 2 tSIK1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ 23 110 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ 33 110 ns SI00 hold time (from SCK00↓) Note 2 tKSI1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ 10 10 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ 10 10 ns Delay time from SCK00↑ to SO00 output Note 2 tKSO1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ 10 10 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ 10 10 ns (Notes, Caution, and Remarks are listed on the next page.)

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 42 of 109 Notes 1. When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1 2. When DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0. Caution Select the TTL input buffer for the SI00 pin and the N-ch open drain output (V DD tolerance) mode for the SO00 pin and SCK00 pin by using port input mode register 1 (PIM1) and port output mode register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remarks 1. R b [Ω]:Communication line (SCK00, SO00) pull-up resistance, Cb [F]: Communication line (SCK00, SO00) load capacitance, Vb [V]: Communication line voltage 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register 0 (SPS0 ) and the CKS00 bit of serial mode register 00 (SMR00).)

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 43 of 109 internal clock output) (1/3) (TA = –40 to +85°C, 1.8 V ≤ VDD ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditi ons HS (high-speed main) Mode LS (low-speed main) Mode Unit MIN. MAX. MIN. MAX. SCKp cycle time t KCY1 t KCY1 ≥ 4/fCLK 4.0 V ≤ VDD ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 300 1150 ns 2.7 V ≤ VDD < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 500 1150 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note, Cb = 30 pF, Rb = 5.5 kΩ 1150 1150 ns SCKp high-level width t KH1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ tKCY1/2 –75 tKCY1/2–75 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ tKCY1/2 –170 tKCY1/2–170 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note, Cb = 30 pF, Rb = 5.5 kΩ tKCY1/2 –458 tKCY1/2–458 ns SCKp low-level width t KL1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ tKCY1/2 –12 tKCY1/2–50 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ tKCY1/2 –18 tKCY1/2–50 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note, Cb = 30 pF, Rb = 5.5 kΩ tKCY1/2 –50 tKCY1/2–50 ns Note Use it with VDD ≥ Vb. Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (V DD tolerance) mode for the SOp pin and SCKp pin by using port input mode register 1 (PIM1) and port output mode register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL input buffer selected. 2. CSI01 and CSI11 cannot communicate at different potential. Remarks 1. R b [Ω]: Communication line (SCKp, SOp) pull-up resistance, C b [F]: Communication line (SCKp, SOp) load capacitance, Vb [V]: Communication line voltage 2. p: CSI number (p = 00, 20)

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 44 of 109 internal clock output) (2/3) (TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Condi tions HS (high-speed main) Mode LS (low-speed main) Mode Unit MIN. MAX. MIN. MAX. SIp setup time (to SCKp↑) Note 1 tSIK1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 81 479 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 177 479 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 30 pF, Rb = 5.5 kΩ 479 479 ns SIp hold time (from SCKp↑) Note 1 tKSI1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 19 19 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 19 19 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 30 pF, Rb = 5.5 kΩ 19 19 ns Delay time from SCKp↓ to SOp output Note 1 tKSO1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 100 100 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 195 195 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 30 pF, Rb = 5.5 kΩ 483 483 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. 2. Use it with VDD ≥ Vb. (Cautions and Remarks are listed on the next page.)

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 45 of 109 internal clock output) (3/3) (TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Condi tions HS (high-speed main) Mode LS (low-speed main) Mode Unit MIN. MAX. MIN. MAX. SIp setup time (to SCKp↓) Note 1 tSIK1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 44 110 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 44 110 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 30 pF, Rb = 5.5 kΩ 110 110 ns SIp hold time (from SCKp↓) Note 1 tKSI1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 19 19 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 19 19 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 30 pF, Rb = 5.5 kΩ 19 19 ns Delay time from SCKp↑ to SOp output Note 1 tKSO1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 25 25 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 25 25 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 30 pF, Rb = 5.5 kΩ 25 25 ns Notes 1. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. Use it with VDD ≥ Vb. Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (V DD tolerance) mode for the SOp pin and SCKp pin by using port input mode register 1 (PIM1) and port output mode register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL input buffer selected. 2. CSI01 and CSI11 cannot communicate at different potential. Remarks 1. R b [Ω]: Communication line (SCKp, SOp) pull-up resistance, C b [F]: Communication line (SCKp, SOp) load capacitance, Vb [V]: Communication line voltage 2. p: CSI number (p = 00, 20), m: Unit numbe r (m = 0, 1), n: Channel number (n = 0) Simplified SPI (CSI) mode connection diagram (during communication at different potential) Vb Rb SCKp SOp SCK SI User's deviceSIp SO Vb Rb <Master> RL78 microcontroller

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 46 of 109 Simplified SPI (CSI) mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1) Input data Output data SIp SOp tKCY1 tKL1 tKH1 tSIK1 tKSI1 tKSO1 SCKp Simplified SPI (CSI) mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1 tKL1tKH1 tSIK1 tKSI1 tKSO1 SIp SOp SCKp Input data Output data

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 47 of 109 clock input) (TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditi ons HS (high-speed main) Mode LS (low-speed main) Mode Unit MIN. MAX. MIN. MAX. SCKp cycle time Note 1 t KCY2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V

20 MHz < fMCK ≤ 24 MHz 12/f MCK – ns

8 MHz < fMCK ≤ 20 MHz 10/f MCK – ns

4 MHz < fMCK ≤ 8 MHz 8/f MCK 16/f MCK ns

fMCK ≤ 4 MHz 6/f MCK 10/f MCK ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V

20 MHz < fMCK ≤ 24 MHz 16/f MCK – ns

16 MHz < fMCK ≤ 20 MHz 14/f MCK – ns

8 MHz < fMCK ≤ 16 MHz 12/f MCK – ns

fMCK ≤ 4 MHz 6/fMCK 10/f MCK ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2

20 MHz < fMCK ≤ 24 MHz 36/f MCK – ns

16 MHz < fMCK ≤ 20 MHz 32/f MCK – ns

8 MHz < fMCK ≤ 16 MHz 26/f MCK – ns

4 MHz < fMCK ≤ 8 MHz 16/fMCK 16/f MCK ns

fMCK ≤ 4 MHz 10/fMCK 10/f MCK ns SCKp high-/low-level width tKH2, tKL2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V tKCY2/2 – 12 t KCY2/2 – 50 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V tKCY2/2 – 18 t KCY2/2 – 50 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2 tKCY2/2 – 50 t KCY2/2 – 50 ns SIp setup time (to SCKp↑) Note 3 tSIK2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ VDD ≤ 4.0 V 1/fMCK + 20 1/f MCK + 30 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V 1/fMCK + 20 1/f MCK + 30 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ VDD ≤ 2.0 V Note 2 1/fMCK + 30 1/f MCK + 30 ns SIp hold time (from SCKp↑) Note 4 tKSI2 1/fMCK + 31 1/f MCK + 31 ns Delay time from SCKp↓ to SOp output Note 5 tKSO2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 2/f MCK + 120 2/f MCK + 573 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 2/fMCK + 214 2/fMCK + 573 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 30 pF, Rb = 5.5 kΩ 2/f MCK + 573 2/f MCK + 573 ns Notes 1. Transfer rate in the SNOOZE mode: MAX. 1 Mbps 2. Use it with VDD ≥ Vb. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Cautions 1. Select the TTL input buffer for the SIp and SCKp pins and the N-ch open drain output (V DD tolerance) mode for the SOp pin by using port input mode register 1 (PIM1) and port output mode register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL input buffer selected. 2. CSI01 and CSI11 cannot communicate at different potential.

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 48 of 109 Simplified SPI (CSI) mode connection diagram (during communication at different potential) RL78 microcontroller SOp SCK SI User's deviceSIp SO Vb Rb SCKp <Slave> Remarks 1. R b [Ω]: Communication line (SOp) pull-up resistance, Cb [F]: Communication line (SOp) load capacitance, V b [V]: Communication line voltage 2. p: CSI number (p = 00, 20), m: Unit numbe r (m = 0, 1), n: Channel number (n = 0) 3. f MCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 10)) Simplified SPI (CSI) mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY2 tKL2 tKH2 tSIK2 tKSI2 tKSO2 SIp SOp SCKp Input data Output data

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 49 of 109 Simplified SPI (CSI) mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY2 tKL2tKH2 tSIK2 tKSI2 tKSO2 SIp SOp SCKp Input data Output data Remark p: CSI number (p = 00, 20), m: Unit numbe r (m = 0, 1), n: Channel number (n = 0)

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 50 of 109 (10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Condi tions HS (high-speed main) Mode LS (low-speed main) Mode Unit MIN. MAX. MIN. MAX. SCLr clock frequency f SCL 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 kΩ

400 Note1 300 Note1 kHz

2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,Note2 Cb = 100 pF, Rb = 5.5 kΩ

300 Note1 300 Note1 kHz

Hold time when SCLr = “L” t LOW 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 kΩ 1150 1550 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 1150 1550 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,Note2 Cb = 100 pF, Rb = 5.5 kΩ 1550 1550 ns Hold time when SCLr = “H” t HIGH 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 kΩ 675 610 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 600 610 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,Note2 Cb = 100 pF, Rb = 5.5 kΩ 610 610 ns Data setup time (reception) t SU:DAT 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 kΩ 1/fMCK + 190 Note3 1/f MCK + 190 Note3 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 1/fMCK + 190 Note3 1/f MCK + 190 Note3 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,Note2 Cb = 100 pF, Rb = 5.5 kΩ 1/fMCK + 190 Note3 1/fMCK + 190 Note3 ns Data hold time (transmission) tHD:DAT 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 kΩ 0 355 0 355 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 0 355 0 355 ns 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,Note2 Cb = 100 pF, Rb = 5.5 kΩ 0 405 0 405 ns Notes 1. The value must be equal to or less than fMCK/4. 2. Use it with VDD ≥ Vb. 3. Set tSU:DAT so that it will not exceed the hold time when SCLr = “L” or SCLr = “H”. Cautions 1. Select the TTL input buffer and the N-ch open drain output (V DD tolerance) mode for the SDAr pin and the N-ch open drain output (V DD tolerance) mode for the SCLr pin by using port input mode register 1 (PIM1) and port output mode register 1 (POM1). For V IH and V IL, see the DC characteristics with TTL input buffer selected. 2. IIC01 and IIC11 cannot communicate at different potential. (Remarks are listed on the next page.)

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 51 of 109 Simplified I2C mode connection diagram (during communication at different potential) SDAr SCLr SDA SCL User's device Vb Rb Vb Rb RL78 microcontroller Simplified I2C mode serial transfer timing (during communication at different potential) SDAr tLOW tHIGH tHD : DAT SCLr tSU : DAT 1/fSCL Remarks 1. R b [Ω]: Communication line (SDAr, SCLr) pull-up resistance, C b [F]: Communication line (SDAr, SCLr) load capacitance, Vb [V]: Communication line voltage 2. r: IIC Number (r = 00, 20) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0,1), n: Channel number (n = 0)) 4. Simplified I 2C mode is supported only by the R5F102 products.

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2.5.2 Serial interface IICA

(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) mode LS (low-speed main) mode Unit Standard Mode Fast Mode MIN. MAX. MIN. MAX. SCLA0 clock frequency f SCL Fast mode: f CLK ≥ 3.5 MHz 0 400 kHz Normal mode: fCLK ≥ 1 MHz 0 100 kHz Setup time of restart condition t SU:STA 4.7 0.6 µs Hold timeNote 1 t HD:STA 4.0 0.6 µs Hold time when SCLA0 = “L” t LOW 4.7 1.3 µs Hold time when SCLA0 = “H” t HIGH 4.0 0.6 µs Data setup time (reception) t SU:DAT 250 100 ns Data hold time (transmission)Note 2 t HD:DAT 0 3.45 0 0.9 µs Setup time of stop condition t SU:STO 4.0 0.6 µs Bus-free time t BUF 4.7 1.3 µs Notes 1. The first clock pulse is generated after this per iod when the start/restart condition is detected. 2. The maximum value (MAX.) of t HD:DAT is during normal transfer and a cloc k stretch state is inserted in the ACK (acknowledge) timing. Caution Only in the 30-pin products, the values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection register (PIOR) is 1. At this time, the pin characteristics (I OH1, I OL1, V OH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of C b (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Normal mode: C b = 400 pF, Rb = 2.7 kΩ Fast mode: C b = 320 pF, Rb = 1.1 kΩ IICA serial transfer timing tLOW tR tHIGH tF tBUF tHD:DAT tSU:DATtHD:STA tSU:STA tHD:STA tSU:STO SCLA0 SDAA0 Stop condition Start condition Restart condition Stop condition

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2.6 Analog Characteristics

2.6.1 A/D converter characteristics

Classification of A/D converter characteristics Input channel Reference Voltage Reference voltage (+) = AVREFP Reference voltage (–) = AVREFM Reference voltage (+) = VDD Reference voltage (–) = VSS Reference voltage (+) = VBGR Reference voltage (–) = AVREFM ANI16 to ANI22 Refer to 2.6.1 (2). Internal reference voltage Temperature sensor output voltage Refer to 2.6.1 (1). – (1) When reference voltage (+) = AV REFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (–) = AV REFM/ANI1 (ADREFM = 1), target pin: ANI2, ANI3, internal reference voltage, and temperature sensor output voltage A = –40 to +85°C, 1.8 V ≤ AVREFP ≤ VDD ≤ 5.5 V, V SS = 0 V, Reference voltage (+) = AV REFP, Reference voltage (–) = AVREFM = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 8 10 bit Overall errorNote 1 AINL 10-bit resolution AVREFP = VDD Note 3 1.2 ±3.5 LSB 1.2 ±7.0 Note 4 LSB Conversion time t CONV 10-bit resolution Target pin: ANI2, ANI3 3.6 V ≤ VDD ≤ 5.5 V 2.125 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 µs 1.8 V ≤ VDD ≤ 5.5 V 17 39 µs 57 95 µs 10-bit resolution Target pin: Internal reference voltage, and temperature sensor output voltage (HS (high-speed main) mode)

3.6 V ≤ V

DD ≤ 5.5 V 2.375 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.5625 39 µs 2.4 V ≤ VDD ≤ 5.5 V 17 39 µs Zero-scale errorNotes 1, 2 EZS 10-bit resolution AVREFP = VDD Note 3 ±0.25 %FSR ±0.50 Note 4 %FSR Full-scale errorNotes 1, 2 EFS 10-bit resolution AVREFP = VDD Note 3 ±0.25 %FSR ±0.50 Note 4 %FSR Integral linearity errorNote 1 ILE 10-bit resolution AVREFP = VDD Note 3 ±2.5 LSB ±5.0 Note 4 LSB Differential linearity error Note 1 DLE 10-bit resolution AVREFP = VDD Note 3 ±1.5 LSB ±2.0 Note 4 LSB Analog input voltage V AIN ANI2, ANI3 0 AV REFP V Internal reference voltage (2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode) VBGR Note 5 V Temperature sensor output voltage (2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode) VTMPS25 Note 5 V (Notes are listed on the next page.)

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 54 of 109 Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When AV REFP < VDD, the MAX. values are as follows. Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD. 4. Values when the conversion time is set to 57 µs (min.) and 95 µs (max.). 5. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics. (2) When reference voltage (+) = AV REFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (–) = AV REFM/ANI1 (ADREFM = 1), target pin: ANI16 to ANI22 (TA = –40 to +85°C, 1.8 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = AV REFP, Reference voltage (–) = AVREFM = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution R ES 8 10 bit Overall error Note 1 AINL 10-bit resolution AVREFP = VDD Note 3 1.2 ±5.0 LSB 1.2 ±8.5 Note 4 LSB Conversion time t CONV 10-bit resolution Target ANI pin: ANI16 to ANI22 3.6 V ≤ VDD ≤ 5.5 V 2.125 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 µs 1.8 V ≤ VDD ≤ 5.5 V 17 39 µs 57 95 µs Zero-scale error Notes 1, 2 EZS 10-bit resolution AVREFP = VDD Note 3 ±0.35 %FSR ±0.60 Note 4 %FSR Full-scale error Notes 1, 2 EFS 10-bit resolution AVREFP = VDD Note 3 ±0.35 %FSR ±0.60 Note 4 %FSR Integral linearity error Note 1 ILE 10-bit resolution AVREFP = VDD Note 3 ±3.5 LSB ±6.0 Note 4 LSB Differential linearity error Note 1 DLE 10-bit resolution AVREFP = VDD Note 3 ±2.0 LSB ±2.5 Note 4 LSB Analog input voltage V AIN ANI16 to ANI22 0 AV REFP and VDD V Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When AV REFP ≤ VDD, the MAX. values are as follows. Overall error: Add ±4.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add ±0.20%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add ±2.0 LSB to the MAX. value when AVREFP = VDD. 4. When the conversion time is set to 57 µs (min.) and 95 µs (max.).

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 55 of 109 (3) When reference voltage (+) = V DD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (–) = V SS (ADREFM = 0), target pin: ANI0 to ANI3, ANI16 to ANI22, internal reference voltage, and temperature sensor output voltage (TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = VDD, Reference voltage (–) = VSS) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution R ES 8 10 bit Overall errorNote 1 AINL 10-bit resolution 1.2 ±7.0 LSB 1.2 ±10.5 Note 3 LSB Conversion time t CONV 10-bit resolution Target pin: ANI0 to ANI3, ANI16 to ANI22 DD ≤ 5.5 V 2.125 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 µs 1.8 V ≤ VDD ≤ 5.5 V 17 39 µs 57 95 µs Conversion time t CONV 10-bit resolution Target pin: internal reference voltage, and temperature sensor output voltage (HS (high-speed main) mode) DD ≤ 5.5 V 2.375 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.5625 39 µs 2.4 V ≤ VDD ≤ 5.5 V 17 39 µs Zero-scale errorNotes 1, 2 EZS 10-bit resolution ±0.60 %FSR ±0.85 Note 3 %FSR Full-scale errorNotes 1, 2 EFS 10-bit resolution ±0.60 %FSR ±0.85 Note 3 %FSR Integral linearity errorNote 1 ILE 10-bit resolution ±4.0 LSB ±6.5 Note 3 LSB Differential linearity error Note 1 DLE 10-bit resolution ±2.0 LSB ±2.5 Note 3 LSB Analog input voltage V AIN ANI0 to ANI3, ANI16 to ANI22 0 V DD V Internal reference voltage (2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode) VBGR Note 4 V Temperature sensor output voltage (2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode) VTMPS25 Note 4 V Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When the conversion time is set to 57 µs (min.) and 95 µs (max.). 4. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics.

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 56 of 109 (4) When reference voltage (+) = Inte rnal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (–) = AVREFM (ADREFM = 1), target pin: ANI0, ANI2, ANI3, and ANI16 to ANI22 (TA = –40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = V BGR Note 3, Reference voltage (–) = AVREFM Note 4= 0 V, HS (high-speed main) mode) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution R ES 8 bit Conversion time t CONV 8-bit resolution 17 39 µs Zero-scale errorNotes 1, 2 EZS 8-bit resolution ±0.60 %FSR Integral linearity errorNote 1 ILE 8-bit resolution ±2.0 LSB Differential linearity error Note 1 DLE 8-bit resolution ±1.0 LSB Analog input voltage V AIN 0 V BGR Note 3 V Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics. 4. When reference voltage (–) = V SS, the MAX. values are as follows. Zero-scale error: Add ±0.35%FSR to the MAX. value when reference voltage (–) = AVREFM. Integral linearity error: Add ±0.5 LSB to the MAX. value when reference voltage (–) = AVREFM. Differential linearity error: Add ±0.2 LSB to the MAX. value when reference voltage (–) = AVREFM.

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 57 of 109

2.6.2 Temperature sensor/internal reference voltage characteristics

(TA = –40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, HS (high-speed main) mode Parameter Symbol Conditions MIN. TYP. MAX. Unit Temperature sensor output voltage V TMPS25 Setting ADS register = 80H, TA = +25°C 1.05 V Internal reference voltage V BGR Setting ADS register = 81H 1.38 1.45 1.50 V Temperature coefficient F VTMPS Temperature sensor output voltage that depends on the temperature –3.6 mV/°C Operation stabilization wait time t AMP 5 µs

2.6.3 POR circuit characteristics

(TA = –40 to +85°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage V POR The power supply voltage is rising. 1.47 1.51 1.55 V VPDR The power supply voltage is falling. 1.46 1.50 1.54 V Minimum pulse width Note T PW 300 µs Note Minimum time required for a POR reset when V DD exceeds below VPDR. This is also the minimum time required for a POR reset from when V DD exceeds below 0.7 V to when V DD exceeds VPOR while STOP mode is entered or the main system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register (CSC). TPW VPOR VPDR or 0.7 V Supply voltage (VDD)

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2.6.4 LVD circuit characteristics

LVD Detection Voltage of Reset Mode and Interrupt Mode A = –40 to +85°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection supply voltage V LVD0 The power supply voltage is rising. 3.98 4.06 4.14 V The power supply voltage is falling. 3.90 3.98 4.06 V VLVD1 The power supply voltage is rising. 3.68 3.75 3.82 V The power supply voltage is falling. 3.60 3.67 3.74 V VLVD2 The power supply voltage is rising. 3.07 3.13 3.19 V The power supply voltage is falling. 3.00 3.06 3.12 V VLVD3 The power supply voltage is rising. 2.96 3.02 3.08 V The power supply voltage is falling. 2.90 2.96 3.02 V VLVD4 The power supply voltage is rising. 2.86 2.92 2.97 V The power supply voltage is falling. 2.80 2.86 2.91 V VLVD5 The power supply voltage is rising. 2.76 2.81 2.87 V The power supply voltage is falling. 2.70 2.75 2.81 V VLVD6 The power supply voltage is rising. 2.66 2.71 2.76 V The power supply voltage is falling. 2.60 2.65 2.70 V VLVD7 The power supply voltage is rising. 2.56 2.61 2.66 V The power supply voltage is falling. 2.50 2.55 2.60 V VLVD8 The power supply voltage is rising. 2.45 2.50 2.55 V The power supply voltage is falling. 2.40 2.45 2.50 V VLVD9 The power supply voltage is rising. 2.05 2.09 2.13 V The power supply voltage is falling. 2.00 2.04 2.08 V VLVD10 The power supply voltage is rising. 1.94 1.98 2.02 V The power supply voltage is falling. 1.90 1.94 1.98 V VLVD11 The power supply voltage is rising. 1.84 1.88 1.91 V The power supply voltage is falling. 1.80 1.84 1.87 V Minimum pulse width t LW 300 µs Detection delay time 300 µs

RL78/G12 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 59 of 109 LVD detection voltage of interrupt & reset mode (TA = –40 to +85°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Interrupt and reset mode VLVDB0 V POC2, VPOC1, VPOC0 = 0, 0, 1, falling reset voltage 1.80 1.84 1.87 V VLVDB1 LVIS1, LVIS0 = 1, 0 Rising reset release voltage 1.94 1.98 2.02 V Falling interrupt voltage 1.90 1.94 1.98 V VLVDB2 LVIS1, LVIS0 = 0, 1 Rising reset release voltage 2.05 2.09 2.13 V Falling interrupt voltage 2.00 2.04 2.08 V VLVDB3 LVIS1, LVIS0 = 0, 0 Rising reset release voltage 3.07 3.13 3.19 V Falling interrupt voltage 3.00 3.06 3.12 V VLVDC0 V POC2, VPOC1, VPOC0 = 0, 1, 0, falling reset voltage 2.40 2.45 2.50 V VLVDC1 LVIS1, LVIS0 = 1, 0 Rising reset release voltage 2.56 2.61 2.66 V Falling interrupt voltage 2.50 2.55 2.60 V VLVDC2 LVIS1, LVIS0 = 0, 1 Rising reset release voltage 2.66 2.71 2.76 V Falling interrupt voltage 2.60 2.65 2.70 V VLVDC3 LVIS1, LVIS0 = 0, 0 Rising reset release voltage 3.68 3.75 3.82 V Falling interrupt voltage 3.60 3.67 3.74 V VLVDD0 V POC2, VPOC1, VPOC1 = 0, 1, 1, falling reset voltage 2.70 2.75 2.81 V VLVDD1 LVIS1, LVIS0 = 1, 0 Rising reset release voltage 2.86 2.92 2.97 V Falling interrupt voltage 2.80 2.86 2.91 V VLVDD2 LVIS1, LVIS0 = 0, 1 Rising reset release voltage 2.96 3.02 3.08 V Falling interrupt voltage 2.90 2.96 3.02 V VLVDD3 LVIS1, LVIS0 = 0, 0 Rising reset release voltage 3.98 4.06 4.14 V Falling interrupt voltage 3.90 3.98 4.06 V

2.6.5 Power supply voltage rising slope characteristics

(TA = –40 to +85°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Power supply voltage rising slope S VDD 54 V/ms Caution Make sure to keep the internal reset state by the LVD circuit or an external reset until V DD reaches the operating voltage range shown in 2.4 AC Characteristics.

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2.7 RAM Data Retention Characteristics

(TA = –40 to +85°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention supply voltage V DDDR 1.46 Note 5.5 V Note This depends on the POR detection voltage. For a fallin g voltage, data in RAM are retained until the voltage reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is generated. VDD STOP instruction execution Standby release signal (interrupt request) STOP mode RAM data retention VDDDR Operation mode

2.8 Flash Memory Programming Characteristics

(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit System clock frequency f CLK 1 24 MHz Code flash memory rewritable times Notes 1, 2, 3 Cerwr Retained for 20 years TA = 85°C 1,000 Times Data flash memory rewritable times Notes 1, 2, 3 Retained for 1 year TA = 25°C 1,000,000 Retained for 5 years TA = 85°C 100,000 Retained for 20 years TA = 85°C 10,000 Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewr ite. The retaining years are until next rewrite after the rewrite. 2. When using flash memory programmer and Renesas Electronics self programming library 3. These are the characteristics of t he flash memory and the results obtai ned from reliability testing by Renesas Electronics Corporation.

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2.9 Dedicated Flash Memory Programmer Communication (UART)

(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate During serial programming 115,200 1,000,000 bps

2.10 Timing of Entry to Flash Memory Programming Modes

(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Time to complete the communication for the initial setting after the external reset is released tSUINIT POR and LVD reset are released before external reset release 100 ms Time to release the external reset after the TOOL0 pin is set to the low level tSU POR and LVD reset are released before external reset release 10 µs Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing time of the firmware to control the flash memory) tHD POR and LVD reset are released before external reset release 1 ms RESET TOOL0 tSUINIT tHD + software processing time 1-byte data for setting mode tSU <4> <1> The low level is input to the TOOL0 pin. <2> The external reset is released (POR and LVD reset must be released before the external reset is released.). <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. Remark t SUINIT: Communication for the initial setting must be complet ed within 100 ms after the external reset is released during this period. tSU: Time to release the exte rnal reset after the TOOL0 pin is set to the low level tHD: Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing time of the firmware to control the flash memory)

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 62 of 109 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) This chapter describes the following electrical specifications. Target products G: Industrial applications T A = -40 to +105°C R5F102xxGxx Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. product in the RL78/G12 User’s Manual. 3. Please contact Renesas Electronics sal es office for derating of operation under T A = +85°C to +105°C. Derating is the systematic reduction of load for the sake of improved reliability. Remark When the RL78 microcontroller is used in the range of T A = -40 to +85°C, see 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C). There are following differences between the products “G: Industrial applications (T A = -40 to +105°C)” and the products “A: Consumer applications, and D: Industrial applications”. Parameter Application A: Consumer applications, D: Industrial applications G: Industrial applications Operating ambient temperature T A = -40 to +85°C T A = -40 to +105°C Operating mode Operating voltage range HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 24 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz LS (low-speed main) mode: DD ≤ 5.5 V@1 MHz to 8 MHz HS (high-speed main) mode only: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 24 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz High-speed on-chip oscillator clock accuracy R5F102 products, 1.8 V ≤ VDD ≤ 5.5 V: R5F103 products, 1.8 V ≤ VDD ≤ 5.5 V: R5F102 products, 2.4 V ≤ VDD ≤ 5.5 V: Serial array unit UART Simplified SPI (CSI): fCLK/2 (supporting 12 Mbps), fCLK/4 Simplified I2C communication UART Simplified SPI (CSI): fCLK/4 Simplified I2C communication Voltage detector Rise detection voltage: 1.88 V to 4.06 V (12 levels) Fall detection voltage: 1.84 V to 3.98 V (12 levels) Rise detection voltage: 2.61 V to 4.06 V (8 levels) Fall detection voltage: 2.55 V to 3.98 V (8 levels) Remark The electrical characteristics of t he products G: Industrial applications (TA = -40 to +105°C) are different from those of the products “A: Consumer applications, and D: Industrial applications”. For details, refer to 3.1 to 3.10.

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3.1 Absolute Maximum Ratings

Absolute Maximum Ratings (TA = 25°C) Parameter Symbols Condi tions Ratings Unit Supply Voltage V DD –0.5 to + 6.5 V REGC terminal input voltageNote1 VIREGC REGC –0.3 to +2.8 and –0.3 to VDD + 0.3 Note 2 V Input Voltage V I1 Other than P60, P61 –0.3 to V DD + 0.3Note 3 V VI2 P60, P61 (N-ch open drain) –0.3 to 6.5 V Output Voltage V O –0.3 to V DD + 0.3Note 3 V Analog input voltage V AI 20, 24-pin products: ANI0 to ANI3, ANI16 to ANI22 30-pin products: ANI0 to ANI3, ANI16 to ANI19 –0.3 to VDD + 0.3 and –0.3 to AVREF(+)+0.3 Notes 3, 4 V Output current, high IOH1 Per pin Other than P20 to P23 –40 mA Total of all pins All the terminals other than P20 to P23 –170 mA 20-, 24-pin products: P40 to P42 30-pin products: P00, P01, P40, P120 –70 mA 20-, 24-pin products: P00 to P03Note 5, P10 to P14 30-pin products: P10 to P17, P30, P31, P50, P51, P147 –100 mA IOH2 Per pin P20 to P23 –0.5 mA Total of all pins –2 mA Output current, low I OL1 Per pin Other than P20 to P23 40 mA Total of all pins All the terminals other than P20 to P23 170 mA 20-, 24-pin products: P40 to P42 30-pin products: P00, P01, P40, P120 70 mA 20-, 24-pin products: P00 to P03 Note 5, P10 to P14, P60, P61 30-pin products: P10 to P17, P30, P31, P50, P51, P60, P61, P147 100 mA IOL2 Per pin P20 to P23 1 mA Total of all pins 5 mA Operating ambient temperature TA –40 to +105 °C Storage temperature T stg –65 to +150 °C Notes 1. 30-pin product only. 2. Connect the REGC pin to VSS via a capacitor (0.47 to 1 µF). This value determines the absolute maximum rating of the REGC pin. Do not use it with voltage applied. 3. Must be 6.5 V or lower. 4. Do not exceed AV REF (+) + 0.3 V in case of A/D conversion target pin . 5. 24-pin products only. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remarks 1. Unless specified otherwise, the characteristics of alter nate-function pins are the same as those of the port pins. 2. AV REF(+) : + side reference voltage of the A/D converter. 3. V SS : Reference voltage

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 64 of 109

3.2 Oscillator Characteristics

3.2.1 X1 oscillator characteristics

(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Resonator Conditions MIN. TYP. MAX. Unit X1 clock oscillation frequency (fX)Note Ceramic resonator / crystal oscillator 2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz 2.4 V ≤ VDD < 2.7 V 1.0 8.0 Note Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics. Caution Since the CPU is started by the high-speed on-chip osc illator clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscilla tion stabilization time of the OSTC register and the oscillation stabilization time select register (OSTS) after suffi ciently evaluating the o scillation stabilization time with the resonator to be used. Remark When using the X1 oscillator, refer to 5.4 System Clock Oscillator in the RL78/G12 User’s Manual.

3.2.2 On-chip oscillator characteristics

(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Oscillators Parameters Conditions MIN. TYP. MAX. Unit High-speed on-chip oscillator clock frequency Notes 1, 2 fIH 1 24 MHz High-speed on-chip oscillator clock frequency accuracy R5F102 products T A = –20 to +85°C -1.0 +1.0 % Low-speed on-chip oscillator clock frequency fIL 15 kHz Low-speed on-chip oscillator clock frequency accuracy -15 +15 % Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H) and bits 0 to 2 of HOCODIV register. 2. This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time.

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3.3 DC Characteristics

3.3.1 Pin characteristics

Parameter Symbol Conditions MIN. TYP. MAX. Unit Output current, highNote 1 I OH1 20-, 24-pin products: Per pin for P00 to P03Note 4, P10 to P14, P40 to P42 30-pin products: Per pin for P00, P01, P10 to P17, P30, P31, P40, P50, P51, P120, P147 –3.0 Note 2 mA 20-, 24-pin products: Total of P40 to P42 30-pin products: Total of P00, P01, P40, P120 (When duty ≤ 70% Note 3) 4.0 V ≤ VDD ≤ 5.5 V –9.0 mA 2.7 V ≤ VDD < 4.0 V –6.0 mA 2.4 V ≤ VDD < 2.7 V –4.5 mA 20-, 24-pin products: Total of P00 to P03Note 4, P10 to P14 30-pin products: Total of P10 to P17, P30, P31, P50, P51, P147 (When duty ≤ 70% Note 3) 4.0 V ≤ VDD ≤ 5.5 V –27.0 mA 2.7 V ≤ VDD < 4.0 V –18.0 mA 2.4 V ≤ VDD < 2.7 V –10.0 mA Total of all pins (When duty ≤ 70%Note 3) –36.0 mA IOH2 Per pin for P20 to P23 –0.1 mA Total of all pins –0.4 mA Notes 1 . value of current at which the device operation is guaranteed even if the current flows from the VDD pin to an output pin. 2. However, do not exceed the total current value. 3. The output current value under conditions where the duty factor ≤ 70%. If duty factor > 70%: The output current value c an be calculated with the following expression (where n represents the duty factor as a percentage).

• Total output current of pins = (IOH × 0.7)/(n × 0.01) <Example> Where n = 80% and I OH = –10.0 mA Total output current of pins = (–10.0 × 0.7)/(80 × 0.01)  –8.7 mA However, the current that is allowed to flow into one pin does not vary depe nding on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. 4. 24-pin products only. Caution P10 to P12 and P41 for 20-pin products, P01, P 10 to P12, and P41 for 24-pin products, and P00, P10 to P15, P17, and P50 for 30-pin products do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the charac teristics of alternate-function pins are the same as those of the port pins.

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 66 of 109 Parameter Symbol Conditions MIN. TYP. MAX. Unit Output current, lowNote 1 I OL1 20-, 24-pin products: Per pin for P00 to P03Note 4, P10 to P14, P40 to P42 30-pin products: Per pin for P00, P01, P10 to P17, P30, P31, P40, P50, P51, P120, P147 8.5 Note 2 mA Per pin for P60, P61 15.0 Note 2 mA 20-, 24-pin products: Total of P40 to P42 30-pin products: Total of P00, P01, P40, P120 (When duty ≤ 70% Note 3) 4.0 V ≤ VDD ≤ 5.5 V 25.5 mA 2.7 V ≤ VDD < 4.0 V 9.0 mA 2.4 V ≤ VDD < 2.7 V 1.8 mA 20-, 24-pin products: Total of P00 to P03Note 4, P10 to P14, P60, P61 30-pin products: Total of P10 to P17, P30, P31, P50, P51, P60, P61, P147 (When duty ≤ 70% Note 3) 4.0 V ≤ VDD ≤ 5.5 V 40.0 mA 2.7 V ≤ VDD < 4.0 V 27.0 mA 2.4 V ≤ VDD < 2.7 V 5.4 mA Total of all pins (When duty ≤ 70%Note 3) 65.5 mA IOL2 Per pin for P20 to P23 0.4 mA Total of all pins 1.6 mA Notes 1 . Value of current at which the devic e operation is guaranteed even if the current flows from an output pin to the VSS pin. 2. However, do not exceed the total current value. 3. The output current value under conditions where the duty factor ≤ 70%. If duty factor > 70%: The output current value c an be calculated with the following expression (where n represents the duty factor as a percentage).

• Total output current of pins = (IOL × 0.7)/(n × 0.01) <Example> Where n = 80% and I OL = 10.0 mA Total output current of pins = (10.0 × 0.7)/(80 × 0.01)  8.7 mA However, the current that is allowed to flow in to one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. 4. 24-pin products only. Remark Unless specified otherwise, the charac teristics of alternate-function pins are the same as those of the port pins.

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 67 of 109 Parameter Symbol Conditions MIN. TYP. MAX. Unit Input voltage, high V IH1 Normal input buffer 20-, 24-pin products: P00 to P03Note 2, P10 to P14, P40 to P42 30-pin products: P00, P01, P10 to P17, P30, P31, P40, P50, P51, P120, P147 0.8VDD V DD V VIH2 TTL input buffer 20-, 24-pin products: P10, P11 30-pin products: P01, P10, P11, P13 to P17 DD ≤ 5.5 V 2.2 V DD V 3.3 V ≤ VDD < 4.0 V 2.0 V DD V 2.4 V ≤ VDD < 3.3 V 1.5 V DD V VIH3 Normal input buffer P20 to P23 0.7VDD V DD V VIH4 P60, P61 0.7V DD 6.0 V VIH5 P121, P122, P125 Note 1, P137, EXCLK, RESET 0.8V DD V DD V Input voltage, low V IL1 Normal input buffer 20-, 24-pin products: P00 to P03Note 2, P10 to P14, P40 to P42 30-pin products: P00, P01, P10 to P17, P30, P31, P40, P50, P51, P120, P147 0 0.2V DD V VIL2 TTL input buffer 20-, 24-pin products: P10, P11 30-pin products: P01, P10, P11, P13 to P17 DD ≤ 5.5 V 0 0.8 V 3.3 V ≤ VDD < 4.0 V 0 0.5 V 2.4 V ≤ VDD < 3.3 V 0 0.32 V VIL3 P20 to P23 0 0.3V DD V VIL4 P60, P61 0 0.3V DD V VIL5 P121, P122, P125 Note 1, P137, EXCLK, RESET 0 0.2V DD V Output voltage, high V OH1 20-, 24-pin products: P00 to P03Note 2, P10 to P14, P40 to P42 30-pin products: P00, P01, P10 to P17, P30, P31, P40, P50, P51, P120, P147 DD ≤ 5.5 V, IOH1 = –3.0 mA VDD–0.7 V 2.7 V ≤ VDD ≤ 5.5 V, IOH1 = –2.0 mA VDD–0.6 V 2.4 V ≤ VDD ≤ 5.5 V, IOH1 = –1.5 mA VDD–0.5 V VOH2 P20 to P23 I OH2 = –100 µA V DD–0.5 V Notes 1. 20, 24-pin products only. 2. 24-pin products only. Caution The maximum value of V IH of pins P10 to P12 and P41 for 20-pin products, P01, P10 to P12, and P41 for 24-pin products, and P00, P10 to P15, P17, and P50 for 30-pin products is V DD even in N-ch open- drain mode. High level is not output in the N-ch open-drain mode. Remark Unless specified otherwise, the charac teristics of alternate-function pins are the same as those of the port pins.

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 68 of 109 Parameter Symbol Conditions MIN. TYP. MAX. Unit Output voltage, low V OL1 20-, 24-pin products: P00 to P03Note, P10 to P14, P40 to P42 30-pin products: P00, P01, P10 to P17, P30, P31, P40, P50, P51, P120, P147 DD ≤ 5.5 V, IOL1 = 8.5 mA 0.7 V 2.7 V ≤ VDD ≤ 5.5 V, IOL1 = 3.0 mA 0.6 V 2.7 V ≤ VDD ≤ 5.5 V, IOL1 = 1.5 mA 0.4 V 2.4 V ≤ VDD ≤ 5.5 V, IOL1 = 0.6 mA 0.4 V VOL2 P20 to P23 I OL2 = 400 µA 0.4 V VOL3 P60, P61 4.0 V ≤ VDD ≤ 5.5 V, IOL1 = 15.0 mA 2.0 V 4.0 V ≤ VDD ≤ 5.5 V, IOL1 = 5.0 mA 0.4 V 2.7 V ≤ VDD ≤ 5.5 V, IOL1 = 3.0 mA 0.4 V 2.4 V ≤ VDD ≤ 5.5 V, IOL1 = 2.0 mA 0.4 V Input leakage current, high ILIH1 Other than P121, P122 VI = VDD 1 µA ILIH2 P121, P122 (X1, X2/EXCLK) VI = VDD Input port or external clock input 1 µA When resonator connected 10 µA Input leakage current, low ILIL1 Other than P121, P122 VI = VSS –1 µA ILIL2 P121, P122 (X1, X2/EXCLK) VI = VSS Input port or external clock input –1 µA When resonator connected –10 µA On-chip pull-up resistance RU 20-, 24-pin products: P00 to P03Note, P10 to P14, P40 to P42, P125, RESET 30-pin products: P00, P01, P10 to P17, P30, P31, P40, P50, P51, P120, P147 V I = VSS, input port 10 20 100 k Ω Note 24-pin products only. Remark Unless specified otherwise, the charac teristics of alternate-function pins are the same as those of the port pins.

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3.3.2 Supply current characteristics

(1) 20-, 24-pin products Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply currentNote 1 IDD1 Operating mode HS (High-speed main) mode Note 4 fIH = 24 MHzNote 3 Basic operation VDD = 5.0 V 1.5 mA VDD = 3.0 V 1.5 Normal operation VDD = 5.0 V 3.3 5.3 mA VDD = 3.0 V 3.3 5.3 fIH = 16 MHzNote 3 VDD = 5.0 V 2.5 3.9 mA VDD = 3.0 V 2.5 3.9 fMX = 20 MHzNote 2, VDD = 5.0 V Square wave input 2.8 4.7 mA Resonator connection 3.0 4.8 fMX = 20 MHzNote 2, VDD = 3.0 V Square wave input 2.8 4.7 mA Resonator connection 3.0 4.8 fMX = 10 MHzNote 2, VDD = 5.0 V Square wave input 1.8 2.8 mA Resonator connection 1.8 2.8 fMX = 10 MHzNote 2, VDD = 3.0 V Square wave input 1.8 2.8 mA Resonator connection 1.8 2.8 Notes 1. Total current flowing into V DD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. When high-speed on-chip oscillator clock is stopped. 3. When high-speed system clock is stopped 4. Relationship between operation voltage width, oper ation frequency of CPU and operation mode is as follows. HS (High speed main) mode: V DD = 2.7 V to 5.5 V @1 MHz to 24 MHz V DD = 2.4 V to 5.5 V @1 MHz to 16 MHz Remarks 1. f MX: High-speed system clock frequency (X1 clock oscilla tion frequency or external main system clock frequency) 2. f IH: high-speed on-chip oscillator clock frequency 3. Temperature condition of the TYP. value is T A = 25°C.

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 70 of 109 (1) 20-, 24-pin products Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply currentNote 1 IDD2 Note 2 HALT mode HS (High-speed main) mode Note 6 fIH = 24 MHzNote 4 VDD = 5.0 V 440 2230 µA VDD = 3.0 V 440 2230 fIH = 16 MHzNote 4 V DD = 5.0 V 400 1650 µA VDD = 3.0 V 400 1650 fMX = 20 MHzNote 3, VDD = 5.0 V Square wave input 280 1900 µA Resonator connection 450 2000 fMX = 20 MHzNote 3, VDD = 3.0 V Square wave input 280 1900 µA Resonator connection 450 2000 fMX = 10 MHzNote 3, VDD = 5.0 V Square wave input 190 1010 µA Resonator connection 260 1090 fMX = 10 MHzNote 3, VDD = 3.0 V Square wave input 190 1010 µA Resonator connection 260 1090 IDD3 Note 5 STOP mode TA = –40°C 0.19 0.50 µA TA = +25°C 0.24 0.50 TA = +50°C 0.32 0.80 TA = +70°C 0.48 1.20 TA = +85°C 0.74 2.20 TA = +105°C 1.50 10.20 Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. During HALT instruction execution by flash memory. 3. When high-speed on-chip oscillator clock is stopped. 4. When high-speed system clock is stopped. 5. Not including the current flowing into the 12-bit interval timer and watchdog timer. 6. Relationship between operation voltage width, oper ation frequency of CPU and operation mode is as follows. HS (High speed main) mode: V DD = 2.7 V to 5.5 V @1 MHz to 24 MHz V DD = 2.4 V to 5.5 V @1 MHz to 16 MHz Remarks 1. f MX: High-speed system clock frequency (X1 clock oscilla tion frequency or external main system clock frequency) 2. f IH: high-speed on-chip oscillator clock frequency 3. Except temperature conditi on of the TYP. value is TA = 25°C, other than STOP mode

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 71 of 109 (2) 30-pin products Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply currentNote 1 IDD1 Operating mode HS (High-speed main) mode Note 4 fIH = 24 MHzNote 3 Basic operation VDD = 5.0 V 1.5 mA VDD = 3.0 V 1.5 Normal operation VDD = 5.0 V 3.7 5.8 mA VDD = 3.0 V 3.7 5.8 fIH = 16 MHzNote 3 VDD = 5.0 V 2.7 4.2 mA VDD = 3.0 V 2.7 4.2 fMX = 20 MHzNote 2, VDD = 5.0 V Square wave input 3.0 4.9 mA Resonator connection 3.2 5.0 fMX = 20 MHzNote 2, VDD = 3.0 V Square wave input 3.0 4.9 mA Resonator connection 3.2 5.0 fMX = 10 MHzNote 2, VDD = 5.0 V Square wave input 1.9 2.9 mA Resonator connection 1.9 2.9 fMX = 10 MHzNote 2, VDD = 3.0 V Square wave input 1.9 2.9 mA Resonator connection 1.9 2.9 Notes 1. Total current flowing into V DD, including the input leakage current flowin g when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D c onverter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. When high-speed on-chip oscillator clock is stopped. 3. When high-speed system clock is stopped 4. Relationship between operation voltage width, oper ation frequency of CPU and operation mode is as follows. HS (High speed main) mode: V DD = 2.7 V to 5.5 V @1 MHz to 24 MHz V DD = 2.4 V to 5.5 V @1 MHz to 16 MHz Remarks 1. f MX: High-speed system clock frequency (X1 clock oscilla tion frequency or external main system clock frequency) 2. f IH: high-speed on-chip oscillator clock frequency 3. Temperature condition of the TYP. value is T A = 25°C.

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 72 of 109 (2) 30-pin products Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply current Note 1 IDD2 Note 2 HALT mode HS (High-speed main) mode Note 6 fIH = 24 MHzNote 4 VDD = 5.0 V 440 2300 µA VDD = 3.0 V 440 2300 fIH = 16 MHzNote 4 V DD = 5.0 V 400 1700 µA VDD = 3.0 V 400 1700 fMX = 20 MHzNote 3, VDD = 5.0 V Square wave input 280 1900 µA Resonator connection 450 2000 fMX = 20 MHzNote 3, VDD = 3.0 V Square wave input 280 1900 µA Resonator connection 450 2000 fMX = 10 MHzNote 3, VDD = 5.0 V Square wave input 190 1020 µA Resonator connection 260 1100 fMX = 10 MHzNote 3, VDD = 3.0 V Square wave input 190 1020 µA Resonator connection 260 1100 IDD3 Note 5 STOP mode TA = –40°C 0.18 0.50 µA TA = +25°C 0.23 0.50 TA = +50°C 0.30 1.10 TA = +70°C 0.46 1.90 TA = +85°C 0.75 3.30 TA = +105°C 2.94 15.30 Notes 1. Total current flowing into V DD, including the input leakage current flowin g when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D c onverter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. During HALT instruction execution by flash memory. 3. When high-speed on-chip oscillator clock is stopped. 4. When high-speed system clock is stopped. 5. Not including the current flowing into the 12-bit interval timer and watchdog timer. 6. Relationship between operation voltage width, oper ation frequency of CPU and operation mode is as follows. HS (High speed main) mode: V DD = 2.7 V to 5.5 V @1 MHz to 24 MHz V DD = 2.4 V to 5.5 V @1 MHz to 16 MHz Remarks 1. f MX: High-speed system clock frequency (X1 clock oscilla tion frequency or external main system clock frequency) 2. f IH: high-speed on-chip oscillator clock frequency 3. Except STOP mode, temperature c ondition of the TYP. value is TA = 25°C.

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 73 of 109 (3) Peripheral functions (Common to all products) (TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Low-speed onchip oscillator operating current I FIL Note 1 0.20 µA 12-bit interval timer operating current ITMKA Notes 1, 2, 3 0.02 µA Watchdog timer operating current IWDT Notes 1, 2, 4 fIL = 15 kHz 0.22 µA A/D converter operating current IADC Notes 1, 5 When conversion at maximum speed Normal mode, AVREFP = VDD = 5.0 V 1.30 1.70 mA Low voltage mode, AVREFP = VDD = 3.0 V 0.50 0.70 mA A/D converter reference voltage operating current IADREF Note 1 75.0 µA Temperature sensor operating current ITMPS Note 1 75.0 µA LVD operating current I LVD Notes 1, 6 0.08 µA Self-programming operating current IFSP Notes 1, 8 2.00 12.20 mA BGO operating current IBGO Notes 1, 7 2.00 12.20 mA SNOOZE operating current ISNOZ Note 1 ADC operation The mode is performed Note 9 0.50 1.10 mA The A/D conversion operations are performed, Low voltage mode, AVREFP = VDD = 3.0 V 1.20 2.04 mA Simplified SPI (CSI)/UART operation 0.70 1.54 mA Notes 1. Current flowing to the V DD. 2. When high speed on-chip oscillator and high-speed system clock are stopped. 3. Current flowing only to the 12-bit interval timer (e xcluding the operating current of the low-speed on-chip oscillator). The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3, and IFIL and ITMKA when the 12-bit interval timer operates. 4. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer operates. 5. Current flowing only to the A/D conver ter. The current value of the R L78 microcontrollers is the sum of I DD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode. 6. Current flowing only to the LVD circuit. The current value of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ILVD when the LVD circuit operates. 7. Current flowing only during data flash rewrite. 8. Current flowing only during self programming. 9. For shift time to the SNOOZE mode, see 17.3.3 SNOOZE mode in the RL78/G12 User’s Manual. Remarks 1. f IL: Low-speed on-chip oscillator clock frequency 2. Temperature condition of the TYP. value is T A = 25°C

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 74 of 109

3.4 AC Characteristics

(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Items Symbol Conditions MIN. TYP. MAX. Unit Instruction cycle (minimum instruction execution time) TCY Main system clock (fMAIN) operation HS (High- speed main) mode 2.7 V ≤ VDD ≤ 5.5 V 0.04167 1 µs 2.4 V ≤ VDD < 2.7 V 0.0625 1 µs During self programming HS (High- speed main) mode 2.7 V ≤ VDD ≤ 5.5 V 0.04167 1 µs 2.4 V ≤ VDD < 2.7 V 0.0625 1 µs External main system clock frequency fEX 2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz 2.4 V ≤ VDD < 2.7 V 1.0 16.0 MHz External main system clock input high-level width, low- level width t EXH, tEXL 2.7 V ≤ VDD ≤ 5.5 V 24 ns 2.4 V ≤ VDD < 2.7 V 30 ns TI00 to TI07 input high-level width, low-level width tTIH, tTIL 1/fMCK + ns TO00 to TO07 output frequency fTO 4.0 V ≤ VDD ≤ 5.5 V 12 MHz 2.7 V ≤ VDD < 4.0 V 8 MHz 2.4 V ≤ VDD < 2.7 V 4 MHz PCLBUZ0, or PCLBUZ1 output frequency fPCL 4.0 V ≤ VDD ≤ 5.5 V 16 MHz 2.7 V ≤ VDD < 4.0 V 8 MHz 2.4 V ≤ VDD < 2.7 V 4 MHz INTP0 to INTP5 input high- level width, low-level width tINTH, tINTL 1 µs KR0 to KR9 input available width tKR 250 ns RESET low-level width t RSL 10 µs Remark f MCK: Timer array unit operation clock frequency (Operation clock to be set by the ti mer clock select register 0 (TPS0) and the CKS0n bit of timer mode register 0n (TMR0n). n: Channel number (n = 0 to 7))

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 75 of 109 Minimum Instruction Execution Time during Main System Clock Operation TCY vs VDD (HS (high-speed main) mode) When the high-speed on-chip oscillator clock is selected During self programming When high-speed system clock is selected Cycle time TCY [µs] Supply voltage VDD [V] 1.0 0.1 5.52.7 0.01 2.4 0.04167 0.0625 AC Timing Test Point VIH/VOH VIL/VOL Test points VIH/VOH VIL/VOL External Main System Clock Timing EXCLK 1/fEX tEXL tEXH

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 76 of 109 TI/TO Timing TI00 to TI07 tTIL tTIH TO00 to TO07 1/fTO Interrupt Request Input Timing INTP0 to INTP5 tINTL tINTH Key Interrupt Input Timing KR0 to KR9 tKR RESET Input Timing RESET tRSL

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 77 of 109

3.5 Peripheral Functions Characteristics

3.5.1 Serial array unit

(1) During communication at sam e potential (UART mode) (TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. Transfer rate Note 1 f MCK/12 bps Theoretical value of the maximum transfer rate fCLK = fMCKNote 2

2.0 Mbps

Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only. 2. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main ) mode: 24 MHz (2.7 V ≤ VDD ≤ 5.5 V) 16 MHz (2.4 V ≤ VDD ≤ 5.5 V) Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). UART mode connection diagram (during communication at same potential) RL78 microcontroller TxDq RxDq Rx Tx User's device UART mode bit width (during communication at same potential) (reference) TxDq RxDq Baud rate error tolerance High-/Low-bit width 1/Transfer rate Remarks 1. q: UART number (q = 0 to 2), g: PIM, POM number (g = 0, 1) 2. f MCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock se lect register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10, 11))

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 78 of 109 (2) During communication at same potential (simplified SPI (CSI) mode) (master m ode, SCKp... internal clock output) (TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCKp cycle time t KCY1 t KCY1 ≥ 4/fCLK 2.7 V ≤ VDD ≤ 5.5 V 334 ns 2.4 V ≤ VDD ≤ 5.5 V 500 ns SCKp high-/low-level width t KH1, tKL1 4.0 V ≤ VDD ≤ 5.5 V t KCY1/2–24 ns 2.7 V ≤ VDD ≤ 5.5 V t KCY1/2–36 ns 2.4 V ≤ VDD ≤ 5.5 V t KCY1/2–76 ns SIp setup time (to SCKp↑) Note 1 t SIK1 4.0 V ≤ VDD ≤ 5.5 V 66 ns 2.7 V ≤ VDD ≤ 5.5 V 66 ns 2.4 V ≤ VDD ≤ 5.5 V 113 ns SIp hold time (from SCKp↑) Note 2 t KSI1 38 ns Delay time from SCKp↓ to SOp output Note 3 tKSO1 C = 30 pF Note 4 50 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp and SCKp pins by using port input mode register 1 (PIM1) and port output mode registers 0, 1, 4 (POM0, POM1, POM4). Remarks 1. p: CSI number (p = 00, 01, 11, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3) 2. f MCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock sele ct register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3))

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 79 of 109 (3) During communication at same potential (simplified SPI (CSI) mode) (slave mode, SCKp... external clock input) (TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCKp cycle time Note 5 t KCY2 4.0 V ≤ VDD ≤ 5.5 V 20 MHz < f MCK 16/f MCK ns fMCK ≤ 20 MHz 12/f MCK ns 2.7 V ≤ VDD ≤ 5.5 V 16 MHz < f MCK 16/f MCK ns fMCK ≤ 16 MHz 12/f MCK ns 2.4 V ≤ VDD ≤ 5.5 V 12/f MCK and 1000 ns SCKp high-/low-level width t KH2, tKL2 4.0 V ≤ VDD ≤ 5.5 V t KCY2/2–14 ns 2.7 V ≤ VDD ≤ 5.5 V t KCY2/2–16 ns 2.4 V ≤ VDD ≤ 5.5 V t KCY2/2–36 ns SIp setup time (to SCKp↑) Note 1 tSIK2 2.7 V ≤ VDD ≤ 5.5 V 1/f MCK + 40 ns 2.4 V ≤ VDD ≤ 5.5 V 1/f MCK + 60 ns SIp hold time (from SCKp↑) Note 2 tKSI2 1/f MCK + 62 ns Delay time from SCKp↓ to SOp output Note 3 tKSO2 C = 30 pF Note 4 2.7 V ≤ VDD ≤ 5.5 V 2/f MCK + 66 ns 2.4 V ≤ VDD ≤ 5.5 V 2/f MCK + 113 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitanc e of the SOp output lines. 5. Transfer rate in the SNOOZE mode: MAX. 1 Mbps. Caution Select the normal input buffer for the SIp and SCKp pins and the normal output mode for the SOp pin by using port input mode register 1 (PIM1) and port output mode registers 0, 1, 4 (POM0, POM1, POM4). Simplified SPI (CSI) mode connection diagram (during communication at same potential) RL78 microcontroller SCKp SOp SCK SI User's deviceSIp SO

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 80 of 109 Simplified SPI (CSI) mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) SIp SOp tKCY1, 2 tKL1, 2 tKH1, 2 tSIK1, 2 tKSI1, 2 tKSO1, 2 SCKp Input data Output data Simplified SPI (CSI) mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) SIp SOp tKCY1, 2 tKH1, 2 tKL1, 2 tSIK1, 2 tKSI1, 2 tKSO1, 2 SCKp Input data Output data Remarks 1. p: CSI number (p = 00, 01, 11, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3) 2. f MCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock se lect register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0,1), n: Channel number (n = 0, 1, 3))

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 81 of 109 (4) During communication at same potential (simplified I 2C mode) (TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCLr clock frequency f SCL C b = 100 pF, Rb = 3 kΩ 100 Note 1 kHz Hold time when SCLr = “L” t LOW C b = 100 pF, Rb = 3 kΩ 4600 ns Hold time when SCLr = “H” t HIGH C b = 100 pF, Rb = 3 kΩ 4600 ns Data setup time (reception) t SU:DAT C b = 100 pF, Rb = 3 kΩ 1/f MCK + 580 Note 2 ns Data hold time (transmission) t HD:DAT C b = 100 pF, Rb = 3 kΩ 0 1420 ns Notes 1. The value must be equal to or less than f MCK/4. 2. Set t SU:DAT so that it will not exceed the hold time when SCLr = “L” or SCLr = “H”. Caution Select the N-ch open drain output (V DD tolerance) mode for SDAr by using port output mode register h (POMh). Simplified I2C mode connection diagram (during communication at same potential) RL78 microcontroller SDAr SCLr SDA SCL User's device VDD Rb Simplified I2C mode serial transfer timing (during communication at same potential) SDAr tLOW tHIGH tHD:DAT SCLr tSU:DAT 1/fSCL Remarks 1. R b [Ω]:Communication line (SDAr) pull-up resistance C b [F]: Communication line (SCLr, SDAr) load capacitance 2. r: IIC number (r = 00, 01, 11, 20), h: = POM number (h = 0, 1, 4, 5) 3. f MCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (0, 1, 3))

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 82 of 109 (5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. Transfer rate Note4 Reception 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V f MCK/12 Note 1 bps Theoretical value of the maximum transfer rate f MCK = fCLKNote 2 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V f MCK/12 Note 1 bps Theoretical value of the maximum transfer rate fMCK = fCLKNote 2 2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V f MCK/12 Note 1 bps Theoretical value of the maximum transfer rate fMCK = fCLKNote 2 Transmission 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V Note 3 bps Theoretical value of the maximum transfer rate C b = 50 pF, Rb = 1.4 kΩ, Vb = 2.7 V 2.0 Note 4 Mbps 2.7 V ≤ VDD < 4.0 V, Note 5 bps Theoretical value of the maximum transfer rate C b = 50 pF, Rb = 2.7 kΩ, Vb = 2.3 V 1.2 Note 6 Mbps 2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Notes 2, 7 bps Theoretical value of the maximum transfer rate C b = 50 pF, Rb = 5.5 kΩ, Vb = 1.6 V 0.43 Note 8 Mbps Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only. 2. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main ) mode: 24 MHz (2.7 V ≤ VDD ≤ 5.5 V) 16 MHz (2.4 V ≤ VDD ≤ 5.5 V) 3. The smaller maximum transfer rate derived by using f MCK/12 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V ≤ VDD ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V Maximum transfer rate = [bps] Vb )} × 3

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 83 of 109 Transfer rate × 2 – {–Cb × Rb × ln (1 – 2.2 Vb )} Baud rate error (theoretical value) = × 100 [%] ( 1 Transfer rate ) × Number of transferred bits * This value is the theoretical value of the relative difference between the transmission and reception sides. 4. This value as an example is calcul ated when the conditions described in the “Conditions” column are met. Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer. 5. The smaller maximum transfer rate derived by using f MCK/12 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V ≤ VDD < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V Maximum transfer rate = [bps] Vb )} × 3 Transfer rate × 2 – {–Cb × Rb × ln (1 – 2.0 Vb )} Baud rate error (theoretical value) = × 100 [%] ( 1 Transfer rate ) × Number of transferred bits * This value is the theoretical value of the relative difference between the transmission and reception sides. 6. This value as an example is calcul ated when the conditions described in the “Conditions” column are met. Refer to Note 5 above to calculate the maximum transfer rate under conditions of the customer. 7. The smaller maximum transfer rate derived by using f MCK/12 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Maximum transfer rate = [bps] Vb )} × 3 Transfer rate × 2 – {–Cb × Rb × ln (1 – 1.5 Vb )} Baud rate error (theoretical value) = × 100 [%] ( 1 Transfer rate ) × Number of transferred bits * This value is the theoretical value of the relative difference between the transmission and reception sides. 8. This value as an example is calculated when the condi tions described in the “Conditions” column are met. Refer to Note 7 above to calculate the maximum transfer rate under conditions of the customer. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (V DD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 84 of 109 UART mode connection diagram (during communication at different potential) RL78 microcontroller TxDq RxDq Rx Tx User's device Vb Rb UART mode bit width (during communication at different potential) (reference) TxDq RxDq Baud rate error tolerance High-/Low-bit width 1/Transfer rate Baud rate error tolerance High-bit width Low-bit width 1/Transfer rate Remarks 1. R b[Ω]: Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage 2. q: UART number (q = 0 to 2), g: PIM and POM number (g = 0, 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock sele ct register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10, 11)) 4. UART0 of the 20- and 24-pin products supports communication at different potential only when the peripheral I/O redirection function is not used.

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 85 of 109 internal clock output) (1/3) (TA = –40 to +105°C, 2.4 V ≤ VDD ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCKp cycle time t KCY1 t KCY1 ≥ 4/fCLK 4.0 V ≤ VDD ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 600 ns 2.7 V ≤ VDD < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 1000 ns 2.4 V ≤ VDD < 3.3 V, Cb = 30 pF, Rb = 5.5 kΩ 2300 ns SCKp high-level width t KH1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ tKCY1/2 –150 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ tKCY1/2 –340 ns 2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ tKCY1/2 –916 ns SCKp low-level width t KL1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ tKCY1/2 –24 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ tKCY1/2 –36 ns 2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ tKCY1/2 –100 ns Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (V DD tolerance) mode for the SOp pin and SCKp pin by using port input mode register 1 (PIM1) and port output mode register 1 (POM1). For V IH and VIL, see the DC characteristics with TTL input buffer selected. 2. CSI01 and CSI11 cannot communicate at different potential. Remarks 1. R b [Ω]: Communication line (SCKp, SOp) pull-up resistance, C b [F]: Communication line (SCKp, SOp) load capacitance, Vb [V]: Communication line voltage 2. p: CSI number (p = 00, 20)

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 86 of 109 internal clock output) (2/3) (TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SIp setup time (to SCKp↑) Note tSIK1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 162 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 354 ns 2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ 958 ns SIp hold time (from SCKp↑) Note tKSI1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 38 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 38 ns 2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ 38 ns Delay time from SCKp↓ to SOp output Note tKSO1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 200 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 390 ns 2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ 966 ns Note When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. (Cautions and Remarks are listed on the next page.)

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 87 of 109 internal clock output) (3/3) (TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SIp setup time (to SCKp↓) Note tSIK1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 88 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 88 ns 2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ 220 ns SIp hold time (from SCKp↓) Note tKSI1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 38 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 38 ns 2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ 38 ns Delay time from SCKp↑ to SOp output Note tKSO1 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 50 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 50 ns 2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ 50 ns Note When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (V DD tolerance) mode for the SOp pin and SCKp pin by using port input mode register 1 (PIM1) and port output mode register 1 (POM1). For VIH and VIL, see the DC characteristics with TTL input buffer selected. 2. CSI01 and CSI11 cannot communicate at different potential. Remarks 1. R b [Ω]: Communication line (SCKp, SOp) pull-up resistance, C b [F]: Communication line (SCKp, SOp) load capacitance, Vb [V]: Communication line voltage 2. p: CSI number (p = 00, 20), m: Unit numbe r (m = 0, 1), n: Channel number (n = 0) Simplified SPI (CSI) mode connection diagram (during communication at different potential) Vb Rb SCKp SOp SCK SI User's deviceSIp SO Vb Rb <Master> RL78 microcontroller

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 88 of 109 Simplified SPI (CSI) mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1) tKCY1 tKL1 tKH1 tSIK1 tKSI1 tKSO1 SIp SOp SCKp Input data Output data Simplified SPI (CSI) mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1 tKL1tKH1 tSIK1 tKSI1 tKSO1 SIp SOp SCKp Input data Output data Remark p: CSI number (p = 00, 20), m: Unit numbe r (m = 0, 1), n: Channel number (n = 0)

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 89 of 109 clock input) (TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditi ons HS (high-speed main) Mode Unit MIN. MAX. SCKp cycle time Note 1 t KCY2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V

20 MHz < fMCK ≤ 24 MHz 24/f MCK ns

8 MHz < fMCK ≤ 20 MHz 20/f MCK ns

4 MHz < fMCK ≤ 8 MHz 16/f MCK ns

fMCK ≤ 4 MHz 12/f MCK ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V

20 MHz < fMCK ≤ 24 MHz 32/f MCK ns

16 MHz < fMCK ≤ 20 MHz 28/f MCK ns

8 MHz < fMCK ≤ 16 MHz 24/f MCK ns

fMCK ≤ 4 MHz 12/fMCK ns 2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V

20 MHz < fMCK ≤ 24 MHz 72/f MCK ns

16 MHz < fMCK ≤ 20 MHz 64/f MCK ns

8 MHz < fMCK ≤ 16 MHz 52/f MCK ns

4 MHz < fMCK ≤ 8 MHz 32/fMCK ns

fMCK ≤ 4 MHz 20/fMCK ns SCKp high-/low-level width tKH2, tKL2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V tKCY2/2 – 24 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V tKCY2/2 – 36 ns 2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V tKCY2/2 – 100 ns SIp setup time (to SCKp↑) Note 2 tSIK2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ VDD ≤ 4.0 V 1/fMCK + 40 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V 1/fMCK + 40 ns 2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ VDD ≤ 2.0 V 1/fMCK + 60 ns SIp hold time (from SCKp↑) Note 3 tKSI2 1/fMCK + 62 ns Delay time from SCKp↓ to SOp output Note 4 tKSO2 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 2/f MCK + 240 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 2/f MCK + 428 ns 2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ 2/fMCK + 1146 ns Notes 1. Transfer rate in the SNOOZE mode: MAX. 1 Mbps 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Cautions 1. Select the TTL input buffer for the SIp and SCKp pins and the N-ch open drain output (V DD tolerance) mode for the SOp pin by using port input mode register 1 (PIM1) and port output mode register 1 (POM1). For V IH and V IL, see the DC characteristics with TTL input buffer selected. 2. CSI01 and CSI11 cannot communicate at different potential.

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 90 of 109 Simplified SPI (CSI) mode connection diagram (during communication at different potential) RL78 microcontroller SOp SCK SI User's deviceSIp SO Vb Rb SCKp <Slave> Simplified SPI (CSI) mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY2 tKL2 tKH2 tSIK2 tKSI2 tKSO2 SIp SOp SCKp Input data Output data Remarks 1. R b [Ω]: Communication line (SOp) pull-up resistance, Cb [F]: Communication line (SOp) load capacitance, V b [V]: Communication line voltage 2. p: CSI number (p = 00, 20), m: Unit numbe r (m = 0, 1), n: Channel number (n = 0) 3. f MCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn))

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 91 of 109 Simplified SPI (CSI) mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY2 tKL2tKH2 tSIK2 tKSI2 tKSO2 SIp SOp SCKp Input data Output data Remark p: CSI number (p = 00, 20), m: Unit numbe r (m = 0, 1), n: Channel number (n = 0)

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 92 of 109 (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCLr clock frequency f SCL 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 kΩ

100 Note1 kHz

2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 100 pF, Rb = 5.5 kΩ Hold time when SCLr = “L” t LOW 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 kΩ 4600 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 4600 ns 2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 100 pF, Rb = 5.5 kΩ 4650 ns Hold time when SCLr = “H” t HIGH 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 kΩ 2700 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 2400 ns 2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 100 pF, Rb = 5.5 kΩ 1830 ns Data setup time (reception) t SU:DAT 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 kΩ 1/fMCK + 760 Note2 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 1/fMCK + 760 Note2 ns 2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 100 pF, Rb = 5.5 kΩ 1/fMCK + 570 Note2 ns Data hold time (transmission) t HD:DAT 4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 kΩ 0 1420 ns 2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 0 1420 ns 2.4 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 100 pF, Rb = 5.5 kΩ 0 1215 ns Notes 1. The value must be equal to or less than fMCK/4. 2. Set tSU:DAT so that it will not exceed the hold time when SCLr = “L” or SCLr = “H”. Cautions 1. Select the TTL input buffer and the N-ch open drain output (V DD tolerance) mode for the SDAr pin and the N-ch open drain output (V DD tolerance) mode for the SCLr pin by using port input mode register 1 (PIM1) and port output mode register 1 (POM1). For V IH and V IL, see the DC characteristics with TTL input buffer selected. 2. IIC01 and IIC11 cannot communicate at different potential. (Remarks are listed on the next page.)

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 93 of 109 Simplified I2C mode connection diagram (during communication at different potential) SDAr SCLr SDA SCL User's device Vb Rb Vb Rb RL78 microcontroller Simplified I2C mode serial transfer timing (during communication at different potential) SDAr tLOW tHIGH tHD : DAT SCLr tSU : DAT 1/fSCL Remarks 1. R b [Ω]: Communication line (SDAr, SCLr) pull-up resistance, C b [F]: Communication line (SDAr, SCLr) load capacitance, Vb [V]: Communication line voltage 2. r: IIC Number (r = 00, 20) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register m (SPSm) and the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0,1), n: Channel number (n = 0))

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 94 of 109

3.5.2 Serial interface IICA

(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) mode Unit Standard Mode Fast Mode MIN. MAX. MIN. MAX. SCLA0 clock frequency f SCL Fast mode: f CLK ≥ 3.5 MHz 0 400 kHz Normal mode: fCLK ≥ 1 MHz 0 100 kHz Setup time of restart condition t SU:STA 4.7 0.6 µs Hold timeNote 1 t HD:STA 4.0 0.6 µs Hold time when SCLA0 = “L” t LOW 4.7 1.3 µs Hold time when SCLA0 = “H” t HIGH 4.0 0.6 µs Data setup time (reception) t SU:DAT 250 100 ns Data hold time (transmission)Note 2 t HD:DAT 0 3.45 0 0.9 µs Setup time of stop condition t SU:STO 4.0 0.6 µs Bus-free time t BUF 4.7 1.3 µs Notes 1. The first clock pulse is generated after this per iod when the start/restart condition is detected. 2. The maximum value (MAX.) of t HD:DAT is during normal transfer and a cloc k stretch state is inserted in the ACK (acknowledge) timing. Caution Only in the 30-pin products, the values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection register (PIOR) is 1. At this time, the pin characteristics (I OH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of C b (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Normal mode: C b = 400 pF, Rb = 2.7 kΩ Fast mode: C b = 320 pF, Rb = 1.1 kΩ IICA serial transfer timing tLOW tR tHIGH tF tBUF tHD:DAT tSU:DATtHD:STA tSU:STA tHD:STA tSU:STO SCLA0 SDAA0 Stop condition Start condition Restart condition Stop condition

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 95 of 109

3.6 Analog Characteristics

3.6.1 A/D converter characteristics

Classification of A/D converter characteristics Input channel Reference Voltage Reference voltage (+) = AVREFP Reference voltage (–) = AVREFM Reference voltage (+) = VDD Reference voltage (–) = VSS Reference voltage (+) = VBGR Reference voltage (–) = AVREFM ANI16 to ANI22 Refer to 3.6.1 (2). Internal reference voltage Temperature sensor output voltage Refer to 3.6.1 (1). – (1) When reference voltage (+) = AV REFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (–) = AV REFM/ANI1 (ADREFM = 1), target pin: ANI2, ANI3, internal reference voltage, and temperature sensor output voltage A = –40 to +105°C, 2.4 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (–) = AVREFM = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 8 10 bit Overall errorNote 1 AINL 10-bit resolution AVREFP = VDD Note 3 1.2 ±3.5 LSB Conversion time t CONV 10-bit resolution Target pin: ANI2, ANI3 3.6 V ≤ VDD ≤ 5.5 V 2.125 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 µs 2.4 V ≤ VDD ≤ 5.5 V 17 39 µs 10-bit resolution Target pin: Internal reference voltage, and temperature sensor output voltage (HS (high-speed main) mode) DD ≤ 5.5 V 2.375 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.5625 39 µs 2.4 V ≤ VDD ≤ 5.5 V 17 39 µs Zero-scale errorNotes 1, 2 EZS 10-bit resolution AVREFP = VDD Note 3 ±0.25 %FSR Full-scale errorNotes 1, 2 EFS 10-bit resolution AVREFP = VDD Note 3 ±0.25 %FSR Integral linearity errorNote 1 ILE 10-bit resolution AVREFP = VDD Note 3 ±2.5 LSB Differential linearity error Note 1 DLE 10-bit resolution AVREFP = VDD Note 3 ±1.5 LSB Analog input voltage V AIN ANI2, ANI3 0 AV REFP V Internal reference voltage (HS (high-speed main) mode) VBGR Note 4 V Temperature sensor output voltage (HS (high-speed main) mode) VTMPS25 Note 4 V (Notes are listed on the next page.)

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 96 of 109 Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When AV REFP < VDD, the MAX. values are as follows. Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD. 4. Refer to 3.6.2 Temperature sensor/internal reference voltage characteristics. (2) When reference voltage (+) = AV REFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (–) = AV REFM/ANI1 (ADREFM = 1), target pin: ANI16 to ANI22 A = –40 to +105°C, 2.4 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (–) = AVREFM = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution R ES 8 10 bit Overall error Note 1 AINL 10-bit resolution AVREFP = VDD Note 3 1.2 ±5.0 LSB Conversion time t CONV 10-bit resolution Target ANI pin: ANI16 to ANI22 3.6 V ≤ VDD ≤ 5.5 V 2.125 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 µs 2.4 V ≤ VDD ≤ 5.5 V 17 39 µs Zero-scale error Notes 1, 2 EZS 10-bit resolution AVREFP = VDD Note 3 ±0.35 %FSR Full-scale error Notes 1, 2 EFS 10-bit resolution AVREFP = VDD Note 3 ±0.35 %FSR Integral linearity error Note 1 ILE 10-bit resolution AVREFP = VDD Note 3 ±3.5 LSB Differential linearity error Note 1 DLE 10-bit resolution AVREFP = VDD Note 3 ±2.0 LSB Analog input voltage V AIN ANI16 to ANI22 0 AV REFP and VDD V Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When AV REFP ≤ VDD, the MAX. values are as follows. Overall error: Add ±4.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add ±0.20%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add ±2.0 LSB to the MAX. value when AVREFP = VDD.

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 97 of 109 (3) When reference voltage (+) = V DD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (–) = V SS (ADREFM = 0), target pin: ANI0 to ANI3, ANI16 to ANI22, internal reference voltage, and temperature sensor output voltage (TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = VDD, Reference voltage (–) = VSS) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution R ES 8 10 bit Overall errorNote 1 AINL 10-bit resolution 1.2 ±7.0 LSB Conversion time t CONV 10-bit resolution Target pin: ANI0 to ANI3, ANI16 to ANI22 DD ≤ 5.5 V 2.125 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 µs 2.4 V ≤ VDD ≤ 5.5 V 17 39 µs Conversion time t CONV 10-bit resolution Target pin: internal reference voltage, and temperature sensor output voltage (HS (high-speed main) mode) DD ≤ 5.5 V 2.375 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.5625 39 µs 2.4 V ≤ VDD ≤ 5.5 V 17 39 µs Zero-scale errorNotes 1, 2 EZS 10-bit resolution ±0.60 %FSR Full-scale errorNotes 1, 2 EFS 10-bit resolution ±0.60 %FSR Integral linearity errorNote 1 ILE 10-bit resolution ±4.0 LSB Differential linearity error Note 1 DLE 10-bit resolution ±2.0 LSB Analog input voltage V AIN ANI0 to ANI3, ANI16 to ANI22 0 V DD V Internal reference voltage (HS (high-speed main) mode) VBGR Note 3 V Temperature sensor output voltage (HS (high-speed main) mode) VTMPS25 Note 3 V Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. Refer to 3.6.2 Temperature sensor/internal reference voltage characteristics.

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 98 of 109 (4) When reference voltage (+) = Inte rnal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (–) = AVREFM (ADREFM = 1), target pin: ANI0, ANI2, ANI3, and ANI16 to ANI22 A = –40 to +105°C, 2.4 V ≤ V DD ≤ 5.5 V, V SS = 0 V, Reference voltage (+) = V BGR Note 3, Reference voltage (–) = AVREFM Note 4 = 0 V, HS (high-speed main) mode) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution R ES 8 bit Conversion time t CONV 8-bit resolution 17 39 µs Zero-scale errorNotes 1, 2 EZS 8-bit resolution ±0.60 %FSR Integral linearity errorNote 1 ILE 8-bit resolution ±2.0 LSB Differential linearity error Note 1 DLE 8-bit resolution ±1.0 LSB Analog input voltage V AIN 0 V BGR Note 3 V Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. Refer to 3.6.2 Temperature sensor/internal reference voltage characteristics. 4. When reference voltage (–) = V SS, the MAX. values are as follows. Zero-scale error: Add ±0.35%FSR to the MAX. value when reference voltage (–) = AVREFM. Integral linearity error: Add ±0.5 LSB to the MAX. value when reference voltage (–) = AVREFM. Differential linearity error: Add ±0.2 LSB to the MAX. value when reference voltage (–) = AVREFM.

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 99 of 109

3.6.2 Temperature sensor/internal reference voltage characteristics

(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, HS (high-speed main) mode Parameter Symbol Conditions MIN. TYP. MAX. Unit Temperature sensor output voltage V TMPS25 Setting ADS register = 80H, TA = +25°C 1.05 V Internal reference voltage V BGR Setting ADS register = 81H 1.38 1.45 1.50 V Temperature coefficient F VTMPS Temperature sensor output voltage that depends on the temperature –3.6 mV/°C Operation stabilization wait time t AMP 5 µs

3.6.3 POR circuit characteristics

(TA = –40 to +105°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage V POR The power supply voltage is rising. 1.45 1.51 1.57 V VPDR The power supply voltage is falling. 1.44 1.50 1.56 V Minimum pulse width Note T PW 300 µs Note Minimum time required for a POR reset when V DD exceeds below VPDR. This is also the minimum time required for a POR reset from when V DD exceeds below 0.7 V to when V DD exceeds VPOR while STOP mode is entered or the main system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register (CSC). TPW VPOR VPDR or 0.7 V Supply voltage (VDD)

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 100 of 109

3.6.4 LVD circuit characteristics

LVD Detection Voltage of Reset Mode and Interrupt Mode (TA = –40 to +105°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection supply voltage V LVD0 The power supply voltage is rising. 3.90 4.06 4.22 V The power supply voltage is falling. 3.83 3.98 4.13 V VLVD1 The power supply voltage is rising. 3.60 3.75 3.90 V The power supply voltage is falling. 3.53 3.67 3.81 V VLVD2 The power supply voltage is rising. 3.01 3.13 3.25 V The power supply voltage is falling. 2.94 3.06 3.18 V VLVD3 The power supply voltage is rising. 2.90 3.02 3.14 V The power supply voltage is falling. 2.85 2.96 3.07 V VLVD4 The power supply voltage is rising. 2.81 2.92 3.03 V The power supply voltage is falling. 2.75 2.86 2.97 V VLVD5 The power supply voltage is rising. 2.70 2.81 2.92 V The power supply voltage is falling. 2.64 2.75 2.86 V VLVD6 The power supply voltage is rising. 2.61 2.71 2.81 V The power supply voltage is falling. 2.55 2.65 2.75 V VLVD7 The power supply voltage is rising. 2.51 2.61 2.71 V The power supply voltage is falling. 2.45 2.55 2.65 V Minimum pulse width t LW 300 µs Detection delay time 300 µs

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 101 of 109 LVD detection voltage of interrupt & reset mode (TA = –40 to +105°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Interrupt and reset mode VLVDD0 V POC2, VPOC1, VPOC1 = 0, 1, 1, falling reset voltage 2.64 2.75 2.86 V VLVDD1 LVIS1, LVIS0 = 1, 0 Rising reset release voltage 2.81 2.92 3.03 V Falling interrupt voltage 2.75 2.86 2.97 V VLVDD2 LVIS1, LVIS0 = 0, 1 Rising reset release voltage 2.90 3.02 3.14 V Falling interrupt voltage 2.85 2.96 3.07 V VLVDD3 LVIS1, LVIS0 = 0, 0 Rising reset release voltage 3.90 4.06 4.22 V Falling interrupt voltage 3.83 3.98 4.13 V

3.6.5 Power supply voltage rising slope characteristics

(TA = –40 to +105°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Power supply voltage rising slope S VDD 54 V/ms Caution Make sure to keep the internal reset state by the LVD circuit or an external reset until V DD reaches the operating voltage range shown in 3.4 AC Characteristics.

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 102 of 109

3.7 RAM Data Retention Characteristics

(TA = –40 to +105°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention supply voltage V DDDR 1.44 Note 5.5 V Note This depends on the POR detection voltage. For a falling voltage, data in RAM are re tained until the voltage reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is generated. VDD STOP instruction execution Standby release signal (interrupt request) STOP mode RAM data retention VDDDR Operation mode

3.8 Flash Memory Programming Characteristics

(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit System clock frequency f CLK 1 24 MHz Code flash memory rewritable times Notes 1, 2, 3 Cerwr Retained for 20 years TA = 85°C Note 4 1,000 Times Data flash memory rewritable times Notes 1, 2, 3 Retained for 1 year TA = 25°C 1,000,000 Retained for 5 years TA = 85°C Note 4 100,000 Retained for 20 years TA = 85°C Note 4 10,000 Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewr ite. The retaining years are until next rewrite after the rewrite. 2. When using flash memory programmer and Renesas Electronics self programming library 3. These are the characteristics of t he flash memory and the results obtai ned from reliability testing by Renesas Electronics Corporation. 4. This temperature is the average value at which data are retained.

RL78/G12 3. ELECTRICAL SPECIFICATION S (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 103 of 109

3.9 Dedicated Flash Memory Programmer Communication (UART)

(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate During serial programming 115,200 1,000,000 bps

3.10 Timing of Entry to Flash Memory Programming Modes

(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Time to complete the communication for the initial setting after the external reset is released tSUINIT POR and LVD reset are released before external release 100 ms Time to release the external reset after the TOOL0 pin is set to the low level tSU POR and LVD reset are released before external release 10 µs Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing time of the firmware to control the flash memory) tHD POR and LVD reset are released before external release 1 ms RESET TOOL0 tSUINIT tHD + software processing time 1-byte data for setting mode tSU <4> <1> The low level is input to the TOOL0 pin. <2> The external reset is released (POR and LVD reset must be released before the external reset is released.). <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. Remark t SUINIT: Communication for the initial setting must be complet ed within 100 ms after the external reset is released during this period. tSU: Time to release the exte rnal reset after the TOOL0 pin is set to the low level tHD: Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing time of the firmware to control the flash memory)

RL78/G12 4. PACKAGE DRAWINGS R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 104 of 109 4. PACKAGE DRAWINGS 4.1 20-pin package 2012 Renesas Electronics Corporation. All rights reserved. P-LSSOP20-4.4x6.5-0.65 PLSP0020JB-A P20MA-65-NAA-1 0.1 1 10 detail of lead end ITEM DIMENSIONS D E e A L c y bp 0.10 0.10 0 to 10 (UNIT:mm) A A1 ey HE c 6.50 4.40 0.20 0.10 6.40 0.100.10 1.45 MAX. 1.15 0.65 0.12 0.10 0.050.22 0.05 0.020.15 0.50 0.20 bp HE E D L NOTE 1.Dimensions “ 1” and “ 2” 2.Dimension “ ” does not include tr

RL78/G12 4. PACKAGE DRAWINGS R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 105 of 109

RL78/G12 4. PACKAGE DRAWINGS R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 106 of 109 4.2 24-pin package 2012 Renesas Electronics Corporation. All rights reserved. Sy eLp SxbA B M A D E A S B A D E A e Lp x y 4.00 0.05 0.50 0.05 0.05 4.00 0.05 0.75 0.05 0.40 0.10 S (UNIT:mm) ITEM DIMENSIONS DETAIL OF A PART EXPOSED DIE PAD ITEM D2 E2 A MIN NOM MAX 2.45 2.50 EXPOSED DIE PAD VARIATIONS 2.55 MIN NOM MAX 2.45 2.50 2.55 b 0.25 0.05 0.07 P-HWQFN24-4x4-0.50 PWQN0024KE-A P24K8-50-CAB-1 0.04

RL78/G12 4. PACKAGE DRAWINGS R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 107 of 109 D SEATING PLANE ccc C 24X bbb C A B ddd C b(24X) 1318 L(24X) K(24X) C aaa C B aaa C (A3) A1A eee C fff C A B fff C A B AE e 18 13 1 6 EXPOSED DIE PAD INDEX AREA (D/2 X E/2) Reference Symbol Dimension in Millimeters Min. Nom. Max. A0 . 8 0 A1 0.00 0.02 0.05 A3 0.203 REF. b 0.18 0.25 0.30 D4 . 0 0 B S C E4 . 0 0 B S C e0 . 5 0 B S C L 0.35 0.40 0.45 K 0.20 D2 2.55 2.60 2.65 E2 2.55 2.60 2.65 aaa 0.15 bbb 0.10 ccc 0.10 ddd 0.05 eee 0.08 fff 0.10 P-HWQFN024-4x4-0.50 PWQN0024KF-A 0.04

RL78/G12 4. PACKAGE DRAWINGS R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 108 of 109 INDEX AREA (D/2 X E/2) SEATING PLANE EXPOSED DIE PAD P-HWQFN24-4×4-0.50 PWQN0024KH-A 0.04 Reference Symbol Dimension in Millimeters Min. Nom. Max. A －－ 0.80 A1 0.00 － 0.05 A3 0.20 REF. b 0.20 0.25 0.30 D － 4.00 － E － 4.00 － e － 0.50 － N2 4 L 0.30 0.40 0.50 K0 . 2 0 －－ D2 2.50 2.60 2.70 E2 2.50 2.60 2.70 aaa －－ 0.15 bbb －－ 0.10 ccc －－ 0.10 ddd －－ 0.05 eee －－ 0.08

RL78/G12 4. PACKAGE DRAWINGS R01DS0193EJ0250 Rev.2.50 Jan 17, 2025 Page 109 of 109 4.3 30-pin package P-LSSOP30-0300-0.65 PLSP0030JB-B S30MC-65-5A4-3 0.18 S S H J T I G D E F C B K P L U N ITEM B C I L M N A K D E F G H J P 30 16 11 5 A detail of lead end MM T MILLIMETERS 0.65 (T.P .) 0.45 MAX. 0.13 0.5 6.1 0.2 0.10 9.85 0.15 0.17 0.03 0.1 0.05 0.24 1.3 0.1 8.1 0.2 1.2 0.08 0.07 1.0 0.2 3 5 0.25 0.6 0.15U NOTE Each lead centerline is located within 0.13 mm of its true position (T.P .) at maximum material condition. 2012 Renesas Electronics Corporation. All rights reserved.

Rev. Date

Description

1.00 Dec 10, 2012 - First Edition issued

2.00 Sep 06, 2013 1 Modi fication of 1.1 Features 3 Modification of 1.2 List of Part Numbers 4 Modification of Table 1-1. List of Ordering Part Numbers, Note, and Caution 7 to 9 Modification of package name in 1.4.1 to 1.4.3 14 Modification of tables in 1.7 Outline of Functions 17 Modification of description of table in 2.1 Absolute Maximum Ratings (T A = 25°C) 18 Modification of table, Note, and Cauti on in 2.2.1 X1 oscillator characteristics 18 Modification of table in 2.2.2 On-chip oscillator characteristics 19 Modification of Note 3 in 2.3.1 Pin characteristics (1/4) 20 Modification of Note 3 in 2.3.1 Pin characteristics (2/4)

23 Modification of Notes 1 and 2 in (1) 20-, 24-pin products (1/2)

24 Modification of Notes 1 and 3 in (1) 20-, 24-pin products (2/2)

25 Modification of Notes 1 and 2 in (2) 30-pin products (1/2)

26 Modification of Notes 1 and 3 in (2) 30-pin products (2/2)

27 Modification of (3) Peripheral functions (Common to all products)

28 Modification of table in 2.4 AC Characteristics

29 Addition of Minimum Instruction Execution Time during Main System Clock

30 Modification of figures of AC Timing Test Point and External Main System

31 Modification of figure of AC Timing Test Point

31 Modification of description and Note 2 in (1) During communication at same

potential (UART mode)

32 Modification of description in (2) During communication at same potential (CSI

mode)

33 Modification of description in (3) During communication at same potential (CSI

mode)

34 Modification of description in (4) During communication at same potential (CSI

mode)

36 Modification of table and Note 2 in (5) During communication at same

potential (simplified I 2C mode) 38, 39 Modification of table and Notes 1 to 9 in (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) 40 Modification of Remarks 1 to 3 in (6) Communication at different potential (1.8

2.5 V, 3 V) (UART mode)

41 Modification of table in (7) Communication at different potential (2.5 V, 3 V) (CSI mode) 42 Modification of Caution in (7) Communication at different potential (2.5 V, 3 V) (CSI mode) 43 Modification of table in (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (1/3)

44 Modification of table and Notes 1 and 2 in (8) Communication at different

potential (1.8 V, 2.5 V, 3 V) (CSI mode) (2/3)

45 Modification of table, Note 1, and Caution 1 in (8) Communication at different

potential (1.8 V, 2.5 V, 3 V) (CSI mode) (3/3) 47 Modification of table in (9) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode)

50 Modification of table, Note 1, and Caution 1 in (10) Communication at different

potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode)

Rev. Date 2.00 Sep 06, 2013 52 Modification of Remark in 2.5.2 Serial interface IICA 53 Addition of table to 2.6.1 A/D converter characteristics 53 Modification of description in 2.6.1 (1) 54 Modification of Notes 3 to 5 in 2.6.1 (1) 54 Modification of description and Notes 2 to 4 in 2.6.1 (2) 55 Modification of description and Notes 3 and 4 in 2.6.1 (3) 56 Modification of description and Notes 3 and 4 in 2.6.1 (4) 57 Modification of table in 2.6.2 Temperature sensor/internal reference voltage characteristics 57 Modification of table and Note in 2.6.3 POR circuit characteristics 58 Modification of table in 2.6.4 LVD circuit characteristics

59 Modification of table of LVD detection voltage of interrupt & reset mode

59 Modification of number and title to 2.6.5 Power supply voltage rising slope characteristics 61 Modification of table, figure, and Remark in 2.10 Timing of Entry to Flash Memory Programming Modes 62 to 103 Addition of products of industrial applications (G: T A = -40 to +105°C) 104 to 106 Addition of products of industrial applications (G: T A = -40 to +105°C)

2.10 Mar 25, 2016 6 Modification of Figure 1- 1 Part Number, Memory Size, and Package of

7 Modification of Table 1-1 Li st of Ordering Part Numbers

8 Addition of product name (RL78/G12) an d description (Top View) in 1.4.1 20- pin products 9 Addition of product name (RL78/G12) an d description (Top View) in 1.4.2 24- pin products 10 Addition of product name (RL78/G12) and description (Top View) in 1.4.3 30- pin products 15 Modification of description in 1.7 Outline of Functions

16 Modification of description, an d addition of target products

52 Modification of note 2 in 2.5.2 Serial interface IICA 60 Modification of title and note, and addition of caution in 2.7 RAM Data Retention Characteristics 60 Modification of conditions in 2.8 Flash Memory Programming Characteristics

62 Modification of description, and add ition of target products and remark

94 Modification of note 2 in 3.5.2 Serial interface IICA 102 Modification of title and note in 3. 7 RAM Data Retention Characteristics 102 Modification of conditions in 3.8 Flash Memory Programming Characteristics 104 to 106 Addition of package name

2.20 Oct 31, 2018 4 Modification of Tabl e 1-1 List of Ordering Part Numbers

7 Modification of pin configuratio n diagram in 1.4.1 20-pin products

2.21 Jan 31, 2020 3 Addition of pac kaging specifications in Figure 1-1 Part Number, Memory Size,

4, 5 Addition of part number s and RENESAS codes in Table 1-1 List of Ordering Part Numbers 105, 106, 108 Modification of the titles of the subchapters and deletion of product names in Chapter 4 107 Addition of figure in 4.2 24-pin package

2.22 Apr 28, 2020 3 Addition of packaging specifications and package type in Figure 1-1 Part

Number, Memory Size, and Package of RL78/G12

4 Addition of packaging specifications in Table 1-1 List of Ordering Part

9 Addition of packaging specificat ions in 1.4.1 20-pin products 107 Addition of figure in 4.1 20-pin package

Rev. Date

2.30 Jun 19, 2020 3 Modification of Figure 1-1 Part Number, Memory Size, and Package of

4 Modification of Table 1-1 Li st of Ordering Part Numbers

2.31 Mar 20, 2023 All The module name for CSI was changed to Simplified SPI (CSI)

All "wait" for IIC was m odified to "clock stretch"

1 Addition of Note 1 in 1 Features

4 Modification of description in Table 1-1 List of Ordering Part Numbers

108 Addition of package drawing in 4.4 24-pin Package 2.40 Mar 29, 2024 3 Modification of Figure 1-1. Part Number, Memory Size, and Package of RL78/G12 4 Modification of Table 1-1. Li st of Ordering Part Numbers 2.50 Jan 17, 2025 3 Modification of Figure 1-1. Part Number, Memory Size, and Package of RL78/G12 4 Modification of Table 1-1. Li st of Ordering Part Numbers All trademarks and registered trademarks are the property of their respective owners. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.

General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. Precaution against Electrostatic Discharge (ESD) A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices. 2. Processing at power-on The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the level at which resetting is specified. 3. Input of signal during power-off state Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Follow the guideline for input signal during power-off state as described in your product documentation. 4. Handling of unused pins Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. 5. Clock signals After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or f rom an external oscillator during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable. 6. Voltage application waveform at input pin Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between V IL (Max.) and VIH (Min.). 7. Prohibition of access to reserved addresses Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these addresses as the correct operation of the LSI is not guaranteed. 8. Differences between products Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, im plement a system- evaluation test for the given product.

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When using Renesas Electronics products, refer to the latest product information (data sheets, user’s manuals, application notes, “General Notes for Handling and Using Semiconductor Devices” in the reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat dissipation characteristics, installation, etc. Renesas Electronics disclaims any and all liability for any malfunctions, failure or accident arising out of the use of Renesas Electronics products outside of such specified ranges. 9. Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific characteristics, such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Unless designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are not subject to radiation resistance design. You are responsible for implementing safety measures to guard against the possibility of bodily injury, injury or damage caused by fire, and/or danger to the public in the event of a failure or malfunction of Renesas Electronics products, such as safety design for hardware and software, including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult and impractical, you are responsible for evaluating the safety of the final products or systems manufactured by you. 10. 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(Note2) “Renesas Electronics product(s) ” means any product developed or manufactured by or for Renesas Electronics. (Rev.5.0-1 October 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners.