RL5C476A

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PCI-CARDBUS BRIDGE DATA SHEET

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RiGOH Version 1.4 May. 13,1998 RL5C476A_Pci-CARDBUS BRIDGE DATA SHEET

1 OVERVIEW

The RL5C476A is a PC card controller offering a single chip solution as a bridge between PCI bus and CardBus. The RL5C476A includes two PC Card 95 compliant sockets interface and a bridge function to the PCI bus of 33Mhz. The RL5C476A can support the 32-bit CardBus(Card-32) and the 16-bit PC card(Card-16) without external buffers. Concerning the card control interface, the RL5C476A‘s register is compatible with the Intel 82365SL and Ricoh’s RF5C396/366 in order to maintain backward compatibility with the existing 16-bit PC Card compliant with PCMCIA2.1/JEIDA4.2. All PC card interface signals are individually buffered to allow direct connection to CardBus and Hot insertion/removal without external buffers. The RL5C476A also allows direct connection to PCI bus. The PCI interface and PC card socket interface have their own power supply terminals that can be powered at either 3.3V or 5V for compatibility with 3.3V and 5V signaling environments. The core logic is powered at 3.3V. The RL5C476A allows the system to be equipped with the high performance multimedia PC cards like the Video capture card. @ = ~=PC97 compliant . PC97 Design Guide compliant (Subsystem ID, Subsystem Vender ID) . ACPI 1.0 and PCI Bus Power Management 1.0 compliant @ Low Power consumption . Hardware Suspend (Non shared Hardware Suspend Input) . CLKRUN#,CCLKRUN# support @ High-performance @ Single Chip PCI-CardBus Bridge . 2 PCMCIA PC-Card 95 sockets support : CardBus(Card-32) Card and 16-bit(PCMCIA2.1/JEIDA4.2) Card work at the same time . Bridge function between PCI bus and CardBus @ = = PCI Bus Interface @ Compliant with PCI Local Bus Specification 2.1 . the maximum frequency 33MHz . PCI Master/Target protocol support —— . - Separated PCI configuration each socket Sen geag ie + Direct connection to PCI bus 82 Windews Ne? Windors’SS Microsoft, Windows, the Windows logo, and Windows NT are registered trademarks of Microsoft Corporation. RICOH ©1998 REV 1.4 1

RL5C476A_ PCI-CARDBUS BRIDGE DATA SHEET RICOH COMPANY,LTD. @ CardBus PC card Bridge . Compliant with PCMCIA PC Card 95/CardBus Standard Specification . Compliant with Yenta register set Rev2.2 . the maximum frequency 33MHz . CardBus Master/Target protocol support . Transfer transactions . All memory read/write transaction(bi-direction) . V/O read/write transaction(bi-direction) . Configuration read/write transaction(PCl > Card) . 2 programmable memory windows. . 2 programmable I/O windows @ = PC Card-16 Bridge . Compliant with PCMCIA PC Card 95 CardBus(PC Card-16) Standard Specification . 5 programmable memory windows. . 2 programmable I/O windows . Compliant with i82365SL compatible register set / ExCA TM @ == System Interrupt . INTA#,INTB# support for PCI system interrupt (Non shared INT# pin) . IRQn support for ISA system interrupt (Non shared IRQn pins) . Serialized IRQ support @ = 3.3V/5V Mixed Voltage Operation at 33Mhz @ = GPIO support @ Posting Write and Prefetching Read support @ = Plug and Play support @ = =16-bit Legacy mode (3E0/3E2 I/O port) support @ Zoomed Video Port support . Bypass type @ ~~ PClway Legacy DMA support @ = Package . 208pin LQFP 0.5P t=1.7mm 2 REV 1.4 RIGO 1998

RL5C476A_ PCI-CARDBUS BRIDGE DATA SHEET RICOH COMPANY LTD.

2 BLOCK DIAGRAM

Socket B(Func#1) : Socket A (Func#0) REGS por] [eaatus | [ cardaus ACCU - Address Address | | Interface 1DSEL Decode Decode ACREGH AD/31:0) PCI & & Master & CIBE[3:0# Interface Mapping Mapping Target ACCLKRUN# PAR ‘ACAD[31:0) =RAMEF ACC/BE[3.0) DEVSEL# ACPAR IRDY# ACFRAME# TRDY# ACDEVSEL# STOPS 16-bit ACIRDY# - rf on RoDRIDATA] | Interface ACTRDY# : Buff PERR# Registers}! ports carg || Master ACPERR# SERR# MPX ACSERR# Buffer ACCD1.2# Manage Socket ‘ACVS1,2 PCICLK _._.[ RESET Cardbus Status & ACSTSCHG PCIRST# a Resistors Control ACINT# CLKRUN# Clock eo ACAUDIO ADDR/DATA HWSPND# revit |] ate, |] Socket G3EN# AVCCSEN#, INTAS_INTB# | [Interrupt Registers Control /PPENO.AVPPEN1 IRQ3-IRQ15 & RI_OUT# Audio SPKROUT# RIGOR ©1998 REV 1.4 3

RL5C476A_ PCI-CARDBUS BRIDGE DATA SHEET RICOH COMPANY,LTD.

3 PIN DESCRIPTION

3.1 Pin Assignments

IRLSC476A PIN ASSIGNMENT(TOP VIEW) £ coy 3s Th stest = 5 = 3 33008 See S.Get25 Gos o8, cnt wot REZ aeEe ROCF coagotce ROD DoOoRONSS 88 SASSSt Bono herons SSSSESRaLUOES | BoGeSggSESS eee es oooooo0ooooooooooooooooooooooOoOoDoooooooOooooooOoooooo_ ACADI9 ql 1978 2 soa aps AEABIE AB AEABeS ABs GE8"Sora g q AB XSKoss AB Acagis ABE AGSERR ie] 4 CIBEOt ACSERR# 4 pig Acabes = ABS Reaince H VOC PCI Actes Fl vee, AEKbes A Bs ASAIO Fl AB READS? ADIS READS ADI4 ASABE 816 AERBES shes " AGADat FR oa H BEARE Eee E H Ssh BExBto a ieee BcADi | ive BEABI Ae BEABIS FRA Beean See BeeEARe Ate Bene Abe Bera” GI q Peal Ea! ABee BESPARe A ee VeeStors Giese Vee"Store be Scape ; Age Betsy RL5C476A Pin Assignment j {Repo Ew CardBus PC Card Interface Config. i4 BCCURRUNE 5 Abs BGoree ie] A030 BOCIBE1# 4 a an Ae Ge BEABe A git BEAR? | BOicLK BEAR? 206 A Se BeerseKe = Bl ops PORsre QOD 000NDNO ORONO NOON RO RANSHOONROROBAHEBANHNHaoAop seaeae | SSaasgc5 (SRRAENIAR EOE Reece eee eae ae fase Pence Ss GES Se 8 g® © BOR aa 3 4 REV. 1.4 RIGOHe1998

RL5C476A_ PCI-CARDBUS BRIDGE DATA SHEET RICOH COMPANY,LTD. RL5C476A PIN ASSIGNMENT(TOP VIEW) we os 6 ei Skee akakas S228 NELNS Nn BzIP2—roO,- S Tees ese panes FERRE G0 CRREREERGCER Keatcie PectrOeenesanune Ss SSeS eS Sess SeSBES BNSC ae oes Les pee cere eee eee cere ee ee eet eee entree: ce eeeeee eee ooooooooooooooooooOoooOoooooooOooODoooooooooOooooOooooooo y B Bj 104,00 ALT ACADK25 DB} 1572 = AEABRS 4 BABS AC 6 (Seon GI qe Ageger BOR AAD | Bee oy Ra Xie ASR ee AGS Bio ABVD2 Ath Agbaino «= A H ABs ACDATAO: Ae ASBaA; = B ABls ASBAS Bis ASA GI a Se, ASN S ge ASEAN 9 cat BESS BLVSEe Boer TROY# Haat IROYa BoWat 4 B taMee ECabat: CIBE2H ntl qe BEABaig Bis Bet coe B i Eby, ADIS Boca GI a BS Bava Be Beapies pa Benger ies BcAbaS ibSEL Séxone A Hoxos" Beat a mes aye RL5C476A Pin Assignment F Wee pci BOAR soe A 16-bit PC Card Interface Contig. |B A822 Exteosior FI A ae Buse! 3 Benes Be Beas Be BAGS El ae Bt BEABAIS 53]0 PCIRST# Beas Bl o TE gen oemengooagengopagsorageunumcosssenengaannorswos Bee ae acs ae en ee eae Bie Se mes EERE BEB5888"3 Sonese pansion g Seogee ees Sages ganeaas yranss a: > c RIGOW ©1998 REV. 1.4 5

RL5C476A PCI-CARDBUS BRIDGE DATA SHEET RICOH COMPANY,LTD.

3.2 Pin Characteristics

RL5C476A pin characteristics Interface Interface Grsoesoecesce Type Pulldown 16/CB [1_[acoaras | vo [cass | vo | vor |e [ro] | oma |i _| [2 [sooatas | vo [acaos | v0 | worm | 6 | Po | | ama | i _| [3 [ooarar [vo [ecaor [vo | worn {| 8 | ro] | ona | + | [+ [eooarart [vo [ocave [vo [ worn [| 8 [ro] | ena |_| [s_[ecoatae [vo [acaos | wo | worn | 6 | ro] | oma | a _| [= [ecaoras [0 [acramwer [wo | vo [es | | | ama |_| [7 fecaons [of |—| os fs] | [em |_| s_[veo sive | eo [veo sore | oof pwn fe | | | — | | [2s [ecaore [0 [ecsrope [vo | voru | 8 | | ru ona | = | [10 [ecaon7 | o fecane [vol vo fs] | | ea | [ai_[ecannae [0 [acao [wo [vo fs | | | oma |_| [2 [ecaonis [0 [eomove | vo | voru | 6 | | ru ona | 2 | [is [ono [ecfen [oc] pm fs] | |— | | [is [sonora [0 [scan [wo] vo |e | | | ama | | [is [ecoatae [vo [— | —| ro fs [ro] | oma |_| [7 [econ [0 [ecu [rot wo fe] | | ma | [ie [ecaoas | 0 |acaow [wo] vo |e | | | emal| | [12 [eooaraio [vo [ecaosr [vo | worn {8 | ro] | ona | + | [20 [ecaons [0 fecanr [of wo fs] | | ea | [21 _[ecoatas | vo [acaos | wo | worn | 6 | ro] | oma | a _| [22 [ecaona [0 [acanz [wo | vo [es | | | emal| | [2s [ecaonie | 0 |scosew [wo | vo |e | | | oma | | [24 [coarse | vo [acane | wo | voro | = | ro] | oma | a _| [25 [ecoatar | vo [acaoa | vo | woro |e | ro | | oma | 1_| [es [ecoae [vo [| — [wor fe [rot [ama [1 | [27 [ecoaras [vo [cans [vo | worn {| 8 | ro] | ena | | [2s [ecoatas | vo [scans | vo | worn | 5 | ro] | ama | a _| [2 [anraces [1 [eorece [1 [wo [es fetel — | | BBVD1/ BCSTCHG (PUY PU fee | Pe TTT BRI# [si _[veo.cone [eo [veo core [oo [pwn fe] | | — | | [ss_[averens | 0 [averenr [| o | o [s | | | ama] | [ss [evereno [0 [overeo [o | o {s | | | | [35 [evocsens [0 [ovecsew [of o {s | | | ml _| [se [evoosens [0 [avoosers [o [ots [| | [al | 6 REV. 1.4 RIGOHe1998

RL5C476A_ PCI-CARDBUS BRIDGE DATA SHEET RICOH COMPANY,LTD. Interface Interface fell EEE Type Pulldown 16/CB Da [om [o[aom ~opos |s) | [a] | [se [ecow [1 [ecco [1 [wo fs [ule] — |_| [ss [acces [1 [eccoee [7 [es Propet — |_| [wo [evsie [vo fost prof wo fs | | | ma] | [a [ever [uo [aovse Po [wo fs | || ma |_| [eines [wo [ros fo [wo fr [|| oma |_| Ps [noe [vo [mos [wo [ofp [| | | ona | [«[inos [wo [mos [wo [wo fr | || oma |_| [ws [nor [wo [rar wo [oe [| |] ona | [a6 [inowsnncr | 10 [moomosr [vo [wo [Pr ||| ena |_| [we [ron [ofan fo [ons fr | || ma] _| [as [noe [0 [ware [0 [ons Pr [ff ama | [so [incre [0 [wars fo [ons Pr | | | oma |_| [si [nos | -o [rors [0 [ons Pf | | ona |_| [se [oro [vo [euro [vo fo fr | || roe |_| Ps [ew [oe [eno foe [awe Pe | fT - |_| [ss [rac [7 [rack fa [7 fe [ff [ss [ows [a fews [7 [7 fe f ft [- ]_ [sr [rece | 0 [rece fo [ors Pr [| reer | [se [aes [wo [asst fe [0 fe | |_| roe |_| [ss [ase | wo [aoso [we [ofp | |_| oer |_| [so [aves [wo [aos [wo [wo [er | | | roa[ _| [si [ane | wo [aoe [wo [ofp | | | oer |_| [sx [aver [wo [aor [wo [wo [re | | | roa |_| [s5 [aes | wo [aves [wo [wo |p | | | oer |_| Pe pe=fefe= fete TT a [es [aes | wo [aan [wo [wo |p | | | oer |_| [or [ove [vo [osew [of wo [re] | [ro] _| [ee fost [1 fost ff fe Pf [ss [aves [10 [noms [ro [oe [|_| roar |_| [70 [anze [wo [aoe [wo [wo fr | |_| roa |_| [7 [aver [ve [aoa Pe [0 fe ff oer [| [72 [aves [1 [asso [we [wo fe [| | roe |_| [7 [avis [10 [aos [wo [wo fe | |_| roar |_| [7 [aoe [wo [aoe [wo [wo fr | | | oer |_| [7s [ao [10 [aor Pwo [wo fe [|_| oer |_| Pre [aoe [wo [aoe po [wo fret | | roe [ | RIGO 01998 REV. 1.4 7

RL5C476A_ PCI-CARDBUS BRIDGE DATA SHEET RICOH COMPANY,LTD. == lass Interface Interface ScScesrace Type Pulldown 16/CB [7 [ose [vo fos [mol wo |r| | [ral] | [7e_[rraves [vo [raver [wo [vo [fe [| | rom |_| [7 [rove | vo prow [ol] vo |e | | [ron] | [so [rove [vo [rove [wo | vo fe | | | roe] | [et _forvses [vo forvsew [of vo |e | | | ron] | [se [store [vo [store [wo [vo fe | | | ro] | [as _[reane [vo [rene [wo [vo fe [|_| roe |_| [s_[senne | 0 [scare [0 | oon |e | | | row] _| [ss [ran [10 [ran [wo] vo [| | | ro] | [es [ose [10 [owe [wo | vo [| | | ro] | [er[eno focfew [oc] pwa «| | | —| | [ee fas [vofaos |mol wo |e | | [room| | [ee faow [wo [aoe [wo [vo fe [| | rom] | [20 faoe [vo Pao [wo [vo fe [|| Poe [| [sia [10 [aoe [wo [vo [e [| | row |_| [ee fan [vofaon |ol wi fe} | [rol | [e_[aoo [vo [ao [wf wo fe | | | ro| | Ps |vecra [oc[vecra [oct ewe tet | | — | | [ss [acs [ vo fae [ol wo fe] | [ro | | [2 [aos [10 [aos [wo] vo [| | [rom] | [sr [owe [vo [ower [wo | vo |e | | | roe | | [ss [aor | 1o|ar [wo] o |e] | [rom] | [se [aos | vo fans fof wo |e | | | rom] | [too [aos [wo fans [wo [vo fe [| | ro] | [wer_[aoe vo [aoe [wo [vo [Poet [ioe [aos [vo [aos [wo [vo [e [|_| roe |_| [ies_[aoe [vo [ave [wo [vo fe [|| Poet [ioe [aor vo far [wo [vo [er [| | ro |_| [is_[aoo [vo [avo [wo [vo fe [|_| roe [| [ios [rar | 0 [wre [0 | oo |e | | | row] _| [108 [rwsenow [1 [rwsenoe [1 [1 | s | | | — | | [ios_[avereni | 0 |averenr | o | o [5 | | | ma] | [iii [avecsens [0 [avecses |-o [o [| s | | | ama |_| [ire [aveosens [0 [avecses |-o [o [fs [| | | ama |_| pees Tepes Tete tet [1 in in [a _[acow [1 [accom eo fs peut | [ts [acoer [1 [accor Tt [wo fs [eutel — |_| 8 REV. 1.4 RIGOMo1998

RL5C476A_ PCI-CARDBUS BRIDGE DATA SHEET RICOH COMPANY,LTD. == lass Interface Interface ScScesrsce Type Pulldown 16/CB [ne favs [vofawsr | o] mo |s | 7 | ml | [a7 [aver [vo [roves [wo [vo fs | | | ml ae | Ps ASTSCHG#/ \\(PD) ARI# [ne _[anracee [1 [acre [1 [wo [a feof — [| [20 [aopatas | 10 [acaoo | 10 | vor) | a [ro | | ana | 7 _| [rex [acoatatr [vo [acaoe | vo | voro [a [ro] | ena | 1 | [ize [acpatas | 10 [acaor | wo | vom) | a [ro | | ana | 1 _| [ves [acoataie | 10 [acaos | wo | worn) [a [ro] | ena | 1 _| [iar _[acoatas | 10 [acaos | wo | von) | a | Po | | ama | 1 _| fas [ow foo feno [oct ewe to | | [ — [| [125 [acoatats | vo facade | vO | vor) | aA | Po | | ena | 1 _| [rer [acoatas [vo [acaos | wo | vowo [a [ro] | ena | 1 | [vee [acoaaa [vo [— | — | oro | a fro] [ana | 1 | [iza_[acoatar [vo [aoaor | wo | vowo [a [ro || ena [7 _| [is0_[aopatais | 10 [acaos | v0 | voro) | a | Po | | ana | 7_| [ist [ace | 0 acoeor [wo [ vo [a | | | ama |_| [ise [acese | 0 [acano [wo] vo | a | | | ama |_| [iss_[acaonio | 0 [acaos [wo] vo [a | | | ama | | [ioe [acre | 0 [acaon [wo] vo [a] | | ama |_| [ies _[acaonis [0 [aca [wo [vo [at | | ema |_| [ier [wowne [0 [acaos [wo [vo [a [|| ama [| [138 [veo.siora [oc [vec sical vc | ewe ta | | | — |_| [ise_[acaona [0 [acaos [wo | vo [a | | | ama |_| [40 [acaoni7 [0 [acaoie [wo [vo [a [|| ema |_| [ia [acaons | 0 [acowew [wo] vo [a | | | ama |_| [we [acaonis [off — | om [af | [ema [| [14s [acaoars | © [acran [wo | vo [a] | | ema |_| [14s [acaonia [0 [aorenns | vo | voruy [a [|u| ena | 2 | [ve [acaonee [0 [acstors | vo | voru [a [| ru] ena [2 | [ias_[aoaona’ | 0 [acoevser [10 | voru | a | | ru] ana | 2 | Oa a AIREQ# | iso_[acaonze [0 [actaove [vo | worn [a [| ro] ana | 2 | Pas fow foote foct pw tet | [| | [ise [acaonie [0 [aoox [-o [ors [a [ | [= [| RIGOR ©1998 REV. 1.4 9

RL5C476A_ PCI-CARDBUS BRIDGE DATA SHEET RICOH COMPANY,LTD. === Interface Interface SoScearsce Type Pulldown 16/CB [153 [Acaones | 0 [acrrawer | vo | vo | A] | | ema |_| [we [acanis [0 [aorove | vo [vor [a [| Pu| ama | 2 | [155 [acaones | 0 [acaoy | wo | vo | a | | | ema |_| [vss [acaonie [o [acowesr [wo [vo [a | | | eal | [157 [acaones [0 [acaote | wo | vo | a | | | ema |_| [vs [acaon7 [0 [acaois [wo [vo [a | | | ema |_| [ise [acaone [~o [acaoz [wo [vo [a [|| ema |_| [120 [veo stor | oc [vec siota| vc | pwa ta | | | — |_| [ist_[acaoas | 0 |acaor [wo] vo [a | | | ama | | [ise_[aneser [0 [acaste | o | ons | a | | | ama |_| [ies_[acaons | 0 |acaoze [wo] vo [a | | | ema |_| [vee [aware [1 [acsenne [1 [eo [a peut lt — || [ies [acaons [0 [acanes [vo [vo [a [| | ama [| [ise [acaone [0 [canes [wo [vo [a | | | ama |_| [ter [anece [0 [acowese [wo [vo [a [| | ema |_| [iss_[acaoni [0 [canes [wo [vo [a | | | ana |_| Oe i ASPKR# [-i70 [acaono | 0 [acaos | vo | vo | a | | | ema |_| [71 [acoatae [vo [cane | wo | voro) [a [ro] | ema | 1 | [ive [acoatas [vo [acanas [vo | vowo [a [eo] | ana [1 | [izs_[aopatar | vo [acaoes [wo | voro) | a [ro | | ana | 1 [ia [acoatas [vo [cao | vo | voro [a [ro] | ena | 1 | is [acon [vo [— | — | worn, | a [ro] | ema | + | [ize _[acoataio | vo [acaosr | vo | vor | a | ro | | ana | 1 _| Oe ad ll AIOIS16# | ive [voc_cone | oc [vec.core | oc | pwr [ c | | | — || [ie [occ | 0 [cower [vo | vo |e | | | ema | | [ao [sce [0 [scan [wo] vo | s| | | ama | | [tr [eocr | 0 fac [io] vo |e | | | ema | | [ie [sionow | 0 |acaos [wo] vo | s| | | ema |_| [ie [ecaonis [0 [aoran [wo [vo fs | | | ema |_| [vs [canna [0 [aorenns [vo [vory [= [|u| ana [2 | oe a in in [iar [ewer | 0 [eco [| o | om | 5 | | | ama] | a Ga BIREQ# [iss_[sonona [0 | ecoevsere [vo | worn | 8 | | ru] ana | | [is [socaonz [0 [ectaove [wo | orn] s | | ru] ama | 2 | 10 REV. 1.4 RIGOMo1998

RL5C476A_ PCI-CARDBUS BRIDGE DATA SHEET RICOH COMPANY LTD. 16-bit Card CardBus Card Pin Characteristics Interface Interface Pullup Type | Pwr Pulldown Rail 16/CB Tiei_[oneser | 0 foorsw | o | om [2] | | ma] | Vise [owas [1 [ocserae [i [ro [es fete, — |_| [iss [ecaons | o [ecase [vo | wo |e] | [ema |_| | te [vecsiore [oc [vec store [oc [ pwr [ 8 | fT — [| [iss [ecaore | 0 [ecanee | wo | vo |e || [ema |_| [ise [Pecans | 0 [ecanes | vo | vo |e | [| ena |_| [sr [oncce | 0 fecowes [wo] vo [e| | | ema] | BBVD2/ BCAUDIO (PU) PU PU BSPKR# [ise [ecanne | 0 [ecases | vo | vo |e || [ema |_|

200 BWP/ BCCLKRUN# | I/O VO(PU) PU 8mA

BIOIS16# | 201 [eooatas | vo [acano | vo | voro) [ 8 [po] [ama [ 1 | gcaore | 0 [ecoses [vo | vo |e | | [ema |_| [2s [ecaore | o facapw [wo] vo | e| | | ema] | [20 [ecoarais [v0 [scans | vo | wore |e | Po] | oma [7 | [205 [acaonio [0 [scans uo f wo fe] || oma| | [206 [ecoara | vo [ecani | vo | oro) |e | Po [ | ena | 1_| [sor fecaoans | 0 [ecane | vo] 1 [|e | | [ena |_| [2s Jecaors fof | olwerte| [a] ema] | Pin Type |: Input Pin, O: Output Pin, VO: Input Output Pin, \\(PU): Input Pin with Internal Pullup Resister, (PD): Input Pin with Internal Pulldown Resister, VO(PU): Input Output Pin with Internal Pullup Resister, VO(PD): Input Output Pin with Internal Pulldown Resister, O(TS): Three State Output Pin, (OD): Open Drain Output Pin Power Rail P: VCC_PCI, Cc: VCC_CORE, A: VCC_SLOTA, B: VCC_SLOTB, 5: VCC_5V Drive PCI21: PCI2.1 Compliant, CB: PCMCIA CardBus PC Card Compliant Note 1: Pull down is attached when PC Card Interface is configured as 16-bit Interface Mode. 2: Pull up is attached when PC Card Interface is configured as a CardBus Interface Mode. 3: Pull up or Pull down is configured according to the type of a card inserted. RIGOR ©1998 REV. 1.4 1

RL5C476A_ PCI-CARDBUS BRIDGE DATA SHEET RICOH COMPANY,LTD.

3.3 Pin Functions Outline & Description

In this chapter, the detailed signal pins in RL5C476A are explained. Every signal is divided according to their relational interface. Card Interface signal pin is multi-functional pin. Card Interface mode is configured automatically by the card insertion ; CardBus card or 16-bit card. And the pin function is redefined again. # mark means the signal is on either active or asserted when the signal is low-level. Otherwise, no-mark means the signal is asserted when the signal is high-level. The following the notations are used to describe the signal type. IN Input Pin OUT Output Pin ouT(Ts) Three State Output Pin ouT(OD) Open Drain Output Pin vo Input Output Pin vocop) Input Output Pin (Output is Open Drain) shiz Sustained Tri-State is an active low tri-state signal owned and driven by one and only one agent ata time. The agent that drives an s/t/z pin low must drive it high for at least one clock before letting it float. A new agent cannot start driving a s/h/z signal any sooner than one clock after the previous owner tri-state is. 12 REV. 1.4 RIGOGIC1998

RL5C476A_ PCI-CARDBUS BRIDGE DATA SHEET RICOH COMPANY LTD.

3.4 PCI Local Bus interface

| Pintieme | twe [Description PCI Bus Interface Pin Descriptions PCICLK PCI CLOCK: PCICLK provides timing for all transactions on PCI. All other PCI signals are sampled on the rising edge of PCICLK. CLKRUN# VO(OD)_| PCI CLOCK RUN: This signal indicates the status of PCICLK and an open drain output to request the starting or speeding up of PCICLK. This pin complies with Mobile PCI specification. This signal has no meaning for 16bit card. Tie to GND if not used. PCIRST# PCI RESET: This input is used to initialize all registers, sequences and signals of the RL5C476A to their rest states. All of the outputs of the RL5C476A will be tri-stated during PCIRST is asserted. ADIS1:0] ADDRESS AND DATA: Address and Data are multiplexed on the same PCI pins C/BE[3:0}# vo BUS COMMAND AND BYTE ENABLES: Bus Command and Byte Enables are multiplexed on the same PCI pins. During the address phase of transaction, C/BE{3:0}# define the bus command. During the data phase C/BE[3:0}# are used as Byte Enables. The Byte Enables are valid for the entire data phase and determine which byte lanes carry meaningful data. vo | PARITY: Parity is even parity across AD[31:0] and C/BE[3:0}#. PAR is stable and valid one clock after the address phase. For data phases, PAR Is stable and valid one clock after either IRDY# is asserted on a write transaction or TRDY# is asserted on a read transaction. The master drives PAR for address and write data phases; the target drives PAR for read data phases. FRAME# vO | CYCLE FRAME: This signal is driven by the current master to indicate the beginning shiz and duration of an access. FRAME# is asserted to indicate a bus transaction is beginning. While FRAME# is asserted, data transfers continue. When FRAME# is deasserted, the transaction is in the final data phase or has complete. TRDY# vo TARGET READY: This signal indicates the initialing agent's ability to complete the sih/z | current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed on any clock both TROY# and IRDY# are sampled asserted. During a read, TROY# and IRDY# are sampled asserted. During a read, TRDY# indicates that valid data is present on AD[31:0]. During a write, it indicates the target is prepared to accept data, Wait cycles are inserted both IRDY# and TROY# are asserted together. IRDY# vo | INITIATOR READY: This signal indicates the initiating agent's ability to complete the sih’z | current data phase of the transaction. IRDY# is used in conjunction with TRDY#. A data phase is completed on any clock both TROY# and IRDY# are sampled asserted. During a write, IRDY# indicates that valid data is present on AD[31:0]. During a read, it indicates the target is prepared to accept data. Wait cycles are inserted both IRDY# and TRDY# are asserted together. STOP# vo | STOP: This signal indicates the current target is requesting the master to stop the sih/z__| current transaction. IDSEL INITIALIZATION DEVICE SELECT: This signal is used as a chip select during configuration read and write transactions. DEVSEL# vO | DEVICE SELECT: When actively driven, indicates the driving device has decoded its siniz | address as the target of the current access. As an input, DEVSEL¢ indicates whether any device on the bus has been selected. vO | PARITY ERROR: This signal is only for the reporting of data parity errors during all sih/z | PCI transactions except a Special Cycle. The RL5C476A drives this output active “low” if it detects a data parity error during a write phase. SERR# OUT(OD) | SYSTEM ERROR: This signal is pure open drain. The RLSC476A actively drives this output for a single PCI clock when it detects an address parity error on either the primary bus or the secondary bus. OUT(TS) | REQUEST: This signal indicates to the arbiter that the RLSC476A desires use of the bus. This is a point to point signal GNT# GRANT: This signal indicates the RL5C476A that access to the bus has been granted. This is a point to point signal. RIGOR ©1998 REV. 1.4 13

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3.5 System Interrupt Signals

[Paname [Te [pion Sd System Interrupt Pin Descriptions INTA# OUT(OD) | PCI INTERRUPT REQUEST A: This signal indicates a programmable interrupt request generated from the card socket A interface. This signal is connected PCI bus INTAé interrupt line. INTB# OUT(OD) | PCI INTERRUPT REQUEST B: This signal indicates a programmable interrupt request generated from the card socket B interface. This signal is connected PCI bus INTB# interrupt line. IRQ3/GPIOO OUT(TS) | SYSTEM INTERRUPT REQUEST IRQ 3-15: These signals indicate the interrupts Inoveplos requests from one of the cards and are connected to the ISA bus IRQx signal. IROT/GPIO3 IRQ12 Is reassigned as an LED output when LED enable bit in ATA control register is IRQQ/SRIRQ# set to one. When Serial IRQ Enable bit in Misc Control register is set to one, IRQ9 is IRQ10/LEDA# reassigned as SRIRQ# signal, at the same time |RQ14,15 are reassigned as AZVEN#, BZVEN# signals ; ZV port buffer control signal, and IRQ10,11 are reassigned as IRQ11/LEDB# LEDA#, LEDB# signals IRQ12/ When Serial IRQ signal is enabled, |RQ3,4,5 and 7 are assigned as GPIO (General LEDOUT Purpose I/O) pins. These are input/output pins determined by user without effect on the controller transaction IRQ14/ AZVEN# IRQ15/ BZVEN# RI_OUT# OUT | RING INDICATE OUTPUT: When 16-bit card is inserted, this signal is assigned as IPME# RI_OUT# from a socket's Ri# input when Ring Indicate Enable bit in Interrupt and General control register is set to one. POWER MANAGEMENT EVENT: This signal is reassigned as a signal equivalent to Power Management Event when PME Enable bit in Power Management Control/Status register is set to one. PCI Bus Power Management Spec requires for PME¢# to be open drain output. An extemal gate is required to become an open drain output because this pin outputs “H” or "L”. 3.6 16-bit PC Card Interface Signals | Pinname [type [Description ACDATA[15:0] vo 16-bit Card DATA BUS SIGNALS [15:0]: input buffer is disabled when the card BCDATA[15:0] socket power supply Is off or card is not inserted. ACADR(25:0] | OUT(TS) | 16-bit Card ADDRESS BUS SIGNALS [25:0]: BCADR[25:0] AlOR# OUT(TS) 16-bit Card I/O READ: BIOR# AlOW# OUT(TS) | 16-bit Card YO WRITE: Blows AOE# OUT(TS) 16-bit Card OUTPUT ENABLE: BOE# AWE# OUT(TS) | 16-bit Card WRITE ENABLE: BWE# ACE1# OUT(TS) 16-bit Card CARD ENABLE 1: BCE1# ACE2# OUT(TS) | 16-bit Card CARD ENABLE 2: BCE2# 14 REV. 1.4 RIGOHe1998

RL5C476A_ PCI-CARDBUS BRIDGE DATA SHEET RICOH COMPANY,LTD. 16-bit PC Card Interface Pin Descriptions AREG# OUT(TS) | 16-bit Card ATTRIBUTE MEMORY SELECT: Memory access is limited to Attribute BREG# memory when this signal is “low”. During normal access for /O, this signal is kept “low” and high” for DMA transfers. AREADY/ 16-bit Card READY/BUSY or INTERRUPT REQUEST: This signal has two different AIREQ# functions. READY/BUSY# input on the memory PC card, and IREQ# input on the I/O BREADY/ card, BIREQ# AWP/ 16-bit Card WRITE PROTECT or CARD IS 16-BIT PORT: This signal has two AlOIS16# different functions. Write Protect Switch input on the memory PC card, and IOIS16 awry input on the I/O card BIOIst6# ARESET OUT(TS) 16-bit Card CARD RESET: BRESET AWAIT# 16-bit Card BUS CYCLE WAIT: BWAIT# ABVD1/ 16-bit Card BATTERY VOLTAGE DETECT 1 or STATUS CHANGE: This signal has ASTSCHG#/ three different functions. The battery voltage detect input 1 on the memory PC card, ARI# and Card Status Change#/Ring Indicate# input on the V/O card BBVD1/ BSTSCHG#Y/ BRI ABVD2/ 16-bit Card BATTERY VOLTAGE DETECT 2 or DIGITAL AUDIO or LED INPUT: ASPKR#/ This signal has three different functions. The battery voltage detect input 2 on the ALED memory PC card, and SPEAKER# input or LED input on the I/O card. BBVD2/ BSPKR#/ BLED AINPACK# 16-bit Card INPUT ACKNOWLEDGE: BINPACK# ACD1# 16-bit Card CARD DETECT 1: CD[2:1}# pins are used to detect the card insertion. BCDI# CD[2:1}# pins are used in conjunction with VS[2:1}#t to decode card type information, ACD2# 16-bit Card CARD DETECT 2: CD[2:1}# pins are used to detect the card insertion. BCD2# CD[2:1} pins are used in conjunction with VS[2:1}# to decode card type information, AVSI# VO | 16-bit Card CARD VOLTAGE CAPABILITY SENSE 1: VS[2:1}# pins are used in BVS1# conjunction with CD[2:1] to decode card type information AVS2# VO | 16-bit Card CARD VOLTAGE CAPABILITY SENSE 2: VS[2:1}# pins are used in BVS2# conjunction with CD[2:1]# to decode card type information. RIGOR ©1998 REV. 1.4 15

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3.7 CardBus PC Card Interface Signals

[_pinname [type [Description CardBus PC Card Interface Pin Descriptions ACCLK OUT(TS) | CardBus Clock: This signal provides timing for all transactions on the PC Card BCCLK Standard 95 interface and it is an input to every PC Card Standard 95 device. All other CardBus PC Card signals, except CRST# (upon assertion), CCLKR, CCLKRUN#, CINT#, CSTSCHG, CAUDIO, CCD/2:1}#, and CVS[2:1], are sampled on the rising edge of CCLK, and all timing parameters are defined with respect to this edge. ACCLKRUN# vo CardBus Clock Run: This signal is used by cards to request starting (or speeding up) BCCLKRUN# sih/z__ | clock CCLK. CCLKRUN# also indicates the clock status. For PC cards, CCLKRUN# is an open drain output and it is also an input. The RL5C467 indicates the clock status of the primary bus to the CardBus card. ACRST# OUT(TS) | CardBus Card Reset: This signal is used to bring CardBus Card specific registers. BCRST# sequencers and signals to a consistent state. Anytime CRST# is asserted, all CardBus card output signals will be driven to their begin state. ACAD[31:0] i) CardBus Address/Data: These signals are multiplexed on the same CardBus card BCADI31 0] pins. A bus transaction consists of an address phase followed by one or more data phases. CardBus card supports both read and write bursts. CAD[31:0] contain a physical address (32 bits). For I/O, this is a byte address ; for configuration and memory it is a DWORD address. During data phases, CAD[7:0] contain the east significant byte(LSB) and CAD[31:24] contain the most significant byte(MSB). Write data is stable and valid when CIRDY# is asserted and read data is stable and valid when CTRDY# is asserted. Data is transferred during those clocks where both CIRDY# and CTRDY# are asserted ACC/BE[3:0]# vo CardBus Command/Bye Enables: These signals are multiplexed on the same BCC/BE(3:0}# CardBus card pins. During the address phase of a transaction, CC/BE[3:0]# define the bus command. During the data phase, CC/BE[3:0}# are used as Byte Enables. The Byte Enables are valid for the entire data phase and determine which byte lanes carry meaningful data. CC/BE[0}# applies to byte 0 (LSB) and CC/BE[3]# applies to byte 3 (MSB). ACPAR i) CardBus Parity: This signal is even parity across CADJ[31:0] and CC/BE[3:0}#. Parity BCPAR generation is required by all CardBus card agents. CPAR is stable and valid clock after either CIRDY# is asserted on a write transaction or CTRDY# is asserted on a read transaction. Once CPAR is valid, it remains valid until one clock after the completion of the current data phase. (CPAR has the same timing as CAD[31:0] but delayed by one clock.) The master drives CPAR for address and write data phases ; the target drives CPAR for read data phases. ACFRAME# vo CardBus Cycle Frame: This signal is driven by the current master to indicate the BCFRAME# s/h/z__ | beginning and duration of a transaction. CFRAME# is asserted to indicate that a bus transaction is beginning. While CFRAME# is asserted, data transfers continue. When CFRAME# is deasserted, the transaction is in the final data phase ACIRDY# vo CardBus Initiator Ready: This signal indicates the initiating agent's(bus master’s) BCIRDY# s/h/z | ability to complete the current data phase of the transaction. CIRDY# Is used in conjunction with CTRDY#. A data phase is completed on any clock both CIRDY# and CTRDY# are sampled asserted. During a write, CIRDY# indicates that valid data is present on CAD[31:0]. During a read, it indicates the master is prepared to accept data. Wait cycles are inserted until both CIRDY# and CTRDY# are asserted together. ACTRDY# vo CardBus Target Ready: This signal indicates the agent's(selected target's) ability to BCTRDY# s/h/z__| complete the current data phase of the transaction. CTRDY¢# is used in conjunction with CIRDY#. A data phase is completed on any clock both CTRDY# and CIRDY# are sampled asserted. During a read, CTRDY# indicates that valid data is present on CAD[31:0]. During a write, it indicates the target is prepared to accept data. Wait cycles are inserted until both CIRDY# and CTRDY# are asserted together. ACSTOP# vo CardBus Stop: This signal indicates the current target is requesting the master to stop BcsToP# s/h/z__ | the current transaction ACDEVSEL# vo CardBus Device Select: This signal indicates the driving device has decoded its BCDEVSEL# s/h/z | address as the target of the current access when actively driven. As an input, CDEVSEL+# indicates whether any device on the bus has been selected. ACREQ# CardBus Request: This signal indicates to the arbiter that this agent desires use of BCREQH the bus. Every master has its own CREQH 16 REV. 1.4 RIGOHe1998

RL5C476A_ PCI-CARDBUS BRIDGE DATA SHEET RICOH COMPANY,LTD. CardBus PC Card Interface Pin Descriptions (Continued) ACGNT# OuT | CardBus Grant: This signal indicates to the agent that access to the bus has been BCGNT# granted. Every master has its own CGNT#. ACPERR# vO CardBus Parity Error: This signal is only for the reporting of data parity errors during BCPERRE s/h/z__ | all CardBus Card transactions except a Special Cycle. An agent cannot report a CPERR¢# untll it has claimed the access by asserting CDEVSEL# and completed a data phase ACSERR# CardBus System Error: This signal is for reporting address parity errors, data parity BCSERR# errors on the Special Cycle command, or any other system error where the result could be catastrophic. ACINT# CardBus Interrupt Request: This signal is an input signal from CardBus card. It is BCINT# level sensitive, and asserted low (negative true), using an open drain output driver. The assertion and deassertion of CINT# is asynchronous to CCLK. ACSTSCHG CardBus Card Status Change: This signal is an input signal used to alert the system BCSTSCHG to changes in the READY, WP, or BVD[2:1] conditions of the card. It is also used for the system and/or CardBus card interface Wake up. CSTSCHG Is asynchronous to CCLK. ACAUDIO IN CardBus Card Audio: This signal is a digital audio input signal from a CardBus Card BCAUDIO to the system's speaker. CAUDIO has no relationship to CCLK ACCDi# CardBus Card Detect 1: CCD[2:1}# pins are used to detect the card insertion. BCCDI# CCD[2:1}# pins are used in conjunction with CVS[2:1] to decode card type information. ACCD2# CardBus Card Detect 2: CCD[2:1}# pins are used to detect the card insertion. BCCD2# CCD[2:1}# pins are used in conjunction with CVS[2:1] to decode card type information. ACVS1 i) CardBus Card Voltage Sense 1: CVS[2:1] pins are used in conjunction with BCVS1 CCD[2:1}# to decode card type information ACVS2 i) CardBus Card Voltage Sense 2: CVS[2:1] pins are used in conjunction with BCVS2 CCD[2:1}# to decode card type information. RIGOR ©1998 REV. 1.4 17

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3.8 Socket Power Control Signals

Socket Power Control Signal Descriptions AVCC5EN# out | vec SV ENABLE: BVCCSEN# AVCC3EN# out | vec 3.3V ENABLE: BVCC3EN# AVPPENO OUT VPP ENABLE 0: BVPPENO AVPPEN1 out | VPP ENABLE 1: BVPPEN1

3.9 Audio

3.10 Hardware Suspend

[fnene [We [on Hardware Suspend HWSPND# IN Hardware Suspend: This signal works as HWSPND# input. PCIRST# is not accepted as long as HWSPND# is asserted so that VCC_PCI can be powered off. When Serial IRQ mode is set, HWSPND# must be asserted after Serial |RQ mode on the chip-set has been deasserted. When Hardware Suspend mode is off, HWSPND# must be deasserted before Serial IRQ mode is enabled

3.11 Power and GND

[Pnveme [Wwe [ton SSCS Power Pin Descriptions voc PCI PWR | PCI VCC : Power Supply pins for PCI interface signals. This pin can be powered at either 3.3V or 5V. VCC_CORE PwR | CORE VCC : Power Supply pins for the internal core logic. This pin must be powered at 3.3V only. VCC_SLOTA SLOTA VCC : Power Supply for Card socket A. This pin can be powered at either 3.3V or 5V. VCC_SLOTB SLOTB VCC : Power Supply for Card socket B. This pin can be powered at either 3.3V or 5V. vcc_5V PWR | 5V VCC:This supply pin is connected to 5V. In systems where 5V is not available, this pin is connected to 3.3V. eno [ewe few, SSCS 18 REV. 1.4 RIGOHe1998

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4 ELECTRICAL CHARACTERISTICS

4.1 Absolute Maximum rating

[symbor | Parameter min] unit] conaition [note | [ect Sippy Votagonenget J ea-ee vow |_| [vce2 | Supply Vatage Range? | 03-so__| v | enoov |? _| vie | Votege onAnyen | oa-Veoos |v | enoov |__| [Tope [Amen Tenperueuncerbas | o-s [ o [| ——_~id [rsig [Serge Tonportworange [| _s8=8 | co | |_| note 1 : Applied for Vcc_xxx except for Vec_core . note 2 : Applied for Vcc_core only. Note: Stresses above those listed may cause permanent damage to system components. These are stress ratings only. Functional operation at these or any conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect system reliability.

4.2 DC Characteristics

4.2.1 Recommended Operating Conditions for Power Supply

[PowerPn | Parameter | wm | Tw [me [um [noe] VCC_PCI, Supply Voltage for PCI interface 4.75 5,25 Vv vec_Zv (5.0V Operation) VCC_PCI. Supply Voltage for PCI interface 3.3 v vec_zv (3.3V Operation) VCC_5V Supply Voltage for 5V Control 5.25 v Signals VCC_SLOT | Supply Voltage for Card Socket 4.75 5.0 5.25 7 AB AB (5.0V Operation) VCC_SLOT | Supply Voltage for Card Socket 33 Vv AB AVB (3.3V Operation) RICOM ©1998 REV. 1.4 19

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4.2.2 PCI interface

VCC_CORE=3.0~3.6V, VCC_PCl=4.75~5.25V, Ta=0~70°C) [symmor [Parameter | _win | Max | Unit] TeatConaiion | note | [wk [pot rignVorage | 20 [verows[v] [7 | Fun [ npttowvorage | os | oe |v] | | [vor | owpurion votage fea | |v [wana |_| [vou | owputtow vonage |__| 08s | v [ramema | 1_| Pins [npurrgnvearago coro | 7 ww [vince | | Pic [ per tow eaiage corent [| 70 a [vmosv | [cin [porn Capactancs fit or | id Fock rcicixPin carsctanes | | 2 ter] + | For 3.3V signaling VCC_CORE=3.0~3.6V, VCC_PCI=3.0~3.6V, Ta=0~70°C) [symoor[Porameter | win] Max | unit] TeatConaiion | note | [we [pot righ Vorage | caver Por | veerowos[ Vv _-| + | [vn [pt towvorage | 05 | aver |v | |_| [vor oupurtighvoroge | oven |__| v [eusooa 1 | vot [oupettowvotage || aaveerer | v [teurtsoowa | 7 | Pix [per toarage curont [fo | 9a | vinsorvee Por | [cin | prin Capactancs ff ofr | it +] Fock rcicixPincarsctancs | | 2 ter] 1+ | Note 1: Applied for PCICLK, CLKRUN#, PCIRST#, AD[31:0], C/BE#{3:0], PAR, FRAME#, IRDY#, TRDY#,STOP#, DEVSEL#, IDSEL, PERR#, SERR#, REQ#, GNT#, INTA#, INTB# pins 20 REV. 1.4 RICOL ©1998

RL5C476A__PCI-CARDBUS BRIDGE DATA SHEET RICOH COMPANY, LTD. 4.2.3. 16-bit PC Card Interface For 5V signaling Sa a lc a al ch VIH Input High Voltage 2.4 Vec_SLO v T40.3 [vi [inputtowvorage [os | [oe fv [i | [vor [ouput ign votags [24 [|| v [mena i | Fvor2 [Output igh votage [24 | | |v [toumama | 28 | Pvo.2 [ouput ow vorage |_| | 04 |v [toscana | 28 | Pik [put oatage Curent | | | x10 | ya | vnno-veo sora | 2 | wt Input Leakage Current -120 nA | Vin=0 24 (Pull-up) Le Input Leakage Current 25 uA | Vin=Vec_SLOTA/B 25 (Pull-down) fon —[inpurrincapactancs | | | [| =| For 3.3V signaling Sl ca ald Ral a VIH Input High Voltage Vec_SLO v 740.3 [vi [inputtowvorage [os | [os |v | i 2 | [vor [ouput tien votes [2a | | |v [mana i | [rove [ouput ign vorage [24 | | |v [toumama | 28 | [vor [oupertowvorage |__| | o* | v oumana | 2 | [vor [ouput ow votage | | | 08 |v [toscana [28 | Fux [nputteakage cure | | x10 | a | vineo-vee storwe | 2 | Lt Input Leakage Current nA | Vin=0 24 (Pull-up) Le Input Leakage Current nA | Vin=Vec_SLOTA/B 25 (Pull-down) [in [putin capactancs | | | [or] —~id 2 | Note 2: Applied for CADR[25:0], CDATA[15:0], CE[2:1]#, IOR#, IOW#, OE#, WE#, REG#, RDY/IREQ#, WAIT#, WP/IOIS16#, RESET, BVD1/STSCHG#RI#, BVD2/SPKR#, INPACK# pins, if Card interface is configured as a 16-bit Card Socket. Note 3: Applied for RESET pins Note 4: Applied for RDY/IREQ#, WAIT#, BVD1/STSCHG#/RI#, BVD2/SPKR#, INPACK# pins Note 5: Applied for ~CDATA[15:0]pins RICOM ©1998 REV. 1.4 21

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4.2.4 CardBus PC Card Interface

[Symbor[Perometer | min | typ] Mex | Unit] TestConditon | Note ] VIH Input High Voltage 0.475x Vec_SLOT v Vec_SLOTA/B 40.5 VIL Input Low Voltage 05 0.325x Vv Vec_SLOT [von | Ouputrin vorage pave sioTws | | |v ‘ewmiooa | 6 _| vot [oupatowvenage [| panes stor | v [rouarooia 6 | HLK Input Leakage Current +10 uA | Vin=0~Vec_SLO TAB Lt Input Leakage Current uA | Vin=0 67 (Pull-up) [en [neuen capaciance | iP or | Cd Note 6: Applied for CCLK, CCLKRUN#, CRST#, CAD[31:0], CC/BE#[3:0], CPAR, CFRAME#, CIRDY#,CTRDY#,CSTOP#, CDEVSEL#, CBLOCK#, CPERR#, CSERR#, CREQ#, CGNT#, CINT#, CAUDIO, CSTSCHG pins, if Card interface is configured as a CardBus Card Socket. Note 7 : Applied for +CCLKRUN#, CIRDY#,CTRDY#,CSTOP#, CDEVSEL#, CPERR#, CSERR#, CREQ#, CINT#, CAUDIO pins Note 8 : Applied for CSTSCHG pins

4.2.5 PC Card Interface Card detect Pins and System Interface Pins

PC Card Interface Card Detect Pins and System Interface Pins [Symbor | Poramewer | min | tw | Max | unit | Testconation | note] VIH Input High 24 Vec_5V+0. v Voltage 3 VIL Input Low Vv 911 Voltage VOH Output High 24 Vv | lout=-4ma Voltage VOH2 Output High Vv | lout=-1ma 4 Voltage VOLt Output Low 04 Vv | tout=4ma Voltage voLz Output Low 04 Vv | tout=1ma 14 Voltage ea = eee Current re] Input Leakage yA | Vin=o Current (Pull-up) fase = ee Leakage Current Note 9: Applied for CD1#(CCD1#), CD2#(CCD2#) pins Note 10: Applied for RI_OUT#, SPKROUT#, VCCS5EN#, VCC3EN#, VPPENO, VPPEN1 pins Note 11: Applied for VS1#(CVS1#), VS2#(CVS2#), pins 22 REV. 1.4 RICOM ©1998

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4.2.6 IRQ3-15 pin

4.2.7 Power Consumption

[ Powerein | __ Parameter | win [tw | wor unt] conaiton | Power Supply Current, Standby HA felk(PCICLK)=0, Vin=0or Vee Power Supply Current, HA Mode = H/W Bridge Hardware Suspend Mode Suspend VCC_SLOT=5.0V VCC_5V=5.0V VCC_PCl=0V VCC_CORE=3.3V Vin=0 or Vee Power Supply Current, Operating folk(PCICLK)=33Mhz VCC_SLOT=5.0/3.3V VCC_5V=5.0V VCC_PCI=5.0V VCC_CORE=3.3V Vin=0 or Vee RICOM ©1998 REV. 1.4 23

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4.3 AC Characteristics

4.3.1 PCI Interface Signals

RL5C476A__PCI-CARDBUS BRIDGE DATA SHEET RICOH COMPANY, LTD. PCI Interface Output Signals [symbot | ___ Parameter | min | Max | unt | notes |_| ADI81:0}, C/BE#(3:0), PAR, FRAME#, DEVSEL#, IRDY#, TRDY#,STOP#, PERR#, SERR#, CLKRUN# from PCICLK Max: CL=50 pF (10 pF 3.3v) t3b Enable Time, Hi-Z to active delay from PCICLK

130 Disable Time, Active to Hi-Z

a 13d Point to Point Signal Valid delay Min: CL=0 pF time from = PCICLK Max: CL=50 pF (10 pF 3.3v) PCI Output Signals Timing *1.5V(0.4Vec) PCICLK > \\<!3a(Shared), 13d(ptp) OUTPUT (Shared or pip) *1.5V(0.285Vce:Rise Edge, 0.615Vcc:Fall Edge) OUTPUT + id *5.0V Signaling(3.3V Signaling) PCI Output Signals Timing RICO ©1998 REV. 1.4 25

RL5C476A__PCI-CARDBUS BRIDGE DATA SHEET RICOH COMPANY, LTD. PCI Interface Input Signals [Symon] Parameter min [Max | unt [Notes || CAD[31:0], C/BE#[3:0], PAR, FRAME#,DEVSEL#, IRDY#, TRDY#,STOP#, IDSEL, PERR#, SERRY, CLKRUN# ler [TT before PCICLK femme [TP Time after PCICLK High [ere OOSSCCCCCOCCCCCC—*Y Gam =a Valid before PCICLK PCI Input Signals Timing *1.5V(0.4Vec) t4a (Shared) t4b « oe INPUT X X t4c (ptp) ——— *4.5V(0.4Vec) *5.0V Signaling(3.3V Signaling) PCI Input Signals Timing 26 REV. 1.4 RICOM ©1998

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4.3.2 System Interface Signals

System Interface Signals AC Characteristics [Looe asi NTA NTR SSCS fis [RwiomLouTwoey [<i [TY f= feats [pee IRQ3-15/INTA#,INTB# Delay 15d Card IREQ#/CINT# to IRQS-15/INTA#,INTB# Delay a 15e SPKR#/CAUDIO to SPKOUT# Delay Note1: Tcyc is PCICLK cycle time.( Typically 30ns ) ‘System Sgnals Timing t5b t5e Card Status | Change 18d 5d > « i IREQH CINT# | INTA#INTB# x RI_OUT# SPKR# \\ / CAUDIO t5e t5e SPKOUT# \\ [TS System Signals Timing RICOM ©1998 REV. 1.4 27

RL5C476A__PCI-CARDBUS BRIDGE DATA SHEET RICOH COMPANY, LTD. 4.3.3 16-bit PC Card Interface Signals Memory Read |_| CADRI25:0], REG#, CEI2:1}# 16a Setup Time, CADR[25:0], REG# Tsu-20 12 and CE[2:1}# before OE# Low Tsu=1~7Teye Programmable t6c Hold Time, CADR[25:0], REG# Thi-10 12 and CE[2:1]# after OE# High Thl=1~7Teye Programmable t6b Pulse Duration, OE# Low Tpw-20 12 Tpw=3~31Tcye Programmable [fous —SSCSCSSSSCSCSCSCC“C;™S~S~S~SCSCCCCCCSY t6d Hold Time, CDATA[15:0] after OE# High a t6e Hold Time, OE# Low 1Teyc+0 1 after WAIT# High t6f Valid Delay, OE# Low to WAIT# Low Note1: Teyc is PCICLK cycle time.( Typically 30ns ) Note2: Tsu, Tpw, Thl can be programmed by setting 16-bit Memory Timing 0 register. 16-bit Card Memory Read Timing CADR,REG#, X X CE1#,CE2# 16a t6b t6c ———— OE# \\ t6d DATA (aa) 16f t6e WAIT#t \\ Data Latched 16-bit Card Memory Read Timing 28 REV. 1.4 RICOL ©1998

RL5C476A__PCI-CARDBUS BRIDGE DATA SHEET RICOH COMPANY, LTD. Memory Write [eymvar] Parameter [win | Max | Unt | Notes ‘| t7a Setup Time, CADR[25:0], REG# Tsu-20 12 and CE[2:1]# before WE# Low Tsu=1~7Teye Programmable t7e Hold Time, CADR[25:0], REG# Thi-10 1,2 and CE[2:1}# after WE# High Thi=1~7Teyc Programmable [wee SSCS

17 Pulse Duration, WE# Low Tpw-20 1,2

Tpw=3~31Teye Programmable A {7d Setup Time, CDATAI15:0] before Tsu-20 1,2 WE# Low Tsu=1~7Teyc Programmable t7e Hold Time, CDATA[15:0] Thi-10 12 after WE# High Thi=1~7Teye Programmable [ware OSOSSSCCCOCOCOCTCCSCTCCCTCC~*Y t7t Hold Time, WE# Low Teyc+0 1 after WAIT# High 17g Valid Delay, WE# Low to WAIT# 50 Low Note1: Tcyc is PCICLK cycle time.( Typically 30ns ) Note2: Tsu, Tpw, Thl can be programmed by setting 16-bit Memory Timing 0 register. 16-bit Card Memory Write Timing CADR,REG#, X CE1#,CE2# {7a t7e t7b We# \\ le t7d t7e CDATA Data 17g , k t7t WaAIT# 16-bit Card Memory Write Timing RICOM ©1998 REV. 1.4 29

RL5C476A__PCI-CARDBUS BRIDGE DATA SHEET RICOH COMPANY, LTD. VO Read [symbor] Parameter [win ax [unt | Notes [_[caoesonnece SSSCSCSCSCSCSCSCSSSTTTCCC*‘(s 18a Setup Time, CADR[25:0] and Tsu-20 1,3 REG# before |ORD# Low Tsu=2~7Tcyc Programmable 18¢ Hold Time, CADR[25:0] and Thi-10 1.3 REG# after IORD # High Thi=1~7Teye Programmable 18b Pulse Duration, ORD # Low Tpw-20 1.3 Tpw=3~31Tcyc Programmable [eee SOSSCCCCCCST 18d Valid Delay, CADR[15:0] and 1Teyo-10 1 REG# to CE[2:1]# [—[ooarso. 18e Hold Time, CDATA[15:0] after ORD # High a 18f Hold Time, IORD # Low 1Teyc+0 1 after WAIT# High 18g Valid Delay, IORD # Low to WAIT# Low [Tose iY 18h Valid Delay, CADR[25:0] to lO1S16# Low a 18k Hold Time, INPCK# Low afterlORD# High 18) Valid Delay, ORD # Low to INPACK# Low Note1: Tcyc is PCICLK cycle time.( Typically 30ns ) Note3: Tsu, Tpw, Thl can be programmed by setting 16-bit I/O Timing 0 register. 30 REV. 1.4 RICOH ©1998

RL5C476A__PCI-CARDBUS BRIDGE DATA SHEET RICOH COMPANY, LTD. 16-bit Card /O Read Timing CADR X X 18d | CE1#,CE2# X X 48h 8h loisi6# WM I «2 tab te |ORD# \\ t8e DATA Coaa__) t8g , | tet WAIT# 8) | 18k INPACK# Data Latched 16-bit Card I/O Read Timing RICOM ©1998 REV. 1.4 31

RL5C476A_PCI-CARDBUS BRIDGE DATA SHEET RICOH COMPANY, LTD. VO Write [symbot | Parameter] min ax] unit [Notes 19a Setup Time, CADR[25:0], REG# Tsu-20 13 and CE[2:1]# before IOWR # Low Tsu=2~7Tcyc Programmable

19 Hold Time, CADR[25:0], REG# ‘Thi-10 1,3

and CE[2:1]}# after IOWR # High Thi=1~7Teyc Programmable t9b Pulse Duration, |OWR# Low ‘Tpw-20 1,3 Tpw=3~31Teye Programmable 19h Valid Delay, CADR[15:0] and 1Teyc-10 REG# to CE[2:1]# |_| coaratts:o] 19d Setup Time, CDATA[15:0] before | Tsu-2Tcyc-10 13 IOWR # Low Tsu=3~7Tcyc Programmable t9e Hold Time, CDATA[15:0] Thi-10 1,3 after IOWR # High Thi=1~7Teye Programmable 19f Hold Time, IOWR # Low 1Teyc+0 after WAIT# High 19g Valid Delay, IOWR # Low to WAIT# Low 19) Valid Delay, CADR[25:0] and REG# to |OIS16# Low Note1: Tcyc is PCICLK cycle time.( Typically 30ns ) Note3: Tsu, Tpw, Thl can be programmed by setting 16-bit I/O Timing 0 register. 32 REV. 1.4 RICOH ©1998

RL5C476A__PCI-CARDBUS BRIDGE DATA SHEET RICOH COMPANY, LTD. 16-bit Card /O Write Timing CADR,REG# X X 1a 1c «19h, CE1#,CE2# X 19) » le 19-5 loist6# J 19b lowr# \\ ol 4 . 19e CDATA X 19g of, 16-bit Card 1/O Write Timing RIGOM ©1998 REV. 1.4 33

RL5C476A__PCI-CARDBUS BRIDGE DATA SHEET RICOH COMPANY, LTD.

4.3.4 CardBus PC Card Interface Signals

RL5C476A__PCI-CARDBUS BRIDGE DATA SHEET RICOH COMPANY, LTD. Card Reset | Symbot | Parameter | min, | Max | unit | Notes Pes OOCOOSOCOSOSOCOCSCSCSCSC“‘“S‘“CS*SY [iia | Puce ovation caste J 1] im | SY re fsenger [ee CRST# Negation CardBus Reset Timing tila CRST# t1tb CCLK CardBus Reset Timing Card Output [symbor | Parameter] min max unit [Notes CADJ[31:0], CC/BE#[3:0], CPAR, CFRAME#,CDEVSEL#, CIRDY#, CTRDY#,CSTOP#, CBLOCK#, CPERR#, CSERR#, CCLKRUN#, CGNT# tla Valid delay time from CCLK 2 18 Min: CL=0 pF Max: CL=30 pF t12b Enable Time, Hi-Z to active delay from CCLK t12c Disable Time, Active to Hi-Z 28 delay from CCLK CardBus Interface Output Signals Timing 0.4Vec cCCLK 7 ff ‘ t12a(Min.) OUTPUT V 0.475Vee cen 0.8 25VEC > < t12a(Max.) t12b t120 CardBus Interface Output Signals Timing RIGOM ©1998 REV. 1.4 35

RL5C476A__PCI-CARDBUS BRIDGE DATA SHEET RICOH COMPANY, LTD. Card Input VCC_CORE=3.0~3.6V, VCC_SLOTA/B=3.0~3.6V, Ta=0~70°C} | Symbot | Parameter | Min, | Max | unit | Notes | | CAD[31:0], CC/BE#[3:0], CPAR, CFRAME#, CDEVSEL#, CIRDY#, CTRDY#.CSTOP#, CBLOCK# CPERR#, CSERR#, CCLKRUN#, CREQ# fermen TTT CCLK t13b Hold Time, Signal Hold Time after CCLK High CardBus Interface Input Signals Timing CLK 0.4Vee t13a 113b INPUT “V [~~ 0.475Vec y = = _0325Vce CardBus Input Signals Timing

4.3.5 Hardware Suspend mode

RL5C476A_PCI-CARDBUS BRIDGE DATA SHEET RICOH COMPANY, LTD.

5 MECHANICAL PACKAGE OUTLINE

5.1 208 pin LOFP 300.04 11810 2a.0yp 1 102typ ‘ 156 105, AAT AAA TTT =| = 08 UL BE |. ls oo & = NUNN AL 1 52 a 88 aE ly g gle 3/8 _,_ row s4 rls “ls feast 31g PF" alo www TT \\ 515 loser [aL aro] onto 0020.00 Reference wat UNIT: INCH RIEOkIo1998 REV. 1.4 37

The products and the product specifications described in this document are subject to change or discontinuation of production without notice for reasons such as improvement. Therefore, before deciding to use the products, please refer to Ricoh sales representatives for the latest information thereon. 2. This document may not be copied or otherwise reproduced in whole or in part without prior written consent of Ricoh. 3. Please be sure to take any necessary formalities under relevant laws or regulations before exporting or other- wise taking out of your country the products or the technical information described herein. 4. The technical information described in this document shows typical characteristics of and example application circuits for the products. The release of such information is not to be construed as a warranty of or a grant of license under Ricoh's or any third party's intellectual property rights or any other rights. 5. The products listed in this document are intended and designed for use as general electronic components in standard applications (office equipment, computer equipment, measuring instruments, consumer electronic products, amusement equipment etc.). Those customers intending to use a product in an application requiring extreme quality and reliability, for example, in a highly specific application where the failure or misoperation of the product could result in human injury or death (aircraft, spacevehicle, nuclear reactor control system, traffic control system, automotive and transportation equipment, combustion equipment, safety devices, life support system etc.) should first contact us. 6. We are making our continuous effort to improve the quality and reliability of our products, but semiconductor products are likely to fail with certain probability. In order prevent any injury to persons or damages to property resulting from such failure, customers should be careful enough to incorporate safety measures in their design, such as redundancy feature, fire-containment feature and fail-safe feature. We do not assume any liability or responsibility for any loss or damage arising from misuse or inappropriate use of the products. 7. Anti-radiation design is not implemented in the products described in this document. 8. Please contact Ricoh sales representatives should you have any questions or comments concerning the prod- ucts or the technical information. June 1995

Product Information

RL5C476A specifications and overview.

Summary

PCI-CARDBUS BRIDGE DATA SHEET

Description

PCI-CARDBUS BRIDGE DATA SHEET

Source title RL5C476A Datasheet(PDF) - RICOH electronics devices division

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