RHS0048A

DS15MB200_13 TI1 | Alldatasheet

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www.ti.com SNLS196E –NOVEMBER 2005–REVISED MARCH 2013 DS15MB200Dual1.5Gbps2:1/1:2LVDSMux/BufferwithPre-Emphasis Check forSamples: DS15MB200 1FEATURES DESCRIPTION The DS15MB200 isa dual-port2 to1 multiplexerand 2• 1.5Gbps Data Rate Per Channel 1 to 2 repeater/buffer.High-speeddata paths and• ConfigurableOff/OnPre-emphasis Drives flow-throughpinoutminimizeinternaldevicejitterandLossy Backplanes and Cables simplifyboard layout,whilepre-emphasisovercomes

• LVDS/BLVDS/CML/LVPECL Compatible Inputs, ISIjittereffectsfrom lossybackplanesand cables. The differentialinputsand outputsinterfacetoLVDSLVDS Compatible Outputs or Bus LVDS signalssuch as those on Texas• Low Output Skew and Jitter Instrument's10-,16-,and 18-bitBus LVDS SerDes,• On-chip 100Ω Inputand Output Termination ortoCML orLVPECL signals.
• 15 kV ESD Protectionon LVDS Inputs/Outputs The 3.3V supply,CMOS process,and robustI/O
• Hot Plug Protection ensurehighperformanceatlow power overtheentire industrial-40to+85°C temperaturerange.• Single3.3VSupply
• Industrial-40to+85°C Temperature Range
• 48-pinWQFN Package TypicalApplication Figure1. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2005–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

LI_0 SOA_0 SOB_0 SIA_0 SIB_0 MUX_S0 PREA_0 ENA_0 PREB_0 ENB_0 LO_0 PREL_0 ENL_0 DS15MB200 SNLS196E –NOVEMBER 2005–REVISED MARCH 2013 www.ti.com Block Diagram Figure2. PIN DESCRIPTIONS Pin WQFN Pin I/O,Type DescriptionName Number SWITCH SIDE DIFFERENTIAL INPUTS SIA_0+ 30 I,LVDS SwitchA-sideChannel0 invertingand non-invertingdifferentialinputs.LVDS, Bus LVDS, CML, or SIA_0− 29 LVPECL compatible. SIA_1+ 19 I,LVDS SwitchA-sideChannel1 invertingand non-invertingdifferentialinputs.LVDS, Bus LVDS, CML, or SIA_1− 20 LVPECL compatible. SIB_0+ 28 I,LVDS SwitchB-sideChannel0 invertingand non-invertingdifferentialinputs.LVDS, Bus LVDS, CML, or SIB_0− 27 LVPECL compatible. SIB_1+ 21 I,LVDS SwitchB-sideChannel1 invertingand non-invertingdifferentialinputs.LVDS, Bus LVDS, CML, or SIB_1− 22 LVPECL compatible. LINE SIDE DIFFERENTIAL INPUTS LI_0+ 40 I,LVDS Line-sideChannel0 invertingand non-invertingdifferentialinputs.LVDS, Bus LVDS, CML, or LI_0− 39 LVPECL compatible. LI_1+ 9 I,LVDS Line-sideChannel1 invertingand non-invertingdifferentialinputs.LVDS, Bus LVDS, CML, or LI_1− 10 LVPECL compatible. SWITCH SIDE DIFFERENTIAL OUTPUTS SOA_0+ 34 O, LVDS SwitchA-sideChannel0 invertingand non-invertingdifferentialoutputs.LVDS compatible(1)(2). SOA_0 − 33 SOA_1+ 15 O, LVDS SwitchA-sideChannel1 invertingand non-invertingdifferentialoutputs.LVDS compatible(1)(2). SOA_1 − 16 SOB_0+ 32 O, LVDS SwitchB-sideChannel0 invertingand non-invertingdifferentialoutputs.LVDS compatible(1)(2). SOB_0 − 31 SOB_1+ 17 O, LVDS SwitchB-sideChannel1 invertingand non-invertingdifferentialoutputs.LVDS compatible(1)(2). SOB_1 − 18 LINE SIDE DIFFERENTIAL OUTPUTS LO_0+ 42 O, LVDS Line-sideChannel0 invertingand non-invertingdifferentialoutputs.LVDS compatible(1)(2). LO_0 − 41 LO_1+ 7 O, LVDS Line-sideChannel1 invertingand non-invertingdifferentialoutputs.LVDS compatible(1)(2). LO_1 − 8 (1) ForinterfacingLVDS outputstoCML orLVPECL compatibleinputs,refertotheapplicationssectionofthisdatasheet(planned). (2) The LVDS outputsdo notsupporta multidrop(BLVDS) environment.The LVDS outputcharacteristicsoftheDS15MB200 devicehave been optimizedforpoint-to-pointbackplaneand cableapplications.

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ENL_0 PREL_0 VDD LO_0+ LO_0- LI_0+ LI_0- MUX_S0 VDD ENA_1 ENB_1 SOA_1+ SOA_1- SOB_1+ SOB_1- SIA_1+ SIA_1- SIB_1+ SIB_1- PREA_1 PREB_1 VDD MUX_S1 LI_1- LI_1+ LO_1- LO-1+ VDD PREL_1 ENL_1 GND VDD N/C 12 11 10 9 8 7 6 5 4 3 2 1PREB_0 PREA_0 SIB_0- SIB_0+ SIA_0- SIA_0+ SOB_0- SOB_0+ SOA_0- SOA_0+ ENB_0 ENA_0 25 26 27 28 29 30 31 32 33 34 35 36 DAP (GND) VDD GND VDD ENL_0 PREL_0 VDD LO_0+ LO_0- LI_0+ LI_0- MUX_S0 VDD ENA_1 ENB_1 SOA_1+ SOA_1- SOB_1+ SOB_1- SIA_1+ SIA_1- SIB_1+ SIB_1- PREA_1 PREB_1 VDD MUX_S1 LI_1- LI_1+ LO_1- LO-1+ VDD PREL_1 ENL_1 GND VDD N/C PREB_0 PREA_0 SIB_0- SIB_0+ SIA_0- SIA_0+ SOB_0- SOB_0+ SOA_0- SOA_0+ ENB_0 ENA_0 Channel 0 Channel 1 DS15MB200 www.ti.com SNLS196E –NOVEMBER 2005–REVISED MARCH 2013 PIN DESCRIPTIONS (continued) Pin WQFN Pin I/O,Type DescriptionName Number DIGITAL CONTROL INTERFACE MUX_S0 38 I,LVTTL Mux SelectControlInputs(perchannel)toselectwhichSwitch-sideinput,A orB,ispassed through MUX_S1 11 totheLine-side. PREA_0 26 I,LVTTL Outputpre-emphasiscontrolforSwitch-sideoutputs.Each outputdriveron theSwitchA-sideand B- PREA_1 23 sidehas a separatepintocontrolthepre-emphasison oroff. PREB_0 25 PREB_1 24 PREL_0 44 I,LVTTL Outputpre-emphasiscontrolforLine-sideoutputs.Each outputdriveron theLineA-sideand B-side PREL_1 5 has a separatepintocontrolthepre-emphasison oroff. ENA_0 36 I,LVTTL OutputEnableControlforSwitchA-sideand B-sideoutputs.Each outputdriveron theA-sideand ENA_1 13 B-sidehas a separateenablepin. ENB_0 35 ENB_1 14 ENL_0 45 I,LVTTL OutputEnableControlforThe Line-sideoutputs.Each outputdriveron theLine-sidehas a separate ENL_1 4 enablepin. POWER VDD 2,6,12, I,Power VDD = 3.3V±0.3V. 37,43,46, GND 3,47(3) I,Power Ground referenceforLVDS and CMOS circuitry. FortheWQFN package,theDAP isused as theprimaryGND connectiontothedevice.The DAP is theexposed metalcontactatthebottomoftheWQFN-48 package.Itshouldbe connectedtothe groundplanewithatleast4 viasforoptimalAC and thermalperformance. (3) Note thattheDAP on thebacksideoftheWQFN package istheprimaryGND connectionforthedevicewhen usingtheWQFN package. Connection Diagrams Figure3.WQFN Top View Figure4.DirectionalSignalPaths Top View DAP = GND (Refertopinnames forsignalpolarity) Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS15MB200

SNLS196E –NOVEMBER 2005–REVISED MARCH 2013 www.ti.com Output Characteristics The outputcharacteristicsof the DS15MB200 have been optimizedforpoint-to-pointbackplaneand cable applications,and arenotintendedformultipointormultidropsignaling. A 100Ω output(source)terminationresistorisincorporatedinthedevicetoeliminatetheneed foran external resistor,providingexcellentdrivecharacteristicsby locatingthe sourceterminationas closeto the outputas physicallypossible. Pre-Emphasis Controls The pre-emphasisisused tocompensate forlongor lossytransmissionmedia.Separatepinsare providedfor each outputto minimizepower consumption.Pre-emphasisis programmable to be offor on per the Pre- emphasisControlTable. PREx_n (1) Output Pre-Emphasis 0 0% 1 100% (1) AppliestoPREA_0, PREA_1, PREB_0, PREB_1, PREL_0, PREL_1 MultiplexerTruthTable(2)(3) Data Inputs ControlInputs Output SIA_0 SIB_0 MUX_S0 ENL_0 LO_0 X valid 0 1 SIB_0 valid X 1 1 SIA_0 X X X 0 Z (2) Same functionalityforchannel1 (3) X = Don 'tCare Z = HighImpedance (TRI-STATE) Repeater/BufferTruthTable(1)(2) Data Input ControlInputs Outputs LI_0 ENA_0 ENB_0 SOA_0 SOB_0 X 0 0 Z Z valid 0 1 Z LI_0 valid 1 0 LI_0 Z valid 1 1 LI_0 LI_0 (1) Same functionalityforchannel1 (2) X = Don 'tCare Z = HighImpedance (TRI-STATE) These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates.

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www.ti.com SNLS196E –NOVEMBER 2005–REVISED MARCH 2013 AbsoluteMaximum Ratings(1) Value Unit SupplyVoltage(VDD ) −0.3to+4.0 V CMOS InputVoltage -0.3to (VDD +0.3) V LVDS ReceiverInputVoltage(2) -0.3to (VDD +0.3) V LVDS DriverOutputVoltage -0.3to (VDD +0.3) V LVDS OutputShortCircuitCurrent +40 mA JunctionTemperature +150 °C StorageTemperature −65 to+150 °C Lead Temperature(Solder,4sec) 260 °C Max Pkg Power Capacity@ 25°C 5.2 W ThermalResistance(θJA) 24 °C/W Package Deratingabove +25°C 41.7 mW/ °C HBM, 1.5kΩ,100pF 8 kV LVDS pinstoGND only 15 kV ESD LastPassingVoltage EIAJ,0Ω,200pF 250 V CDM 1000 V (1) Absolutemaximum ratingsarethosevaluesbeyond whichdamage tothedevicemay occur.The databookspecificationsshouldbe met, withoutexception,toensurethatthesystemdesignisreliableoveritspower supply,temperature,and output/inputloadingvariables. Texas Instrumentsdoes notrecommend operationofproductsoutsideofrecommended operationconditions. (2) VID max < 2.4V Recommended OperatingConditions Min Max Unit SupplyVoltage(VCC ) 3.0 3.6 V InputVoltage(VI)(1) 0 VCC V OutputVoltage(VO ) 0 VCC V OperatingTemperature(TA)Industrial −40 +85 °C (1) VID max < 2.4V Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS15MB200

SNLS196E –NOVEMBER 2005–REVISED MARCH 2013 www.ti.com ElectricalCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherspecified. Symbol Parameter Conditions Min Typ (1) Max Units LVTTL DC SPECIFICATIONS (MUX_Sn, PREA_n, PREB_n, PREL_n, ENA_n, ENB_n, ENL_n) VIH HighLevelInputVoltage 2.0 VDD V VIL Low LevelInputVoltage GND 0.8 V IIH HighLevelInputCurrent VIN = VDD = VDDMAX −10 +10 µA IIHR HighLevelInputCurrent PREA_n, PREB_n, PREL_n 40 200 µA IIL Low LevelInputCurrent VIN = VSS ,VDD = VDDMAX −10 +10 µA C IN1 InputCapacitance Any DigitalInputPintoVSS 2.0 pF C OUT1 OutputCapacitance Any DigitalOutputPintoVSS 4.0 pF VCL InputClamp Voltage ICL = −18 mA −1.5 −0.8 V LVDS INPUT DC SPECIFICATIONS (SIA±,SIB±,LI±) VTH DifferentialInputHighThreshold(2) VCM = 0.8Vor1.2Vor3.55V, 0 100 mVVDD = 3.6V VTL DifferentialInputLow Threshold(2) VCM = 0.8Vor1.2Vor3.55V, −100 0 mVVDD = 3.6V VID DifferentialInputVoltage VCM = 0.8Vto3.55V,VDD = 3.6V 100 2400 mV VCMR Common Mode VoltageRange VID = 150 mV, VDD = 3.6V 0.05 3.55 V C IN2 InputCapacitance IN+ orIN− toVSS 2.0 pF IIN InputCurrent VIN = 3.6V,VDD = VDDMAX or0V −15 +15 µA VIN = 0V,VDD = VDDMAX or0V −15 +15 µA LVDS OUTPUT DC SPECIFICATIONS (SOA_n ±,SOB_n ±,LO_n ±) VOD DifferentialOutputVoltage, R L istheinternal100Ω between OUT+ 250 360 500 mV0% Pre-emphasis(2) and OUT − ΔVOD Change inVOD between -35 35 mVComplementaryStates VOS OffsetVoltage(3) 1.05 1.22 1.475 V ΔVOS Change inVOS between -35 35 mVComplementaryStates IOS OutputShortCircuitCurrent OUT+ orOUT − ShorttoGND −21 -40 mA C OUT2 OutputCapacitance OUT+ orOUT − toGND when TRI- 4.0 pFSTATE SUPPLY CURRENT (Static) ICC SupplyCurrent Allinputsand outputsenabledand active,terminatedwithexternalloadof 225 275 mA 100Ω between OUT+ and OUT-. ICCZ SupplyCurrent-Powerdown Mode ENA_0 = ENB_0 = ENL_0 = ENA_1 = 0.6 4.0 mAENB_1 = ENL_1 = L SWITCHING CHARACTERISTICS — LVDS OUTPUTS tLHT DifferentialLow toHighTransition Use an alternating1 and 0 patternat200 170 250 psTime Mb/s,measure between 20% and 80% of VOD .(4) tHLT DifferentialHightoLow Transition 170 250 psTime tPLHD DifferentialLow toHighPropagation Use an alternating1 and 0 patternat200 1.0 2.5 nsDelay Mb/s,measure at50% VOD between inputtooutput.tPHLD DifferentialHightoLow Propagation 1.0 2.5 nsDelay tSKD1 PulseSkew |tPLHD –tPHLD |(4) 25 75 ps tSKCC OutputChanneltoChannelSkew Differenceinpropagationdelay(tPLHD or 50 115 pstPHLD )among alloutputchannels.(4) (1) Typicalparametersaremeasured atVDD = 3.3V,TA = 25°C. They areforreferencepurposes,and arenotproduction-tested. (2) DifferentialoutputvoltageVOD isdefinedas ABS(OUT+ –OUT −).DifferentialinputvoltageVID isdefinedas ABS(IN+–IN−). (3) OutputoffsetvoltageVOS isdefinedas theaverageoftheLVDS single-endedoutputvoltagesatlogichighand logiclowstates. (4) Not productiontested.Guaranteedby statisticalanalysison a sample basisatthetimeofcharacterization.

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www.ti.com SNLS196E –NOVEMBER 2005–REVISED MARCH 2013 ElectricalCharacteristics(continued) Over recommended operatingsupplyand temperaturerangesunlessotherspecified. Symbol Parameter Conditions Min Typ (1) Max Units tJIT Jitter(0% Pre-emphasis)(5) RJ -Alternating1 and 0 at750MHz (6) 1.1 1.5 psrms DJ -K28.5Pattern,1.5Gbps (7) 20 34 psp-p TJ -PRBS 27-1Pattern,1.5Gbps (8) 14 28 psp-p tON LVDS OutputEnableTime Time fromENA_n, ENB_n, orENL_n to 0.5 1.5 µsOUT ± change fromTRI-STATE toactive. tON2 LVDS OutputEnableTime from Time fromENA_n, ENB_n, orENL_n to Powerdown Mode OUT ± change fromPowerdown Mode to 10 20 µs active. tOFF LVDS OutputDisableTime Time fromENA_n, ENB_n, orENL_n to OUT ± change fromactivetoTRI-STATE 12 ns orPowerdown mode. (5) Jitterisnotproductiontested,butguaranteedthroughcharacterizationon a sample basis. (6) Random Jitter,orRJ,ismeasured RMS witha histogramincluding1500 histogramwindow hits.The inputvoltage= VID = 500mV, 50% dutycycleat750MHz, tr = tf= 50ps (20% to80%). (7) DeterministicJitter,orD J,ismeasured toa histogrammean witha sample sizeof350 hits.Stimulusand fixturejitterhave been streamsof(00111110101100000101). (8) TotalJitter,orTJ,ismeasured peak topeak witha histogramincluding3500 window hits.Stimulusand fixturejitterhave been subtracted.The inputvoltage= VID = 500mV, 27-1PRBS patternat1.5Gbps, tr = tf= 50ps (20% to80%). Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS15MB200

TOTAL JITTER (ps) TEMPERATURE (°C) -40 1000 -20 20 40 60 80 POWER SUPPLY CURRENT (mA) 350 BIT DATA RATE (Mbps) 0 2000 100 150 200 500 1000 1500 250 300 PRE-EMPHASIS ON PRE-EMPHASIS OFF TOTAL JITTER (ps) BIT DATA RATE (Mbps) 0 2000 500 1000 1500 VCM = 3.0V VCM = 0.25V VCM = 1.2V DS15MB200 SNLS196E –NOVEMBER 2005–REVISED MARCH 2013 www.ti.com WQFN Performance Characteristics Power Supply Currentvs.BitData Rate TotalJittervs.BitData Rate Dynamic power supplycurrentwas measured withallchannels TotalJittermeasured at0V differentialwhilerunninga PRBS 27-1 patternwithone channelactive,allotherchannelsaredisabled.activeand togglingatthebitdatarate.Data patternhas no effect VDD = 3.3V,TA = +25°C, VID = 0.5V,pre-emphasisoff.on thepower consumption. VDD = 3.3V,TA = +25°C, VID = 0.5V,VCM = 1.2V Figure5. Figure6. TotalJittervs.Temperature TotalJittermeasured at0V differentialwhilerunninga PRBS 27-1patternwithone channelactive,allotherchannelsaredisabled.VDD = Figure7.

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150: 150: 50: 50: 15MB200 DS15MB200 www.ti.com SNLS196E –NOVEMBER 2005–REVISED MARCH 2013 TRI-STATE AND POWERDOWN MODES The DS15MB200 has outputenablecontrolon each ofthesixonboardLVDS outputdrivers.Thiscontrolallows each outputindividuallytobe placedina low power TRI-STATE mode whilethedeviceremainsactive,and is usefultoreducepower consumptionon unused channels.InTRI-STATE mode, some outputsmay remainactive whilesome areinTRI-STATE. When allsixoftheoutputenables(alldriverson bothchannels)aredeasserted(LOW), thenthedeviceentersa Powerdown mode thatconsumes only0.5mA (typical)of supplycurrent.In thismode, the entiredeviceis essentiallypowered off,includingallreceiverinputs,outputdriversand internalbandgap referencegenerators. When returningto activemode from Powerdown mode, thereisa delayuntilvaliddata ispresentedat the outputsbecause oftheramp topower up theinternalbandgap referencegenerators. Any singleoutputenablethatremainsactivewillholdthedeviceinactivemode even iftheotherfiveoutputsare inTRI-STATE. When inPowerdown mode, any outputenablethatbecomes activewillwake up the deviceback intoactive mode, even iftheotherfiveoutputsareinTRI-STATE. InputFailsafeBiasing Externalpullup and pulldown resistorsmay be used toprovideenough ofan offsettoenablean inputfailsafe under open-circuitconditions.ThisconfigurationtiesthepositiveLVDS inputpintoVDD thrua pullup resistor and the negativeLVDS inputpinistiedto GND by a pulldown resistor.The pullup and pulldown resistors shouldbe inthe 5kΩ to 15kΩ range to minimizeloadingand waveform distortionto the driver.The common- mode biaspointideallyshouldbe settoapproximately1.2V (lessthan1.75V)tobe compatiblewiththeinternal circuitry.Please referto applicationnote AN-1194, “FailsafeBiasingof LVDS Interfaces” (SNLA051 ) formore information. InterfacingLVPECL toLVDS An LVPECL driverconsistsofa differentialpairwithcoupledemittersconnectedtoGND viaa currentsource. This drivesa pairof emitter-followersthatrequirea 50 ohm to VCC -2.0load.A modern LVPECL driverwill typicallyincludetheterminationscheme withinthedevicefortheemitterfollower.Ifthedriverdoes notinclude theload,thenan externalscheme must be used.The 1.3V supplyisusuallynotreadilyavailableon a PCB, therefore,a loadscheme withouta uniquepower supplyrequirementmay be used. Figure8. DC Coupled LVPECL toLVDS Interface Figure8 isa separatedπ terminationscheme fora 3.3V LVPECL driver.R1 and R2 providesproperDC loadfor thedriveremitterfollowers,and may be includedas partofthedriverdevice(1).The DS15MB200 includesa 100 ohm inputterminationforthe transmissionline.The common mode voltagewillbe at the normal LVPECL levels– around 2 V. Thisscheme works wellwithLVDS receiversthathave rail-to-railcommon mode voltage, VCM ,range.Most Texas Instrument'sLVDS receivershave wideVCM range.The exceptionsarenotedindevices’ respectivedatasheets.Those LVDS devicesthatdo have a wide VCM range do not vary in performance significantlywhen receivinga signalwitha common mode otherthanstandardLVDS VCM of1.2V. (1) The biasnetworksshown above forLVPECL driversand receiversmay ormay notbe presentwithinthedriverdevice.The LVPECL driverand receiverspecificationmust be reviewedcloselytoensurecompatibilitybetween thedriverand receiverterminationsand common mode operatingranges. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS15MB200

50: 50: 50: 50: LVPECL VT LVPECL 150: 150: 50: 50: 15MB200 0.1 PF 0.1 PF DS15MB200 SNLS196E –NOVEMBER 2005–REVISED MARCH 2013 www.ti.com Figure9. AC Coupled LVPECL toLVDS Interface An AC coupledinterfaceispreferredwhen transmitterand receivergroundreferencesdiffermore than1 V. This isa likelyscenariowhen transmitterand receiverdevicesare on separatePCBs. Figure9 illustratesan AC coupledinterfacebetween a LVPECL driverand LVDS receiver.R1 and R2, ifnotpresentinthedriverdevice(2), provideDC loadfortheemitterfollowersand may range between 140-220 ohms formost LVPECL devicesfor thisparticularconfiguration.The DS15MB200 includesan internal100 ohm resistortoterminatethetransmission lineforminimalreflections.The signalafterAC couplingcapacitorswillswing around a levelsetby internal biasingresistors(i.e.fail-safe)which iseitherVDD /2or 0 V dependingon theactualfailsafeimplementation.If internalbiasingisnotimplemented,thesignalcommon mode voltagewillslowlywander toGND level. InterfacingLVDS toLVPECL An LVDS driverconsistsofa currentsource(nominal3.5mA) which drivesa CMOS differentialpair.Itneeds a differentialresistiveloadintherangeof70 to130 ohms togenerateLVDS levels.Ina system,theloadshould be selectedto match transmissionlinecharacteristicdifferentialimpedance so thatthe lineis properly terminated.The terminationresistorshould be placed as close to the receiverinputsas possible.When interfacingan LVDS driverwitha non-LVDS receiver,one onlyneeds tobiastheLVDS signalso thatitiswithin thecommon mode range ofthereceiver.Thismay be done by usingseparatebiasingvoltagewhich demands anotherpower supply.Some receivershave requiredbiasingvoltageavailableon-chip(VT,VTT orVBB ). Figure10. DC Coupled LVDS toLVPECL Interface Figure10 illustratesinterfacebetween an LVDS driverand a LVPECL witha VT pinavailable.R1 and R2, ifnot presentinthe receiver(2), provideproperresistiveloadforthe driverand terminationforthe transmissionline, and VT setsdesiredbiasforthereceiver. (2) The biasnetworksshown above forLVPECL driversand receiversmay ormay notbe presentwithinthedriverdevice.The LVPECL driverand receiverspecificationmust be reviewedcloselytoensurecompatibilitybetween thedriverand receiverterminationsand common mode operatingranges.

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130: 130: 50: 50: LVPECL VDD 83: 83: 0.1 PF 0.1 PF DS15MB200 www.ti.com SNLS196E –NOVEMBER 2005–REVISED MARCH 2013 Figure11. AC Coupled LVDS toLVPECL Interface Figure11 illustratesAC coupledinterfacebetween an LVDS driverand LVPECL receiverwithouta VT pin available.The resistorsR1, R2, R3, and R4, ifnot presentin the receiver(2), providea load forthe driver, terminatethetransmissionline,and biasthesignalforthereceiver. Packaging Information The LeadlessLeadframe Package (WQFN) isa leadframebased chipscalepackage (CSP) thatmay enhance chipspeed,reduce thermalimpedance,and reduce the printedcircuitboard area requiredformounting.The smallsizeand verylow profilemake thispackage idealforhighdensityPCBs used insmall-scaleelectronic applicationssuch as cellularphones,pagers,and handheldPDAs. The WQFN package isofferedinthe no Pullbackconfiguration.In the no Pullbackconfigurationthe standardsolderpads extendand terminateat the edge ofthepackage.Thisfeatureoffersa visiblesolderfilletafterboardmounting. The WQFN has thefollowingadvantages:

• Low thermalresistance
• Reduced electricalparasitics
• Improvedboardspace efficiency
• Reduced package height
• Reduced package mass For more detailsaboutWQFN packagingtechnology,refertoapplicationsnoteAN-1187, "LeadlessLeadframe Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:DS15MB200

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REVISION HISTORY

Changes from RevisionD (March 2013)toRevisionE Page

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www.ti.com 1-Nov-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DS15MB200TSQ NRND WQFN RHS 48 250 TBD Call TI Call TI -40 to 85 15M200 DS15MB200TSQ/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 15M200 DS15MB200TSQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 15M200 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

www.ti.com 1-Nov-2013 Addendum-Page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS15MB200TSQ WQFN RHS 48 250 213.0 191.0 55.0 DS15MB200TSQ/NOPB WQFN RHS 48 250 213.0 191.0 55.0 DS15MB200TSQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 Pack Materials-Page 2

www.ti.com SQA48A (Rev B)

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