RHRP6120CC INTERSIL | Alldatasheet

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Technical content

Features

  • Avalanche Energy Rated
  • Planar Construction

Applications

  • Switching Power Supplies
  • Power Switching Circuits
  • General Purpose Symbol Packaging JEDEC TO-220AB PACKAGE AVAILABILITY PART NUMBER PACKAGE BRAND RHRP6120CC TO-220AB RHR6120C NOTE: When ordering, use the entire part number. A 1 K A 2 ANODE 1 CATHODE (FLANGE) ANODE 2 CATHODE July 1996 File Number 4091.1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

Absolute Maximum Ratings (Per Leg)TC = +25oC, Unless Otherwise Specified RHRP6120CC UNITS TC = 130oC Square Wave, 20kHz 12 A Halfwave, 1 Phase, 60Hz 60 A CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications(Per Leg)TC = +25oC, Unless Otherwise Specified SYMBOL TEST CONDITION MIN TYP MAX UNITS VF IF = 6A, TC = +25oC - - 3.2 V IF = 6A, TC = +150oC - - 2.6 V IR VR = 1200V, TC = +25oC - - 100 µA VR = 1200V, TC = +150oC - - 500 µA tRR IF = 1A, dIF/dt = 200A/µs- - 5 5 n s IF = 6A, dIF/dt = 200A/µs- - 6 5 n s tA IF = 6A, dIF/dt = 200A/µs - 33 - ns tB IF = 6A, dIF/dt = 200A/µs - 22 - ns Q RR IF = 6A, dIF/dt = 200A/µs - 210 - nC C J VR = 10V, IF = 0A - 22 - pF R θJC --3 oC/W DEFINITIONS VF = Instantaneous forward voltage (pw = 300µs, D = 2%). IR = Instantaneous reverse current. tRR = Reverse recovery time (See Figure 9), summation of tA + tB. tA = Time to reach peak reverse current (See Figure 9). tB = Time from peak IRM to projected zero crossing of IRM based on a straight line from peak IRM through 25% of IRM (See Figure 9). Q RR = Reverse recovery charge. C J = Junction Capacitance. R θJC = Thermal resistance junction to case. EAVL = Controlled Avalanche Energy (See Figures 10 and 11). pw = pulse width. D = duty cycle. RHRP6120CC

FIGURE 7. TYPICAL JUNCTION CAPACITANCE vs REVERSE VOLTAGE FIGURE 8. tRR TEST CIRCUIT FIGURE 9. t RR WAVEFORMS AND DEFINITIONS FIGURE 10. AVALANCHE ENERGY TEST CIRCUIT FIGURE 11. AVALANCHE CURRENT AND VOLTAGE

0.25 IRM

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitewww.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 RHRP6120CC TO-220AB

3 LEAD JEDEC TO-220AB PLASTIC PACKAGE

EØP Q D H 1 L 60o b 1 2 3 e A c 45o D 1 A 1 TERM. 4 LEAD 2. CATHODE LEAD 3. ANODE 2 TERM. 4. CATHODE LEAD 1. ANODE 1 SYMBOL INCHES MILLIMETERS NOTESMIN MAX MIN MAX A 0.170 0.180 4.32 4.57 - A1 0.048 0.052 1.22 1.32 - b 0.030 0.034 0.77 0.86 3, 4 b1 0.045 0.055 1.15 1.39 2, 3 c 0.014 0.019 0.36 0.48 2, 3, 4 D 0.590 0.610 14.99 15.49 - D 1 - 0.160 - 4.06 - E 0.395 0.410 10.04 10.41 - e 0.100 TYP 2.54 TYP 5 e1 0.200 BSC 5.08 BSC 5 H 1 0.235 0.255 5.97 6.47 - J1 0.100 0.110 2.54 2.79 6 L 0.530 0.550 13.47 13.97 - L1 0.130 0.150 3.31 3.81 2 ØP 0.149 0.153 3.79 3.88 - Q 0.102 0.112 2.60 2.84 - NOTES: 1. These dimensions are within allowable dimensions of Rev. J of JEDEC TO-220AB outline dated 3-24-87. 2. Lead dimension and finish uncontrolled in L1. 3. Lead dimension (without solder). 4. Add typically 0.002 inches (0.05mm) for solder coating. 5. Position of lead to be measured 0.250 inches (6.35mm) from bot- tom of dimension D. 6. Position of lead to be measured 0.100 inches (2.54mm) from bot- tom of dimension D. 7. Controlling dimension: Inch. 8. Revision 1 dated 1-93.