RHP50000

RHP50000 Rev. A

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 33

Technical content

5.5V, 12.5A Synchronous Step-Down Silent Switcher 2 for Commercial Space Rev. A DOCUMENT FEEDBACK TECHNICAL SUPPORT © 2025 A n a l o g D e v i c e s , I n c . A l l r i g h t s r e s e r v e d .

FEATURES

 No Single-Event Latch-Up (SEL) up to 47.0 MeV·cm2/mg at VIN ≤ 3.6V  Total Ionizing Dose (TID) Assured up to 30krad(Si)  Silent Switcher®2 Architecture: Ultralow EMI Emissions  High Efficiency—4.5mΩ NMOS and 16mΩ PMOS  Wide Bandwidth, Fast Transient Response  Safely Tolerates Inductor Saturation in Overload  VIN Range: 2.25V to 5.5V  VOUT Range: 0.5V to VIN  VOUT Accuracy: ±1% with Remote Sense  Minimum On-Time: 35ns  Programmable Frequency to 5MHz  Shutdown Current: 1µA  Output Soft-Start with Voltage Tracking  Power Good Output  Die Temperature Monitor  Configurable for Paralleling Power Stages in Forced Continuous Mode  Thermally Enhanced 3mm × 3mm LQFN Package COMMERCIAL SPACE FEATURES  Supports Aerospace Applications  One Fabrication, Assembly, and Test Site  Wafer Diffusion Lot Traceability  Radiation Monitors  Single-Event Latch-Up (SEL)  Total Ionizing Dose (TID)  Gold (Au) Terminal Finish  Outgassing Characterization GENERAL DESCRIPTION The RHP50000-CSL is a very small, low noise, monolithic step-down DC/DC converter capable of providing up to 12.5A of output current from a 2.25V to 5.5V input supply. The device employs Silent Switcher 2 architecture with internal hot loop bypass capacitors to achieve both low EMI and high efficiency at switching frequencies as high as 5MHz. For systems with higher power requirements, multi -phasing parallel converters is readily implemented. The RHP50000 -CSL uses a constant frequency, peak current mode control architecture for fast transient response. A 500mV reference allows for low voltage outputs. 100% duty cycle operation delivers low drop out. Other features include a power good signal when the output is in regulation, precision enable threshold, output overvoltage protection, thermal shutdown, a temperature monitor, clock synchronization, mode selection and output short circuit protection. The device is available in a compact 18 -lead 3mm × 3mm LQFN package. Additional application and technical information can be found in the Commercial Space Products Program brochure.

APPLICATIONS

 Low Earth Orbit (LEO) Satellites  Avionics  Point-to-Point Communication Systems  Distributed DC Power Systems (Point-of-Load)  FPGA, ASIC, µP Core Supplies Analog Devices is in the process of updating documentation to provide culturally appropriate terminology and language. This is a process with a wide scope and will be phased in as quickly as possible. Thank you for your patience. TYPICAL APPLICATION 140kΩ 47µF 100kΩ VOUT 1.2V 12.5A6.8pF 274kΩ 22µF 22µF 0.1µF SW FB RT AGND EN ITH SSTT PGOOD MODE/SYNC 15kΩ 470pF VIN VIN 3.0V TO 5.5V PGND RHP50000-CSL 100nH 001 EFFICIENCY POWER LOSS VIN = 3.3V VOUT = 1.2V f = 2MHz ILOAD (A) 0 1 3 2 4 5 7 6 8 9 10 12 11 13 100 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 EFFICIENCY (%) POWER LOSS (W) 003

analog.com Rev. A 2 of 33 TABLE OF CONTENTS

Table 1. Electrical Characteristics

analog.com Rev. A 4 of 33 (Specifications are guaranteed over the -40°C to 125°C operating junction temperature (TJ) range, unless otherwise noted1. The same electrical characteristics apply to radiation tests and limits, tested at ambient temperature (TA) of 25°C. Total ionizing dose (TID) testing characterized up to 30krad(Si).) PARAMETER CONDITIONS COMMENTS MIN TYP MAX UNITS Feedback Voltage Line Regulation 2.5V ≤ VIN ≤ 5.0V TA = 25°C 0.002 0.025 %/V Feedback Pin Input Current VFB = 0.5V TA = 25°C ±20 nA Error Amp Transconductance TA = 25°C 1 mS Error Amp Sink/Source Current TA = 25°C ±45 µA Top Switch Current Limit VOUT/VIN ≤ 0.2, Current Out of SW 15 18 21 A Bottom Switch Current Limit (IVALLEY(MAX)) Current Out of SW 12 14 16 A Top Switch On-Resistance TA = 25°C 16 mΩ Bottom Switch On-Resistance TA = 25°C 4.5 mΩ SW Leakage Current VEN = 0.1V TA = 25°C ±100 nA VITH to IPEAK Current Gain TA = 25°C 26 A/V Minimum On-Time 35 60 ns Maximum Duty cycle 100 % Power Good/Soft-Start/Temp Monitor PGOOD Rising Threshold As a Percentage of the Regulated VOUT 97 98 99 % PGOOD Hysteresis 0.5 1 1.5 % Overvoltage Rising Threshold As a Percentage of the Regulated VOUT 105 110 115 % Overvoltage Hysteresis 1 2.5 3.5 % PGOOD Leakage Current VPGOOD = 5.5V TA = 25°C 20 nA PGOOD Pull Down Resistance VPGOOD = 0.1V TA = 25°C 12 20 Ω PGOOD Delay TA = 25°C 125 µs PGOOD Input Threshold Multi-Phase Mode, Rising 390 440 490 mV

analog.com Rev. A 5 of 33 (Specifications are guaranteed over the -40°C to 125°C operating junction temperature (TJ) range, unless otherwise noted1. The same electrical characteristics apply to radiation tests and limits, tested at ambient temperature (TA) of 25°C. Total ionizing dose (TID) testing characterized up to 30krad(Si).) PARAMETER CONDITIONS COMMENTS MIN TYP MAX UNITS PGOOD Input Hysteresis TA = 25°C 130 mV Soft-Start Charge Current VSSTT = 0.5V 7 10 13 µA Temp Monitor Slope TA = 25°C 4 mV/°C Oscillator Switching Frequency Range RT Programmable 0.5 5 MHz Switching Frequency RT = 274k 1.8 2 2.2 MHz Synchronization Frequency Range RT = VIN 0.5 2.25 MHz Default Frequency RT = VIN 1.8 2 2.2 MHz SYNC Level High on MODE/SYNC 1.2 V SYNC Level Low on MODE/SYNC 0.4 V Minimum MODE/SYNC Pulse Width TA = 25°C 40 ns MODE/SYNC Input Resistance TA = 25°C 200 kΩ MODE/SYNC No Clock Detect Time TA = 25°C 20 µs MODE/SYNC Clock Out Rise/Fall Time CMODE/SYNC = 50pF TA = 25°C 10 ns MODE/SYNC Clock Low Output Voltage IMODE/SYNC = 100µA TA = 25°C 0.2 V MODE/SYNC Clock High Output Voltage IMODE/SYNC = 100µA TA = 25°C VIN – 0.2 V MODE/SYNC Clock Out Duty Cycle TA = 25°C 50 % The RHP50000-CSL includes overtemperature protection which protects the device during momentary overload conditions. Junction temperatures will exceed 150°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. 2 If applying an input voltage > 3.6V, mitigation must be used to avoid SEL. 3 Supply current specification does not include switching currents. Actual supply currents will be higher.

Table 2. Absolute Maximum Ratings 1 If applying an input voltage > 3.6V, mitigation must be used to avoid SEL. extended periods may affect product reliability. condensable material (CVCM) of 0.10% have been used as screening levels for rejection of spacecraft materials. Table 3. Outgas Testing

Table 4. Radiation Features through the purchase order or contract. If applying an input voltage > 3.6V mitigation must be used to avoid SEL. beyond the report published on the web page.

Table 5. Pin Descriptions shutdown mode where all internal circuitry is disabled.

2 AGND

12 VIN

pins together to the inductor with short, wide traces.

analog.com Rev. A 9 of 33 PIN NAME DESCRIPTION

13 MODE/SYNC

The MODE/SYNC pin facilitates multiphase operation and synchronization to an external clock. Depending on the mode of operation, the MODE/ SYNC pin either accepts an input clock pulse or outputs a clock pulse at its operating frequency. (see Multiphase Operation in Applications Information). The MODE/SYNC pin also programs the mode of operation: pulse-skipping or forced continuous.

14 PGOOD

The PGOOD pin is a power good pin and is the open drain output of an internal comparator. The PGOOD output is pulled low when VIN is above 2.25V and the part is in shutdown. 15 RT The RT pin sets the oscillator frequency with an external resistor to AGND or sets the phasing for multiphase operation. (see Multiphase Operation in Applications Information).

16 SSTT

Soft-Start, Track, Temperature Monitor. An internal 10µA current into an external capacitor on the soft-start pin programs the output voltage ramp rate during start- up. During the soft-start cycle, the FB pin voltage will track the SSTT pin voltage. When the soft-start cycle is complete, the tracking function is disabled, the internal reference resumes control of the error amplifier and the SSTT pin servos to a voltage representative of junction temperature. For a clean recovery from an output short circuit condition, the SSTT pin is pulled down to approximately 140mV above the VFB voltage and a new soft-start cycle is initiated. During shutdown and fault conditions, the SSTT pin is pulled to ground. 17 ITH The ITH pin is the compensation node for the output voltage regulation control loop. Compensation components connected to this pin are referenced to AGND. 18 FB The output voltage feedback pin is externally connected to the output voltage via a resistive divider and is internally connected to the inverting input of the error amplifier. The RHP50000-CSL regulates the FB pin to 500mV. A phase lead capacitor connected between VFB and VOUT is used to optimize the transient response.

analog.com Rev. A 12 of 33 BLOCK DIAGRAM 0.55V 0.49V SENSE+ SENSE– FAULT FAULT 10µA RA RB CFF COUT VOUT VIN CIN 0.1µF RT RC CC CSS SW PGND FB AGND PGOOD VIN VIN ERROR AMP 0.5V 0.5V 0.55V 0.49V0.4V VTEMP OSCILLATOR S Q R SWITCH LOGIC AND ANTI-SHOOT THROUGH VIN SLOPE COMP INTERNAL REFERENCE MODE/SYNC RT EN ITH SSTT L 031

analog.com Rev. A 13 of 33 THEORY OF OPERATION Voltage Regulation The RHP50000 -CSL is a monolithic, constant frequency, current mode step -down DC/DC converter. An oscillator turns on the internal top power switch at the beginning of each clock cycle. Current in the inductor increases until the top switch current comparator trips and turns off the top power switch. The peak inductor current at which the top switch turns off is controlled by the voltage on the ITH node. The error amplifier servos the ITH node by comparing the voltage on the FB pin with an internal 500mV ref erence. When the load current increases, it causes a reduction in the feedback voltage relative to the reference leading the error amplifier to raise the ITH voltage until the average inductor current matches the new load current. When the top power switch turns off, the synchronous power switch turns on until the next clock cycle begins or, in pulse -skipping mode, inductor current falls to zero. If overload conditions result in excessive current flowing through the bottom switch, the next clock cycle will be delayed until switch current returns to a safe level. The output voltage is resistively divided externally to create a feedback voltage for the regulator. In high current operation, a ground offset may be present between the RHP50000 -CSL local ground and ground at the load. To overcome this offset, AGND shoul d have a Kelvin connection to the load ground, and the lowest potential node of the resistor divider should be connected to AGND. The internal error amplifier senses the difference between this feedback voltage and a 0.5V AGND referenced voltage. This sche me overcomes any ground offsets between local ground and remote output ground, resulting in a more accurate output voltage. The RHP50000 -CSL allows for remote output ground deviations as much as ±100mV with respect to local ground. If the EN pin is low, the RHP50000 -CSL is shut down and in a low quiescent current state. When the EN pin is above its threshold, the switching regulator will be enabled. The RHP50000 -CSL employs the second -generation Silent Switcher technology. This technology allows fast switching edges for high efficiency at high switching frequencies, while simultaneously achieving optimized EMI performance. Ceramic capacitors on VIN keep all the fast AC current loops small, improving EMI performance. Synchronizing the Oscillator to an External Clock The RHP50000-CSL’s internal oscillator is synchronized through an internal PLL circuit to an external frequency by applying a square wave clock signal to the MODE/ SYNC pin. During synchronization, the top power switch turn -on is locked to the rising edge of the external frequency source. While synchronizing, the switcher operates in forced continuous mode. The slope compensation is automatically adapted to the external clock frequency. After detecting an external clock on the first rising edge of the MODE/SYNC pin, the internal PLL gradually adjusts its operating frequency to match the frequency and phase of the signal on the MODE/SYNC pin. When the external clock is removed, the RHP50000-CSL detects the absence of the external clock within approximately 20µs. During this time, the PLL will continue to provide clock cycles. Once the external clock removal has been detected, the oscillator gradually adjusts its operating frequency back to the default frequency. Mode Selection The MODE/SYNC pin either synchronizes the switching frequency to an external clock, is a clock output, or sets the PWM mode. The PWM modes of operation are either pulse -skipping or forced continuous. See Table 9 in the Applications Information section. In pulse-skipping mode, switching cycles are skipped at light loads to regulate the output voltage. During forced continuous mode, the top switch turns on every cycle and light load regulation is achieved by allowing negative inductor current.

analog.com Rev. A 14 of 33 Output Power Good Comparators monitoring the FB pin voltage pull the PGOOD pin low if the output voltage varies from the nominal set point or if a fault condition is present. The comparator includes voltage hysteresis. A time delay to report PGOOD is used to filter short duration output voltage transients. Soft-Start/Tracking/Temperature Monitor The soft-start tracking function facilitates supply sequencing, limits V IN inrush current and reduces start -up output overshoot. When soft-starting is completed, the SSTT pin parks itself at a voltage representative of the RHP50000 - CSL die junction temperature. The SSTT capacitor is reset during shutdown, VIN UVLO and thermal shutdown. Dropout Operation As the input supply voltage approaches the output voltage, the duty cycle increases. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle, eventually reaching 100% duty cycle. The output voltage will then be d etermined by the input voltage minus the DC voltage drop across the internal main P-channel MOSFET and the inductor. In many designs when the input voltage approaches the output voltage, the amplitude of the output ripple voltage increases from its normally low value. To avoid any increase in output ripple voltage under these conditions, it is recommended to utilize a resistor divider on the EN input and limit the VIN turn-on and turn-off thresholds to where the output ripple voltage is acceptable for the given application. Operating Supply Voltage The RHP50000-CSL is designed to operate down to an input supply voltage of 2.25V. An important thermal design consideration is that the R DS(ON) of the power switches increase at low V IN. Calculate the worst -case RHP50000-CSL power dissipation and die junction temperature at the lowest input voltages. When the supply voltage is greater than 3.6V, mitigation must be applied to avoid single-event latch-up (SEL). Output Short-Circuit Protection and Recovery The peak inductor current level, at which the current comparator shuts off the top power switch, is controlled by the voltage on the ITH pin. If the output current increases, the error amplifier raises the ITH pin voltage until the average inductor current matches the load current. The RHP50000 -CSL clamps the maximum ITH pin voltage, thereby limiting the peak inductor current. When the output is shorted to ground, the inductor current decays very slowly during a single switching cycle because the voltage across the inductor is low. To keep the inductor current in control, a secondary limit is imposed on the valley of the inducto r current. If the inductor current measured through the bottom power switch is greater than the I VALLEY(MAX) the top power switch will be held off. Subsequent switching cycles will be skipped until the inductor current is reduced below IVALLEY(MAX). Recovery from an output short circuit goes through a soft -start cycle. When V OUT goes below regulation, as defined by the PGOOD threshold, the SSTT voltage is pulled to a voltage just above the FB voltage. Because the SSTT pin is pulled low, a soft-start cycle is initiated once the output short is removed.

analog.com Rev. A 15 of 33 APPLICATIONS INFORMATION See the Block Diagram for reference. FB Resistor Network The output voltage is programmed with a resistor divider between the output and the FB pin. Choose the resistor values according to Equation 1 as shown in Figure 27: RA = RB ( VOUT 500mV − 1) (1) Figure 27.Feedback Resistor Network Reference designators refer to the Block Diagram. 1% resistors are recommended to maintain output voltage accuracy. When optimizing the control loop for high bandwidth and optimal transient response, add a phase -lead capacitor connected from VOUT to FB. Operating Frequency Selection and Trade-Offs Selection of the operating frequency is a trade-off between efficiency, component size, transient response and input voltage range. The advantage of high frequency operation is that smaller inductor and capacitor values may be used. Higher switching frequencies allow for higher control loop bandwidth and, therefore, faster transient response. The disadvantages of higher switching frequ encies are lower efficiency, because of increased switching losses, and a smaller input voltage range, because of minimum switch on-time limitations. Although the maximum programmable switching frequency is 5MHz, the minimum on -time of the RHP50000 -CSL imposes a minimum operating duty cycle. The highest switching frequency (f SW(MAX)) for a given application can be calculated using Equation 2. fSW(MAX) = VOUT + VSW(BOT) tON(MIN)(VIN(MAX) − VSW(TOP) + VSW(BOT) (2) where VIN(MAX) is the maximum input voltage, V OUT is the output voltage, V SW(TOP) and VSW(BOT) are the internal switch drops and t ON(MIN) is the minimum top switch on -time. This equation shows that a slower switching frequency is necessary to accommodate a high VIN/VOUT ratio. The RHP50000-CSL is capable of a maximum duty cycle of 100%, therefore, the V IN-to-VOUT dropout is limited by the RDS(ON) of the top switch, the inductor DCR and the load current. COUTCFFRA VOUT FB BUCK SWITCHING REGULATOR (OPTIONAL) RB 032

to switch from 500kHz to 5MHz. Table 6 shows the necessary RT value for a desired switching frequency. The RT resistor required for a desired switching frequency is calculated using Equation 3. where RT is in kΩ and fSW is the desired switching frequency in MHz. Table 6. SW Frequency vs. RT Value external frequency applied to the MODE/SYNC pin. The synchronization frequency range is 0.5MHz to 2.25MHz. The third method of setting the RHP50000-CSL switching frequency is to use the internal nominal 2MHz default clock. See Table 7 for pin configuration. A good first choice for the inductor value is given by Equation 4 and Equation 5.

• (1 − VOUT VIN(MAX) ) for VOUT VIN(MAX) ≤ 0.5 (4) L ≈ 0.25 • VIN(MAX) 4A • fSW for VOUT VIN(MAX) > 0.5 (5) where fSW is the switching frequency in MHz, VIN is the input voltage, and L is the inductor value in μH.

analog.com Rev. A 17 of 33 To avoid overheating of the inductor, choose an inductor with an RMS current rating that is greater than the maximum expected output load of the application. Overload and short circuit conditions may need to be taken into consideration. In addition, the saturation current (I SAT) rating of the inductor must be higher than the load current plus 1/2 of the inductor ripple current: ISAT ≥ ILOAD(MAX) + 1 2 ∆IL (6) where I LOAD(MAX) is the maximum output load current for a given application and ΔIL is the inductor ripple current calculated using Equation 7. ∆IL = VOUT L • fSW

• (1 − VOUT VIN(MAX) ) (7) where VIN(MAX) is the maximum application input voltage. To keep the efficiency high, choose an inductor with the lowest series resistance (DCR). The core material should be intended for high frequency applications. The RHP50000-CSL limits the peak switch current in order to protect the switches and the system from overload faults. The inductor value must then be sufficiently large to supply the desired maximum output current, I OUT(MAX), which is a function of the switch current limit, ILIM, and the ripple current. IOUT(MAX) = ILIM − ∆IL (8) Therefore, the maximum output current that the RHP50000-CSL will deliver depends on the switch current limit, the inductor value, and the input and output voltages. The inductor value may have to be increased if the inductor ripple current does not allow s ufficient maximum output current (I OUT(MAX)) given the switching frequency, and maximum input voltage used in the desired application. Input Capacitors Bypass the input of the RHP50000 -CSL with at least two bulk storage ceramic capacitors close to the part, one on each side from VIN to PGND. These capacitors should be 0603 or 0805 in size. See Low EMI PCB Layout section for more detail. X7R or X5R capacitors are recommended for best performance across temperature and input voltage variations. Note that larger input capacitance is required when a lower switching frequency is used. For high frequency applications, adding two small capacitors close to the part is recommended. If the input power source has high impedance, or there is significant inductance due to long wires or cables, additional bulk capacitance may be necessary. A ceramic input capacitor combined with trace or cable inductance forms a high quality (under damped) tank circuit. If the RHP50000 -CSL circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possibly exceeding the RHP 50000-CSL’s voltage rating. This situation is easily avoided (see Analog Devices Application Note 88).

provide the best ripple performance. For good starting values, see the Typical Applications section. Applications for suggested capacitor values. The RHP50000-CSL is easily configurable for multiphase operation. See Table 7. MODE/SYNC pin to become clock output used to drive the MODE/SYNC pin of the secondary phase(s). external clock is unavailable, such as during start-up. communicate with the secondary phases on when start-up has been completed. Table 7. RHP50000-CSL Multiphase Configuration pin. Use of 1% resistors is recommended. See Table 8 for more information.

Table 8. RHP50000-CSL Programming Secondary Phase Angle When configured for primary/secondary operation, the secondary phases operate in forced-continuous modes. Figure 28. Phase Programming regulation at low currents is achieved by allowing negative inductor current. Switching cycles are not skipped. current is disallowed and regulation at low currents is achieved by skipping switching cycles. Table 9. RHP50000-CSL Single-Phase Configuration 2.25MHz range, an amplitude greater than 1.2V and less than 0.4V with a pulse width greater than 40ns. removed, the RHP50000-CSL will slowly transition back to the default frequency. MODE/SYNC pin to AGND allows the MODE/SYNC pin to be left floating.

analog.com Rev. A 20 of 33 Transient Response and Loop Compensation When determining the compensation components, CFF, RC, and CC, control loop stability and transient response are the two main considerations. The RHP50000 -CSL has been designed to operate at a high bandwidth for fast transient response capability. Operating at a high loop bandwidth reduces the output capacitance required to meet transient response requirements. Applying a load transient and monitoring the response of the system or using a network analyzer to measure the actual loop response are two ways to verify and optimize the control loop stability. When using the load transient response method to stabilize the control loop, apply an output current pulse of 20% to 100% of full load current having a rise time of 1µs. This will produce a transient on the output voltage and ITH pin waveforms. Switching regulators take multiple cycles to respond to a step in load current. When a load step occurs, V OUT is immediately perturbed, generating a feedback error signal used by the regulator to return V OUT to its steady -state value. During this recovery time, monitor V OUT for overshoot or ringing that would indicate a stability problem. The initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order overshoot/DC ratio cannot be used to determine phase margin. The gain of t he loop increases with the R C and the bandwidth of the loop increases with decreasing C C. If R C is increased by the same factor that C C is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. In addition, adding a feed forward capacitor, C FF, improves the high frequency response. Capacitor CFF provides phase lead by creating a high frequency zero with R A to improve the phase margin. The compensation components of the typical application circuits are a good starting point for component values. The output voltage settling behavior is related to the stability of the closed -loop system. For a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to Analog Devices Application Note 76. Output Overvoltage Protection During an output overvoltage event, when the FB pin voltage is greater than 110% of nominal, the RHP50000 -CSL top power switch will be turned off. If the output remains out of regulation for more than 100µs, the PGOOD pin will be pulled low. An output overvoltage event should not happen under normal operating conditions. Output Voltage Sensing The RHP50000-CSL AGND pin is the ground reference for the internal analog circuitry, including the bandgap voltage reference. To achieve good load regulation, connect the AGND pin to the negative terminal of the output capacitor (COUT) at the load. A drop in the high current power ground return path will be compensated. All of the signal components, such as the FB resistor dividers and softstart capacitor, should be referenced to the AGND node. The AGND node carries very little current and, therefore, can be a minimal size trace. See the Low EMI PCB Layout section for more information.

analog.com Rev. A 21 of 33 Enable Threshold Programming The RHP50000 -CSL has a precision threshold enable pin to enable or disable switching. When forced low, the RHP50000-CSL enters a low current shutdown mode. The rising threshold of the EN comparator is 400mV, with 60mV of hysteresis. Connect the EN pin to V IN if the shutdown feature is not used. Adding a resistor divider from VIN to EN programs RHP50000-CSL to regulate the output only when VIN is above a desired voltage (see the Block Diagram). Typically, this threshold, VIN(EN), is used in situations where the input supply is current limited or has a relatively high source resistance. A switching regulator draws constant power from the source, so source current increases as source voltage drops. This looks like a negative resistance load to the source and can cause the source to current limit or latch low under low source voltage conditions. The VIN(EN) threshold prevents the regulator from operating at source voltages where problems may occur. This threshold can be adjusted by setting the values R1 and R2 such that they satisfy the following equation: VIN(EN) = (R1 where the RHP50000-CSL will remain off until V IN is above VIN(EN). Due to the comparator’s hysteresis, switching will not stop until the input falls slightly below VIN(EN). Alternatively, a resistor divider from an output of another regulator to the enable pin of the RHP50000-CSL provides event-based power-up sequencing, enabling the RHP50000 -CSL when the output of the other regulator reaches a predetermined level. Output Voltage Tracking and Soft-Start The RHP50000-CSL allows the user to program its output voltage ramp rate by means of the SSTT pin. An internal 10μA pulls up the SSTT pin. Putting an external capacitor on SSTT enables soft-starting the output to prevent current surge on the input supply and output voltage overshoot. During the soft -start ramp, the output voltage will proportionally track the SSTT pin voltage. When the soft-start is complete, the pin will servo to a voltage proportional to the RHP50000-CSL junction temperature. See Figure 29 showing the SSTT pin operating range. The soft-start time is calculated as follows: tSS = CSS • 500mV 10μA (10) For output tracking applications, SSTT can be externally driven by another voltage source. From 0V to 0.5V, the SSTT voltage will override the internal 0.5V reference input to the error amplifier, thus regulating the FB pin voltage to that of SSTT pin. Whe n SSTT is above 0.5V, tracking is disabled and the feedback voltage will regulate to the internal reference voltage. An active pull-down circuit is connected to the SSTT pin to discharge the external soft -start capacitor in the case of fault conditions. The ramp will restart when the fault is cleared. Fault conditions that clear the soft -start capacitor are the EN/UV pin transitioning low, VIN voltage falling too low or thermal shutdown. Temperature Monitor Once the soft-start cycle has completed and the output power good flag thrown, the SSTT pin reports the die junction temperature. The RHP50000-CSL regulates the SSTT pin to a voltage proportional to the junction temperature. While reporting the temperature, the SSTT voltage is not valid below 1V. The junction temperature is calculated with Equation 11. TJ(°C) = VSSTT 4mV − 273 (11)

1. Measure the ambient temperature TA.
2. Measure the SSTT voltage while in pulse -skipping mode with the V OUT pulled up slightly higher than the
3. Calculate the slope of the temperature sensing circuit with Equation 12.
4. Calculate the junction temperature with the new calibrated slope.

Figure 29. Soft-Start and Temperature Monitor Operation pin is also actively pulled low during fault conditions: EN pin is low, VIN is too low or in thermal shutdown. For multiphase applications the PGOOD pin is used for communication between the primary and secondary phases. Connect the PGOOD pins together and pull-up to VIN or VOUT with an external resistor. top power switch will be held off and switching cycles will be skipped until the inductor current is reduced.

capacitors should be moved as close as to the VIN pin as possible. to be accurately regulated through remote differential sensing. See Figure 30 for a recommended PCB layout. Figure 30. Recommended PCB Layout for the RHP50000-CSL

analog.com Rev. A 24 of 33 Large, switched currents flow in the RHP50000 -CSL V IN, SW and PGND pins and the input capacitors. The loops formed by the input capacitors should be as small as possible by placing the capacitors adjacent to the VIN and PGND pins. Place the input capacitors, inductor and output capacitors on the same layer of the circuit board. Place a local, unbroken ground plane under the application circuit on the layer closest to the surface layer. The SW node should be as short as possible. Finally, keep the FB and RT nodes small and away from the noisy SW node. High Temperature Considerations For higher ambient temperatures, care should be taken in the layout of the PCB to ensure good heat sinking of the RHP50000-CSL. The PGND pins and the exposed pad on the bottom of the package should be soldered to a ground plane. This ground should be tied to large copper layers below with many thermal vias; these layers will spread heat dissipated by the RHP50000-CSL. Placing additional vias can reduce thermal resistance further. The maximum load current should be derated as the ambient temperature approaches the maximum junction rating. Power dissipation within the RHP50000-CSL can be estimated by calculating the total power loss from an efficiency measurement and subtracting the inductor loss. The die temperature is monitored with the SSTT pin.

Figure 31. Dual Phase 5V to 3.3V, 25A, Forced Continuous Mode

Figure 32. Three Phase, 0.6V, 37.5A, Forced Continuous Mode

Figure 33. Four Phase, 2MHz, 1.2V, 50A, Forced Continuous Mode

Figure 34. Four Phase, 2MHz, 1.2V, 50A Driven with External Clock, Forced Continuous Mode

analog.com Rev. A 31 of 33

ORDERING INFORMATION

Table 10. Product Ordering Guide Table 11. Evaluation Board Ordering Guide

PACKAGE INFORMATION

Table 12. Product Package Guide For the latest package outline information and land patterns (footprints), go to Package Index.

analog.com Rev. A 32 of 33

REVISION HISTORY

0 08/25 Initial release — A 08/25 Removed CSL from the part number 1–33

ALL INFORMATION CONTAINED HEREIN IS PROVIDED “AS IS” WITHOUT REPRESENTATION OR WARRANTY. NO RESPONSIBILITY IS ASSUMED BY ANALOG DEVICES FOR ITS USE, NOR FOR ANY INFRINGEMENTS OF PATENTS OR OTHER RIGHTS OF THIRD PARTIES THAT MAY RESULT FROM ITS USE. SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. NO LICE NCE, EITHER EXPRESSED OR IMPLIED, IS GRANTED UNDER ANY ADI PATENT RIGHT, COPYRIGHT, MASK WORK RIGHT, OR ANY OTHER ADI INTELLECTUAL PROPERTY RIGHT RELATING TO ANY COMBINATION, MACHINE, OR PROCESS, IN WHICH ADI PRODUCTS OR SERVICES ARE USED. TRADEMARKS AND REGISTERED TRADEMARKS ARE THE PROPERTY OF THEIR RESPECTIVE OWNERS. ALL ANALOG DEVICES PRODUCTS CONTAINED HEREIN ARE SUBJECT TO RELEASE AND AVAILABILITY. analog.com Rev. A 33 of 33