RH4Z2501

RH4Z2501 RENESAS | Alldatasheet

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 29

Technical content

Datasheet sections

• 1.1 Block Diagram
• 1.2 Ordering Information
• 1.3 Pin Configuration
• 1.4 Pin Description
• 1.5 Absolute Maximum Ratings
• 1.6 Thermal Information
• 1.7 Recommended Operating Conditions
• 1.8 Electrical Specifications
• 3.1 Linear Regulators
• 3.2 C/Q Driver
• 3.3 Receiver Threshold
• 3.4 Wake-Up Detection
• 3.5 Wake-Up Generation
• 3.6 Protection
• 4.1 OWI Protocol
• 4.2 OWI Commands Structure
• 5.1 IRQ_Status
• 5.2 Status
• 5.3 IRQ_Enable

Features

• Voltage supply range from 9V to 36V.
• Over-voltage peak robustness of ±60V.
• Configurable driver output current 50mADC to 400mADC.
• RDSON of less than 2.5Ω.
• Adjustable driver slew rate.
• Integrated Wake-up detection.
• MCU assisted Wake-up generation (typ. 700mA).
• OWI digital communication and calibration interface.
• Integrated Linear Voltage Regulators 3.3V and 5V.
• Ambient Temperature range -40°C to 125°C.
• Glitch filter for receiver.
• Integrated protection: o ±1.25kV/2.5A (peak) surge protection for L+, CQ, GND/L- (8/20 µs pulse acc. IEC 61000-4- 5). o Reverse polarity protection for L+, CQ, GND/L-
• On-chip diagnostics: o Over temperature detection. o Supply voltage monitor. o Broken chip detection. µC Sensor / Actuator V33 Power Management /WU TxD TxEN RxD OWI Driver Digital interface Receiver GND/L- C/Q VR Protection

Figure 1. Typical Application Diagram

1.1 Block Diagram

Figure 2. Block Diagram

1.2 Ordering Information

Table 1. Part Number Description

1.3 Pin Configuration

Figure 3. DFN 12 Pin Layout (Top View)

1.4 Pin Description

Table 2. Pin Description

1 A2 V5 5V Power supply input/output

5V must be present for normal operation. 2, 9 A3, D1, D2 GND/L- Ground Ground pins, all GND pins must be connected.

3 B3 V33 3V3 Power supply output

Add a 1µF blocking capacitor on this pin to GND. 4 C3 RxD Digital output C/Q receiver output (the default RxD is inverse of C/Q). 5 D3 TxD Digital input C/Q driver logic level (the default C/Q output level is inverse of TxD). 6 E3 TxEN Digital input C/Q driver enable input. Drive TxEN high to enable C/Q driver.

7 E2 OWI/DIAG Digital input/output

8 E1 /WU Digital input/output

10 C1, C2 C/Q Analog input/output

is by default the opposite of TxD. 11 B1, B2 L+ Supply voltage Power supply using a 100nF capacitor as close as possible to the pad. The pin is typically connected to the IO-link supply voltage. 12 A1 VR Analog output Regulator output. See section 3.1 for possible configurations. Pad to be used for heat dissipation and additional EMC robustness.

1.5 Absolute Maximum Ratings

Table 3. Absolute Maximum Ratings

1. CAUTION: Do not operate at or near the maximum ratings for extended periods of time. Exposure to such conditions can adversely

impact product reliability and result in failures not covered by warranty.

1.6 Thermal Information

Table 4. θJA According to Package

1. θJA is simulated under 125°C ambient temperature in free air with the component mounted on a high-effective thermal conductivity test

board. Used standard is JESD51-2A.

1. 3×2 thermal vias configuration used.
2. 3×5 thermal micro vias configuration used (one under each solder ball).

1.7 Recommended Operating Conditions

Table 5. Recommended Operating Conditions

1.8 Electrical Specifications

Table 6. Electrical Specification

1 For the 50mA range the lower limit is 90%

R36DS0032ED0100 Rev. 1.3 Dec.11.24 Page 9 Symbol Parameter Conditions Minimum Typical Maximum Units C/Q Receiver VIN Input voltage range VL+-36V 36V V VTH Input high threshold L+ >= 18V 11 11.8 12.5 V L+ < 18V 60 72 80 % of L+ VTL Input low threshold L+ >= 18V 9 9.8 10.5 V L+ < 18V 50 60 68 % of L+ VHYST Input hysteresis L+ >= 18V 2 V L+ < 18V 12 % of L+ Input capacitance Driver disabled f = 100kHz 200 pF L-H propagation delay AFilter = 0, DFilter = off 180 300 ns AFilter = 1, DFilter = off 570 1000 ns H-L propagation delay AFilter = 0, DFilter = off 250 400 ns AFilter = 1, DFilter = off 690 1000 ns Receiver skew AFilter = 0, DFilter = off 50 ns AFilter = 1, DFilter = off 100 ns /WU Detection TWU_MIN Wake-up min pulse width CLOAD = 3nF 45 75 µs TWU_MAX Wake-up max pulse width CLOAD = 3nF 85 115 µs Thermal Management Thermal shutdown Temperature rising 165 °C Temperature falling 150 °C Thermal warning Temperature rising 140 °C Temperature falling 125 °C Pads VIO IO-Voltage 2.97 3.3 5.5 V VIL Logic input voltage low TxEN, TxD, /WU, OWI 0.25×VIO V VIH Logic input voltage high TxEN, TxD, /WU, OWI 0.75×VIO V RPD_Tx Input leakage TxEN, TxD 70 100 130 kΩ VOL Output voltage low IOUT = -4mA (RxD, /WU) 0.4 V VOH Output voltage high IOUT = 4mA (RxD) VIO-0.6 V RPU_WU Pull-up resistance /WU pad 5 10 kΩ VOL Output voltage low IOUT = -1.5 mA (OWI) 0.6 V RPU_OWI Pull-up resistance OWI 10 15 20 kΩ IMax_OWI Max output current OWI 2 6 mA OWI timing tOWI_START Minimum TLOW time to detect a start condition 4 µs tOWI_BIT OWI bit time 15 11114 µs tOWI_0 Duty ratio bit ‘0’ 0.125 0.25 0.375 tOWI_BIT tOWI_1 Duty ratio bit ‘1’ 0.625 0.75 0.875 tOWI_BIT tOWI_STOP Hold time STOP condition tOWI_BIT_L is the bit period of the last valid bit 3 250 tOWI_BIT_L tOWI_BIT_DEV Bit time deviation Duration of most recent bit versus previous bit duration 0.5 1.0 2.0 tOWI_BIT ESD tolerance ESD protection (L+, CQ) IEC-61000-4-2- contact discharge +/-4 kV HBM (Human Body Model) +/-4 kV ESD protection all pins HBM (Human Body Model) +/-2 kV CDM (Charged Device Model) +/-750 V Surge protection (L+, CQ, GND) IEC 61000-4-5, 500Ω, 8/20µs surge +/-1.25 kV 1. All devices 100% production tested at TA = +25ºC. Limits over operating temperature range are guaranteed by design. 2. Currents out of the device are negative. Currents into the device are positive. 3. Not production tested. Guaranteed by design.

Figure 15. V33 Load Regulation Figure 16. V33 Output Voltage vs. Temperature

3.1 Linear Regulators

There are different configuration options to generate the 5V supply. The device is equipped with two internal LDOs that are able to generate both 5V and 3.3V rails. Figure 17. Internal V5 LDO Figure 18. External NPN Transistor Using an external NPN transistor improves thermal performance of the device allowing a higher current supply. Make sure to place a diode on the collector of the NPN transistor to ensure the reverse polarity protection.

Figure 19. External DC-DC Regulator The 3.3V regulator defines the logic level. Connect the V33 pin with the V5 pin to operate at 5V logic levels. smaller than the package can dissipate. Total power dissipation for the device is calculated using the equations displayed in Table 7. Table 7. Power Dissipation Equations 2 × Ron PCQ is the power generated in the C/Q driver. PV5 = (VL+ – 5V) × IV5 PV5 is the power generated by the 5V LDO. PV33 = 1.7V × IV33 PV33 is the power generated by the 3.3V LDO. but including switching current consumption. PTOTAL = PCQ + PV5 + PV33 + PDev + PPU/PD PTOTAL is the sum of the above calculated powers.

3.2 C/Q Driver

The C/Q driver is enabled when TxEN is set to ‘High’ and disabled when it is set to ‘Low’. Table 8 lists the C/Q driver output modes according to TxEN and TxD signals. Table 8. C/Q Driver Output Modes

1. X = Not to be considered, Z = High impedance; H = High, L = Low

R36DS0032ED0100 Rev. 1.3 Dec.11.24 Page 14 3.2.2. Overcurrent Protection The C/Q driver can sense an overload condition. If an overload situation occurs (either high side or low side drivers) and remains for longer than the blanking time (“blankTim”), a driver fault condition is detected, resulting in overload (“overLoad") and interrupt (“overLoadInt”) status bits being set. If the auto-retry bit (“autoRetryEn”) is enabled (default):

• The C/Q driver is disabled for the duration of the auto-retry off time (“autoRetryTim”). After this time, the driver is automatically re-enabled. If the overload condition remains for longer than the blanking time, the C/Q driver stays disabled and the auto-retry timer restarts.
• The “overLoad" status bit is set if the overload condition remains for longer than the blanking time and remains set during the auto-retry off time.
• The driver is re-enabled once the “overLoad" status bit is cleared for longer than the blanking time indicating that the overload situation is gone. The overload status is re-checked at either of the following cases: o The driver is disabled again, and the “overLoad" status bit remains set. o The driver stays enabled and the “overLoad" status bit is cleared. The intention is to avoid permanent toggling of the “overLoad" status bit. If the auto-retry bit (“autoRetryEn”) is disabled:
• The C/Q driver remains active until a thermal shutdown event occurs.
• The status bit is set after the blanking time. The status bit is cleared when the overload condition is gone. Overload can only occur when TxE N is ‘High’ and “disCShut” bit is set to 0. When TxEN is ‘Low’ (receive only mode) or “disCShut” is 1, the Overload bit and lock condition is cleared. 3.2.3. Low Voltage Detection 3.2.3.1. Under-Voltage Warning The IC returns a warning if a low voltage condition is detected at the L+ pin. When the L+ supply voltage drops below the warning voltage, the following bits are set:
• The under-voltage warning interrupt “uvWarnInt” (if enabled) is raised.
• the under-voltage warning status bit “uvWarn” is set. This status bit is cleared once the L+ voltage rises above the warning release threshold voltage. 3.2.3.2. Under-Voltage Shutdown The C/Q driver automatically switches off if the L+ supply drops below the shutdown voltage. When the L+ supply voltage drops below the shutdown voltage, the following bits are set:
• The shutdown interrupt “uvShutInt “(if enabled) is raised.
• the Shutdown status bit “cqShut” is set (under-voltage warning bit remains set).
• the C/Q driver switches off. The driver is enabled and status bit is cleared when the L+ Voltage rises above the shutdown voltage. 3.2.4. Thermal Protection A thermal warning is generated if the device exceeds 140°C. The “TempWarn” bit in the status register bit is cleared when the temperature drops below 125°C. The device continues to operate up to 165°C, above that the device’s driver is disabled. A temperature drops of 15°C enables the driver to operate again.

3.3 Receiver Threshold

are calculated according to an L+ ratio (refer to VTH and VTL values in Table 6).

3.4 Wake-Up Detection

• A current overload (either of High side driver or Low side driver) in the driver output for a certain period.
• A contradiction of the TxD and RxD lines of the device between TWU_MIN and TWU_MAX period (Master pull- down, Slave driver high-Z) when transmitter is enabled The IC configuration register (“wuMode”) defines if “overload”, “contradiction”, or both events are chosen for the WURQ detection. If a WURQ is detected, the /WU pin is pulled low until TxEN is released. The wake-up prevention logic avoids generating false wake-up alarms, which can occur when larger capacitances are connected on the /CQ pin. After TxD toggle or driver enable, the Wake-up signal generation is prevented for the duration of the blanking time.

3.5 Wake-Up Generation

power mode) and activating TxEN for 80µs with TxD in the opposite direction of RxD.

• The /WU pin is an input with activated pull-up resistor.
• When the /WU pin is pulled to low the driver is switched to high power mode and fastest slew-rate, a current >600mA is applied when TxEN is enabled. Figure 20 displays how to generate a Wake-Up pulse (masterMode bit set to 1). /WU RxD TxD TxEN 80µs TxD to be set to the opposite of RxD

Figure 20. /WU Signal Procedure OWI/DIAG pin can be used if sparing 1 GPIO of the external MCU is needed.

3.6 Protection

of these pins with positive or negative surge voltage. L+, C/Q, and L- pins. The maximum voltage between any of the pins must not exceed ± 60V DC. conductivity of that metal wire is checked via a dedicated circuitry by its diagnostic function, see Table 11. information. It combines a simple and easy protocol adaptation with a cost-saving pin sharing.

• When DIAG output is asserted, disable the OWI communication.
• The DIAG output can only indicate an interrupt when OWI is in idle mode. If OWI communication is used, the DIAG signal is delayed until OWI returns to idle.

4.1 OWI Protocol

• Idle state During inactivity of the bus, the OWI line is pulled up to the IO supply voltage VIO by an internal resistor.
• Start condition When the OWI line is in idle mode, a ‘Low’ pulse with a minimum width of tOWI_START ≥ 4μs followed by a ‘High’ indicates a start condition. Every request must be initiated by a start condition sent by the OWI master. A master can generate a start condition only when the OWI line is in idle mode.
• Valid data Data is transmitted in bytes (8 bits) starting with the most significant bit (MSB). Transmitted bits are recognized after a start condition at every transition from ‘Low’ to ‘High’ at the OWI line. The value of the transmitted bit depends on the duty ratio between the high phase and the ‘High’/’Low’ period (bit period, tOWI_BIT). A duty ratio greater than 1/8 and less than 3/8 is detected as 0; a duty ratio greater than 5/8 and less than 7/8 is detected as 1. The bit period of consecutive bits must not increase to more than 1.5 times the previous bit period or decrease to less than half of the previous bit period otherwise it is detected as a stop condition. OWI protocol timing and parameters are specified in Figure 21 and Table 6.

Figure 21. OWI Timing Diagram

4.2 OWI Commands Structure

There is an automatic increment of address pointer to write multiple registers in a short time period. Figure 22. OWI Command Request

Table 9. Register Mapping

5.1 IRQ_Status

The register bits are set by an interrupt event. The content of this register stays until the register is read. Table 10. Register IRQ_Status Description

• 1: The voltage on L+ fell below shutdown threshold since the last register read.
• 0: The voltage on L+ stayed above shutdown threshold. 6 thShutInt Thermal shutdown interrupt
• 1: The junction temperature exceeded thermal shutdown threshold since the last register read.
• 0: No thermal shutdown occurred. 5 thWarnInt Thermal warning interrupt
• 1: The junction temperature exceeded thermal warning threshold since the last register read.
• 0: No thermal warning occurred. 4 uvWarnInt Under-voltage warning interrupt
• 1: The voltage on L+ happened to fall below under-voltage warning threshold since the last register read.
• 0: The voltage on L+ stayed above under-voltage warning threshold 3 ovWarnInt Over-voltage warning interrupt
• 1: The voltage on L+ exceeded over-voltage warning threshold since the last register read.
• 0: The voltage on L+ stayed below over-voltage warning threshold. 2 wurqInt Wake-up interrupt

• 1: A wake-up event was detected since the last register read.
• 0: No wake-up event detected. 1 overLoadInt Overload interrupt
• 1: The C/Q driver current exceeded the overload condition longer than the blanking time since last register read.
• 0: The C/Q driver current stayed within the limits. 0 porInt Power-on reset (not mask able)
• 1: A power-on reset happened since the last readout.
• 0: No power-on reset happened.

5.2 Status

The register bits shows the current status of the device. This register is read-only. Table 11. Register Status Description 7 cqLogic Logic level on RxD pin.

• 1: RxD pin is high.
• 0: RxD pin is low. 6 cqShut C/Q driver in shutdown (thermal or under-voltage shutdown condition).
• 1: Shutdown due to under-voltage condition or thermal temperature exceeding limit.
• 0: C/Q driver not in shutdown. 5 thWarn Thermal warning.
• 1: The junction temperature exceeded the thermal warning threshold.
• 0: The temperature is below the thermal warning condition. 4 uvWarn Under-voltage warning.
• 1: The voltage on L+ is below under-voltage warning threshold.
• 0: The voltage on L+ is above under-voltage warning threshold. 3 ovWarn Over-voltage warning
• 1: The voltage on L+ is above over-voltage warning threshold.
• 0: The voltage on L+ is below over-voltage warning threshold. 2 wurq Wake-up signal
• 1: A wake-up event was detected. This bit is cleared when TxEN is low.
• 0: No wake-up event detected. 1 overLoad Overload detected.
• 1: The C/Q driver is in overload condition.
• 0: The C/Q driver is within the limits. 0 bcc Broken chip information (bit is set/cleared in the start-up phase)
• 0: Device satisfactory.

R36DS0032ED0100 Rev. 1.3 Dec.11.24 Page 21

5.3 IRQ_Enable

The register bits enable or mask interrupt events. Table 12. Register IRQ_Enable Description

Description

(Bold font indicates the default setting) 7 uvShutIntEn Under-voltage shutdown interrupt enable.

• 1: Interrupt signaling of under-voltage shutdown on OWI/DIAG pin is enabled.
• 0: OWI/DIAG pin does not signal an under-voltage shutdown condition. 6 thShutIntEn Thermal shutdown interrupt enable.
• 1: Interrupt signaling of thermal shutdown on OWI/DIAG pin is enabled.
• 0: OWI/DIAG pin does not signal a thermal shutdown condition. 5 thWarnIntEn Thermal warning interrupt enable.
• 1: Interrupt signaling of thermal warning on OWI/DIAG pin is enabled.
• 0: OWI/DIAG pin does not signal a thermal warning condition. 4 uvWarnIntEn Under-voltage warning interrupt enable.
• 1: Interrupt signaling of under-voltage warning on OWI/DIAG pin is enabled.
• 0: OWI/DIAG pin does not signal an under-voltage warning condition. 3 ovWarnIntEn Over-voltage warning interrupt enable.
• 1: Interrupt signaling of over-voltage warning on OWI/DIAG pin is enabled.
• 0: OWI/DIAG pin does not signal an over-voltage warning condition. 2 wurqIntEn Wake-up interrupt enable.
• 1: Interrupt signaling of a wake-up detection on OWI/DIAG pin is enabled.
• 0: OWI/DIAG pin does not signal a wake-up detection. 1 overLoadIntEn Overload interrupt enable.
• 1: Interrupt signaling of an overload condition on OWI/DIAG pin is enabled.
• 0: OWI/DIAG pin does not signal an overload condition.

0 Reserved Not used

R36DS0032ED0100 Rev. 1.3 Dec.11.24 Page 22 5.4 comParam The register bits configure the driver parameters. Table 13. Register comParam Description (Bold font indicates the default setting) 7 slewRateEn Enable slew rate.

• 1: Slew rate is regulated.
• 0: Slew rate regulation is disabled. 6 slewRate Value of slew rate (default 120V/µs).
• 000: 20V/µs
• 001: 30V/µs
• 010: 40V/µs
• 011: 60V/µs
• 100: 80V/µs
• 101: 100V/µs
• 110: 120V/µs (default)
• 111: 140V/µs

3 Reserved 0

2 currLim Value of current limit.

• 000: 50mA
• 001: 100mA
• 010: 150mA
• 011: 200mA (default)
• 100: 250mA
• 101: 300mA
• 110: 350mA
• 111: 400mA

R36DS0032ED0100 Rev. 1.3 Dec.11.24 Page 23 5.5 comCtrl1 The register bits configure the transceiver parameters. Table 14. Register comCtrl1 Description (Bold font indicates the default setting) 7 digFiltSel Digital deglitch filter.

• 00: Disable digital filter function.
• 01: Digital 200ns filter (COM3).
• 10: Digital 1.6µs filter (COM2).
• 11: Digital 13µs filter (COM1). 5 anaFiltEn Analog (slow) deglitch filter.
• 1: Enable filter function.
• 0: Disabled filter function. 4 cqInvert C/Q Invert enable/disable.
• 1: The C/Q driver logic follows the TX input logic (if driver is enabled). RX logic follows the C/Q driver/receiver logic.
• 0: The C/Q driver logic is the inverse of the TX input logic (if driver is enabled). RX logic is the inverse of the C/Q driver/receiver logic. 3 pullUpEn Weak Pull-up current source.
• 0: No pull-up current source.
• 1: A pull-up current source is activated on CQ pin. 2 pullDownEn Weak pull-down current source.
• 0: No pull-down current source.
• 1: A pull-down current sink is activated on CQ pin. 1 lshsEn C/Q Driver mode
• 00: C/Q driver is disabled regardless of TxEN, the driver is high impedance.
• 01: PNP operation.
• 10: NPN operation.
• 11: Push-Pull mode.

R36DS0032ED0100 Rev. 1.3 Dec.11.24 Page 24 5.6 comCtrl2 The register bits configure the transceiver parameters. Table 15. Register comCtrl2 Description (Bold font indicates the default setting) 7 swRst Software reset

• 1: Trigger a reset, all registers are set to their default state. Status is cleared, IRQ is de-asserted.
• 0: Normal operation. 6 autoRetryEn Auto-retry enable
• 1: Fixed off-time functionality is enabled. C/Q driver is disabled for a fixed time after an overcurrent or thermal fault occurs. The driver is re-enabled automatically after the fixed off- delay.
• 0: Fixed off-time functionality is disabled. The driver is re-enabled after temperature falls below the thermal hysteresis. 5 autoRetryTim Auto-retry fixed off-time Set the autoRetryTim to select the fixed driver off-time after a fault was generated when auto-retry functionality is enabled (autoRetryEn = 1). The driver is re-enabled automatically after the fixed off-delay.
• 00: Fixed off-time is 50ms.
• 01: Fixed off-time is 100ms.
• 10: Fixed off-time is 200ms.
• 11: Fixed off-time is 500ms. 3 blankTim Blanking time Minimum blanking time to signal a current limit.
• 00: 128µs.
• 01: 500µs.
• 10: 1ms.
• 11: 5ms. 1 wuMode Wake-up detection Turn on both OVL and RX/TX wakeup detection mechanisms (wuMode = 11) for stable Wakeup detection.
• 00: No Wake-up detection.
• 01: Enable Wake-up detection by OVL condition.
• 10: Enable Wake-up detection by RX/TX mismatch.
• 11: Enable Wake-up detection by OVL condition or RX/TX mismatch.

R36DS0032ED0100 Rev. 1.3 Dec.11.24 Page 25 5.7 alarm The register bits configure the transceiver parameters. Table 16. Register Alarm Description (Bold font indicates the default setting) 7 reserved Set to 0 6 disSurgeProt Surge protection.

• 1: Surge protection disabled.
• 0: Surge protection enabled. 5 reserved Set to 0 4 disDebounce Debouncing filter for thermal and voltage monitor.
• 1: Debouncing filter disabled.
• 0: Debouncing filter enabled. 3 disLDO Disable 3.3V LDO.
• 1: 3.3V LDO disabled.
• 0: 3.3V LDO enabled. 2 disCShut Disable driver detection&shutdown of driver in overload condition.
• 1: Driver shut-down disabled.
• 0: Driver shut-down enabled/possible. 1 disTShut Disable shut-down of driver for over-temperature condition.
• 1: Thermal shut-down disabled.
• 0: Thermal shut-down enabled/possible. 0 disVShut Disable shut-down of driver for under-voltage condition
• 1: Under-voltage shut-down disabled.
• 0: Under-voltage shut-down enabled/possible.

5.8 Master

The register bits configure the transmitter for master mode operation. Table 17. Register Master Description

7 Reserved

6 Reserved

5 Reserved

4 Reserved

3 Reserved

2 CurrSinkSel • 00: No current sink.

• 01: 3mA current sink.
• 10: 6mA current sink.
• 11: 9mA current sink. 0 MasterMode Set the device to master mode.
• 1: the device is able to generate a wake-up pulse. A low on WU pin sets highest slew rate and min 500mA current; TxD defines high side or low side driver; TxEN controls the pulse length.
• 0: /WU pin is used as output to signal a wake-up pulse detection. 6. Package Outline Drawings The package outline drawings are available below:

6.1 DFN12

R36DS0032ED0100 Rev. 1.3 Dec.11.24 Page 27 7. Glossary Term Definition ADC Analog to Digital Converter C/Q connection for communication (C) or switching (Q) CRC Cyclic Redundancy Check DC Direct Current DC-DC Direct Current to Direct Current DFN Dual Flat no Leads Package ESD Electro-Static Discharge GPIO General Purpose Input Output HBM Human Body Model IC Integrated Circuit IEC Internation Electrotechnical Commission IO Input Output IRQ Interrupt Request LDO Low Drop Out MCU Microcontroller MSB Most Significant Bit NPN Negative-Positive-Negative PNP Positive-Negative-Positive OVL Over-Voltage Level OWI One Wire Interface PHY Physical Layer WCSP Wafer Level Chip Scale Package WURQ Wake-Up Request

R36DS0032ED0100 Rev. 1.3 Dec.11.24 Page 28 8. Revision History Revision Date Description 1.3 Dec.11.24 Added MSL information. 1.2 Aug.28.24 Added Exposed Pad (EP) description. 1.1 Jun.25.24 Added Wakeup detection setting recommendation. 1.0 Jun.08.23 Initial release

TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www. renesas.com Contact Information For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit www.renesas.com /contact-us/ . Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SU BSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD-PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers who are designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicabl e standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only to develop an application that uses Renesas products. Other reproduction or use of these resour ces is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third-party intellectual property. Renesas disclaims responsibility for, and you will fully indem nify Renesas and its representatives again st, any claims, damages, costs, losses, or liabilities arising from your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writ ing. No use of any Renesas re sources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Disclaimer Rev.1.01) © 2026 Renesas Electronics Corporation. All rights reserved.