RH1020-CQ172V

RH1280-CQ172V ACTEL | Alldatasheet

Document overview

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Technical content

Features

• Guaranteed Total Dose Radiation Capability  Low Single Event Upset Susceptibility  High Dose Rate Survivability  Latch-Up Immunity Guaranteed  QML Qualified Devices  Commercial Devices Available for Prototyping and Pre-Production Requirements  Gate Capacities of 2,000 and 8,000 Gate Array Gates  More Design Flexibilit y than Custom ASICs  Significantly Greater Dens ities than Discrete Logic Devices  Replaces up to 200 TTL Packages  Design Library with over 500 Macro Functions  Single-Module Sequential Functions  Wide-Input Combin atorial Functions  Up to Two High-Speed, Low-Skew Clock Networks  Two In-Circuit Diagnostic Probe Pins Support Speed Analysis to 50 MHz  Non-Volatile, User Programmable Devices  Fabricated in 0.8 µ Epitaxial Bulk CMOS Process  Unique In-System Diagnostic and Verification Capability with Silicon Explorer Product Family Profile Device RH1020 RH1280 Capacity System Gates Gate Array Equivalent Gates PLD Equivalent Gates TTL Equivalent Packages 20-Pin PAL Equivalent Packages 3,000 2,000 6,000 12,000 8,000 20,000 200 Logic Modules S-Modules C-Modules 547 547 1,232 624 608 Flip-Flops (Maximum) 273 998 Routing Resources Horizontal Tracks/Channel Vertical Tracks/Channel PLICE Antifuse Elements 186,000 750,000 User I/Os (Maximum) 69 140 Packages (by Pin Count) Ceramic Quad Flat Pack (CQFP) 84 172 v3.1

ii v3.1

Ordering Information

Figure 1-1 • Ordering Information Application V = QML Qualified Package Type CQ = Ceramic Quad Flat Pack Part Number RH1280 = 8000 Gates RH1020 = 2000 Gates Package Lead Count RH1280 – CQ 172 V CQFP 84-Pin CQFP 172-Pin RH1020 69 – RH1280 – 140

v3.1 iii Table of Contents Radiation-Hardened FPGAs

v3.1 1-1 Radiation-Hardened FPGAs General Description Actel Corporation, the leader in antifuse-based field programmable gate arrays (FPGAs), offers fully guaranteed RadHard versio ns of the A1280 and A1020 devices with gate densities of 8,000 and 2,000 gate array gates, respectively. The RH1020 and RH1280 devices are processed in 0.8 µ, two-level metal epitaxial bulk CMOS technology. The devices are based on the Actel patented channeled array architecture, and employ Actel’s PLICE antifuse technology. This architecture offers gate array flexibility, high performance, and fast design implementation through user programming. Actel devices also provide unique on-chip diagnostic probe capabilities, allowing convenient testing and debugging. On-chip clock drivers with hard-wired distribution networks provide efficient clock distribution with minimum skew. A security fuse may be programmed to disable all further programming, and to protect the design from being copied or reverse engineered. The RH1020 and RH1280 are available as fully qualified QML devices. Unlike traditional ASIC devices, the design does not have to be finalized six months prior to receiving the devices. Customers can make design modifications and program new devices within hours. These devices are fabricated , assembled, and tested at the Lockheed-Martin Space and Electronics facility in Manassas, Virginia on an optimized radiation-hardened CMOS process. Radiation Survivability In addition to all electrical limits, all radiation characteristics are tested and guaranteed, reducing overall system-level risks. With total dose hardness of 300 krad (Si), latch-up immunity, and a tested single event upset (SEU) of less than 1x10 –6 errors/bit-day, these are the only RadHard, high-density field programmable products available today. QML Qualification Lockheed Martin Space and Electronics in Manassas, Virginia has achieved full QML certification, assuring that quality management, procedures, processes, and controls are in place from wafer fabrication through final test. QML qualification means that quality is built into the production process rather than verified at the end of the line by expensive and destructive testing. QML also ensures continuous process improvement, a focus on enhanced quality and reliab ility, and shortened product introduction and cycle time. Actel Corporation has also achieved QML certification. All RH1020 and RH1280 devices will be shipped with a "QML" marking, signifying that the devices and processes have been reviewed and approved by DESC for QML status. Development Tool Support The RadHard family of FPGAs is fully supported by both Actel Libero ® Integrated Design Environment (IDE) and Designer FPGA development software. Actel Libero IDE is a design management environment, seamlessly integrating design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. Additionally, Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment. Libero IDE includes Synplify ® for Actel from Synplicity ®, ViewDraw ® for Actel from Mentor Graphics®, ModelSim® HDL Simulator from Mentor Graphics, WaveFormer Lite™ from SynaptiCAD™, and Designer software from Actel. Refer to the Libero IDE flow diagram for more information (located on the Actel website). Actel Designer software is a place-and-route tool and provides a comprehensive suite of backend support tools for FPGA development. The Designer software includes timing-driven place-and-ro ute, and a world-class integrated static timing anal yzer and constraints editor. With the Designer software, a user can select and lock package pins while only minimally impacting the results of place-and-route. Additionally, the back-annotation flow is compatible with all the major simulators and the simulation results can be cross-probed with Silicon Explorer II, Actel’s integrated verification and logic analysis tool. Another tool included in the Designer software is the ACTgen macro builder, which easily creates popular and commonly used logic functions for implementation in your schematic or HDL design. Actel's Designer software is compat ible with the most popular FPGA design entry and verification tools from companies such as Mentor Graphics, Synplicity, Synopsys, and Cadence Design Systems. The Designer software is available for both the Windows and UNIX operating systems.

1-2 v3.1

Applications

The RH1020 and RH1280 devices are targeted for use in military and space applicati ons subject to radiation effects. 1. Accumulated Total Dose Effects With the significant in crease in Earth-orbiting satellite launches and the ever-decreasing time-to- launch design cycles, the RH1020 and RH1280 devices offer the best combination of total dose radiation hardness and quick design implementation necessary for this increasingly competitive industry. In addition, the high total dose capability allows the use of these devices for deep space probes, which encounter other planetary bodies where the total dose radiation effects are more pronounced. 2. Single Event Effects (SEE) Many space applications are more concerned with the number of single event upsets and potential for latch- up in space. The RH1020 and RH1280 devices are latch-up immune, guarant eeing that no latch-up failures will occur. Single event upsets can occur in these devices as with all semiconductor products, but the rate of upset is low, as shown in Table 1-2 on page 1-6. 3. High Dose Rate Survivability An additional radiation concern is high dose rate survivability. Solar flares and sudden nuclear events can cause immediate high levels of radiation. The RadHard devices are appropriate for use in these types of applications, including missile systems, ground-based communication systems, and orbiting satellites. RadHard Architecture The RH1020 and RH1280 architecture is composed of fine-grained building blocks that produce fast and efficient logic designs. All the devices are composed of logic modules, routing resources, clock networks, and I/O modules, which are the building blocks for fast logic designs. Logic Modules RH1280 devices contain two types of logic modules, combinatorial (C-modules) and sequential (S-modules). RH1020 devices contain only C-modules. The C-module, shown in Figure 1-1, implements the following function: × D10 + S1 × S0 × D11 EQ 1-1 where S0 = A0 × B0 S1 = A1 + B1 The S-module, shown in Figure 1-2 on page 1-3 , is designed to implement high-speed sequential functions within a single logic modul e. The S-module implements the same combinatorial logic function as the C-module while adding a sequential element. The sequential element can be configured as either a D-flip-flop or a transparent latch. To incr ease flexibility, the S-module register can be bypassed so it implements purely combinatorial logic. Flip-flops can also be created using two C-modules. The single event upset (SEU) characteristics differ between an S-module flip-flop and a f lip-flop created using two C-modules. For details see the Radiation Specifications table on Table 1-2 on page 1-6 and the Design Techniques for RadHard Field Programmable Gate Arrays application note. The RH1020 Logic Module The RH1020 logic module is an 8-input, one-output logic circuit chosen for the wide range of functions it implements and for its effi cient use of interconnect routing resources (Figure 1-3 on page 1-3). The logic module can implem ent the four basic logic functions (NAND, AND, OR, and NOR) in gates of two, three, or four inputs. Each function may have many versions, with different co mbinations of active-low inputs. The logic module can also implement a variety of D-latches, exclusivity func tions, AND-ORs, and OR-ANDs. No dedicated hardwired latches or flip-flops are required in the array, since latches and flip-flops may be constructed from logic modules wherever needed in the application. Figure 1-1  C-Module Implementation D00 D01 D10 D11 Y

v3.1 1-5 QML Flow Absolute Maximum Ratings Test Inspection Method Wafer Lot Acceptance LMFS Procedure MAN-STC-Q014 Serialization Required – 100% Die Adhesion Test 2027 (Stud Pull) Bond Pull Test 2011 (Wirebond) Internal Visual 2010, Condition A Temperature Cycle 1010, Condition C, 50 Cycles Constant Acceleration 2001, Condition D or E, Y1 Orientation Only Particle Impact Noise Detection (PIND) 2020, Condition A X-Ray Radiography 2012 Pre Burn-In Electrical Parameters (T0) Per Device Specification Dynamic Burn-In 1015, 240 Hour Minimum, 125°C Interim Electrical Parameters (T1) Per Device Specification Percent Defective Allowable (PDA) LMFS Procedure MAN-STC-Q016 Static Burn-In 1015, 144 Hour Minimum, 125°C Minimum Final Electrical Parameters (T2) Per Device Specification Percent Defective Allowable (PDA) LMFS Procedure MAN-STC-Q016 Seal – Fine/Gross Leak 1014 External Visual (as required) 2009 Table 1-1  Free Air Temperature Range Symbol Parameter Limits Units VCC DC Supply Voltage2,3,4,5 –0.5 to +7.0 V VI Input Voltage –0.5 to V CC +0.5 V VO Output Voltage –0.5 to V CC +0.5 V IIO I/O Source/Sink Current6 ±20 mA TSTG Storage Temperature2 –65 to +150 °C Notes: 1. Stresses beyond those listed under "Absolute Maximu m Ratings" may cause permanent damage to the device. 2. Exposure to absolute maximum rated cond itions for extended periods may affect device reliability. Devices should not be operated outside the recommended operating conditions. 3. V PP = VCC , except during device operation. 4. V SV = VCC , except during device operation. 5. V KS = GND , except during device operation. 6. Device inputs are normally high impedance and draw extremely low current. However, when inpu t voltage is greater than V CC + 0.5 V or less than GND – 0.5V, the internal protection diode will be forward-biased and can draw excessive current.

1-6 v3.1 Recommended Operating Conditions Electrical Specifications Radiation Specifications Parameter Military Units Temperature Range1 –55 to +125 °C Power Supply Tolerance2 ±10 %V CC Notes: 1. Case temperature (T C) is used. 2. All power supplies must be in the recommended operating range. Symbol Group A Subgroups Limits UnitsTest Conditions Min. Max. VOH 1 (IOH = –4 mA) 1, 2, 3 3.7 V VOL 1 (IOL = 4 mA) 1, 2, 3 0.4 V VIH 1, 2, 3 2.2 V CC + 0.3 V VIL 1, 2, 3 –0.3 0.8 V Input Transition Time tR, tF 2 —5 0 0 n s CIO, I/O Capacitance2 42 0 p F IIH, IIL VIN = VCC or GND VCC = 5.5 V 1, 2, 3 –10 10 µA IOZL, IOZH VOUT = VCC or GND VCC = 5.5 V 1, 2, 3 –10 10 µA ICC Standby3 1, 2, 3 25 mA Notes: 1. Only one output tested at a time. V CC = min. 2. Not tested, for information only. 3. All outputs unloaded. All inputs = V CC or GND. Table 1-2  Radiation Specifications1, 2 Symbol Characteristics Conditions Min. Max. Units RTD Total Dose 300 k Rad (Si) SEL Single Event Latch-Up –55°C ≤ Tcase ≤ 125°C 0 Fails/Device-Day SEU13 Single Event Upset for S-modules –55°C ≤ Tcase ≤ 125°C 1E-6 Upsets/Bit-Day SEU23 Single Event Upset for C-modules –55°C ≤ Tcase ≤ 125°C 1E-7 Upsets/Bit-Day SEU33 Single Event Fuse Rupture –55°C ≤ Tcase ≤ 125°C <1 FIT (Fails/Device/1E9 Hrs) RNF Neutron Fluence >1 E+12 N/cm 2 Notes: 1. Measured at room temperat ure unless otherwise stated. 2. Device electrical characteristics are guaranteed for post-irradiation levels at worst-case conditions. 3. 10% worst-case particle environment, geosynchronous orbit, 0. 025" of aluminum shielding. Specification set using the CREME code upset rate calculation method with a 2 µ epi thickness.

v3.1 1-7 Package Thermal Characteristics The device junction to case thermal characteristics is θjc, and the junction to ambient air ch aracteristics is θja. The thermal characteristics for θja are listed with two different air flow rates, as shown in Table 1-3. Maximum junction temperature is 150°C. A sample calculation of the maximum power dissipation for an 84-pin ceramic quad flat pack at commercial temperature is shown in EQ 1-2. EQ 1-2 Power Dissipation General Power Equation P = [ICCstandby + ICCactive] × VCC + IOL × VOL × N + IOH × (VCC – VOH) × M EQ 1-3 where ICCstandby is the current flowing when no inputs or outputs are changing. ICCactive is the current flowing due to CMOS switching. IOL, IOH are TTL sink/source currents. VOL, VOH are TTL level output voltages. N equals the number of outputs driving TTL loads to VOL. M equals the number of outputs driving TTL loads to VOH. Accurate values for N and M are difficult to determine because they depend on the family type, design details, and on the system I/O. The power can be divided into two components: static and active. Static Power Components Actel FPGAs have small static power components that result in lower power dissipation than PALs or PLDs. By integrating multiple PALs/P LDs into one FPGA, an even greater reduction in board- level power dissipation can be achieved. The power due to standby cu rrent is typically a small component of the overall power. Standby power is calculated below for military, worst case conditions. I CC VCC Power 25 mA 5.5 V 138 mW (max) 1 mA 5.5 V 5.5 mW (typ) Active Power Components Power dissipation in CMOS devices is usually dominated by the active (dynamic) power dissipation. This component is frequency-dependent and a function of the logic and the external I/O. Active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to PC board traces and load devi ce inputs. An additional component of the active power dissipation is the totempole current in CMOS transistor pairs. The net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. The power dissipated by a CMOS circuit can be expressed by EQ 1-4: Power (uW) = CEQ × VCC 2 × F EQ 1-4 Table 1-3  Thermal Characteristics Package Type Pin Count θjc θja UnitsStill Air 1.0 m/s 200 ft. / min. 2.5 m/s 500 ft. / min. Ceramic Quad Flat Pack 84 2.0 40.0 33.0 30.0 °C/W Ceramic Quad Flat Pack 172 2.0 28.0 23.1 21.0 °C/W Note: θjc for CQFP packages refers to the thermal resistance between the junction and the bottom of the package. Max. Junction Temperature °C() Max. Commercial Temperature °C()–

1-8 v3.1 where Equivalent Capacitance Equivalent capacitance is calculated by measuring I CC active at a specified fre quency and voltage for each circuit component of intere st. Measurements have been made over a range of frequencies at a fixed value of VCC. Equivalent capacitance is frequency-independent so the results may be used over a wide range of operating conditions. Equivalent capacitance values follow. CEQ Values for Actel FPGAs To calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. EQ 1-5 shows a piece-wise linear summation over all components. Power = VCC 2 × [(m × CEQM × fm)modules + (n × CEQI × fn)inputs + (p × (CEQO+ CL) × fp)outputs + 0.5 × (q1 × CEQCR × fq1)routed_Clk1 + (r1 × fq1)routed_Clk1 + 0.5 (q2 × CEQCR × fq2)routed_Clk2 + (r2 × fq2)routed_Clk2] EQ 1-5 where Fixed Capacitance Values for Actel FPGAs (pF) r1 r2 Device Type routed_Clk1 routed_Clk2 RH1020 69 N/A RH1280 168 168 Determining Average Switching Frequency To determine the switching frequency for a design, you must have a detailed understanding of the data input values to the circuit. The following guidelines are meant to represent worst-case scenarios, so they can be generally used to predict the upper limits of power dissipation. These guidelines are as follow: CEQ = Equivalent capacitance in pF VCC = Power supply in volts (V) F = Switching frequency in MHz RH1020 RH1280 Modules (CEQM)3 . 7 5.2 Input Buffers (CEQI) 22.1 11.6 Output Buffers (CEQO) 31.2 23.8 Routed Array Clock Buffer Loads (CEQCR)4 . 6 3 . 5 m = Number of logic mo dules switching at fm n = Number of input buffers switching at f n p = Number of output buffers switching at f p q1 = Number of clock loads on the first routed array clock q2 = Number of clock loads on the second routed array clock (RH1280 only) r1 = Fixed capacitance due to first routed array clock r2 = Fixed capacitance due to second routed array clock (RH1280 only) CEQM = Equivalent capacitance of logic modules in pF CEQI = Equivalent capacitance of input buffers in pF CEQO = Equivalent capacitance of output buffers in pF CEQCR = Equivalent capacitance of routed array clock in pF CL = Output lead capacitance in pF fm = Average logic module switching rate in MHz fn = Average input buffer switching rate in MHz fp = Average output buffer switching rate in MHz fq1 = Average first routed array clock rate in MHz fq2 = Average second routed array clock rate in MHz (RH1280 only) Logic Modules (m) = 80% of Modules Inputs Switching (n) = # Inputs/4 Outputs Switching (p) = # Outputs/4 First Routed Array Clock Loads (q1) = 40% of Sequential Modules Second Routed Array Clock Loads 2) (RH1280 only) = 40% of Sequential Modules Load Capacitance (CL) = 35 pF Average Logic Module Switching Rate (fm) =F / 1 0 Average Input Switching Rate (fn) =F / 5 Average Output Switching Rate (fp) =F / 1 0 Average First Routed Array Clock Rate (fq1) Average Second Routed Array Clock Rate (fq2) (RH1280 only) =F / 2

1-12 v3.1 Figure 1-14  Output Buffer Latches D G PAD OBDLHS D G tOUTSU tOUTH

v3.1 1-13 Timing Characteristics Table 1-4  RH1020 Timing Characteristics (Worst-Case Military Conditions, VCC = 4.5 V, T J = 125°C, RTD = 300 krad (Si)) Parameter Description Min. Max. Units Logic Module Propagation Delays t PD1 Single Module 3.9 ns tPD2 Dual Module Macros 9.2 ns tCO Sequential Clk to Q 3.9 ns tGO Latch G to Q 3.9 ns tRS Flip-Flop (Latch) Reset to Q 3.9 ns Logic Module Predicted Routing Delays1 tRD1 FO=1 Routing Delay 1.2 ns tRD2 FO=2 Routing Delay 1.9 ns tRD3 FO=3 Routing Delay 2.8 ns tRD4 FO=4 Routing Delay 4.2 ns tRD8 FO=8 Routing Delay 8.9 ns Logic Module Sequential Timing 2 tSUD Flip-Flop (Latch) Data Input Set-Up 7.5 ns tHD Flip-Flop (Latch) Data Input Hold 0.0 ns tSUENA Flip-Flop (Latch) Enable Set-Up 7.5 ns tHENA Flip-Flop (Latch) Enable Hold 0.0 ns tWCLKA Flip-Flop (Latch) Clock Active Pulse Width 9.2 ns tWASYN Flip-Flop (Latch) Asynchronous Pulse Width 9.2 ns tA Flip-Flop Clock Input Period 19.2 ns fMAX Flip-Flop (Latch) Clock Frequency 50 MHz Input Module Propagation Delays t INYH Pad to Y High 4.2 ns tINYL Pad to Y Low 4.2 ns Input Module Predicted Routing Delays1, 3 tIRD1 FO=1 Routing Delay 1.2 ns tIRD2 FO=2 Routing Delay 1.9 ns tIRD3 FO=3 Routing Delay 2.8 ns tIRD4 FO=4 Routing Delay 4.2 ns tIRD8 FO=8 Routing Delay 8.9 ns Notes: 1. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing analysis or simulation is required to determin e actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 2. Set-up times assume fanout of 3. Further testing informati on can be obtained from the DirectTime Analyzer utility. 3. Optimization techniques may furt her reduce delays by 0 to 4 ns. 4. The hold time for the DFME1A macro may be greater than 0 ns. Us e the Designer v3.0 (or later) Ti mer to check the hold time for this macro.

1-14 v3.1 Table 1-5  RH1020 Timing Characteristics (Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125°C, RTD = 300 krad (Si)) Parameter Description Min. Max. Units Global Clock Network tCKH Input Low to High FO = 16 FO = 128 6.6 7.6 ns tCKL Input High to Low FO = 16 FO = 128 8.7 9.5 ns tPWH Minimum Pulse Width High FO = 16 FO = 128 8.8 9.2 ns tPWL Minimum Pulse Width Low FO = 16 FO = 128 1.6 2.4 ns tCKSW Maximum Skew FO = 16 FO = 128 1.6 2.5 ns tP Minimum Period FO = 16 FO = 128 17.9 19.2 ns fMAX Maximum Frequency FO = 16 FO = 128 MHz TTL Output Module Timing1 tDLH Data to Pad High 9.1 ns tDHL Data to Pad Low 10.2 ns tENZH Enable Pad Z to High 8.9 ns tENZL Enable Pad Z to Low 10.7 ns tENHZ Enable Pad High to Z 13.5 ns tENLZ Enable Pad Low to Z 12.2 ns dTLH Delta Low to High 0.08 ns/pF dTHL Delta High to Low 0.11 ns/pF CMOS Output Module Timing1 tDLH Data to Pad High 10.7 ns tDHL Data to Pad Low 8.7 ns tENZH Enable Pad Z to High 8.1 ns tENZL Enable Pad Z to Low 11.2 ns tENHZ Enable Pad High to Z 13.5 ns tENLZ Enable Pad Low to Z 12.2 ns dTLH Delta Low to High 0.14 ns/pF dTHL Delta High to Low 0.08 ns/pF Notes: 1. Delays based on 35 pF loading. 2. SSO information can be found in the Simultaneously Switching Noise and Signal Integrity application note.

v3.1 1-15 Table 1-6  RH1280 Timing Characteristics (Worst-Case Military Conditions, VCC = 4.5 V, T J = 125°C, RTD = 300 krad (Si)) Parameter Description Min. Max. Units Logic Module Propagation Delays1 tPD1 Single Module 4.7 ns tCO Sequential Clk to Q 4.7 ns tGO Latch G to Q 4.7 ns tRS Flip-Flop (Latch) Reset to Q 4.7 ns Logic Module Predicted Routing Delays2 tRD1 FO=1 Routing Delay 2.7 ns tRD2 FO=2 Routing Delay 3.4 ns tRD3 FO=3 Routing Delay 4.1 ns tRD4 FO=4 Routing Delay 4.8 ns tRD8 FO=8 Routing Delay 9.0 ns Sequential Timing Characteristics3, 4 tSUD Flip-Flop (Latch) Data Input Set-Up 0.7 ns tHD Flip-Flop (Latch) Data Input Hold 0.0 ns tSUENA Flip-Flop (Latch) Enable Set-Up 1.4 ns tHENA Flip-Flop (Latch) Enable Hold 0.0 ns tWCLKA Flip-Flop (Latch) Clock Active Pulse Width 6.6 ns tWASYN Flip-Flop (Latch) Asynchronous Pulse Width 6.6 ns tA Flip-Flop Clock Input Period 13.5 ns tINH Input Buffer Latch Hold 0.0 ns tINSU Input Buffer Latch Set-Up 0.6 ns tOUTH Output Buffer Latch Hold 0.0 ns tOUTSU Output Buffer Latch Set-Up 0.6 ns fMAX Flip-Flop (Latch) Clock Frequency 95 MHz Notes: 1. For dual-module macros, use t PD + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs ac ross worst-case operating co nditions. These parameters sh ould be used for estimating device performance. Post-route timing an alysis or simulation is required to dete rmine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Data applies to macros based on the S-module. Timing para meters for sequential macros constructed from C-modules can be obtained from the DirectTime Analyzer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External set-up/ hold timing parameters must account for dela y from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal set-up (hold) time.

1-16 v3.1 Table 1-7  RH1280 Timing Characteristics (Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125°C, RTD = 300 krad (Si)) Parameter Description Min. Max. Units Input Module Propagation Delays tINYH Pad to Y High 1.9 ns tINYL Pad to Y Low 2.3 ns tINGH G to Y High 4.1 ns tINGL G to Y Low 5.3 ns Input Module Predicted Routing Delays* tIRD1 FO=1 Routing Delay 6.8 ns tIRD2 FO=2 Routing Delay 7.5 ns tIRD3 FO=3 Routing Delay 8.2 ns tIRD4 FO=4 Routing Delay 8.9 ns tIRD8 FO=8 Routing Delay 11.7 ns Global Clock Network tCKH Input Low to High FO = 32 FO = 384 9.6 11.2 ns tCKL Input High to Low FO = 32 FO = 384 9.6 11.2 ns tPWH Minimum Pulse Width High FO = 32 FO = 384 5.8 6.2 ns tPWL Minimum Pulse Width Low FO = 32 FO = 384 5.8 6.2 ns tCKSW Maximum Skew FO = 32 FO = 384 1.1 1.1 ns tSUEXT Input Latch External Set-Up FO = 32 FO = 384 0.0 0.0 ns tHEXT Input Latch External Hold FO = 32 FO = 384 4.6 5.8 ns tP Minimum Period FO = 32 FO = 384 11.8 13.0 ns fMAX Maximum Frequency FO = 32 FO = 384 105 MHz Note: *Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce delays by 0 to 4 ns.

v3.1 1-17 Table 1-8  RH1280 Timing Characteristics (Worst-Case Military Conditions, V CC = 4.5 V, T J = 125°C, RTD = 300 krad (Si)) Parameter Description Min. Max. Units TTL Output Module Timing1 tDLH Data to Pad High 6.8 ns tDHL Data to Pad Low 7.6 ns tENZH Enable Pad Z to High 6.8 ns tENZL Enable Pad Z to Low 7.6 ns tENHZ Enable Pad High to Z 9.7 ns tENLZ Enable Pad Low to Z 9.7 ns tGLH G to Pad High 7.6 ns tGHL G to Pad Low 8.9 ns tLCO I/O Latch Clock-Out (Pad-to-Pad), 64 Clock Loading 17.7 ns tACO Array Clock-Out (Pad-to-Pad), 64 Clock Loading 25.0 ns dTLH Capacitive Loading, Low to High 0.07 ns/pF dTHL Capacitive Loading, High to Low 0.09 ns/pF CMOS Output Module Timing1 tDLH Data to Pad High 8.7 ns tDHL Data to Pad Low 6.4 ns tENZH Enable Pad Z to High 6.8 ns tENZL Enable Pad Z to Low 7.6 ns tENHZ Enable Pad High to Z 9.7 ns tENLZ Enable Pad Low to Z 9.7 ns tGLH G to Pad High 7.6 ns tGHL G to Pad Low 8.9 ns tLCO I/O Latch Clock-Out (Pad-to-Pad), 64 Clock Loading 20.1 ns tACO Array Clock-Out (Pad-to-Pad), 64 Clock Loading 29.5 ns dTLH Capacitive Loading, Low to High 0.09 ns/pF dTHL Capacitive Loading, High to Low 0.08 ns/pF Notes: 1. Delays based on 35 pF loading. 2. SSO information can be found in the Simultaneously Switching Noise and Signal Integrity application note.

1-18 v3.1 Pin Description CLKA Clock A (Input) TTL clock input for clock distribution networks. The clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O. CLKB Clock B (Input) Not applicable for RH1020. TTL clock input for clock distribution networks. The clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O. DCLK1 Diagnostic Clock (Input) TTL clock input for diagnostic probe and device programming. DCLK is acti ve when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. If the Program fuse is not programmed and DCLK is undefined, it is configured as an inactive input. In this case, tie the DCLK pin to ground. If the Program fuse is programmed and DCLK is un defined, it will become an active LOW output.The Program fuse must be programmed if the DCLK pin is used as an output or a bidirectional pin. GND Ground LOW supply voltage. I/O Input/Output (Input, Output) The I/O pin functions as an in put, output, three-state, or bidirectional buffer. Input and output levels are compatible with standard TTL and CMOS specifications. Unused I/O pins are automatically driven LOW by the Designer software. MODE Mode (Input) The MODE pin controls the use of multi-function pins (DCLK, PRA, PRB, SDI). When the MODE pin is HIGH, the special functions are active. When the MODE pin is LOW, the pins function as I/Os. To provide debugging capability, the MODE pin should be terminated to GND through a 10 k Ω resistor so that the MODE pin can be pulled HIGH when required. NC No Connection This pin is not connected to circuitry within the device. PRA, I/O Probe A (Output) The Probe A pin is used to output data from any user- defined design node within the device. This independent diagnostic pin can be used in conjunction with the Probe B pin to allow real-time diagnostic output of any signal path within the device. The Probe A pin can be used as a user-defined I/O when verification has been completed. The pin’s probe capabilities can be permanently disabled to protect programmed design confidentiality. PRA is accessible when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. PRB, I/O Probe B (Output) The Probe B pin is used to output data from any user- defined design node within the device. This independent diagnostic pin can be used in conjunction with the Probe A pin to allow real-time diagnostic output of any signal path within the device. The Probe B pin can be used as a user-defined I/O when verification has been completed. The pin’s probe capabilities can be permanently disabled to protect programmed design confidentiality. PRB is accessible when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. SDI1 Serial Data Input (Input) Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. If the Program fuse is not programmed and SDI is undefined, it is configured as an inactive input. In this case, tie the SDI pin to ground. If the Program fuse is programmed and SDI is und efined, it will become an active LOW output.The Program fuse must be programmed if the SDI pin is used as an output or a bidirectional pin. VCC 5.0V Supply Voltage HIGH supply voltage. 1. Please refer to the Actel Technical Brief Analysis of SDI/DCLK Issue for RH1020 and RT1020.

v3.1 2-1 Package Pin Assignments 84-Pin CQFP Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html. Figure 2-1  84-Pin CQFP (Top View) Pin #1 Index 84-Pin CQFP 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64

2-2 v3.1 84-Pin CQFP Pin Number RH1020 Function 1N C 2I / O 3I / O 4I / O 5I / O 6I / O 7G N D 8G N D 9I / O

10 I/O

11 I/O

12 I/O

13 I/O

15 V CC

16 I/O

17 I/O

18 I/O

19 I/O

20 I/O

21 I/O

23 I/O

24 I/O

25 I/O

26 I/O

27 I/O

28 I/O

29 GND

30 I/O

31 I/O

32 I/O

33 I/O

34 I/O

36 I/O

37 I/O

38 I/O

39 I/O

40 I/O

41 I/O

42 I/O

43 I/O

44 I/O

45 I/O

46 I/O

47 I/O

48 I/O

49 GND

50 GND

51 I/O

52 I/O

53 CLKA, I/O

54 I/O

55 MODE

57 V CC

58 I/O

59 I/O

60 I/O

61 SDI, I/O

62 DCLK, I/O

63 PRA, I/O

64 PRB, I/O

65 I/O

66 I/O

67 I/O

68 I/O

69 I/O

70 I/O

71 GND

72 I/O

73 I/O

74 I/O

75 I/O

76 I/O

78 I/O

79 I/O

80 I/O

81 I/O

82 I/O

83 I/O

84 I/O

v3.1 2-3 172-Pin CQFP Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html. Figure 2-2  172-Pin CQFP (Top View) 172-Pin CQFP Pin #1 Index 172 171 170 169 168 167 166 165 164 137 136 135 134 133 132 131 130 44 45 46 47 48 49 50 51 52 79 80 81 82 83 84 85 86 122 123 125 126 127 129

2-4 v3.1 172-Pin CQFP Pin Number RH1280A Function 1M O D E 2I / O 3I / O 4I / O 5I / O 6I / O 7G N D 8I / O 9I / O

14 I/O

15 I/O

17 GND

22 GND

24 V CC

29 I/O

32 GND

35 I/O

37 GND

49 I/O

53 I/O

55 GND

56 I/O

57 I/O

61 I/O

62 I/O

63 I/O

64 I/O

65 GND

71 I/O

75 GND

77 I/O

85 I/O

86 I/O

87 I/O

88 I/O

89 I/O

90 I/O

91 I/O

92 I/O

93 I/O

94 I/O

95 I/O

96 I/O

97 I/O

98 GND

99 I/O

100 I/O

101 I/O

102 I/O

103 GND

104 I/O

105 I/O

106 GND

107 V CC

108 GND

110 V CC

111 I/O

112 I/O

114 I/O

115 I/O

116 I/O

117 I/O

118 GND

119 I/O

120 I/O

121 I/O

122 I/O

123 GND

124 I/O

125 I/O

126 I/O

127 I/O

128 I/O

129 I/O

130 I/O

131 SDI, I/O

132 I/O

133 I/O

134 I/O

135 I/O

137 I/O

138 I/O

139 I/O

140 I/O

v3.1 2-5

141 GND

142 I/O

143 I/O

144 I/O

145 I/O

146 I/O

147 I/O

148 PRA, I/O

149 I/O

150 CLKA, I/O

152 GND

153 I/O

154 CLKB, I/O

155 I/O

156 PRB, I/O

157 I/O

158 I/O

159 I/O

160 I/O

161 GND

162 I/O

163 I/O

164 I/O

165 I/O

167 I/O

168 I/O

169 I/O

170 I/O

171 DCLK, I/O

172 I/O

v3.1 3-1 Datasheet Information List of Changes The following table lists critical changes that were made in the current version of the document. Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are desi gnated as "Product Brief," "Advance d," "Production," and "Datasheet Supplement." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advanced or production) containing general product information. This brief gives an overview of specific device and family information. Advanced This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. Unmarked (production) This datasheet version contains information that is considered to be final. Datasheet Supplement The datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications that do not differ between the two families. International Traffic in Arms Regulations (ITAR) The product described in this datasheet are subject to the International Traf fic in Arms Regulations (ITAR). They require an approved export license prior to export from th e United States. An export in cludes release of product or disclosure of technology to a foreign national inside or outside the United States. Previous Version Changes in Current Version (v3.1) Page v3.0 "Development Tool Support" section was updated. 1-1 Table 1-1 was updated. 1-5 Table 1-2 was updated. 1-6 Table 1-3 was updated. 1-7 The "DCLK Diagnostic Clock (Input)" section was updated. 1-18 The "SDI1 Serial Data Input (Input)" section was updated. 1-18

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