RFW2N06RLE INTERSIL | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 5
Technical content
Features
- 2A, 60V
- r DS (on) = 0.160Ω
- UIS Rating Curve (Single Pulse)
- Design Optimized For 5 Volt Gate Drive
- Can be Driven Directly from CMOS, NMOS, TTL Circuits
- Compatible with Automotive Drive Requirements
- SOA is Power Dissipation Limited
- Nanosecond Switching Speeds
- Linear Transfer Characteristics
- High Input Impedance
- Majority Carrier Device
- Electrostatic Discharge Protected
- Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol Packaging
4 PIN HEXDIP
Ordering Information
RFW2N06RLE HEXDIP RFW2N06RLE NOTE: When ordering, use the entire part number. D G S SOURCE GATE DRAIN Data Sheet July 1999
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFW2N06RLE UNITS A A J,TSTG -55 to 150 oC Maximum Temperature for Soldering 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationo ft h e device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical SpecificationsTC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BV DSS ID =250µA, VGS = 0V 60 - - V Gate Threshold Voltage V GS(TH) VGS = VDS , ID = 250µA1 - 2 V Zero Gate Voltage Drain Current I DSS VDS = Rated BVDSS , VGS = 0V - - 1 µA VDS = 0.8 x Rated BVDSS , VGS = 0V TC = 125oC -- 2 5 µA Gate to Source Leakage Current I GSS VGS =-5V to 10V - - ±100 nA Drain to Source On Resistance (Note 2) rDS(ON) ID = 2A, VGS = 5V (Figure 8) - - 160 m Ω ID = 2A, VGS = 4.3V (Figure 8) - - 200 m Ω Turn-On Time t (ON) VDD = 30V, ID = 2A, RL = 15Ω , VGS = 5V, R G = 25Ω (Figures 12, 13, 14) - - 100 ns Turn-On Delay Time t d(ON) -1 3- n s Rise Time t r -4 2- n s Turn-Off Delay Time t d(OFF) -9 5- n s Fall Time t f -4 5- n s Turn-Off Time t (OFF) - 200 ns Total Gate Charge Q g(TOT) VGS = 0 to 10V V DD = 48V, ID = 2A, IG(REF) =0.5mA, R L = 24Ω (Figures 12, 15, 16) -2 0 3 0 n C Gate Charge at 5V Q g(5) V GS = 0 to 5V - 11 16 nC Threshold Gate Charge Q g(TH) V GS = 0 to 1V - 0.6 1.0 nC Input Capacitance C ISS VDS = 25V, VGS = 0V, f = 1MHz (Figure 11) - 535 - pF Output Capacitance C OSS - 175 - pF Reverse Transfer Capacitance C RSS -3 2- p F Thermal Resistance, Junction to Ambient RθJA - - 115 oC/W Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage (Note 2) VSD ISD = 2A - - 1.2 V Reverse Recovery Time t rr ISD = 2A, dlSD /dt = 100A/µs - - 200 ns NOTES: 2. Pulse test: width ≤300µs duty cycle≤ 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. RFW2N06RLE
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs FIGURE 3. FORWARD BIAS SAFE OPERATING AREA FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 5. SATURATION CHARACTERISTICS FIGURE 6. TRANSFER CHARACTERISTICS
0.01 ID, DRAIN CURRENT, (A)
FIGURE 7. NORMALIZED DRAIN TO SOURCE ON VOLTAGE FIGURE 8. NORMALIZED DRAIN TO SOURCE ON FIGURE 9. NORMALIZED GATE THRESHOLD VOLTAGE vs FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE NOTE: Refer to Harris Application Notes AN7254 and AN7260. FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR
20 IG(REF)
0.75 BVDSS
0.25 BVDSS
0.50 BVDSS
All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
1130 Brussels, Belgium
FIGURE 13. SWITCHING TIME TEST CIRCUIT FIGURE 14. RESISTIVE SWITCHING WAVEFORMS FIGURE 15. GATE CHARGE TEST CIRCUIT FIGURE 16. GATE CHARGE WAVEFORMS