RFT2P03L INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • 2.1A, 30V
  • r DS(ON) = 0.150Ω
  • Temperature Compensating PSPICE® Model
  • Thermal Impedance SPICE Model
  • Peak Current vs Pulse Width Curve
  • UIS Rating Curve
  • Related Literature - TB334, “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol Packaging SOT-223

Ordering Information

NOTE: RFT2P03L is available only in tape and reel. Use the entire part number and add the suffix T. D G S DRAIN SOURCE GATE DRAIN (FLANGE) July 1999 File Number 4574.2Data Sheet

Absolute Maximum Ratings TA = 25oC, Unless Otherwise Specified UNITS Drain Current 2.1 Figure 5 A 1.1 0.009 W W/oC Maximum Temperature for Soldering 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationo ft h e device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical SpecificationsTA = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BV DSS ID = 250µA, VGS = 0V (Figure 11) -30 - - V Gate to Source Threshold Voltage V GS(TH) VGS = VDS , ID = 250µA (Figure 10) -1 - -3 V Zero Gate Voltage Drain Current I DSS VDS = -30V, VGS = 0V - - -1 µA VDS = -30V, VGS = 0V, TA = 150oC - - -50 µA Gate to Source Leakage Current I GSS VGS =±20V - - ±100 nA Drain to Source On Resistance r DS(ON) ID = 2.1A, VGS = -10V (Figure 9) - 0.120 0.150 Ω ID = 2.1A, VGS = -4.5V (Figure 9) - 0.300 0.360 Ω Turn-On Time t ON VDD = -15V, ID ≅ 2.1A, R L = 7.1Ω , VGS = −10V, R GS = 21Ω - - 50 ns Turn-On Delay Time t d(ON) -1 3 - n s Rise Time t r -1 8 - n s Turn-Off Delay Time t d(OFF) -4 3 - n s Fall Time t f -2 4 - n s Turn-Off Time t OFF - - 100 ns Total Gate Charge Q g(TOT) VGS = 0V to -20V VDD = -15V, ID ≅ 2.1A, R L = 7.1Ω Ig(REF) = -1.0mA (Figure 13) -2 73 3n C Gate Charge at -10V Q g(-10) VGS = 0V to -10V - 14 17 nC Threshold Gate Charge Q g(TH) VGS = 0V to -2V - 1.3 1.6 nC Input Capacitance C ISS VDS = -25V, VGS = 0V, f = 1MHz (Figure 12) - 620 - pF Output Capacitance C OSS - 240 - pF Reverse Transfer Capacitance C RSS -3 0 - p F Thermal Resistance Junction to Ambient R θJA Pad Area = 0.171 in2 (See note 2) - - 110 oC/W Pad Area = 0.068 in2 (See Tech Brief 377) - - 128 oC/W Pad Area = 0.026 in2 (See Tech Brief 377) - - 147 oC/W Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage V SD ISD = -2.1A - - -1.25 V Reverse Recovery Time t rr ISD = -2.1A, dISD /dt = 100A/µs- - 4 9 n s Reverse Recovered Charge Q RR ISD = -2.1A, dISD /dt = 100A/µs- - 4 5 n C NOTE: 2. 110oC/W measured using FR-4 board with 0.171 in2 footprint for 1000 seconds. RFT2P03L

.SUBCKT RFT2P03L 2 1 3 ; REV July 1998 CA 12 8 6.5e-10 CB 15 14 6.4e-10 CIN 6 8 5.77e-10 DBODY 5 7 DBODYMOD DBREAK 7 11 DBREAKMOD DPLCAP 10 6 DPLCAPMOD EBREAK 5 11 17 18 -41.2 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 5 10 8 6 1 EVTHRES 6 21 19 8 1 EVTEMP 6 20 18 22 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 1.27e-9 LSOURCE 3 7 4.2e-10 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 24e-3 RGATE 9 20 5.2 RLDRAIN 2 5 10 RLGATE 1 9 12.7 RLSOURCE 3 7 4.2 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 68e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*45),2.5))} .MODEL DBREAKMOD D (RS = 2e-1 TRS1 = 1e-4 TRS2 = 1e-5) .MODEL DPLCAPMOD D (CJO = 2.65e-10 IS = 1e-30 N = 10 M = 0.63) .MODEL MMEDMOD PMOS (VTO = -2.6 KP = 1.2 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 5.2) .MODEL MSTROMOD PMOS (VTO = -3.27 KP = 6 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD PMOS (VTO = -2.11 KP = 0.07 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 52 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 9.2e-4 TC2 = -1e-7) .MODEL RDRAINMOD RES (TC1 = 1.8e-2 TC2 = 2.1e-5) .MODEL RSLCMOD RES (TC1 = 3.5e-3 TC2 = 1.3e-6) .MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0) .MODEL RVTHRESMOD RES (TC1 = 8.8e-4 TC2 = 6.1e-6) .MODEL RVTEMPMOD RES (TC1 = -2e-3 TC2 = 1e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 5.7 VOFF= 2.7) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.7 VOFF= 5.7) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.1 VOFF= -2.4) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.4 VOFF= -0.1) .ENDS NOTE: For further discussion of the PSPICE model, consultA New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. GATE RGATE EVTEMP 229 12 13 S1A S1B S2A S2B CA CB EGS EDS CIN MWEAK RDRAIN DBREAK EBREAK DBODY DRAIN RSOURCE SOURCE RBREAK RVTEMP VBAT IT EVTHRES ESG DPLCAP ESLC RSLC1 RSLC2 610 7 3 17 18 MMED MSTRO RVTHRES LSOURCE RLSOURCE LDRAIN RLDRAIN LGATE RLGATE RFT2P03L

CTHERM1 9 8 1.9e-5 CTHERM2 8 7 3.0e-4 CTHERM3 7 6 1.2e-3 CTHERM4 6 5 3.5e-3 CTHERM5 5 4 2.0e-2 CTHERM6 4 3 6.5e-2 CTHERM7 3 2 2.0e-1 CTHERM8 2 1 1 RTHERM1 9 8 3.5e-2 RTHERM2 8 7 8.5e-2 RTHERM3 7 6 3.5e-1 RTHERM4 6 5 1.85 RTHERM5 5 4 2.75 RTHERM6 4 3 15 RTHERM7 3 2 30 RTHERM8 2 1 50 RTHERM4 RTHERM6 RTHERM5 RTHERM3 RTHERM2 RTHERM1 CTHERM4 CTHERM6 CTHERM5 CTHERM3 CTHERM2 CTHERM1

9 JUNCTION

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 RFT2P03L