RFPS43N50K VISHAY | Alldatasheet

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Document Number: 91262 www.vishay.com S-81367-Rev. B, 21-Jul-08 1 Power MOSFET IRFPS43N50K, SiHFPS43N50K Vishay Siliconix

FEATURES

  • Low Gate Charge Q g Results in Simple Drive Requirement  Improved Gate, Avalanche and Dynamic dV/dt Ruggedness  Fully Characterized Capacitance and Avalanche Voltage and Current L o w RDS(on)  Lead (Pb)-free Available

APPLICATIONS

 Switch Mode Power Supply (SMPS)  Uninterruptible Power Supply  High Speed Power Switching  Hard Switched and High Frequency Circuits Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Starting T J = 25 °C, L = 0.82 mH, RG = 25 Ω, IAS = 47 A (see fig. 12c). c. I SD ≤ 47 A, dI/dt ≤ 230 A/µs, VDD ≤ VDS, TJ ≤ 150 °C. d. 1.6 mm from case. PRODUCT SUMMARY VDS (V) 500 RDS(on) (Ω)V GS = 10 V 0.078 Qg (Max.) (nC) 350 Qgs (nC) 85 Qgd (nC) 180 Configuration Single N-Channel MOSFET G D S G D S SUPER-247TM Available RoHS* COMPLIANT

ORDERING INFORMATION

Lead (Pb)-free IRFPS43N50KPbF SiHFPS43N50K-E3 SnPb IRFPS43N50K SiHFPS43N50K ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER SYMBOL LIMIT UNIT Drain-Source Voltage V DS 500 V Gate-Source Voltage V GS ± 30 Continuous Drain Current V GS at 10 V TC = 25 °C ID ATC = 100 °C 29 Pulsed Drain Currenta IDM 190 Linear Derating Factor 4.3 W/°C Single Pulse Avalanche Energyb EAS 910 mJ Repetitive Avalanche Currenta IAR 47 A Repetitive Avalanche Energya EAR 54 mJ Maximum Power Dissipation T C = 25 °C P D 540 W Peak Diode Recovery dV/dtc dV/dt 9.0 V/ns Operating Junction and Storage Temperature Range T J, Tstg - 55 to + 150 Soldering Recommendations (Peak Temperature) for 10 s 300 d * Pb containing terminations are not RoHS compliant, exemptions may apply

www.vishay.com Document Number: 91262 2 S-81367-Rev. B, 21-Jul-08 IRFPS43N50K, SiHFPS43N50K Vishay Siliconix Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 400 µs; duty cycle ≤ 2 %. c. C oss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS. THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. UNIT Maximum Junction-to-Ambient R thJA -4 0 °C/WCase-to-Sink, Flat, Greased Surface R thCS 0.24 - Maximum Junction-to-Case (Drain) R thJC -0 . 2 3 SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage V DS VGS = 0 V, ID = 250 µA 500 - - V VDS Temperature Coefficient ΔVDS/TJ Reference to 25 °C, I D = 1 mA - 0.60 - V/°C Gate-Source Threshold Voltage V GS(th) VDS = VGS, ID = 250 µA 3.0 - 5.0 V Gate-Source Leakage I GSS V GS = ± 30 V - - ± 100 nA Zero Gate Voltage Drain Current I DSS VDS = 500 V, VGS = 0 V - - 50 µA VDS = 400 V, VGS = 0 V, TJ = 125 °C - - 250 Drain-Source On-State Resistance R DS(on) V GS = 10 V I D = 28 Ab - 0.078 0.090 Ω Forward Transconductance g fs VDS = 50 V, ID = 28 A 23 - - S Dynamic Input Capacitance C iss VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 - 8310 - pF Output Capacitance C oss - 960 - Reverse Transfer Capacitance C rss - 120 - Output Capacitance C oss VGS = 0 V VDS = 1.0 V, f = 1.0 MHz - 10170 - VDS = 400 V, f = 1.0 MHz - 240 - Effective Output Capacitance C oss eff. V DS = 0 V to 400 Vc - 440 - Total Gate Charge Q g VGS = 10 V ID = 47 A, VDS = 400 V, see fig. 6 and 13b - - 350 nC Gate-Source Charge Q gs -- 8 5 Gate-Drain Charge Q gd - - 180 Turn-On Delay Time t d(on) VDD = 250 V, ID = 47 A, RG = 1.0 Ω, see fig. 10b -2 5- ns Rise Time t r - 140 - Turn-Off Delay Time t d(off) -5 5- Fall Time t f -7 4- Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current I S MOSFET symbol showing the integral reverse p - n junction diode -- 4 7 A Pulsed Diode Forward Current a ISM - - 190 Body Diode Voltage V SD TJ = 25 °C, IS = 47 A, VGS = 0 Vb -- 1 . 5 V Body Diode Reverse Recovery Time t rr TJ = 25 °C, IF = 47 A, dI/dt = 100 A/µsb - 620 940 ns Body Diode Reverse Recovery Charge Q rr -1 4 2 1 µ C Body Diode Recovery Current I RRM -3 8-A Forward Turn-On Time t on Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) S D G

Document Number: 91262 www.vishay.com S-81367-Rev. B, 21-Jul-08 3 IRFPS43N50K, SiHFPS43N50K Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Output Characteristics Fig. 3 - Typical Transfer Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature 0.01 0.1 100 1000 0.1 100 20µs PULSE WIDTH T = 25 C J TOP BOTTOM VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V V , Drain-to-Source Voltage (V) I , Drain-to-Source Current (A) DS D 4.5V 0.1 100 1000 0.1 100 20µs PULSE WIDTH T = 150 C J TOP BOTTOM VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V V , Drain-to-Source Voltage (V) I , Drain-to-Source Current (A) DS D 4.5V 0.1 100 1000 V = 50V 20µs PULSE WIDTH DS V , Gate-to-Source Voltage (V) I , Drain-to-Source Current (A) GS D T = 25 C J T = 150 C J -60 -40 -20 100 120 140 160 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 T , Junction Temperature ( C) R , Drain-to-Source On Resistance (Normalized) J DS(on) V I GS D 10V 48A

www.vishay.com Document Number: 91262 4 S-81367-Rev. B, 21-Jul-08 IRFPS43N50K, SiHFPS43N50K Vishay Siliconix Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 8 - Maximum Safe Operating Area 100 1000 VDS, Drain-to-Source Voltage (V) 100 1000 10000 100000 1000000 C,Capacitance(pF) Coss Crss Ciss V GS = 0V, f = 1 MHZ C iss = C gs + C gd , C ds SHORTED C rss = C gd C oss = C ds + C gd 100 150 200 250 300 350 Q , Total Gate Charge (nC) V , Gate-to-Source Voltage (V) G GS I D 48A V 100V DS V 250V DS V 400V DS 0.1 100 1000 0.2 0.7 1.2 1.7 2.2 V ,Source-to-Drain Voltage (V) I , Reverse Drain Current (A) SD SD V = 0 V GS T = 25 C J T = 150 C J 100 1000 100 1000 OPERATION IN THIS AREA LIMITED BY R DS(on) Single Pulse T T = 150 C = 25 C J C V , Drain-to-Source Voltage (V) I , Drain Current (A) I , Drain Current (A) DS D 10us 100us 1ms 10ms

Document Number: 91262 www.vishay.com S-81367-Rev. B, 21-Jul-08 5 IRFPS43N50K, SiHFPS43N50K Vishay Siliconix Fig. 9 - Maximum Drain Current vs. Case Temperature Fig. 10a - Switching Time Test Circuit Fig. 10b - Switching Time Waveforms Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms 100 125 150 T , Case Temperature ( C) I , Drain Current (A) C D Pulse width ≤ 1 µs Duty factor ≤ 0.1 % RD VGS RG D.U.T. 10 V VDS VDD VDS 90 % 10 % VGS td(on) tr td(off) tf 0.001 0.01 0.1 0.00001 0.0001 0.001 0.01 0.1 Notes: 1. Duty factor D = t / t 2. Peak T P x Z + T J DM thJC C P t t DM t , Rectangular Pulse Duration (sec) Thermal Response (Z ) thJC 0.01 0.02 0.05 0.10 0.20 D = 0.50 SINGLE PULSE (THERMAL RESPONSE) A R G IAS 0.01 Ωtp D.U.T LVDS - VDD Driver 15 V 20 V IAS VDS tp

www.vishay.com Document Number: 91262 6 S-81367-Rev. B, 21-Jul-08 IRFPS43N50K, SiHFPS43N50K Vishay Siliconix Fig. 12c - Maximum Avalanche Energy vs. Drain Current Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit 100 125 150 500 1000 1500 2000 Starting T , Junction Temperature ( C) E , Single Pulse Avalanche Energy (mJ) J AS I D TOP BOTTOM 22A 30A 47A QGS QGD QG VG Charge 10 V D.U.T. 3 mA VGS VDS IG ID 0.3 µF 0.2 µF 50 kΩ 12 V Current regulator Current sampling resistors Same type as D.U.T.

Document Number: 91262 www.vishay.com S-81367-Rev. B, 21-Jul-08 7 IRFPS43N50K, SiHFPS43N50K Vishay Siliconix Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Pr oducts may be manufactured at one of several qualified locatio ns. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?91262. P.W. Period dI/dt Diode recovery dV/dt Ripple ≤ 5 % Body diode forward drop Re-applied voltage Reverse recovery current Body diode forward current VGS = 10 V* VDD ISD Driver gate drive D.U.T. ISD waveform D.U.T. VDS waveform Inductor current D = P.W. Period * VGS = 5 V for logic level devices Peak Diode Recovery dV/dt Test Circuit RG VDD

  • dV/dt controlled by RG
  • Driver same type as D.U.T.
  • ISD controlled by duty factor "D"
  • D.U.T. - device under test D.U.T Circuit layout considerations
  • Low stray inductance
  • Ground plane
  • Low leakage inductance current transformer

Document Number: 91000 www.vishay.com Revision: 18-Jul-08 1 Disclaimer Legal Disclaimer Notice Vishay All product specifications and data are subject to change without notice. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. Vishay disclaims any and all li ability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permit ted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purcha se, including but not limited to the warranty expressed therein, which apply to these products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. The products shown herein are not designed for use in medi cal, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. Product names and markings noted herein may be trademarks of their respective owners.