RFPIC12C509AF

RFPIC12C509AG MICROCHIP | Alldatasheet

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 2001 Microchip Technology Inc. Preliminary DS70031A rfPIC12C509AG/509AF Data Sheet 18/20-Pin 8-Bit CMOS Microcontroller with UHF ASK/FSK Transmitter

DS70031A - page ii Preliminary  2001 Microchip Technology Inc. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip T echnology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical com- ponents in life support systems is not authorized except with express written approval by Microchip. No licenses are con- veyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, K EE LOQ ,S E E V A L , MPLAB and The Embedded Control Solutions Company are reg- istered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Total Endurance, ICSP, In-Circuit Serial Programming, FilterLab, MXDEV , microID, FlexROM, fuzzyLAB, MPASM, MPLINK, MPLIB, PICC, PICDEM, PICDEM.net, ICEPIC, Migratable Memory, FanSense, ECONOMONITOR, Select Mode, dsPIC, rfPIC and microPort are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick T erm Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2001, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEE LOQ ® code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. Note the following details of the code protection feature on PICmicro® MCUs.

• The PICmicro family meets the specifications contained in the Microchip Data Sheet.
• Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl- edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable”.
• Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our product. If you have any further questions about this matter, please contact the local sales office nearest to you.

 2001 Microchip Technology Inc. Preliminary DS70031A-page 1 rfPIC12C509AG/509AF High-Performance RISC CPU:

• Only 33 single word instructions to learn
• All instructions are single cycle (1µs) except for program branches which are two-cycle
• Operating speed: DC - 4 MHz clock input DC - 1µs instruction cycle
• 12-bit wide instructions
• 8-bit wide data path
• Seven special function hardware registers
• Two-level deep hardware stack
• Direct, indirect and relative addressing modes for data and instructions
• Internal 4 MHz RC oscillator with programmable calibration (independent from transmitter quartz crystal reference)
• In-Circuit Serial Programming™ (ICSP™) Peripheral Features:
• 8-bit real time clock/counter (TMR0) with 8-bit programmable prescaler
• Power-On Reset (POR)
• Device Reset Timer (DRT)
• Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation
• Programmable code-protection
• Power saving SLEEP mode
• Wake-up from SLEEP on pin change
• Internal weak pull-ups on I/O pins
• Internal pull-up on MCLR pin
• Selectable oscillator options: - INTRC: Internal 4 MHz RC oscillator - EXTRC: External low-cost RC oscillator - XT: Standard crystal/resonator - LP: Power saving, low frequency crystal Pin Diagram UHF ASK/FSK Transmitter:
• Conforms to US FCC Part 15.231 regulations and European ERC 70-03E and EN 300 220-1 requirements
• VCO phase locked to quartz crystal reference; allows narrow band receivers to be used to maxi- mize range and interference immunity
• Integrated crystal oscillator and VCO requiring minimum of external components
• Crystal frequency divide by 4 available (CLKOUT)
• Frequency range set by crystal: 310 – 480 MHz
• A S KD a t ar a t e :0–4 0K b p s
• FSK through crystal pulling allows modulation at 0–2 0K b p s
• Adjustable output power: +2 dBm to -12 dBm in six discrete steps
• Differential output configurable for single or double ended loop antenna
• Power amplifier automatically disabled until after PLL lock Device Memory EPROM Program RAM Data Transmitter rfPIC12C509AG 1024 x 12 41 ASK rfPIC12C509AF 1024 x 12 41 ASK/FSK SOIC VSS GP2/T0CKI XTAL GP1 VDD GP5/OSC1/CLKIN GP3/MCLR/ VPP RFEN IN CLKOUT PS/DATA ASK VDDRF GP4/OSC2 LF rfPIC12C509AG GP0 ANT2 NC VSSRF ANT1 SSOP VSS GP2/T0CKI DATA FSK GP1 VDD GP5/OSC1/CLKIN GP3/MCLR/ VPP RFEN IN CLKOUT PS/DATA ASK VDDRF GP4/OSC2 LF rfPIC12C509AF GP0 NC VSSRF ANT2 ANT110 11 FSK OUTXTAL 8-Bit CMOS Microcontroller with UHF ASK/FSK Transmitter

DS70031A-page 2 Premilinary  2001 Microchip Technology Inc. CMOS Technology:

• Low power, high speed CMOS EPROM technology
• Fully static design
• Wide operating voltage range
• Wide temperature range: - Industrial: -40°C to +85°C
• P I C m i c r o ® MCU power consumption: -< 2 m A @ 5 V , 4 M H z -1 5 µA typical @ 3V, 32 KHz -< 1 µA typical standby current
• Transmitter power consumption: (depending on power selection) - 4.8 mA to 11.5 mA @ 3V -< 1 µA typical standby current

 2001 Microchip Technology Inc. Preliminary DS70031A-page 3 rfPIC12C509AG/509AF TABLE OF CONTENTS TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Micro- chip products. T o this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail atdocerrors@mail.microchip.comor fax theReader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
• The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include lit- erature number) you are using. Customer Notification System Register on our web site atwww.microchip.com/cn to receive the most current information on all of our products.

DS70031A-page 4 Premilinary  2001 Microchip Technology Inc.

1.0 GENERAL DESCRIPTION

The rfPIC12C509AG/509AF from Microchip Technol- ogy is a low-cost, high performance, 8-bit, fully static, EPROM-based CMOS microcontroller combined with a UHF ASK/FSK transmitter. It employs a RISC architec- ture with only 33 single word/single cycle instructions. All instructions are single cycle (1µs) except for program branches which take two cycles. The 12-bit wide instructions are highly symmetrical resulting in 2:1 code compression over other 8-bit microcontrollers in its class. The easy to use and easy to remember instruction set reduces development time significantly. The rfPIC12C509AG/509AF product is equipped with special features that reduce system cost and power requirements. The Power-on Reset (POR) and Device Reset Timer (DRT) eliminate the need for external RESET circuitry. There are four oscillator configura- tions to choose from, including INTRC internal oscilla- tor mode and the power-saving LP (Low Power) oscillator mode. Power saving SLEEP mode, Watch- dog Timer and code protection features also improve system cost, power and reliability. The Transmitter is a fully integrated UHF ASK/FSK transmitter consisting of crystal oscillator, phase- locked loop (PLL), open-collector differential-output Power Amplifier (PA), and mode control logic. External components consist of bypass capacitors, crystal, and PLL loop filter. There are no internal electrical connec- tions between the PICmicro MCU and the transmitter. The PICmicro MCU oscillator is independent from the transmitter crystal oscillator. The rfPIC12C509AG is capable of Amplitude Shift Key- ing (ASK) modulation by turning the PA on and off. The rfPIC12C509AF is capable of ASK or Frequency Shift Keying (FSK) modulation by employing an internal FSK switch to pull the transmitter crystal via a second load capacitor. The rfPIC12C509AG/509AF is a single channel device. The transmit frequency is fixed and set by an external reference crystal. Transmit frequencies in the range of 310 to 480 MHz can be selected. Output drive is an open-collector differential amplifier. The differential out- put is well suited for loop antennas. Output power is adjustable from +2 dBm to -12 dBm in six discrete steps. The rfPIC12C509AG/509AF are radio frequency (RF) emitting devices. Wireless RF devices are governed by a country’s regulating agency. For example, in the United States it is the Federal Communications Com- mittee (FCC) and in Europe it is the European Confer- ence of Postal and Telecommunications Administrations (CEPT). It is the responsibility of the designer to ensure that their end product conforms to rules and regulations of the country of use and/or sale. RF devices require correct board level implementation in order to meet regulatory requirements. Layout con- siderations are given in Section 7.0 UHF ASK/FSK Transmitter. The rfPIC12C509AG/509AF is available in the cost- effective One-Time-Programmable (OTP) version which is suitable for production in any volume. The cus- tomer can take full advantage of Microchip’s price lead- ership in OTP microcontrollers while benefiting from the OTP’s flexibility. The rfPIC12C509AG/509AF product is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a ‘C’ compiler, a low-cost develop- ment programmer, and a full featured programmer. All the tools are supported on IBM  PC and compatible machines.

1.1 Applications

The rfPIC12C509AG/509AF fits perfectly in applica- tions ranging from wireless remote operation, security systems, to low-power remote transmitters. The EPROM technology makes customizing application programs (transmitter codes, appliance settings, etc.) extremely fast and convenient. The small footprint packages make this rfPIC ™ perfect for applications with space limitations. Low-cost, low-power, high per- formance, ease of use and I/O flexibility make the rfPIC12C509AG/509AF very versatile.

 2001 Microchip Technology Inc. Preliminary DS70031A-page 5 rfPIC12C509AG/509AF TABLE 1-1: rfPIC12C509AG/509AF DEVICE rfPIC12C509AG rfPIC12C509AF Clock Maximum Frequency of Operation (MHz) Memory EPROM Program Memory 1024 x 12 RAM Data Memory (bytes) 41 Peripherals EEPROM Data Memory (bytes) Timer Module(s) TMR0 A/D Converter (8-bit) Channels Features Transmitter ASK ASK, FSK Wake-up from SLEEP on pin change Yes Interrupt Sources — I/O Pins 5 Input Pins 1 Internal Pull-ups Yes In-Circuit Serial Programming Yes Number of Instructions 33 Packages 18-pin JW, SOIC 20-pin JW, SSOP The rfPIC12C509AG/509AF has Power-on Reset, selectable Watchdog Timer, select- able code protect and high I/O current capability. The rfPIC12C509AG/509AF has serial programming with data pin GP0 and clock pin GP1.

DS70031A-page 6 Premilinary  2001 Microchip Technology Inc. NOTES:

 2001 Microchip Technology Inc. Preliminary DS70031A-page 7 rfPIC12C509AG/509AF 2.0 rfPIC12C509AG/509AF DEVICE VARIETIES A variety of packaging options are available. Depend- ing on application and production requirements, the proper device option can be selected using the infor- mation in this section. When placing orders, please use the rfPIC12C509AG/509AF Product Identification Sys- tem at the back of this data sheet to specify the correct part number.

2.1 UV Erasable Devices

The UV erasable version, offered in a windowed ceramic DIP package, is optimal for prototype devel- opment and pilot programs. T h eU Ve r a s a b l ev e r s i o nc a nb ee r a s e da n d reprogrammed to any of the configuration modes. Microchip's PICSTART  PLUS and PRO MATE  pro- grammers all support programming of the rfPIC12C509AG/509AF. Third party programmers also are available; refer to theMicrochip Third Party Guide (DS00104) for a list of sources.

2.2 One-Time-Programmable (OTP)

The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates or small volume applications. The OTP devices, packaged in plastic packages permit the user to program them once. In addition to the program memory, the configuration bits must also be programmed.

2.3 Quick-Turnaround-Production

(QTP)Devices Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and fuse options already programmed by the factory. Certain code and prototype verification procedures do apply before production shipments are available. Please contact your local Microchip Technology sales office for more details.

2.4 Serialized Quick-Turnaround

Production (SQTPSM ) Devices Microchip offers a unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential. Serial programming allows each device to have a unique number which can serve as an entry-code, password or ID number. Note: Please note that erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. The calibration value must be saved prior to erasing the part.

DS70031A-page 8 Preliminary  2001 Microchip Technology Inc. NOTES:

 2001 Microchip Technology Inc. Preliminary DS70031A-page 9 rfPIC12C509AG/509AF

3.0 ARCHITECTURAL OVERVIEW

The rfPIC12C509AG/509AF is a low-cost, high perfor- mance, 8-bit, fully static, EPROM-based CMOS micro- controller combined with a UHF ASK/FSK transmitter. There are no internal electrical connections between the PICmicro MCU and the transmitter. Section 7 has a detailed description of UHF ASK/FSK transmitter.

3.1 PICmicro Microcontroller Unit

The high performance of the rfPIC12C509AG/509AF family can be attributed to a number of architectural features commonly found in RISC microprocessors. T o begin with, the rfPIC12C509AG/509AF uses a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over tra- ditional von Neumann architecture where program and data are fetched on the same bus. Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 12 bits wide making it possible to have all single word instructions. A 12-bit wide program mem- ory access bus fetches a 12-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execu- tion of instructions. Consequently, all instructions (33) execute in a single cycle (1µs @ 4MHz) except for pro- gram branches. The table below lists program memory (EPROM) and data memory (RAM) for each device. The rfPIC12C509AG/509AF can directly or indirectly address its register files and data memory. All special function registers including the program counter are mapped in the data memory. The rfPIC12C509AG/ 509AF has a highly orthogonal (symmetrical) instruc- tion set that makes it possible to carry out any opera- tion on any register using any addressing mode. This symmetrical nature and lack of special optimal situa- tions make programming with the rfPIC12C509AG/ 509AF simple yet efficient. In addition, the learning curve is reduced significantly. The rfPIC12C509AG/509AF contains an 8-bit ALU and working register. The ALU is a general purpose arith- metic unit. It performs arithmetic and Boolean functions between data in the working register and any register file. The ALU is 8 bits wide and capable of addition, subtrac- tion, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's comple- ment in nature. In two-operand instructions, typically one operand is the W (working) register. The other operand is either a file register or an immediate con- stant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow and digit borrowout bit, respec- tively, in subtraction. See theSUBWFand ADDWF instructions for examples.

3.2 UHF ASK/FSK Transmitter

The Transmitter is a fully integrated UHF ASK/FSK transmitter consisting of crystal oscillator, phase- locked loop (PLL), open-collector differential-output Power Amplifier (PA), and mode control logic. External components consist of bypass capacitors, crystal, and PLL loop filter. There are no internal electrical connec- tions between the PICmicro MCU and the transmitter. The rfPIC12C509AG is capable of Amplitude Shift Key- ing (ASK) modulation by turning the PA on and off. The rfPIC12C509AF is capable of ASK or Frequency Shift Keying (FSK) modulation by employing an internal FSK switch to pull the transmitter crystal via a second load capacitor. The PICmicro MCU oscillator is independent from the transmitter crystal oscillator. The transmit frequency is fixed and set by an external reference crystal. Trans- mit frequencies in the range of 310 to 480 MHz can be selected. Output drive is an open-collector differential amplifier. The differential output is well suited for loop antennas. Output power is adjustable from +2 dBm to -12 dBm in six discrete steps. The rfPIC12C509AG/509AF are radio frequency (RF) emitting devices. Wireless RF devices are governed by a country’s regulating agency. For example, in the United States it is the Federal Communications Com- mittee (FCC) and in Europe it is the European Confer- ence of Postal and Telecommunications Administrations (CEPT). It is the responsibility of the designer to ensure that their end product conforms to rules and regulations of the country of use and/or sale. Device Memory EPROM Program RAM Data Transmitter rfPIC12C509AG 1024 x 12 41 ASK rfPIC12C509AF 1024 x 12 41 ASK/FSK

DS70031A-page 10 Preliminary  2001 Microchip Technology Inc. RF devices require correct board level implementation in order to meet regulatory requirements. Layout con- siderations are given in Section 7.0 UHF ASK/FSK Transmitter. A simplified block diagram is shown in Figure 3-1, with the corresponding device pins described in Table 3-1.

 2001 Microchip Technology Inc. Preliminary DS70031A-page 11 rfPIC12C509AG/509AF FIGURE 3-1: rfPIC12C509AG/509AF BLOCK DIAGRAM Device Reset Timer Power-on Reset Watchdog Timer

12 Data Bus 8

Decode & Control Timing GenerationOSC1/CLKIN OSC2 MCLR VDD ,VSS Timer0 GPIO GP4/OSC2 GP3/MCLR /VPP GP2/T0CKI GP1 GP0 5-7 GP5/OSC1/CLKIN STACK1 STACK2 Internal RC OSC RAM 41 x 8 File Registers EPROM 1024 x 12 Program Memory UHF ASK/FSK Transmitter FSK Switch rfPIC12C509AF Only VDDRF CLKOUT PS/DATA ASK DATA FSK FSK OUT XTAL LF ANT2 ANT1 V SSRF RFEN IN (see Figure 7-1)

DS70031A-page 12 Preliminary  2001 Microchip Technology Inc. TABLE 3-1: rfPIC12C509AG/509AF PINOUT DESCRIPTION Name SOIC CERDIP Pin # SSOP Pin # I/O/P Type Buffer Type Description GP0 17 19 I/O TTL/ST Bi-directional I/O port/ serial programming data. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. This buffer is a Schmitt Trigger input when used in serial programming mode. GP1 16 18 I/O TTL/ST Bi-directional I/O port/ serial programming clock. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. This buffer is a Schmitt Trigger input when used in serial programming mode. GP2/T0CKI 15 17 I/O ST Bi-directional I/O port. Can be configured as T0CKI. GP3/MCLR /VPP 4 4 I TTL/ST Input port/master clear (Reset) input/programming voltage input. When configured as MCLR, this pin is an active low RESET to the device. Voltage on MCLR/ VPP must not exceed VDD during normal device opera- tion or the device will enter programming mode. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. Weak pull-up always on if configured as MCLR . ST when in MCLR mode. GP4/OSC2 3 3 I/O TTL Bi-directional I/O port/oscillator crystal output. Con- nections to crystal or resonator in crystal oscillator mode (XT and LP modes only, GPIO in other modes). GP5/OSC1/CLKIN 2 2 I/O TTL/ST Bi-directional IO port/osc illator crystal input/external clock source input (GPIO in Internal RC mode only, OSC1 in all other oscillator modes). TTL input when GPIO, ST input in external RC oscillator mode. V DD 1 1 P — Positive supply for logic and I/O pins VSS 18 20 P — Ground reference for logic and I/O pins RFEN IN 5 6 I TTL Transmitter and CLKOUT enable. Internal pull-down. CLKOUT 6 7 O — Clock output. PS/DATA ASK 7 8 I — Power select and ASK data input. VDDRF 8 9 P — Positive supply for transmitter. ANT2 9 10 O — Antenna connection to differential power amplifier out- put, open collector. ANT1 10 11 O — Antenna connection to differential power amplifier out- put, open collector. VSSRF 11 12 P — Ground reference for transmitter. LF 13 14 — AN External loop filter connection. Common node of charge pump output and VCO tuning input. XTAL 14 5 I — Transmitter crystal connection to colpitts type crystal oscillator. DATA FSK — 15 I TTL FSK data input. FSK OUT — 16 O — FSK crystal pulling output. Legend: I = input, O = output, I/O = input/output, P = power, — = not used, TTL = TTL input, ST = Schmitt Trigger input, AN = analog, CMOS = CMOS

 2001 Microchip Technology Inc. Preliminary DS70031A-page 13 rfPIC12C509AG/509AF

3.3 Clocking Scheme/Instruction

The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the pro- gram counter is incremented every Q1, and the instruc- tion is fetched from program memory and latched into instruction register in Q4. It is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2 and Example 3-1.

3.4 Instruction Flow/Pipelining

An Instruction Cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g.,GOTO) then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 3-2: CLOCK/INSTRUCTION CYCLE EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 PC PC PC+1 PC+2 Fetch INST (PC) Execute INST (PC-1) Fetch INST (PC+1) Execute INST (PC) Fetch INST (PC+2) Execute INST (PC+1) Internal phase clock All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. 1. MOVLW 03H Fetch 1 Execute 1 2. MOVWF GPIO Fetch 2 Execute 2 3. CALL SUB_1 Fetch 3 Execute 3 4. BSF GPIO, BIT1 Fetch 4 Flush Fetch SUB_1 Execute SUB_1

DS70031A-page 14 Preliminary  2001 Microchip Technology Inc. NOTES:

 2001 Microchip Technology Inc. Preliminary DS70031A-page 15 rfPIC12C509AG/509AF

4.0 MEMORY ORGANIZATION

rfPIC12C509AG/509AF memory is organized into pro- gram memory and data memory. For devices with more than 512 bytes of program memory, a paging scheme is used. Program memory pages are accessed using one STATUS register bit. For the rfPIC12C509AG/ 509AF , with a data memory register file of more than 32 registers, a banking scheme is used. Data memory banks are accessed using the File Select Register (FSR).

4.1 Program Memory Organization

The rfPIC12C509AG/509AF devices have a 12-bit Pro- gram Counter (PC) capable of addressing a 2K x 12 program memory space. Only the first 1K x 12 (0000h-03FFh) for the rfPIC12C509AG/509AF is physically implemented. Refer to Figure 4-1. Accessing a location above these boundaries will cause a wrap-around within the first 1K x 12 space. The effective RESET vector is at 000h, (see Figure 4-1). Location 03FFh contains the internal clock oscillator calibration value. This value should never be overwritten. FIGURE 4-1: PROGRAM MEMORY MAP AND STACK CALL, RETLW PC<11:0> Stack Level 1 Stack Level 2 User Memory Space 0000h 7FFh 01FFh 0200h On-chip Program Memory RESET Vector (note 1) Note 1: Address 0000h becomes the effective RESET vector. Location 03FFh contains theMOVLW XX INTERNAL RC oscillator calibra- tion value.

512 Word

1024 Word 03FFh

DS70031A-page 16 Preliminary  2001 Microchip Technology Inc.

4.2 Data Memory Organization

Data memory is composed of registers, or bytes of RAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two functional groups: special function registers and gen- eral purpose registers. The special function registers include the TMR0 regis- ter, the Program Counter (PC), the Status Register, the I/O registers (ports), and the File Select Register (FSR). In addition, special purpose registers are used to control the I/O port configuration and prescaler options. The general purpose registers are used for data and control information under command of the instructions. For the rfPIC12C509AG/509AF, the register file is com- posed of 7 special function registers, 25 general pur- pose registers, and 16 general purpose registers that may be addressed using a banking scheme (Figure 4- 2).

4.2.1 GENERAL PURPOSE REGISTER

The general purpose register file is accessed either directly or indirectly through the file select register FSR FIGURE 4-2: rfPIC12C509AG/509AF REGISTER FILE MAP File Address 00h 01h 02h 03h 04h 05h 06h 07h 1Fh INDF(1) TMR0 PCL STATUS FSR OSCCAL GPIO 0Fh 10h Bank 0 Bank 1 3Fh 30h 20h 2Fh General Purpose Registers General Purpose Registers General Purpose Registers Addresses map back to addresses in Bank 0. Note 1: Not a physical register. See Section 4.8 FSR<6:5> 00 01

 2001 Microchip Technology Inc. Preliminary DS70031A-page 17 rfPIC12C509AG/509AF

4.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers used by the CPU and peripheral functions to control the operation of the device (Table 4-1). The special registers can be classified into two sets. The special function registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature. TABLE 4-1: SPECIAL FUNCTION REGISTER (SFR) SUMMARY Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on All Other RESETS (2) N/A TRIS — — --11 1111 --11 1111 N/A OPTION Contains control bits to configure Timer0, Timer0/WDT prescaler, wake-up on change, and weak pull-ups 1111 1111 1111 1111 00h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu 01h TMR0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu 02h(1) PCL Low order 8 bits of PC 1111 1111 1111 1111 03h STATUS GPWUF —P A 0 T O PD ZD C C 0001 1xxx q00q quuu(3) 04h FSR Indirect data memory address pointer 110x xxxx 11uu uuuu 05h OSCCAL CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — — 1000 00-- uuuu uu-- 06h GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu Legend: Shaded boxes = unimplemented or unused,—= unimplemented, read as '0' (if applicable) x= unknown,u= unchanged,q= see the tables in Section 8.7 for possible values. Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.6 for an explanation of how to access these bits. 2: Other (non power-up) RESETS include external RESET through MCLR, Watchdog Timer and Wake-up-on- Pin Change Reset. 3: If RESET was due to Wake-up-on-Pin Change then bit 7 = 1. All other RESETS will cause bit 7 = 0.

DS70031A-page 18 Preliminary  2001 Microchip Technology Inc.

4.3 STATUS Register

This register contains the arithmetic status of the ALU, the RESET status, and the page preselect bit for pro- gram memories larger than 512 words. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example,CLRF STATUSwill clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu(whereu= unchanged). It is recommended, therefore, that onlyBCF,BSFand MOVWFinstructions be used to alter the STATUS regis- ter because these instructions do not affect the Z, DC or C bits from the STATUS register. For other instruc- tions, which do affect STATUS bits, see Instruction Set Summary. figure 4-3: STATUS REGISTER (ADDRESS:03h) R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x GPWUF — PA0 TO PD Z DC C R = Readable bit W = Writable bit - n = Value at POR Reset bit7 6 5 4 3 2 1 bit0 bit 7: GPWUF : GPIO Reset bit 1 = Reset due to wake-up from SLEEP on pin change 0 = After power-up or other RESET bit 6: Unimplemented bit 5: PA0 : Program page preselect bits 1 = Page 1 (200h - 3FFh) 0 = Page 0 (000h - 1FFh Each page is 512 bytes. Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program page preselect is not recommended since this may affect upward compatibility with future products. bit 4: TO : Time-out bit 1 = After power-up,CLRWDTinstruction, orSLEEPinstruction 0 = A WDT time-out occurred bit 3: PD : Power-down bit 1 = After power-up or by theCLRWDTinstruction 0 = By execution of theSLEEPinstruction bit 2: Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1: DC : Digit carry/borrowbit (forADDWFand SUBWFinstructions) ADDWF 1 = A carry from the 4th low order bit of the result occurred 0 = A carry from the 4th low order bit of the result did not occur SUBWF 1 = A borrow from the 4th low order bit of the result did not occur 0 = A borrow from the 4th low order bit of the result occurred bit 0: C : Carry/borrow bit (forADDWF,SUBWFand RRF,RLFinstructions) ADDWF SUBWF RRF or RLF 1 = A carry occurred 1 = A borrow did not occur Load bit with LSB or MSB, respectively 0 = A carry did not occur 0 = A borrow occurred

 2001 Microchip Technology Inc. Preliminary DS70031A-page 19 rfPIC12C509AG/509AF

4.4 OPTION Register

The OPTION register is a 8-bit wide, write-only register which contains various control bits to configure the Timer0/WDT prescaler and Timer0. By executing theOPTIONinstruction, the contents of the W register will be transferred to the OPTION regis- ter. A RESET sets the OPTION<7:0> bits. FIGURE 4-4: OPTION REGISTER Note: If TRIS bit is set to ‘0’, the wake-up on change and pull-up functions are disabled for that pin (i.e., note that TRIS overrides OPTION control of GPPU and GPWU) . Note: If the T0CS bit is set to ‘1’, GP2 is forced to be an input even if TRIS GP2 = ‘0’. W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1 GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 W = Writable bit U = Unimplemented bit - n = Value at POR Reset Reference Table 4-1 for other RESETS. bit7 6 5 4 3 2 1 bit0 bit 7: GPWU :Enable wake-up on pin change (GP0, GP1, GP3) 1 = Disabled 0 = Enabled bit 6: GPPU : Enable weak pull-ups (GP0, GP1, GP3) 1 = Disabled 0 = Enabled bit 5: T0CS : Timer0 clock source select bit 1 = Transition on T0CKI pin 0 = Transition on internal instruction cycle clock, Fosc/4 bit 4: T0SE : Timer0 source edge select bit 1 = Increment on high to low transition on the T0CKI pin 0 = Increment on low to high transition on the T0CKI pin bit 3: PSA : Prescaler assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0 bit 2-0:PS2:PS0 : Prescaler rate select bits 000 001 010 011 100 101 110 111 1:2 1:4 1:8 1:1 6 1:3 2 1:6 4 1:1 2 8 1:2 5 6 1:1 1:2 1:4 1:8 1:1 6 1:3 2 1:6 4 1:1 2 8 Bit Value Timer0 Rate WDT Rate

DS70031A-page 20 Preliminary  2001 Microchip Technology Inc.

4.5 OSCCAL Register

The Oscillator Calibration (OSCCAL) register is used to calibrate the internal 4 MHz oscillator. It contains six bits for calibration. Increasing the cal value increases the frequency. See Section 8.2.5 for more information on the internal oscillator. FIGURE 4-5: OSCCAL REGISTER (ADDRESS 05h) R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — — R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR Reset bit7 bit0 bit 7-2:CAL<5:0>: Calibration bit 1-0:Unimplemented: Read as '0'

 2001 Microchip Technology Inc. Preliminary DS70031A-page 21 rfPIC12C509AG/509AF

4.6 Program Counter

As a program instruction is executed, the Program Counter (PC) will contain the address of the next pro- gram instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC. For aGOTOinstruction, bits 8:0 of the PC are provided by theGOTOinstruction word. The PC Latch (PCL) is mapped to PC<7:0>. Bit 5 of the STATUS register pro- vides page information to bit 9 of the PC (Figure 4-6). For a CALLinstruction, or any instruction where the PCL is the destination, bits 7:0 of the PC again are pro- vided by the instruction word. However, PC<8> does not come from the instruction word, but is always cleared (Figure 4-6). Instructions where the PCL is the destination, or Modify PCL instructions, includeMOVWF PC, ADDWF PC,and BSF PC,5. FIGURE 4-6: LOADING OF PC BRANCH INSTRUCTIONS - rfPIC12C509AG/509AF

4.6.1 EFFECTS OF RESET

The Program Counter is set upon a RESET , which means that the PC addresses the last location in the last page (i.e., the oscillator calibration instruction). After executing MOVLW XX, the PC will roll over to location 00h, and begin executing user code. The STATUS register page preselect bits are cleared upon a RESET, which means that page 0 is pre- selected. Therefore, upon a RESET, a GOTOinstruction will auto- matically cause the program to jump to page 0 until the value of the page bits is altered.

4.7 Stack

The rfPIC12C509AG/509AF device has a 12-bit wide A CALLinstruction will push the current value of stack 1 into stack 2 and then push the current program counter value, incremented by one, into stack level 1. If more than two sequentialCALL’s are executed, only the most recent two return addresses are stored. A RETLWinstruction will pop the contents of stack level 1 into the program counter and then copy stack level 2 contents into level 1. If more than two sequential RETLW’s are executed, the stack will be filled with the address previously stored in level 2. Note that the W register will be loaded with the literal value specified in the instruction. This is particularly useful for the implementation of data look-up tables within the pro- gram memory. Upon any RESET, the contents of the stack remain unchanged, however the program counter (PCL) will also be Reset to 0. Note: Because PC<8> is cleared in theCALL instruction, or any Modify PCL instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any pro- gram memory page (512 words long). PA0 STATUS PC 87 0 PCL 910 Instruction Word GOTO Instruction CALL or Modify PCL Instruction PA0 STATUS PC 87 0 PCL 910 Instruction Word Reset to ‘0’ Note 1: There are no STATUS bits to indicate stack overflows or stack underflow condi- tions. 2: There are no instructions mnemonics called PUSH or POP . These are actions that occur from the execution of theCALL and RETLWinstructions.

DS70031A-page 22 Preliminary  2001 Microchip Technology Inc.

4.8 Indirect Data Addressing; INDF

The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing. EXAMPLE 4-1: INDIRECT ADDRESSING

• Register file 07 contains the value 10h
• R e g i s t e rf i l e0 8c o n t a i n st h ev a l u e0 A h
• Load the value 07 into the FSR register
• A read of the INDF register will return the value of 10h
• Increment the value of the FSR register by one (FSR = 08)
• A read of the INDR register now will return the value of 0Ah. Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected). A simple program to clear RAM locations 10h-1Fh using indirect addressing is shown in Example 4-2. EXAMPLE 4-2: HOW TO CLEAR RAM USING INDIRECT ADDRESSING movlw 0x10 ;initialize pointer movwf FSR ; to RAM NEXT clrf INDF ;clear INDF register incf FSR,F ;inc pointer btfsc FSR,4 ;all done? goto NEXT ;NO, clear next CONTINUE : ;YES, continue T h eF S Ri sa5 - b i tw i d er e g i s t e r .I ti su s e di nc o n j u n c - tion with the INDF register to indirectly address the data memory area. The FSR<4:0> bits are used to select data memory addresses 00h to 1Fh. rfPIC12C509AG/509AF: Uses FSR<5>. Selects between bank 0 and bank 1. FSR<7:6> is unimple- mented, read as '1’. FIGURE 4-7: DIRECT/INDIRECT ADDRESSING Note 1: For register map detail see Section 4.2. bank location selectlocation selectbank select Indirect AddressingDirect Addressing Data Memory (1) 0Fh 10h Bank 0 Bank 1 0456 (FSR) 00 01 00h 1Fh 3Fh (opcode) 0456 (FSR) Addresses map back to addresses in Bank 0.

 2001 Microchip Technology Inc. Preliminary DS70031A-page 23 rfPIC12C509AG/509AF

5.0 I/O PORT

As with any other register, the I/O register can be writ- ten and read under program control. However, read instructions (e.g.,MOVF GPIO,W) always read the I/O pins independent of the pin’s input/output modes. On RESET, all I/O ports are defined as input (inputs are at hi-impedance) since the I/O control registers are all set.

5.1 GPIO

GPIO is an 8-bit I/O register. Only the low order 6 bits are used (GP5:GP0). Bits 7 and 6 are unimplemented and read as '0's. Please note that GP3 is an input only pin. The configuration word can set several I/O’s to alternate functions. When acting as alternate functions the pins will read as ‘0’ during port read. Pins GP0, GP1, and GP3 can be configured with weak pull-ups and also with wake-up on change. The wake-up on change and weak pull-up functions are not pin select- able. If pin 4 is configured as MCLR , weak pull-up is always on and wake-up on change for this pin is not enabled.

5.2 TRIS Register

The output driver control register is loaded with the contents of the W register by executing theTRIS f instruction. A '1' from a TRIS register bit puts the corre- sponding output driver in a hi-impedance mode. A '0' puts the contents of the output data latch on the selected pins, enabling the output buffer. The excep- tions are GP3 which is input only and GP2 which may be controlled by the option register, see Figure 4-4. The TRIS registers are “write-only” and are set (output drivers disabled) upon RESET.

5.3 I/O Interfacing

The equivalent circuit for an I/O port pin is shown in Figure 5-1. All port pins, except GP3 which is input only, may be used for both input and output operations. For input operations these ports are non-latching. Any input must be present until read by an input instruction (e.g.,MOVF GPIO,W). The outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding direction control bit in TRIS must be cleared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O pin (except GP3) can be programmed individually as input or output. FIGURE 5-1: EQUIVALENT CIRCUIT FOR A SINGLE I/O PIN Note: A read of the ports reads the pins, not the output data latches. That is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low. Data Bus QD QCK QD QCK P N WR Port TRIS ‘f’ Data TRIS RD Port VSS VDD I/O pin(1) W Reg Latch Latch Reset (2) Note 1: I / Op i n sh a v ep r o t e c t i o nd i o d e st oVDD and VSS . 2: See Table 3-1 for buffer type.

DS70031A-page 24 Preliminary  2001 Microchip Technology Inc. TABLE 5-1: SUMMARY OF PORT REGISTERS

5.4 I/O Programming Considerations

5.4.1 BI-DIRECTIONAL I/O PORTS

Some instructions operate internally as read followed by write operations. TheBCFand BSFinstructions, for example, read the entire port into the CPU, execute the bit operation and re-write the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. For example, aBSFo p e r a t i o no nb i t 5o fG P I Ow i l lc a u s ea l l eight bits of GPIO to be read into the CPU, bit5 to be set and the GPIO value to be written to the output latches. If another bit of GPIO is used as a bi-direc- tional I/O pin (say bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched into output mode later on, the content of the data latch may now be unknown. Example 5-1 shows the effect of two sequential read- modify-write instructions (e.g.,BCF, BSF, etc.) on an I/ Op o r t . A pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin (“wired-or”, “wired-and”). The resulting high output currents may damage the chip. EXAMPLE 5-1: Read-Modify-Write Instructions on an I/O Port ;Initial GPIO Settings ; GPIO<5:3> Inputs ; GPIO<2:0> Outputs ; GPIO latch GPIO pins BCF GPIO, 5 ;--01 -ppp --11 pppp BCF GPIO, 4 ;--10 -ppp --11 pppp MOVLW 007h ; TRIS GPIO ;--10 -ppp --11 pppp ;Note that the user may have expected the pin ;values to be --00 pppp. The 2nd BCF caused ;GP5 to be latched as the pin value (High).

5.4.2 SUCCESSIVE OPERATIONS ON I/O

The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5- 2). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should allow the pin volt- age to stabilize (load dependent) before the next i n s t r u c t i o n ,w h i c hc a u s e st h a tf i l et ob er e a di n t ot h e CPU, is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instruc- tions with aNOPor another instruction not accessing this I/O port. Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on All Other RESETS N/A TRIS — — --11 1111 --11 1111 N/A OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 03H STATUS GPWUF — PAO TO PD Z DC C 0001 1xxx q00q quuu(1) 06h GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu Legend: Shaded cells not used by Port Registers, read as ‘0’, — = unimplemented, read as '0',x= unknown,u= unchanged, q = see tables in Section 8.7 for possible values. Note 1: If reset was due to wake-up on change, then bit 7 = 1. All other resets will cause bit 7 = 0.

 2001 Microchip Technology Inc. Preliminary DS70031A-page 25 rfPIC12C509AG/509AF FIGURE 5-2: SUCCESSIVE I/O OPERATION P C P C+1 P C+2 P C+3 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Instruction fetched GP5:GP0 MOVWF GPIO NOP Port pin sampled here NOPMOVF GPIO,W Instruction executed MOVWF GPIO (Write to GPIO) NOPMOVF GPIO,W This example shows a write to GPIO followed b yar e a df r o mG P I O . Data setup time = (0.25 TCY –T PD ) where: TCY = instruction cycle. TPD = propagation delay Therefore, at higher clock frequencies, a write followed by a read may be problematic. (Read GPIO) Port pin written here

DS70031A-page 26 Preliminary  2001 Microchip Technology Inc. NOTES:

 2001 Microchip Technology Inc. Preliminary DS70031A-page 27 rfPIC12C509AG/509AF

6.0 TIMER0 MODULE AND TMR0

The Timer0 module has the following features:

• 8-bit timer/counter register, TMR0 - Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select - Edge select for external clock Figure 6-1 is a simplified block diagram of the Timer0 module. Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If TMR0 register is written, the increment is inhibited for the following two instruction cycles (Figure 6-2 and Figure 6-3). The user can work around this by writing an adjusted value to the TMR0 register. Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The T0SE bit (OPTION<4>) determines the source edge. Clearing the T0SE bit selects the rising edge. Restric- tions on the external clock input are discussed in detail in Section 6.1. The prescaler may be used by either the Timer0 mod- ule or the Watchdog Timer, but not both. The prescaler assignment is controlled in software by the control bit PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0. FIGURE 6-1: TIMER0 BLOCK DIAGRAM Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register. 2: The prescaler is shared with the Watchdog Timer (Figure 6-5). T0CS (1) FOSC /4 Programmable Prescaler(2) Sync with Internal Clocks TMR0 reg PSout (2 TCY delay) PSout Data bus PSA (1)PS2, PS1, PS0(1) SyncT0SE GP2/T0CKI Pin

 2001 Microchip Technology Inc. Preliminary DS70031A-page 29 rfPIC12C509AG/509AF

6.1 Using Timer0 with an External

When an external clock input is used for Timer0, it must meet certain requirements. The external clock require- ment is due to internal phase clock (T OSC ) synchroniza- tion. Also, there is a delay in the actual incrementing of Timer0 after synchronization.

6.1.1 EXTERNAL CLOCK

When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accom- plished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 6-4). Therefore, it is necessary for T0CKI to be high for at least 2T OSC (and a small RC delay of 20 ns) and low for at least 2TOSC (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device. When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type pres- caler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. There- fore, it is necessary for T0CKI to have a period of at least 4T OSC (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the mini- mum pulse width requirement of 10 ns. Refer to param- eters 40, 41 and 42 in the electrical specification of the desired device.

6.1.2 TIMER0 INCREMENT DELAY

Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 mod- ule is actually incremented. Figure 6-4 shows the delay from the external clock edge to the timer incrementing.

6.1.3 OPTION REGISTER EFFECT ON

If the option register is set to read TIMER0 from the pin, the port is forced to an input regardless of the TRIS reg- ister setting. FIGURE 6-4: TIMER0 TIMING WITH EXTERNAL CLOCK Increment Timer0 (Q4) External Clock Input or Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Timer0 T0 T0 + 1 T0 + 2 Small pulse misses sampling External Clock/Prescaler Output After Sampling (3) Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input =± 4Tosc max. External clock if no prescaler selected, Prescaler output otherwise. The arrows indicate the points in time where sampling occurs. Prescaler Output(2) (1)

DS70031A-page 30 Preliminary  2001 Microchip Technology Inc.

6.2 Prescaler

An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer (WDT), respectively (Section 8.6). For simplicity, this counter is being referred to as “prescaler” through- out this data sheet. Note that the prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT, and vice-versa. The PSA and PS2:PS0 bits (OPTION<3:0>) determine prescaler assignment and prescale ratio. When assigned to the Timer0 module, all instructions w r i t i n gt ot h eT M R 0r e g i s t e r( e . g . ,CLRF 1, MOVWF 1, BSF 1,x,etc.) will clear the prescaler. When assigned to WDT, aCLRWDTinstruction will clear the prescaler along with the WDT . The prescaler is nei- ther readable nor writable. On a RESET, the prescaler contains all '0's.

6.2.1 SWITCHING PRESCALER

The prescaler assignment is fully under software con- trol (i.e., it can be changed “on the fly” during program execution). To avoid an unintended device RESET, the following instruction sequence (Example 6-1) must be executed when changing the prescaler assignment from Timer0 to the WDT . EXAMPLE 6-1: Changing Prescaler (Timer0→ WDT) 1.CLRWDT ;Clear WDT 2.CLRF TMR0 ;Clear TMR0 & Prescaler 3.MOVLW '00xx1111’b;These 3 lines (5, 6, 7) 4.OPTION ; are required only if ; desired 5.CLRWDT ;PS<2:0> are 000 or 001 6.MOVLW '00xx1xxx’b ;Set Postscaler to 7.OPTION ; desired WDT rate To change prescaler from the WDT to the Timer0 mod- ule, use the sequence shown in Example 6-2. This sequence must be used even if the WDT is disabled. A CLRWDTinstruction should be executed before switch- ing the prescaler. EXAMPLE 6-2: Changing Prescaler (WDT → Timer0) CLRWDT ;Clear WDT and ;prescaler MOVLW 'xxxx0xxx' ;Select TMR0, new ;prescale value and ;clock source OPTION

 2001 Microchip Technology Inc. Preliminary DS70031A-page 31 rfPIC12C509AG/509AF FIGURE 6-5: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER TCY ( = Fosc/4) Sync Cycles TMR0 reg 8-bit Prescaler 8-t o-1 M U X M MUX Watchdog Timer PSA 0 1 WDT Time-Out PS2:PS0 Note:T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register. PSA WDT Enable bit Data Bus PSA T0CS M U X M U X U X T0SE GP2/T0CKI Pin

DS70031A-page 32 Preliminary  2001 Microchip Technology Inc. NOTES:

 2001 Microchip Technology Inc. Preliminary DS70031A-page 33 rfPIC12C509AG/509AF

7.0 UHF ASK/FSK TRANSMITTER

7.1 Transmitter Operation

The transmitter is a fully integrated UHF ASK/FSK transmitter consisting of crystal oscillator, phase- locked loop (PLL), open-collector differential-output Power Amplifier (PA), and mode control logic. External components consist of bypass capacitors, crystal, and PLL loop filter. The rfPIC12C509AG is capable of Amplitude Shift Keying (ASK) modulation. The rfPIC12C509AF is capable of ASK or Frequency Shift Keying (FSK) modulation by employing an internal FSK switch to pull the transmitter crystal via a second load capacitor. Figure 7-1 shows the internal structure of the transmit- ter. Transmitter connections are independent from the PICmicro microcontroller unit (MCU) to provide for maximum design flexibility. Example application cir- cuits for ASK or FSK modulation are presented at the end of this section. The rfPIC12C509AG/509AF are radio frequency (RF) emitting devices. Wireless RF devices are governed by a country’s regulating agency. For example, in the United States it is the Federal Communications Com- mittee (FCC) and in Europe it is the European Confer- ence of Postal and Telecommunications Administrations (CEPT). It is the responsibility of the designer to ensure that their end product conforms to rules and regulations of the country of use and/or sale.

7.2 Supply Voltage (V DDRF ,VSSRF )

Pins VDDRF and V SSRF supply power and ground respectively to the transmitter. These power pins are separate from power supply pins V DD and VSS to the PICmicro MCU.

7.3 Crystal Oscillator

The transmitter crystal oscillator is a Colpitts oscillator that provides the reference frequency to the PLL. It is independent from the PICmicro oscillator. An external crystal or AC coupled reference signal is connected to the XTAL pin. The transmit frequency is fixed and determined by the crystal frequency according to the formula: Due to the flexible selection of transmit frequency, the resulting crystal frequency may not be a standard off- the-shelf value. Therefore, for some carrier frequencies the designer will have to consult a crystal manufacturer and have a custom crystal manufactured. Crystal parameters are listed in T able 7-1. For background information on crystal selection see Application Note AN588, PICmicro ® Microcontroller Oscillator Design Guide. The crystal oscillator start time (ton)i sl i s t e di n Table 11-10, Transmitter AC Characteristics. TABLE 7-1: CRYSTAL PARAMETERS RF devices require correct board level implementa- tion in order to meet regulatory requirements. Layout considerations are listed at the end of each subsec- tion. It is best to place a ground plane on the PCB to reduce radio frequency emmissions and cross talk. Layout Considerations- Provide low impedance power and ground traces to minimize spurious emis- sions. A two-sided PCB with a ground plane on the bottom layer is highly recommended. Separate bypass capacitors should be connected as close as possible to each of the supply pins V DD and VDDRF . Connect VSS and VSSRF to the ground plane using separate PCB vias. Do not share a PCB via with mul- tiple ground traces. 32×= XTALtransmit ff Sym Characteristic Min Max Units Conditions fXTAL Crystal Frequency 9.69 15 MHz Parallel Resonant Mode C L Load Capacitance 10 15 pF C O Shunt Capacitance — 7 pF ESR Equivalent Series Resistance — 60 Ω These values are for design guidance only.

DS70031A-page 34 Preliminary  2001 Microchip Technology Inc. FIGURE 7-1: rfPIC12C509AG/509AF TRANSMITTER BLOCK DIAGRAM RFEN IN Divide by 4 Mode Control Logic CLKOUT Power Amplifier (PA) Crystal Oscillator ANT2 ANT1 XTAL Phase Frequency Detector and Charge Pump Voltage Controlled Oscillator (VCO) Fixed Divide by 32 LF PS/DATA ASK DATA FSK FSK OUT rfPIC12C509AF Only FSK Switch

 2001 Microchip Technology Inc. Preliminary DS70031A-page 35 rfPIC12C509AG/509AF

7.3.1 CRYSTAL OSCILLATOR ASK

The rfPIC12C509AG or 509AF crystal oscillator can be configured for ASK operation. Figure 7-2 shows an example ASK circuit. Capacitor C1 trims the crystal load capacitance to the circuit load capacitance and places the crystal on the desired frequency. FIGURE 7-2: EXAMPLE ASK EXTERNAL CRYSTAL CIRCUIT TABLE 7-2: XTAL OSC APPROXIMATE FREQ. VS. CAPACITANCE (ASK MODE) (1) XTAL rfPIC12C509AG/ 509AF C1 Predicted Frequency (MHz) PPM from 13.55 MHz Transmit Frequency (MHz) (32 * fXTAL ) 22 pF 13.551438 +106 433.646 39 pF 13.550563 +42 433.618 100 pF 13.549844 -12 433.595 150 pF 13.549672 -24 433.5895 470 pF 13.549548 -33 433.5856 1000 pF 13.549344 -48 433.579 Note 1: Standard Operating Conditions (unless otherwise stated) T A = 25°C, RFEN =1 ,VDDRF =3 V , fXTAL = 13.55 MHz

DS70031A-page 36 Preliminary  2001 Microchip Technology Inc.

7.3.2 CRYSTAL OSCILLATOR FSK

The rfPIC12C509AF crystal oscillator can be config- ured for FSK operation. Figure 7-3 shows an example FSK circuit. Capacitors C1 and C2 achieve FSK modu- lation by pulling the crystal. When DATA FSK = 1, FSK- OUT is high-impedance effectively coupling only capacitor C1 to the crystal and the resulting transmit frequency equals f MAX .W h e nD A T AFSK = 0, FSKOUT is grounded to VSSRF and will parallel capacitor C2 with C1. The resulting transmit frequency will equal fMIN . Selecting the appropriate values for C1 and C2 sets the center frequency and frequency deviation. Capacitor C1 sets f MAX and capacitors C1 and C2 in parallel set fMIN . The graph in Figure 7-4 illustrates this relation- ship. The transmit center frequency fC is defined as: The frequency deviation of the transmit frequency is defined as: TABLE 7-3: TYPICAL TRANSMIT CENTER FREQUENCY AND FREQUENCY DEVIATION (FSK MODE) (1) FIGURE 7-3: EXAMPLE FSK EXTERNAL CRYSTAL CIRCUIT FIGURE 7-4: LOAD CAPACITANCE VERSUS CHANGE IN TRANSMITTED FREQUENCY Layout considerations- Avoid parallel traces in order to reduce circuit stray capacitance. Keep traces as short as possible. Isolate components to prevent cou- pling. Use ground traces to isolate signals. minmax fffc minmax fff −=Δ C2 = 1000 pF C2 = 100 pF C2 = 47 pF C1 (pF) Freq (MHz) / Dev (kHz) Freq (MHz) / Dev (kHz) Freq (MHz) / Dev (kHz) 22 433.612 / 34 433.619 / 27 433.625 / 21 33 433.604 / 25 433.610 / 19 433.614 / 14 39 433.598 / 20 433.604 / 14 433.608 / 10 47 433.596 / 17 433.601 / 11.5 433.604 / 8 68 433.593 / 13 433.598 / 9 433.600 / 5.5 100 433.587 / 8 — — Note 1: Standard Operating Conditions (unless otherwise stated) T A = 25°C, RFEN =1 ,VDDRF =3 V , fXTAL =1 3 . 5 5M H z XTAL rfPIC12C509AF FSKOUT Frequency (MHz) Fmax Fmin C1 C1||C2 DATA FSK =1 DATA FSK =0 Load Capacitance (pF)

 2001 Microchip Technology Inc. Preliminary DS70031A-page 37 rfPIC12C509AG/509AF

7.4 Clock Output (CLKOUT)

The crystal oscillator feeds a divide-by-four circuit that provides a clock output at the CLKOUT pin. The CLK- OUT signal can be used as an input to the microcon- troller or other external circuitry requiring a stable reference frequency. Do not connect the CLKOUT sig- nal to the PICmicro OSC1 input because the PICmicro cannot run when there is no clock signal and therefore cannot enable the transmitter oscillator. It is required that the PICmicro be clocked externally or via the inter- nal RC oscillator (see Section 8.2). Connect CLKOUT to GP2/T0CKI input and use the Timer0 module if the application requires a stable refer- ence frequency. CLKOUT is slew-rate limited in order to keep spurious signal emissions as low as possible. The voltage swing CLKOUT ) depends on the capacitive loading (CLOAD ) on the CLKOUT pin (2 VPP at 5 pF).

7.5 Phase-Locked Loop (PLL)

The PLL consists of a phase-frequency detector (PFD), charge pump, voltage-controlled oscillator (VCO), and fixed divide-by-32 divider. An external loop filter is con- nected to pin LF. The loop filter controls the dynamic behavior of the PLL, primarily lock time and spur levels. The application determines the loop filter requirements. The rfPIC ™ employs a charge pump PLL that offers many advantages over the classical voltage phase detector PLL: infinite pull-in range and zero steady state phase error. The charge pump PLL allows the use of passive loop filters that are lower cost and mini- mize noise. Charge pump PLLs have reduced flicker noise thus limiting phase noise. Many of the classical texts on PLLs do not cover this type of PLL, however, today this is the most common type of PLL. This data sheet briefly covers the general terms and design requirements for the rfPIC. Detailed PLL design and operation is beyond the scope of this data sheet. For more information, the designer is referred to " PLL Per- formance, Simulation, and Design," Second Edition by Dean Banerjee ISBN 0970820704. Banerjee covers charge pump PLLs and loop filter selection. The loop filter has a major impact on lock time and spur levels. Lock time is the time it takes the PLL to lock on frequency. When the PLL is first powered on or is changing frequencies, no data can be transmitted. Lock time must be considered before data transmission can begin. In addition to PLL lock time, the designer must take into account the crystal oscillator start time of approximately 1 ms. See Section 7.3 for more informa- tion about the crystal oscillator. Reference spurs occur at the carrier frequency plus and minus integer multi- ples of the reference frequency. Phase noise refers to noise generated by the PLL. Spur levels and phase noise can increase the signal to noise ratio (SNR) of the system and mask or degrade the transmitted sig- nal. The first order effect on PLL performance is loop band- width. Loop bandwidth (ω c) is defined as the point where the open loop phase transfer function equals 0 dB. Selecting a small loop bandwidth results in lower spur levels but slower lock time. Selecting a larger loop bandwidth results in a faster lock time but higher spur levels. Second order effects on PLL performance is Phase margin (φ)a n dD a m p i n gf a c t o r(ζ). Phase margin is a measure of PLL stability. Choosing a phase margin that is too low will result in PLL instability. Choosing a higher phase margin results in less ringing and faster lock time at the expense of higher spur levels. Loop fil- ters are typically designed for a total phase margin between 30 and 70 degrees. The aim of the designer is to choose a loop bandwidth and phase margin that gives the fastest possible lock time and meets the spur level requirements of the application. Damping factor governs the second order transient response that determines the shape of the exponential envelope of the natural frequency. The natural fre- quency, also called ringing frequency, is the frequency of the VCO steering voltage as the PLL settles. Lock time is proportional to damping factor and inversely proportional to loop bandwidth. The application determines the loop filter component requirements. For example, if the transmit frequency selected is near band edges or restricted bands, spur levels must be reduced to meet regulatory require- ments. However, this will be at the expense of lock time. For an FSK application, a larger damping factor (≅ 1.0) is desired so that there is less overshoot in the keying of FSK. For an ASK application, a damping fac- tor = 0.707 results in less settling time and near opti- mum noise performance. Figure 7-5 shows an example passive second order loop filter circuit. Table 7-4 gives example loop filter values for a crystal frequency of 13.56 MHz and trans- mit frequency of 433.92 MHz. Layout considerations- Shield each side of the clock output trace with ground traces to isolate the CLK- OUT signal and reduce coupling. Layout considerations- Keep traces short and place loop filter components as close as possible to the LF pin.

DS70031A-page 38 Preliminary  2001 Microchip Technology Inc. FIGURE 7-5: EXAMPLE LOOP FILTER CIRCUIT TABLE 7-4: EXAMPLE LOOP FILTER VALUES (1) LF rfPIC12C509AG C1C2 C1 C2 R1 Loop BW Fn (natural freq in Hz) Phase Margin (not counting sampling delay) 2nd Order damping factor Calculated Lock Time 0.01 uF 390 pF 680 165 kHz 64 kHz 65 deg 1.37 51 µS 3900 pF 100 pF 1.5K 360 kHz 103 kHz 63 deg 1.89 16 µS 1500 pF 47 pF 2.7K 610 kHz 166 kHz 55 deg 2.10 10 µS 1000 pF 18 pF 4.7K 1.05 MHz 203 kHz 50 deg 3.0 8 µS Note 1: Standard Operating Conditions (unless otherwise stated) TA = 25°C, RFEN =1 ,VDDRF =3 V , fTRANSMIT = 433.92 MHz

 2001 Microchip Technology Inc. Preliminary DS70031A-page 39 rfPIC12C509AG/509AF

7.6 Power Amplifier

The PLL output feeds the power amplifier (PA). The open-collector differential output (ANT1, ANT2) can be used to drive a loop antenna directly or converted to single-ended output via an impenance matching net- work or balanced-to-unbalanced (balun) transformer. Pins ANT1 and ANT2 are open-collector outputs and must be pulled-up to V DDRF through the load. The differential output of the PA should be matched to an impedance of 1 kΩ. Failure to match the impedance will cause excessive spurious and harmonic emissions. The transmit output power can be adjusted in six dis- crete steps from +2 dBm to -12 dBm by varying the volt- age (VPS ) at the PS/DATAASK pin. Figure 7-6 shows an example voltage divider network for ASK operation and Figure 7-7 for FSK operation. For FSK operation, the PS/DATA ASK pin only serves as a Power Select (PS) pin. An internal 20µA current source pushes current through the PS/DATAASK pin resulting in a voltage drop across resistor R2 at the VPS level selected for transmitter output power. VPS selects the PA bias current. Higher transmit power will draw higher current. For ASK operation, the function of the PS/DATA ASK pin is to turn the Power Amplifier (PA) on and off. Resistors R1 and R2 form a voltage divider network to apply volt- age V PS for the selected transmitter output power. If maximum transmitter output is desired, the output of a GP0 pin can be connected directly to PS/DATAASK . Table 7-5 lists typical values for R1 and R2 for both the ASK and FSK modes. FIGURE 7-6: EXAMPLE ASK POWER SELECT CIRCUIT FIGURE 7-7: EXAMPLE FSK POWER SELECT CIRCUIT TABLE 7-5: POWER SELECT (1) PS/DATAASK rfPIC12C509AG DATA IN VPS 20µA To power select circuitry PS/DAT AASK rfPIC12C509AF VPS 20µA To power select circuitry Transmitter Output Power (dBm) Transmitter Operating Current (mA) Power Select (PS) Voltage VPS (Volts)(2) ASK FSK +2 11.5 ≥2.0 2400 4700 ≥75K -1 8.6 1.2 6800 4700 56K -4 7.3 0.9 11K 4700 47K -7 6.2 0.7 15K 4700 39K -10 5.3 0.5 24K 4700 27K -12 4.8 0.3 43K 4700 15K -60 <4.8 <0.1 OPEN 4700 4700 Note 1: Standard Operating Conditions (unless otherwise stated) T A = 25°C, RFEN =1 , VDDRF =3 V ,fTRANSMIT = 433.92 MHz 2: VPS is actual voltage on PS/DATAASK pin. 3: The Power Select circuitry contains an internal 20µA current source. T o ensure that the transmitter output power is at the minimum when transmitting a DATAASK =0( VSSRF ), select the value of resistor R2 such that the voltage drop across it is less than 0.1 volts.

DS70031A-page 40 Preliminary  2001 Microchip Technology Inc.

7.7 Mode Control Logic

The mode control logic pin RFENIN controls the oper- ation of the transmitter (T able 7-6). When RFENIN = 1 the transmitter and CLKOUT are enabled. When RFEN IN = 0 the transmitter and CLKOUT are in standby mode. In standby mode the transmitter draws the least amount of current. The RFENIN pin has an internal pull-down resistor. TABLE 7-6: RFEN IN PIN STATES RF EN Description

0 Transmitter and CLKOUT in Standby

1 Transmitter and CLKOUT enabled

 2001 Microchip Technology Inc. Preliminary DS70031A-page 41 rfPIC12C509AG/509AF

7.8 Application Circuits

7.8.1 EXAMPLE rfPIC12C 509AG ASK CIRCUIT

DS70031A-page 42 Preliminary  2001 Microchip Technology Inc.

7.8.2 EXAMPLE rfPIC12C 509AF FSK CIRCUIT

 2001 Microchip Technology Inc. Preliminary DS70031A-page 43 rfPIC12C509AG/509AF

8.0 SPECIAL FEATURES OF THE

The rfPIC12C509AG/509AF microcontroller has a host of features intended to maximize system reliability, min- imize cost through elimination of external components, provide power saving operating modes and offer code protection. These features are:

• Oscillator selection
• RESET - Power-on Reset (POR) - Device Reset Timer (DRT) - Wake-up from SLEEP on pin change
• Watchdog Timer (WDT)
• SLEEP
• C o d e p r o t e c t i o n
• ID locations
• In-Circuit Serial Programming The above features are configured by the configuration bits during programming.

8.1 Configuration Bits

The rfPIC12C509AG/509AF configuration word con- sists of 12 bits. Configuration bits can be programmed to select various device configurations. Two bits are for the selection of the oscillator type, one bit is the Watch- dog Timer enable bit, one bit for code protection, and one bit is the MCLR enable bit. FIGURE 8-1: CONFIGURATION WORD FOR rfPIC12C509AG/509AF — — — — — — — MCLRE CP WDTE FOSC1 FOSC0 Register: CONFIG Address(1): FFFhb i t 1 1 1 0 987654321 b i t 0 bit 11-5:Unimplemented bit 4: MCLRE: MCLR enable bit. 1=M C L Rpin enabled 0=M C L Rtied to VDD , (Internally) bit 3: CP: Code protection bit. 1 = Code protection off 0 = Code protection on bit 2: WDTE: Watchdog timer enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSC0: Oscillator selection bits 11 = EXTRC - external RC oscillator 10 = INTRC - internal RC oscillator 01 = XT oscillator 00 = LP oscillator Note 1: Refer to the PIC12C5XX Programming Specifications to determine how to access the configuration word. This register is not user addressable during device operation.

DS70031A-page 44 Preliminary  2001 Microchip Technology Inc.

8.2 Oscillator Configurations

8.2.1 OSCILLATOR TYPES

The oscillator frequency is a primary factor in determin- ing PICmicro microcontroller unit (MCU) current draw. As a rough guideline, the rfPIC12C509AG/509AF draws approximately 250µA per MHz. The rfPIC12C509AG/509AF can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1:FOSC0) to select one of these four modes:

• LP: Low Power Crystal
• XT : Crystal/Resonator
• INTRC: Internal 4 MHz Oscillator
• EXTRC: External Resistor/Capacitor

8.2.2 CRYSTAL OSCILLATOR / CERAMIC

In XT or LP modes, a crystal or ceramic resonator is connected to the GP5/OSC1/CLKIN and GP4/OSC2 pins to establish oscillation (Figure 8-2). The rfPIC12C509AG/509AF oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT or LP modes, the device can have an external clock source drive the GP5/ OSC1/CLKIN pin (Figure 8-3). FIGURE 8-2: CRYSTAL OPERATION (OR CERAMIC RESONATOR) (XT OR LP OSC CONFIGURATION) FIGURE 8-3: EXTERNAL CLOCK INPUT OPERATION (XT OR LP OSC CONFIGURATION) TABLE 8-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS - rfPIC12C509AG/509AF TABLE 8-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR - rfPIC12C509AG/509AF Note 1: See Capacitor Selection tables for recommended values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF approximate value = 10 MΩ . C1 (1) C2 (1) XTAL OSC2 OSC1 RF (3) SLEEP To i nte rna l logic RS (2) rfPIC12C509AG/509AF Osc Type Resonator Freq Cap. Range Cap. Range XT 4.0 MHz 30 pF 30 pF These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components. Osc Type Resonator Freq Cap.Range Cap. Range LP 32 kHz (1) 15 pF 15 pF XT 200 kHz 1M H z 4M H z 47-68 pF 15 pF 15 pF 47-68 pF 15 pF 15 pF Note 1: For VDD >4 . 5 V ,C 1=C 2≈ 30 pF is recommended. These values are for design guidance only. Rs may be required to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crys- tal manufacturer for appropriate values of external components. Clock from ext. system OSC1 OSC2Open rfPIC12C509AG/509AF

 2001 Microchip Technology Inc. Preliminary DS70031A-page 45 rfPIC12C509AG/509AF

8.2.3 EXTERNAL RC OSCILLATOR

For timing insensitive applications, the RC device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resis- tor (R EXT ) and capacitor (CEXT ) values, and the operat- ing temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal pro- cess parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low C EXT values. The user also needs to take into account variation due to tolerance of external R and C compo- nents used. Figure 8-4 shows how the R/C combination is con- nected to the rfPIC12C509AG/509AF. For R EXT values below 2.2 kΩ , the oscillator operation may become unstable, or stop completely. For very high REXT values (e.g., 1 MΩ ) the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend keeping R EXT between 3 kΩ and 100 kΩ . Although the oscillator will operate with no external capacitor (CEXT = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or pack- age lead frame capacitance. The Electrical Specifications sections show RC fre- quency variation from part to part due to normal pro- cess variation. The variation is larger for larger R (since leakage current variation will affect RC frequency more for large R) and for smaller C (since variation of input capacitance will affect RC frequency more). Also, see the Electrical Specifications sections for vari- ation of oscillator frequency due to V DD for given REXT / C EXT values as well as frequency variation due to oper- ating temperature for given R, C, and VDD values. FIGURE 8-4: EXTERNAL RC OSCILLATOR MODE VDD R EXT C EXT VSS OSC1 Internal clock N rfPIC12C509AG/509AF

DS70031A-page 46 Preliminary  2001 Microchip Technology Inc.

8.2.4 INTERNAL 4 MHz RC OSCILLATOR

The internal RC oscillator provides a fixed 4 MHz (nom- inal) system clock at VDD = 5V and 25°C, see “Electri- cal Specifications” section for information on variation over voltage and temperature. In addition, a calibration instruction is programmed into the top of memory which contains the calibration value for the internal RC oscillator. This location is never code protected regardless of the code protect settings. This value is programmed as aMOVLW XXinstruction where XX is the calibration value, and is placed at the RESET vector. This will load the W register with the cal- ibration value upon RESET and the PC will then roll over to the users program at address 0x000. The user then has the option of writing the value to the OSCCAL Register (05h) or ignoring it. OSCCAL, when written to with the calibration value, will “trim” the internal oscillator to remove process variation from the oscillator frequency. For the rfPIC12C509AG/509AF bits <7:2>, CAL5- CAL0 are used for calibration. Adjusting CAL5-0 from 000000 to111111 yields a higher clock speed. Note that bits 1 and 0 of OSCCAL are unimplemented and should be written as 0 when modifying OSCCAL for compatibility with future devices.

8.3 RESET

The device differentiates between various kinds of RESET: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during SLEEP d) WDT Time-out Reset during normal operation e) WDT Time-out Reset during SLEEP f) Wake-up from SLEEP on pin change Some registers are not RESET in any way; they are unknown on POR and unchanged in any other RESET. Most other registers are RESET to “RESET state” on Power-on Reset (POR), MCLR , WDT or Wake-up-on- Pin Change Reset during normal operation. They are not affected by a WDT Reset during SLEEP or MCLR Reset during SLEEP , since these RESETS are viewed as resumption of normal operation. The exceptions to this are TO ,P D, and GPWUF bits. They are set or cleared differently in different RESET situations. These bits are used in software to determine the nature of reset. See T able 8-3 for a full description of RESET states of all registers. Note: Please note that erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part. so it can be repro- grammed correctly later.

 2001 Microchip Technology Inc. Preliminary DS70031A-page 47 rfPIC12C509AG/509AF TABLE 8-3: RESET CONDITIONS FOR REGISTERS TABLE 8-4: RESET CONDITION FOR SPECIAL REGISTERS Register Address Power-on Reset MCLR Reset WDT time-out Wake-up-on-Pin Change W— qqqq qqxx (1) qqqq qquu (1) INDF 00h xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu PC 02h 1111 1111 1111 1111 STATUS 03h 0001 1xxx q00q quuu (2,3) FSR 04h 110x xxxx 11uu uuuu OSCCAL 05h 1000 00-- uuuu uu-- GPIO 06h --xx xxxx --uu uuuu OPTION — 1111 1111 1111 1111 TRIS — --11 1111 --11 1111 Legend: u= unchanged,x= unknown,-= unimplemented bit, read as ‘0’,q= value depends on condition. Note 1: Bits <7:2> of W register contain oscillator calibration values due toMOVLW XXinstruction at top of memory. Note 2: See Table 8-7 for RESET value for specific conditions Note 3: If RESET was due to Wake-up-on-Pin Change, then bit 7 = 1. All other RESETS will cause bit 7 = 0. STATUS Addr: 03h PCL Addr: 02h Power-on Reset 0001 1xxx 1111 1111 MCLR Reset during normal operation 000u uuuu 1111 1111 MCLR Reset during SLEEP 0001 0uuu 1111 1111 WDT Reset during SLEEP 0000 0uuu 1111 1111 WDT Reset normal operation 0000 uuuu 1111 1111 Wake-up from SLEEP on pin change 1001 0uuu 1111 1111 Legend: u= unchanged,x= unknown,-= unimplemented bit, read as ‘0’.

DS70031A-page 48 Preliminary  2001 Microchip Technology Inc.

8.3.1 MCLR ENABLE

This configuration bit when unprogrammed (left in the ‘1’ state) enables the external MCLRfunction. When programmed, the MCLR function is tied to the internal VDD , and the pin is assigned to be a GPIO. See Figure 8-5. When pin GP3/MCLR/VPP is configured as MCLR , the internal pull-up is always on. FIGURE 8-5: MCLR SELECT

8.4 Power-On Reset (POR)

The rfPIC12C509AG/509AF incorporates on-chip Power-on Reset (POR) circuitry which provides an internal chip RESET for most power-up situations. The on-chip POR circuit holds the chip in RESET until V DD has reached a high enough level for proper oper- ation. T o take advantage of the internal POR, program the GP3/MCLR /VPP pin as MCLR and tie through a resistor to VDD or program the pin as GP3. An internal weak pull-up resistor is implemented using a transistor. Refer to T able 11-1 for the pull-up resistor ranges. This will eliminate external RC components usually needed to create a Power-on Reset. A maximum rise time for V DD is specified. See Electrical Specifications for details. When the device starts normal operation (exits the RESET condition), device operating parameters (volt- age, frequency, temperature,...) must be met to ensure operation. If these conditions are not met, the device must be held in RESET until the operating parameters are met. A simplified block diagram of the on-chip Power-on Reset circuit is shown in Figure 8-6. The Power-on Reset circuit and the Device Reset Timer (Section 8.5) circuit are closely related. On power-up, the RESET latch is set and the DRT is RESET. The DRT timer begins counting once it detects MCLR to be high. After the time-out period, which is typically 18 ms, it will RESET the RESET latch and thus end the on-chip RESET signal. A power-up example where MCLR is held low is shown in Figure 8-7. VDD is allowed to rise and stabilize before bringing MCLRhigh. The chip will actually come out of RESET T DRT msec after MCLRgoes high. In Figure 8-8, the on-chip Power-on Reset feature is being used (MCLRand VDD are tied together or the pin is programmed to be GP3.). The VDD is stable before the start-up timer times out and there is no problem in getting a proper RESET. However, Figure 8-9 depicts a problem situation where V DD rises too slowly. The time between when the DRT senses that MCLRis high and when MCLR (and VDD ) actually reach their full value, is too long. In this situation, when the start-up timer times out, V DD has not reached the VDD (min) value and the chip is, therefore, not guaranteed to function correctly. For such situations, we recommend that external RC circuits be used to achieve longer POR delay times (Figure 8-8). For additional information refer to Application Notes Power-Up Considerations”- AN522 and “Power-up Trouble Shooting” - AN607. GP3/MCLR /VPP MCLRE INTERNAL MCLR WEAK PULL-UP Note: When the device starts normal operation (exits the RESET condition), device oper- ating parameters (voltage, frequency, tem- perature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in RESET until the operating conditions are met.

DS70031A-page 50 Preliminary  2001 Microchip Technology Inc. FIGURE 8-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD ): SLOW VDD RISE TIME

8.5 Device Reset Timer (DRT)

In the rfPIC12C509AG/509AF, DRT runs from RESET and varies based on oscillator selection (see Table 8- 5). The DRT operates on an internal RC oscillator. The processor is kept in RESET as long as the DRT is active. The DRT delay allows V DD to rise above VDD min., and for the oscillator to stabilize. Oscillator circuits based on crystals or ceramic resona- tors require a certain time after power-up to establish a stable oscillation. The on-chip DRT keeps the device in a RESET condition for approximately 18 ms after MCLR has reached a logic high (VIHMCLR ) level. Thus, programming GP3/MCLR /VPP as MCLR and using an external RC network connected to the MCLRinput is not required in most cases, allowing for savings in cost- sensitive and/or space restricted applications, as well as allowing the use of the GP3/MCLR /VPP pin as a general purpose input. The Device Reset time delay will vary from chip to chip due to VDD , temperature, and process variation. See AC parameters for details. The DRT will also be triggered upon a Watchdog Timer time-out. This is particularly important for applications using the WDT to wake from SLEEP mode automati- cally.

8.6 Watchdog Timer (WDT)

The rfPIC12C509AG/509AF has a Watchdog Timer which can be shut off only through configuration bit WDTE. It runs off of its own RC oscillator foradded reli- ability. If using XT or LP selectable oscillator options, there is always an 18 ms (nominal) delay provided by the Device Reset Timer (DRT), intended to keep the chip in RESET until the crystal oscillator is stable. If using INTRC or EXTRC there is an 18 ms delay only on V DD power-up. With this timer on-chip, most applica- tions need no external RESET circuitry. The Watchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external com- ponents. This RC oscillator is separate from the exter- nal RC oscillator of the GP5/OSC1/CLKIN pin and the internal 4 MHz oscillator. That means that the WDT will run even if the main processor clock has been stopped, for example, by execution of aSLEEPinstruction. Dur- ing normal operation or SLEEP , a WDT Reset or wake- up Reset generates a device RESET. The TO bit (STATUS<4>) will be cleared upon a Watch- dog Timer Reset. The WDT can be permanently disabled by program- ming the configuration bit WDTE as a '0' (Section 8.1). Refer to the PIC12C5XX Programming Specifications to determine how to access the configuration word. TABLE 8-5: DRT (DEVICE RESET TIMER PERIOD) VDD MCLR INTERNAL POR DRT TIME-OUT INTERNAL RESET TDRT When V DD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will RESET properly if, and only if, V1≥ VDD min. Oscillator Configuration POR Reset Subsequent RESETS IntRC & ExtRC 18 ms (typical) 300 µs (typical) XT & LP 18 ms (typical) 18 ms (typical)

 2001 Microchip Technology Inc. Preliminary DS70031A-page 51 rfPIC12C509AG/509AF

8.6.1 WDT PERIOD

The WDT has a nominal time-out period of 18 ms, (with no prescaler). If a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT (under software control) by writ- ing to the OPTION register. Thus, a time-out period of a nominal 2.3 seconds can be realized. These periods vary with temperature, V DD and part-to-part process variations (see DC specs). Under worst case conditions (VDD = Min., Temperature = Max., max. WDT prescaler), it may take several sec- onds before a WDT time-out occurs.

8.6.2 WDT PROGRAMMING

The CLRWDTinstruction clears the WDT and the postscaler, if assigned to the WDT, and prevents it from timing out and generating a device RESET. The SLEEPinstruction RESETS the WDT and the postscaler, if assigned to the WDT. This gives the max- imum SLEEP time before a WDT wake-up Reset. FIGURE 8-10: WATCHDOG TIMER BLOCK DIAGRAM TABLE 8-6: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on All Other RESETS N/A OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: Shaded boxes = Not used by Watchdog Timer,—= unimplemented, read as '0',u= unchanged From Timer0 Clock Source (Figure 8-5) To Timer0 (Figure 8-4) Postscaler WDT Enable Configuration PSA WDT Time-out PS2:PS0 PSAMUX 8-t o-1M U X PostscalerM U X Watchdog Timer Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register.

DS70031A-page 52 Preliminary  2001 Microchip Technology Inc.

8.7 Time-Out Sequence, Power Down,

and Wake-up from SLEEP Status Bits (TO /PD/GPWUF) The TO,P D, and GPWUF bits in the STATUS register can be tested to determine if a RESET condition has been caused by a power-up condition, a MCLR or Watchdog Timer (WDT) Reset.

8.7.1 RESET ON BROWN-OUT

A Brown-out is a condition where device power (VDD ) dips below its minimum value, but not to zero, and then recovers. The device should be RESET in the event of a Brown-out. To RESET the rfPIC12C509AG/509AF when a Brown-out occurs, external Brown-out protection circuits may be built, as shown in Figure 8-11, Figure 8-12 and Figure 8-13. FIGURE 8-11: BROWN-OUT PROTECTION CIRCUIT 1 FIGURE 8-12: BROWN-OUT PROTECTION CIRCUIT 2 FIGURE 8-13: BROWN-OUT PROTECTION CIRCUIT 3 TABLE 8-7: TO /PD/GPWUF STATUS AFTER RESET GPWUF TO PD RESET caused by 0 0 0 WDT wake-up from SLEEP 0 0 u WDT time-out (not from SLEEP) 01 0 M C L R wake-up from SLEEP 01 1 P o w e r - u p 0u u M C L R not during SLEEP 1 1 0 Wake-up from SLEEP on pin change Legend: u = unchanged Note 1: The TO,P D, and GPWUF bits maintain their status (u) until a RESET occurs. A low-pulse on the MCLR input does not change the TO,P D, and GPWUF status bits. This circuit will activate RESET when VDD goes below Vz + 0.7V (where Vz = Zener voltage). *Refer to Figure 8-5 and Table 11-1 for internal weak pull-up on MCLR. 33k 10k 40k* MCLR rfPIC12C509AG/ VDD VDD VDD 509AF This Brown-out circuit is less expensive, although less accurate. Transistor Q1 turns off when VDD is below a certain level such that: *Refer to Figure 8-5 and Table 11-1 for internal weak pull-up on MCLR. VDD • R1 + R2 =0 . 7 V R2 40k* MCLR rfPIC12C509AG/ VDD VDD VDD 509AF This Brown-out protection circuit employs Microchip Technology’s MCP809 microcontroller supervisor. The MCP8XX and MCP1XX family of supervisors provide push-pull and open collector outputs with both high and low active RESET pins. There are 7 different trip point selections to accommodate 5V and 3V systems. MCLR rfPIC12C509AG/ VDD VDD Vss RST MCP809 VDD bypasscapacitor 509AF

 2001 Microchip Technology Inc. Preliminary DS70031A-page 53 rfPIC12C509AG/509AF

8.8 Power-Down Mode (SLEEP)

The SLEEP mode is designed to offer a very low cur- rent power-down mode. The user can wake-up from SLEEP through a change on input pins or through a Watchdog Timer time-out. Several oscillator options are also made available to allow the part to fit the appli- cation, including an internal 4 MHz oscillator. The EXTRC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options. A device may be powered down (SLEEP) and later powered up (Wake-up from SLEEP).

8.8.1 SLEEP

The Power-down mode is entered by executing a SLEEPinstruction. If enabled, the Watchdog Timer will be cleared but keeps running, the TO bit (STATUS<4>) is set, the PD bit (STATUS<3>) is cleared and the oscillator driver is turned off. The I/O ports maintain the status they had before theSLEEPinstruction was executed (driving high, driving low, or hi-impedance). It should be noted that a RESET generated by a WDT time-out does not drive the MCLR pin low. For lowest current consumption while powered down, the T0CKI input should be at VDD or VSS and the GP3/ MCLR /VPP pin must be at a logic high level (VIHMC )i f MCLR is enabled.

8.8.2 WAKE-UP FROM SLEEP

The device can wake-up from SLEEP through one of the following events: 1. An external RESET input on GP3/MCLR /VPP pin, when configured as MCLR. 2. A Watchdog Timer time-out Reset (if WDT was enabled). 3. A change on input pin GP0, GP1, or GP3/ MCLR /VPP when wake-up on change is enabled. These events cause a device RESET . The TO,P D,a n d GPWUF bits can be used to determine the cause of device RESET. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). The PDbit, which is set on power-up, is cleared whenSLEEPis invoked. The GPWUF bit indicates a change in state while in SLEEP at pins GP0, GP1, or GP3 (since the last time there was a file or bit operation on GP port). The WDT is cleared when the device wakes from sleep, regardless of the wake-up source. Caution: Right before entering SLEEP , read the input pins. When in SLEEP , wake up occurs when the values at the pins change from the state they were in at the last read- ing. If a wake-up on change occurs and the pins are not read before reentering SLEEP , a wake up will occur immediately even if no pins change while in SLEEP mode.

DS70031A-page 54 Preliminary  2001 Microchip Technology Inc.

8.9 Program Verification/Code

If the code protection bit has not been programmed, the on-chip program memory can be read out for verifica- tion purposes. The first 64 locations can be read by the rfPIC12C509AG/509AF regardless of the code protec- tion bit setting. The last memory location can be read regardless of the code protection bit setting on the rfPIC12C509AG/ 509AF .

8.10 ID Locations

Four memory locations are designated as ID locations where the user can store checksum or other code-iden- tification numbers. These locations are not accessible during normal execution but are readable and writable during program/verify. Use only the lower 4 bits of the ID locations and always program the upper 8 bits as '0's.

 2001 Microchip Technology Inc. Preliminary DS70031A-page 55 rfPIC12C509AG/509AF

8.11 In-Circuit Serial Programming

The rfPIC12C509AG/509AF microcontroller with EPROM program memory can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unpro- grammed devices, and then program the microcontrol- ler just before shipping the product. This also allows the most recent firmware or a custom firmware to be pro- grammed. The device is placed into a program/verify mode by holding the GP1 and GP0 pins low while raising the MCLR (VPP )p i nf r o mVIL to VIHH (see programming specification). GP1 becomes the programming clock and GP0 becomes the programming data. Both GP1 and GP0 are Schmitt Trigger inputs in this mode. After RESET, a 6-bit command is then supplied to the device. Depending on the command, 14-bits of pro- gram data are then supplied to or from the device, depending if the command was a load or a read. For complete details of serial programming, please refer to the PIC12C5XX Programming Specifications. A typical in-circuit serial programming connection is shown in Figure 8-14. FIGURE 8-14: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION External Connector Signals To Normal Connections To Normal Connections rfPIC12C509AG/ VDD VSS MCLR /VPP GP1 GP0 +5V VPP CLK Data I/O VDD 509AF

DS70031A-page 56 Preliminary  2001 Microchip Technology Inc. NOTES:

 2001 Microchip Technology Inc. Preliminary DS70031A-page 57 rfPIC12C509AG/509AF

9.0 INSTRUCTION SET SUMMARY

Each rfPIC12C509AG/509AF instruction is a 12-bit word divided into an OPCODE, which specifies the instruction type, and one or more operands which fur- ther specify the operation of the instruction. The rfPIC12C509AG/509AF instruction set summary in Table 9-2 groups the instructions into byte-oriented, bit- oriented, and literal and control operations. Table 9-1 shows the opcode field descriptions. For byte-orientedinstructions, 'f' represents a file reg- ister designator and 'd' represents a destination desig- nator. The file register designator is used to specify w h i c ho n eo ft h e3 2f i l er e g i s t e r si st ob eu s e db yt h e instruction. The destination designator specifies where the result of the operation is to be placed. If 'd' is '0', the result is placed in the W register. If 'd' is '1', the result is placed in the file register specified in the instruction. For bit-orientedinstructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. For literal and controloperations, 'k' represents an 8 or 9-bit constant or literal value. TABLE 9-1: OPCODE FIELD DESCRIPTIONS All instructions are executed within a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1µs. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2µs. Figure 9-1 shows the three general formats that the instructions can have. All examples in the figure use the following format to represent a hexadecimal num- ber: 0xhhh where 'h' signifies a hexadecimal digit. FIGURE 9-1: GENERAL FORMAT FOR INSTRUCTIONS Field Description f Register file address (0x00 to 0x7F) W Working register (accumulator) b Bit address within an 8-bit file register k Literal field, constant data or label x Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d=0( s t o r er e s u l ti nW ) d=1( s t o r er e s u l ti nf i l er e g i s t e r' f ' ) Default is d = 1 labelLabel name TOSTop of Stack PC Program Counter WDTWatchdog Timer Counter TO Time-Out bit PD Power-Down bit destDestination, either the W register or the specified register file location [] Options () Contents → Assigned to <> Register bit field ∈ In the set of italics User defined term (font is courier) Byte-orientedfile register operations 11 6 5 4 0 d = 0 for destination W OPCODE d f (FILE #) d = 1 for destination f f = 5-bit file register address Bit-orientedfile register operations 11 8 7 5 4 0 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 5-bit file register address Literal and controloperations (exceptGOTO) 11 8 7 0 OPCODE k (literal) k = 8-bit immediate value Literal and controloperations -GOTOinstruction 11 9 8 0 OPCODE k (literal) k = 9-bit immediate value

DS70031A-page 58 Preliminary  2001 Microchip Technology Inc. TABLE 9-2: INSTRUCTION SET SUMMARY Mnemonic, Operands Description Cycles 12-Bit Opcode Status Affected NotesMSb LSb ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f,d f,d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate left f through Carry Rotate right f through Carry Subtract W from f Swap f Exclusive OR W with f 1(2) 1(2) 0001 0001 0000 0000 0010 0000 0010 0010 0011 0001 0010 0000 0000 0011 0011 0000 0011 0001 11df 01df 011f 0100 01df 11df 11df 10df 11df 00df 00df 001f 0000 01df 00df 10df 10df 10df ffff ffff ffff 0000 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff C,DC,Z Z Z Z Z Z None Z None Z Z None None C C C,DC,Z None Z 1,2,4 2,4 2,4 2,4 2,4 2,4 2,4 2,4 1,4 2,4 2,4 1,2,4 2,4 2,4 BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f B i tT e s tf ,S k i pi fC l e a r B i tT e s tf ,S k i pi fS e t 1( 2 ) 1( 2 ) 0100 0101 0110 0111 bbbf bbbf bbbf bbbf ffff ffff ffff ffff None None None None 2,4 2,4 LITERAL AND CONTROL OPERATIONS ANDLW CALL CLRWDT GOTO IORLW MOVLW OPTION RETLW SLEEP TRIS XORLW k k k k k k k f k AND literal with W Call subroutine Clear Watchdog Timer Unconditional branch Inclusive OR Literal with W Move Literal to W Load OPTION register Return, place Literal in W Go into standby mode Load TRIS register Exclusive OR Literal to W 1110 1001 0000 101k 1101 1100 0000 1000 0000 0000 1111 kkkk kkkk 0000 kkkk kkkk kkkk 0000 kkkk 0000 0000 kkkk kkkk kkkk 0100 kkkk kkkk kkkk 0010 kkkk 0011 0fff kkkk Z None TO ,PD None Z None None None TO ,PD None Z Note 1: The 9th bit of the program counter will be forced to a '0' by any instruction that writes to the PC except for GOTO.( S e c t i o n4 . 6 ) 2: When an I/O register is modified as a function of itself (e.g.MOVF GPIO, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 3: The instructionTRIS f, where f = 6 causes the contents of the W register to be written to the tristate latches of GPIO. A '1' forces the pin to a hi-impedance state and disables the output buffers. 4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared (if assigned to TMR0).

 2001 Microchip Technology Inc. Preliminary DS70031A-page 59 rfPIC12C509AG/509AF ADDWF Add W and f Syntax: [ label] ADDWF f,d Operands: 0 ≤ f≤ 31 d ∈ [0,1] Operation: (W) + (f) → (dest) Status Affected: C, DC, Z Encoding: 0001 11df ffff Description: Add the contents of the W register and register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is '1' the result is stored back in register 'f'. Words: 1 Cycles: 1 Example: ADDWF FSR, 0 Before Instruction W = 0x17 FSR = 0xC2 After Instruction W= 0 x D 9 FSR = 0xC2 ANDLW And literal with W Syntax: [ label] ANDLW k Operands: 0 ≤ k ≤ 255 Operation: (W).AND. (k) → (W) Status Affected: Z Encoding: 1110 kkkk kkkk Description: The contents of the W register are AND’ed with the eight-bit literal 'k'. The result is placed in the W register. Words: 1 Cycles: 1 Example: ANDLW 0x5F Before Instruction W= 0 x A 3 After Instruction W = 0x03 ANDWF AND W with f Syntax: [ label] ANDWF f,d Operands: 0 ≤ f≤ 31 d ∈ [0,1] Operation: (W) .AND. (f) → (dest) Status Affected: Z Encoding: 0001 01df ffff Description: The contents of the W register are AND’ed with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is '1' the result is stored back in register 'f'. Words: 1 Cycles: 1 Example: ANDWF FSR, 1 Before Instruction W=0 x 1 7 FSR = 0xC2 After Instruction W= 0 x 1 7 FSR = 0x02 BCF Bit Clear f Syntax: [ label]B C F f , b Operands: 0 ≤ f≤ 31 0 ≤ b ≤ 7 Operation: 0 → (f<b>) Status Affected: None Encoding: 0100 bbbf ffff Description: Bit 'b' in register 'f' is cleared. Words: 1 Cycles: 1 Example: BCF FLAG_REG, 7 Before Instruction FLAG_REG = 0xC7 After Instruction FLAG_REG = 0x47

DS70031A-page 60 Preliminary  2001 Microchip Technology Inc. BSF Bit Set f Syntax: [ label] BSF f,b Operands: 0 ≤ f≤ 31 0 ≤ b ≤ 7 Operation: 1 → (f<b>) Status Affected: None Encoding: 0101 bbbf ffff Description: Bit 'b' in register 'f' is set. Words: 1 Cycles: 1 Example: BSF FLAG_REG, 7 Before Instruction FLAG_REG = 0x0A After Instruction FLAG_REG = 0x8A BTFSC Bit Test f, Skip if Clear Syntax: [ label] BTFSC f,b Operands: 0 ≤ f≤ 31 0 ≤ b ≤ 7 Operation: skip if (f<b>) = 0 Status Affected: None Encoding: 0110bbbf ffff Description: If bit 'b' in register 'f' is 0 then the next instruction is skipped. If bit 'b' is 0 then the next instruction fetched during the current instruction execution is discarded, and anNOPis executed instead, making this a 2 cycle instruction. Words: 1 Cycles: 1(2) Example: HERE FALSE TRUE BTFSC GOTO FLAG,1 PROCESS_CODE Before Instruction PC = address (HERE) After Instruction if FLAG<1> = 0, PC = address (TRUE); if FLAG<1> = 1, PC = address (FALSE) BTFSS Bit Test f, Skip if Set Syntax: [ label] BTFSS f,b Operands: 0 ≤ f≤ 31 0 ≤ b<7 Operation: skip if (f<b>) = 1 Status Affected: None Encoding: 0111 bbbf ffff Description: If bit 'b' in register 'f' is '1' then the next instruction is skipped. If bit 'b' is '1', then the next instruction fetched during the current instruction execution, is discarded and anNOPis executed instead, making this a 2 cycle instruction. Words: 1 Cycles: 1(2) Example: HERE BTFSS FLAG,1 FALSE GOTO PROCESS_CODE TRUE • Before Instruction PC = address (HERE) After Instruction If FLAG<1> = 0, PC = address (FALSE); if FLAG<1> = 1, PC = address (TRUE)

 2001 Microchip Technology Inc. Preliminary DS70031A-page 61 rfPIC12C509AG/509AF CALL Subroutine Call Syntax: [ label]C A L Lk Operands: 0 ≤ k ≤ 255 Operation: (PC) + 1 → Top of Stack; k → PC<7:0>; (STATUS<6:5>) → PC<10:9>; 0 → PC<8> Status Affected: None Encoding: 1001 kkkk kkkk Description: Subroutine call. First, return address (PC+1) is pushed onto the stack. The eight bit immediate address is loaded into PC bits <7:0>. The upper bits PC<10:9> are loaded from STA- TUS<6:5>, PC<8> is cleared. CALLis a two cycle instruction. Words: 1 Cycles: 2 Example: HERE CALL THERE Before Instruction PC = address (HERE) After Instruction PC = address (THERE) TOS = address (HERE + 1) CLRF Clear f Syntax: [ label]C L R F f Operands: 0 ≤ f≤ 31 Operation: 00h → (f); 1 → Z Status Affected: Z Encoding: 0000 011f ffff Description: The contents of register 'f' are cleared and the Z bit is set. Words: 1 Cycles: 1 Example: CLRF FLAG_REG Before Instruction FLAG_REG = 0x5A After Instruction FLAG_REG = 0x00 Z= 1 CLRW Clear W Syntax: [ label]C L R W Operands: None Operation: 00h → (W); 1 → Z Status Affected: Z Encoding: 0000 0100 0000 Description: The W register is cleared. Zero bit (Z) is set. Words: 1 Cycles: 1 Example: CLRW Before Instruction W= 0 x 5 A After Instruction W= 0 x 0 0 Z=1 CLRWDT Clear Watchdog Timer Syntax: [ label]C L R W D T Operands: None Operation: 00h → WDT; 0 → WDT prescaler (if assigned); 1 → TO; 1 → PD Status Affected: TO,P D Encoding: 0000 0000 0100 Description: The CLRWDTinstruction RESETS the WDT. It also RESETS the prescaler, if the prescaler is assigned to the WDT and not Timer0. Status bits TO and PD are set. Words: 1 Cycles: 1 Example: CLRWDT Before Instruction WDT counter = ? After Instruction WDT counter = 0x00 WDT prescale = 0 TO =1 PD =1

DS70031A-page 62 Preliminary  2001 Microchip Technology Inc. COMF Complement f Syntax: [ label]C O M F f , d Operands: 0 ≤ f≤ 31 d ∈ [0,1] Operation: (f )→ (dest) Status Affected: Z Encoding: 0010 01df ffff Description: The contents of register 'f' are comple- mented. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. Words: 1 Cycles: 1 Example: COMF REG1,0 Before Instruction REG1 = 0x13 After Instruction REG1 = 0x13 W= 0 x E C DECF Decrement f Syntax: [ label]D E C F f , d Operands: 0 ≤ f≤ 31 d ∈ [0,1] Operation: (f) – 1 → (dest) Status Affected: Z Encoding: 0000 11df ffff Description: Decrement register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. Words: 1 Cycles: 1 Example: DECF CNT,1 Before Instruction CNT = 0x01 Z= 0 After Instruction CNT = 0x00 Z= 1 DECFSZ Decrement f, Skip if 0 Syntax: [ label]D E C F S Zf , d Operands: 0 ≤ f≤ 31 d ∈ [0,1] Operation: (f) – 1 → d; skip if result = 0 Status Affected: None Encoding: 0010 11df ffff Description: The contents of register 'f' are decre- mented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 0, the next instruction, which is already fetched, is discarded and anNOPis executed instead mak- i n gi tat w oc y c l ei n s t r u c t i o n . Words: 1 Cycles: 1(2) Example: HERE DECFSZ CNT, 1 GOTO LOOP CONTINUE • Before Instruction PC = address (HERE) After Instruction CNT = CNT - 1; if CNT = 0, PC = address (CONTINUE); if CNT ≠ 0, PC = address (HERE+1) GOTO Unconditional Branch Syntax: [ label] GOTO k Operands: 0 ≤ k ≤ 511 Operation: k → PC<8:0>; Status Affected: None Encoding: 101k kkkk kkkk Description: GOTOis an unconditional branch. The 9-bit immediate value is loaded into PC bits <8:0>. The upper bits of PC are loaded from STATUS<6:5>. GOTOis a two cycle instruction. Words: 1 Cycles: 2 Example: GOTO THERE After Instruction PC = address (THERE)

 2001 Microchip Technology Inc. Preliminary DS70031A-page 63 rfPIC12C509AG/509AF INCF Increment f Syntax: [ label] INCF f,d Operands: 0 ≤ f≤ 31 d ∈ [0,1] Operation: (f) + 1 → (dest) Status Affected: Z Encoding: 0010 10df ffff Description: The contents of register 'f' are incre- mented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. Words: 1 Cycles: 1 Example: INCF CNT,1 Before Instruction CNT = 0xFF Z= 0 After Instruction CNT = 0x00 Z= 1 INCFSZ Increment f, Skip if 0 Syntax: [ label] INCFSZ f,d Operands: 0 ≤ f≤ 31 d ∈ [0,1] Operation: (f) + 1 → (dest), skip if result = 0 Status Affected: None Encoding: 0011 11df ffff Description: The contents of register 'f' are incre- mented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 0, then the next instruc- tion, which is already fetched, is dis- carded and anNOPis executed instead making it a two cycle instruction. Words: 1 Cycles: 1(2) Example: HERE INCFSZ CNT, 1 GOTO LOOP CONTINUE • Before Instruction PC = address (HERE) After Instruction CNT = CNT + 1; if CNT = 0, PC = address (CONTINUE); if CNT ≠ 0, PC = address (HERE +1) IORLW Inclusive OR literal with W Syntax: [ label]I O R L W k Operands: 0 ≤ k ≤ 255 Operation: (W) .OR. (k) → (W) Status Affected: Z Encoding: 1101 kkkk kkkk Description: The contents of the W register are OR’ed with the eight bit literal 'k'. The result is placed in the W register. Words: 1 Cycles: 1 Example: IORLW 0x35 Before Instruction W= 0 x 9 A After Instruction W= 0 x B F Z=0 IORWF Inclusive OR W with f Syntax: [ label]I O R W Ff , d Operands: 0 ≤ f≤ 31 d ∈ [0,1] Operation: (W).OR. (f) → (dest) Status Affected: Z Encoding: 0001 00df ffff Description: Inclusive OR the W register with regis- ter 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. Words: 1 Cycles: 1 Example: IORWF RESULT, 0 Before Instruction RESULT = 0x13 W= 0 x 9 1 After Instruction RESULT = 0x13 W= 0 x 9 3 Z= 0

DS70031A-page 64 Preliminary  2001 Microchip Technology Inc. MOVF Move f Syntax: [ label]M O V F f , d Operands: 0 ≤ f≤ 31 d ∈ [0,1] Operation: (f) → (dest) Status Affected: Z Encoding: 0010 00df ffff Description: The contents of register 'f' is moved to destination 'd'. If 'd' is 0, destination is the W register. If 'd' is 1, the destination is file register 'f'. 'd' is 1 is useful to test af i l er e g i s t e rs i n c es t a t u sf l a gZi s affected. Words: 1 Cycles: 1 Example: MOVF FSR, 0 After Instruction W = value in FSR register MOVLW Move Literal to W Syntax: [ label]M O V L W k Operands: 0 ≤ k ≤ 255 Operation: k → (W) Status Affected: None Encoding: 1100 kkkk kkkk Description: The eight bit literal 'k' is loaded into the W register. The don’t cares will assem- ble as 0s. Words: 1 Cycles: 1 Example: MOVLW 0x5A After Instruction W = 0x5A MOVWF Move W to f Syntax: [ label]M O V W F f Operands: 0 ≤ f≤ 31 Operation: (W) → (f) Status Affected: None Encoding: 0000 001f ffff Description: Move data from the W register to regis- ter 'f'. Words: 1 Cycles: 1 Example: MOVWF TEMP_REG Before Instruction TEMP_REG = 0xFF W= 0 x 4 F After Instruction TEMP_REG = 0x4F W= 0 x 4 F NOP No Operation Syntax: [ label]N O P Operands: None Operation: No operation Status Affected: None Encoding: 0000 0000 0000 Description: No operation. Words: 1 Cycles: 1 Example: NOP

 2001 Microchip Technology Inc. Preliminary DS70031A-page 65 rfPIC12C509AG/509AF OPTION Load OPTION Register Syntax: [ label]O P T I O N Operands: None Operation: (W) → OPTION Status Affected: None Encoding: 0000 0000 0010 Description: The content of the W register is loaded into the OPTION register. Words: 1 Cycles: 1 Example OPTION Before Instruction W = 0x07 After Instruction OPTION = 0x07 RETLW Return with Literal in W Syntax: [ label]R E T L W k Operands: 0 ≤ k ≤ 255 Operation: k → (W); TOS → PC Status Affected: None Encoding: 1000 kkkk kkkk Description: The W register is loaded with the eight bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two cycle instruction. Words: 1 Cycles: 2 Example: TABLE CALL TABLE ;W contains ;table offset ;value.

• ;W now has table
• ;value. ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W= v a l u e o f k 8 RLF Rotate Left f through Carry Syntax: [ label]R L F f , d Operands: 0 ≤ f≤ 31 d ∈ [0,1] Operation: See description below Status Affected: C Encoding: 0011 01df ffff Description: The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is stored back in register 'f'. Words: 1 Cycles: 1 Example: RLF REG1,0 Before Instruction REG1 = 1110 0110 C= 0 After Instruction REG1 = 1110 0110 W= 1100 1100 C= 1 RRF Rotate Right f through Carry Syntax: [ label] RRF f,d Operands: 0 ≤ f≤ 31 d ∈ [0,1] Operation: See description below Status Affected: C Encoding: 0011 00df ffff Description: The contents of register 'f' are rotated o n eb i tt ot h er i g h tt h r o u g ht h eC a r r y Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. Words: 1 Cycles: 1 Example: RRF REG1,0 Before Instruction REG1 = 1110 0110 C= 0 After Instruction REG1 = 1110 0110 W= 0111 0011 C= 0 C register 'f' C register 'f'

DS70031A-page 66 Preliminary  2001 Microchip Technology Inc. SLEEP Enter SLEEP Mode Syntax: [label] SLEEP Operands: None Operation: 00h → WDT; 0 → WDT prescaler; 1 → TO ; 0 → PD Status Affected: TO,P D ,GPWUF Encoding: 0000 0000 0011 Description: Time-out status bit (TO) is set. The power down status bit (PD) is cleared. GPWUF is unaffected. T h eW D Ta n di t sp r e s c a l e ra r e cleared. The processor is put into SLEEP mode with the oscillator stopped. See sec- tion on SLEEP for more details. Words: 1 Cycles: 1 Example: SLEEP SUBWF Subtract W from f Syntax: [label]S U B W F f , d Operands: 0 ≤ f≤ 31 d ∈ [0,1] Operation: (f) – (W) → (dest) Status Affected: C, DC, Z Encoding: 0000 10df ffff Description: Subtract (2’s complement method) the W register from register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. Words: 1 Cycles: 1 Example 1: SUBWF REG1, 1 Before Instruction REG1 = 3 W= 2 C= ? After Instruction REG1 = 1 W= 2 C = 1 ; result is positive Example 2: Before Instruction REG1 = 2 W= 2 C= ? After Instruction REG1 = 0 W= 2 C = 1 ; result is zero Example 3: Before Instruction REG1 = 1 W= 2 C= ? After Instruction REG1 = FF W= 2 C = 0 ; result is negative

 2001 Microchip Technology Inc. Preliminary DS70031A-page 67 rfPIC12C509AG/509AF SWAPF Swap Nibbles in f Syntax: [ label] SWAPF f,d Operands: 0 ≤ f≤ 31 d ∈ [0,1] Operation: (f<3:0>) → (dest<7:4>); Status Affected: None Encoding: 0011 10df ffff Description: The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0 the result is placed in W register. If 'd' is 1 the result is placed in register 'f'. Words: 1 Cycles: 1 Example SWAPFREG1, 0 Before Instruction REG1 = 0xA5 After Instruction REG1 = 0xA5 W = 0X5A TRIS Load TRIS Register Syntax: [ label]T R I S f Operands: f = 6 Operation: (W) → TRIS register f Status Affected: None Encoding: 0000 0000 0fff Description: TRIS register 'f' (f = 6) is loaded with the contents of the W register Words: 1 Cycles: 1 Example TRIS GPIO Before Instruction W = 0XA5 After Instruction TRIS = 0XA5 Note: f = 6 for PIC12C5XX only. XORLW Exclusive OR literal with W Syntax: [label]X O R L W k Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → (W) Status Affected: Z Encoding: 1111 kkkk kkkk Description: The contents of the W register are XOR’ed with the eight bit literal 'k'. The result is placed in the W register. Words: 1 Cycles: 1 Example: XORLW 0xAF Before Instruction W= 0 x B 5 After Instruction W= 0 x 1 A XORWF Exclusive OR W with f Syntax: [ label]X O R W F f , d Operands: 0 ≤ f≤ 31 d ∈ [0,1] Operation: (W) .XOR. (f) → (dest) Status Affected: Z Encoding: 0001 10df ffff Description: Exclusive OR the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. Words: 1 Cycles: 1 Example XORWFREG,1 Before Instruction REG = 0xAF W= 0 x B 5 After Instruction REG = 0x1A W= 0 x B 5

DS70031A-page 68 Preliminary  2001 Microchip Technology Inc. NOTES:

 2001 Microchip Technology Inc. Preliminary DS70031A-page 69 rfPIC12C509AG/509AF

10.0 DEVELOPMENT SUPPORT

The PICmicro® microcontrollers are supported with a full range of hardware and software development tools:

• Integrated Development Environment - MPLAB ® IDE Software
• Assemblers/Compilers/Linkers - MPASM TM Assembler - MPLAB C17 and MPLAB C18 C Compilers -M P L I N K TM Object Linker/ MPLIB TM Object Librarian
• Simulators - MPLAB SIM Software Simulator
• E m u l a t o r s - MPLAB ICE 2000 In-Circuit Emulator - ICEPIC™ In-Circuit Emulator
• In-Circuit Debugger - MPLAB ICD
• Device Programmers -P R O M A T E ® II Universal Device Programmer - PICSTART ® Plus Entry-Level Development Programmer
• Low Cost Demonstration Boards - PICDEM TM 1 Demonstration Board - PICDEM 2 Demonstration Board - PICDEM 3 Demonstration Board - PICDEM 17 Demonstration Board EE LOQ ® Demonstration Board

10.1 MPLAB Integrated Development

The MPLAB IDE software brings an ease of software development previously unseen in the 8-bit microcon- troller market. The MPLAB IDE is a Windows® -based application that contains:

• An interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately)
• A full-featured editor
• A project manager
• Customizable toolbar and key mapping
• A status bar
• On-line help The MPLAB IDE allows you to:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download to PICmicro emulator and simulator tools (auto- matically updates all project information)
• Debug using: - source files - absolute listing file - machine code The ability to use MPLAB IDE with multipledebugging tools allows users to easily switch from the cost- effective simulator to a full-featured emulator with minimal retraining.

10.2 MPASM Assembler

The MPASM assembler is a full-featured universal macro assembler for all PICmicro MCU’s. The MPASM assembler has a command line interface and a Windows shell. It can be used as a stand-alone application on a Windows 3.x or greater system, or it can be used through MPLAB IDE. The MPASM assem- bler generates relocatable object files for the MPLINK object linker, Intel ® standard HEX files, MAP files to detail memory usage and symbol reference, an abso- lute LST file that contains source lines and generated machine code, and a COD file for debugging. The MPASM assembler features include:

• Integration into MPLAB IDE projects.
• User-defined macros to streamline assembly code.
• Conditional assembly for multi-purpose source files.
• Directives that allow complete control over the assembly process.

10.3 MPLAB C17 and MPLAB C18

The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI ‘C’ compilers for Microchip’s PIC17CXXX and PIC18CXXX family of microcontrollers, respectively. These compilers provide powerful integration capabilities and ease of use not f o u n dw i t ho t h e rc o m p i l e r s . For easier source level debugging, the compilers pro- vide symbol information that is compatible with the MPLAB IDE memory display.

DS70031A-page 70 Preliminary  2001 Microchip Technology Inc.

10.4 MPLINK Object Linker/

The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can also link relocatable objects from pre-compiled libraries, using directives from a linker script. The MPLIB object librarian is a librarian for pre- compiled code to be used with the MPLINK object linker. When a routine from a library is called from another source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The MPLIB object librarian manages the creation and modification of library files. The MPLINK object linker features include:

• Integration with MPASM assembler and MPLAB C17 and MPLAB C18 C compilers.
• Allows all memory areas to be defined as sections to provide link-time flexibility. The MPLIB object librarian features include:
• Easier linking because single libraries can be included instead of many smaller files.
• Helps keep code maintainable by grouping related modules together.
• Allows libraries to be created and modules to be added, listed, replaced, deleted or extracted.

10.5 MPLAB SIM Software Simulator

The MPLAB SIM software simulator allows code devel- opment in a PC-hosted environment by simulating the PICmicro series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user-defined key press, to any of the pins. The execution can be performed in single step, execute until break, or trace mode. The MPLAB SIM simulator fully supports symbolic debugging using the MPLAB C17 and the MPLAB C18 C compilers and the MPASM assembler. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent multi-project software development tool.

10.6 MPLAB ICE High Performance

Universal In-Circuit Emulator with MPLAB IDE The MPLAB ICE universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers (MCUs). Software control of the MPLAB ICE in-circuit emulator is provided by the MPLAB Integrated Development Environment (IDE), which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator sys- tem with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of differ- ent processors. The universal architecture of the MPLAB ICE in-circuit emulator allows expansion to support new PICmicro microcontrollers. The MPLAB ICE in-circuit emulator system has been designed as a real-time emulation system, with advanced features that are generally found on more expensive development tools. The PC platform and Microsoft ® Windows environment were chosen to best make these features available to you, the end user.

10.7 ICEPIC In-Circuit Emulator

The ICEPIC low cost, in-circuit emulator is a solution for the Microchip Technology PIC16C5X, PIC16C6X, PIC16C7X and PIC16CXXX families of 8-bit One- Time-Programmable (OTP) microcontrollers. The mod- ular system can support different subsets of PIC16C5X or PIC16CXXX products through the use of inter- changeable personality modules, or daughter boards. The emulator is capable of emulating without target application circuitry being present.

 2001 Microchip Technology Inc. Preliminary DS70031A-page 71 rfPIC12C509AG/509AF

10.8 MPLAB ICD In-Circuit Debugger

Microchip's In-Circuit Debugger, MPLAB ICD, is a pow- erful, low cost, run-time development tool. This tool is based on the FLASH PICmicro MCUs and can be used to develop for this and other PICmicro microcontrollers. The MPLAB ICD utilizes the in-circuitdebugging capa- bility built into the FLASH devices. This feature, along with Microchip's In-Circuit Serial Programming TM proto- col, offers cost-effective in-circuit FLASH debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by watch- ing variables, single-stepping and setting break points. Running at full speed enables testing hardware in real- time.

10.9 PRO MATE II Universal Device

The PRO MATE II universal device programmer is a full-featured programmer, capable of operating in stand-alone mode, as well as PC-hosted mode. The PRO MATE II device programmer is CE compliant. The PRO MATE II device programmer has program- mable V DD and VPP supplies, which allow it to verify programmed memory at VDD min and VDD max for max- imum reliability. It has an LCD display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In stand-alone mode, the PRO MATE II device programmer can read, verify, or program PICmicro devices. It can also set code protection in this mode.

10.10 PICSTART Plus Entry Level

The PICSTART Plus development programmer is an easy-to-use, low cost, prototype programmer. It con- nects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer sup- ports all PICmicro devices with up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant.

10.11 PICDEM 1 Low Cost PICmicro

The PICDEM 1 demonstration board is a simple board which demonstrates the capabilities of several of Microchip’s microcontrollers. The microcontrollers sup- ported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The user can program the sample microcon- trollers provided with the PICDEM 1 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer, and easily test firmware. The user can also connect the PICDEM 1 demonstration board to the MPLAB ICE in- circuit emulator and download the firmware to the emu- lator for testing. A prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simu- lated analog input, push button switches and eight LEDs connected to PORTB.

10.12 PICDEM 2 Low Cost PIC16CXX

The PICDEM 2 demonstration board is a simple dem- onstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and soft- ware is included to run the basic demonstration pro- grams. The user can program the sample microcontrollers provided with the PICDEM 2 demon- stration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer, and easily test firmware. The MPLAB ICE in-circuit emula- tor may also be used with the PICDEM 2 demonstration board to test firmware. A prototype area has been pro- vided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push button switches, a potentiometer for simulated analog input, a serial EEPROM to demonstrate usage of the I 2C TM bus and separate headers for connection to an LCD module and a keypad.

DS70031A-page 72 Preliminary  2001 Microchip Technology Inc.

10.13 PICDEM 3 Low Cost PIC16CXXX

The PICDEM 3 demonstration board is a simple dem- onstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with an LCD Mod- ule. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers pro- vided with the PICDEM 3 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer with an adapter socket, and easily test firmware. The MPLAB ICE in-circuit emula- tor may also be used with the PICDEM 3 demonstration board to test firmware. A prototype area has been pro- vided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM 3 demonstration board is a LCD panel, with 4 commons and 12 segments, that is capable of display- ing time, temperature and day of the week. The PICDEM 3 demonstration board provides an additional RS-232 interface and Windows software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.

10.14 PICDEM 17 Demonstration Board

The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756A, PIC17C762 and PIC17C766. All neces- sary hardware is included to run basic demo programs, which are supplied on a 3.5-inch disk. A programmed sample is included and the user may erase it and program it with the other sample programs using the PRO MATE II device programmer, or the PICSTART Plus development programmer, and easily debug and test the sample code. In addition, the PICDEM 17 dem- onstration board supports downloading of programs to and executing out of external FLASH memory on board. The PICDEM 17 demonstration board is also usable with the MPLAB ICE in-circuit emulator, or the PICMASTER emulator and all of the sample programs can be run and modified using either emulator. Addition- ally, a generous prototype area is available for user hardware.

10.15 K EE LOQ Evaluation and

KEE LOQ evaluation and programming tools support Microchip’s HCS Secure Data Products. The HCS eval- uation kit includes a LCD display to show changing codes, a decoder to decode transmissions and a pro- gramming interface to program test transmitters.

 2001 Microchip Technology Inc. Preliminary DS70031A-page 73 rfPIC12C509AG/509AF TABLE 10-1: DEVELOPMENT TOOLS FROM MICROCHIP PIC12CXXX PIC14000 PIC16C5X PIC16C6X PIC16CXXX PIC16F62X PIC16C7X PIC16C7XX PIC16C8X PIC16F8XX PIC16C9XX PIC17C4X PIC17C7XX PIC18CXX2 PIC18FXXX 24CXX/ 25CXX/ 93CXX HCSXXX MCRFXXX MCP2510 Software Tools MPLAB ® Integrated Development Environment /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld MPLAB ® C17 C Compiler /checkbld /checkbld MPLAB ® C18 C Compiler /checkbld /checkbld MPASM TM Assembler/ MPLINK TM Object Linker /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld Emulators MPLAB ® ICE In-Circuit Emulator /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld ** /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld ICEPICTM In-Circuit Emulator /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld Debugger MPLAB ® ICD In-Circuit Debugger /checkbld * /checkbld * /checkbld /checkbld Programmers PICSTART ® Plus Entry Level Development Programmer /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld PRO MATE ® II Universal Device Programmer /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld /checkbld Demo Boards and Eval Kits PICDEM TM 1 Demonstration Board /checkbld /checkbld /checkbld † /checkbld /checkbld PICDEM TM 2 Demonstration Board /checkbld † /checkbld † /checkbld /checkbld PICDEM TM 3 Demonstration Board /checkbld PICDEM TM 14A Demonstration Board /checkbld PICDEM TM 17 Demonstration Board /checkbld K EE LOQ ® Evaluation Kit /checkbld K EE LOQ ® Transponder Kit /checkbld microIDTM Programmer’s Kit /checkbld 125 kHz microIDTM Developer’s Kit /checkbld 125 kHz Anticollision microIDTM Developer’s Kit /checkbld

13.56 MHz Anticollision

microIDTM Developer’s Kit /checkbld MCP2510 CAN Developer’s Kit /checkbld * Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB® ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77. ** Contact Microchip Technology Inc. for availability date. † Development tool is available on select devices.

DS70031A-page 74 Preliminary  2001 Microchip Technology Inc. NOTES:

 2001 Microchip Technology Inc. Preliminary DS70031A-page 75 rfPIC12C509AG/509AF

11.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings† Absolute Maximum Ratings - PICmicro Absolute Maximum Ratings - Transmitter Note 1: Power Dissipation is calculated as follows: PDIS =V DD x{ IDD -∑ IOH }+ ∑ {(VDD -VOH )xIOH }+ ∑ (VOL xIOL ) †NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

 2001 Microchip Technology Inc. Preliminary DS70031A-page 77 rfPIC12C509AG/509AF

11.1 DC CHARACTERISTICS: rfPIC12C509AG/509AF (Industrial)

DC Characteristics Standard Operating Conditions (unless otherwise specified) Operating T emperature –40 °C ≤ TA ≤ +85°C (industrial) Param No. Sym Characteristic Min Typ (1) Max Units Conditions D001 V DD Supply Voltage 2.5 5.5 V See Figures 11-1 through 11-2 D002 V DR RAM Data Retention Voltage(2) 1.5* V Device in SLEEP mode D003 V POR VDD Start Voltage to ensure Power-on Reset VSS V See section on Power-on Reset for details D004 S VDD VDD Rise Rate to ensure Power-on Reset 0.05 V/ms See section on Power-on Reset for details D010 D010C D010A IDD Supply Current(3) - 0.4 0.4 115 0.8 0.8 mA mA µA XT and EXTRC options (Note 4) FOSC =4M H z ,VDD =2 . 5 V INTRC Option FOSC =4M H z ,VDD =2 . 5 V LP Option, Industrial T emperature F OSC =3 2k H z ,VDD =2 . 5 V ,W D Td i s a b l e d D020 D021 D021B I PD Power-Down Current (5) -0 . 24 µAV DD =2 . 5 V ,I n d u s t r i a l ΔIWDT -2 . 05 µAV DD =2 . 5 V ,I n d u s t r i a l 1A Fosc LP Oscillator Operating Frequency XT Oscillator Operating Frequency 200 kHz MHz All temperatures All temperatures * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guid- ance only and is not tested. 2: This is the limit to which V DD can be lowered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) The test conditions for all I DD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to Vss, T0CKI = VDD, MCLR= VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. 4: Does not include current through REXT . The current through the resistor can be estimated by the formula: IR =V DD /2REXT (mA) with REXT in kOhm. 5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS .

DS70031A-page 78 Preliminary  2001 Microchip Technology Inc.

11.2 DC CHARACTERISTICS: rfPIC12C509AG/509AF (Industrial)

Standard Operating Conditions (unless otherwise specified) Operating Temperature –40 °C ≤ TA ≤ +85°C (industrial) Operating voltage VDD range as described in DC spec Section 11.1. Param No. Sym Characteristic Min Typ† Max Units Conditions Input Low Voltage VIL I/O ports D030 with TTL buffer Vss - 0.8V V For 4.5V ≤ VDD ≤ 5.5V Vss - 0.15V DD V otherwise D031 with Schmitt Trigger buffer Vss - 0.2V DD V D032 MCLR , GP2/T0CKI (in EXTRC mode) VSS -0 . 2 VDD V D033 OSC1 (in EXTRC mode) Vss - 0.2V DD V Note 1 D033 OSC1 (in XT and LP) V SS -0 . 3 VDD V Note 1 Input High Voltage VIH I/O ports - D040 with TTL buffer 2.0V - V DD V4 . 5 V≤ VDD ≤ 5.5V D040A 0.25V DD + 0.8V -V DD V otherwise D041 with Schmitt Trigger buffer 0.8V DD -V DD V For entire VDD range D042 MCLR , GP2/T0CKI 0.8V DD -V DD V D042A OSC1 (XT and LP) 0.7V DD -V DD V Note 1 D043 OSC1 (in EXTRC mode) 0.9V DD -V DD V D070 I PUR GPIO weak pull-up current (Note 4) 30 250 400 µAV DD =5 V ,VPIN =V SS Input Leakage Current(Notes 2, 3) D060 I IL I/O ports - - + 1 µAV s s ≤ VPIN ≤ VDD ,P i na t hi-impedance D061 D061A GP3/MCLR (Note 5) GP3/MCLR (Note 6) 130 250 µA µA Vss ≤ VPIN ≤ VDD Vss ≤ VPIN ≤ VDD D063 OSC1 - - + 5 µAV s s ≤ VPIN ≤ VDD , XT and LP osc configuration Output Low Voltage D080 V OL I/O ports - - 0.6 V I OL =8 . 5m A ,VDD =4 . 5 V , –40°Ct o+ 8 5°C D080A - - 0.6 V I OL =7 . 0m A ,VDD =4 . 5 V , –40°Ct o+ 1 2 5°C Output High Voltage D090 V OH I/O ports (Note 3) V DD -0 . 7 - - V I OH =- 3 . 0m A ,VDD =4 . 5 V , –40°Ct o+ 8 5°C D090A V DD -0 . 7 - - V I OH =- 2 . 5m A ,VDD =4 . 5 V , –40°C to +125°C Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin - - 15 pF In XT and LP modes when exter- nal clock is used to drive OSC1. D101 C IO All I/O pins - - 50 pF † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the rfPIC12C509AG be driven with external clock in RC mode. 2: The leakage current on the MCLRpin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. 4: Does not include GP3. For GP3 parameters D0061 and D0061A.

 2001 Microchip Technology Inc. Preliminary DS70031A-page 79 rfPIC12C509AG/509AF TABLE 11-1: PULL-UP RESISTOR RANGES*

11.3 Reset

When MCLR is asserted, the state of the OSC1/CLKIN and OSC2 pins are as follows: VDD (Volts) Temperature ( °C) Min Typ Max Units GP0/GP1 2.5 –40 38K 42K 63K Ω 25 42K 48K 63K Ω 85 42K 49K 63K Ω 5.5 –40 15K 17K 20K Ω 25 18K 20K 23K Ω 85 19K 22K 25K Ω GP3 (1) 2.5 –40 65K 80K 850K Ω 25 80K 100K 1150K Ω 85 85K 110K 1300K Ω 5.5 –40 50K 60K 600K Ω 25 60K 65K 750K Ω 85 65K 80K 900K Ω * These parameters are characterized but not tested. Note 1: The weak pull-up resistor and associated current for the GP3/MCLRpin is non-linear when the respective pin voltage is less than VDD - 1.0V. See parameter D061 for GP3/MCLRpin current specifications. TABLE 11-2: CLKIN/CLKOUT PIN STATES WHEN MCLR ASSERTED Oscillator Mode OSC1/CLKIN Pin OSC2 Pin EXTRC OSC1 pin is tristated and driven by external circuit OSC2 pin is driven low INTRC OSC1 pin is tristate input OSC2 pin is tristate input

DS70031A-page 80 Preliminary  2001 Microchip Technology Inc.

11.4 Timing Parameter Symbology and Load Conditions

The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase subscripts (pp) and their meanings: pp 2t o m c M C L R ck CLKOUT osc oscillator cy cycle time os OSC1 drt device reset timer t0 T0CKI io I/O port wdt watchdog timer Uppercase letters and their meanings: S F Fall P Period HH i g h RR i s e I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance FIGURE 11-3: LOAD CONDITIONS C L VSS Pin C L = 50 pF for all pins except OSC2 15 pF for OSC2 in XT, HS or LP modes when external clock is used to drive OSC1

 2001 Microchip Technology Inc. Preliminary DS70031A-page 81 rfPIC12C509AG/509AF

11.5 Timing Diagrams and Specifications

FIGURE 11-4: EXTERNAL CLOCK TIMING TABLE 11-3: EXTERNAL CLOCK TIMING REQUIREMENTS AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature –40 °C ≤ TA ≤ +85°C( i n d u s t r i a l ) Operating Voltage VDD range is described in Section 11.1 Parameter No. Sym Characteristic Min Typ (1) Max Units Conditions FOSC External CLKIN Frequency(2) DC — 4 MHz XT osc mode DC — 200 kHz LP osc mode Oscillator Frequency(2) DC — 4 MHz EXTRC osc mode 0.1 — 4 MHz XT osc mode DC — 200 kHz LP osc mode 1T OSC External CLKIN Period(2) 250 — — ns XT osc mode 5—— m s L P o s c m o d e Oscillator Period(2) 250 — — ns EXTRC osc mode 250 — 10,000 ns XT osc mode 5—— m s L P o s c m o d e 2T c y Instruction Cycle Time(3) —4 / F OSC —— 3T o s L , T o s HClock in (OSC1) Low or High Time50* — — ns XT oscillator 2* — — ms LP oscillator 4T o s R , T o s FClock in (OSC1) Rise or Fall Time— — 25* ns XT oscillator — — 50* ns LP oscillator * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 3: Instruction cycle period (TCY ) equals four times the input oscillator time base period. OSC1 Q4 Q1 Q2 Q3 Q4 Q1 13 3 44

DS70031A-page 82 Preliminary  2001 Microchip Technology Inc. TABLE 11-4: CALIBRATED INTERNAL RC FREQUENCIES AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature –40 °C ≤ TA ≤ +85°C (industrial) Operating Voltage VDD range is described in Section 10.1 Parameter No. Sym Characteristic Min* Typ (1) Max* Units Conditions Internal Calibrated RC Frequency3.65 4.00 4.28 MHz V DD =5 . 0 V Internal Calibrated RC Frequency3.55 — 4.31 MHz V DD =2 . 5 V * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

 2001 Microchip Technology Inc. Preliminary DS70031A-page 83 rfPIC12C509AG/509AF FIGURE 11-5: I/O TIMING TABLE 11-5: TIMING REQUIREMENTS AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature –40 °C ≤ TA ≤ +85°C (industrial) Operating Voltage VDD range is described in Section 11.1 Parameter No. Sym Characteristic Min Typ (1) Max Units

17 TosH2ioV OSC1 ↑ (Q1 cycle) to Port out valid(3) — — 100* ns

18 TosH2ioI OSC1 ↑ (Q2 cycle) to Port input invalid

(I/O in hold time) TBD — — ns

19 TioV2osH Port input valid to OSC1 ↑

(I/O in setup time) TBD — — ns

20 TioR Port output rise time (2, 3) — 10 25** ns

21 TioF Port output fall time (2, 3) — 10 25** ns

• These parameters are characterized but not tested. ** These parameters are design targets and are not tested. No characterization data available at this time. Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: Measurements are taken in EXTRC mode. 3: See Figure 11-3 for loading conditions. OSC1 I/O Pin (input) I/O Pin (output) Q4 Q1 Q2 Q3 20, 21 Old Value New Value Note:All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.

DS70031A-page 84 Preliminary  2001 Microchip Technology Inc. FIGURE 11-6: RESET , WATCHDOG TIMER AND DEVICE RESET TIMER TABLE 11-6: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating T emperature –40 °C ≤ TA ≤ +85°C (industrial) Operating Voltage VDD range is described in Section 11.1 Parameter No. Sym Characteristic Min Typ (1) Max Units Conditions

30 TmcL MCLR Pulse Width (low) 2000* — — ns V DD =5V

31 Twdt Watchdog Timer Time-out Period

(No Prescaler) 9* 18* 30* ms V DD = 5 V (Commercial)

32 T DRT Device Reset Timer Period(2) 9* 18* 30* ms V DD = 5 V (Commercial)

34 Tio Z I/O Hi-impedance from MCLRLow — — 2000* ns

• These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: See T able 13-6. V DD MCLR Internal POR DRTTimeout Internal RESET Watchdog Timer Reset I/O pin 32 32 (Note 1) Note 1:I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software. (Note 2) 2:Runs in MCLR or WDT Reset only in XT and LP modes.

 2001 Microchip Technology Inc. Preliminary DS70031A-page 85 rfPIC12C509AG/509AF TABLE 11-7: DRT (DEVICE RESET TIMER PERIOD) FIGURE 11-7: TIMER0 CLOCK TIMINGS TABLE 11-8: TIMER0 CLOCK REQUIREMENTS Oscillator Configuration POR Reset Subsequent RESETS IntRC & ExtRC 18 ms (typical) (1) 300 µs (typical)(1) XT & LP 18 ms (typical) (1) 18 ms (typical)(1) Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature –40 °C ≤ TA ≤ +85°C (industrial) Operating Voltage VDD range is described in Section 11.1. Parameter No. Sym Characteristic Min Typ (1) Max Units Conditions 40 Tt0H T0CKI High Pulse Width- No Prescaler 0.5 TCY + 20* — — ns - With Prescaler 10* — — ns 41 Tt0L T0CKI Low Pulse Width- No Prescaler 0.5 TCY + 20* — — ns - With Prescaler 10* — — ns

42 Tt0P T0CKI Period 20 or T CY +4 0*

N — — ns Whichever is greater. N =Prescale Value (1, 2, 4,..., 256) * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. T0CKI 40 41

DS70031A-page 86 Preliminary  2001 Microchip Technology Inc.

11.6 Transmitter Characteristics: rfPIC12C509AG/509AF (Industrial)

TABLE 11-9: TRANSMITTER DC CHARACTERISTICS* * These parameters are characterized but not tested. † Data in “Typ” column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Depends on output power selection. See Table 7-5. Note 2: Applies to RFEN pin. TABLE 11-10: TRANSMITTER AC CHARACTERISTICS* * These parameters are characterized but not tested. † Data in “Typ” column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Values dependent on PLL loop filter values. Note 2: ton equals crystal oscillator and PLL start up time. DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating T emperature -40°C≤ TA ≤ +85°C Param No. Sym Characteristic Min Typ † Max Units Conditions VDDRF Supply Voltage 2.1 — 5.5 V IPDRF Power-Down Current — 0.05 0.1 µAR F EN =0 IDDRF Supply Current 4.8 — 11.5 mA Note 1 VILRF Input Low Voltage -0.3 — 0.3V SSRF V Note 2 VIHRF Input High Voltage 0.7VSSRF —V SSRF +0 . 3 V Note 2 IILRF Input Leakage Current -1 — 1 µA AC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating T emperature -40°C≤ TA ≤ +85°C Param No. Sym Characteristic Min Typ † Max Units Conditions fxtal Crystal Frequency 9.69 — 15 MHz ftransmit Transmit Frequency 310 — 480 MHz Fixed, set by f xtal fCLKOUT CLKOUT Frequency 2.42 — 3.75 MHz Fixed, set by f xtal Po Transmit Output Power -12 — +2 dBm See Table 7-5 fASK ASK Data Rate — — 40 kHz fFSK FSK Data Rate — — 20 kHz PREF Reference Spurs(1) —- 4 4— d B m f transmit±fxtal PCLK Clock Spurs(1) —- 4 4— d B m f transmit±fCLKOUT PHARM Harmonic Content — -40 — dBm 2f transmit,3 ftransmit, 4ftransmit,... POFF Spurious Output Signal — -60 — dBm Vps ≤ 0.1V PN Phase Noise — -87 — dBc/Hz f transmit± 500 kHz KVCO VCO Gain — 100 — MHz/V ICP Charge Pump Current — ±260 — µA VCLKOUT Clock Voltage Swing — 2 — V PP C load=5p F ton Start-up Time — 0.9 — ms Note 2

 2001 Microchip Technology Inc. Preliminary DS70031A-page 87 rfPIC12C509AG/509AF

12.0 DC AND AC CHARACTERISTICS

“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3σ) or (mean - 3σ) respectively, whereσ is a standard deviation over the whole temperature range. FIGURE 12-1: CALIBRATED INTERNAL RC FREQUENCY RANGE VS. TEMPERATURE DD =5 . 0 V ) (INTERNAL RC IS CALIBRATED TO 25°C, 5.0V) FIGURE 12-2: CALIBRATED INTERNAL RC FREQUENCY RANGE VS. TEMPERATURE DD =2 . 5 V ) (INTERNAL RC IS CALIBRATED TO 25°C, 5.0V) The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 4.40 4.30 4.20 4.10 4.00 3.90 3.80 3.70 3.60 3.50 -40 25 85 125 4.50 Max. Min. Frequency (MHz) Temperature (Deg.C) 4.40 4.30 4.20 4.10 4.00 3.90 3.80 3.70 3.60 3.50 -40 25 85 125 4.50 Max. Min. Frequency (MHz) Temperature (Deg.C)

DS70031A-page 92 Preliminary  2001 Microchip Technology Inc. FIGURE 12-15: VIL, VIH OF NMCLR, AND T0CKI VS. VDD 3.5 3.0 2.5 2.0 1.5 1.0 0.5 2.5 3.5 4.5 5.5 VDD (Volts) VIL,VIH (Volts) Vih Max (-40 to 125) VIH Typ (25) VIH M i n( - 4 0t o1 2 5 ) VILMax (-40 to 125) VILTyp (25) VILMin (-40 to 125)

 2001 Microchip Technology Inc. Preliminary DS70031A-page 93 rfPIC12C509AG/509AF

13.0 PACKAGING INFORMATION

13.1 Package Marking Information

18-Lead SOIC (.300”) Example Example XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 20-Lead SSOP XXXXXXXXXXX XXXXXXXXXXX YYWWNNN rfPIC 9901CBA 12C509AG/JW rfPIC 12C509AG/SO 9918CDK rfPIC 12C509AF/SS 9951CBP Example 20-Lead CERDIP Windowed XXXXXXXX YYWWNNN XXXXXXXX Example rfPIC 9901CBA 12C509AF/JW Legend: XX...X Customer specific information* Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard PICmicro device marking consists of Microchip part number, year code, week code, and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.

DS70031A-page 94 Preliminary  2001 Microchip Technology Inc. Package Type: 18-Lead CERDIP 18-Lead Ceramic Dual In-line with Window (JW) - 300 mil (CERDIP) 3.30 3.56 3.81 .150.140.130W1Window Width 2.54.100pPitch 1818nNumber of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units D n c eB E p L B A * Controlling Parameter § Significant Characteristic JEDEC Equivalent: MO-036 Drawing No. C04-010

 2001 Microchip Technology Inc. Preliminary DS70031A-page 95 rfPIC12C509AG/509AF Package Type: 18-Lead SOIC - 300 mil 18-Lead Plastic Small Outline (SO) - Wide, 300 mil (SOIC) Foot Angle φ 048048 1512015120βMold Draft Angle Bottom 1512015120αMold Draft Angle Top 1.27.050pPitch 1818nNumber of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units Lβ c φ h 45° D p nB E α A * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-051 § Significant Characteristic

DS70031A-page 96 Preliminary  2001 Microchip Technology Inc. Package Type: 20-Lead SSOP 20-Lead Plastic Shrink Small Outline (SS) - 209 mil, 5.30 mm (SSOP) 10501050βMold Draft Angle Bottom 10501050αMold Draft Angle Top 203.20101.600.00840φFoot Angle 0.65.026pPitch 2020nNumber of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units D p n B E L c β φ α A2A * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-150 Drawing No. C04-072 § Significant Characteristic

 2001 Microchip Technology Inc. Preliminary DS70031A-page 97 INDEX A Assembler B Block Diagram C Crystal Oscillator ASK Operation Cystal Oscillator FSK Operation D E F I K L M MPLAB ICE High Performance Universal In-Circuit MPLAB Integrated Development Environment O Oscillator Types P PICDEM 2 Low Cost PIC16CXX Demonstration Board.... 71 PICDEM 3 Low Cost PIC16CXXX Demonstration PICSTART Plus Entry Level Development POR

DS70031A-page 98 Preliminary  2001 Microchip Technology Inc. Q R Registers S T Timer0 U W Z

 2001 Microchip Technology Inc. Preliminary DS70031A-page 99 rfPIC12C509AG/509AF Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. T o view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site. Connecting totheMicrochip InternetWebSite The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP ser- vice to connect to: ftp://ftp.microchip.com T h ew e bs i t ea n df i l et r a n s f e rs i t ep r o v i d eav a r i e t yo f services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A vari- ety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is:

• Latest Microchip Press Releases
• T echnical Support Section with Frequently Asked Questions
• Design Tips
• D e v i c e E r r a t a
• J o b P o s t i n g s
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to Microchip Products
• Conferences for products, Development Sys- tems, technical information and more
• Listing of seminars and events 013001

DS70031A-page 100 Preliminary  2001 Microchip Technology Inc. READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? To : T echnical Publications Manager RE: Reader Response Total Pages Sent From: Name Company Address City / State / ZIP / Country Application (optional): Would you like a reply? Y N Device: Literature Number: Questions: DS70031ArfPIC12C509AG/509AF

 2000 Microchip Technology Inc. Preliminary DS70031A-page101 rfPIC12C509AG/509AF rfPIC12C509AG/509AF PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. T o determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. Pattern: Special Requirements Package: SO = 300 mil SOIC SS = 209 mil SSOP JW = 300 mil Windowed Ceramic Side Brazed Temperature Range: Device rfPIC12C509AG rfPIC12C509AF PART NO. X /XX XXX Examples a) rfPIC12C509AG/JW Industrial T emp., Win- dowed CERDIP , 4 MHz b) rfPIC12C509AG/SO Industrial T emp., SOIC package, 4 MHz c) rfPIC12C509AF/SS Industrial T emp., SSOP package, 4 MHz

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