RFP70N03 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • 70A, 30V
  • r DS(ON) = 0.010Ω
  • Temperature Compensating PSPICE® Model
  • Peak Current vs Pulse Width Curve
  • UIS Rating Curve (Single Pulse)
  • 175 oC Operating Temperature
  • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol Packaging JEDEC TO-220AB JEDEC TO-263AB

Ordering Information

RFP70N03 TO-220AB RFP70N03 RF1S70N03SM TO-263AB F1S70N03 NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-263AB variant in tape and reel, e.g., RF1S70N03SM9A D G S DRAIN (FLANGE) SOURCE DRAIN GATE DRAIN (FLANGE) GATE SOURCE Data Sheet July 1999 File Number 3404.4

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified UNITS Drain Current 200 A A 150 1.0 W W/oC Maximum Temperature for Soldering 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationo ft h e device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical SpecificationsTC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BV DSS ID = 250µA, VGS = 0V (Figure 10) 30 - - V Gate to Source Threshold Voltage V GS(TH) VGS = VDS , ID = 250µA (Figure 9) 2 - 4 V Zero Gate Voltage Drain Current I DSS VDS = 30V, VGS = 0V - - 1 µA VDS = 30V, VGS = 0V, TC = 150oC- - 5 0 µA Gate to Source Leakage Current I GSS VGS =±20V - - 100 nA Drain to Source On Resistance r DS(ON) ID = 70A, VGS = 10V (Figure 8) - - 0.010 Ω Turn-On Time t ON VDD = 15V, ID ≅ 70A, R L = 0.214Ω , VGS = 10V, R GS = 2.5Ω - - 80 ns Turn-On Delay Time t d(ON) -2 0-n s Rise Time t r -2 0-n s Turn-Off Delay Time t d(OFF) -4 0-n s Fall Time t f -2 5-n s Turn-Off Time t OFF - - 125 ns Total Gate Charge Q g(TOT) VGS = 0V to 20V VDD = 24V, ID ≅ 70A, R L = 0.343Ω Ig(REF) = 1.0mA (Figure 12) - 215 260 nC Gate Charge at 10V Q g(10) VGS = 0V to 10V - 120 145 nC Threshold Gate Charge Q g(TH) VGS = 0V to 2V - 6.5 8.0 nC Input Capacitance C ISS VDS = 25V, VGS = 0V, f = 1MHz (Figure 11) - 3300 - pF Output Capacitance C OSS - 1750 - pF Reverse Transfer Capacitance C RSS - 750 - pF Thermal Resistance Junction to Case R θJC (Figure 3) - - 1.0 oC/W Thermal Resistance Junction to Ambient R θJA TO-220, TO-263 - - 62 oC/W Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage V SD ISD = 70A - - 1.5 V Reverse Recovery Time t rr ISD = 70A, dISD /dt = 100A/µs - - 125 ns RFP70N03, RF1S70N03SM

FIGURE 17. GATE CHARGE TEST CIRCUIT FIGURE 18. GATE CHARGE WAVEFORM

.SUBCKT RFP70N03 2 1 3 ; rev 9/16/92 *NOM TEMP = 25 oC CA 12 8 6.09e-9 CB 15 14 6.05e-9 CIN 6 8 3.40e-9 DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 35.4 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 3.10e-9 LSOURCE 3 7 1.82e-9 MOS1 16 6 8 8 MOSMOD M=0.99 MOS2 16 21 8 8 MOSMOD M=0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 30.7e-6 RGATE 9 20 0.890 RIN 6 8 1e9 RSOURCE 8 7 RDSMOD 3.92e-3 RVTO 18 19 RVTOMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 0.605 .MODEL DBKMOD D (RS=3.9e-2 TRS1=1.05e-4 TRS2=3.11e-5) .MODEL DPLCAPMOD D (CJO=4.8e-9 IS=1e-30 N=10) .MODEL MOSMOD NMOS (VTO=3.46 KP=47 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL RBKMOD RES (TC1=8.46e-4 TC2=-8.48e-7) .MODEL RDSMOD RES (TC1=2.23e-3 TC2=6.56e-6) .MODEL RVTOMOD RES (TC1=-3.29e-3 TC2=3.49e-7) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-8.35 VOFF=-6.35) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-6.35 VOFF=-8.35) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.0 VOFF=3.0) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=3.0 VOFF=-2.0) .ENDS NOTE: For further discussion of the PSPICE model consultA New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; written by William J. Hepp and C. Frank Wheatley. DPLCAP RDRAIN DBREAK LDRAIN DRAIN SOURCE LSOURCE DBODY RBREAK RVTO VBAT 19IT RSOURCE EBREAK MOS2 EDSEGS RIN CIN VTO ESG S1A S2A S2BS1B CBCA EVTO RGATE GATE LGATE 1817 2091 12 15 13 + + - MOS1 8 17 RFP70N03, RF1S70N03SM

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 RFP70N03, RF1S70N03SM

1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. PSPICE® is a registered trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999 RFP70N03, RF1S70N03SM 70A, 30V, 0.010 Ohm, N-Channel Power MOSFETs These N-Channel power MOSFETs are manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers, and relay drivers. These transistors can be operated directly from integrated circuits. Formerly developmental type TA49025.

  • 70A, 30V
  • r DS(ON) = 0.010Ω
  • Temperature Compensating PSPICE® Model
  • Peak Current vs Pulse Width Curve
  • UIS Rating Curve (Single Pulse)
  • 175 oC Operating Temperature
  • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol Packaging JEDEC TO-220AB JEDEC TO-263AB

RFP70N03 TO-220AB RFP70N03 RF1S70N03SM TO-263AB F1S70N03 NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-263AB variant in tape and reel, e.g., RF1S70N03SM9A D G S DRAIN (FLANGE) SOURCE DRAIN GATE DRAIN (FLANGE) GATE SOURCE Data Sheet July 1999 File Number 3404.4

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified UNITS Drain Current 200 A A 150 1.0 W W/oC Maximum Temperature for Soldering 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationo ft h e device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical SpecificationsTC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BV DSS ID = 250µA, VGS = 0V (Figure 10) 30 - - V Gate to Source Threshold Voltage V GS(TH) VGS = VDS , ID = 250µA (Figure 9) 2 - 4 V Zero Gate Voltage Drain Current I DSS VDS = 30V, VGS = 0V - - 1 µA VDS = 30V, VGS = 0V, TC = 150oC- - 5 0 µA Gate to Source Leakage Current I GSS VGS =±20V - - 100 nA Drain to Source On Resistance r DS(ON) ID = 70A, VGS = 10V (Figure 8) - - 0.010 Ω Turn-On Time t ON VDD = 15V, ID ≅ 70A, R L = 0.214Ω , VGS = 10V, R GS = 2.5Ω - - 80 ns Turn-On Delay Time t d(ON) -2 0-n s Rise Time t r -2 0-n s Turn-Off Delay Time t d(OFF) -4 0-n s Fall Time t f -2 5-n s Turn-Off Time t OFF - - 125 ns Total Gate Charge Q g(TOT) VGS = 0V to 20V VDD = 24V, ID ≅ 70A, R L = 0.343Ω Ig(REF) = 1.0mA (Figure 12) - 215 260 nC Gate Charge at 10V Q g(10) VGS = 0V to 10V - 120 145 nC Threshold Gate Charge Q g(TH) VGS = 0V to 2V - 6.5 8.0 nC Input Capacitance C ISS VDS = 25V, VGS = 0V, f = 1MHz (Figure 11) - 3300 - pF Output Capacitance C OSS - 1750 - pF Reverse Transfer Capacitance C RSS - 750 - pF Thermal Resistance Junction to Case R θJC (Figure 3) - - 1.0 oC/W Thermal Resistance Junction to Ambient R θJA TO-220, TO-263 - - 62 oC/W Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage V SD ISD = 70A - - 1.5 V Reverse Recovery Time t rr ISD = 70A, dISD /dt = 100A/µs - - 125 ns RFP70N03, RF1S70N03SM

FIGURE 17. GATE CHARGE TEST CIRCUIT FIGURE 18. GATE CHARGE WAVEFORM

.SUBCKT RFP70N03 2 1 3 ; rev 9/16/92 *NOM TEMP = 25 oC CA 12 8 6.09e-9 CB 15 14 6.05e-9 CIN 6 8 3.40e-9 DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 35.4 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 3.10e-9 LSOURCE 3 7 1.82e-9 MOS1 16 6 8 8 MOSMOD M=0.99 MOS2 16 21 8 8 MOSMOD M=0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 30.7e-6 RGATE 9 20 0.890 RIN 6 8 1e9 RSOURCE 8 7 RDSMOD 3.92e-3 RVTO 18 19 RVTOMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 0.605 .MODEL DBKMOD D (RS=3.9e-2 TRS1=1.05e-4 TRS2=3.11e-5) .MODEL DPLCAPMOD D (CJO=4.8e-9 IS=1e-30 N=10) .MODEL MOSMOD NMOS (VTO=3.46 KP=47 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL RBKMOD RES (TC1=8.46e-4 TC2=-8.48e-7) .MODEL RDSMOD RES (TC1=2.23e-3 TC2=6.56e-6) .MODEL RVTOMOD RES (TC1=-3.29e-3 TC2=3.49e-7) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-8.35 VOFF=-6.35) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-6.35 VOFF=-8.35) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.0 VOFF=3.0) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=3.0 VOFF=-2.0) .ENDS NOTE: For further discussion of the PSPICE model consultA New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; written by William J. Hepp and C. Frank Wheatley. DPLCAP RDRAIN DBREAK LDRAIN DRAIN SOURCE LSOURCE DBODY RBREAK RVTO VBAT 19IT RSOURCE EBREAK MOS2 EDSEGS RIN CIN VTO ESG S1A S2A S2BS1B CBCA EVTO RGATE GATE LGATE 1817 2091 12 15 13 + + - MOS1 8 17 RFP70N03, RF1S70N03SM

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 RFP70N03, RF1S70N03SM