RFG45N06_02 FAIRCHILD | Alldatasheet
Document overview
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Technical content
Features
- 45A, 60V DS(ON) = 0.028 Ω
- Temperature Compensating PSPICE Model
- Peak Current vs Pulse Width Curve
- UIS Rating Curve
- 175 o C Operating Temperature
- Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol Packaging
Ordering Information
RFP45N06 TO-220AB RFP45N06 RF1S45N06SM TO-263AB F1S45N06 NOTE: When ordering, use the entire part number. Add the suffix, 9A, to obtain the TO-263AB variant in tape and reel, i.e. RF1S45N06SM9A. DRAIN SOURCE GATE JEDEC STYLE TO-247 JEDEC TO-220AB JEDEC TO-263AB DRAIN (BOTTOM SIDE METAL) SOURCE DRAIN GATE DRAIN (FLANGE) SOURCE DRAIN GATE DRAIN (FLANGE)GATE SOURCE Data Sheet January 2002
©2002 Fairchild Semiconductor Corporation RFG45N06, RFP45N06, RF1S45N06SM Rev. B Absolute Maximum Ratings T C = 25 o C, Unless Otherwise Specified RFG45N06, RFP45N06 RF1S45N06SM UNITS DSS 60 V Drain to Gate Voltage (R G = 20K Ω DGR 60 V D DM Refer to Peak Current Curve A GS 20 V AS Refer to UIS Curve D 131 0.877 W o C J , T STG -55 to 175 o C Maximum Temperature for Soldering L pkg 300 260 o C o C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. T J = 25 o C to 150 o Electrical Specifications T C = 25 o C, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BV DSS I D = 250 µ A, V GS = 0V (Figure 11) 60 - - V Gate Threshold Voltage V GS(TH) V GS = V DS , I D = 250 µ A (Figure 10) 2 - 4 V Zero Gate Voltage Drain Current I DSS V DS = Rated BV DSS , V GS = 0V - - 1 µ A V DS = 0.8 x Rated BV DSS , V GS = 0V (125 o C) - - 25 µ A Gate to Source Leakage Current I GSS V GS 20V - - 100 nA Drain Source On Resistance (Note 2) r DS(ON) I D = 45A, V GS = 10V (Figure 9) - - 0.028 Ω Turn-On Time t ON V DD = 30V, I D = 45A R L = 0.667 Ω , V GS = +10V R G = 3.6 Ω (Figure 13) - - 120 ns Turn-On Delay Time t d(ON) -1 2- n s Rise Time t r -7 4- n s Turn-Off Delay Time t d(OFF) -3 7- n s Fall Time t f -1 6- n s Turn-Off Time t OFF - - 80 ns Total Gate Charge Q g(TOT) V GS = 0 to 20V V DD = 48V, I D = 45A, R L = 1.07 Ω I g(REF) = 1.5mA (Figure 13) - 125 150 nC Gate Charge at 10V Q g(10) V GS = 0 to 10V - 67 80 nC Threshold Gate Charge Q g(TH) V GS = 0 to 2V - 3.7 4.5 nC Input Capacitance C ISS V DS = 25V, V GS = 0V f = 1MHz (Figure 12) - 2050 - pF Output Capacitance C OSS - 600 - pF Reverse Transfer Capacitance C RSS - 200 - pF Thermal Resistance Junction to Case R θ JC - - 1.14 o C/W Thermal Resistance Junction to Ambient R θ JA -- 8 0 o C/W Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage V SD I SD = 45A - - 1.5 V Diode Reverse Recovery Time t rr I SD = 45A, dI SD /dt = 100A/ µ s - - 125 ns NOTES: 2. Pulse test: pulse width 300 µ s, duty cycle 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3) and Peak Current Capability Curve (Figure 5). RFG45N06, RFP45N06, RF1S45N06SM
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY
175 T C–
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
0.75 BVDSS
0.50 BVDSS
0.25 BVDSS
FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS
©2002 Fairchild Semiconductor Corporation RFG45N06, RFP45N06, RF1S45N06SM Rev. B .SUBCKT RFP45N06213 REV 1/18/93 *NOM TEMP = +25oC CA 12 8 3.49E-9 CB 15 14 3.8E-9 CIN 6 8 2E-9 DBODY 7 5 DBDMOD DBREAK 5 11DBKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 66.5 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 IT 8 17 1 LDRAIN 2 5 1E-9 LGATE 1 9 5.65E-9 LSOURCE 3 7 4.13E-9 MOS1 16 6 8 8 MOSMOD M=0.99 MOS2 16 21 8 8 MOSMOD M=0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 3.58E-3 RGATE 9 20 0.681 RIN 6 8 1E9 RSOURCE 8 7 RDSMOD 13.6E-3 RVTO 18 19 RVTOMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 0.92 .MODEL DBKMOD D (RS=1.93E-1 TRS1=5.13E-4 TRS2=-2.15E-5) .MODEL DPLCAPMOD D (CJO=1.25E-9 IS=1E-30 N=10) .MODEL MOSMOD NMOS (VTO=3.862 KP=55.57 IS=1E-30 N=10 TOX=1 L=1U W=1U) .MODEL RBKMOD RES (TC1=1.12E-3 TC2=-5.18E-7) .MODEL RDSMOD RES (TC1=4.64E-3 TC2=1.58E-5) .MODEL RVTOMOD RES (TC1=-4.27E-3 TC2=-6.55E-6) .MODEL S1AMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-6.5 VOFF=-1.7) .MODEL S1BMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-1.7 VOFF=-6.5) .MODEL S2AMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-3.0 VOFF=2) .MODEL S2BMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=2.0 VOFF=-3.0) .ENDS NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; authors, William J. Hepp and C. Frank Wheatley. DPLCAP RDRAIN DBREAK LDRAIN DRAIN SOURCE LSOURCE DBODY RBREAK RVTO VBAT 19IT RSOURCE EBREAK MOS2 EDSEGS RIN CIN VTO ESG S1A S2A S2BS1B CBCA EVTO RGATE GATE LGATE 1817 2091 12 15 + - + MOS1 8 17 RFG45N06, RFP45N06, RF1S45N06SM
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