RFG40N10LE INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • 40A, 100V
  • r DS(ON) = 0.040Ω
  • Temperature Compensating PSPICE® Model
  • Peak Current vs Pulse Width Curve
  • UIS Rating Curve
  • 175 oC Operating Temperature
  • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol Packaging

Ordering Information

RFG40N10LE TO-247 FG40N10L RFP40N10LE TO-220AB FP40N10L RF1S40N10LESM TO-263AB F40N10LE NOTE: When ordering, use the entire part number. Add the suffix, 9A, to obtain the TO-263AB variant in tape and reel, i.e. RF1S40N10LESM9A. D G S JEDEC STYLE TO-247 JEDEC TO-220AB JEDEC TO-263AB DRAIN (FLANGE) SOURCE DRAIN GATE GATE DRAIN (FLANGE) SOURCE DRAIN DRAIN (FLANGE) GATE SOURCE Data Sheet October 1999 File Number 4061.5

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFG40N10LE, RFP40N10LE, RF1S40N10LESM UNITS Refer to Peak Current Curve A 150 1.00 W W/oC Maximum Temperature for Soldering 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. T J = 25oC to 150oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BV DSS ID = 250µA, VGS = 0V (Figure 13) 100 - - V Gate Threshold Voltage V GS(TH) VGS = VDS, ID = 250µA (Figure 12) 1 - 3 V Zero Gate Voltage Drain Current I DSS VDS = 95V, VGS = 0V - - 1 µA VDS = 90V, VGS = 0V, TC = 150oC - - 250 µA Gate to Source Leakage Current I GSS VGS = ±10V - - 10 µA Drain to Source On Resistance (Note 2) r DS(ON) ID = 40A, VGS = 5V - - 0.040 Ω Turn-On Time t ON VDD = 50V, ID = 40A, RL = 1.25Ω, VGS = 5V, RGS = 2.5Ω (Figures 10, 18, 19) - - 200 ns Turn-On Delay Time t d(ON) -2 2-n s Rise Time t r - 140 - ns Turn-Off Delay Time t d(OFF) -7 0-n s Fall Time t f -6 5-n s Turn-Off Time t OFF - - 165 ns Total Gate Charge Q g(TOT) VGS = 0V to 10V V DD = 80V, ID = 40A, RL = 2.0Ω (Figures 20, 21) - 145 180 nC Gate Charge at 5V Q g(5) VGS = 0V to 5V - 85 105 nC Threshold Gate Charge Q g(TH) VGS = 0V to 1V - 3 4 nC Input Capacitance C ISS VDS = 25V, VGS = 0V, f = 1MHz (Figure 14) - 3000 - pF Output Capacitance C OSS - 500 - pF Reverse Transfer Capacitance C RSS - 200 - pF Thermal Resistance Junction-to-Case R θJC All Packages - - 1.0 oC/W Thermal Resistance Junction-to-Ambient R θJA TO-247 - - 30 oC/W TO-220AB and TO-263AB - - 80 oC/W Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage V SD ISD = 40A - - 1.5 V Diode Reverse Recovery Time t rr ISD = 40A, dISD/dt = 100A/µs - - 205 ns NOTES: 2. Pulse test: pulse width ≤ 80µs, duty cycle ≤ 2%. 3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). RFG40N10LE, RFP40N10LE, RF1S40N10LESM

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

175 T C–

SUBCKT 40N10LE 2 1 3 ; rev 8/15/95 CA 12 8 3.50e-9 CB 15 14 3.50e-9 CIN 6 8 1.70e-9 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 120.7 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1.00e-9 LGATE 1 9 5.17e-9 LSOURCE 3 7 2.13e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 2.04e-2 RGATE 9 20 2.15 RLDRAIN 2 5 10 RLGATE 1 9 51.7 RLSOURCE 3 7 21.3 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 4.85e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*79),3.5))} .MODEL DBREAKMOD D (RS = 3.12e-1 TRS1 = 1.07e-3 TRS2 = 0) .MODEL DPLCAPMOD D (CJO = 1.97e-9 IS = 1e-30 M = 0.87) .MODEL MMEDMOD NMOS (VTO = 1.73 KP = 2.80 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.15) .MODEL MSTROMOD NMOS (VTO = 2.04 KP = 80 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBREAKMOD RES (TC1 = 9.74e-4 TC2 = -3.71e-7) .MODEL RDRAINMOD RES (TC1 = 9.71e-3 TC2 = 2.90e-5) .MODEL RSLCMOD RES (TC1 = 2.17e-3 TC2 = 1.27e-6) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 0) .MODEL RVTHRESMOD RES (TC1 = -2.08e-3 TC2 = -6.82e-6) .MODEL RVTEMPMOD RES (TC1 = -1.52e-3 TC2 = -1.21e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.00 VOFF= -1.50) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.50 VOFF= -6.00) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.50 VOFF= 0.0) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.0 VOFF= -0.50) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. + - + - RBREAK RVTEMP VBAT RVTHRES IT 17 18 S1A S1B S2A S2B CA CB EGS EDS MWEAK EBREAK DBODY RSOURCE SOURCE 7 3 LSOURCE RLSOURCE CIN RDRAIN EVTHRES 1621 MMED MSTRO DRAIN LDRAIN RLDRAIN DBREAK DPLCAP ESLC RSLC1 RSLC2 GATE RGATE EVTEMP ESG LGATE RLGATE RFG40N10LE, RFP40N10LE, RF1S40N10LESM

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 RFG40N10LE, RFP40N10LE, RF1S40N10LESM