RFP2N20 INTERSIL | Alldatasheet

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Technical content

Features

  • 2A, 200V
  • r DS(ON) = 3.500Ω Symbol Packaging JEDEC TO-220AB

Ordering Information

NOTE: When ordering, include the entire part number. G D S SOURCE DRAIN GATEDRAIN (FLANGE) July 1999 File Number 2881.2Data Sheet

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFP2N20 UNITS Maximum Temperature for Soldering 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationo ft h e device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical SpecificationsTC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BV DSS ID = 250µA, VGS = 0 200 - - Gate Threshold Voltage V GS(TH) VGS = VDS , ID = 250µA, (Figure 8) 2 - 4 V Zero Gate Voltage Drain Current I DSS VDS = Rated BVDSS --1 µA VDS = 0.8 x Rated BVDSS , TC = 125oC- - 2 5 µA Gate to Source Leakage Current I GSS VGS =±20V, VDS = 0 - - ±100 nA Drain to Source On Resistance (Note 2) r DS(ON) ID = 2A, VGS = 10V, (Figures 6, 7) - - 3.500 Ω Drain to Source On Voltage (Note 2) V DS(ON) ID = 2A, VGS = 10V - - 7.0 V Turn-On Delay Time t d(ON) ID ≈ 1A, VDD = 100V, RG = 50Ω VGS = 10V, RL = 96.5Ω (Figure 10) -1 5 2 5 n s Rise Time t r -2 0 3 0 n s Turn-Off Delay Time t d(OFF) -2 5 4 0 n s Fall Time t f -1 5 2 5 n s Input Capacitance C ISS VGS = 0V, VDS = 25V f = 1MHz, (Figure 9) - - 200 pF Output Capacitance C OSS - - 60 pF Reverse-Transfer Capacitance C RSS - - 25 pF Thermal Resistance Junction to Case R θJC --5 oC/W Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage (Note 2) V SD ISD = 1A - - 1.4 V Diode Reverse Recovery Time t rr ISD = 2A, dlSD /dt = 50A/µs - 200 - ns NOTES: 2. Pulsed test: width≤ 300µs duty cycle≤ 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. RFP2N20

FIGURE 7. NORMALIZED DRAIN TO SOURCE ON FIGURE 8. NORMALIZED GATE THRESHOLD VOLTAGE vs FIGURE 9. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 10. NORMALIZED SWITCHING WAVEFORMS FOR FIGURE 11. SWITCHING TIME TEST CIRCUIT FIGURE 12. RESISTIVE SWITCHING WAVEFORMS

0.75 BVDSS

0.50 BVDSS

0.25 BVDSS

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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FIGURE 13. GATE CHARGE TEST CIRCUIT FIGURE 14. GATE CHARGE WAVEFORMS