RFP15N15 INTERSIL | Alldatasheet
Document overview
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Technical content
Features
- 15A, 150V
- r DS(ON) = 0.150Ω
- Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol Packaging JEDEC TO-220AB
Ordering Information
RFP15N15 TO-220AB RFP15N15 NOTE: When ordering, use the entire part number. D G S SOURCE DRAIN GATEDRAIN (TAB) October 1998 File Number 1443.2Data Sheet
Absolute Maximum RatingsTC = 25oC, Unless Otherwise Specified RFP15N15 UNITS A A 0.6 W W/oC Maximum Temperature for Soldering 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationo ft h e device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical SpecificationsTC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BV DSS ID = 250µA, VGS = 0V 150 - - V Gate Threshold Voltage V GS(TH) VGS = VDS , ID = 250µA2 - 4 V Zero Gate Voltage Drain Current I DSS VDS = Rated BVDSS , VGS = 0V - - 1 µA VDS = 0.8 x Rated BVDSS ,VGS = 0V, TC = 125oC2 5 µA Gate to Source Leakage Current I GSS VGS =±20V, VDS = 0V - - ±100 nA Drain to Source On Resistance (Note 2) rDS(ON) ID = 15A, VGS = 10V (Figures 6, 7) - - 0.150 Ω Drain to Source On Voltage (Note 2) V DS(ON) ID = 15A, VGS = 10V - - 2.25 V Input Capacitance C ISS VDS = 25V, VGS = 0V, f = 1MHz (Figure 9) - - 1700 pF Output Capacitance C OSS - - 750 pF Reverse-Transfer Capacitance C RSS - - 350 pF Turn-On Delay Time t d(ON) VDD = 75V, ID ≈ 7.5A, RG = 50Ω, VGS = 10V R L = 9.9Ω, (Figures 10, 11, 12) -5 0 7 5 n s Rise Time t r - 150 225 ns Turn-Off Delay Time t d(OFF) - 185 280 ns Fall Time t f - 125 190 ns Thermal Resistance Junction-to-Case - - 1.67 oC/W Source to Drain Diode Specifications PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage (Note 2) V SD ISD = 7.5A - - 1.4 V Reverse Recovery Time t rr ISD = 4A, dISD /dt = 100A/µs - 200 - ns NOTES: 2. Pulse test: width≤ 300µs, duty cycle≤ 2%. 3. Repetitive rating: pulse width is limited by maximum junction temperature. RFP15N15
FIGURE 7. NORMALIZED DRAIN TO SOURCE ON FIGURE 8. NORMALIZED GATE THRESHOLD VOLTAGE vs FIGURE 9. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE NOTE: Refer toIntersil Application Notes AN7254 and AN7260. FIGURE 10. NORMALIZED SWITCHING WAVEFORMS FOR
20 IG(REF)
FIGURE 11. SWITCHING TIME TEST CIRCUIT FIGURE 12. RESISTIVE SWITCHING WAVEFORMS
All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 RFP15N15