RFD14N05L INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • 14A, 50V
  • r DS(ON) = 0.100Ω
  • Temperature Compensating PSPICE™ Model
  • Can be Driven Directly from CMOS, NMOS, and TTL Circuits
  • Peak Current vs Pulse Width Curve
  • UIS Rating Curve
  • 175 oC Operating Temperature
  • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol Packaging JEDEC TO-251AA JEDEC TO-252AA JEDEC TO-220AB

Ordering Information

RFD14N05LSM TO-252AA 14N05L RFP14N05L TO-220AB FP14N05L NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-252AA variant in the tape and reel, i.e., RFD14N05LSM9A. G D S SOURCE DRAIN (FLANGE) GATE DRAIN GATE SOURCE DRAIN (FLANGE) GATE DRAIN (FLANGE) SOURCE DRAIN Data Sheet April 1999

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFD14N05L, RFD14N05LSM, RFP14N05L UNITS Refer to Peak Current Curve A 0.32 W W/oC Maximum Temperature for Soldering 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationo ft h e device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical SpecificationsTC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BV DSS ID = 250µA, VGS = 0V, Figure 13 50 - - V Gate Threshold Voltage V GS(TH) VGS = VDS , ID = 250µA, Figure12 1 - 2 V Zero Gate Voltage Drain Current I DSS VDS = 40V, VGS = 0V - - 1 µA VDS = 40V, VGS = 0V, TC = 150oC- - 5 0 µA Gate to Source Leakage Current I GSS VGS =±10V - - ±100 nA Drain to Source On Resistance (Note 2) r DS(ON) ID = 14A, VGS = 5V, Figures 9, 11 - - 0.100 Ω Turn-On Time t (ON) VDD = 25V, ID = 7A, R L = 3.57Ω , VGS = 5V, R GS = 0.6Ω - - 60 ns Turn-On Delay Time t d(ON) -1 3 - n s Rise Time t r -2 4 - n s Turn-Off Delay Time t d(OFF) -4 2 - n s Fall Time t f -1 6 - n s Turn-Off Time t (OFF) - - 100 ns Total Gate Charge Q g(TOT) VGS = 0V to 10V V DD = 40V, ID = 14A, R L = 2.86Ω Figures 20, 21 - - 40 nC Gate Charge at 5V Q g(5) VGS = 0V to 5V - - 25 nC Threshold Gate Charge Q g(TH) VGS = 0V to 1V - - 1.5 nC Input Capacitance C ISS VDS = 25V, VGS = 0V, f = 1MHz Figure 14 - 670 - pF Output Capacitance C OSS - 185 - pF Reverse Transfer Capacitance C RSS -5 0 - p F Thermal Resistance Junction to Case R θJC - - 3.125 oC/W Thermal Resistance Junction to Ambient R θJA TO-251 and TO-252 - - 100 oC/W R θJA TO-220 - - 80 oC/W Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage (Note 2) V SD ISD = 14A - - 1.5 V Diode Reverse Recovery Time t rr ISD = 14A, dISD /dt = 100A/µs - - 125 ns NOTES: 2. Pulse Test: Pulse Width≤ 300ms, Duty Cycle≤ 2%. 3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current Capability Curve (Figure 5). RFD14N05L, RFD14N05LSM, RFP14N05L

NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING FIGURE 7. SATURATION CHARACTERISTICS FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE FIGURE 10. SWITCHING TIME vs GATE RESISTANCE FIGURE 11. NORMALIZED DRAIN TO SOURCE ON

2.5 PULSE DURATION = 80 µs

FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 15. TRANSCONDUCTANCE vs DRAIN CURRENT

0.75 BVDSS

0.50 BVDSS

0.25 BVDSS

.SUBCKT RFP14N05L 2 1 3 ; rev 9/15/94 CA 12 8 1.464e-9 CB 15 14 1.64e-9 CIN 6 8 6.17e-10 DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 65.35 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 5.68e-9 LSOURCE 3 7 5.35e-9 MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 50 16 RDSMOD 33.1e-3 RGATE 9 20 5.85 RIN 6 8 1e9 RSCL1 5 51 RSCLMOD 1e-6 RSCL2 5 50 1e3 RSOURCE 8 7 RDSMOD 14.3e-3 RVTO 18 19 RVTOMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 0.485 ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/46,7))} .MODEL DBKMOD D (RS = 3.8e-1 TRS1 = 1.89e-3 TRS2 = 1.13e-5) .MODEL DPLCAPMOD D (CJO = 25.7e-11 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 1.935 KP = 18.89 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 7.18e-4 TC2 = 1.53e-6) .MODEL RDSMOD RES (TC1 = 4.45e-3 TC2 = 2.9e-5) .MODEL RSCLMOD RES (TC1 = 2.8e-3 TC2 = 6.0e-6) .MODEL RVTOMOD RES (TC1 = -1.7e-3 TC2 = -2.0e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.55 VOFF= -1.55) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.55 VOFF= -3.55) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.55 VOFF= 2.45) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.45 VOFF= -2.55) .ENDS NOTE: For further discussion of the PSPICE model, consultA New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; authored by William J. Hepp and C. Frank Wheatley. GATE LGATE RGATE EVTO 12 13 S1A S1B S2A S2B CA CB EGS EDS RIN CIN MOS1 MOS2 DBREAK EBREAK DBODY LDRAIN DRAIN RSOURCE LSOURCE SOURCE RBREAK RVTO VBAT IT VTO ESG DPLCAP 7 3 17 18 RDRAIN ESCL RSCL1 RSCL2 51 RFD14N05L, RFD14N05LSM, RFP14N05L

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 RFD14N05L, RFD14N05LSM, RFP14N05L