RFP10P03L

RFD10P03L INTERSIL | Alldatasheet

Document overview

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• PDF pages: 8

Technical content

Features

• 10A, 30V
• r DS(ON) = 0.200Ω
• Temperature Compensating PSPICE® Model
• PSPICE Thermal Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175 oC Operating Temperature Symbol Packaging

Ordering Information

RFD10P03LSM TO-252AA 10P03L RFP10P03L TO-220AB F10P03L NOTE: When ordering, use the entire part number. Add the suffix, 9A, to obtain the TO-252AA variant in tape and reel, i.e.RFD10P03LSM 9A.. G D S JEDEC TO-251AA JEDEC TO-252AA JEDEC TO-220AB SOURCE DRAIN (FLANGE) GATE DRAIN GATE SOURCE DRAIN (FLANGE) GATE DRAIN (FLANGE) SOURCE DRAIN Data Sheet July 1999 File Number 3515.2

Absolute Maximum Ratings TC = 25oC Unless Otherwise Specifie RFD10P03L, RFD10P03LSM, RFP10P03L UNITS Drain Current See Figure 5 A 0.43 W W/oC (0.063in (1.6mm) from case for 10s) 300 oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationo ft h e device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC Electrical SpecificationsTC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BV DSS ID = 250µA, VGS = 0V (Figure 11) -30 - - V Gate Threshold Voltage V GS(TH) VGS = VDS , ID = 250µA (Figure 12) -1 - -2 V Zero Gate Voltage Drain Current I DSS VDS = -30V, T C = 25oC- - - 1 µA VGS = 0V T C = 150oC - - -50 µA Gate to Source Leakage Current I GSS VGS =±10V - - ±100 nA Drain to Source On Resistance (Note 1) rDS(ON) ID = 10A, VGS = -5V (Figures 9, 10) - - 0.200 Ω ID = 10A, VGS = -4.5V (Figures 9, 10) 0.220 Ω Turn-On Time t ON VDD = 15V, ID ≅ 10A, RL = 1.5Ω , R GS = 5Ω, VGS = -5V (Figure 13) - - 100 ns Turn-On Delay Time t d(ON) -1 5-n s Rise Time t r -5 0-n s Turn-Off Delay Time t d(OFF) -3 5-n s Fall Time t f -2 0-n s Turn-Off Time t OFF - - 80 ns Total Gate Charge Q g(TOT) VGS = 0 to -10V VDD = -24V, ID ≅ 10A, R L = 2.4Ω Ig(REF) = -0.25mA (Figure 14) -2 5 3 0 n C Gate Charge at -5V Q g(-5) VGS = 0 to -5V - 13 16 nC Threshold Gate Charge Q g(TH) VGS = 0 to -1V - 1.2 1.5 nC Input Capacitance C ISS VDS = -25V, VGS = 0V, f = 1MHz (Figure 15) - 1035 - pF Output Capacitance C OSS - 340 - pF Reverse Transfer Capacitance C RSS -3 5-p F Thermal Resistance, Junction to Case R θJC - - 2.30 oC/W Thermal Resistance, Junction to Ambient R θJA RFD10P03L, RFD10P03LSM - - 100 oC/W RFP10P03L 80 oC/W Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Forward Voltage V SD ISD = -10A - - -1.5 V Reverse Recovery Time t rr ISD = -10A, dISD /dt = -100A/µs- - 7 5 n s NOTE: 2. Pulse Test: Pulse width≤ 300µs, Duty Cycle≤ 2%. RFD10P03L, RFD10P03LSM, RFP10P03L

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

175 T C–

FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs FIGURE 13. SWITCHING TIME vs GATE RESISTANCE NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 14. NORMALIZED SWITCHING WAVEFORMS FOR FIGURE 15. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 17. UNCLAMPED ENERGY WAVEFORMS

0.75 BVDSS

0.50 BVDSS

0.25 BVDSS

.SUBCKT RFD10P03L 2 1 3 REV 22 Aug 96 CA 12 8 1.29e-9 CB 15 14 9.90e-10 CIN 6 8 1.01e-9 DBODY 5 7 DBODYMOD DBREAK 7 11 DBREAKMOD DPLCAP 10 6 DPLCAPMOD EBREAK 5 11 17 18 -36.49 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 5 10 8 6 1 EVTHRES 6 21 19 8 1 EVTEMP 6 20 18 22 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 3.40e-9 LSOURCE 3 7 3.22e-9 MMED 16 6 8 8 MmedMOD MSTRO 16 6 8 8 MstroMOD MWEAK 16 21 8 8 MweakMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 68.25e-3 RGATE 9 20 2.54 RSCL1 5 51 RSCLMOD 1e-6 RSCL2 5 50 1e3 RSOURCE 8 7 RSourceMOD 25.00e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESCL 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*33),5.0))} .MODEL DBREAKMOD D ( RS=2.62e-1 TRS1=1.74e-3 TRS2=-3.81e-6) .MODEL DPLCAPMOD D (CJO=1.46e-10 IS=1e-30 N=10 M=0.50) .MODEL MSTRONGMOD PMOS (VTO=-1.95 KP=11.60 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MMEDMOD PMOS (VTO=-1.65 KP=1.00 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.54) .MODEL RBREAKMOD RES (TC1=9.17e-4 TC2=-2.74e-7) .MODEL RDRAINMOD RES (TC1=6.35e-3 TC2=1.98e-5) .MODEL RSOURCEMOD RES (TC1=0 TC2=0) .MODEL RSCLMOD RES (TC1=2e-3 TC2=0) .MODEL RVTHRESMOD RES (TC1=1.23e-3 TC2=1.97e-6) .MODEL RVTEMPMOD RES (TC1=-1.18e-3 TC2=1.44e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=4.80 VOFF=1.80) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1.80 VOFF=4.80) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.40 VOFF=-3.40) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.40 VOFF=-0.40) ENDS For further discussion of the PSPICE model consult A New PSPICE Sub-circuit for the Power MOSFet Featuring Global Temperature Options; authored by William J. Hepp and C. Frank Wheatley. - + + - RBREAK RVTEMP VBAT RVTHRES IT 17 18 S1A S1B S2A S2B CA CB EGS EDS MWEAK DBODY RSOURCE SOURCE 7 3 LSOURCE RLSOURCE CIN RDRAIN EVTHRES 1621 MMED MSTRO DRAIN LDRAIN RLDRAIN DBREAK DPLCAP ESLC RSLC1 RSLC2 GATE RGATE EVTEMP ESG LGATE RLGATE EBREAK RFD10P03L, RFD10P03LSM, RFP10P03L

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 PSpice Thermal Model REV 29 Aug 96 RFP10P03L CTHERM1 7 6 5.00e-7 CTHERM2 6 5 5.35e-4 CTHERM3 5 4 5.50e-4 CTHERM4 4 3 1.75e-3 CTHERM5 3 2 1.25e-2 CTHERM6 2 1 0.45 RTHERM1 7 6 1.00e-2 RTHERM2 6 5 2.05e-2 RTHERM3 5 4 5.39e-2 RTHERM4 4 3 5.45e-1 RTHERM5 3 2 1.01 RTHERM6 2 1 0.50 RFD10P03L, RFD10P03LSM CTHERM1 7 6 5.00e-7 CTHERM2 6 5 5.35e-4 CTHERM3 5 4 5.50e-4 CTHERM4 4 3 1.75e-3 CTHERM5 3 2 1.25e-2 CTHERM6 2 1 0.11 RTHERM1 7 6 1.00e-2 RTHERM2 6 5 2.05e-2 RTHERM3 5 4 5.39e-2 RTHERM4 4 3 5.45e-1 RTHERM5 3 2 1.01 RTHERM6 2 1 0.50 RTHERM4 RTHERM6 RTHERM5 RTHERM3 RTHERM2 RTHERM1 CTHERM4 CTHERM6 CTHERM5 CTHERM3 CTHERM2 CTHERM1

7 JUNCTION

RFD10P03L, RFD10P03LSM, RFP10P03L