RFM93W-915S2

RFM93W HOPE | Alldatasheet

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RFM92W/93W V2.0 DATASHEET WIRELESS & SENSING Page 1 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM92W/93W - Low Power Long Range Transceiver Module V2.0 GENERAL DESCRIPTION The RFM92W/93W transceivers feature the LoRaTM long range modem that provides ultra-long range spread spectrum c ommunication a nd high interference immunity whilst minimising current consumption. Using Semtech‟s patented LoRaTM modulation t echnique RFM92W/93W can achieve a sensitivity of over -137 dBm using a low cost crystal and bill of materials. The high sensitivity combined with the integrated +20 dBm power amplifier y ields industry leading link budget making it optimal for any application requiring range or robustness. LoRaTM also provid es significant advantages in both blocking and selectivity over conventional modulation techniques, solving the traditional design compromise between range, interference immunity and energy consumption. These devices also support high performance ( G)FSK modes for systems including WMBus, IEEE802.15.4g. The RFM92W/93W deliver exceptional phase noise, selectivity, receiver linearity and IIP3 for significantly lower current consumption than competing devices.

APPLICATIONS

 Automated Meter Reading  Home and Building Automation  Wireless Alarm and Security Systems  Industrial Monitoring and Control  Long range Irrigation Systems KEY PRODUCT FEATURES  LoRaTM Modem  157 dB maximum link budget  +20 dBm at 100 mW constant RF output vs. V supply  +14 dBm high efficiency PA  Programmable bit rate up to 300 kbps  High sensitivity: down to -137 dBm  Bullet-proof front end: IIP3 = -12.5 dBm  89 dB blocking immunity  Low RX current of 10 mA, 100 nA register retention  Fully integrated synthesizer with a resolution of 61 Hz  FSK, GFSK, MSK, GMSK, LoRaTM and OOK modulation  Built-in bit synchronizer for clock recovery  Preamble detection  127 dB Dynamic Range RSSI  Automatic RF Sense and CAD with ultra-fast AFC  Packet engine up to 256 bytes with CRC  Built-in temperature sensor and low battery indicator RFM92W/93W

RFM92W/93W V2.0 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com WIRELESS & SENSING DATASHEET Table of contents Section Page

RFM92W/93W V2.0 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com G DATASHEET Table of contents Section Page

RFM92W/93W V2.0 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Table of contents Section Page

RFM92W/93W V2.0 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Table of contents Section Page

existing systems or standards such as wireless MBUS and IEEE 802.15.4g.

1. The RFM93W offers the same bandwidth options with spreading factors from 6 to 9.

Figure 1. RFM92W/93W Block Diagram

The features of the two product variants RFM92W and RFM93W are detailed in the following table. The following diagram shows the pin arrangement of the QFN package, top view. Figure 2. Pin Diagram

RFM92W/93W V2.0 Page 12 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com 1.4. Pin Description Table 2 Pin Description Number Name Type Description

1 GND -

2 MISO I

3 MOSI O

4 SCK

I SPI Clock input

5 NSS I

6 RESET I/O

7 DIO5 I/O

Digital I/O, software configured

8 GND -

9 ANT -

RF signal output/input.

10 GND -

11 DIO3 I/O

Digital I/O, software configured

12 DIO4 I/O

Digital I/O, software configured 3.3V - Supply voltage

14 DIO0 I/O

Digital I/O, software configured

15 DIO1 I/O

Digital I/O, software configured

16 DIO2 I/O

Digital I/O, software configured

Figure 3. Package Marking

RFM92W/93W V2.0 Page 14 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com 2. Electrical Characteristics 2.1. ESD Notice The RFM92W/93W is a high performance radio frequency device. It satisfies:  Class II of the JEDEC standard JESD22-A114-B (Human Body Model) on all pins.  Class III of the JEDEC standard JESD22-C101C (Charged Device Model) on all pins It should thus be handled with all the necessary ESD precautions to avoid any permanent damage. 2.2. Absolute Maximum Ratings Stresses above the values listed below may cause permanent device failure. Exposure to absolute maximum ratings for extended periods may affect device reliability. Table 3 Absolute Maximum Ratings Symbol Description Min Max Unit VDDmr Supply Voltage -0.5 3.9 V Tmr Temperature -55 +115 ° C Tj Junction temperature - +125 ° C Pmr RF Input Level - +10 dBm Note Specific ratings apply to +20 dBm operation (see Section 5.4.3). 2.3. Operating Range Table 4 Operating Range Symbol Description Min Max Unit VDDop Supply voltage 1.8 3.7 V Top Operational temperature range -40 +85 °C Clop Load capacitance on digital ports - 25 pF ML RF Input Level - +10 dBm Note A specific supply voltage range applies to +20 dBm operation (see Section 5.4.3). 2.4. Thermal Properties Table 5 Operating Range Symbol

Description

THETA_JA Package ja (Junction to ambient) - 22.185 - ° C/W THETA_JC Package jc (Junction to case ground paddle) - 0.757 - ° C/W

RFM92W/93W V2.0 Page 15 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com 2.5. Chip Specification The tables below give the electrical specifications of the transceiver under the following conditions: Supply voltage VBAT1 = VBAT2 = VDD = 3.3 V, temperature = 25 °C, FXOSC = 32 MHz, FRF = 915 MHz, Pout = +13 dBm, 2 level FSK modulation without pre-filtering, FDA = 5 kHz, Bit Rate = 4.8 kbps and terminated in a matched 50 Ohm impedance, unless otherwise specified. Shared Rx and Tx path matching. Note Unless otherwise specified, the performance in the 868 MHz band is identical or better. 2.5.1. Power Consumption Table 6 Power Consumption Specification Symbol Description Conditions Min Typ Max Unit IDDSL Supply current in Sleep mode - 0.1 1 uA IDDIDLE Supply current in Idle mode RC oscillator enabled - 1.5 - uA IDDST Supply current in Standby mode Crystal oscillator enabled - 1.4 1.6 mA IDDFS Supply current in Synthesizer mode FSRx 4.5 mA IDDR Supply current in Receive mode LnaBoost Off LnaBoost On 10.5 11.2 mA IDDT Supply current in Transmit mode with impedance matching RFOP = +20 dBm on PA_BOOST RFOP = +17 dBm on PA_BOOST RFOP = +13 dBm on RFO pin RFOP = + 7 dBm on RFO pin 125 mA mA mA mA 2.5.2. Frequency Synthesis Table 7 Frequency Synthesizer Specification Symbol Description Conditions Min Typ Max Unit FRF Synthesizer frequency range Programmable 860 - 1020 MHz FXOSC Crystal oscillator frequency MHz TS_OSC Crystal oscillator wake-up time 250 us TS_FS Frequency synthesizer wake-up time to PllLock signal From Standby mode us TS_HOP Frequency synthesizer hop time at most 10 kHz away from the tar- get frequency 200 kHz step

1 MHz step

5 MHz step

7 MHz step

12 MHz step

20 MHz step

25 MHz step

FSTEP Frequency synthesizer step FSTEP = FXOSC/219 - 61.0 - Hz FRC RC Oscillator frequency After calibration - 62.5 - kHz

RFM92W/93W V2.0 Page 16 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com BRF Bit rate, FSK Programmable values (1) 1.2 - 300 kbps BRO Bit rate, OOK Programmable 1.2 - 32.768 kbps BRA Bit Rate Accuracy ABS(wanted BR - available BR) - - 250 ppm FDA Frequency deviation, FSK (1) Programmable FDA + BRF/2 =< 250 kHz 0.6 - 200 kHz Note For Maximum Bit Rate the maximum modulation index is 0.5. 2.5.3. FSK/OOK Mode Receiver All receiver tests are performed with RxBw = 10 kHz (Single Side Bandwidth) as programmed in RegRxBw, receiving a PN15 sequence. Sensitivities are reported for a 0.1% BER (with Bit Synchronizer enabled), unless otherwise specified. Blocking tests are performed with an unmodulated interferer. The wanted signal power for the Blocking Immunity, ACR, IIP2, IIP3 and AMR tests is set 3 dB above the receiver sensitivity level. Table 8 Receiver Specification Symbol RFS_F Direct tie of RFI and RFO pins, shared Rx, Tx paths FSK sensitiv- ity, highest LNA gain. FDA = 5 kHz, BR = 1.2 kbps FDA = 5 kHz, BR = 4.8 kbps FDA = 40 kHz, BR = 38.4 kbps* FDA = 20 kHz, BR = 38.4 kbps FDA = 62.5 kHz, BR = 250 kbps* -119 -115 -105 -106 -92 dBm dBm dBm dBm dBm Split RF paths, LnaBoost is turned on, the RF switch insertion loss is not accounted for. FDA = 5 kHz, BR = 1.2 kbps FDA = 5 kHz, BR = 4.8 kbps FDA = 40 kHz, BR = 38.4 kbps* FDA = 20 kHz, BR = 38.4 kbps FDA = 62.5 kHz, BR = 250 kbps* -123 -119 -110 -110 -97 dBm dBm dBm dBm dBm RFS_O OOK sensitivity, highest LNA gain shared Rx, Tx paths BR = 4.8 kbps BR = 32 kbps -117 -108 dBm dBm CCR Co-Channel Rejection - -9 - dB ACR Adjacent Channel Rejection FDA = 2 kHz, BR = 1.2 kbps, RxBw = 5.2 kHz Offset = +/- 25 kHz dB FDA = 5 kHz, BR=4.8kbps Offset = +/- 25 kHz Offset = +/- 50 kHz dB dB BI Blocking Immunity Offset = + /- 1 MHz Offset = + /- 2 MHz Offset = +/- 10 MHz dB dB dB AMR AM Rejection, AM modulated interferer with 100% modulation depth, fm = 1 kHz, square Offset = + /- 1 MHz Offset = + /- 2 MHz Offset = +/- 10 MHz dB dB dB

RFM92W/93W V2.0 Page 17 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Symbol RF_OP RF output power in 50 ohms on RFO pin (High efficiency PA). Programmable with steps Max Min +11 +14 dBm dBm ΔRF_ OP_V RF output power stability on RFO pin versus voltage supply VDD = 2.5 V to 3.3 V VDD = 1.8 V to 3.7 V dB dB RF_OPH RF output power in 50 ohms, on PA_BOOST pin (Regulated PA) Programmable with 1dB steps Max Min +17 dBm dBm RF_OPH_ MAX Max RF output power, on PA_BOOST pin High power mode +20 dBm ΔRF_ OPH_V RF output power stability on PA_- BOOST pin versus voltage supply. VDD = 2.4 V to 3.7 V +/-1 dB ΔRF_T RF output power stability versus From T = -40 °C to +85 °C +/-1 dB PHN Transmitter Phase Noise Low Consumption PLL, 915 MHz 50 kHz offset 400 kHz offset

1 MHz offset

-102 -114 -120 dBc/ Hz Low Phase Noise PLL, 915 MHz 50 kHz offset 400 kHz offset -106 -117 -122 dBc/ Hz IIP2 2nd Order input intercept point unwanted tones are 20 MHz above the LO Highest LNA gain +57 dBm IIP3 3rd Order input intercept point unwanted tones are 1 MHz and

1.995 MHz above the LO

LNA gain G2, 4dB sensitivity reduction. -12.5 -8.5 dBm dBm BW_SSB Single Side channel filter BW Programmable 2.7 - 250 kHz IMR Image Rejection Wanted signal power sensitivity +3 dB BER = 0.1% dB IMA Image Attenuation - 57 - dB DR_RSSI RSSI Dynamic Range AGC enabled Min Max -127 dBm dBm * RxBw = 83 kHz (Single Side Bandwidth) RxBw = 50 kHz (Single Side Bandwidth) * RxBw = 250 kHz (Single Side Bandwidth) 2.5.4. FSK/OOK Mode Transmitter Table 9 Transmitter Specification temperature on both RF pins.

 Spreading Factor (SF) = 12.  Error Correction Code (EC) = 4/6.  Output power = 13 dBm in transmission.  Payload length = 10 bytes. Table 10. Electrical specifications: LoraTM mode

RFM92W/93W V2.0 Page 20 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com 2.5.6. Digital Specification Conditions: Temp = 25° C, VDD = 3.3 V, FXOSC = 32 MHz, unless otherwise specified. Table 11 Digital Specification Symbol Description Conditions Min Typ Max Unit VIH Digital input level high 0.8 - - VDD VIL Digital input level low - - 0.2 VDD VOH Digital output level high Imax = 1 mA 0.9 - - VDD VOL Digital output level low Imax = -1 mA - - 0.1 VDD FSCK SCK frequency - - 10 MHz tch SCK high time 50 - - ns tcl SCK low time 50 - - ns trise SCK rise time - 5 - ns tfall SCK fall time - 5 - ns tsetup MOSI setup time From MOSI change to SCK rising edge 30 - - ns thold MOSI hold time From SCK rising edge to MOSI change 20 - - ns tnsetup NSS setup time From NSS falling edge to SCK rising edge 30 - - ns tnhold NSS hold time From SCK falling edge to NSS rising edge, normal mode 100 - - ns tnhigh NSS high time between SPI accesses 20 - - ns T_DATA DATA hold and setup time 250 - - ns

This section gives a high-level overview of the functionality of the RFM92W/93W low-power, highly integrated transceiver. The following figure shows a simplified block diagram of the RFM92W/93W. Figure 4. Simplified RFM92W Block Schematic Diagram of the top level sequencer (TLS). +20 dBm via a dedicated matching network. calibration of the RFM92W/93W between intermediate modes of operation in the fastest time possible.

RFM92W/93W V2.0 Page 22 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com The RFM92W/93W are equipped with both standard FSK and long range spread spectrum (LoRaTM) modems. Depending upon the mode selected either conventional OOK or FSK modulation may be employed or the LoRaTM spread spectrum modem. 3.1. LoRaTM Modem The LoRaTM modem uses a proprietary spread spectrum modulation technique. This modulation, in contrast to legacy modulation techniques, permits an increase in link budget and increased immunity to in-band interference. At the same time the frequency tolerance requirement of the crystal reference oscillator is relaxed - allowing a performance increase for a reduction in system cost. For a fuller descrip tion of the design trade-offs and operation of the RFM92W/93W please consult Section 4.1 of the datasheet. 3.2. FSK/OOK Modem In FSK/OOK mode the RFM92W/93W supports standard modulation techniques including OOK, FSK, GFSK, MSK and GMSK. The RFM92W/93W is especially suited to narrow band communication thanks the low-IF architecture employed and the built-in AFC functionality. For full information on the FSK/OOK modem please consult Section 4.2 of this document.

RFM92W/93W V2.0 Page 23 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com 4. RFM92W/93W Digital Electronics 4.1. The LoRaTM Modem The LoRaTM modem uses spread spectrum modulation and forward error correction techniques to increase the range and robustness of radio communication links compared to traditional FSK or OOK based modulation. Examples of the performance improvement possible for several settings are summarised in the table below. The spreading factor and error correction rate are design variables that allow the designer to optimise the trade-off between occupied bandwidth, data rate, link budget improvement and immunity to interference. In the table below a coding rate of 4/5 is used. Table 12 Example LoRaTM Modem Performances Bandwidth (kHz) Spreading Factor Nominal Rb (bps) Sensitivity (dBm) 125 6 9380 -122 125 12 293 -137 250 6 18750 -119 250 12 586 -134 500 6 3750 -116 500 12 1172 -131 Typically such performance gains require high stability frequency references, with LoRaTM this is not the case. Low crystal tolerances are easily accommodated reducing the overall BoM cost for a given increase in link budget. For European operation the range of crystal tolerances acceptable for each sub-band (of the ERC 70-03) is given in the specifications table. For US based operation a frequency hopping mode is available that automates both the LoRaTM spread spectrum and frequency hopping spread spectrum processes. Another important facet of the LoRaTM modem is its increased immunity to interference. The LoRaTM modem is capable of co-channel GMSK rejection of up to 25 dB. This immunity to interference permits the simple coexistence of LoRaTM modulated systems either in bands of heavy spectral usage or in hybrid communication networks that use LoRaTM to extend range when legacy modulation schemes fail.

enhanced immunity to interference. Figure 5. LoRaTM Modem Connectivity consult the register description of Section 6. occupancy and nominal data rate. These parameters are spreading factor, modulation bandwidth and error coding rate.

RFM92W/93W V2.0 Page 25 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com 4.1.1.2. Spreading Factor The spread spectrum LoRaTM modulation is performed by representing each bit of payload information by multiple chips of information. The rate at which the spread information is sent is referred to as the symbol rate (Rs), the ratio between the nominal symbol rate and chip rate is the spreading factor and represents the number of symbols sent per bit of information. The range of values accessible with the LoRaTM modem are shown in the following table. Table 13 Range of Spreading Factors SpreadingFactor (RegModemConfig2) Spreading Factor (Chips / symbol) LoRa Demodulator SNR 6 64 -5 dB 7 128 -7.5 dB 8 256 -10 dB 9 512 -12.5 dB 10 1024 -15 dB 11 2048 -17.5 dB 12 4096 -20 dB Note that the spreading factor, SpreadingFactor, must be known in advance on both transmit and receive sides of the link as different spreading factors are orthogonal to each other. Note also the resulting signal to noise ratio (SNR) required at the receiver input. It is the capability to receive signals with negative SNR that increases the sensitivity, so link budget and range, of the LoRa receiver. Spreading Factor 6 SF = 6 Is a special use case for the highest data rate transmission possible with the LoRa modem. To this end several settings must be activated in the RFM92W/93W registers when it is in use:  Set SpreadingFactor = 6 in RegModemConfig2  The header must be set to Implicit mode.  Write bits 2-0 of register address 0x31 to value "0b101".  Write register address 0x37 to value 0x0C. 4.1.1.3. Coding Rate To further improve the robustness of the link the LoRaTM modem employs cyclic error coding to perform forward error detection and correction. Such error coding incurs a transmission overhead - the resultant additional data overhead per transmission is shown in the table below. Table 14 Cyclic Coding Overhead CodingRate (RegModemConfig1) Cyclic Coding Rate Overhead Ratio 1 4/5 1.25 2 4/6 1.5 3 4/7 1.75 4 4/8 2

RFM92W/93W V2.0 Page 26 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Rs W Forward error correction is particularly efficient in improving the reliability of the link in the presence of interference. So that the coding rate (and so robustness to interference) can be changed in response to channel conditions - the coding rate can optionally be included in the packet header for use by the receiver. Please consult Section 4.1.1.6 for more information on the LoRaTM packet and header. 4.1.1.4. Signal Bandwidth An increase in signal bandwidth permits the use of a higher effective data rate, thus reducing transmission time at the expense of reduced sensitivity improvement. There are of course regulatory constraints in most countries on the permissible occupied bandwidth. Contrary to the FSK modem, which is described in terms of the single sideband bandwidth, the LoRaTM modem bandwidth refers to the double sideband bandwidth (or total channel bandwidth). The range of bandwidths relevant to most regulatory situations is given in the LoRaTM modem specifications table (see Section 2.5.5). Bandwidth (kHz) Spreading Factor Coding rate Nominal Rb (bps) Sensitivity (dBm) 125 12 4/5 293 -136 250 12 4/5 586 -133 500 12 4/5 1172 -130 4.1.1.5. LoRaTM Transmission Parameter Relationship With a knowledge of the key parameters that can be controlled by the user we define the LoRaTM symbol rate as: BW 2SF where BW is the programmed bandwidth and SF is the spreading factor. The transmitted signal is a constant envelope signal. Equivalently, one chip is sent per second per Hz of bandwidth.

format is shown in the following figure. Figure 6. LoRaTM Packet Structure of near arbitrarily long preamble sequences. maximum preamble length should be programmed on the receiver side. ImplictHeaderModeOn bit found within the RegModemConfig1 register.  The payload length in bytes.  The presence of an optional 16-bits CRC for the payload.

RFM92W/93W V2.0 Page 28 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com The header is transmitted with maximum error correction code (4/8). It also has its own CRC to allow the receiver to discard invalid headers. Implicit Header Mode In certain scenarios, where the payload, coding rate and CRC presence are fixed or known in advance, it may be advantageous to reduce transmission time by invoking implicit header mode. In this mode the header is removed from the packet. In this case the payload length, error coding rate and presence of the payload CRC must be manually configured on both sides of the radio link. Note that with SF = 6 selected implicit header mode is the only mode of operation possible. Low Data Rate Optimization Given the potentially long duration of the packet at high spreading factors the option is given to improve the robustness of the transmission to variations in frequency over the duration of the packet transmission and reception. The bit LowDataRateOptimize increases the robustness of the LoRa link at these low effective data rates, its use is mandated with spreading factors of 11 and 12 at 125 kHz bandwidth. Payload The packet payload is a variable-length field that contains the actual data coded at the error rate either as specified in the header in explicit mode or in the register settings in implicit mode. An optional CRC may be appended. F or more information on the payload and how it is loaded from the data buffer FIFO please see Section 4.1.2.3. 4.1.1.7. Time on air For a given combination of spreading factor (SF), coding rate (CR) and signal bandwidth (BW) the total on-the-air transmission time of a LoRaTM packet can be calculated as follows. From the definition of the symbol rate it is convenient to define the symbol period: Ts = --1--- Rs The LoRa packet duration is the sum of the duration of the preamble and the transmitted packet. The preamble length is calculated as follows: Tpr ea mbl e =  npr ea m b l e + 4.25Tsy m where npreamble is the programmed preamble length, taken from the registers RegPreambleMsb and RegPreambleLsb. The payload duration depends upon the header mode that is enabled. The following formula gives the number of payload symbols. Where PL is the number of bytes of payload, SF is the spreading factor, IH = 1 when implicit header mode is enabled and IH = 0 when explicit header mode is used. DE set to 1 indicates the use of the low data rate optimization, 0 when disabled. Tpayl o ad = npayl o ad + Tsy m

RFM92W/93W V2.0 Page 29 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Addition of the preamble and payload durations gives the total packet time on air. Tpack e t = Tpr ea m b le + Tpa yl oa d 4.1.1.8. Frequency Hopping with LoRaTM Frequency hopping spread spectrum (FHSS) is typically employed when the duration of a single packet could exceed regulatory requirements relating to the maximum permissible channel dwell time. This is most notably the case in US operation where the 902 to 928 MHz ISM band which makes provision for frequency hopping operation. To ease the implementation of FHSS systems the frequency hopping mode of the LoRaTM modem can be enabled by setting FreqHoppingPeriod to a non-zero value in register RegHopPeriod. Principle of Operation The principle behind the FHSS scheme is that a portion of each LoRaTM packet is transmitted on each hopping channel from a look up table of frequencies managed by the host microcontroller. After a predetermined hopping period the transmitter and receiver change to the next channel in a predefined list of hopping frequencies to continue transmission and reception of the next portion of the packet. The time which the transmission will dwell in any given channel is determined by FreqHoppingPeriod which is an integer multiple of symbol periods: Hoppin gPerio d s  = Ts  F reqHoppingP e riod The frequency hopping transmission and reception process starts at channel 0. The preamble and header are transmitted first on channel 0. At the beginning of each transmission the channel counter FhssPresentChannel (located in the register RegHopChannel) is incremented and the interrupt signal FhssChangeChannel is generated. The new frequency must then be programmed within the hopping period to ensure it is taken into account for the next hop, the interrupt ChangeChannelFhss is then to be cleared by writing a logical „1‟. FHSS Reception always starts on channel 0. The receiver waits for a valid preamble detection before starting the frequency hopping process as described above. Note that in the eventuality of header CRC corruption, the receiver will automatically request channel 0 and recommence the valid preamble detection process.

Figure 7. Interrupts generated in the case of successful frequency hopping communication.

below. Full listings of the register addresses used for SPI access are given in Section 6.3. Configuration registers are accessed through the SPI interface. Registers are readable in all device mode including Sleep. Status registers provide status information during receiver operation. content upon each new transition to receive mode. Figure 8. LoRaTM data buffer

RFM92W/93W V2.0 Page 32 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Principle of Operation Thanks to its dual port configuration, it is possible to simultaneously store both transmit and receive information in the FIFO data buffer. The register RegFifoTxBaseAddr specifies the point in memory where the transmit information is stored. Similarly, for receiver operation, the register RegFifoRxBaseAddr indicates the point in the data buffer where information will be written to in event of a receive operation. By default, the device is configured at power up so that half of the available memory is dedicated to Rx (RegFifoRxBaseAddr initialized at address 0x00) and the other half is dedicated for Tx (RegFifoTxBaseAddr initialized at address 0x80). However, due to the contiguous nature of the FIFO data buffer, the base addresses for Tx and Rx are fully configurable across the 256 byte memory area. Each pointer can be set independently anywh ere within the FIFO. To exploit the maximum FIFO data buffer size in transmit or receive mode, the whole FIFO data buffer can be used in each mode by setting the base addresses RegFifoTxBaseAddr and RegFifoRxBaseAddr at the bottom of the memory (0x00). The FIFO data buffer is cleared when the device is put in SLEEP mode, consequently no access to the FIFO data buffer is possible in sleep mode. However, the data in the FIFO data buffer are retained when switching across the other LoRaTM modes of operation, so that a received packet can be retransmitted with minimum data handling on the controller side. The FIFO data buffer is not self-clearing (unless if the device is put in sleep mode) and the data will only be “erased” when a new set of data is written into the occupied memory location. TheFIFO data buffer location to be read from, or written to, via the SPI interface is defined by the address pointer RegFifoAddrPtr. Before any read or write operation it is hence necessary to initialize this pointer to the corresponding base value. Upon reading or writing to the FIFO data buffer (RegFifo) the address pointer will then increment automatically. The register RegRxNbBytes defines the size of the memory location to be written in the event of a successful receive operation. The register RegPayloadLength indicates the size of the memory location to be transmitted. In implicit header mode, the register RegRxNbBytes is not used as the number of payload bytes is known. Otherwise, in explicit header mode, the initial size of the receive buffer is set to the packet length in the received heade r. The register RegFifoRxCurrentAddr indicates the location of the last packet received in the FIFO so that the last packet received can be easily read by pointing the register RegFifoAddrPtr to this register. It is important to notice that all the received data will be written to the FIFO data buffer even if the CRC is invalid, permitting user defined post processing of corrupted data. It is also important to note that when receiving, if the packet size exceeds the buffer memory allocated for the Rx, it will overwrite the transmit portion of the data buffer.

RFM92W/93W V2.0 Page 33 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com 4.1.3. Operation of the LoRaTM Modem 4.1.3.1. Operating Mode Control The operating modes of the LoRaTM modem are accessed by enabling LoRaTM mode (setting the LongRangeMode bit of RegOpMode). Depending upon the operating mode selected the range of functionality and register access is given by the following table: Table 15 LoRaTM Operating Mode Functionality Operating Mode Description SLEEP Low-power mode. In this mode only SPI and configuration registers are accessible. Lora FIFO is not accessible. Note that this is the only mode permissible to switch between FSK/OOK mode and LoRa mode. STAND-BY Both crystal oscillator and LoRa baseband blocks are turned on. RF front-end and PLLs are disabled FSTX This is a frequency synthesis mode for transmission. The PLL selected for transmission is locked and active at the transmit frequency. The RF front-end is off. FSRX This is a frequency synthesis mode for reception. The PLL selected for reception is locked and active at the receive frequency. The RF front-end is off. TX When activated the RFM92W/93W powers all remaining blocks required for transmit, ramps the PA, transmits the packet and returns to Stand-by mode. RXCONTINUOUS When activated the RFM92W/93W powers all remaining blocks required for reception, processing all received data until a new user request is made to change operating mode. RXSINGLE When activated the RFM92W/93W powers all remaining blocks required for reception, remains in this state until a valid packet has been received and then returns to Stand-by mode. CAD When in CAD mode, the device will check a given channel to detect LoRa preamble signal It is possible to access any mode from any other mode by changing the value in the RegOpMode register.

RFM92W/93W V2.0 Page 34 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com F = XO S C 4.1.4. Frequency Settings Recalling that the frequency step is given by: F 219 In order to set LO frequency values following registers are available. Frf is a 24-bit register which defines carrier frequency. The carrier frequency relates to the register contents by following formula: FRF = FSTE P  Frf (23,0)

sequences of operation, are detailed below. transmitted. Figure 9 shows a typical LoRaTM transmit sequence. Figure 9. LoRaTM modulation transmission sequence.  Static configuration registers can only be accessed in Sleep mode, Stand-by mode or FSTX mode.  The LoRaTM FIFO can only be filled in Stand-by mode.  Data transmission is initiated by sending TX mode request.  Upon completion the TxDone interrupt is issued and the radio returns to Stand-by mode.

1 Set FifoAddrPtr to FifoTxBaseAddrs.

2 Write PayloadLength bytes to the FIFO (RegFifo)

Figure 10 shows typical LoRaTM receive sequences for both single and continuous receiver modes of operation. Figure 10. LoRaTM receive sequence.

RFM92W/93W V2.0 Page 37 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com The LoRaTM modem can work in two distinct reception modes: 1. Single receive mode 2. Continuous receive mode Single Reception Operating Mode In this mode, the modem searches for a preamble during a given time window. If a preamble hasn‟t been found at the end of the time window, the chip generates the RxTimeout interrupt and goes back to stand-by mode. The length of the window (in symbols) is defined by the RegSymbTimeout register and should be in the range of 4 (minimum time for the modem to acquire lock on a preamble) up to 1023 symbols. (The default value being 5). If no preamble is detected during this window the RxTimeout interrupt is generated and the radio goes back to stand-by mode. At the end of the payload, the RxDone interrupt is generated together with the interrupt PayloadCrcError if the payload CRC is not valid. However, even when the CRC is not valid, the data are written in the FIFO data buffer for post processing. Following the RxDone interrupt the radio goes to stand-by mode. The modem will also automatically return in stand-by mode when the interrupts RxDone or RxTimeout are generated. Therefore, this mode should only be used when the time window of arrival of the packet is known . In other cases, the RX continuous mode should be used. In Rx single mode low-power is achieved by turning off PLL and RF blocks as soon as a packet has been received. The flow is as follows: 1 Set FifoAddrPtr to FifoRxBaseAddr. 2 Static configuration register device can be written in either Sleep mode, Stand-by mode or FSRX mode. 3 A single packet receive operation is initiated by selecting the operating mode RXSINGLE. 4 The receiver will then await the reception of a valid preamble. Once received, the gain of the receive chain is set. Following the ensuing reception of a valid header, indicated by the ValidHeader interrupt in explicit mode. The packet reception process commences. Once the reception process is complete the RxDone interrupt is set. The radio then returns automatically to Stand-by mode to reduce power consumption. 5 The receiver status register PayloadCrcError should be checked for packet payload integrity. 6 If a valid packet payload has been received then the FIFO should be read (See Payload Data Extraction below). Should a subsequent single packet reception need to be triggered, then the RXSINGLE operating mode must be re-selected to launch the receive process again - taking care to reset the SPI pointer (FifoAddrPtr) to the base location in memory (FifoRxBaseAddr). Continuous Reception Operating Mode In continuous receive mode the modem scans the channel continuously for a preamble. Each time a preamble is detected the modem detects and tracks it until the packet is received and then carries on waiting for the next preamble. If the preamble length exceeds the anticipated value set by the registers RegPreambleMsb and RegPreambleLsb (measured in symbol periods) the preamble will be dropped and the search for a preamble restarted. However, this scenario will not be flagged by an interrupt. In continuous RX mode, opposite to the single RX mode, when a timeout interrupt is generated, the device will not go in standby mode. In this case, the user must simply clear the interrupt while the device carry on waiting for a valid preamble. It is also important to note that the demodulated bytes are written in the data buffer memory in the order received. Meaning, the first byte of a new packet is written just after the last byte of the preceding packet. The RX modem address pointer is never reset as long as this mode is enabled. It is therefore necessary for the companion microcontroller controller to handle the address pointer to make sure the FIFO data buffer is never full.

RFM92W/93W V2.0 Page 38 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com In continuous mode the received packet processing sequence is given below. 1 Whilst in Sleep or Stand-by mode select RXCONT mode. 2 Upon reception of a valid header CRC the RxDone interrupt is set. The radio remains in RXCONT mode waiting for the next RX LoRaTM packet. 3 The PayloadCrcError flag should be checked for packet integrity. 4 If packet has been correctly received the FIFO data buffer can be read (see below). 5 The reception process (steps 2 - 4) can be repeated or receiver operating mode exited as desired. In continuous mode status information are available only for the last packet received, i.e. the corresponding registers should be read before the next RxDone arrives. Payload Data Extraction from FIFO In order to retrieve received data from FIFO the user must ensure that ValidHeader, PayloadCrcError, RxDone and RxTimeout interrupts in the status register RegIrqFlags are not asserted to ensure that packet reception has terminated successfully (i.e. no flags should be set). In case of errors the steps below should be skipped and the packet discarded. In order to retrieve valid received data from the FIFO the user must:  RegRxNbBytes Indicates the number of bytes that have been received thus far.  RegFifoAddrPtr is a dynamic pointer that indicates precisely where the Lora modem received data has been written up to.  Set RegFifoAddrPtr to RegFifoRxCurrentAddr. This sets the FIFO pointer to the location of the last packet received in the FIFO. The payload can then be extracted by reading the register RegFifo, RegRxNbBytes times. Alternatively, it is possible to manually point to the location of the last packet received, from the start of the current packet, by setting RegFifoAddrPtr to RegFifoRxByteAddr minus RegRxNbBytes. The payload bytes can then be read from the FIFO by reading the RegFifo address RegRxNbBytes times. Packet Filtering based on Preamble Start The LoRaTM modem does not automatically filter received packets based upon an address. However, the RFM92W/93W permits software filtering of the received packets based on the contents of the first few bytes of payload. A brief example is given below for a 4 byte address, however, the address length can be selected by the designer. The objective of the packet filtering process is to determine the presence, or otherwise, of a valid packet designed for the receiver. If the packet is not for the receiver then the radio returns to sleep mode in order to improve battery life.

RFM92W/93W V2.0 Page 39 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com The software packet filtering process follows the steps below:  Each time the RxDone interrupt is received, latch the RegFifoRxByteAddr[7:0] register content in a variable, this variable will be called start_address. The RegFifoRxByteAddr[7:0] register of the RFM92 gives in real time the address of the last byte written in the data buffer + 1 (or the address at which the next byte will be written by the receive LoRaTM modem). So by doing this, we make sure that the variable start_address always contains the start address of the next packet.  Upon reception of the interrupt ValidHeader, start polling the RegFifoRxByteAddr[7:0] register until it begins to increment. The speed at which this register will increment depends on the spreading factor, the error correction code and the modulation bandwidth. (Note that this interrupt is still generated in implicit mode).  As soon as RegFifoRxByteAddr[7:0] >= start address + 4, the first 4 bytes (address) are stored in the FIFO data buffer. These can be read and tested to see if the packet is destined for the radio and either remaining in Rx mode to receive the packet or returning to sleep mode if not. Receiver Timeout Operation In either single or continuous LoRaTM reception modes, a receiver timeout functionality is available that permits the receiver to listen for a predetermined period of time before generating an interrupt signal to indicate that no valid packets have been received. The timer is absolute and commences as soon as the radio is placed in either single or continuous receive mode. The interrupt itself, RxTimeout, can be found in the interrupt register RegIrqFlags. In Rx Single mode, the device will return to Standby mode as soon as the interrupt occurs and the interrupt needs to be cleared before returning to Rx Single mode. In Rx Continuous mode, the interrupt will simply be raised but the device will stay in Rx Continuous mode. It is therefore the responsibility on the companion microcontroller to clear the interrupt while still in Rx Continuous mode. The programmed timeout value is expressed as a multiple of the symbol period and is given by: TimeOu t = LoraRxTimeou t  Ts

Figure 11. LoRaTM CAD flow

that phase is approximately 10 mA.  The radio receiver and the PLL turn off and the modem digital processing starts. CadDetected is generated simultaneously.  The chip goes back to stand-by mode. radio is in a reduced consumption state. Figure 12. Channel activity detection (CAD) time as a function of spreading factor.

Figure 13. Consumption Profile of the LoRa CAD Process processing phase where the consumption varies with the LoRa bandwidth as shown in the table below. and depends upon the configuration of registers RegDioMapping1 and RegDioMapping2.

00 ModeReady CadDetected CadDone FhssChangeChannel RxTimeout RxDone

01 ClkOut PllLock ValidHeader FhssChangeChannel FhssChangeChannel TxDone

10 ClkOut PllLock PayloadCrcError FhssChangeChannel CadDetected CadDone

RFM92W/93W V2.0 Page 43 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com 4.2. FSK/OOK Modem 4.2.1. Bit Rate Setting The bit rate setting is referenced to the crystal oscillator and provides a precise means of setting the bit rate (or equivalently chip) rate of the radio. In continuous transmit mode (Section 3.2.2) the data stream to be transmitted can be input directly to the modulator via pin 9 (DIO2/DATA) asynchronously, unless Gaussian filtering is used, in which case the DCLK signal In Packet mode or in Continuous mode with Gaussian filtering enabled, the Bit Rate (BR) is controlled by bits BitRate in RegBitrateMsb and RegBitrateLsb Bi tR ate(15,0) + -----i--t--r--a- - --t--e---F- - --r--a- - --c- Note: BitrateFrac bits have no effect (i.e may be considered equal to 0) in OOK modulation mode. The quantity BitrateFrac is hence designed to allow very high precision (max. 250 ppm programing resolution) for any bitrate in the programmable range. Table 18 below shows a range of standard bitrates and the accuracy to within which they may be attained. Table 18 Bit Rate Examples Type BitRate (15:8) BitRate (7:0) (G)FSK (G)MSK OOK Actual BR (b/s) Classical modem baud rates (multiples of 1.2 kbps) 0x68 0x2B 1.2 kbps 1.2 kbps 1200.015 0x34 0x15 2.4 kbps 2.4 kbps 2400.060 0x1A 0x0B 4.8 kbps 4.8 kbps 4799.760 0x0D 0x05 9.6 kbps 9.6 kbps 9600.960 0x06 0x83 19.2 kbps 19.2 kbps 19196.16 0x03 0x41 38.4 kbps 38415.36 0x01 0xA1 76.8 kbps 76738.60 0x00 0xD0 153.6 kbps 153846.1 Classical modem baud rates (multiples of 0.9 kbps) 0x02 0x2C 57.6 kbps 57553.95 0x01 0x16 115.2 kbps 115107.9

RFM92W/93W V2.0 Page 44 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Type BitRate (15:8) BitRate (7:0) (G)FSK (G)MSK OOK Actual BR (b/s) Round bit rates (multiples of 12.5, 25 and 50 kbps) 0x0A 0x00 12.5 kbps 12.5 kbps 12500.00 0x05 0x00 25 kbps 25 kbps 25000.00 0x80 0x00 50 kbps 50000.00 0x01 0x40 100 kbps 100000.0 0x00 0xD5 150 kbps 150234.7 0x00 0xA0 200 kbps 200000.0 0x00 0x80 250 kbps 250000.0 0x00 0x6B 300 kbps 299065.4 Watch Xtal frequency 0x03 0xD1 32.768 kbps 32.768 kbps 32753.32 4.2.2. FSK/OOK Transmission 4.2.2.1. FSK Modulation FSK modulation is performed inside the PLL bandwidth by changing the fractional divider ratio in the feedback loop of the PLL. The high resolution of the sigma-delta modulator allows for very narrow frequency deviation. The frequency deviation FDEV is given by: FDE V = FSTE P  Fde v (13,0) To ensure correct modulation the following limit applies: FDE V Note No constraint applies to the modulation index of the transmitter, but the frequency deviation must be set between 600 Hz and 200 kHz. 4.2.2.2. OOK Modulation OOK modulation is applied by switching on and off the power amplifier. Digital control and ramping are available to improve the transient power response of the OOK transmitter. 4.2.2.3. Modulation Shaping Modulation shaping can be applied in both OOK and FSK modulation modes to improve the narrowband response of the transmitter. Both shaping features are controlled with PaRamp bits in RegPaRamp.  In FSK mode, a Gaussian filter with BT = 0.5 or 1 can be used to filter the modulation stream, at the input of the sigma- delta modulator. If the Gaussian filter is enabled when the RFM92W/93W is in Continuous mode, DCLK signal on pin 10 (DIO1/DCLK) will trigger an interrupt on the uC each time a new bit has to be transmitted. Please refer to section 5.4.2 for details.  When OOK modulation is used the PA bias voltages are ramped up and down smoothly when the PA is turned on and off to reduce spectral splatter.

Note The transmitter must be restarted if the ModulationShaping setting is changed in order to recalibrate the built-in filter. The FSK demodulator of the RFM92W/93W is designed to demodulate FSK, GFSK, MSK and GMSK modulated signals. synchronous data stream in Continuous mode. are available, configured through bits OokThreshType in RegOokPeak. Figure 14. OOK Peak Demodulator Description every OokPeakThreshDec period. the peak threshold level will continue falling until it reaches the “Floor Threshold” programmed in OokFixedThresh.

(i.e. those close to the noise floor). Significant sensitivity improvements can be generated if configured correctly.  The noise figure of the receiver.  The gain of the receive chain from antenna to base band.  The matching - including SAW filter if any.  The bandwidth of the channel filters. is recommended to optimize OokFixedThresh. Figure 15. Floor Threshold Optimization The new floor threshold value found during this test should be used for OOK reception with those receiver settings.

Figure 16. Bit Synchronizer Description better the ensuing packet detection rate will be.  The absolute error between transmitted and received bit rate must not exceed 6.5%.

RFM92W/93W V2.0 Page 48 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com 4.2.3.4. Frequency Error Indicator This frequency error indicator measures the frequency error between the programmed RF centre frequency and the carrier frequency of the modulated input signal to the receiver. When the FEI is performed the frequency error is measured and the signed result is loaded in FeiValue in RegFei in 2‟s complement format. The time required for an FEI evaluation is 4 bit periods. To ensure correct operation of the FEI:  The measurement must be launched during the reception of preamble.  The sum of the frequency offset and the 20 dB signal bandwidth must be lower than the base band filter bandwidth. i.e. The whole modulated spectrum must be received. The 20 dB bandwidth of the signal can be evaluated as follows (double-side bandwidth): =  The frequency error, in Hz, can be calculated with the following formula: FEI = FSTE P  Fe iV alue The FEI is enabled automatically upon the transition to receive mode and automatically updated every 4 bits. 4.2.3.5. AFC The AFC is based on the FEI measurement therefore the same input signal and receiver setting conditions apply. When the AFC procedure is performed the AfcValue is directly subtracted f rom the register that defines the frequency of operation of the chip, FRF. The AFC is executed each time the receiver is enabled, if AfcAutoOn = 1. When the AFC is enabled (AfcAutoOn = 1) the user has the option to:  Clear the former AFC correction value if AfcAutoClearOn = 1. Allowing the next frequency correction to be performed from the initial centre frequency.  Start the AFC evaluation from the previously corrected frequency. This may be useful in systems in which the centre frequency experiences cumulative drift - such as the ageing of a crystal reference. The RFM92W/93W offers an alternate receiver bandwidth setting during the AFC phase allowing the accommodation of larger frequency errors. The setting RegAfcBw sets the receive bandwidth during the AFC process. In a typical receiver application, once the AFC is performed, the radio will revert to the receiver communication or channel bandwidth (RegRxBw) for the ensuing communication phase. Note that the FEI measurement is valid only during the reception of preamble. The provision of the PreambleDetect flag can hence be used to detect this condition and allow a reliable AFC or FEI operation to be triggered. This process can be performed automatically by using the appropriate options in StartDemodOnPreamble found in the RegRxConfig register. A detailed description of the receiver setup to enable the AFC is provided in section 4.2.7.

RFM92W/93W V2.0 Page 49 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com PreambleDetectorSize # of Bytes 00 1 01 2 (recommended) 10 3 11 reserved 4.2.3.6. Preamble Detector The Preamble Detector indicates the reception of a carrier modulated with a 0101...sequence. It is insensitive to the frequency offset, as long as the receiver bandwidth is large enough. The size of detection can be programmed from 1 to 3 bytes with PreambleDetectorSize in RegPreambleDetect as defined in the next table. Table 19 Preamble Detector Settings For normal operation, PreambleDetectTol should be set to be set to 10 (0x0A) with a qualifying preamble size of 2 bytes. The PreambleDetect interrupt (either in RegIrqFlags1 or mapped to a specific DIO) then goes high every time a valid preamble is detected assuming PreambleDetectorOn=1. The preamble detector can also be used as a gate to ensure that AFC and AGC are performed on valid preamble. See section 4.2.7. for details. 4.2.3.7. Image Rejection Mixer The RFM92W/93W employs an image rejection mixer (IRM) which, uncalibrated, gives 35 dB image rejection. The low phase noise PLL is used to perform calibration of the receiver chain. Which increases the typical image rejection to 48 dB. This process is fully automated in FSK/OOK mode and radio power-up. 4.2.3.8. Image and RSSI Calibration An automatic calibration process is used to calibrate the phase and gain of both I and Q receive paths. This calibration allows enhanced image frequency rejection and improves the RSSI precision. This calibration process is launched under the following circumstances:  Automatically at Power On Reset or after a Manual Reset of the chip (refer to section 7.2). For applications where the temperature remains stable, or if the Image Rejection is not a major concern, this single calibration will suffice.  Automatically when a pre-defined temperature change is observed.  Upon User request, by setting bit ImageCalStart in RegImageCal, when the device is in Standby mode. Note that in LoRaTM mode the calibration command is inaccessible. To perform the calibration the radio must be returned temporarily to FSK/OOK mode. A selectable temperature change, set with TempThreshold (5, 10, 15 or 20°C), is detected and reported in TempChange if the temperature monitoring is turned On with TempMonitorOff = 0. This interrupt flag can be used by the application to launch a new image calibration at a convenient time if AutoImageCalOn=0, or immediately when this temperature variation is detected, if AutoImageCalOn=1.

RFM92W/93W V2.0 Page 50 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com The calibration process takes approximately 10 ms. 4.2.3.9. Timeout Function The RFM92W/93W includes a Timeout function, which allows the automation of a duty-cycled recceive oprtation where the radio periodically wakes from sleep mode into receiver mode.  Timeout interrupt is generated TimeoutRxRssi x 16 x Tbit after switching to Rx mode if the Rssi flag does not raise within this time frame (RssiValue > RssiThreshold).  Timeout interrupt is generated TimeoutRxPreamble x 16 x Tbit after switching to Rx mode if the PreambleDetect flag does not raise within this time frame.  Timeout interrupt is generated TimeoutSignalSync x 16 x Tbit after switching to Rx mode if the SyncAddress flag does not raise within this time frame. This timeout interrupt can be used to warn the companion processor to shut down the receiver and return to a lower power mode. To become active, these timeouts must also be enabled by setting the correct RxTrigger parameters in RegRxConfig: Table 20 RxTrigger Settings to Enable Timeout Interrupts Receiver Triggering Event RxTrigger (2:0) Timeout on Rssi Timeout on Preamble Timeout on SyncAddress None 000 Off Off Active Rssi Interrupt 001 Active Off PreambleDetect 110 Off Active Rssi Interrupt & PreambleDetect 111 Active Active 4.2.4. Operating Modes in FSK/OOK Mode 4.2.5. General Overview The RFM92W/93W has several working modes, manually programmed in RegOpMode. Fully automated mode selection, packet transmission and reception is also possible using the Top Level Sequencer described in Section 4.2.9. Table 21 Basic Transceiver Modes Mode Selected mode Symbol Enabled blocks

000 Sleep mode Sleep None

001 Standby mode Stdby Top regulator and crystal oscillator

010 Frequency synthesiser to Tx

FSTx Frequency synthesizer at Tx frequency (Frf)

011 Transmit mode Tx Frequency synthesizer and transmitter

100 Frequency synthesiser to Rx

FSRx Frequency synthesizer at frequency for reception (Frf-IF)

101 Receive mode Rx Frequency synthesizer and receiver

When switching from a mode to another the sub-blocks are woken up according to a pre-defined optimized sequence.

The startup time of the transmitter or the receiver is dependent upon which mode the transceiver was in at the beginning. For a complete description, Figure 17 below shows a complete startup process, from the lower power mode “Sleep”.

0 TS_OSC TS_OSC

Figure 17. Startup Process the startup time of the PLL including systematic calibration of the VCO. Typical values of TS_OSC and TS_FS are given in Section 2.3. where PaRamp is the ramp-up time programmed in RegPaRamp and Tbit is the bit time.

receive mode instruction was issued.

0 TS_RE TS_RE

Figure 18. Time to Rssi Sample calculate TS_RSSI is provided in section 2.5.4.

0 TS_HOP

Figure 19. Tx to Rx Turnaround Figure 20. Rx to Tx Turnaround

Figure 21. Receiver Hopping The second method is quicker and should be used if a very quick RF sniffing mechanism is to be implemented. Figure 22. Transmitter Hopping  When the receiver is turned On. RestartRxWithPllLock in RegRxConfig.  When the receiver is automatically restarted after the reception of a valid packet or after a packet collision.

RFM92W/93W V2.0 Page 55 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Automatic restart capabilities are detailed in Section 4.2.8. The receiver startup options available in RFM92W/93W are described in Table 23. Table 23 Receiver Startup Options Triggering Event Realized Function AgcAutoOn AfcAutoOn RxTrigger (2:0) None None 0 0 000 Rssi Interrupt AGC 1 0 001 AGC & AFC 1 1 001 PreambleDetect AGC 1 0 110 AGC & AFC 1 1 110 Rssi Interrupt PreambleDetect AGC 1 0 111 AGC & AFC 1 1 111 When AgcAutoOn=0, the LNA gain is manually selected by choosing LnaGain bits in RegLna. 4.2.8. Receiver Restart Methods The options for restart of the receiver are covered below. This is typically of use to prepare for the reception of a new signal whose strength or carrier frequency is different from the preceding packet to allow the AGC or AFC to be re-evaluated. 4.2.8.1. Restart Upon User Request In Receive mode the user can request a receiver restart - this can be useful in conjunction with the use of a Timeout interrupt following a period of inactivity in the channel of interest. Two options are available:  No change in the Local Oscillator upon restart: the AFC is disabled, and the Frf register has not been changed through SPI before the restart instruction: set bit RestartRxWithoutPllLock in RegRxConfig to 1.  Local Oscillator change upon restart: if AFC is enabled (AfcAutoOn=1), and/or the Frf register had been changed during the last Rx period: set bit RestartRxWithPllLock in RegRxConfig to 1. Note ModeReady must be at logic level 1 for a new RestartRx command to be taken into account. 4.2.8.2. Automatic Restart after valid Packet Reception The bits AutoRestartRxMode in RegSyncConfig control the automatic restart feature of the RFM92W/93W receiver, when a valid packet has been received:  If AutoRestartRxMode = 00, the function is off, and the user should manually restart the receiver upon valid packet reception (see section 4.2.8.1).  If AutoRestartRxMode = 01, after the user has emptied the FIFO following a PayloadReady interrupt, the receiver will automatically restart itself after a delay of InterPacketRxDelay, allowing for the distant transmitter to ramp down, hence avoiding a false RSSI detection on the „tail‟ of the previous packet.  If AutoRestartRxMode = 10 should be used if the next reception is expected on a new frequency, i.e. Frf is changed after the reception of the previous packet. An additional delay is systematically added, in order for the PLL to lock at a new frequency.

RFM92W/93W V2.0 Page 56 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com 4.2.8.3. Automatic Restart when Packet Collision is Detected In receive mode the RFM92W/93W is able to detect packet collision and restart the receiver. Collisions are detected by a sudden rise in received signal strength, detected by the RSSI. This functionality can be useful in network configurations where many asynchronous slaves attempt periodic communication with a single a master node. The collision detector is enabled by setting bit RestartRxOnCollision to 1. The decision to restart the receiver is based on the detection of RSSI change. The sensitivity of the system can be adjusted in 1 dB steps by using register RssiCollisionThreshold in RegRxConfig. 4.2.9. Top Level Sequencer Depending on the application it may be desirable to be able to change the mode of the circuit according to a predefined sequence without access to the serial interface. In order to define different sequences or scenarios a user-programmable state machine called the Top Level Sequencer (herein reffered to as the Sequencer) can automatically control the chip modes. NOTE THAT THIS FUNCTIONALITY IS ONLY AVAILABLE IN FSK/OOK MODE. The Sequencer is activated by setting the SequencerStart bit in RegSeqConfig1 to 1 in Sleep or Standby mode (called initial mode). It is also possible to force the Sequencer off by setting the Stop bit in RegSeqConfig1 to 1 at any time. Note SequencerStart and Stop bit must never be set at the same time. 4.2.9.1. Sequencer States As shown in the table below, with the aid of a pair of interrupt timers (T1 and T2), the sequencer can take control of the chip operation in all modes. Table 24 Sequencer States Sequencer State The Sequencer is not activated. Sending a SequencerStart command will launch it. When coming from LowPowerSelection state, the Sequencer will be Off, whilst the chip will return to its initial mode (either Sleep or Standby mode). Idle State The chip is in low-power mode, either Standby or Sleep, as defined by IdleMode in RegSeqConfig1. The Sequencer waits only for the T1 interrupt. Transmit State The transmitter in on. Receive State The receiver in on. PacketReceived The receiver is on and a packet has been received. It is stored in the FIFO. LowPowerSelection Selects low power state (SequencerOff or Idle State)

RFM92W/93W V2.0 Page 57 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RxTimeout Defines the action to be taken on a RxTimeout interrupt. RxTimeout interrupt can be a TimeoutRxRssi, TimeoutRxPreamble or TimeoutSignalSync interrupt. 4.2.9.2. Sequencer Transitions The transitions between sequencer states are listed in the forthcoming table. Table 25 Sequencer Transition Options Variable Transition IdleMode Selects the chip mode during Idle state: 0: Standby mode 1: Sleep mode FromStart Controls the Sequencer transition when the SequencerStart bit is set to 1 in Sleep or Standby mode: 00: to LowPowerSelection 01: to Receive state 10: to Transmit state 11: to Transmit state on a FifoThreshold interrupt LowPowerSelection Selects Sequencer LowPower state after a to LowPowerSelection transition 0: SequencerOff state with chip on Initial mode 1: Idle state with chip on Standby or Sleep mode depending on IdleMode Note: Initial mode is the chip LowPower mode at Sequencer start. FromIdle Controls the Sequencer transition from the Idle state on a T1 interrupt: 0: to Transmit state 1: to Receive state FromTransmit Controls the Sequencer transition from the Transmit state: 0: to LowPowerSelection on a PacketSent interrupt 1: to Receive state on a PacketSent interrupt FromReceive Controls the Sequencer transition from the Receive state: 000 and 111: unused 001: to PacketReceived state on a PayloadReady interrupt 010: to LowPowerSelection on a PayloadReady interrupt 011: to PacketReceived state on a CrcOk interrupt. If CRC is wrong (corrupted packet, with CRC on but CrcAutoClearOn is off), the PayloadReady interrupt will drive the sequencer to RxTimeout state. 100: to SequencerOff state on a Rssi interrupt 101: to SequencerOff state on a SyncAddress interrupt 110: to SequencerOff state on a PreambleDetect interrupt Irrespective of this setting, transition to LowPowerSelection on a T2 interrupt FromRxTimeout Controls the state-machine transition from the Receive state on a RxTimeout interrupt (and on PayloadReady if FromReceive = 011): 00: to Receive state via ReceiveRestart 01: to Transmit state 10: to LowPowerSelection 11: to SequencerOff state Note: RxTimeout interrupt is a TimeoutRxRssi, TimeoutRxPreamble or TimeoutSignalSync interrupt.

generate interrupts, which can trigger transitions of the Sequencer. T1 interrupt is generated (Timer1Resolution * Timer1Coefficient) after T2 interrupt or SequencerStart. command. T2 interrupt is generated (Timer2Resolution * Timer2Coefficient) after T1 interrupt. The timer mechanism is summarized on the following diagram. Figure 23. Timer1 and Timer2 Mechanism

RFM92W/93W V2.0 Page 59 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Table 26 Sequencer Timer Settings Variable Description Timer1Resolution Resolution of Timer1 00: disabled 01: 64 us 10: 4.1 ms 11: 262 ms Timer2Resolution Resolution of Timer2 00: disabled 01: 64 us 10: 4.1 ms 11: 262 ms Timer1Coefficient Multiplying coefficient for Timer1 Timer2Coefficient Multiplying coefficient for Timer2

transition arrow. For better readability, the start transitions are separated from the rest of the graph. Sequencer off by setting the Stop bit in RegSeqConfig1 to 1 at any time. Figure 24. Sequencer State Machine

demodulator and the uC access points (SPI and DIO pins). It also controls all the configuration registers. The circuit contains several control blocks which are described in the following paragraphs. Figure 25. RFM92W/93W Data Processing Conceptual View used if adequate external signal processing is available. the optional features activated (CRC, etc) the maximum payload length is limited to 255, 2047 bytes or unlimited. Each of these data operation modes is fully described in the following sections.

In First Out). It is accessed via the SPI interface and provides several interrupts for transfer management. from the demodulator and writes them byte by byte to the FIFO. This is illustrated in figure below. Figure 26. FIFO and Shift Register (SR) The FIFO size is fixed to 64 bytes.  FifoFull: FifoFull interrupt source is high when the last FIFO byte, i.e. the whole FIFO, is full. Otherwise it is low.  PacketSent: PacketSent interrupt source goes high when the SR's last bit has been sent.  FifoLevel: Threshold can be programmed by FifoThreshold in RegFifoThresh. Its behavior is illustrated in figure below.

0 B B+1

Figure 27. FifoLevel IRQ Source Behavior synchronizer must also be activated in Continuous mode (automatically done in Packet mode). word and sets SyncAddressMatch when a match is detected. This is illustrated in Figure 28 below.

Figure 28. Sync Word Recognition SyncAddressMatch is cleared when leaving Rx or FIFO is emptied. field is also used for Sync word generation in Tx mode. The packet handler is the block used in Packet mode. Its functionality is fully described in section 4.2.14.

RFM92W/93W V2.0 Page 65 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com 4.2.12. Digital IO Pins Mapping Six general purpose IO pins are available on the RFM92W/93W and their configuration in Continuous or Packet mode is controlled through RegDioMapping1 and RegDioMapping2. Table 28 DIO Mapping, Continuous Mode DIOx Mapping Sleep Standby FSRx/Tx Rx Tx 00 - SyncAddress TxReady DIO0 01 - Rssi / PreambleDetect - 10 - RxReady TxReady 11 - 00 - Dclk DIO1 01 - Rssi / PreambleDetect - 10 - 11 - 00 - Data DIO2 01 - Data 10 - Data 11 - Data 00 - Timeout - DIO3 01 - Rssi / PreambleDetect - 10 - 11 - TempChange / LowBat TempChange / LowBat 00 - TempChange / LowBat DIO4 01 - PllLock 10 - TimeOut - 11 - ModeReady ModeReady

00 ClkOut if RC ClkOut ClkOut

10 - Rssi / PreambleDetect - 11 - ModeReady ModeReady Table 29 DIO Mapping, Packet Mode DIOx Mapping Sleep Standby FSRx/Tx Rx Tx 00 - PayloadReady PacketSent DIO0 01 - CrcOk - 10 - 11 - TempChange / LowBat TempChange / LowBat

00 FifoLevel FifoLevel FifoLevel

DIO1 01 FifoEmpty FifoEmpty FifoEmpty

10 FifoFull FifoFull FifoFull

00 FifoFull FifoFull FifoFull

10 FifoFull TimeOut FifoFull

11 FifoFull SyncAddress FifoFull

00 FifoEmpty FifoEmpty FifoEmpty

10 FifoEmpty FifoEmpty FifoEmpty

11 FifoEmpty FifoEmpty FifoEmpty

00 - TempChange / LowBat TempChange / LowBat DIO4 01 - PllLock 10 - TimeOut - 11 - Rssi / PreambleDetect -

Figure 31. Rx Processing in Continuous Mode DCLK signal is not used by the uC (bit synchronizer is automatically enabled in Packet mode). accessed via the SPI interface. generation, CRC calculation/check, whitening/dewhitening of data, Manchester encoding/decoding, address filtering, etc. This simplifies software and reduces uC overhead by performing these repetitive tasks within the RF chip itself. when accessing payload data.

Figure 32. Packet Mode Conceptual View Note The Bit Synchronizer is automatically enabled in Packet mode. The length of the payload is limited to 2047 bytes. address byte. In this mode the payload must contain at least one byte i.e. address or message byte.

Figure 33. Fixed Length Packet Format Variable length packet format is selected when bit PacketFormat is set to 1. bytes i.e. length + address or message byte.

RFM92W/93W V2.0 Page 71 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com 4.2.14.3. Tx Processing In Tx mode the packet handler dynamically b uilds the packet by performing the following operations on the payload available in the FIFO:  Add a programmable number of preamble bytes.  Add a programmable Sync word.  Optionally calculating CRC over complete payload field (optional length byte + optional address byte + message) and appending the 2 bytes checksum.  Optional DC-free encoding of the data (Manchester or whitening). Only the payload (including optional address and length fields) is required to be provided by the user in the FIFO. The transmission of packet data is initiated by the Packet Handler only if the chip is in Tx mode and the transmission condition defined by TxStartCondition is fulfilled. If transmission condition is not fulfilled then the packet handler transmits a preamble sequence until the condition is met. This happens only if the preamble length /= 0, otherwise it transmits a zero or one until the condition is met to transmit the packet data. The transmission condition itself is defined as:  if TxStartCondition = 1, the packet handler waits until the first byte is written into the FIFO, then it starts sending the preamble followed by the sync word and user payload  If TxStartCondition = 0, the packet handler waits until the number of bytes written in the FIFO is equal to the number defined in RegFifoThresh + 1  If the condition for transmission was already fulfilled i.e. the FIFO was filled in Sleep/Stdby then the transmission of packet starts immediately on enabling Tx 4.2.14.4. Rx Processing In Rx mode the packet handler extracts the user payload to the FIFO by performing the following operations:  Receiving the preamble and stripping it off.  Detecting the Sync word and stripping it off.  Optional DC-free decoding of data.  Optionally checking the address byte.  Optionally checking CRC and reflecting the result on CrcOk.. Only the payload (including optional address and length fields) is made available in the FIFO. When the Rx mode is enabled the demodulator receives the preamble followed by the detection of sync word. If fixed length packet format is enabled then the number of bytes received as the payload is given by the PayloadLength parameter. In variable length mode the first byte received after the sync word is interpreted as the length of the received packet. The internal length counter is initialized to this received length. The PayloadLength register is set to a value which is greater than the maximum expected length of the received packet. If the received length is greater than the maximum length stored in PayloadLength register the packet is discarded otherwise the complete packet is received. If the address check is enabled then the second byte received in case of variable length and first byte in case of fixed length is the address byte. If the address matches to the one in the NodeAddress field reception of the data continues otherwise it's stopped. The CRC check is performed if CrcOn = 1 and the result is available in CrcOk indicating that the

RFM92W/93W V2.0 Page 72 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com CRC was successful. An interrupt (PayloadReady) is also generated on DIO0 as soon as the payload is available in the FIFO. The payload available in the FIFO can also be read in Sleep/Standby mode. If the CRC fails the PayloadReady interrupt is not generated and the FIFO is cleared. This function can be overridden by setting CrcAutoClearOff = 1, forcing the availability of PayloadReady interrupt and the payload in the FIFO even if the CRC fails. 4.2.14.5. Handling Large Packets When PayloadLength exceeds FIFO size (64 bytes) whether in fixed, variable or unlimited length packet format, in addition to PacketSent in Tx and PayloadReady or CrcOk in Rx, the FIFO interrupts/flags can be used as described below:  For Tx: FIFO can be prefilled in Sleep/Standby but must be refilled “on-the-fly” during Tx with the rest of the payload. 1) Pre-fill FIFO (in Sleep/Standby first or directly in Tx mode) until FifoThreshold or FifoFull is set 2) In Tx, wait for FifoThreshold or FifoEmpty to be set (i.e. FIFO is nearly empty) 3) Write bytes into the FIFO until FifoThreshold or FifoFull is set. 4) Continue to step 2 until the entire message has been written to the FIFO (PacketSent will fire when the last bit of the packet has been sent).  For Rx: FIFO must be emptied “on-the-fly” during Rx to prevent FIFO overrun. 1) Start reading bytes from the FIFO when FifoEmpty is cleared or FifoThreshold becomes set. 2) Suspend reading from the FIFO if FifoEmpty fires before all bytes of the message have been read 3) Continue to step 1 until PayloadReady or CrcOk fires 4) Read all remaining bytes from the FIFO either in Rx or Sleep/Standby mode 4.2.14.6. Packet Filtering The RFM92W/93W packet handler offers several mechanisms for packet filtering, ensuring that only useful packets are made available to the uC, significantly reducing system power consumption and software complexity. Sync Word Based Sync word filtering/recognition is used for identifying the start of the payload and also for network identification. As previously described, the Sync word recognition block is configured (size, value) in RegSyncConfig and RegSyncValue(i) registers. This information is used both for appending Sync word in Tx and filtering packets in Rx. Every received packet which does not start with this locally configured Sync word is automatically discarded and no interrupt is generated. When the Sync word is detected payload reception automatically starts and SyncAddressMatch is asserted. Note Sync Word values containing 0x00 are forbidden.

RFM92W/93W V2.0 Page 73 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Address Based Address filtering can be enabled via the AddressFiltering bits. It adds another level of filtering above Sync word (i.e. Sync must match first) and is typically useful in a multi-node networks where a network ID is shared between all nodes (Sync word) and each node has its own ID (address). Two address based filtering options are available:  AddressFiltering = 01: Received address field is compared with internal register NodeAddress. If they match then the packet is accepted and processed, otherwise it is discarded.  AddressFiltering = 10: Received address field is compared with internal registers NodeAddress and BroadcastAddress. If either is a match, the received packet is accepted and processed, otherwise it is discarded. This additional check with a constant is useful for implementing broadcast in a multi-node networks Please note that the received address byte, as part of the payload, is not stripped off the packet and is made available in the FIFO. In addition, NodeAddress and AddressFiltering only apply to Rx. On Tx side, if address filtering is expected, the address byte should simply be put into the FIFO like any other byte of the payload. As address filtering requires a Sync word match hence both features share the same interrupt flag SyncAddressMatch. Length Based In variable length Packet mode, PayloadLength must be programmed with the maximum payload length permitted. If received length byte is smaller than this maximum then the packet is accepted and processed, otherwise it is discarded. Please note that the received length byte, as part of the payload, is not stripped off the packet and is made available in the FIFO. To disable this function the user should set the value of the PayloadLength to 2047. CRC Based The CRC check is enabled by setting bit CrcOn in RegPacketConfig1. It is used for checking the integrity of the message.  On Tx side a two byte CRC checksum is calculated on the payload part of the packet and appended to the end of the message  On Rx side the checksum is calculated on the received payload and compared with the two checksum bytes received. The result of the comparison is stored in bit CrcOk. By default, if the CRC check fails then the FIFO is automatically cleared and no interrupt is generated. This filtering function can be disabled via CrcAutoClearOff bit and in this case, even if CRC fails, the FIFO is not cleared and only PayloadReady interrupt goes high. Please note that in both cases, the two CRC checksum bytes are stripped off by the packet handler and only the payload is made available in the FIFO. Two CRC implementations are selected with bit CrcWhiteningType. Table 30 CRC Description Crc Type CrcWhiteningType Polynomial Seed Value Complemented CCITT 0 (default) X16 + X12 + X5 + 1 0x1D0F Yes IBM 1 X16 + X15 + X2 + 1 0xFFFF No A C code implementation of each CRC type is proposed in Application Section 7.

For such purposes, two techniques are made available in the packet handler: Manchester encoding and data whitening. Note Only one of the two methods can be enabled at a time. Manchester encoding/decoding is enabled if DcFree = 01 and can only be used in Packet mode. The NRZ data is converted to Manchester code by coding '1' as “10” and '0' as “01”. Bit Rate NRZ = 2 x Bit Rate Manchester). Manchester encoding/decoding is thus transparent with NRZ transferred between FIFO and MCU. Figure 36. Manchester Encoding/Decoding Another technique called whitening or scrambling is widely used for randomizing the user data before radio transmission. The data is whitened using a random sequence on the Tx side and de-whitened on the Rx side using the same sequence. actual bit rate is not halved. on the receiver side by XORing with the same random sequence.

Figure 37. Data Whitening Polynomial multiple times with the same data. exits Transmit mode. FifoEmpty, FifoFull and FifoLevel flags are also restored. example in section 4.2.14.8. The Beacon Tx mode is exited by setting BeaconOn to 0 and clearing the FIFO by setting FifoOverrun to 1. details on its implementation.

CPOL = 0 and CPHA = 0 in Motorola/Freescale nomenclature. Only the slave side is implemented. beginning of the frame and stay low between each byte. It goes high only after the last byte transfer. The figure below shows a typical SPI single access to a register. Figure 38. SPI Timing Diagram (single access) rising edge of SCK. MISO is generated by the slave on the falling edge of SCK. A transfer is always started by the NSS pin going low. MISO is high impedance when NSS is high.  A wnr bit, which is 1 for write access and 0 for read access.  Then 7 bits of address, MSB first. MISO in case of read access. The data byte is transmitted MSB first.

RFM92W/93W V2.0 Page 77 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com The frame ends when NSS goes high. The next frame must start with an address byte. The SINGLE access mode is therefore a special case of FIFO / BURST mode with only 1 data byte transferred. During the write access the byte transferred from the slave to the master on the MISO line is the value of the written register before the write operation.

1. RFM92W/93W Analog & RF Frontend

VR_PA, VR_DIG and VR_ANA pins to ensure correct operation of the built-in voltage regulators. mapped to any of the DIO pins by programming RegDioMapping. frequency synthesis and as the clock signal for all digital processing. oscillator signal is stable. RegTcxo should be set to 1 and the external clock has to be provided on XTA (pin 4). XTB (pin 5) should be left open. appropriate value of decoupling capacitor, CD.

32 MHz

Figure 39. TCXO Connection

RFM92W/93W V2.0 Page 79 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com 5.3.2. CLKOUT Output The reference frequency, or a fraction of it, can be provided on DIO5 (pin 12) by modifying bits ClkOut in RegDioMapping2. Two typical applications of the CLKOUT output include:  To provide a clock output for a companion processor, thus saving the cost of an additional oscillator. CLKOUT can be made available in any operation mode except Sleep mode and is automatically enabled at power on reset.  To provide an oscillator reference output. Measurement of the CLKOUT signal enables simple software trimming of the initial crystal tolerance. Note To minimize the current consumption of the RFM92W/93W, please ensure that the CLKOUT signal is disabled when not required. 5.3.3. PLL The local oscillator of the RFM92W/93W is derived from a fractional-N PLL that is referenced to the crystal oscillator circuit. Two PLLs are available for transmit mode operation - either low phase noise or low current consumption to maximize either transmit power consumption or transmit spectral purity respectively. Both PLLs feature a programmable bandwidth setting where one of four discrete preset bandwidths may be accessed. For reference the relative performance of both low consumption and low phase noise PLLs, for each programmable bandwidth setting, is shown in the following figure.

Figure 40. Typical Phase Noise Performances of the Low Consumption and Low Phase Noise PLLs. Note In receive mode only the low consumption PLL is available.

RFM92W/93W V2.0 Page 81 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com The carrier frequency is programmed through RegFrf, split across addresses 0x06 to 0x08: FRF = FSTE P  Frf(23,0) Note The Frf setting is split across 3 bytes. A change in the center frequency will only be taken into account when the least significant byte FrfLsb in RegFrfLsb is written. This allows the potential for user generation of m-ary FSK at very low bit rates. This is possible where frequency modulation is achieved by direct programming of the programmed RF centre frequency. To enable this functionality set the FastHopOn bit of register RegPllHop. 5.3.4. RC Oscillator All timing operations in the low-power Sleep state of the Top Level Sequencer rely on the accuracy of the internal low- power RC oscillator. This oscillator is automatically calibrated at the device power-up not requiring any user input.

power amplifier blocks, together with the DC biasing and ramping functionality that is provided through the VR_PA block. operation up to +20 dBm. For full details of operation at +20 dBm please consult Section 5.4.3. Figure 41. RF Front-end Architecture Shows the Internal PA Configuration. consumption. PA0 is connected to pin RFO (pin 24). this document for more details).

0 PA0 output on pin RFO -1 to +14 dBm -1 dBm + OutputPower

1 PA1 and PA2 combined on pin PA_-

RFM92W/93W V2.0 Page 83 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Notes - For +20 dBm restrictions on operation please consult the following section. - To ensure correct operation at the highest power levels ensure that the current limiter OcpTrim is adjusted to permit delivery of the requisite supply current. - If the PA_BOOST pin is not used it may be left floating. 5.4.3. High Power +20 dBm Operation The RFM92W/93W has a high power +20 dBm capability on PA_BOOST pin, with the following settings: Table 32 High Power Settings Register Address Value for High Power Default value PA0 or +17dBm 0x84 High power PA control Notes - High Power settings must be turned off when using PA0 - The Over Current Protection limit should be adapted to the actual power level, in RegOcp Specific Absolute Maximum Ratings and Operating Range restrictions apply to the +20 dBm operation. They are listed in Table 33 and Table 34. Table 33 Operating Range, +20 dBm Operation Symbol DC_20dBm Duty Cycle of transmission at +20 dBm output - 1 % VSWR_20dBm Maximum VSWR at antenna port, +20 dBm output - 3:1 - Table 34 Operating Range, +20 dBm Operation Symbol VDDop_20dBm Supply voltage, +20 dBm output 2.4 3.7 V The duty cycle of transmission at +20 dBm is limited to 1%, with a maximum VSWR of 3:1 at antenna port, over the standard operating range (-40 to +85 ° C). For any other operating conditions, contact your Semtech representative.

RFM92W/93W V2.0 Page 84 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com 5.4.4. Over Current Protection The power amplifiers of RFM92W/93W are protected against current over supply in adverse RF load conditions by the over current protection block. This has the added benefit of protecting battery chemistries with limited peak current capability and minimising worst case PA consumption in battery life calculations. The current limiter value is controlled by the OcpTrim bits in RegOcp and is calculated according to the following formulas: Table 35 Trimming of the OCP Current OcpTrim IMAX Imax Formula 0 to 15 45 to 120 mA 45 + 5*OcpTrim [mA] 16 to 27 130 to 240 mA -30 + 10*OcpTrim [mA] 27+ 240 mA 240 [mA] Note Imax sets a limit on the current drain of the Power Amplifier only, hence the maximum current drain of the RFM92/ 73 is equal to Imax + IFS. 5.5. Receiver Description 5.5.1. Overview The RFM92W/93W features a digital receiver with the analog to digital conversion process performed directly following the LNA-Mixer block. In addition to the LoRaTM modulation scheme the low-IF receiver is able to demodulate ASK, OOK, (G)FSK and (G)MSK modulation. All filtering, demodulation, gain control, synchronization and packet handling is performed digitally allowing a high degree of programmable flexibility. The receiver also has automatic gain calibration, this improves the precision of RSSI measurement and enhances image rejection. 5.5.2. Receiver Enabled and Receiver Active States In the receiver operating mode two states of functionality are defined. Upon initial transition to receiver operating mode the receiver is in the „receiver-enabled‟ state. In this state the receiver awaits for either the user defined valid preamble or RSSI detection criterion to be fulfilled. Once met the receiver enters „receiver-active‟ state. In this second state the received signal is processed by the packet engine and top level sequencer. For a complete description of the digital functions of the RFM92W/93W receiver please see Section 5.5 of the datasheet.

Figure 42. Receiver Block Diagram level of 0 dBm or more, whilst optimizing the system linearity. The following table shows typical NF and IIP3 performances for the RFM92W/93W LNA gains available.

Figure 43. AGC Steps Definition with SNR = 8 dB (considered a fixed value). A detailed description of the receiver setup to enable the AGC is provided in section 9.3. SNR and response time versus the number of RSSI samples programmed in RssiSmoothing.

RFM92W/93W V2.0 Page 87 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Table 37 RssiSmoothing Options RssiSmoothing Number of Samples Estimated Accuracy Response Time „000‟ 2 ± 6 dB „001‟ 4 ± 5 dB „010‟ 8 ± 4 dB „011‟ 16 ± 3 dB „100‟ 32 ± 2 dB „101‟ 64 ± 1.5 dB „110‟ 128 ± 1.2 dB „111‟ 256 ± 1.1 dB The RSSI is calibrated when the image and RSSI calibration process is launched. Please see Section for details. 5.5.5. RSSI in LoRaTM Mode The RSSI values reported by the LoRaTM modem differ from those expressed by the FSK/OOK modem. The following formula shows the method used to interpret the LoRaTM RSSI values. R SSI dB m  = –125 + RSSI 5.5.6. Channel Filter The role of the channel filter is to reject noise and interference outside of the wanted channel. The RFM92W/93W channel filtering is implemented with a 16-tap finite impulse response (FIR) filter. Rejection of the filter is high enough that the filter stop-band performance is not the dominant influence on adjacent channel rejection performance. This is instead limited by the RFM92W/93W PLL phase noise. Note To respect sampling criterion in the decimation chain of the receiver, the communication bit rate cannot be set at a higher than twice the single side receiver bandwidth (BitRate < 2 x RxBw) The programmed single side bandwidth RxBw of the channel filter is determined by the parameters RxBwMant and RxBwExp in RegRxBw: RxB wMan t  2RxBw E x p + 2 The following channel filter bandwidths are hence accessible in the case of a 32 MHz reference oscillator. Table 38 Available RxBw Settings RxBwMant (binary/value) RxBwExp (decimal) RxBw (kHz) FSK / OOK 10b / 24 7 2.6 01b / 20 7 3.1 00b / 16 7 3.9 10b / 24 6 5.2

stored in TempValue in RegTemp. including source code, please consult the applications section of this document. Figure 44. Temperature Sensor Response

RFM92W/93W V2.0 Page 89 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com 6. Description of the Registers The register mapping d epends upon whether FSK/OOK or LoRaTM mode has been selected. The following table summarises the location and function of each register and gives an overview of the changes in register mapping between both modes of operation. 6.1. Register Table Summary Table 39 Registers Summary Address Register Name Reset (POR) Default (FSK) FSK/OOK Mode LoRaTM Mode FSK Mode LoRaTM Mode 0x00 RegFifo 0x00 FIFO read/write access 0x01 RegOpMode 0x01 Operating mode & LoRaTM / FSK selection 0x02 RegBitrateMsb Unused 0x1A Bit Rate setting, Most Significant Bits 0x03 RegBitrateLsb 0x0B Bit Rate setting, Least Significant Bits 0x04 RegFdevMsb 0x00 Frequency Deviation setting, Most Significant Bits 0x05 RegFdevLsb 0x52 Frequency Deviation setting, Least Significant Bits 0x06 RegFrfMsb 0xE4 RF Carrier Frequency, Most Significant Bits 0x07 RegFrfMid 0xC0 RF Carrier Frequency, Intermediate Bits 0x08 RegFrfLsb 0x00 RF Carrier Frequency, Least Significant Bits 0x09 RegPaConfig 0x0F PA selection and Output Power control 0x0A RegPaRamp 0x19 Control of PA ramp time, low phase noise PLL 0x0B RegOcp 0x2B Over Current Protection control 0x0C RegLna 0x20 LNA settings 0x0D RegRxConfig RegFifoAddrPtr 0x08 0x00 AFC, AGC, ctrl FIFO SPI pointer 0x0E RegRssiConfig RegFifoTxBa- seAddr 0x02 0x80 RSSI Start Tx data 0x0F RegRssiCollision RegFifoRxBa- seAddr 0x0A 0x00 RSSI Collision detector Start Rx data 0x10 RegRssiThresh FifoRxCurren- tAddr 0xFF n/a RSSI Threshold control Start address of last packet received 0x11 RegRssiValue RegIrqFlagsMask n/a n/a RSSI value in dBm Optional IRQ flag mask 0x12 RegRxBw RegIrqFlags 0x15 0x00 Channel Filter BW Control IRQ flags 0x13 RegAfcBw RegRxNbBytes 0x0B n/a AFC Channel Filter BW Number of received bytes 0x14 RegOokPeak RegRxHeaderCnt ValueMsb 0x28 n/a OOK demodulator Number of valid headers received 0x15 RegOokFix RegRxHeaderCnt ValueLsb 0x0C Threshold of the OOK demod 0x16 RegOokAvg RegRxPacketCnt ValueMsb 0x12 n/a Average of the OOK demod Number of valid packets received 0x17 Reserved17 RegRxPacketCnt ValueLsb 0x47 0x18 Reserved18 RegModemStat 0x32 0x10 - Live LoRaTM modem status 0x19 Reserved19 RegPktSnrValue 0x3E n/a - Espimation of last packet SNR 0x1A RegAfcFei RegPktRssiValue 0x00 n/a AFC and FEI control RSSI of last packet

RFM92W/93W V2.0 Page 90 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Address Register Name Reset (POR) Default (FSK) FSK/OOK Mode LoRaTM Mode FSK Mode LoRaTM Mode 0x1B RegAfcMsb RegRssiValue 0x00 n/a Frequency correction value of the AFC Current RSSI 0x1C RegAfcLsb RegHopChannel 0x00 n/a FHSS start channel 0x1D RegFeiMsb RegModemConfig 0x00 0x08 Value of the calculated frequency error Modem PHY config 1 0x1E RegFeiLsb RegModemConfig 0x00 0x74 Modem PHY config 2 0x1F RegPreambleDe- tect RegSymbTimeout Lsb 0x40 0x64 Settings of the Preamble Detector Receiver timeout value 0x20 RegRxTimeout1 RegPreambleMsb 0x00 0x00 Timeout Rx request and RSSI Size of preamble 0x21 RegRxTimeout2 RegPreambleLsb 0x00 0x08 Timeout RSSI and Pay- loadReady 0x22 RegRxTimeout3 RegPay- loadLength 0x00 0x01 Timeout RSSI and SyncAd- dress LoRaTM payload length 0x23 RegRxDelay RegMaxPayloadL ength 0x00 0xFF Delay between Rx cycles LoRaTM maximum pay- load length 0x24 RegOsc RegHopPeriod 0x05 0x00 RC Oscillators Settings, CLK- OUT frequency FHSS Hop period 0x25 RegPreambleMsb RegFifoRxByteAd dr 0x00 n/a Preamble length, MSB Address of last byte written in FIFO 0x26 RegPreambleLsb RESERVED 0x03 Preamble length, LSB LoRaTM rx data pointer 0x27 RegSyncConfig 0x93 Sync Word Recognition control RESERVED 0x28- 0x2F RegSyncValue1-8 0x55 0x01 Sync Word bytes, 1 through 8 0x30 RegPacketConfig1 0x90 Packet mode settings 0x31 RegPacketConfig2 0x40 Packet mode settings 0x32 RegPayloadLength 0x40 Payload length setting 0x33 RegNodeAdrs RESERVED 0x00 Node address RESERVED 0x34 RegBroadcastAdrs 0x00 Broadcast address 0x35 RegFifoThresh 0x0F 0x8F Fifo threshold, Tx start condi- tion 0x36 RegSeqConfig1 0x00 Top level Sequencer settings 0x37 RegSeqConfig2 0x00 Top level Sequencer settings 0x38 RegTimerResol 0x00 Timer 1 and 2 resolution control 0x39 RegTimer1Coef 0xF5 Timer 1 setting 0x3A RegTimer2Coef 0x20 Timer 2 setting 0x3B RegImageCal 0x82 0x02 Image calibration engine con- trol 0x3C RegTemp - Temperature Sensor value 0x3D RegLowBat 0x02 Low Battery Indicator Settings 0x3E RegIrqFlags1 0x80 Status register: PLL Lock state, Timeout, RSSI 0x3F RegIrqFlags2 0x40 Status register: FIFO handling flags, Low Battery 0x40 RegDioMapping1 0x00 Mapping of pins DIO0 to DIO3 0x41 RegDioMapping2 0x00 Mapping of pins DIO4 and DIO5, ClkOut frequency

RFM92W/93W V2.0 Page 91 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Address Register Name Reset (POR) Default (FSK) FSK/OOK Mode LoRaTM Mode FSK Mode LoRaTM Mode 0x42 RegVersion 0x22 Semtech ID relating the silicon revision 0x43 RegAgcRef 0x13 Adjustment of the AGC thresholds 0x44 RegAgcThresh1 0x0E 0x45 RegAgcThresh2 0x5B 0x46 RegAgcThresh3 0xDB 0x4B RegPllHop 0x2E Control the fast frequency hopping mode 0x58 RegTcxo 0x09 TCXO or XTAL input setting 0x5A RegPaDac 0x84 Higher power settings of the PA 0x5C RegPll 0xD0 Control of the PLL bandwidth 0x5E RegPllLowPn 0xD0 Control of the Low Phase Noise PLL bandwidth 0x6C RegFormerTemp - Stored temperature during the former IQ Calibration 0x70 RegBitRateFrac 0x00 Fractional part in the Bit Rate division ratio 0x42 + RegTest - Internal test registers. Do not overwrite Note - Reset values are automatically refreshed in the chip at Power On Reset - Default values are the Semtech recommended register values, optimizing the device operation - Registers for which the Default value differs from the Reset value are denoted by an * in the tables of section 6.2

RFM92W/93W V2.0 Page 92 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com 6.2. FSK/OOK Mode Register Map This section details the RFM92W/93W register mapping and the precise contents of each register in FSK/OOK mode. Convention: r: read, w: write, t:trigger, c: clear Table 40 Register Map Name (Address) Bits Variable Name Mode Default value FSK/OOK Description RegFifo (0x00) 7-0 Fifo rw 0x00 FIFO data input/output Registers for Common settings RegOpMode (0x01) LongRangeMode r 0x00 0  FSK/OOK Mode 1 LoRaTM Mode This bit can be modified only in Sleep mode. A write operation on other device modes is ignored. 6-5 ModulationType rw 0x00 Modulation scheme: 00  FSK 01  OOK 10 -11  reserved 4-3 ModulationShaping rw 0x00 Data shaping: In FSK: 00  no shaping 01  Gaussian filter BT = 1.0 10  Gaussian filter BT = 0.5 11  Gaussian filter BT = 0.3 In OOK: 00  no shaping 01  filtering with fcutoff = bit_rate 10  filtering with fcutoff = 2*bit_rate (for bit_rate < 125 kbps) 11  reserved 2-0 Mode rw 0x01 Transceiver modes 000  Sleep mode 001  Stdby mode 010  FS mode TX (FSTx) 011  Transmitter mode (Tx) 100  FS mode RX (FSRx) 101  Receiver mode (Rx) 110  reserved 111  reserved RegBitrateMsb (0x02) 7-0 BitRate(15:8) rw 0x1A MSB of Bit Rate (chip rate if Manchester encoding is enabled) RegBitrateLsb (0x03) 7-0 BitRate(7:0) rw 0x0B LSB of bit rate (chip rate if Manchester encoding is enabled) Bi tR ate(15,0) + -B----i--t--r--a- - --t--e---F----r--a----c- Default value: 4.8 kbps

RFM92W/93W V2.0 Page 93 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Name (Address) Bits Variable Name Mode Default value FSK/OOK Description RegFdevMsb (0x04) 7-6 unused r 0x00 unused 5-0 Fdev(13:8) rw 0x00 MSB of the frequency deviation RegFdevLsb (0x05) 7-0 Fdev(7:0) rw 0x52 LSB of the frequency deviation Fdev = Fste p  Fdev(15,0) Default value: 5 kHz RegFrfMsb (0x06) 7-0 Frf(23:16) rw 0xE4 MSB of the RF carrier frequency RegFrfMid (0x07) 7-0 Frf(15:8) rw 0xC0 MSB of the RF carrier frequency RegFrfLsb (0x08) 7-0 Frf(7:0) rw 0x00 LSB of RF carrier frequency Frf = F ste p  Frf 23;0  Default value: 915.000 MHz The RF frequency is taken into account internally only when: - entering FSRX/FSTX modes - re-starting the receiver Registers for the Transmitter RegPaConfig (0x09) PaSelect rw 0x00 Selects PA output pin 0  RFO pin. Maximum power of +13 dBm 1  PA_BOOST pin. Maximum power of +20 dBm 6-4 unused r 0x00 unused 3-0 OutputPower rw 0x0F Output power setting, with 1dB steps Pout = 2 + OutputPower [dBm], on PA_BOOST pin Pout = -1 + OutputPower [dBm], on RFO pin RegPaRamp (0x0A) 7-5 unused r - unused LowPnTxPllOff rw 0x01 Select a higher power, lower phase noise PLL only when the transmitter is used: 0  Standard PLL used in Rx mode, Lower PN PLL in Tx 1  Standard PLL used in both Tx and Rx modes 3-0 PaRamp rw 0x09 Rise/Fall time of ramp up/down in FSK 0000  3.4 ms 0001  2 ms 0010  1 ms 0011  500 us 0100  250 us 0101  125 us 0110  100 us 0111  62 us 1000  50 us 1001  40 us (d) 1010  31 us 1011  25 us 1100  20 us 1101  15 us 1110  12 us 1111  10 us

RFM92W/93W V2.0 Page 94 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Name (Address) Bits Variable Name Mode Default value FSK/OOK Description RegOcp (0x0B) 7-6 unused r 0x00 unused OcpOn rw 0x01 Enables overload current protection (OCP) for the PA: 0  OCP disabled 1  OCP enabled 4-0 OcpTrim rw 0x0B Trimming of OCP current: Imax = 45+5*OcpTrim [mA] if OcpTrim <= 15 (120 mA) / Imax = -30+10*OcpTrim [mA] if 15 < OcpTrim <= 27 (130 to 240 mA) Imax = 240mA for higher settings Default Imax = 100mA Registers for the Receiver RegLna (0x0C) 7-5 LnaGain rw 0x01 LNA gain setting: 000  reserved 001  G1 = highest gain 010  G2 = highest gain – 6 dB 011  G3 = highest gain – 12 dB 100  G4 = highest gain – 24 dB 101  G5 = highest gain – 36 dB 110  G6 = highest gain – 48 dB 111  reserved Note: Reading this address always returns the current LNA gain (which may be different from what had been previously selected if AGC is enabled. 4-2 - r 0x00 unused 1-0 LnaBoost rw 0x00 Improves the system Noise Figure at the expense of Rx current consumption: 00  Default setting, meeting the specification 11  Improved sensitivity RegRxConfig (0x0D) RestartRxOnCollision rw 0x00 Turns on the mechanism restarting the receiver automatically if it gets saturated or a packet collision is detected 0  No automatic Restart 1  Automatic restart On RestartRxWithoutPllLock wt 0x00 Triggers a manual Restart of the Receiver chain when set to 1. Use this bit when there is no frequency change, RestartRxWithPllLock otherwise. RestartRxWithPllLock wt 0x00 Triggers a manual Restart of the Receiver chain when set to 1. Use this bit when there is a fr equency change, requiring some time for the PLL to re-lock. AfcAutoOn rw 0x00 0  No AFC performed at receiver startup 1  AFC is performed at each receiver startup AgcAutoOn rw 0x01 0  LNA gain forced by the LnaGain Setting 1  LNA gain is controlled by the AGC 2-0 RxTrigger rw 0x06 Selects the event triggering AGC and/or AFC at receiver startup. See Table 18 for a description.

RFM92W/93W V2.0 Page 95 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Name (Address) Bits Variable Name Mode Default value FSK/OOK Description RegRssiConfig (0x0E) 7-3 RssiOffset rw 0x00 Signed RSSI offset, to compensate for the possible losses/gains in the front-end (LNA, SAW filter...) 1dB / LSB, 2‟s complement format 2-0 RssiSmoothing rw 0x02 Defines the number of samples taken to average the RSSI result: 000  2 samples used 001  4 samples used 010  8 samples used 011  16 samples used 100  32 samples used 101  64 samples used 110  128 samples used 111  256 samples used RegRssiCollision (0x0F) 7-0 RssiCollisionThreshold rw 0x0A Sets the threshold used to consider that an interferer is detected, witnessing a packet collision. 1dB/LSB (only RSSI increase) Default: 10dB RegRssiThresh (0x10) 7-0 RssiThreshold rw 0xFF RSSI trigger level for the Rssi interrupt: - RssiThreshold / 2 [dBm] RegRssiValue (0x11) 7-0 RssiValue r - Absolute value of the RSSI in dBm, 0.5dB steps. RSSI = - RssiValue/2 [dBm] RegRxBw (0x12) 7 unused r - unused 6-5 reserved rw 0x00 reserved 4-3 RxBwMant rw 0x02 Channel filter bandwidth control: 00  RxBwMant = 16 10  RxBwMant = 24 01  RxBwMant = 20 11  reserved 2-0 RxBwExp rw 0x05 Channel filter bandwidth control: FSK Mode: Rx BwMan t  2RxBwEx p + 2 RegAfcBw (0x13) 7-5 reserved rw 0x00 reserved 4-3 RxBwMantAfc rw 0x01 RxBwMant parameter used during the AFC 2-0 RxBwExpAfc rw 0x03 RxBwExp parameter used during the AFC RegOokPeak (0x14) 7-6 reserved rw 0x00 reserved BitSyncOn rw 0x01 Enables the Bit Synchronizer. 0  Bit Sync disabled (not possible in Packet mode) 1  Bit Sync enabled 4-3 OokThreshType rw 0x01 Selects the type of threshold in the OOK data slicer: 00  fixed threshold 10  average mode 01  peak mode (default) 11  reserved 2-0 OokPeakTheshStep rw 0x00 Size of each decrement of the RSSI threshold in the OOK demodulator: 000  0.5 dB 001  1.0 dB 010  1.5 dB 011  2.0 dB 100  3.0 dB 101  4.0 dB 110  5.0 dB 111  6.0 dB

RFM92W/93W V2.0 Page 96 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Name (Address) Bits Variable Name Mode Default value FSK/OOK Description RegOokFix (0x15) 7-0 OokFixedThreshold rw 0x0C Fixed threshold for the Data Slicer in OOK mode Floor threshold for the Data Slicer in OOK when Peak mode is used RegOokAvg (0x16) 7-5 OokPeakThreshDec rw 0x00 Period of decrement of the RSSI threshold in the OOK demodulator: 000  once per chip 001  once every 2 chips 010  once every 4 chips 011  once every 8 chips 100  twice in each chip 101  4 times in each chip 110  8 times in each chip 111  16 times in each chip 4 reserved rw 0x01 reserved 3-2 OokAverageOffset rw 0x00 Static offset added to the threshold in average mode in order to reduce glitching activity (OOK only): 00  0.0 dB 10  4.0 dB 01  2.0 dB 11  6.0 dB 1-0 OokAverageThreshFilt rw 0x02 Filter coefficients in average mode of the OOK demodulator: 00  fC ≈ chip rate / 32.π 01  fC ≈ chip rate / 8.π 10  fC ≈ chip rate / 4.π 11 fC ≈ chip rate / 2.π RegRes17 to RegRes19 7-0 reserved rw 0x47 0x32 0x3E reserved. Keep the Reset values. RegAfcFei (0x1A) 7-5 unused r - unused 4 AgcStart wt 0x00 Triggers an AGC sequence when set to 1. 3 reserved rw 0x00 reserved 2 unused - - unused 1 AfcClear wc 0x00 Clear AFC register set in Rx mode. Always reads 0. AfcAutoClearOn rw 0x00 Only valid if AfcAutoOn is set 0  AFC register is not cleared at the beginning of the automatic AFC phase 1  AFC register is cleared at the beginning of the automatic AFC phase RegAfcMsb (0x1B) 7-0 AfcValue(15:8) rw 0x00 MSB of the AfcValue, 2‟s complement format. Can be used to overwrite the current AFC value RegAfcLsb (0x1C) 7-0 AfcValue(7:0) rw 0x00 LSB of the AfcValue, 2‟s complement format. Can be used to overwrite the current AFC value RegFeiMsb (0x1D) 7-0 FeiValue(15:8) rw - MSB of the measured frequency offset, 2‟s complement. Must be read before RegFeiLsb. RegFeiLsb (0x1E) 7-0 FeiValue(7:0) rw - LSB of the measured frequency offset, 2‟s complement Frequency error = FeiValue x Fstep

RFM92W/93W V2.0 Page 97 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Name (Address) Bits Variable Name Mode Default value FSK/OOK Description RegPreambleDetect (0x1F) PreambleDetectorOn rw 0x01 Enables Preamble detector when set to 1. The AGC settings supersede this bit during the startup / AGC phase. 0  Turned off 1  Turned on 6-5 PreambleDetectorSize rw 0x01 Number of Preamble bytes to detect to trigger an interrupt 00  1 byte 10  3 bytes 01  2 bytes 11  Reserved 4-0 PreambleDetectorTol rw 0x0A Number or chip errors tolerated over PreambleDetectorSize. 4 chips per bit. RegRxTimeout1 (0x20) 7-0 TimeoutRxRssi rw 0x00 Timeout interrupt is generated TimeoutRxRssi*16*Tbit after switching to Rx mode if Rssi interrupt doesn‟t occur (i.e. RssiValue > RssiThreshold) 0x00: TimeoutRxRssi is disabled RegRxTimeout2 (0x21) 7-0 TimeoutRxPreamble rw 0x00 Timeout interrupt is generated TimeoutRxPreamble*16*Tbit after switching to Rx mode if Preamble interrupt doesn‟t occur 0x00: TimeoutRxPreamble is disabled RegRxTimeout3 (0x22) 7-0 TimeoutSignalSync rw 0x00 Timeout interrupt is generated TimeoutSignalSync*16*Tbit after the Rx mode is programmed, if SyncAddress doesn‟t occur 0x00: TimeoutSignalSync is disabled RegRxDelay (0x23) 7-0 InterPacketRxDelay rw 0x00 Additional delay before an automatic receiver restart is launched: Delay = InterPacketRxDelay*4*Tbit RC Oscillator registers RegOsc (0x24) 7-4 unused r - unused RcCalStart wt 0x00 Triggers the calibration of the RC oscillator when set. Always reads 0. RC calibration must be triggered in Standby mode. 2-0 ClkOut rw 0x07 Selects CLKOUT frequency: 000  FXOSC 001  FXOSC / 2 010  FXOSC / 4 011  FXOSC / 8 100  FXOSC / 16 101  FXOSC / 32 110  RC (automatically enabled) 111  OFF Packet Handling registers RegPreambleMsb (0x25) 7-0 PreambleSize(15:8) rw 0x00 Size of the preamble to be sent (from TxStartCondition fulfilled). (MSB byte) RegPreambleLsb (0x26) 7-0 PreambleSize(7:0) rw 0x03 Size of the preamble to be sent (from TxStartCondition fulfilled). (LSB byte)

RFM92W/93W V2.0 Page 98 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Name (Address) Bits Variable Name Mode Default value FSK/OOK Description RegSyncConfig (0x27) 7-6 AutoRestartRxMode rw 0x02 Controls the automatic restart of the receiver after the reception of a valid packet (PayloadReady or CrcOk): 00  Off 01  On, without waiting for the PLL to re-lock 10  On, wait for the PLL to lock (frequency changed) 11  reserved PreamblePolarity rw 0x00 Sets the polarity of the Preamble 0  0xAA (default) 1  0x55 SyncOn rw 0x01 Enables the Sync word generation and detection: 0  Off 1  On FifoFillCondition rw 0x00 FIFO filling condition: 0  if SyncAddress interrupt occurs 1  as long as FifoFillCondition is set 2-0 SyncSize rw 0x03 Size of the Sync word: (SyncSize + 1) bytes, (SyncSize) bytes if ioHomeOn=1 RegSyncValue1 (0x28) 7-0 SyncValue(63:56) rw 0x01 1st byte of Sync word. (MSB byte) Used if SyncOn is set. RegSyncValue2 (0x29) 7-0 SyncValue(55:48) rw 0x01 2nd byte of Sync word Used if SyncOn is set and (SyncSize +1) >= 2. RegSyncValue3 (0x2A) 7-0 SyncValue(47:40) rw 0x01 3rd byte of Sync word. Used if SyncOn is set and (SyncSize +1) >= 3. RegSyncValue4 (0x2B) 7-0 SyncValue(39:32) rw 0x01 4th byte of Sync word. Used if SyncOn is set and (SyncSize +1) >= 4. RegSyncValue5 (0x2C) 7-0 SyncValue(31:24) rw 0x01 5th byte of Sync word. Used if SyncOn is set and (SyncSize +1) >= 5. RegSyncValue6 (0x2D) 7-0 SyncValue(23:16) rw 0x01 6th byte of Sync word. Used if SyncOn is set and (SyncSize +1) >= 6. RegSyncValue7 (0x2E) 7-0 SyncValue(15:8) rw 0x01 7th byte of Sync word. Used if SyncOn is set and (SyncSize +1) >= 7. RegSyncValue8 (0x2F) 7-0 SyncValue(7:0) rw 0x01 8th byte of Sync word. Used if SyncOn is set and (SyncSize +1) = 8.

RFM92W/93W V2.0 Page 99 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Name (Address) Bits Variable Name Mode Default value FSK/OOK Description RegPacketConfig1 (0x30) PacketFormat rw 0x01 Defines the packet format used: 0  Fixed length 1  Variable length 6-5 DcFree rw 0x00 Defines DC-free encoding/decoding performed: 00  None (Off) 01  Manchester 10  Whitening 11  reserved CrcOn rw 0x01 Enables CRC calculation/check (Tx/Rx): 0  Off 1  On CrcAutoClearOff rw 0x00 Defines the behavior of the packet handler when CRC check fails: 0  Clear FIFO and restart new packet reception. No PayloadReady interrupt issued. 1  Do not clear FIFO. PayloadReady interrupt issued. 2-1 AddressFiltering rw 0x00 Defines address based filtering in Rx: 00  None (Off) 01  Address field must match NodeAddress 10  Address field must match NodeAddress or BroadcastAddress 11  reserved CrcWhiteningType rw 0x00 Selects the CRC and whitening algorithms: 0  CCITT CRC implementation with standard whitening 1  IBM CRC implementation with alternate whitening RegPacketConfig2 (0x31) 7 unused r - unused DataMode rw 0x01 Data processing mode: 0  Continuous mode 1  Packet mode IoHomeOn rw 0x00 Enables the io-homecontrol® compatibility mode 0  Disabled 1  Enabled

4 IoHomePowerFrame rw 0x00 reserved - Linked to io-homecontrol® compatibility mode

3 BeaconOn rw 0x00 Enables the Beacon mode in Fixed packet format

2-0 PayloadLength(10:8) rw 0x00 Packet Length Most significant bits RegPayloadLength (0x32) 7-0 PayloadLength(7:0) rw 0x40 If PacketFormat = 0 (fixed), payload length. If PacketFormat = 1 (variable), max length in Rx, not used in Tx. RegNodeAdrs (0x33) 7-0 NodeAddress rw 0x00 Node address used in address filtering. RegBroadcastAdrs (0x34) 7-0 BroadcastAddress rw 0x00 Broadcast address used in address filtering.

RFM92W/93W V2.0 Page 100 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Name (Address) Bits Variable Name Mode Default value FSK/OOK Description RegFifoThresh (0x35) TxStartCondition rw 0x01 Defines the condition to start packet transmission: 0  FifoLevel (i.e. the number of bytes in the FIFO exceeds FifoThreshold) 1  FifoEmpty goes low(i.e. at least one byte in the FIFO) 6 unused r - unused 5-0 FifoThreshold rw 0x0f Used to trigger FifoLevel interrupt, when: number of bytes in FIFO >= FifoThreshold + 1 Sequencer registers RegSeqConfig1 (0x36) SequencerStart wt 0x00 Controls the top level Sequencer When set to „1‟, executes the “Start” transition. The sequencer can only be enabled when the chip is in Sleep or Standby mode. SequencerStop wt 0x00 Forces the Sequencer Off. Always reads „0‟ IdleMode rw 0x00 Selects chip mode during the state: 0: Standby mode 1: Sleep mode 4-3 FromStart rw 0x00 Controls the Sequencer transition when SequencerStart is set to 1 in Sleep or Standby mode: 00: to LowPowerSelection 01: to Receive state 10: to Transmit state 11: to Transmit state on a FifoLevel interrupt LowPowerSelection rw 0x00 Selects the Sequencer LowPower state after a to LowPowerSelection transition: 0: SequencerOff state with chip on Initial mode 1: Idle state with chip on Standby or Sleep mode depending on IdleMode Note: Initial mode is the chip LowPower mode at Sequencer Start. FromIdle rw 0x00 Controls the Sequencer transition from the Idle state on a T1 interrupt: 0: to Transmit state 1: to Receive state FromTransmit rw 0x00 Controls the Sequencer transition from the Transmit state: 0: to LowPowerSelection on a PacketSent interrupt 1: to Receive state on a PacketSent interrupt

RFM92W/93W V2.0 Page 101 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Name (Address) Bits Variable Name Mode Default value FSK/OOK Description RegSeqConfig2 (0x37) 7-5 FromReceive rw 0x00 Controls the Sequencer transition from the Receive state 000 and 111: unused 001: to PacketReceived state on a PayloadReady interrupt 010: to LowPowerSelection on a PayloadReady interrupt 011: to PacketReceived state on a CrcOk interrupt (1) 100: to SequencerOff state on a Rssi interrupt 101: to SequencerOff state on a SyncAddress interrupt 110: to SequencerOff state on a PreambleDetect interrupt Irrespective of this setting, transition to LowPowerSelection on a T2 interrupt (1) If the CRC is wrong (corrupted packet, with CRC on but CrcAutoClearOn=0), the PayloadReady interrupt will drive the sequencer to RxTimeout state. 4-3 FromRxTimeout rw 0x00 Controls the state-machine transition from the Receive state on a RxTimeout interrupt (and on PayloadReady if FromReceive = 011): 00: to Receive State, via ReceiveRestart 01: to Transmit state 10: to LowPowerSelection 11: to SequencerOff state Note: RxTimeout interrupt is a TimeoutRxRssi, TimeoutRxPreamble or TimeoutSignalSync interrupt 2-0 FromPacketReceived rw 0x00 Controls the state-machine transition from the PacketReceived state: 000: to SequencerOff state 001: to Transmit state on a FifoEmpty interrupt 010: to LowPowerSelection 011: to Receive via FS mode, if frequency was changed 100: to Receive state (no frequency change) RegTimerResol (0x38) 7-4 unused r - unused 3-2 Timer1Resolution rw 0x00 Resolution of Timer 1 00: Timer1 disabled 01: 64 us 10: 4.1 ms 11: 262 ms 1-0 Timer2Resolution rw 0x00 Resolution of Timer 2 00: Timer2 disabled 01: 64 us 10: 4.1 ms 11: 262 ms RegTimer1Coef (0x39) 7-0 Timer1Coefficient rw 0xF5 Multiplying coefficient for Timer 1 RegTimer2Coef (0x3A) 7-0 Timer2Coefficient rw 0x20 Multiplying coefficient for Timer 2

RFM92W/93W V2.0 Page 102 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Name (Address) Bits Variable Name Mode Default value FSK/OOK Description Service registers RegImageCal (0x3B) AutoImageCalOn rw 0x00 Controls the Image calibration mechanism 0  Calibration of the receiver depending on the temperature is disabled 1  Calibration of the receiver depending on the temperature enabled. 6 ImageCalStart wt - Triggers the IQ and RSSI calibration when set in Standby mode. ImageCalRunning r 0x00 Set to 1 while the Image and RSSI calibration are running. Toggles back to 0 when the process is completed 4 unused r - unused TempChange r 0x00 IRQ flag witnessing a temperature change exceeding TempThreshold since the last Image and RSSI calibration: 0  Temperature change lower than TempThreshold 1  Temperature change greater than TempThreshold 2-1 TempThreshold rw 0x01 Temperature change threshold to trigger a new I/Q calibration 00  5 ° C 01  10 ° C 10  15 ° C 11  20 ° C TempMonitorOff rw 0x00 Controls the temperature monitor operation: 0  Temperature monitoring done in all modes except Sleep and Standby 1  Temperature monitoring stopped. RegTemp (0x3C) 7-0 TempValue r Measured temperature -1° C per Lsb Needs calibration for absolute accuracy RegLowBat (0x3D) 7-4 unused r - unused LowBatOn rw 0x00 Low Battery detector enable signal 0  LowBat detector disabled 1  LowBat detector enabled 2-0 LowBatTrim rw 0x02 Trimming of the LowBat threshold: 000  1.695 V 001  1.764 V 010  1.835 V (d) 011  1.905 V 100  1.976 V 101  2.045 V 110  2.116 V 111  2.185 V Status registers

RFM92W/93W V2.0 Page 103 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Name (Address) Bits Variable Name Mode Default value FSK/OOK Description RegIrqFlags1 (0x3E) ModeReady r Set when the operation mode requested in Mode, is ready - Sleep: Entering Sleep mode - Standby: XO is running - FS: PLL is locked - Rx: RSSI sampling starts - Tx: PA ramp-up completed Cleared when changing the operating mode. RxReady r - Set in Rx mode, after RSSI, AGC and AFC. Cleared when leaving Rx. TxReady r - Set in Tx mode, after PA ramp-up. Cleared when leaving Tx. PllLock r - Set (in FS, Rx or Tx) when the PLL is locked. Cleared when it is not. Rssi rwc - Set in Rx when the RssiValue exceeds RssiThreshold. Cleared when leaving Rx or setting this bit to 1. Timeout r - Set when a timeout occurs Cleared when leaving Rx or FIFO is emptied. PreambleDetect rwc - Set when the Preamble Detector has found valid Preamble. bit clear when set to 1 SyncAddressMatch rwc Set when Sync and Address (if enabled) are detected. Cleared when leaving Rx or FIFO is emptied. This bit is read only in Packet mode, rwc in Continuous mode RegIrqFlags2 (0x3F) 7 FifoFull r - Set when FIFO is full (i.e. contains 66 bytes), else cleared. FifoEmpty r - Set when FIFO is empty, and cleared when there is at least 1 byte in the FIFO. FifoLevel r - Set when the number of bytes in the FIFO strictly exceeds FifoThreshold, else cleared. FifoOverrun rwc Set when FIFO overrun occurs. (except in Sleep mode) Flag(s) and FIFO are cleared when this bit is set. The FIFO then becomes immediately available for the next transmission / reception. PacketSent r - Set in Tx when the complete packet has been sent. Cleared when exiting Tx PayloadReady r Set in Rx when the payload is ready (i.e. last byte received and CRC, if enabled and CrcAutoClearOff is cleared, is Ok). Cleared when FIFO is empty. CrcOk r - Set in Rx when the CRC of the payload is Ok. Cleared when FIFO is empty. LowBat rwc - Set when the battery voltage drops below the Low Battery threshold. Cleared only when set to 1 by the user. IO control registers

RFM92W/93W V2.0 Page 104 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Name (Address) Bits Variable Name Mode Default value FSK/OOK Description RegDioMapping1 (0x40) 7-6 Dio0Mapping rw 0x00 Mapping of pins DIO0 to DIO5 See Table 23 for mapping in LoRa mode See Table 27 for mapping in Continuous mode See table 28 for mapping in Packet mode 5-4 Dio1Mapping rw 0x00 3-2 Dio2Mapping rw 0x00 1-0 Dio3Mapping rw 0x00 RegDioMapping2 (0x41) 7-6 Dio4Mapping rw 0x00 5-4 Dio5Mapping rw 0x00 3-1 reserved rw 0x00 reserved. Retain default value MapPreambleDetect rw 0x00 Allows the mapping of either Rssi Or PreambleDetect to the DIO pins, as summarized on Table 27 and Table 28 0  Rssi interrupt 1  PreambleDetect interrupt Version register RegVersion (0x42) 7-0 Version r 0x22 Version code of the chip. Bits 7-4 give the full revision number; bits 3-0 give the metal mask revision number. Additional registers RegAgcRef (0x43) 7-6 unused r - unused 5-0 AgcReferenceLevel rw 0x13 Sets the floor reference for all AGC thresholds: AGC Reference [dBm] = -174 dBm + 10*log(2*RxBw) + SNR + AgcReferenceLevel SNR = 8 dB, fixed value RegAgcThresh1 (0x44) 7-5 unused r - unused 4-0 AgcStep1 rw 0x0E Defines the 1st AGC Threshold RegAgcThresh2 (0x45) 7-4 AgcStep2 rw 0x05 Defines the 2nd AGC Threshold: 3-0 AgcStep3 rw 0x0B Defines the 3rd AGC Threshold: RegAgcThresh3 (0x46) 7-4 AgcStep4 rw 0x0D Defines the 4th AGC Threshold: 3-0 AgcStep5 rw 0x0B Defines the 5th AGC Threshold: RegPllHop (0x4b) FastHopOn rw 0x00 Bypasses the main state machine for a quick frequency hop. Writing RegFrfLsb will trigger the frequency change. 0  Frf is validated when FSTx or FSRx is requested 1  Frf is validated triggered when RegFrfLsb is written 6-0 reserved rw 0x2E reserved RegTcxo (0x58) 7-5 reserved rw 0x00 reserved. Retain default value TcxoInputOn rw 0x00 Controls the crystal oscillator 0  Crystal Oscillator with external Crystal 1  External clipped sine TCXO AC-connected to XTA pin 3-0 reserved rw 0x09 Reserved. Retain default value. RegPaDac (0x5A) 7-3 reserved rw 0x10 reserved. Retain default value 2-0 PaDac rw 0x04 Enables the +20 dBm option on PA_BOOST pin 0x04  Default value 0x07  +20 dBm on PA_BOOST when OutputPower = 1111

RFM92W/93W V2.0 Page 105 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Name (Address) Bits Variable Name Mode Default value FSK/OOK Description RegPll (0x5C) 7-6 PllBandwidth rw 0x03 Controls the PLL bandwidth: 00  75 kHz 10  225 kHz 01  150 kHz 11  300 kHz 5-0 reserved rw 0x10 reserved. Retain default value RegPllLowPn (0x5E) 7-6 PllBandwidth rw 0x03 Controls the Low Phase Noise PLL bandwidth: 00  75 kHz 10  225 kHz 01  150 kHz 11  300 kHz 5-0 reserved rw 0x10 reserved. Retain default value RegFormerTemp (0x6C) 7-0 FormerTemp rw - Temperature saved during the latest IQ (RSSI and Image) calibrated. Same format as TempValue in RegTemp. RegBitrateFrac (0x70) 7-4 unused r 0x00 unused 3-0 BitRateFrac rw 0x00 Fractional part of the bit rate divider (Only valid for FSK) If BitRateFrac> 0 then: Bi tR ate(15,0) + -B----i--t--r--a- - --t--e---F----r--a----c-

RFM92W/93W V2.0 Page 106 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com 6.3. LoRaTM Mode Register Map This section details the RFM92W/93W register mapping and the precise contents of each register in LoRaTM mode. It is essential to understand that the LoRa modem is controlled independently of the FSK modem. Therefore, care should be taken when accessing the registers, especially as some register may have the same name in LoRa or FSK mode. The LoRa registers are only accessible when the device is set in Lora mode (and, in the same way, the FSK register are only accessible in FSK mode). However, in some cases, it may be necessary to access some of the FSK register while in LoRa mode. To this aim, the AccesSharedReg bit was created in the RegOpMode register. This bit, when set to „1‟, will grant access to the FSK register 0x0D up to the register 0x3F. Once the setup has been done, it is strongly recommended to clear this bit so that LoRa register can be access normally. Convention: r: read, w: write, c: set to clear and t: trigger Table 41 Register Map, LoRa Mode Name (Address) Bits Variable Name Mode Reset LoRaTM Description RegFifo (0x00) 7-0 Fifo rw 0x00 LoRaTM base-band FIFO data input/output. FIFO is cleared an not accessible when device is in SLEEP mode Common Register Settings RegOpMode (0x01) LongRangeMode rw 0x0 0  FSK/OOK Mode 1  LoRaTM Mode This bit can be modified only in Sleep mode. A write operation on other device modes is ignored. AccesSharedReg rw 0x0 This bit operates when device is in Lora mode; if set it allows access to FSK registers page located in address space (0x0D:0x3F) while in LoRa mode 0  Access LoRa registers page 0x0D: 0x3F 1  Access FSK registers page (in mode LoRa) 0x0D: 0x3F 5-3 unused r 0x00 2-0 Mode rwt 0x01 Device modes 000  SLEEP 001  STDBY 010  Frequency synthesis TX (FSTX) 011  Transmit (TX) 100  Frequency synthesis RX (FSRX) 101  Receive continuous (RXCONTINUOUS) 110  receive single (RXSINGLE) 111  Channel activity detection (CAD) (0x02) 7-0 reserved r 0x00 - (0x03) 7-0 reserved r 0x00 - (0x04) 7-0 reserved r 0x00 - (0x05) 7-0 reserved r 0x00 - RegFrMsb (0x06) 7-0 Frf(23:16) rw 0xE4 MSB of RF carrier frequency RegFrMid (0x07) 7-0 Frf(15:8) rw 0xC0 MSB of RF carrier frequency

RFM92W/93W V2.0 Page 107 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Name (Address) Bits Variable Name Mode Reset LoRaTM Description RegFrLsb (0x08) 7-0 Frf(7:0) rwt 0x00 LSB of RF carrier frequency 219 Resolution is 61.035 Hz if F(XOSC) = 32 MHz. Default value is 0xe4c000 = 915 MHz. Register values must be modified only when device is in SLEEP or STAND-BY mode. register for RF RegPaConfig (0x09) PaSelect rw 0x00 Selects PA output pin 0  RFIO pin. Output power is limited to 13 dBm. 1  PA_BOOST pin. Output power is limited to 20 dBm 6-4 unused r - unused 3-0 OutputPower rw 0x0F power amplifier max output power: Pout = 2 + OutputPower(3:0) on PA_BOOST. Pout = -1 + OutputPower(3:0) on RFIO. RegPaRamp (0x0A) 7-5 unused r - unused LowPnTxPllOff rw 0x01 1  Low consumption PLL is used in receive and transmit mode 0  Low consumption PLL in receive mode, low phase noise PLL in transmit mode. 3-0 PaRamp(3:0) rw 0x09 Rise/Fall time of ramp up/down in FSK 0000  3.4 ms 0001  2 ms 0010  1 ms 0011  500 us 0100  250 us 0101  125 us 0110  100 us 0111  62 us 1000  50 us 1001  40 us 1010  31 us 1011  25 us 1100  20 us 1101  15 us 1110  12 us 1111  10 us RegOcp (0x0B) 7-6 unused r 0x00 unused OcpOn rw 0x01 Enables overload current protection (OCP) for PA: 0  OCP disabled 1  OCP enabled 4-0 OcpTrim rw 0x0B Trimming of OCP current: Imax = 45+5*OcpTrim [mA] if OcpTrim <= 15 (120 mA) / Imax = -30+10*OcpTrim [mA] if 15 < OcpTrim <= 27 (130 to 240 mA) Imax = 240mA for higher settings Default Imax = 100mA

RFM92W/93W V2.0 Page 108 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Name (Address) Bits Variable Name Mode Reset LoRaTM Description RegLna (0x0C) 7-5 LnaGain rwx 0x01 LNA gain setting: 000  not used 001  G1 = maximum gain 010  G2 011  G3 100  G4 101  G5 110  G6 = minimum gain 111  not used 4-2 reserved r 0x00 - 1-0 LnaBoost rw 0x00 00  Default LNA current 11  Boost on, 150% LNA current. Lora page registers RegFifoAddrPtr (0x0D) 7-0 FifoAddrPtr rw 0x00 SPI interface address pointer in FIFO data buffer. RegFifoTxBaseAd dr (0x0E) 7-0 FifoTxBaseAddr rw 0x80 write base address in FIFO data buffer for TX modulator RegFifoRxBaseAd dr (0x0F) 7-0 FifoRxBaseAddr rw 0x00 read base address in FIFO data buffer for RX demodulator RegFifoRxCurrent Addr (0x10) 7-0 FifoRxCurrentAddr r n/a Start address (in data buffer) of last packet received RegIrqFlagsMask (0x11) RxTimeoutMask rw 0x00 Timeout interrupt mask: setting this bit masks the corresponding IRQ in RegIrqFlags RxDoneMask rw 0x00 Packet reception complete interrupt mask: setting this bit masks the corresponding IRQ in RegIrqFlags PayloadCrcErrorMask rw 0x00 Payload CRC error interrupt mask: setting this bit masks the corresponding IRQ in RegIrqFlags ValidHeaderMask rw 0x00 Valid header received in Rx mask: setting this bit masks the corresponding IRQ in RegIrqFlags TxDoneMask rw 0x00 FIFO Payload transmission complete interrupt mask: setting this bit masks the corresponding IRQ in RegIrqFlags CadDoneMask rw 0x00 CAD complete interrupt mask: setting this bit masks the corresponding IRQ in RegIrqFlags

1 FhssChangeChannelM

0x00 FHSS change channel interrupt mask: setting this bit masks the corresponding IRQ in RegIrqFlags CadDetectedMask rw 0x00 Cad Detected Interrupt Mask: setting this bit masks the corresponding IRQ in RegIrqFlags

RFM92W/93W V2.0 Page 109 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Name (Address) Bits Variable Name Mode Reset LoRaTM Description RegIrqFlags (0x12) RxTimeout rc 0x00 Timeout interrupt: a write operation clears IRQ RxDone rc 0x00 Packet reception complete interrupt: a write operation clears IRQ PayloadCrcError rc 0x00 Payload CRC error interrupt: a write operation clears IRQ ValidHeader rc 0x00 Valid header received in Rx: a write operation clears IRQ TxDone rc 0x00 FIFO Payload transmission complete interrupt: a write operation clears IRQ CadDone rc 0x00 CAD complete: write to clear: a write operation clears IRQ FhssChangeChannel rc 0x00 FHSS change channel interrupt: a write operation clears IRQ CadDetected rc 0x00 Valid Lora signal detected during CAD operation: a write operation clears IRQ RegRxNbBytes (0x13) 7-0 FifoRxBytesNb r n/a Number of payload bytes of latest packet received RegRxHeaderCnt ValueMsb (0x14) 7-0 ValidHeaderCntMsb(15: r n/a Number of valid headers received since last transition into Rx mode, MSB(15:8). Header and packet counters are reseted in Sleep mode. RegRxHeaderCnt ValueLsb (0x15) 7-0 ValidHeaderCntLsb(7:0) r n/a Number of valid headers received since last transition into Rx mode, LSB(7:0). Header and packet counters are reseted in Sleep mode. RegRxPacketCntV alueMsb (0x16) 7-0 ValidPacketCntMsb(15: rc n/a Number of valid packets received since last transition into Rx mode, MSB(15:8). Header and packet counters are reseted in Sleep mode. RegRxPacketCntV alueLsb (0x17) 7-0 ValidPacketCntLsb(7:0) r n/a Number of valid packets received since last transition into Rx mode, LSB(7:0). Header and packet counters are reseted in Sleep mode. RegModemStat (0x18) 7-5 RxCodingRate r n/a Coding rate of last header received ModemStatus r „1‟ Modem clear 3 r „0‟ Header info valid 2 r „0‟ RX on-going 1 r „0‟ Signal synchronized 0 r „0‟ Signal detected RegPktSnrValue (0x19) 7-0 PacketSnr r n/a Estimation of SNR on last packet received.In two‟s compliment format mutiplied by 4.

RFM92W/93W V2.0 Page 110 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Name (Address) Bits Variable Name Mode Reset LoRaTM Description RegPktRssiValue (0x1A) 7-0 PacketRssi r n/a RSSI of the latest packet received (dBm) R SSI dB m  = – 125 + Pac k et Rssi RegRssiValue (0x1B) 7-0 Rssi r n/a Current RSSI value (dBm) RSSI  dB m  = – 125 + Rssi RegHopChannel (0x1C) PllTimeout r n/a PLL failed to lock while attempting a TX/RX/CAD operation 1  PLL did not lock 0  PLL did lock RxPayloadCrcOn r n/a CRC Information extracted from the received packet header 0  Header indicates CRC off 1  Header indicates CRC on 5-0 FhssPresentChannel r n/a Current value of frequency hopping channel in use. RegModemConfig (0x1D) 7-6 Bw rw 0x0 Signal bandwidth: 00  125 kHz 01  250 kHz 10  500 kHz 11  reserved 5-3 CodingRate rw „001‟ Error coding rate 001  4/5 010  4/6 011  4/7 100  4/8 All other values  reserved In implicit header mode should be set on receiver to determine ImplicitHeaderModeOn rw 0x0 0  Explicit Header mode 1  Implicit Header mode RxPayloadCrcOn rw 0x0 Enable CRC generation on payload, in implicit header mode this it determines if receiver should expect a payload CRC. 0  CRC disable 1  CRC enable LowDataRateOptimize rw 0x0 0  Disabled 1  Enabled; mandated for SF11 and SF12 with BW = 125 kHz

RFM92W/93W V2.0 Page 111 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com Name (Address) Bits Variable Name Mode Reset LoRaTM Description RegModemConfig (0x1E) 7-4 SpreadingFactor rw 0x7 SF rate (expressed as a base-2 logarithm) 6  64 chips / symbol 7  128 chips / symbol 8  256 chips / symbol 9  512 chips / symbol 10  1024 chips / symbol 11  2048 chips / symbol 12  4096 chips / symbol other values reserved. TxContinuousMode rw 0  normal mode, a single packet is sent 1  continuous mode, send multiple packets across the FIFO (used for spectral analysis) AgcAutoOn rw 0x01 0  LNA gain set by register LnaGain 1  LNA gain set by the internal AGC loop 1-0 SymbTimeout(9:8) rw 0x00 RX Time-Out MSB RegSymbTimeoutL sb (0x1F) 7-0 SymbTimeout(7:0) rw 0x64 RX Time-Out LSB RX operation time-out value expressed as number of symbols: TimeOu t = Symb T imeou t  Ts RegPreambleMsb (0x20) 7-0 PreambleLength(15:8) rw 0x0 Preamble length MSB, = PreambleLength + 4.25 Symbols See Section for more details. RegPreambleLsb (0x21) 7-0 PreambleLength(7:0) rw 0x8 Preamble Length LSB RegPayloadLength (0x22) 7-0 PayloadLength(7:0) rw 0x1 Payload length in bytes. The register needs to be set in implicit header mode for the expected packet length. A 0 value is not permitted RegMaxPayloadLe ngth (0x23) 7-0 PayloadMaxLength(7:0) rw 0xFF Maximum payload length; if header payload length exceeds value a header CRC error is generated. Allows filtering of packet with a bad size. RegHopPeriod (0x24) 7-0 FreqHoppingPeriod(7:0) rw 0x0 Symbol periods between frequency hops. (0 = disabled). 1st hop always happen after the 1st header symbol RegFifoRxByteAdd r (0x25) 7-0 FifoRxByteAddrPtr r n/a Current value of RX databuffer pointer (address of last byte written by Lora receiver) (0x26) - (0x3F) Reserved r n/a Reserved

Table 42 shows the crystal resonator specification for the crystal reference oscillator circuit of the RFM92W/93W. This specification covers the full range of operation of the RFM92W/93W and is employed in the reference design. the target operating temperature range and the receiver bandwidth selected.

• the loading capacitance should be applied externally, and adapted to the actual Cload specification of the XTAL.

6 (Reset) should be left floating during the POR sequence. Figure 45. POR Timing Diagram Please note that any CLKOUT activity can also be used to detect that the chip is ready.

Figure 50. Wake On PreambleDetect State Machine optimize power consumption Timer2 must be set just long enough for Preamble detection. power consumption, Timer1 should be relatively long. However, increasing Timer1 also extends packet reception duration. as long as TTimer1 + 2 x TTimer2. 4 11 PreambleDetect – Note: MapPreambleDetect bit should be set.

RFM92W/93W V2.0 Page 118 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com LowPowerSelection 1: To Idle state FromIdle 1: To Receive state on T1 interrupt FromReceive 101: To Sequencer off on SyncAddress interrupt FromRxTimeout 10: To LowPowerSelection TTimeoutRxPreamble should be set to the expected transmit preamble duration (depends on PreambleDetectSize and BitRate). TTimer1 should be set to 64 µs (shortest possible duration). TTimer2 is set so that TTimer1 + TTimer2 defines the time between two start of reception. In order to ensure packet detection and optimize the receiver power consumption the received packet Preamble should be defined so that TPreamble = TTimer2 - TSyncAddress with TSyncAddress = (SyncSize + 1)*8/BitRate. An example of DIO configuration for this mode is described in the following table: Table 46 Listen Mode with PreambleDetect Condition Recommended DIO Mapping DIO Value Description 0 01 CrcOk 1 00 FifoLevel 2 11 SyncAddress 3 00 FifoEmpty 4 11 PreambleDetect – Note: MapPreambleDetect bit should be set.

RFM92W/93W V2.0 Page 120 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com This example is achieved by programming the Sequencer as follows: Table 47 Beacon Mode Settings Variable Effect IdleMode 1: Sleep mode FromStart 00: To LowPowerSelection LowPowerSelection 1: To Idle state FromIdle 0: To Transmit state on T1 interrupt FromTransmit 0: To LowPowerSelection on PacketSent interrupt TTimer1 + TTimer2 define the time between the start of two transmissions.

Figure 57. Example CRC Code

Figure 58. Example Temperature Reading

RFM92W/93W V2.0 Page 123 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com 7.7. Reference Design Please contact your representative for evaluation tools, reference designs and design assistance. Note that all schematics shown in this section are full schematics, listing ALL required components, including decoupling capacitors. A Figure 59:+20dBm Schematic

The RFM92W/93W is available in a package as shown in Figure 60. Figure 60. Package Outline Drawing

RFM92W/93W V2.0 Page 125 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com 9. Ordering Information DRFM92W/93W —868 S2 P/N: RFM92W-868S2 RFM92W module at 868MHz band, SMD Package P/N: RFM92W-915S2 RFM92W module at 9MHz band, SMD Package P/N: RFM93W-868S2 RFM93W module at 868MHz band, SMD Package P/N: RFM93W-915S2 RFM93W module at 915MHz band, SMD Package Package Operation Band Mode Type

RFM92W/93W V2.0 Page 126 Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com HOPE MICROELECTRONICS CO.,LTD Add: 2 /F, Building 3, Pingshan Private Enterprise Science and Technology Park, Lishan Road, XiLi Town, Nanshan District, Shenzhen, Guangdong, China Tel: 86-755-82973805 Fax: 86-755-82973550 Email: sales@hoperf.com Website: http://www.hoperf.com http://www.hoperf.cn This document may contain preliminary information and is subject to change by Hope Microelectronics without notice. Hope Microelectronics assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of Hope Microelectronics or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in the direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MECHANTABILITY OR FITNESS FOR A ARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT. ©2006, HOPE MICROELECTRONICS CO.,LTD. All rights reserved.