RFM7N35 INTERSIL | Alldatasheet
Document overview
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Technical content
Features
- 7A, 350V and 400V
- r DS(ON) = 0.75Ω
- SOA is Power Dissipation Limited
- Nanosecond Switching Speeds
- Linear Transfer Characteristics
- High Input Impedance
- Majority Carrier Device
- Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards”
Description
These are N-Channel enhancement mode silicon gate power field effect transistors designed for applications such as switching regulators, switching converters, motor drivers, relay drivers and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA17424. Symbol Packaging JEDEC TO-204AA JEDEC TO-220AB
Ordering Information
NOTE: When ordering, use the entire part number. D G S DRAIN (FLANGE) SOURCE (PIN 2) GATE (PIN 1) SOURCE DRAIN GATEDRAIN (TAB) CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper ESD Handling Procedures. Copyright © Harris Corporation 1998 File Number 1536.2 RFM7N35, RFM7N40, RFP7N35, RFP7N40 7A, 350V and 400V, 0.75 Ohm, N-Channel Power MOSFETs
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFM7N35 RFM7N40 RFP7N35 RFP7N40 UNITS Maximum Temperature for Soldering 300 260 300 260 300 260 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical SpecificationsTC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BV DSS ID = 250µA, VGS = 0V RFM7N35, RFP7N35 350 - - V RFM7N40, RFP7N40 400 - - V Gate Threshold Voltage V GS(TH) VGS = VDS , ID = 250µA (Figure 8) 2 - 4 V Zero Gate Voltage Drain Current I DSS VDS = Rated BVDSS , TC = 25oC- - 1 µA VDS = 0.8 x Rated BVDSS , TC = 125oC- - 2 5 µA Gate to Source Leakage Current I GSS VGS =±20V, VDS = 0V - - ±100 nA Drain to Source On Resistance (Note 2) rDS(ON) ID = 7A, VGS = 10V (Figures 6, 7) - - 0.75 Ω Drain to Source On Voltage (Note 2) V DS(ON) ID = 7A, VGS = 10V - - 5.25 V Turn-On Delay Time t d(ON) VDS = 200V, ID ≈ 3.5A, RG = 50Ω , R L = 56Ω , VGS = 10V (Figures 10, 11, 12) -1 6 4 5 n s Rise Time t r -5 4 7 5 n s Turn-Off Delay Time t d(OFF) - 170 250 ns Fall Time t f - 62 100 ns Input Capacitance C ISS VDS = 25V, VGS = 0V, f = 1MHz (Figure 9) - - 1600 pF Output Capacitance C OSS - - 300 pF Reverse-Transfer Capacitance C RSS - - 200 pF Thermal Resistance Junction to Case R θJC RFM7N35, RFM7N40 - - 1.25 oC/W RFP7N35, RFP7N40 - - 1.67 oC/W Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage (Note 2) VSD ISD = 7A - - 1.4 V Reverse Recovery Time t rr ISD = 7A, dISD /dt = 100A/µs - 870 - ns NOTES: 2. Pulse Test: Pulse Width≤ 300µs, duty cycle≤ 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. RFM7N35, RFM7N40, RFP7N35, RFP7N40
FIGURE 7. NORMALIZED DRAIN TO SOURCE ON FIGURE 8. NORMALIZED GATE THRESHOLD VOLTAGE vs FIGURE 9. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE NOTE: Refer to Harris Application Notes AN7254 and AN7260. FIGURE 10. NORMALIZED SWITCHING WAVEFORMS FOR
0.75 VDSS
0.25 VDSS
0.50 VDSS
FIGURE 11. SWITCHING TIME TEST CIRCUIT FIGURE 12. RESISTIVE SWITCHING WAVEFORMS