RFM75P-S2

RFM75P HOPE | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 26

Technical content

Features

/circle6 2400-2483.5 MHz ISM band operation /circle6 Support 250Kbps, 1Mbps and 2 Mbps air data rate /circle6 Programmable output power (-5dBm to +20dBm) /circle6 Tolerate +/- 60ppm 16 MHz crystal /circle6 Variable payload length from 1 to 32bytes /circle6 Automatic packet processing /circle6 6 data pipes for 1:6 star networks /circle6 1.9V to 3.6V power supply /circle6 4-pin SPI interface with maximum 8 MHz clock rate /circle6 SMD-10pin Package

Applications

/circle6 Wireless PC peripherals /circle6 Wireless gamepads /circle6 Wireless audio /circle6 Remote controls /circle6 Home automation /circle6 Toys Block Diagram

E‐ma il:sal es@hoper f.com websi te://ww w.hoper f.com Page 2 of 26 RFM75P V1.1 Table of Contents

E‐ma il:sal es@hoper f.com websi te://ww w.hoper f.com Page 3 of 26 RFM75P V1.1

1 General Description

RFM75P is a GFSK transceiver operating in the world wide ISM frequency band at 2400- 2483.5 MHz. Burst mode transmission and up to 2Mbps air data rate make them suitable for applications requiring ultra low power consumption. The embedded packet processing engines enable their full operation with a very simple MCU as a radio system. Auto re-transmission and auto acknowledge give reliable link without any MCU interference. RFM75P operates in TDD mode, either as a transmitter or as a receiver. The RF channel frequency determines the center of the channel used by RFM75P. The frequency is set by the RF_CH register in register bank 0 according to the following formula: F0= 2400 + RF_CH (MHz). The resolution of the RF channel frequency is 1MHz. A transmitter and a receiver must be programmed with the same RF channel frequency to be able to communicate with each other. The output power of RFM75P is set by the RF_PWR bits in the RF_SETUP register. Demodulation is done with embedded data slicer and bit recovery logic. The air data rate can be programmed to 250Kbps, 1Mbps or 2Mbps by RF_DR_HIGH and RF_DR_LOW register. A transmitter and a receiver must be programmed with the same setting. In the following chapters, all registers are in register bank 0 except with explicit claim. Figure 1 RFM75P Chip Block Diagram

E‐ma il:sal es@hoper f.com websi te://ww w.hoper f.com Page 4 of 26 RFM75P V1.1

2 Abbreviations

ARC Auto Retransmission Count ARD Auto Retransmission Delay CD Carrier Detection CE Chip Enable CRC Cyclic Redundancy Check CSN Chip Select Not DPL Dynamic Payload Length FIFO First-In-First-Out GFSK Gaussian Frequency Shift Keying GHz Gigahertz LNA Low Noise Amplifier IRQ Interrupt Request ISM Industrial-Scientific-Medical LSB Least Significant Bit MAX_RT Maximum Retransmit Mbps Megabit per second MCU Microcontroller Unit MHz Megahertz MISO Master In Slave Out MOSI Master Out Slave In MSB Most Significant Bit PA Power Amplifier PID Packet Identity Bits PLD Payload PRX Primary RX PTX Primary TX PWD_DWN Power Down PWD_UP Power Up RF_CH Radio Frequency Channel RSSI Received Signal Strength Indicator RX Receive RX_DR Receive Data Ready SCK SPI Clock SPI Serial Peripheral Interface TDD Time Division Duplex TX Transmit TX_DS Transmit Data Sent XTAL Crystal

E‐ma il:sal es@hoper f.com websi te://ww w.hoper f.com Page 5 of 26 RFM75P V1.1 NC C D VDD V D D V S S VDD 20 19 18 17 16 C E 1 15 VD D C S N 2 14 VSS S C K 3 R F M 7 5 P 13 RF M O SI 4 12 NC M ISO 5 11 NC 6 7 8 9 10 IR Q N C N C X O XI

3 Pin Information

RFM75P pin assignments (top view) Name Pin Function

Description

GND Ground Groun d (0 V) VDD Power Power Sup ply (3.3V to 4.2V DC) CE Digital Inpu t Chip Enable Activa tes RX or TX mode CSN Digital Inpu t SPI Chip Select, Activ e low SCK Digital Inpu t SPI Clock MOSI Digital Inpu t SPI Slave Data Inp ut MISO Digital Outpu t SPI Slave Data Output wit h tri-state option IRQ Digital Outpu t Mas kable interrupt pin, Active low TRE N Digital,Inpu t 1=TX Active 0=RX Active PAEN Digital,Inpu t 1=Chip is Active,0=chip is,Shu t-,down Table 1 RFM75P pin functions

E‐ma il:sal es@hoper f.com websi te://ww w.hoper f.com Page 6 of 26 RFM75P V1.1

4 State Control

4.1 State Control Diagram

„ Pin signal: VDD, CE „ SPI register: PWR_UP, PRIM_RX, EN_AA, NO_ACK, ARC, ARD „ System information: Time out, ACK received, ARD elapsed, ARC_CNT, TX FIFO empty, ACK packet transmitted, Packet received RFM75P has built-in state machines that control the state transition between different modes. When auto acknowledge feature is disabled, state transition will be fully controlled by MCU. Figure 3 PTX (PRIM_RX=0) state control diagram

E‐ma il:sal es@hop er f.com websi te://ww w.hoper f.com Page 7 of 26 RFM75P V1.1 Figure 4 PRX (PRIM_RX=1) state control diagram

4.2 Power Down Mode

In power down mode RFM75P is in sleep mode with minimal current consumption. SPI interface is still active in this mode, and all register values are available by SPI. Power down mode is entered by setting the PWR_UP bit in the CONFIG register to low.

4.3 Standby-I Mode

By setting the PWR_UP bit in the CONFIG register to 1 and de-asserting CE to 0, the device enters standby-I mode. Standby-I mode is used to minimize average current consumption while maintaining short start-up time. In this mode, part of the crystal oscillator is active. This is also the mode which the RFM75P returns to from TX or RX mode when CE is set low.

4.4 Standby-II Mode

In standby-II mode more clock buffers are active than in standby-I mode and much more current is used. Standby-II occurs when CE is held high on a PTX device with empty TX FIFO. If a new packet is uploaded to the TX FIFO in this mode, the device will automatically enter TX mode and the packet is transmitted.

4.5 TX Mode

„ PTX device (PRIM_RX=0) The TX mode is an active mode where the PTX device transmits a packet. To enter this mode from power down mode, the PTX device must have the PWR_UP bit set high, PRIM_RX bit set low, a payload in the TX FIFO, and a high pulse on the CE for more than 10µs.

E‐ma il:sal es@hop er f.com websi te://ww w.hoper f.com Page 8 of 26 RFM75P V1.1 The PTX device stays in TX mode until it finishes transmitting the current packet. If CE = 0 it returns to standby-I mode. If CE = 1, the next action is determined by the status of the TX FIFO. If the TX FIFO is not empty the PTX device remains in TX mode, transmitting the next packet. If the TX FIFO is empty the PTX device goes into standby-II mode. It is important to never stay in TX mode for more than 4ms at one time. If the auto retransmit is enabled (EN_AA=1) and auto acknowledge is required (NO_ACK=0), the PTX device will enter TX mode from standby-I mode when ARD elapsed and number of retried is less than ARC. „ PRX device (PRIM_RX=1) The PRX device will enter TX mode from RX mode only when EN_AA=1 and NO_ACK=0 in received packet to transmit acknowledge packet with pending payload in TX FIFO.

4.6 RX Mode

„ PRX device (PRIM_RX=1) The RX mode is an active mode where the RFM75P radio is configured to be a receiver. To enter this mode from standby-I mode, the PRX device must have the PWR_UP bit set

5 Packet Processing

high, PRIM_RX bit set high and the CE pin set high. Or PRX device can enter this mode from TX mode after transmitting an acknowledge packet when EN_AA=1 and NO_ACK=0 in received packet. In this mode the receiver demodulates the signals from the RF channel, constantly presenting the demodulated data to the packet processing engine. The packet processing engine continuously searches for a valid packet. If a valid packet is found (by a matching address and a valid CRC) the payload of the packet is presented in a vacant slot in the RX FIFO. If the RX FIFO is full, the received packet is discarded. The PRX device remains in RX mode until the MCU configures it to standby-I mode or power down mode. In RX mode a carrier detection (CD) signal is available. The CD is set to high when a RF signal is detected inside the receiving frequency channel. The internal CD signal is filtered before presented to CD register. The RF signal must be present for at least 128 µs before the CD is set high. „ PTX device (PRIM_RX=0) The PTX device will enter RX mode from TX mode only when EN_AA=1 and NO_ACK=0 to receive acknowledge packet.

5.1 Packet Format

The packet format has a preamble, address, packet contr ol, payload and CRC field. Preamble1byte Address3~5byte Packet C o n tr o l 9/0bit Payload0~32byte CRC2/1byte PayloadLength6bit PID2bit NO_ACK1bit Figure 5 Packet Format

E‐ma il:sal es@hop er f.com websi te://ww w.hoper f.com Page 9 of 26 RFM75P V1.1 5.1.1 Preamble The preamble is a bit sequence used to detect 0 and 1 levels in the receiver. The preamble is one byte long and is either 01010101 or 10101010. If the first bit in the address is 1 the preamble is automatically set to 10101010 and if the first bit is 0 the preamble is automatically set to 01010101. This is done to ensure there are enough transitions in the preamble to stabilize the receiver.

5.1.2 Address

This is the address for the receiver. An address ensures that the packet is detected by the target receiver. The address field can be configured to be 3, 4, or 5 bytes long by the AW register. The PRX device can open up to six data pipes to support up to six PTX devices with unique addresses. All six PTX device addresses are searched simultaneously. In PRX side, the data pipes are enabled with the bits in the EN_RXADDR register. By default only data pipe 0 and 1 are enabled. Each data pipe address is configured in the RX_ADDR_PX registers. Each pipe can have up to 5 bytes configurable address. Data pipe 0 has a unique 5 byte address. Data pipes 1-5 share the 4 most significant address bytes. The LSB byte must be unique for all 6 pipes. To ensure that the ACK packet from the PRX is transmitted to the correct PTX, the PRX takes the data pipe address where it received the packet and uses it as the TX address when transmitting the ACK packet. On the PRX, the RX_ADDR_Pn, defined as the pipe address, must be unique. On the PTX the TX_ADDR must be the same as the RX_ADDR_P0 on the PTX, and as the pipe address for the designated pipe on the PRX. No other data pipe can receive data until a complete packet is received by a data pipe that has detected its address. When multiple PTX devices are transmitting to a PRX, the ARD can be used to skew the auto retransmission so that they only block each other once.

5.1.3 Packet Control

When Dynamic Payload Length function is enabled, the packet control field contains a 6 bit payload length field, a 2 bit PID (Packet Identity) field and, a 1 bit NO_ACK flag. „ Payload length The payload length field is only used if the Dynamic Payload Length function is enabled. „ PID The 2 bit PID field is used to detect whether the received packet is new or retransmitted. PID prevents the PRX device from presenting the same payload more than once to the MCU. The PID field is incremented at the TX side for each new packet received through the SPI. The PID and CRC fields are used by the PRX device to determine whether a packet is old or new. When several data packets are lost on the link, the PID fields may become equal to the last received PID. If a packet has the same PID as the previous packet, RFM75P compares the CRC sums from both packets. If the CRC sums are also equal, the last received packet is considered a copy of the previously received packet and discarded. „ NO_ACK The NO_ACK flag is only used when the auto acknowledgement feature is used. Setting the flag high, tells the receiver that the packet is not to be auto acknowledged. The PTX can set the NO_ACK flag bit in the Packet Control Field with the command: W_TX_PAYLOAD_NOACK. However, the function must first be enabled in the FEATURE register by setting the

E‐ma il:sal es@hop er f.com websi te://ww w.hoper f.com Page 10 of 26 RFM75P V1.1 EN_DYN_ACK bit. When you use this option, the PTX goes directly to standby-I mode after transmitting the packet and the PRX does not transmit an ACK packet when it receives the packet.

5.1.4 Payload

The payload is the user defined content of the packet. It can be 0 to 32 bytes wide, and it is transmitted on-air as it is uploaded (unmodified) to the device. The RFM75P provides two alternatives for handling payload lengths, static and dynamic payload length. The static payload length of each of six data pipes can be individually set. The default alternative is static payload length. With static payload length all packets between a transmitter and a receiver have the same length. Static payload length is set by the RX_PW_Px registers. The payload length on the transmitter side is set by the number of bytes clocked into the TX_FIFO and must equal the value in the RX_PW_Px register on the receiver side. Each pipe has its own payload length. Dynamic Payload Length (DPL) is an alternative to static payload length. DPL enables the transmitter to send packets with variable payload length to the receiver. This means for a system with different payload lengths it is not necessary to scale the packet length to the longest payload. With DPL feature the RFM75P can decode the payload length of the received packet automatically instead of using the RX_PW_Px registers. The MCU can read the length of the received payload by using the command: R_RX_PL_WID. In order to enable DPL the EN_DPL bit in the FEATURE register must be set. In RX mode the DYNPD register has to be set. A PTX that transmits to a PRX with DPL enabled must have the DPL_P0 bit in DYNPD set.

5.1.5 CRC

The CRC is the error detection mechanism in the packet. The number of bytes in the CRC is set by the CRCO bit in the CONFIG register. It may be either 1 or 2 bytes and is calculated over the address, Packet Control Field, and Payload. The polynomial for 1 byte CRC is X 8 + X2 + X + 1. Initial value is 0xFF. The polynomial for 2 byte CRC is X 16 + X12 + X5 + 1. Initial value is 0xFFFF. No packet is accepted by receiver side if the CRC fails.

5.2 Packet Handling

RFM75P uses burst mode for payload transmission and receive. The transmitter fetches payload from TX FIFO, automatically assembles it into packet and transmits the packet in a very short burst period with 1Mbps or 2Mbps air data rate. After transmission, if the PTX packet has the NO_ACK flag set, RFM75P sets TX_DS and gives an active low interrupt IRQ to MCU. If the PTX is ACK packet, the PTX needs receive ACK from the PRX and then asserts the TX_DS IRQ. The receiver automatically validates and disassembles received packet, if there is a valid packet within the new payload, it will write the payload into RX FIFO, set RX_DR and give an active low interrupt IRQ to MCU. When auto acknowledge is enabled (EN_AA=1), the PTX devicewill automatically wait for acknowledge packet after transmission, and re-transmit original packet with the delay of ARD until an acknowledge packet is received or the number of re-transmission exceeds a threshold ARC. If the later one happens, RFM75P will set MAX_RT and give an active low interrupt

E‐ma il:sal es@hop er f.com websi te://ww w.hoper f.com Page 11 of 26 RFM75P V1.1 IRQ to MCU. Two packet loss counters (ARC_CNT and PLOS_CNT) are incremented each time a packet is lost. The ARC_CNT counts the number of retransmissions for the current transaction. The PLOS_CNT counts the total number of retransmissions since the last channel change. ARC_CNT is reset by initiating a new transaction. PLOS_CNT is reset by writing to the RF_CH register. It is possible to use the information in the OBSERVE_TX register to make an overall assessment of the channel quality. The PTX device will retransmit if its RX FIFO is full but received ACK frame has payload. As an alternative for PTX device to auto retransmit it is possible to manually set the RFM75P to retransmit a packet a number of times. This is done by the REUSE_TX_PL command. When auto acknowledge is enabled, the PRX device will automatically check the NO_ACK field in received packet, and if NO_ACK=0, it will automatically send an acknowledge packet to PTX device. If EN_ACK_PAY is set, and the acknowledge packet can also include pending payload in TX FIFO.

6 Data and Control Interface

6.1 TX/RX FIFO

The data FIFOs are used to store payload that is to be transmitted (TX FIFO) or payload that is received and ready to be clocked out (RX FIFO). The FIFO is accessible in both PTX mode and PRX mode. There are three levels 32 bytes FIFO for both TX and RX, supporting both acknowledge mode or no acknowledge mode with up to six pipes. „ TX three levels, 32 byte FIFO „ RX three levels, 32 byte FIFO Both FIFOs have a controller and are accessible through the SPI by using dedicated SPI commands. A TX FIFO in PRX can store payload for ACK packets to three different PTX devices. If the TX FIFO contains more than one payload to a pipe, payloads are handled using the first in first out principle. The TX FIFO in a PRX is blocked if all pending payloads are addressed to pipes where the link to the PTX is lost. In this case, the MCU can flush the TX FIFO by using the FLUSH_TX command. The RX FIFO in PRX may contain payload from up to three different PTX devices. A TX FIFO in PTX can have up to three payloads stored. The TX FIFO can be written to by three commands, W_TX_PAYLOAD and W_TX_PAYLOAD_NO_ACK in PTX mode and W_ACK_PAYLOAD in PRX mode. All three commands give access to the TX_PLD register. The RX FIFO can be read by the command R_RX_PAYLOAD in both PTX and PRX mode. This command gives access to the RX_PLD register. The payload in TX FIFO in a PTX is NOT removed if the MAX_RT IRQ is asserted. In the FIFO_STATUS register it is possible to read if the TX and RX FIFO are full or empty. The TX_REUSE bit is also available in the FIFO_STATUS register. TX_REUSE is set by the SPI command REUSE_TX_PL, and is reset by the SPI command: W_TX_PAYLOAD or FLUSH TX.

6.2 Interrupt

In RFM75P there is an active low interrupt (IRQ) pin, which is activated when TX_DS IRQ, RX_DR IRQ or MAX_RT IRQ are set high by the state machine in the STATUS register. The IRQ pin resets when MCU writes '1' to the IRQ source bit in the STATUS register. The IRQ mask in the CONFIG

E‐ma il:sal es@hoper f.com websi te://ww w.hoper f.com Page 12 of 26 RFM75P V1.1 register is used to select the IRQ sources that are allowed to assert the IRQ pin. By setting one of the MASK bits high, the corresponding IRQ source is disabled. By default all IRQ sources are enabled. The 3 bit pipe information in the STATUS register is updated during the IRQ pin high to low transition. If the STATUS register is read during an IRQ pin high to low transition, the pipe information is unreliable.

6.3 SPI Interface

6.3.1 SPI Command

The SPI commands are shown in Table 3. Every new command must be started by a high to low transition on CSN. In parallel to the SPI command word applied on the MOSI pin, the STATUS register is shifted serially out on the MISO pin. The serial shifting SPI commands is in the following format: „ <Command word: MSB bit to LSB bit (one byte)> „ <Data bytes: LSB byte to MSB byte, MSB bit in each byte first> for all registers at bank 0 and register 9 to register 14 at bank 1 „ <Data bytes: MSB byte to LSB byte, MSB bit in each byte first> for register 0 to register 8 at bank 1 Command name Command word (binary) # Data bytes Operation R_REGISTER 000A AAAA 1 to 5 LSB byte first Read com mand and sta tus reg isters. AA AAA = 5 bit Register Map Address W_REGISTER 001A AAAA 1 to 5 LSB byte first Write command and stat us reg isters . AA AAA = 5 bit Register Map Address Executable in power down or standby modes only. R_RX_PAYLOAD 0110 0001 1 to 32 LSB byte first Read RX -pa ylo ad: 1 – 32 byte s. A read opera tion always starts at byte 0. Payload is deleted from FIFO after it is read. Used in RX mode. W_TX_PAYLOAD 1010 0000 1 to 32 LSB byte first Write TX-paylo ad: 1 – 32 byte s. A write operation always starts at byte 0 used in TX payload. FLUSH_TX 1110 0001 0 Flu sh TX FI FO, us ed in TX mo de FLUSH_RX 1110 0010 Flu sh RX FI FO , used in RX mode Should not be executed during transmission of acknowledge, that is, acknowledge package will not be completed. REUSE_TX_PL 1110 0011 Used for a PTX de vice Reuse last transmitted payload. Packets are repeatedly retransmitted as long as CE is high. TX payload reuse is active until W_TX_PAYLOAD or FLUSH TX is executed. TX payload reuse must not be activated or deactivated during package transmission

E‐ma il:sal es@hoper f.com websi te://ww w.hoper f.com Page 13 of 26 RFM75P V1.1 ACTIVATE 0101 0000 This write com mand followed by data 0x73 activ ates the following features:

• R_RX_PL_WID
• W_ACK_PAYLOAD
• W_TX_PAYLOAD_NOACK A new ACTIVATE command with the same data deactivates them again. This is executable in power down or stand by modes only. The R_RX_PL_WID, W_ACK_PAYLOAD, and W_TX_PAYLOAD_NOACK features registers are initially in a deactivated state; a write has no effec t, a read only results in zeros on MISO. To activate these registers, use the ACTIVATE command followed by data 0x73. Then they can be accessed as any other register. Use the same command and data to deactivate the registers again. This write command followed by data 0x53 toggles the register bank, and the current register bank number can be read out from REG7 [7] R_RX_PL_WID 0110 0000 Read RX -pa ylo ad width for the top R_RX_PAYLOAD in the RX FIFO. W_ACK_PAYLOAD 1010 1PPP 1 to 32 LSB byte first Used in RX mod e. Write Payload to be transmitted together with ACK packet on PIPE PPP. (PPP valid in the range from 000 to 101). Maximum three ACK packet payloads can be pending. Payloads with same PPP are handled using first in - first out principle. Write payload: 1– 32 bytes. A write operation always starts at byte 0. W_TX_PAYLOAD_NO ACK 1011 0000 1 to 32 LSB byte first Used in TX mode. Di sables AU TOACK on this specific packet. NOP 1111 1111 0 No Operat ion. Might be used to read the STATUS register Table 2 SPI command

6.3.2 SPI Timing

W r i t e t o S P I r e g i s t e r: x C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 x D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 x M I S O H I - Z S 7 S 6 S 5 S 4 S 3 S 2 S 1 S 0 0 0 0 0 0 0 0 0 H i - Z R e a d f r o m S P I r e g i s t e r: M O S I x C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 x M I S O x S 7 S 6 S 5 S 4 S 3 S 2 S 1 S 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 x Figure 6 SPI timing

E‐ma il:sal es@hoper f.com websi te://ww w.hoper f.com Page 14 of 26 RFM75P V1.1 Cn: SPI command bit Sn: STATUS register bit Dn: Data Bit (LSB byte to MSB byte, MSB bit in each by te first) Note: The SPI timing is for bank 0 and register 9 to 14 at ba nk 1. For register 0 to 8 at bank 1, the byte order is inversed that the MSB byte is R/W before LSB byte. Figure 7 SPI NOP timing diagram Sym bol Parameters Min Max Units Tdc Data to SC K Setu p 10 ns Tdh SCK to Data Hold 20 ns Tcsd CSN to Data Valid 38 ns Tcd SCK to Data Valid 55 ns Tcl SCK Low Time 40 ns Tch SCK High Tim e 40 ns Fsc k SCK Frequency 0 8 MHz Tr,Tf SCK Rise and Fall 100 ns Tcc CSN to SC K Se tu p 2 ns Tcch SCK to CSN Ho ld 2 ns Tc wh CSN Inacti ve time 50 ns Tcdz CSN to Output High Z 38 ns Table 3 SPI timing parameter

E‐ma il:sal es@hoper f.com websi te://ww w.hoper f.com Page 15 of 26 RFM75P V1.1

7 Register Map

There are two register banks, which can be toggled by S PI command “ACTIVATE” followed with 0x53 byte, and bank status can be read from Bank0_REG7 [7].

7.1 Register Bank 0

(Hex) Mnemonic Bit Reset Value Type

00 CONFIG Con figuration Reg ister

Reser ved 7 0 R/W Only '0' allowe d MASK_ RX_DR 6 0 R/W Mask interru pt cau sed by RX_DR 1: Interrupt not reflected on the IRQ pin 0: Reflect RX_DR as active low interrupt on the IRQ pin MASK_ TX_DS 5 0 R/W Mask interru pt cau sed by TX_DS 1: Interrupt not reflected on the IRQ pin 0: Reflect TX_DS as active low interrupt on the IRQ pin MASK_ MAX _RT 4 0 R/W Mask inter rupt cau sed by MAX_ RT 1: Interrupt not reflected on the IRQ pin 0: Reflect MAX_RT as active low interrupt on the IRQ pin EN_CRC 3 1 R/W Enable CRC. Fo rced high if one of the bits in the EN_AA is high CR CO 2 0 R/W CRC encoding sch eme '0' - 1 byte '1 ' - 2 byte s PW R_UP 1 0 R/W 1: PO WER UP, 0:PO WER DOWN PRIM_RX 0 0 R/W RX /T X co ntrol, 1: PRX, 0: PTX

01 EN_AA Enable ‘Auto Acknowledgment’ Function

Reser ved 7:6 00 R/W On ly '00' allowe d ENA A_P5 5 1 R/W Enable auto acknowl edge ment data pipe 5 ENA A_P4 4 1 R/W Enable auto acknowledge ment data pipe 4 ENA A_P3 3 1 R/W Enable auto acknowledge ment data pipe 3 ENA A_P2 2 1 R/W Enable auto acknowledge ment data pipe 2 ENA A_P1 1 1 R/W Enable auto acknowledge ment data pipe 1 ENA A_P0 0 1 R/W Enable auto acknowledge ment data pipe 0

02 EN_ RXADDR Enabled RX Add re sses

Reser ved 7:6 00 R/W On ly '00' allowe d ERX_ P5 5 0 R/W Enable data pi pe 5. ERX_ P4 4 0 R/W Enable data pi pe 4. ERX_ P3 3 0 R/W Enable data pi pe 3. ERX_P2 2 0 R/W Enable data pi pe 2. ERX_ P1 1 1 R/W Enable data pi pe 1. ERX_ P0 0 1 R/W Enable data pi pe 0.

E‐ma il:sal es@hoper f.com websi te://ww w.hoper f.com Page 16 of 26 RFM75P V1.1

03 SE TUP_AW Setup of Address Widt hs

(common for all data pipes) Reserved 7:2 000000 R/W Only '0 00000' allowe d AW 1:0 11 R/W RX /T X Addre ss field widt h '00' - Illegal '01' - 3 bytes '10' - 4 bytes '11' - 5 bytes LSB bytes are used if address width is bel ow 5 bytes

04 SE TUP_RE TR Setup of Automatic Retra nsmis sion

ARD 7:4 0000 R/W Auto Re tran smission Dela y ‘0000’ – Wait 250 us ‘0001’ – Wait 500 us ‘0010’ – Wait 750 us …….. ‘1111’ – Wait 4000 us (Delay defined from end of transmission to start of ne xt transmis sion) ARC 3:0 0011 R/W Auto Ret ran smis sion Count ‘0000’ –Re-Transmit disabled ‘0001’ – Up to 1 Re-Transmission on fail of AA ‘1111’ – Up to 15 Re-Transmission on fail of AA

05 RF_ CH RF Chann el

Reser ved 7 0 R/W Only '0' allowe d RF_ CH 6:0 00000 10 R/W Sets the freque nc y chann el

06 RF_SETUP RF Setup Re gister

Reser ved 7:6 0 R/W On ly '00' allowe d RF_DR_LOW 5 0 R/W Set Air Data Ra te. See RF_D R_HI GH for encoding. PLL_LO CK 4 0 R/W Force PLL lock sign al. Only used in test RF_DR_HIGH R/W Set Air Data Rate. Encoding: RF_DR_LOW, RF_DR_HIGH: ‘00’ – 1Mbps ‘01’ – 2Mbps (default) ‘10’ – 250Kbps ‘11’ – 2Mbps RF_PWR[1:0] 2:1 R/W Set RF output power in TX mode RF_PWR[1:0] LNA_HCURR R/W Setup LNA gain 0:Low gain(20dB down) 1:High ga in STATUS Status Re gister (In par allel to the SPI command word applied on the MOSI pin, the STATUS register is shifted serially out on the MISO pin) RBANK R Regi ster bank selec tion state s. Switc h register bank is done by SPI command “ACTIVATE” followed by 0x53 0: Register bank 0

E‐ma il:sal es@hoper f.com websi te://ww w.hoper f.com Page 17 of 26 RFM75P V1.1 1: Register bank 1 RX_ DR 6 0 R/W Data Rea dy RX FI FO in te rr upt Asserted when new data arrives RX FIFO Write 1 to clear bit. TX_DS 5 0 R/W Data Sent TX FIFO in te rrupt Asserted when packet transmitted on TX. If AUTO_ACK is activated, this bit is set high only when ACK is received. Write 1 to clear bit. MAX_RT R/W Maxi mum number of TX retra nsmits interrupt Write 1 to clear bit. If MAX_RT is asserted it must be cleared to ena ble further communication. RX_P_NO 3:1 111 R Data pipe nu mber for the payload available for reading from RX_FIFO 000-101: Data Pipe Number 110: Not used 111: RX FI FO Empt y TX_FU LL 0 0 R TX FIFO full flag . 1: TX FIFO full 0: Ava ilab le locations in TX FIFO

08 OBSERVE_TX Trans mit obser ve register

PLOS_CNT 7:4 0000 R Count lost packet s. The counter is overflow protected to 15, and discontinues at max until reset. The counter is reset by writing to RF_CH. ARC_CNT 3:0 0000 R Count retra nsmitted pac ket s. The cou nter is reset when transmission of a new pac ket s ta rts. 09 CD Reser ved 7:1 000 000 R CD 0 0 R Carr ier Dete ct 0A RX_ADDR_P0 39:0 0xE7E7E 7E7E7 R/W Rec eive addr ess data pipe 0. 5 Bytes maximum length. (LSB byte is written first. Write the number of bytes defined by SETUP _A W) 0B RX_ADDR_P1 39:0 0xC2C2C 2C2C2 R/W Rec eive addr ess data pipe 1. 5 Bytes maximum length. (LSB byte is written first. Write the number of bytes defined by SETUP _A W) 0C RX_ADDR_P2 7:0 0xC3 R/W Rec eive addr ess data pipe 2. Only LSB MSB bytes is equal to RX_ADD R_P 1[39:8] 0D RX_ADDR_P3 7:0 0xC4 R/W Rec eive addr ess data pipe 3. Only LSB MSB bytes is equal to RX_ADD R_P 1[39:8] 0E RX_ADDR_P4 7:0 0xC5 R/W Rec eive addr ess data pipe 4. On ly LSB. MSB bytes is equal to RX_ADD R_P 1[39:8] RX_ADDR_P5 7:0 0xC6 R/W Rec eive addr ess data pipe 5. Only LSB. MSB bytes is equal to RX_ADD R_P 1[39:8]

10 TX_ADDR 39:0 0xE7 E7E

R/W Trans mit add ress. Used for a PT X de vice only.

E‐ma il:sal es@hoper f.com websi te://ww w.hoper f.com Page 18 of 26 RFM75P V1.1 (LSB by te is writte n first) Set RX_ADDR_P0 equal to this address to handle automatic acknowledge if this is a PTX de vice

11 RX_ PW_P0

Reser ved 7:6 00 R/W On ly '00' allowe d RX_PW_P0 5:0 000000 R/W Number of bytes in RX payload in data pipe 0 (1 to 32 bytes). 0: not used 1 = 1 byte 32 = 32 bytes

12 RX_P W_P1

Reser ved 7:6 00 R/W On ly '00' allowe d RX_PW_P1 5:0 000000 R/W Number of bytes in RX payload in data pipe 1 (1 to 32 bytes). 0: not used 1 = 1 byte 32 = 32 bytes

13 RX_P W_P2

Reser ved 7:6 00 R/W On ly '00' allowe d RX_PW_P2 5:0 000000 R/W Number of bytes in RX payload in data pipe 2 (1 to 32 bytes). 0: not used 1 = 1 byte 32 = 32 bytes

14 RX_P W_P3

Reser ved 7:6 00 R/W On ly '00' allowe d RX_PW_P3 5:0 000000 R/W Number of bytes in RX payload in data pipe 3 (1 to 32 bytes). 0: not used 1 = 1 byte 32 = 32 bytes

15 RX_P W_P4

Reser ved 7:6 00 R/W Only '00' allowe d RX_PW_P4 5:0 000000 R/W Number of bytes in RX payload in data pipe 4 (1 to 32 bytes). 0: not used 1 = 1 byte 32 = 32 bytes

16 RX_P W_P5

Reser ved 7:6 00 R/W On ly '00' allowe d RX_PW_P5 5:0 000000 R/W Number of bytes in RX payload in data pipe 5 (1 to 32 bytes). 0: not used 1 = 1 byte 32 = 32 bytes

E‐ma il:sal es@hoper f.com websi te://ww w.hoper f.com Page 19 of 26 RFM75P V1.1

17 FIFO _STATU S FIFO Status Re gister

Reser ved 7 0 R/W Only '0' allowe d TX_REUSE R Reuse last tr ansmi tted data packet if set high. The packet is repeatedly retransmitted as long as CE is high. TX_REUSE is set by the SPI command REUSE_TX_PL, and is reset by the SPI command W_TX_PAYLOAD or FLUSH TX TX_FULL 5 0 R TX FIFO full flag 1: TX FIFO full; 0: Available locations in TX FIFO TX_EMPTY R TX FIFO empty flag. 1: TX FIFO empty 0: Data in TX FIFO Reser ved 3:2 00 R/W On ly '00' allowe d RX_FULL R RX FIFO full flag 1: RX FIFO full 0: Ava ilab le locations in RX FI FO RX_EMPTY R RX FIFO empty flag 1: RX FIFO empty 0: Data in RX FI FO N/A ACK_PLD 255:0 X W Written by sepa rate SPI co mmand ACK packet payload to data pipe number PPP given in SPI command Used in RX mode only Maximum three ACK packet payloads can be pending. Payloads with same PPP are handl ed first in first ou t. N/A TX_PLD 255:0 X W Written by sepa rate SPI co mmand TX data pay-load register 1 - 32 bytes. This register is implemented as a FIFO with three levels. Used in TX mode only N/A RX_PL D 25 5:0 X R Read by separate SPI comman d RX data payload register. 1 - 32 bytes. This register is implemented as a FIFO with three levels. All RX chann els share the sa me FIFO . 1C DYN PD Enable dyna mic payload length Reser ved 7:6 0 R/W Only ‘00’ allo wed DPL_P5 5 0 R/W Enable dyna mic pa yload len gth data pip e (R equ ires EN_DPL and ENA A_P5) DPL_P4 4 0 R/W Enable dyna mic pa yload len gth data pip e (R equ ires EN_DPL and ENA A_P4) DPL_P3 3 0 R/W Enable dyna mic pa yload len gth data pip e (R equ ires EN_DPL and ENA A_P3) DPL_P2 2 0 R/W Enable dyna mic pa yload len gth data pip e (R equ ires EN_DPL and ENA A_P2) DPL_P1 1 0 R/W Enable dyna mic pa yload len gth data pipe (R equ ires EN_DPL and ENA A_P1) DPL_P0 0 0 R/W Enable dyna mic pa yload len gth data pip e

E‐ma il:sal es@hoper f.com websi te://ww w.hoper f.com Page 20 of 26 RFM75P V1.1 (Requ ires EN_D PL and ENAA _P0) 1D FEA TURE R/W Feature Register Reser ved 7:3 0 R/W Only ‘00 000’ allowed EN_DPL 2 0 R/W Enables Dynamic Pa yload Leng th EN_A CK_ PAY 1 0 R/W Enables Pay load with ACK EN_DYN_ACK 0 0 R/W Enables the W_ TX_PAYLOAD_NOACK command Note: Don’t write reserved registers and registers at other addresses in regi ster bank 0 Table 4 Register Bank 0

E‐ma il:sal es@hoper f.com websi te://ww w.hoper f.com Page 21 of 26 RFM75P V1.1

7.2 Register Bank 1

(He x) Mne monic Bit Reset Va lue Type Des cript ion 00 31:0 0 W Must write with 0x404 B01E 2 01 31:0 0 W Must write with 0xC04B0000 02 31:0 0 W Must write with 0xD0FC8 C02 31:0 03001200 W Must write with 0x99003921 31:0 W Must wr ite with 1Msps：0xF996821B 2Msps: 0xF99682DB 250ksps：0xF9968ADB For single carrier mode:0xF9968221 31:0 W Must wr ite with 1Msps ：0x24060FA6(Disable RSSI) 2Msps ：0x 24060FB6(Disable RSSI) 250ksps:0x24060FB6(Disable RSSI) RSSI_EN W RSSI measurement: 0:Enable 1:Disa ble 06 31:0 0 W Reser ved 07 31:0 0 W Reser ved RBANK R Register bank selection stat es. Switch register bank is done by SPI command “ACTIVATE” followed by 0x53 0: Register bank 0 1: Re gister bank 1 Chip ID 31:0 R BEK EN Chip ID: 0x00000063(RFM75P) 09 0 Reser ved 0A 0 Reser ved 0B 0 Reser ved 31:0 W Plea se initialize with 0x 0573 1200 For 120us mode:0x00731200 26:2 4 101 PLL Settling time: 101:130us 000:1 20us 9 1 Compatible mod e: 0:Static compatible 1:D ynamic co mpatible 0D NEW_FEA TURE 31:0 0 Plea se initialize with 0x00 80B436 0E RAMP 87:0 NA W Ramp cu rv e Please write with 0x FFF FFEF 7CF20810 4082 041 Note: Don’t write reserved registers and no definition registers in regist er bank 1 Table 5 Register Bank 1

E‐ma il:sal es@hoper f.com websi te://ww w.hoper f.com Page 22 of 26 RFM75P V1.1

8 Electrical Specifications

Name Paramet er (Condit ion) Min Typic al Max Unit Comm ent Operating Condi tion VDD Voltage 1.9 3.0 3.6 V TE MP Te mperatu re -40 +27 +85 ºC Di gita l inpu t Pin VIH High level 0.7V DD VD D+0. 7 V VI L Low level VSS 0.3V DD V Di gita l outpu t Pin VOH High level (IOH =-0.25mA) VDD- 0.3 VDD V VOL Low level(IO L=0.25 mA ) 0 0.3 V Nor mal cond ition IVDD Power Down cur ren t 4 uA IVDD Standb y-I curre nt 50 uA IVDD Standb y-II cu rre nt 300 uA No rmal RF condit ion FOP Oper ating fr equ enc y 2400 2527 MHz FXTA L Cr ystal freque ncy 16 MHz RF SK Air data ra te 250 2000 Kbps Tr an smi tter PRF Output powe r 20 dBm PBW Modul ati on 20 dB ba ndwidt h(2Mbps) TBD MHz PBW Modul ati on 20 dB ban dwidth (1Mbps) TBD MHz PBW Modul ati on 20 dB ban dwidth (25 0Kbp s) TBD KHz IVDD Cu rr ent at 20 dBm ou tp ut pow er 130 mA Rec eiver IVDD Cur ren t (2Mbps) 27 mA IVDD Current (1Mbps) 26 mA IVDD Current (25 0Kbps ) 26 mA Max Inp ut 1 E-3 BER 10 dBm RXSEN S 1 E-3 BER sensitivity (2Mbp s) -98 dBm RXSEN S 1 E-3 BER sensitivity (1Mbp s) -101 dBm RXSEN S 1 E-3 BER se nsitivi ty (250K bps) -106 dBm Table 6 Electrical Specifications

E‐ma il:sal es@hoper f.com websi te://ww w.hoper f.com Page 23 of 26 RFM75P V1.1

9 Typical Application Schematic

Figure 8 RFM75P typical application schematic

E‐ma il:sal es@hoper f.com websi te://ww w.hoper f.com Page 24 of 26 RFM75P V1.1 Figure 9 RFM75P SMD PACKAGE

E‐ma il:sal es@hoper f.com websi te://ww w.hoper f.com Page 25 of 26 RFM75P V1.1

11 Order Information

12 Solder Information

„ Solder Method: Not supported reflow soldering, recommend to use hand solder . „ The Selection of Soldering tools According to both our soldering experiment a nd customers’ feedback, we don’t find that it results in obvious ef fect on soldering and products’ fuctions by using open soldering pens(i.e. c ommon soldering pens without closed-loop temperature control). H owever, considering the requirements of lead-free soldering and i ts productivity improvement, we suggest that you should use thermostatic soldering pen with closed-loop temperature control and select appropriate solder tip. Please kindly note t hat big solder tips, according to the feedback from customers, obviously bring about low efficiency of soldering and increase the poss ibility of short- circuit. „ The Selection of Soldering Materials ——Sn96.5%/Ag3.0%/Cu0.5% ——Sn96.5%/Ag3.5% The wireless modules we provide are green products in c omplete accordance with the lead-free requirement; therefore, we suggest you should use environment-friendly lead-free sol dering tin. We recommend two alloyed soldering tins as below to match the no- clean rosin(core and additive rosin): ——Sn96.5%/Ag3.0%/Cu0.5% ——Sn96.5%/Ag3.5%

E‐ma il:sal es@hoper f.com websi te://ww w.hoper f.com Page 26 of 26 RFM75P V1.1

13 Contact Information

HOPE MICROELECTRONICS CO.,LTD Add: 2/F, Building 3, Pingshan Private Enterprise Science and Technology Park, Lishan Road, XiLi Town, Nanshan District, Shenzhen, Guangdong, China Tel: 86-755-82973805 Fax: 86-755-82973550 Email: sales@hoperf.com Website: http://www.hoperf.com HOPE MICROELECTRONICS CO.,LTD Add: 2/F, Building 3, Pingshan Private Enterprise Science and Technology Park, Lishan Road, XiLi Town, Nanshan District, Shenzhen, Guangdong, China Tel: 86-755-82973805 Fax: 86-755-82973550 Email: sales@hoperf.com Website: http://www.hoperf.com http://www.hoperf.cn This document may contain preliminary information and is subject to change by Hope Microelectronics without notice. Hope Microelectronics assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of Hope Microelectronics or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in the direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MECHANTABILITY OR FITNESS FOR A ARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT. ©2006, HOPE MICROELECTRONICS CO.,LTD. All rights reserved.