RFM66W-868S2

RFM66W HOPE | Alldatasheet

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Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W RFM66W IS M TRANSCEIVE R MODUL E v1.0 868 & 915MHz Ultra Low Power High Link Budget Integrated UHF Transceiver GENERAL DESCRIPTION TAL The RFM66W is a fully integrated ISM band transceiver o ptimized for use in the (EN 300 220-1) 868 MHz band in Europe and the (FCC Part 15) 915 MHz band in the US with a minimum of external components. It offers a combination of high link budget and low current consumption in all operating modes. The 143 dB link budget is achieved by a low noise CMOS receiver front end and up to +20 dBm of transmit output power. A pair of internal power amplifiers are provided permitting either fully regulated - for constant RF p erformance, or direct supply connection - for optimal e fficiency. This makes RFM66W ideal for either M2M a pplications powered by al kaline battery chemistries or long battery life metering applications using Lithium battery chemistries. The Low-IF architecture of the RFM66W sees fast transceiver start times and demodulation p redicated towards low m odulation index and gaussian filtered spectrally efficient modulation formats. KEY PRODUCT FEATURES  +20 dBm - 100 mW Constant RF output vs. Vsupply  +14 dBm high efficiency PA  Programmable bit rate up to 300kbps  High Sensitivity: down to -123 dBm at 1.2 kbps  Bullet-proof front end: IIP3 = -12 dBm  80 dB Blocking Immunity  Low RX current of 9.3 mA, 100nA register retention  Fully integrated synthesizer with a resolution of 61 Hz  FSK, GFSK, MSK, GMSK and OOK modulations  Built-in Bit Synchronizer performing Clock Recovery  Sync Word Recognition  Preamble detection  io-homecontrol® compatibility mode  115 dB+ Dynamic Range RSSI  Automatic RF Sense with ultra-fast AFC  Packet engine up to 64 bytes with CRC  Built-in temperature sensor and Low Battery indicator

APPLICATIONS

 Wireless Sensor Networks  Automated Meter Reading  Home and Building Automation  Wireless Alarm and Security Systems  Industrial Monitoring and Control  Module Size:19.7X16mm RFM66W

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Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET 3.5.8. Bit Synchronizer 34

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Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET Acronyms BOM Bill Of Materials LSB Least Significant Bit BR Bit Rate MSB Most Significant Bit BW Bandwidth NRZ Non Return to Zero CCITT Comité Consultatif International Té lé phonique et Télégraphique - ITU OOK On Off Keying CRC Cyclic Redundancy Check PA Power Amplifier DAC Digital to Analog Converter PCB Printed Circuit Board ETSI European Telecommunications Standards Institute PLL Phase-Locked Loop FCC Federal Communications Commission POR Power On Reset Fdev Frequency Deviation RBW Resolution BandWidth FIFO First In First Out RF Radio Frequency FIR Finite Impulse Response RSSI Received Signal Strength Indicator FS Frequency Synthesizer Rx Receiver FSK Frequency Shift Keying SAW Surface Acoustic Wave GUI Graphical User Interface SPI Serial Peripheral Interface IC Integrated Circuit SR Shift Register ID IDentificator Stby Standby IF Intermediate Frequency Tx Transmitter IRQ Interrupt ReQuest uC Microcontroller ITU International Telecommunication Union VCO Voltage Controlled Oscillator LFSR Linear Feedback Shift Register XO Crystal Oscillator LNA Low Noise Amplifier XOR eXclusive OR LO Local Oscillator

Semtech website for the latest updates or errata. The RFM66W is a single-chip integrated circuit ideally suited for today's high performance ISM band RF applications.

32 MHz

Figure 1. Block Diagram

The following diagram shows the pin arrangement of the top view. Figure 3. Marking Diagram

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W 1.3. Pin Description Table 1 RFM66W Pinouts Number Name Type

Description

Description Stand Alone Mode

1 GND -

2 MISO I

3 MOSI O

4 SCK

I SPI Clock input

5 NSS I

6 RESET I/O

7 DIO5 I/O

Digital I/O, software configured

8 GND -

9 ANT -

RF signal output/input.

10 GND -

11 DIO3 I/O

Digital I/O, software configured

12 DIO4 I/O

Digital I/O, software configured 3.3V - Supply voltage

14 DIO0 I/O

Digital I/O, software configured

15 DIO1 I/O

Digital I/O, software configured

16 DIO2 I/O

Digital I/O, software configured Page 11

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W 2. Electrical Characteristics 2.1. ESD Notice The RFM66W is a high performance radio frequency device. It satisfies:  Class 2 of the JEDEC standard JESD22-A114-B (Human Body Model) on all pins.  Class III of the JEDEC standard JESD22-C101C (Charged Device Model) on all pins It should thus be handled with all the necessary ESD precautions to avoid any permanent damage. 2.2. Absolute Maximum Ratings Stresses above the values listed below may cause permanent device failure. Exposure to absolute maximum ratings for extended periods may affect device reliability. Table 2 Absolute Maximum Ratings Symbol Description Min Max Unit VDDmr Supply Voltage -0.5 3.9 V Tmr Temperature -55 +115 ° C Tj Junction temperature - +125 ° C Pmr RF Input Level - +10 dBm Note Specific ratings apply to the +20dBm operation. Please refer to Section 3.4.7. 2.3. Operating Range Table 3 Operating Range Symbol VDDop Supply voltage 1.8 3.7 V Top Operational temperature range -40 +85 °C Clop Load capacitance on digital ports - 25 pF ML RF Input Level - +10 dBm Note A specific supply voltage range applies to the +20dBm operation. Please refer to Section 3.4.7. Page 12

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET 2.4. Chip Specification The tables below give the electrical specifications of the transceiver under the following conditions: Supply voltage VBAT1= VBAT2=VDD=3.3 V, temperature = 25 °C, FXOSC = 32 MHz, FRF = 915 MHz, Pout = +13dBm, 2-level FSK modulation without pre-filtering, FDA = 5 kHz, Bit Rate = 4.8 kb/s and terminated in a matched 50 Ohm impedance, unless otherwise specified. Matching as per Figure 39. Note Unless otherwise specified, the performance in the 868 MHz band is identical or better. 2.4.1. Power Consumption Table 4 Power Consumption Specification Symbol Description Conditions Min Typ Max Unit IDDSL Supply current in Sleep mode - 0.1 1 uA IDDIDLE Supply current in Idle mode RC oscillator enabled - 1.2 - uA IDDST Supply current in Standby mode Crystal oscillator enabled - 1.3 1.5 mA IDDFS Supply current in Synthesizer mode FSRx - 4.5 - mA IDDR Supply current in Receive mode LnaBoost = 00 - 9.3 - mA IDDT Supply current in Transmit mode with impedance matching RFOP = +20 dBm, on PA_BOOST RFOP = +17 dBm, on PA_BOOST RFOP = +13 dBm, on RFO pin RFOP = + 7 dBm, on RFO pin 125 mA mA mA mA 2.4.2. Frequency Synthesis Table 5 Frequency Synthesizer Specification Symbol Description Conditions Min Typ Max Unit FR Synthesizer frequency range Programmable 862 - 1020 MHz FXOSC Crystal oscillator frequency See section 7.1 - 32 - MHz TS_OSC Crystal oscillator wake-up time With crystal specified in section 7.1 - 250 - us TS_FS Frequency synthesizer wake-up time to PllLock signal From Standby mode - 60 - us TS_HOP Frequency synthesizer hop time at most 10 kHz away from the target frequency 200 kHz step

1 MHz step

5 MHz step

7 MHz step

12 MHz step

20 MHz step

25 MHz step

FSTEP Frequency synthesizer step FSTEP = FXOSC/219 - 61.0 - Hz FRC RC Oscillator frequency After calibration - 62.5 - kHz Page 13

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET BRF Bit rate, FSK Programmable values (1) 1.2 - 300 kbps BRO Bit rate, OOK Programmable 1.2 - 32.768 kbps BRA Bit Rate Accuracy ABS(wanted BR - available BR) - - 250 ppm FDA Frequency deviation, FSK (1) Programmable FDA + BRF/2 =< 250 kHz 0.6 - 200 kHz Note For Maximum Bit rate the maximum modulation index is 1. 2.4.3. Receiver All receiver tests are performed with RxBw = 10 kHz (Single Side Bandwidth) as programmed in RegRxBw, receiving a PN15 sequence. Sensitivities are reported for a 0.1% BER (with Bit Synchronizer enabled), unless otherwise specified. Blocking tests are performed with an unmodulated interferer. The wanted signal power for the Blocking Immunity, ACR, IIP2, IIP3 and AMR tests is set 3 dB above the receiver sensitivity level. Table 6 Receiver Specification Symbol Description Conditions Min Typ Max Unit RFS_F Direct tie of RFI and RFO pins, as shown in Figure 39. FSK sensitivity, highest LNA gain. FDA = 5 kHz, BR = 1.2 kb/s FDA = 5 kHz, BR = 4.8 kb/s FDA = 40 kHz, BR = 38.4 kb/s* FDA = 20 kHz, BR = 38.4 kb/s FDA = 62.5 kHz, BR = 250 kb/s* -119 -115 -105 -106 -92 dBm dBm dBm dBm dBm Split RF paths, as shown in Figure 40, LnaBoost is turned on, the RF switch insertion loss is not accounted for. FDA = 5 kHz, BR = 1.2 kb/s FDA = 5 kHz, BR = 4.8 kb/s FDA = 40 kHz, BR = 38.4 kb/s* FDA = 20 kHz, BR = 38.4 kb/s FDA = 62.5 kHz, BR = 250 kb/s* -123 -119 -110 -110 -97 dBm dBm dBm dBm dBm RFS_O OOK sensitivity, highest LNA gain Conditions of Figure 39 BR = 4.8 kb/s BR = 32 kb/s -117 -108 dBm dBm CCR Co-Channel Rejection - -8 - dB ACR Adjacent Channel Rejection FDA = 2 kHz, BR = 1.2kb/s, RxBw = 5.2kHz Offset = +/- 25 kHz dB FDA = 5 kHz, BR=4.8kb/s Offset = +/- 25 kHz Offset = +/- 50 kHz dB dB BI Blocking Immunity Offset = +/- 1 MHz Offset = +/- 2 MHz Offset = +/- 10 MHz dB dB dB AMR AM Rejection , AM modulated interferer with 100% modulation depth, fm = 1 kHz, square Offset = +/- 1 MHz Offset = +/- 2 MHz Offset = +/- 10 MHz dB dB dB Page 14

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET IIP2 2nd order Input Intercept Point Unwanted tones are 20 MHz above the LO Highest LNA gain - +57 - dBm IIP3 3rd order Input Intercept point Unwanted tones are 1MHz and

1.995 MHz above the LO

LNA gain G2, 4dB sensitivity hit -12 dBm dBm BW_SSB Single Side channel filter BW Programmable 2.7 - 250 kHz IMR Image Rejection Wanted signal 3dB over sens BER=0.1% - 48 - dB IMA Image Attenuation - 56 - dB DR_RSSI RSSI Dynamic Range AGC enabled Min Max -127 dBm dBm * RxBw = 83 kHz (Single Side Bandwidth) RxBw = 50 kHz (Single Side Bandwidth) * RxBw = 250 kHz (Single Side Bandwidth) 2.4.4. Transmitter Table 7 Transmitter Specification Symbol RF_OP RF output power in 50 ohms on RFO pin (High efficiency PA). Programmable with steps Max Min +11 +14 dBm dBm ΔRF_ OP_V RF output power stability on RFO pin versus voltage supply. VDD = 2.5 V to 3.3 V VDD = 1.8 V to 3.7 V dB dB RF_OPH RF output power in 50 ohms, on PA_BOOST pin (Regulated PA). Programmable with 1dB steps Max Min +17 dBm dBm RF_OPH _MAX Max RF output power, on PA_BOOST pin High power mode - +20 - dBm ΔRF_ OPH_V RF output power stability on PA_BOOST pin versus voltage supply. VDD = 2.4 V to 3.7 V - ±1 - dB ΔRF_T RF output power stability versus temperature on both RF pins. From T = -40 ° C to +85 ° C - +/-1 - dB PHN Transmitter Phase Noise Low Consumption PLL, 915 MHz 50kHz Offset 400kHz Offset 1MHz Offset -102 -114 -120 dBc/ Hz Low Phase Noise PLL, 915 MHz 50kHz Offset 400kHz Offset 1MHz Offset -106 -117 -122 dBc/ Hz Page 15

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET ACP Transmitter adjacent channel power (measured at 25 kHz off- set) BT=1 . Measurement conditions as defined by EN 300 220-1 V2.3.1 - - -37 dBm TS_TR Transmitter wake up time, to the first rising edge of DCLK Frequency Synthesizer enabled, PaRamp = 10us, BR = 4.8 kb/s - 120 - us 2.4.5. Digital Specification Conditions: Temp = 25° C, VDD = 3.3V, FXOSC = 32 MHz, unless otherwise specified. Table 8 Digital Specification Symbol Description Conditions Min Typ Max Unit VIH Digital input level high 0.8 - - VDD VIL Digital input level low - - 0.2 VDD VOH Digital output level high Imax = 1 mA 0.9 - - VDD VOL Digital output level low Imax = -1 mA - - 0.1 VDD FSCK SCK frequency - - 10 MHz tch SCK high time 50 - - ns tcl SCK low time 50 - - ns trise SCK rise time - 5 - ns tfall SCK fall time - 5 - ns tsetup MOSI setup time from MOSI change to SCK rising edge 30 - - ns thold MOSI hold time from SCK rising edge to MOSI change 20 - - ns tnsetup NSS setup time from NSS falling edge to SCK rising edge 30 - - ns tnhold NSS hold time from SCK falling edge to NSS rising edge, normal mode 100 - - ns tnhigh NSS high time between SPI accesses 20 - - ns T_DATA DATA hold and setup time 250 - - ns Page 16

figure shows a simplified block diagram of the RFM66W. Figure 4. Simplified RFM66W Block Schematic Diagram signal is processed by the packet engine and top level sequencer.

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET RFM66W features a pair of RF power amplifiers. The first, connected to RFO, can deliver up to +14 dBm, is unregulated for high power efficiency and can be connected directly to the RF receiver input via a pair of passive components to form a single antenna port high efficiency transceiver. The second PA, connected to the PA_BOOST pin and can deliver up to +20 dBm via a dedicated matching network. RFM66W also includes two timing references: an RC oscillator and a 32 MHz crystal oscillator. All major parameters of the RF front end and digital state machine are fully configurable via an SPI interface which gives access to internal registers. This includes a mode auto sequencer that oversees the transition and calibration of the RFM66W between intermediate modes of operation in the fastest time possible. 3.1. Power Supply Strategy The RFM66W employs an advanced power supply scheme, which provides stable operating characteristics over the full temperature and voltage range of operation. This includes the full output power of +17dBm which is maintained from 1.8 to 3.7 V. The RFM66W can be powered from any low-noise voltage source via pins VBAT1 and VBAT2. Decoupling capacitors should be connected, as suggested in the reference design, on VR_PA, VR_DIG and VR_ANA pins to ensure a correct operation of the built-in voltage regulators. 3.2. Low Battery Detector A low battery detector is also included allowing the generation of an interrupt signal in response to passing a programmable threshold adjustable through the register RegLowBat. The interrupt signal can be mapped to any of the DIO pins, by programming RegDioMapping. Page 18

synthesizer and as a clock for the digital processing. RFM66W optimizes the startup time and automatically triggers the PLL when the XO signal is stable. in RegTcxo should be set to 1, and the external clock has to be provided on XTA (pin 4). XTB (pin 5) should be left open. appropriate value of decoupling capacitor, CD. Figure 5. TCXO Connection The reference frequency, or a fraction of it, can be provided on DIO5 (pin 12) by modifying bits ClkOut in RegDioMapping2. be made available in any operation mode except Sleep mode and is automatically enabled at power on reset. the initial crystal tolerance. The local oscillator of the RFM66W is derived from a fractional-N PLL that is referenced to the crystal oscillator circuit. and low phase noise PLL, for each programmable bandwidth setting, is shown in the following figure.

Figure 6. Typical Phase Noise Performances of the Low Consumption and Low Phase Noise PLLs. Note in receive mode, only the low consumption PLL is available.

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET The carrier frequency is programmed through RegFrf, split across addresses 0x06 to 0x08: FRF = FSTE P × Frf(23,0) Note The Frf setting is split across 3 bytes. A change in the center frequency will only be taken into account when the least significant byte FrfLsb in RegFrfLsb is written. This allows for more complex modulation schemes such as m- ary FSK, where frequency modulation is achieved by changing the programmed RF frequency. 3.3.4. RC Oscillator All timings in the low-power state of the Top Level Sequencer rely on the accuracy of the internal low-power RC oscillator. This oscillator is automatically calibrated at the device power-up, and it is a user-transparent process. For applications enduring large temperature variations, and for which the power supply is never removed, RC calibration can be performed upon user request. RcCalStart in RegOsc triggers this calibration, and the flag RcCalDone will be set automatically when the calibration is over.

DC biasing and ramping functionality that is provided through the VR_PA block. operation up to +20 dBm. For full details of operation at +20 dBm please consult Section 3.4.7. Figure 7. RF Front-end Architecture Shows the Internal PA Configuration.

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET Table 9 Bit Rate Examples Type BitRate (15:8) BitRate (7:0) (G)FSK (G)MSK OOK Actual BR (b/s) Classical modem baud rates (multiples of 1.2 kbps) 0x68 0x2B 1.2 kbps 1.2 kbps 1200.015 0x34 0x15 2.4 kbps 2.4 kbps 2400.060 0x1A 0x0B 4.8 kbps 4.8 kbps 4799.760 0x0D 0x05 9.6 kbps 9.6 kbps 9600.960 0x06 0x83 19.2 kbps 19.2 kbps 19196.16 0x03 0x41 38.4 kbps 38415.36 0x01 0xA1 76.8 kbps 76738.60 0x00 0xD0 153.6 kbps 153846.1 Classical modem baud rates (multiples of 0.9 kbps) 0x02 0x2C 57.6 kbps 57553.95 0x01 0x16 115.2 kbps 115107.9 Round bit rates (multiples of 12.5, 25 and 50 kbps) 0x0A 0x00 12.5 kbps 12.5 kbps 12500.00 0x05 0x00 25 kbps 25 kbps 25000.00 0x80 0x00 50 kbps 50000.00 0x01 0x40 100 kbps 100000.0 0x00 0xD5 150 kbps 150234.7 0x00 0xA0 200 kbps 200000.0 0x00 0x80 250 kbps 250000.0 0x00 0x6B 300 kbps 299065.4 Watch Xtal frequency 0x03 0xD1 32.768 kbps 32.768 kbps 32753.32 3.4.3. FSK Modulation FSK modulation is performed inside the PLL bandwidth, by changing the fractional divider ratio in the feedback loop of the PLL. The large resolution of the sigma-delta modulator, allows for very narrow frequency deviation. The frequency deviation FDEV is given by: FDE V = FSTE P × Fde v (13,0) To ensure a proper modulation, the following limit applies: + - Note no constraint applies to the modulation index of the transmitter, but the frequency deviation must be set between 600 Hz and 200 kHz.

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET 3.4.4. OOK Modulation OOK modulation is applied by switching on and off the Power Amplifier. Digital control and smoothing are available to improve the transient power response of the OOK transmitter. 3.4.5. Modulation Shaping Modulation shaping can be applied in both OOK and FSK modulation modes, to improve the narrowband response of the transmitter. Both shaping features are controlled with PaRamp bits in RegPaRamp.  In FSK mode, a Gaussian filter with BT = 0.5 or 1 is used to filter the modulation stream, at the input of the sigma- delta modulator. If the Gaussian filter is enabled when the RFM66W is in Continuous mode, DCLK signal on pin 10 (DIO1/ DCLK) will trigger an interrupt on the uC each time a new bit has to be transmitted. Please refer to section 5.4.2 for details.  When OOK modulation is used, the PA bias voltages are ramped up and down smoothly when the PA is turned on and off, to reduce spectral splatter. Note the transmitter must be restarted if the ModulationShaping setting is changed, in order to recalibrate the built-in filter. 3.4.6. RF Power Amplifiers Three power amplifier blocks are embedded in the RFM66W. The first one herein referred to as PA0, can generate high efficiency RF power into a 50 ohm load. The RF power is programmable between -1dBm and +14dBm. PA0 is connected to pin RFO (pin 22). PA1 and PA2 are both connected to pin PA_BOOST (pin 23). They can deliver up to +17 dBm in programmable step of 1dB to the antenna, a specific impedance matching / harmonic filtering design is required to ensure impedance transformation and regulatory compliance. The RF power is programmable between +2 dBm and +17 dBm. The high power mode allows to achieve fixed output power of +20dBm. Table 10 Power Amplifier Mode Selection Truth Table PaSelect Mode Power Range Pout Formula

0 PA0 output on pin RFO -1 to +14 dBm -1 dBm + OutputPower

1 PA1 and PA2 combined on pin PA_BOOST +2 to +17 dBm +2 dBm + OutputPower

1 PA1+PA2 on PA_BOOST with high output

power +20dBm settings (see 3.4.7) +5 to +20 dBm +5 dBm + OutputPower Notes - For +20dBm restrictions of operation, please consult the following section - To ensure correct operation at the highest power levels, please make sure to adjust the OcpTrim accordingly in RegOcp. - If PA_BOOST pin is not used the pin can be left floating.

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET 3.4.7. High Power +20dBm Operation The RFM66W has a high power +20 dBm capability on PA_BOOST pin, with the following settings: Table 11 High Power Settings Register Address Value for High Power Default value PA0 or +17dBm 0x84 High power PA control Note - High Power settings must be turned off when using PA0 - The Over Current Protection limit should be adapted to the actual power level, in RegOcp Specific Absolute Maximum Ratings and Operating Range restrictions apply to the +20dBm operation. They are listed in Table 12 and Table 13. Table 12 Absolute Maximum Rating, +20dBm Operation Symbol DC_20dBm Duty Cycle of transmission at +20dBm output - 1 % VSWR_20dBm Maximum VSWR at antenna port, +20dBm output - 3:1 - Table 13 Operating Range, +20dBm Operation Symbol VDDop_20dBm Supply voltage, +20dBm output 2.4 3.7 V The Duty Cycle of transmission at +20dBm is limited to 1%, with a maximum VSWR of 3:1 at antenna port, over the standard operating range [-40;+85°C]. For any other operating condition, contact your Semtech representative.

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET 3.4.8. Over Current Protection An over current protection block is built-in the chip. It helps preventing surge currents required when the transmitter is used at its highest power levels, thus protecting the battery that may power the application. The current clamping value is controlled by OcpTrim bits in RegOcp, and is calculated with the following formulas: Table 14 Trimming of the OCP Current OcpTrim IMAX Imax Formula 0 to 15 45 to 120 mA 45 + 5*OcpTrim [mA] 16 to 27 130 to 240 mA -30 + 10*OcpTrim [mA] 27+ 240 mA 240 mA Note Imax sets a limit on the current drain of the Power Amplifier only, hence the maximum current drain of the RFM66W is equal to Imax + IFS

precision on RSSI measurement and enhanced image rejection. Figure 8. Receiver Block Diagram level of 0dBm or more, whilst optimizing the system linearity. performed only at the receiver start up. Table 15 hereafter shows typical NF and IIP3 performances for the different LNA gains.

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET RX input level (Pin) Gain Setting LnaGain Relative LNA Gain [dB] NF [dB] IIP3 [dBm] AgcThresh3 < Pin <= AgcThresh4 „100‟ -24 dB AgcThresh4 < Pin <= AgcThresh5 „110‟ -26 dB AgcThresh5 < Pin „111‟ -48 dB 3.5.3. Enabling the Demodulation At receiver start up, the AGC and AFC features are preformed before providing reliable demodulated data to FIFO or DATA pin. Table 16 hereafter allows the user to set under which criteria he likes to start demodulating data. Table 16 Data Output Conditions. * Data ouput conditions StartDemodOnRSSI StartDemodOnPreamble None (immediate) PreambleDetect Rssi PreambleDetect & Rssi The flowchart of the following figure shows the processing events of AgcAutoOn, AgcOnPreamble and AfcAutoOn control bits at receiver starts up. Finally, when processing events are done and the data output conditions are verified according to Table 16, reliable data starts to be demodulated.

Figure 9. Receiver Startup Process.

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET 3.5.4. RSSI The RSSI value reflects the incoming signal power provided at antenna port within the receiver bandwidth. The signal power is available in RssiValue. T his value is absolute and its unit is in dBm with a resolution of 0.5dB. The formula hereafter gives the relationship between the register value and the absolute input signal level in dBm at antenna port: RssiValue = −2 ⋅ RF level [dBm]+ RssiOffset [dB] The RSSI value can be compensated for to take into account the loss in the matching network or the gain of an additional LNA, by using RssiOffset. The offset can be chosen in 1dB steps from -16 to +15dB. When compensation is applied, the effective signal strength is read as follows: RSSI [dBm] = − RssiValue 2 The RSSI value is smoothed on a given number of measured RSSI samples. The precision of the RSSI value is related to the number of RSSI samples used. RssiSmoothing selects the number of RSSI samples from a minimum of 2 samples up to 256 samples in increments of power of 2. Table 17 hereafter gives the estimation of the RSSI accuracy for a 10dB SNR and the response time versus the number of RSSI samples selected in RssiSmoothing. Table 17 RssiSmoothing Options RssiSmoothing Number of Samples Estimated Accuracy Response Time „000‟ 2 ± 6dB 2 (RssiSmoothing +1) 4 ⋅ RxBw[kHz] [ms] „001‟ 4 ± 5dB „010‟ 8 ± 4dB „011‟ 16 ± 3dB „100‟ 32 ± 2dB „101‟ 64 ± 1.5dB „110‟ 128 ± 1.2dB „111‟ 256 ± 1.1dB The RSSI is calibrated, up the RFI pin, when Image and Rssi calibration is launched; please see section 3.5.13 for details. 3.5.5. Channel Filter The role of the channel filter is to filter out the noise and interferers outside of the channel. Channel filtering on the RFM66W is implemented with a 16-tap Finite Impulse Response (FIR) filter, providing an outstanding Adjacent Channel Rejection performance, even for narrowband applications. Note to respect oversampling rules in the decimation chain of the receiver, the Bit Rate cannot be set at a higher value than 2 times the single-side receiver bandwidth (BitRate < 2 x RxBw) The single-side channel filter bandwidth RxBw is controlled by the parameters RxBwMant and RxBwExp in RegRxBw: RxBwMan t × 2RxBw E x p + 2

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET The following channel filter bandwidths are accessible (oscillator is mandated at 32 MHz): Table 18 Available RxBw Settings RxBwMant (binary/value) RxBwExp (decimal) RxBw (kHz) FSK / OOK 10b / 24 7 2.6 01b / 20 7 3.1 00b / 16 7 3.9 10b / 24 6 5.2 01b / 20 6 6.3 00b / 16 6 7.8 10b / 24 5 10.4 01b / 20 5 12.5 00b / 16 5 15.6 10b / 24 4 20.8 01b / 20 4 25.0 00b / 16 4 31.3 10b / 24 3 41.7 01b / 20 3 50.0 00b / 16 3 62.5 10b / 24 2 83.3 01b / 20 2 100.0 00b / 16 2 125.0 10b / 24 1 166.7 01b / 20 1 200.0 00b / 16 1 250.0 10b / 24 reserved 01b / 20 00b / 16 3.5.6. FSK Demodulator The FSK demodulator of the RFM66W is designed to demodulate FSK, GFSK, MSK and GMSK modulated signals. It is most efficient when the modulation index of the signal is greater than 0.5 and below 10: 0 The output of the FSK demodulator can be fed to the Bit Synchronizer to provide the companion processor with a synchronous data stream in Continuous mode. 3.5.7. OOK Demodulator The OOK demodulator performs a comparison of the RSSI output and a threshold value. Three different threshold modes are available, configured through bits OokThreshType in RegOokPeak. The recommended mode of operation is the "Peak" threshold mode, illustrated in Figure 10:

Figure 10. OOK Peak Demodulator Description OokPeakThreshStep every OokPeakThreshDec period. the peak threshold level will continue falling until it reaches the "Floor Threshold", programmed in OokFixedThresh. (i.e. those close to the noise floor). Significant sensitivity improvements can be generated if configured correctly.  The noise figure of the receiver.  The gain of the receive chain from antenna to base band.  The matching - including SAW filter if any.  The bandwidth of the channel filters. is recommended to optimize OokFixedThresh.

Figure 11. Floor Threshold Optimization The new floor threshold value found during this test should be used for OOK reception with those receiver settings.

receiver performance its use when running Continuous mode is strongly advised. Figure 12. Bit Synchronizer Description

Figure 13. FEI Process FRF. The AFC is executed each time the receiver is enabled, if AfcAutoOn = 1. keeps on drifting in the “same direction”. Ageing compensation is a good example. be programmed in RegAfcBw, at the expense of the receiver noise floor, which will impact upon sensitivity. StartDemodOnPreamble in RegRxConfig.

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET 3.5.11. Preamble Detector The Preamble Detector indicates the reception of a carrier modulated with a 0101...sequence. It is insensitive to the frequency offset, as long as the receiver bandwidth is large enough. The size of detection can be programmed from 1 to 3 bytes with PreambleDetectorSize in RegPreambleDetect as defined in the next table. Table 19 Preamble Detector Settings PreambleDetectorSize # of Bytes 00 1 01 2 (recommended) 10 3 11 reserved For proper operation, PreambleDetectTol should be set to be set to 10 (0x0A), with a qualifying preamble size of 2 bytes. PreambleDetect interrupt (either in RegIrqFlags1 or mapped to a specific DIO) goes high every time a valid preamble is detected, assuming PreambleDetectorOn=1. The preamble detector can also be used to ensure that AFC and AGC are performed on valid preamble. See Figure 9 for details. 3.5.12. Image Rejection Mixer The RFM66W embeds a state of the art Image Rejection Mixer (IRM). Its default rejection, with no calibration, is 35dB typ. The IQ signals can be calibrated by an embedded source, pushing the image rejection to typically 48dB. This process is fully automated and self-contained. 3.5.13. Image and RSSI Calibration Calibration of the I and Q signal is required to improve the RSSI precision, as well as good Image Rejection performance. On the RFM66W, IQ calibration is seamless and user-transparent. Calibration is launched:  Automatically at Power On Reset or after a Manual Reset of the chip (refer to section 7.2). For applications where the temperature remains stable, or if the Image Rejection is not a major concern, this one-shot calibration will suffice  Automatically when a pre-defined temperature change is observed  Upon User request, by setting bit ImageCalStart in RegImageCal A selectable temperature change, set with TempThreshold (5, 10, 15 or 20° C), is detected and reported in TempChange, if the temperature monitoring is turned On with TempMonitorOff=0. This interrupt flag can be used by the application to launch a new Image Calibration at a convenient time if AutoImageCalOn=0, or immediately when this temperature variation is detected, if AutoImageCalOn=1. The calibration process takes approximately 10ms.

stored in TempValue in RegTemp. Figure 14. Temperature Sensor Response An example code for the conversion to be applied to TempValue to obtain the reading in °C is shown in Section 7. sequence and therefore save energy.

packet transmission and reception is also possible using the Top Level Sequencer described in Section 4.3.

000 Sleep mode None

001 Standby mode Top regulator and crystal oscillator

010 FSTx: Frequency synthesiser to Tx frequency Frequency synthesizer at Tx frequency (Frf)

011 Transmit mode (Tx) Frequency synthesizer and transmitter

100 FSRx: Frequency synthesiser to Rx frequency Frequency synthesizer at frequency for reception (Frf-IF)

101 Receive mode (Rx) Frequency synthesizer and receiver

The startup time of the transmitter or the receiver is dependant upon which mode the transceiver was in at the beginning. For a complete description, Figure 15 below shows a complete startup process, from the lower power mode “Sleep”. Figure 15. Startup Process the startup time of the PLL, and it includes a systematic calibration of the VCO. Typical values of TS_OSC and TS_FS are given in section 2.3.

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET 4.2.1. Transmitter Startup Time The transmitter startup time, TS_TR, is calculated as follows, in when FSK modulation is selected: TS _ TR = 5μs + 1.25 × PaRamp + 1 × Tbit 2 , where PaRamp is the ramp-up time programmed in RegPaRamp and Tbit is the bit time. In OOK mode, this equation can be simplified to the following: TS _ TR = 5μs +1 × Tbit 4.2.2. Tx Start Procedure As described in the former section, ModeReady and TxReady interrupts warn the uC that the transmitter is ready to transmit data  In Continuous mode, the preamble bits preceding the payload can be applied on the DIO2/DATA pin immediately after any of these interrupts have fired. The DCLK signal, activated on pin DIO1/DCLK can also be used to start toggling the DATA pin, as described on Figure 29.  In Packet mode, the SX1231 will automatically modulate the RF signal with preamble bytes as soon as TxReady or ModeReady happen. The actual packet transmission (starting with the number of preambles specified in PreambleSize) will start when the TxStartCondition is fulfilled. 4.2.3. Receiver Startup Time The receiver startup time TS_RE, only depends on the receiver bandwidth effective at the time of startup. When AFC is enabled (AfcAutoOn=1), AfcBw should be used instead of RxBw to extract the receiver startup time:

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET 4.3. Top Level Sequencer Depending on the application, it is desirable to be able to change the mode of the circuit according to a predefined sequence without access to the serial interface. Listen mode and Auto Modes as defined in RF69 are example of such predefined sequences. In order to define different sequences or scenarios a user-programmable state machine, called Top Level Sequencer (Sequencer in short), can automatically control the chip modes. The Sequencer is activated by setting SequencerStart in RegSeqConfig1 to 1 in Sleep or Standby mode. It is also possible to force the Idle state of the Sequencer by setting SequencerStop to 1 at any time. 4.3.1. Sequencer States The Sequencer takes control of the chip operation over 7 possible states: Table 21 Sequencer States Sequencer State SequencerIdle State The Sequencer is not activated. Sending a SequencerStart command will launch it. Note: the Idle state of the Sequencer is independant of the actual chip Mode. For example, the Sequencer can be Idle, whilst the chip is in Rx mode. When coming from a LowPower request, the Sequencer will be Idle in Sleep mode. WaitFifo State The Sequencer waits for FifoThreshold interrupt before entering the Transmit state. LowPower State The chip is in low-power mode, either Standby or Sleep, as defined in Sequencer Low Power State. The Sequencer waits only for the Timer1 interrupt. Transmit State The transmitter in on. Receive State The receiver in on. PacketReceived State The receiver is on and a packet has been received. It is stored in the FIFO. ReceiveRestart State The receiver is re-started, for example to start a new AGC and/or AFC after a valid packet reception.

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET 4.3.2. Sequencer Transitions The transitions between states are listed in the forthcoming table. Table 22 Sequencer Transition Options Variable Transition SequencerTransitionFromIdle Control state-machine transition from the Idle state: 00: to LowPower or Idle state on a SequencerStart command, depending on SequencerLowPowerState 01: to Receive state on a SequencerStart command 10: to Transmit state on a SequencerStart command 11: to WaitForFifo on a SequencerStart command SequencerLowPowerState Defines the low power state of the Sequencer, reached at the end of any action (transmission, reception, etc...) 0: to Idle state 1: to LowPower state SequencerTransitionFromLowPower Control the Sequencer transition from the LowPower state: 0: to Transmit state on a Timer 1 interrupt 1: to Receive state on a Timer 1 interrupt SequencerTransitionFromTransmit Control the Sequencer transition from the Transmit state: 0: to LowPower or Idle state on a PacketSent interrupt, depending on SequencerLowPowerState 1: to Receive state on a PacketSent interrupt SequencerTransitionFromReceive Control the Sequencer transition from the Receive state 000 and 111: unused 001: to PacketReceived state on a PayloadReady interrupt 010: to LowPower or Idle state on a PayloadReady interrupt, depending on SequencerLowPowerState 011: to PacketReceived state on a CrcOk interrupt. If the CRC is disabled the PayloadReady interrupt, firing when enough bytes are received, will drive the Sequencer to the PacketReceived state, too. 100: to Idle state on a Rssi interrupt 101: to Idle state on a SyncAddress interrupt 110: to Idle state on a PreambleDetect interrupt Irrespective of this setting, transition to LowPower or Idle state on a Timer2 interrupt, depending on SequencerLowPowerState SequencerTransitionFromRxTimeout Control the state-machine transition from the Receive state on a RxTimeout interrupt (and on PayloadReady if SequencerTransitionFromReceive = 011): 00: to ReceiveRestart 01: to Transmit 10: to LowPower or Idle state, depending on SequencerLowPowerState 11: to Idle state SequencerTransitionFromPacketReceived Control the state-machine transition from the PacketReceived state: 000: to Idle state 001: to Transmit on a FifoEmpty interrupt 010: to LowPower or Idle state on FifoEmpty, depending on SequencerLowPowerState 011: to Receive via FS mode, if frequency was changed 100: to Receive state (no frequency change)

Two timers (Timer1 and Timer2) are also available in order to define periodic sequences. Before Talk, Automatic Acknowledgment, Beacon transmitter... final states are in grey; transition conditions, represented by an arrow, are described in a blue text box. Figure 16. Sequencer Transitions From Idle State

Figure 21. Sequencer Transitions From Transmit State

The simplified timing diagram of this procedure is given in Figure 22. Figure 22. Listen mode Sequence (no wanted signal) The durations of the Idling and Receive periods can be programmed using Timer1 and Timer2 respectively. the variable SequencerTransitionFromReceive. The packet acceptance criteria is, for example, detection of a valid Preamble thanks to the PreambleDetect interrupt.

demodulator and the uC access points (SPI and DIO pins). It also controls all the configuration registers. The circuit contains several control blocks which are described in the following paragraphs. Figure 23. RFM66W Data Processing Conceptual View section. Depending on the data operation mode selected, some control blocks are active whilst others remain disabled. used if adequate external signal processing is available. the optional features activated (CRC, etc) the maximum payload length is limited to 255, 2047 bytes or unlimited. Each of these data operation modes is fully described in the following sections.

= 0 and CPHA = 0 in Motorola/Freescale nomenclature. Only the slave side is implemented. the beginning of the frame and stay low between each byte. It goes high only after the last byte transfer. only after the last byte transfer. Figure below shows a typical SPI single access to a register. Figure 24. SPI Timing Diagram (single access) rising edge of SCK. MISO is generated by the slave on the falling edge of SCK. A transfer always starts by the NSS pin going low. MISO is high impedance when NSS is high. MISO in case of read access. The data byte is transmitted MSB first.

actually a special case of FIFO / BURST mode with only 1 data byte transferred. register before the write operation. (First In First Out) device. It is accessed via the SPI interface and provides several interrupts for transfer management. from the demodulator and writes them byte by byte to the FIFO. This is illustrated in figure below. Figure 25. FIFO and Shift Register (SR) The FIFO size is fixed to 64 bytes.  FifoFull: FifoFull interrupt source is high when the last FIFO byte, i.e. the whole FIFO, is full. Otherwise it is low.  PacketSent: PacketSent interrupt source goes high when the SR's last bit has been sent.  FifoLevel: Threshold can be programmed by FifoThreshold in RegFifoThresh. Its behavior is illustrated in figure below.

0 B B+1

Figure 26. FifoLevel IRQ Source Behavior synchronizer must also be activated in Continuous mode (automatically done in Packet mode). word and sets SyncAddressMatch when a match is detected. This is illustrated in Figure 27 below.

Figure 27. Sync Word Recognition SyncAddressMatch is cleared when leaving Rx or FIFO is emptied. this field is also used for Sync word generation in Tx mode. The packet handler is the block used in Packet mode. Its functionality is fully described in section 5.5. is controlled through RegDioMapping1 and RegDioMapping2.

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET Table 26 DIO Mapping, Continuous Mode Mode Diox Mapping DIO5 DIO4 DIO3 DIO2 DIO1 DIO0 Sleep 00 - - - - - - 01 - - - - - - 10 - - - - - - 11 - - - - - - Stdby 00 ClkOut TempChange/ LowBat - - - - 01 - - - - - - 10 - - - - - -

11 ModeReady ModeReady TempChange/

• - - FSRx or

00 ClkOut TempChange/

• - - - FSTx 01 PllLock PllLock - - - - 10 - - AutoMode - - -
• - - Rx 00 ClkOut TempChange/ LowBat Timeout Data Dclk SyncAddress

01 PllLock PllLock Rssi/

10 Rssi/

• Data Dclk TxReady

01 PllLock PllLock - Data - -

Table 27 DIO Mapping, Packet Mode Mode Diox Mapping DIO5 DIO4 DIO3 DIO2 DIO1 DIO0 Sleep 00 - - FifoEmpty FifoFull FifoLevel - 01 - - - - FifoEmpty - 10 - - FifoEmpty FifoFull FifoFull - 11 - - FifoEmpty FifoFull - TempChange/ LowBat Stdby 00 ClkOut TempChange/ LowBat FifoEmpty FifoFull FifoLevel - 01 - - - - FifoEmpty - 10 - - FifoEmpty FifoFull FifoFull -

11 ModeReady - FifoEmpty FifoFull - TempChange/

FifoEmpty FifoFull FifoLevel - FSTx 01 PllLock PllLock - - FifoEmpty - 10 - - FifoEmpty FifoFull FifoFull - FifoEmpty FifoFull FifoLevel PayloadReady

01 PllLock PllLock - RxReady FifoEmpty CrcOk

10 Data Timeout FifoEmpty Timeout FifoFull -

11 ModeReady Rssi/

FifoEmpty SyncAddress - TempChange/ LowBat Tx 00 ClkOut TempChange/ LowBat FifoEmpty FifoFull FifoLevel PacketSent

01 PllLock PllLock TxReady - FifoEmpty -

10 Data - FifoEmpty FifoFull FifoFull -

Note Received Data is shown on the Data signal when RxReady arises

Figure 30. Rx Processing in Continuous Mode DCLK signal is not used by the uC (bit synchronizer is automatically enabled in Packet mode). accessed via the SPI interface. generation, CRC calculation/check, whitening/dewhitening of data, Manchester encoding/decoding, address filtering, etc. This simplifies software and reduces uC overhead by performing these repetitive tasks within the RF chip itself. and adding more flexibility for the software.

Figure 31. Packet Mode Conceptual View Note The Bit Synchronizer is automatically enabled in Packet mode. The length of the payload is limited to 2047 bytes. address byte. In this mode, the payload must contain at least one byte, i.e. address or message byte.

Figure 32. Fixed Length Packet Format Variable length packet format is selected when bit PacketFormat is set to 1. bytes, i.e. length + address or message byte.

Figure 33. Variable Length Packet Format Unlimited length packet format is selected when bit PacketFormat is set to 0 and PayloadLength is set to 0. for counting the length of the bytes transmitted/received. CrcOk & PayloadReady are not available either.  Optional Address byte (Node ID).

Figure 34. Unlimited Length Packet Format and appending the 2 bytes checksum. Only the payload (including optional address and length fields) is required to be provided by the user in the FIFO. one until the condition is met to transmit the packet data.  Optionally checking CRC and reflecting the result on CrcOk. Only the payload (including optional address and length fields) is made available in the FIFO. in PayloadLength register the packet is discarded otherwise the complete packet is received.

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET If the address check is enabled then the second byte received in case of variable length and first byte in case of fixed length is the address byte. If the address matches to the one in the NodeAddress field, reception of the data continues otherwise it's stopped. The CRC check is performed if CrcOn = 1 and the result is available in CrcOk indicating that the CRC was successful. An interrupt (PayloadReady) is also generated on DIO0 as soon as the payload is available in the FIFO. The payload available in the FIFO can also be read in Sleep/Standby mode. If the CRC fails the PayloadReady interrupt is not generated and the FIFO is cleared. This function can be overridden by setting CrcAutoClearOff = 1, forcing the availability of PayloadReady interrupt and the payload in the FIFO even if the CRC fails. 5.5.5. Handling Large Packets When PayloadLength exceeds FIFO size (64 bytes) whether in fixed, variable or unlimited length packet format, in addition to PacketSent in Tx and PayloadReady or CrcOk in Rx, the FIFO interrupts/flags can be used as described below:  For Tx: FIFO can be prefilled in Sleep/Standby but must be refilled "on-the-fly" during Tx with the rest of the payload. 1) Prefill FIFO (in Sleep/Standby first or directly in Tx mode) until FifoThreshold or FifoFull is set 2) In Tx, wait for FifoThreshold or FifoEmpty to be set (i.e. FIFO is nearly empty) 3) Write bytes into the FIFO until FifoThreshold or FifoFull is set. 4) Continue to step 2 until the entire message has been written to the FIFO (PacketSent will fire when the last bit of the packet has been sent).  For Rx: FIFO must be unfilled "on-the-fly" during Rx to prevent FIFO overrun. 1) Start reading bytes from the FIFO when FifoEmpty is cleared or FifoThreshold becomes set. 2) Suspend reading from the FIFO if FifoEmpty fires before all bytes of the message have been read 3) Continue to step 1 until PayloadReady or CrcOk fires 4) Read all remaining bytes from the FIFO either in Rx or Sleep/Standby mode 5.5.6. Packet Filtering The RFM66W packet handler offers several mechanisms for packet filtering, ensuring that only useful packets are made available to the uC, reducing significantly system power consumption and software complexity. 5.5.6.1. Sync Word Based Sync word filtering/recognition is used for identifying the start of the payload and also for network identification. As previously described, the Sync word recognition block is configured (size, value) in RegSyncConfig and RegSyncValue(i) registers. This information is used, both for appending Sync word in Tx, and filtering packets in Rx. Every received packet which does not start with this locally configured Sync word is automatically discarded and no interrupt is generated. When the Sync word is detected, payload reception automatically starts and SyncAddressMatch is asserted. Note Sync Word values containing 0x00 byte(s) are forbidden 5.5.6.2. Address Based

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET Address filtering can be enabled via the AddressFiltering bits. It adds another level of filtering, above Sync word (i.e. Sync must match first), typically useful in a multi-node networks where a network ID is shared between all nodes (Sync word) and each node has its own ID (address). Two address based filtering options are available:  AddressFiltering = 01: Received address field is compared with internal register NodeAddress. If they match then the packet is accepted and processed, otherwise it is discarded.  AddressFiltering = 10: Received address field is compared with internal registers NodeAddress and BroadcastAddress. If either is a match, the received packet is accepted and processed, otherwise it is discarded. This additional check with a constant is useful for implementing broadcast in a multi-node networks Please note that the received address byte, as part of the payload, is not stripped off the packet and is made available in the FIFO. In addition, NodeAddress and AddressFiltering only apply to Rx. On Tx side, if address filtering is expected, the address byte should simply be put into the FIFO like any other byte of the payload. As address filtering requires a Sync word match, both features share the same interrupt flag SyncAddressMatch. 5.5.6.3. Length Based In variable length Packet mode, PayloadLength must be programmed with the maximum payload length permitted. If received length byte is smaller than this maximum then the packet is accepted and processed, otherwise it is discarded. Please note that the received length byte, as part of the payload, is not stripped off the packet and is made available in the FIFO. To disable this function the user should set the value of the PayloadLength to 2047. 5.5.6.4. CRC Based The CRC check is enabled by setting bit CrcOn in RegPacketConfig1. It is used for checking the integrity of the message.  On Tx side a two byte CRC checksum is calculated on the payload part of the packet and appended to the end of the message  On Rx side the checksum is calculated on the received payload and compared with the two checksum bytes received. The result of the comparison is stored in bit CrcOk. By default, if the CRC check fails then the FIFO is automatically cleared and no interrupt is generated. This filtering function can be disabled via CrcAutoClearOff bit and in this case, even if CRC fails, the FIFO is not cleared and only PayloadReady interrupt goes high. Please note that in both cases, the two CRC checksum bytes are stripped off by the packet handler and only the payload is made available in the FIFO. Two CRC implementations are selected with bit CrcWhiteningType. Table 28 CRC Description Crc Type CrcWhiteningType Polynomial Seed Value Complemented CCITT 0 (default) X16 + X12 + X5 + 1 0x1D0F Yes IBM 1 X16 + X15 + X2 + 1 0xFFFF No A C code implementation of each CRC type is proposed in Application Section 7.

For such purposes, two techniques are made available in the packet handler: Manchester encoding and data whitening. Note Only one of the two methods can be enabled at a time. Manchester encoding/decoding is enabled if DcFree = 01 and can only be used in Packet mode. The NRZ data is converted to Manchester code by coding '1' as "10" and '0' as "01". Bit Rate NRZ = 2 x Bit Rate Manchester). Figure 35. Manchester Encoding/Decoding

Another technique called whitening or scrambling is widely used for randomizing the user data before radio transmission. The data is whitened using a random sequence on the Tx side and de-whitened on the Rx side using the same sequence. Comparing to Manchester technique it has the advantage of keeping NRZ data rate i.e. actual bit rate is not halved. on the receiver side by XORing with the same random sequence. Figure 36. Data Whitening Polynomial multiple times with the same data. Transmit mode. FifoEmpty, FifoFull and FifoLevel flags are also restored. This feature is only available in Fixed packet format, with the Payload Length smaller than the FIFO size. The Beacon Tx mode is exited by setting BeaconOn to 0, and clearing the FIFO by setting FifoOverrun to 1. details on its implementation.

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET 6. Description of the Registers 6.1. Register Table Summary Table 29 Registers Summary Address Register Name Reset (built-in) Default (recom mended) 0x00 RegFifo 0x00 FIFO read/write access 0x01 RegOpMode 0x01 Operating modes of the transceiver 0x02 RegBitrateMsb 0x1A Bit Rate setting, Most Significant Bits 0x03 RegBitrateLsb 0x0B Bit Rate setting, Least Significant Bits 0x04 RegFdevMsb 0x00 Frequency Deviation setting, Most Significant Bits 0x05 RegFdevLsb 0x52 Frequency Deviation setting, Least Significant Bits 0x06 RegFrfMsb 0xE4 RF Carrier Frequency, Most Significant Bits 0x07 RegFrfMid 0xC0 RF Carrier Frequency, Intermediate Bits 0x08 RegFrfLsb 0x00 RF Carrier Frequency, Least Significant Bits 0x09 RegPaConfig 0x0F PA selection and Output Power control 0x0A RegPaRamp 0x19 Control of the PA ramp time in FSK, low phase noise PLL 0x0B RegOcp 0x2B Over Current Protection control 0x0C RegLna 0x20 LNA settings 0x0D RegRxConfig 0x08 Control of the AFC, AGC, Collision detector 0x0E RegRssiConfig 0x02 RSSI-related settings 0x0F RegRssiCollision 0x0A RSSI setting of the Collision detector 0x10 RegRssiThresh 0xFF RSSI Threshold control 0x11 RegRssiValue - RSSI value in dBm 0x12 RegRxBw 0x15 Channel Filter BW Control 0x13 RegAfcBw 0x0B Channel Filter BW control during the AFC 0x14 RegOokPeak 0x28 OOK demodulator selection and control in peak mode 0x15 RegOokFix 0x0C Fixed threshold control of the OOK demodulator 0x16 RegOokAvg 0x12 Average threshold control of the OOK demodulator 0x17 Reserved17 0x47 0x18 Reserved18 0x32 0x19 Reserved19 0x3E

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET Address Register Name Reset (built-in) Default (recom mended) 0x1A RegAfcFei 0x00 AFC and FEI control 0x1B RegAfcMsb 0x00 MSB of the frequency correction of the AFC 0x1C RegAfcLsb 0x00 LSB of the frequency correction of the AFC 0x1D RegFeiMsb 0x00 MSB of the calculated frequency error 0x1E RegFeiLsb 0x00 LSB of the calculated frequency error 0x1F RegPreambleDetect 0x40 Settings of the Preamble Detector 0x20 RegRxTimeout1 0x00 Timeout duration between Rx request and RSSI detection 0x21 RegRxTimeout2 0x00 Timeout duration between RSSI detection and PayloadReady 0x22 RegRxTimeout3 0x00 Timeout duration between RSSI and SyncAddress 0x23 RegRxDelay 0x00 Delay between Rx cycles 0x24 RegOsc 0x05 RC Oscillators Settings, CLKOUT frequency 0x25 RegPreambleMsb 0x00 Preamble length, MSB 0x26 RegPreambleLsb 0x03 Preamble length, LSB 0x27 RegSyncConfig 0x93 Sync Word Recognition control 0x28-0x2F RegSyncValue1-8 0x55 Sync Word bytes, 1 through 8 0x30 RegPacketConfig1 0x90 Packet mode settings 0x31 RegPacketConfig2 0x40 Packet mode settings 0x32 RegPayloadLength 0x40 Payload length setting 0x33 RegNodeAdrs 0x00 Node address 0x34 RegBroadcastAdrs 0x00 Broadcast address 0x35 RegFifoThresh 0x0F Fifo threshold, Tx start condition 0x36 RegSeqConfig1 0x00 Top level Sequencer settings 0x37 RegSeqConfig2 0x00 Top level Sequencer settings 0x38 RegTimerResol 0x00 Timer 1 and 2 resolution control 0x39 RegTimer1Coef 0xF5 Timer 1 setting 0x3A RegTimer2Coef 0x20 Timer 2 setting 0x3B RegImageCal 0x82 Image calibration engine control 0x3C RegTemp - Temperature Sensor value 0x3D RegLowBat 0x02 Low Battery Indicator Settings 0x3E RegIrqFlags1 0x80 Status register: PLL Lock state, Timeout, RSSI > Threshold...

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET Address Register Name Reset (built-in) Default (recom mended) 0x3F RegIrqFlags2 0x40 Status register: FIFO handling flags, Low Battery detection... 0x40 RegDioMapping1 0x00 Mapping of pins DIO0 to DIO3 0x41 RegDioMapping2 0x00 Mapping of pins DIO4 and DIO5, ClkOut frequency 0x42 RegVersion 0x21 Semtech ID relating the silicon revision 0x43 RegAgcRef 0x13 Adjustment of the AGC thresholds 0x44 RegAgcThresh1 0x0E 0x45 RegAgcThresh2 0x5B 0x46 RegAgcThresh3 0xDB 0x58 RegTcxo 0x09 TCXO or XTAL input setting 0x5A RegPaDac 0x84 Higher power settings of the PA 0x5C RegPll 0xD0 Control of the PLL bandwidth 0x5E RegPllLowPn 0xD0 Control of the Low Phase Noise PLL bandwidth 0x6C RegFormerTemp - Stored temperature during the former IQ Calibration 0x70 RegBitRateFrac 0x00 Fractional part in the Bit Rate division ratio 0x42 + RegTest - Internal test registers. Do not overwrite Note - Reset values are automatically refreshed in the chip at Power On Reset - Default values are the Semtech recommended register values, optimizing the device operation - Registers for which the Default value differs from the Reset value are denoted by a * in the tables of section 4

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET 6.2. Register Map Convention: r: read, w: write, p:pulse, x:trigger Table 30 Register Map Name (Address) Bits Variable Name Mode Default value (0x00) 7-0 Fifo rwx 0x00 FIFO data input/output Resisters for Common settings RegOpMode (0x01) 7 unused r 0x00 unused 6-5 ModulationType rw 0x00 Modulation scheme: 00 → FSK 01 → OOK 10 -11 → reserved 4-3 ModulationShaping rw 0x00 Data shaping: In FSK: 00 → no shaping 01 → gaussian filter BT = 1.0 10 → gaussian filter BT = 0.5 11 → gaussian filter BT = 0.3 In OOK: 00 → no shaping 01 → filtering with fcutoff = bit_rate 10 → filtering with fcutoff = 2*bit_rate (for bit_rate < 125 kb/s) 11 → reserved 2-0 Mode rwx 0x01 Transceiver modes 000 → Sleep mode 001 → Stdby mode 010 → FS mode TX (FSTx) 011 → Transmitter mode (Tx) 100 → FS mode RX (FSRx) 101 → Receiver mode (Rx) 110 → reserved 111 → reserved RegBitrateMsb (0x02) 7-0 BitRate(15:8) rw 0x1a MSB of Bit Rate (chip rate if Manchester encoding is enabled) RegBitrateLsb (0x03) 7-0 BitRate(7:0) rw 0x0b LSB of bit rate (chip rate if Manchester encoding is enabled) BitRate(15,0) + -B----i--t--r--a- - --t--e---F- - --r--a- - --c- Default value: 4.8 kb/s RegFdevMsb (0x04) 7-6 unused r 0x00 unused 5-0 Fdev(13:8) rw 0x00 MSB of the frequency deviation RegFdevLsb (0x05) 7-0 Fdev(7:0) rw 0x52 LSB of the frequency deviation Fdev = Fste p × Fdev(15,0) Default value: 5 kHz

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET Name (Address) Bits Variable Name Mode Default value (0x06) 7-0 Frf(23:16) rw 0xe4 MSB of the RF carrier frequency RegFrfMid (0x07) 7-0 Frf(15:8) rw 0xc0 MSB of the RF carrier frequency RegFrfLsb (0x08) 7-0 Frf(7:0) rwx 0x00 LSB of RF carrier frequency Frf = Fste p × Fr f( 23;0 ) Default value: 915.000 MHz The RF frequency is taken into account internally only when: - entering FSRX/FSTX modes - re-starting the receiver Registers for the Transmitter RegPaConfig (0x09)

7 PaSelect rw 0x00 Selects PA output pin

0 → RFO pin. Maximum power of +13 dBm 1 → PA_BOOST pin. Maximum power of +20 dBm 6-4 unused r 0x00 unused 3-0 OutputPower rw 0x0f Output power setting, with 1dB steps Pout = 2 + OutputPower [dBm] , on PA_BOOST pin Pout = -1 + OutputPower [dBm] , on RFO pin RegPaRamp (0x0A) 7-5 unused r - unused

4 LowPnTxPllOff rw 0x01 Select a higher power, lower phase noise PLL only when the

transmitter is used: 0 → Standard PLL used in Rx mode, Lower PN PLL in Tx 1 → Standard PLL used in both Tx and Rx modes 3-0 PaRamp rw 0x09 Rise/Fall time of ramp up/down in FSK 0000 → 3.4 ms 0001 → 2 ms 0010 → 1 ms 0011 → 500 us 0100 → 250 us 0101 → 125 us 0110 → 100 us 0111 → 62 us 1000 → 50 us 1001 → 40 us (d) 1010 → 31 us 1011 → 25 us 1100 → 20 us 1101 → 15 us 1110 → 12 us 1111 → 10 us

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET Name (Address) Bits Variable Name Mode Default value (0x0B) 7-6 unused r 0x00 unused

5 OcpOn rw 0x01 Enables overload current protection (OCP) for the PA:

0 → OCP disabled 1 → OCP enabled 4-0 OcpTrim rw 0x0b Trimming of OCP current: Imax = 45+5*OcpTrim [mA] if OcpTrim <= 15 (120 mA) / Imax = -30+10*OcpTrim [mA] if 15 < OcpTrim <= 27 (130 to 240 mA) Imax = 240mA for higher settings Default Imax = 100mA Registers for the Receiver RegLna (0x0C) 7-5 LnaGain rwx 0x01 LNA gain setting: 000 → reserved 001 → G1 = highest gain 010 → G2 = highest gain – 6 dB 011 → G3 = highest gain – 12 dB 100 → G4 = highest gain – 24 dB 101 → G5 = highest gain – 36 dB 110 → G6 = highest gain – 48 dB 111 → reserved Note: Reading this address always returns the current LNA gain (which may be different from what had been previously selected if AGC is enabled. 4-2 - r 0x00 unused 1-0 LnaBoost rw 0x00 Improves the system Noise Figure at the expense of Rx current consumption: 00 → Default setting, meeting the specification 11 → Improved sensitivity

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET Name (Address) Bits Variable Name Mode Default value (0x0d)

7 RestartRxOnCollision rw 0x00 Turns on the mechanism restarting the receiver automatically

if it gets saturated or a packet collision is detected 0 → No automatic Restart 1 → Automatic restart On 6 RestartRxWithoutPllLock wp 0x00 Triggers a manual Restart of the Receiver chain when set to 1. Use this bit when there is no frequency change, RestartRxWithPllLock otherwise. 5 RestartRxWithPllLock wp 0x00 Triggers a manual Restart of the Receiver chain when set to 1. Use this bit when there is a frequency change, requiring some time for the PLL to re-lock.

4 AfcAutoOn rw 0x00 0 → No AFC performed at receiver startup

1 → AFC is performed at each receiver startup

3 AgcAutoOn rw 0x01 0 → LNA gain forced by the LnaGain Setting

1 → LNA gain is controlled by the AGC

2 AgcOnPreamble rw 0x00 When set to 1, the AGC will adjust the LNA gain until the

preamble is detected, and fix LNA gain only when on a Preamble is detected. The size of the qualifying preamble is set in PreambleDetectSize. When set to 0, the AGC will adjust the LNA gain based on RSSI information

1 StartDemodOnPreamble rw 0x00 Condition required for the circuit to provide valid data to the

0 StartDemodOnRssi rw 0x00 Condition required for the circuit to provide valid data to the

(0x0e) 7-3 RssiOffset rw 0x00 Signed RSSI offset, to compensate for the possible losses/ gains in the front-end (LNA, SAW filter...) 1dB / LSB, 2‟s complement format 2-0 RssiSmoothing rw 0x02 Defines the number of samples taken to average the RSSI result: 000 → 2 samples used 001 → 4 samples used 010 → 8 samples used 011 → 16 samples used 100 → 32 samples used 101 → 64 samples used 110 → 128 samples used 111 → 256 samples used RegRssiCollision (0x0f) 7-0 RssiCollisionThreshold rw 0x0a Sets the threshold used to consider that an interferer is detected, witnessing a packet collision. 1dB/LSB (only RSSI increase) Default: 10dB RegRssiThresh (0x10) 7-0 RssiThreshold rw 0xff RSSI trigger level for the Rssi interrupt : - RssiThreshold / 2 [dBm] RegRssiValue (0x11) 7-0 RssiValue rwx - Absolute value of the RSSI in dBm, 0.5dB steps. RSSI = - RssiValue/2 [dBm]

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET Name (Address) Bits Variable Name Mode Default value (0x12) 7 unused r - unused 6-5 reserved rw 0x00 reserved 4-3 RxBwMant rw 0x02 Channel filter bandwidth control: 00 → RxBwMant = 16 10 → RxBwMant = 24 01 → RxBwMant = 20 11 → reserved 2-0 RxBwExp rw 0x05 Channel filter bandwidth control: FSK Mode: Rx BwMan t × 2RxBwEx p + 2 RegAfcBw (0x13) 7-5 reserved rw 0x00 reserved 4-3 RxBwMantAfc rw 0x01 RxBwMant parameter used during the AFC 2-0 RxBwExpAfc rw 0x03 RxBwExp parameter used during the AFC RegOokPeak (0x14) 7-6 reserved rw 0x00 reserved 5 BitSyncOn rw 0x01 Enables the Bit Synchronizer. 0 → Bit Sync disabled (not possible in Packet mode) 1 → Bit Sync enabled 4-3 OokThreshType rw 0x01 Selects the type of threshold in the OOK data slicer: 00 → fixed threshold 10 → average mode 01 → peak mode (default) 11 → reserved 2-0 OokPeakTheshStep rw 0x00 Size of each decrement of the RSSI threshold in the OOK demodulator: 000 → 0.5 dB 001 → 1.0 dB 010 → 1.5 dB 011 → 2.0 dB 100 → 3.0 dB 101 → 4.0 dB 110 → 5.0 dB 111 → 6.0 dB RegOokFix (0x15) 7-0 OokFixedThreshold rw 0x0C Fixed threshold for the Data Slicer in OOK mode Floor threshold for the Data Slicer in OOK when Peak mode is used RegOokAvg (0x16) 7-5 OokPeakThreshDec rw 0x00 Period of decrement of the RSSI threshold in the OOK demodulator: 000 → once per chip 001 → once every 2 chips 010 → once every 4 chips 011 → once every 8 chips 100 → twice in each chip 101 → 4 times in each chip 110 → 8 times in each chip 111 → 16 times in each chip 4 reserved rw 0x01 reserved 3-2 OokAverageOffset rw 0x00 Static offset added to the threshold in average mode in order to reduce glitching activity (OOK only): 00 → 0.0 dB 10 → 4.0 dB 01 → 2.0 dB 11 → 6.0 dB 1-0 OokAverageThreshFilt rw 0x02 Filter coefficients in average mode of the OOK demodulator: 00 → fC ≈ chip rate / 32.π 01 → fC ≈ chip rate / 8.π 10 → fC ≈ chip rate / 4.π 11 →fC ≈ chip rate / 2.π

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET Name (Address) Bits Variable Name Mode Default value reserved. Keep the Reset values. RegAfcFei (0x1a) 7-5 unused r - unused 4 AgcStart wp 0x00 Triggers an AGC sequence when set to 1. 3 reserved rw 0x00 reserved 2 unused - - unused 1 AfcClear wp 0x00 Clear AFC register set in Rx mode. Always reads 0.

0 AfcAutoClearOn rw 0x00 Only valid if AfcAutoOn is set

0 → AFC register is not cleared at the beginning of the automatic AFC phase 1 → AFC register is cleared at the beginning of the automatic AFC phase RegAfcMsb (0x1b) 7-0 AfcValue(15:8) rwx 0x00 MSB of the AfcValue, 2‟s complement format. Can be used to overwrite the current AFC value RegAfcLsb (0x1c) 7-0 AfcValue(7:0) rwx 0x00 LSB of the AfcValue, 2‟s complement format. Can be used to overwrite the current AFC value RegFeiMsb (0x1d) 7-0 FeiValue(15:8) rwx - MSB of the measured frequency offset, 2‟s complement RegFeiLsb (0x1e) 7-0 FeiValue(7:0) rwx - LSB of the measured frequency offset, 2‟s complement Frequency error = FeiValue x Fstep RegPreambleDete ct (0x1f) 7 PreambleDetectorOn rw 0x00 Enables Preamble detector when set to 1. The AGC settings supersede this bit during the startup / AGC phase. 0 → Turned off 1 → Turned on 6-5 PreambleDetectorSize rw 0x02 Number of Preamble bytes to detect to trigger an interrupt 00 → 1 byte 10 → 3 bytes 01 → 2 bytes 11 → Reserved 4-0 PreambleDetectorTol rw 0x00 Number or chip errors tolerated over PreambleDetectorSize. 4 chips per bit. RegRxTimeout1 (0x20) 7-0 TimeoutRxRssi rw 0x00 Timeout interrupt is generated TimeoutRxRssi*16*Tbit after switching to Rx mode if Rssi interrupt doesn‟t occur (i.e. RssiValue > RssiThreshold) 0x00: TimeoutRxRssi is disabled RegRxTimeout2 (0x21) 7-0 TimeoutRxPreamble rw 0x00 Timeout interrupt is generated TimeoutRxPreamble*16*Tbit after switching to Rx mode if Preamble interrupt doesn‟t occur 0x00: TimeoutRxPreamble is disabled RegRxTimeout3 (0x22) 7-0 TimeoutSignalSync rw 0x00 Timeout interrupt is generated TimeoutSignalSync*16*Tbit after the Rx mode is programmed, if SyncAddress doesn‟t occur 0x00: TimeoutSignalSync is disabled

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET Name (Address) Bits Variable Name Mode Default value (0x23) 7-0 InterPacketRxDelay rw 0x00 Additional delay befopre an automatic receiver restart is launched: Delay = InterPacketRxDelay*4*Tbit RC Oscillator registers RegOsc (0x24) 7-4 unused r - unused 3 RcCalStart rwp 0x00 Triggers the calibration of the RC oscillator when set. Always reads 0. RC calibration must be triggered in Standby mode. 2-0 ClkOut rw 0x05 Selects CLKOUT frequency: 000 → FXOSC 001 → FXOSC / 2 010 → FXOSC / 4 011 → FXOSC / 8 100 → FXOSC / 16 101 → FXOSC / 32 110 → RC (automatically enabled) 111 → OFF Packet Handling registers RegPreambleMsb (0x25) 7-0 PreambleSize(15:8) rw 0x00 Size of the preamble to be sent (from TxStartCondition fulfilled). (MSB byte) RegPreambleLsb (0x26) 7-0 PreambleSize(7:0) rw 0x03 Size of the preamble to be sent (from TxStartCondition fulfilled). (LSB byte) RegSyncConfig (0x27) 7-6 AutoRestartRxMode rw 0x02 Controls the automatic restart of the receiver after the reception of a valid packet (PayloadReady or CrcOk): 00 → Off 01 → On, without waiting for the PLL to re-lock 10 → On, wait for the PLL to lock (frequency changed) 11 → reserved

5 PreamblePolarity rw 0x00 Sets the polarity of the Preamble

0 → 0xAA (default) 1 → 0x55

4 SyncOn rw 0x01 Enables the Sync word generation and detection:

0 → Off 1 → On

3 FifoFillCondition rw 0x00 FIFO filling condition:

0 → if SyncAddress interrupt occurs 1 → as long as FifoFillCondition is set 2-0 SyncSize rw 0x03 Size of the Sync word: (SyncSize + 1) bytes, (SyncSize) bytes if ioHomeOn=1 RegSyncValue1 (0x28) 7-0 SyncValue(63:56) rw 0x55 1st byte of Sync word. (MSB byte) Used if SyncOn is set. RegSyncValue2 (0x29) 7-0 SyncValue(55:48) rw 0x55 2nd byte of Sync word Used if SyncOn is set and (SyncSize +1) >= 2. RegSyncValue3 (0x2a) 7-0 SyncValue(47:40) rw 0x55 3rd byte of Sync word. Used if SyncOn is set and (SyncSize +1) >= 3.

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET Name (Address) Bits Variable Name Mode Default value (0x2b) 7-0 SyncValue(39:32) rw 0x55 4th byte of Sync word. Used if SyncOn is set and (SyncSize +1) >= 4. RegSyncValue5 (0x2c) 7-0 SyncValue(31:24) rw 0x55 5th byte of Sync word. Used if SyncOn is set and (SyncSize +1) >= 5. RegSyncValue6 (0x2d) 7-0 SyncValue(23:16) rw 0x55 6th byte of Sync word. Used if SyncOn is set and (SyncSize +1) >= 6. RegSyncValue7 (0x2e) 7-0 SyncValue(15:8) rw 0x55 7th byte of Sync word. Used if SyncOn is set and (SyncSize +1) >= 7. RegSyncValue8 (0x2f) 7-0 SyncValue(7:0) rw 0x55 8th byte of Sync word. Used if SyncOn is set and (SyncSize +1) = 8. RegPacketConfig1 (0x30)

7 PacketFormat rw 0x01 Defines the packet format used:

0 → Fixed length 1 → Variable length 6-5 DcFree rw 0x00 Defines DC-free encoding/decoding performed: 00 → None (Off) 01 → Manchester 10 → Whitening 11 → reserved

4 CrcOn rw 0x01 Enables CRC calculation/check (Tx/Rx):

0 → Off 1 → On

3 CrcAutoClearOff rw 0x00 Defines the behavior of the packet handler when CRC check

fails: 0 → Clear FIFO and restart new packet reception. No PayloadReady interrupt issued. 1 → Do not clear FIFO. PayloadReady interrupt issued. 2-1 AddressFiltering rw 0x00 Defines address based filtering in Rx: 00 → None (Off) 01 → Address field must match NodeAddress 10 → Address field must match NodeAddress or BroadcastAddress 11 → reserved

0 CrcWhiteningType rw 0x00 Selects the CRC and whitening algorithms:

0 → CCITT CRC implementation with standard whitening 1 → IBM CRC implementation with alternate whitening

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET Name (Address) Bits Variable Name Mode Default value (0x31) 7 unused r - unused

6 DataMode rw 0x01 Data processing mode:

0 → Continuous mode 1 → Packet mode

5 IoHomeOn rw 0x00 Enables the ioHomeControl compatibility mode

0 → Disabled 1 → ioHome enabled

4 IoHomePowerFrame rw 0x00 reserved - Linked to ioHomeControl compatibility mode

3 BeaconOn rw 0x00 Enables the Beacon mode in Fixed packet format

2-0 PayloadLength(10:8) rw 0x00 Packet Length Most significant bits RegPayloadLength (0x32) 7-0 PayloadLength(7:0) rw 0x40 If PacketFormat = 0 (fixed), payload length. If PacketFormat = 1 (variable), max length in Rx, not used in Tx. RegNodeAdrs (0x33) 7-0 NodeAddress rw 0x00 Node address used in address filtering. RegBroadcastAdrs (0x34) 7-0 BroadcastAddress rw 0x00 Broadcast address used in address filtering. RegFifoThresh (0x35)

7 TxStartCondition rw 0x00 Defines the condition to start packet transmission :

0 → FifoLevel (i.e. the number of bytes in the FIFO exceeds FifoThreshold) 1 → FifoEmpty goes low(i.e. at least one byte in the FIFO) 6 unused r - unused 5-0 FifoThreshold rw 0x0f Used to trigger FifoLevel interrupt, when: nbr of bytes in FIFO >= FifoThreshold + 1 Sequencer registers

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET Name (Address) Bits Variable Name Mode Default value (0x36)

7 SequencerStart t 0x00 Controls the top level Sequencer

When set to „1‟, executes the “Start” transition. The sequencer can only be enabled when the chip is in Sleep or Standby mode.

6 SequencerStop t 0x00 Forces the Sequencer to go to Idle state

Always reads „0‟

5 SequencerLowPowerMode rw 0x00 Selects chip mode in LowPower state:

0: Stdby mode 1: Sleep mode 4-3 SequencerTransitionFromI dle rw 0x00 Control state-machine transition from the Idle state: 00: to LowPower or Idle state on a SequencerStart command, depending on SequencerLowPowerState 01: to Receive state on a SequencerStart command 10: to Transmit state on a SequencerStart command 11: to WaitForFifo on a SequencerStart command

2 SequencerLowPowerState rw 0x00 Defines the low power state of the Sequencer, reached at the

end of any action (transmission, reception, etc...) 0: to Idle state 1: to LowPower state

1 SequencerTransitionFromL

rw 0x00 Control the Sequencer transition from the LowPower state: 0: to Transmit state on a Timer 1 interrupt 1: to Receive state on a Timer 1 interrupt

0 SequencerTransitionFromT

rw 0x00 Control the Sequencer transition from the Transmit state: 0: to LowPower or Idle state on a PacketSent interrupt, depending on SequencerLowPowerState 1: to Receive state on a PacketSent interrupt

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET Name (Address) Bits Variable Name Mode Default value (0x37) 7-5 SequencerTransitionFrom Receive rw 0x00 Control the Sequencer transition from the Receive state 000 and 111: unused 001: to PacketReceived state on a PayloadReady interrupt 010: to LowPower or Idle state on a PayloadReady interrupt, depending on SequencerLowPowerState 011: to PacketReceived state on a CrcOk interrupt. If the CRC is disabled the PayloadReady interrupt, firing when enough bytes are received, will drive the Sequencer to the PacketReceived state, too. 100: to Idle state on a Rssi interrupt 101: to Idle state on a SyncAddress interrupt 110: to Idle state on a PreambleDetect interrupt Irrespective of this setting, transition to LowPower or Idle state on a Timer2 interrupt, depending on SequencerLowPowerState 4-3 SequencerTransitionFrom RxTimeout rw 0x00 Control the state-machine transition from the Receive state on a RxTimeout interrupt (and on PayloadReady if SequencerTransitionFromReceive = 011): 00: to ReceiveRestart 01: to Transmit 10: to LowPower or Idle state, depending on SequencerLowPowerState 11: to Idle state 2-0 SequencerTransitionFrom PacketReceived rw 0x00 Control the state-machine transition from the PacketReceived state: 000: to Idle state 001: to Transmit on a FifoEmpty interrupt 010: to LowPower or Idle state on FifoEmpty, depending on SequencerLowPowerState 011: to Receive via FS mode, if frequency was changed 100: to Receive state (no frequency change) RegTimerResol (0x38) 7-4 unused r - unused 3-2 Timer1Resolution rw 0x00 Resolution of Timer 1 00: Timer1 disabled 01: 64 us 10: 4.1 ms 11: 262 ms 1-0 Timer2Resolution rw 0x00 Resolution of Timer 2 00: Timer2 disabled 01: 64 us 10: 4.1 ms 11: 262 ms RegTimer1Coef (0x39) 7-0 Timer1Coefficient rw 0xf5 Multiplying coefficient for Timer 1 RegTimer2Coef (0x3a) 7-0 Timer2Coefficient rw 0x20 Multiplying coefficient for Timer 2 Services registers

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET Name (Address) Bits Variable Name Mode Default value (0x3b)

7 AutoImageCalOn rw 0x01 Controls the Image calibration mechanism

0 → Calibration of the receiver depending on the temperature is disabled 1 → Calibration of the receiver depending on the temperature enabled. 6 ImageCalStart wp - Triggers the IQ and RSSI calibration when set. 5 ImageCalRunning r 0x00 Set to 1 while the Image and RSSI calibration are running. Toggles back to 0 when the process is completed 4 unused r - unused

3 TempChange r 0x00 IRQ flag witnessing a temperature change exceeding

TempThreshold since the last Image and RSSI calibration: 0 → Temperature change lower than TempThreshold 1 → Temperature change greater than TempThreshold 2-1 TempThreshold rw 0x01 Temperature change threshold to trigger a new I/Q calibration 00 → 5 °C 01 → 10 ° C 10 → 15 ° C 11 → 20 ° C

0 TempMonitorOff rw 0x00 Controls the temperature monitor operation:

0 → Temperature monitoring done in all modes except Sleep and Standby 1 → Temperature monitoring stopped. RegTemp (0x3c) 7-0 TempValue r - Measured temperature -1° C per Lsb Needs calibration for absolute accuracy RegLowBat (0x3d) 7-4 unused r - unused

3 LowBatOn rw 0x00 Low Battery detector enable signal

0 → LowBat detector disabled 1 → LowBat detector enabled 2-0 LowBatTrim rw 0x02 Trimming of the LowBat threshold: 000 → 1.695 V 001 → 1.764 V 010 → 1.835 V (d) 011 → 1.905 V 100 → 1.976 V 101 → 2.045 V 110 → 2.116 V 111 → 2.185 V Status registers

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET Name (Address) Bits Variable Name Mode Default value (0x3e)

7 ModeReady r - Set when the operation mode requested in Mode, is ready

• Sleep: Entering Sleep mode - Standby: XO is running - FS: PLL is locked - Rx: RSSI sampling starts - Tx: PA ramp-up completed Cleared when changing the operating mode. 6 RxReady r - Set in Rx mode, after RSSI, AGC and AFC. Cleared when leaving Rx. 5 TxReady r - Set in Tx mode, after PA ramp-up. Cleared when leaving Tx. 4 PllLock r - Set (in FS, Rx or Tx) when the PLL is locked. Cleared when it is not. 3 Rssi rwp - Set in Rx when the RssiValue exceeds RssiThreshold. Cleared when leaving Rx or setting this bit to 1.

2 Timeout r - Set when a timeout occurs

Cleared when leaving Rx or FIFO is emptied. 1 PreambleDetect rwp - Set when the Preamble Detector has found valid Preamble. bit clear when set to 1 0 SyncAddressMatch rwp - Set when Sync and Address (if enabled) are detected. Cleared when leaving Rx or FIFO is emptied. This bit is read only in Packet mode, rwc in Continuous mode RegIrqFlags2 (0x3f) 7 FifoFull r - Set when FIFO is full (i.e. contains 66 bytes), else cleared.

6 FifoEmpty r - Set when FIFO is empty, and cleared when there is at least 1

byte in the FIFO.

5 FifoLevel r - Set when the number of bytes in the FIFO strictly exceeds

FifoThreshold, else cleared. 4 FifoOverrun rwp - Set when FIFO overrun occurs. (except in Sleep mode) Flag(s) and FIFO are cleared when this bit is set. The FIFO then becomes immediately available for the next transmission / reception. 3 PacketSent r - Set in Tx when the complete packet has been sent. Cleared when exiting Tx 2 PayloadReady r - Set in Rx when the payload is ready (i.e. last byte received and CRC, if enabled and CrcAutoClearOff is cleared, is Ok). Cleared when FIFO is empty. 1 CrcOk r - Set in Rx when the CRC of the payload is Ok. Cleared when FIFO is empty.

0 LowBat rwp - Set when the battery voltage drops below the Low Battery

threshold. Cleared only when set to 1 by the user. IO control registers

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET Name (Address) Bits Variable Name Mode Default value (0x40) 7-6 Dio0Mapping rw 0x00 Mapping of pins DIO0 to DIO5 See Table 26 for mapping in Continuous mode See Table 27 for mapping in Packet mode 5-4 Dio1Mapping rw 0x00 3-2 Dio2Mapping rw 0x00 1-0 Dio3Mapping rw 0x00 RegDioMapping2 (0x41) 7-6 Dio4Mapping rw 0x00 5-4 Dio5Mapping rw 0x00 3-1 reserved rw 0x00 reserved. Retain default value

0 MapPreambleDetect rw 0x00 Allows the mapping of either Rssi Or PreambleDetect to the

DIO pins, as summarized on Table 26 and Table 27 0 → Rssi interrupt 1 → PreambleDetect interrupt Version register RegVersion (0x42) 7-0 Version r 0x21 Version code of the chip. Bits 7-4 give the full revision number; bits 3-0 give the metal mask revision number. Additional registers RegAgcRef (0x43) 7-6 unused r - unused 5-0 AgcReferenceLevel rw 0x13 Sets the floor reference for all AGC thresholds RegAgcThresh1 (0x44) 7-5 unused r - unused 4-0 AgcStep1 rw 0x0e Defines the 1st AGC Threshold RegAgcThresh2 (0x45) 7-4 AgcStep2 rw 0x05 Defines the 2nd AGC Threshold: 3-0 AgcStep3 rw 0x0b Defines the 3rd AGC Threshold: RegAgcThresh3 (0x46) 7-4 AgcStep4 rw 0x0d Defines the 4th AGC Threshold: 3-0 AgcStep5 rw 0x0b Defines the 5th AGC Threshold: RegTcxo (0x58) 7-5 reserved rw 0x00 reserved. Retain default value

4 TcxoInputOn rw 0x00 Controls the crystal oscillator

0 → Crystal Oscillator with external Crystal 1 → External clipped sine TCXO AC-connected to XTA pin 3-0 reserved rw 0x09 Reserved. Retain default value. RegPaDac (0x5a) 7-3 reserved rw 0x10 reserved. Retain default value 2-0 PaDac rw 0x04 Enables the +20dBm option on PA_BOOST pin 0x04 → Default value 0x07 → +20dBm on PA_BOOST when OutputPower=1111 RegPll (0x5c) 7-6 PllBandwidth rw 0x03 Controls the PLL bandwidth: 00 → 75 kHz 10 → 225 kHz 01 → 150 kHz 11 → 300 kHz 5-0 reserved rw 0x10 reserved. Retain default value

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET Name (Address) Bits Variable Name Mode Default value (0x5e) 7-6 PllBandwidth rw 0x03 Controls the Low Phase Noise PLL bandwidth: 00 → 75 kHz 10 → 225 kHz 01 → 150 kHz 11 → 300 kHz 5-0 reserved rw 0x10 reserved. Retain default value RegFormerTemp (0x6c) 7-0 FormerTemp rwx - Temprature saved during the latest IQ (RSSI and Image) calibrated. Same format as TempValue in RegTemp. RegBitrateFrac (0x70) 7-4 unused r 0x00 unused 3-0 BitRateFrac rw 0x00 Fractional part of the bit rate divider (Only valid for FSK) If BitRateFrac> 0 then: BitRate(15,0) + -B----i--t--r--a- - --t--e---F- - --r--a- - --c-

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W WIRELESS & SENSING DATASHEET 7. Application Information 7.1. Crystal Resonator Specification Table 31 shows the crystal resonator specification for the crystal reference oscillator circuit of the RFM66W. This specification covers the full range of operation of the RFM66W and is employed in the reference design. Table 31 Crystal Specification Symbol FXOSC XTAL Frequency - 32 - MHz RS XTAL Serial Resistance - 30 140 ohms C0 XTAL Shunt Capacitance - 2.8 7 pF CFOOT External Foot Capacitance On each pin XTA and XTB 8 15 22 pF CLOAD Crystal Load Capacitance 6 - 12 pF Notes - the initial frequency tolerance, temperature stability and ageing performance should be chosen in accordance with the target operating temperature range and the receiver bandwidth selected. - the loading capacitance should be applied externally, and adapted to the actual Cload specification of the XTAL. 7.2. Reset of the Chip A power-on reset of the RFM66W is triggered at power up. Additionally, a manual reset can be issued by controlling pin 6. 7.2.1. POR If the application requires the disconnection of VDD from the RFM66W, despite of the extremely low Sleep Mode current, the user should wait for 10 ms from of the end of the POR cycle before commencing communications over the SPI bus. Pin 6 (Reset) should be left floating during the POR sequence. VDD Pin 6 (output) Undefined Wait for 10 ms Chip is ready from this point on Figure 37. POR Timing Diagram Please note that any CLKOUT activity can also be used to detect that the chip is ready.

Figure 38. Manual Reset Timing Diagram Note whilst pin 6 is driven high, an over current consumption of up to ten milliamps can be seen on VDD.

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W 7.3. Reference Designs Please contact your representative for evaluation tools, reference designs and design assistance. Note that all schematics shown in this section are full schematics, listing ALL required components, including decoupling capacitors. Figure 41:+20dBm Schematic

Figure 43. Example CRC Code

Figure 44. Example Temperature Reading

Figure 42. S2 Package Outline Drawing

Tel: +86-755-82973805 Fax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM66W A 9. Ordering Information DRFM66W —868 S2 P/N: RFM66W-868S2 RFM66W module at 868MHz band, SMD Package P/N: RFM66W-915S2 RFM66W module at 915MHz band, SMD PackageV Package Operation Band Mode Type HOPE MICROELECTRONICS CO.,LTD Add: 2/F, Building 3, Pingshan Private Enterprise Science and Technology Park, Lishan Road, XiLi Town, Nanshan District, Shenzhen, Guangdong, China Tel: 86-755-82973805 Fax: 86-755-82973550 Email: sales@hoperf.com Website: http://www.hoperf.com http://www.hoperf.cn This document may contain preliminary information and is subject to change by Hope Microelectronics without notice. Hope Microelectronics assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of Hope Microelectronics or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in the direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MECHANTABILITY OR FITNESS FOR A ARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT. ©2006, HOPE MICROELECTRONICS CO.,LTD. All rights reserved.