RFM43B

DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 56

Technical content

Features

Applications

Description

The RFM42B/43B offers advanced radio features including adjustable power +13dBm on the RFM43B and +1 to +20dBm are made in 3dB steps.The RFM42B/43B's high level of integration offers reduced BOM cost while si mplifying the overall system design. The RFM42B’s Industry leading +20dBm output power ensures link performance. Additional system features such as an automatic wake-up timer, low battery detector, 64 byte TX FIFO, and automatic packet handling reduce overall current consumption and al low the use of lower-cost system MCUs. An integrated temperature sensor, general purpose ADC, power-on-reset (POR), and GPIOs further reduce overall system cost and size. The direct digital transmit modulation and automatic PA power ramping ensure precise transmit modulation and reduced spectral spreading ensuring compliance with global regulations including FCC,ETSI regulations. An easy-to-use calculator is provided to quickly configure the radio settings, simplifying customer's system design and reducing time to market. Frequency range 433/868/915MHz ISM bands Output Power Range +1 to +20dBm (RFM42B) –8 to +13dBm (RFM43B) Low Power Consumption RFM42B 85 mA @ +20 dBm RFM43B 30 mA @ +13 dBm Data Rate = 0.123 to 256 kbps FSK, GFSK, and OOK modulation Power Supply = 1.8 to 3.6 V Ultra low power shutdown mode Wake-up timer Integrated 32 kHz RC or 32 kHz XTAL Integrated voltage regulators Configurable packet handler TX 64 byte FIFO Low battery detector Temperature sensor and 8-bit ADC –40 to +85 °C temperature range Integrated voltage regulators Frequency hopping capability On-chip crystal tuning Low cost Power-on-reset (POR) Remote control Home security & alarm Telemetry Personal data logging Toy control Wireless PC peripherals Remote meter reading Remote keyless entry Home automation Industrial control Sensor networks Health monitors RFM42B/43B Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com V1.0 14-PIN DIP & 16-PIN SMD package HopeRF's RFM42B/43B are highly integrated, low cost,433/868/915MHZ wireless ISM transmitters module. output levels of –8 to on the RFM42B.Power adjustments extended range and improved

T ABLE OF C ONTENT S Section Page Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com . . .11 .10 .29 . .35 . .44

Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

1. Electrical Specifications

Table 1. DC Characteristics

Table 2. Synthesizer AC Electrical Characteristics XOSC running to any frequency.

Table 3. Transmitter AC Electrical Characteristics

Table 4. Auxiliary Block Specifications

15 MHz, 10 MHz, 4 MHz,

30 MHz XTAL Start-Up time t

30 MHz XTAL Cap

Table 5. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ) Table 6. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2)

Table 7. Absolute Maximum Ratings on TX output pin. Caution: ESD sensitive device.

an ideal solution for battery powered applications. shaped by a Gaussian low-pass filter to reduce unwanted spectral content. PA output power can be configured between –8 and +13 dBm in 3dB steps. ramp-up and ramp-down control to reduce unwanted spectral spreading. A standard 4-pin SPI bus is used to communicate with an external microcontroller. (Auxiliary Blocks) includes the temperature sensor, general purpose ADC, and low-battery detector. Table 8. Operating Modes *Note: Using RFM43B at +13dBm using recommended reference design. HopeRF's RFM42B/43B are highly integrated,low cost,433/868/915MHz wireless ISM transmitters module .

The RFM42B/43B communicates with the host MCU over a standard 3-wire SPI interface: SCLK, SDI, and nSEL. SCLK rate is flexible with a maximum rate of 10 MHz. Figure 1. SPI Timing read from the selected regi ster will be available on the SDO output pin. The READ function is shown in Figure 2. last data bit clocked out (D0). When nSEL goes high the SDO output pin will be pulled high by internal pullup. Table 9. Serial Interface Timing Parameters

3.2.1. SHUTDOWN State The SHUTDOWN state is the lowest current consumption state of the device with nominally less than 15 nA of current consumption. The SHUTDOWN state may be entere d by driving the SDN pin high. The SDN pin should be held low in all states e xcept the SHUTDOWN state. In the SHUTDOWN state, the contents of the registers are lost and there is no SPI access. When the chip is connected to the power supply, a POR will be initiated after the falling edge of SDN. 3.2.2. IDLE State There are five different modes in the IDLE state which may be selected by "Register 07h. Operating Mode and Function Control 1". All modes have a tradeoff between current consumption and response time to TX mode. This tradeoff is shown in Table 10. After the POR event, SWRESET, or exiting from the SHUTDOWN state the chip will default to the IDLE-READY mode. After a POR event the inte rrupt registers must be read to properly enter the SLEEP , SENSOR, or STANDBY mode and to control the 32 kHz clock correctly. 3.2.2.1. STANDBY Mode STANDBY mode has the lowest current consumption of th e five IDLE states with only the LPLDO enabled to maintain the register values. In this mode the regist ers can be accessed in both read and write mode. The STANDBY mode can be entered by writ ing 0h to "Register 07h. Operating Mode and Function Control 1". If an interrupt has occurred (i.e., the nIRQ pin = 0) the interr upt registers must be read to achieve the minimum current consumption. Additionally, the ADC should not be selected as an input to th e GPIO in this mode as it will cause excess current consumption. 3.2.2.2. SLEEP Mode In SLEEP mode the LPLDO is enabled along with the Wake -Up-Timer, which can be used to accurately wake-up the radio at specified intervals. See "7.6. Wake-Up Timer" for more information on the Wake - Up - Timer. SLEEP mode is entered by setting enwt = 1 (40h) in "Register 07h. Operating Mode and Function Control 1". If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current consumption. Also, the ADC sh ould not be selected as an input to the GPIO in this mode as it will cause excess current consumption. 3.2.2.3. SENSOR Mode In SENSOR Mode either the Low Battery Detector, Temperature Sensor, or both may be enabled in addition to the LPLDO and Wake-Up-Timer. The Low Battery Detector can be enabled by setting enlbd = 1 in "Register 07h. Detector" for more information on these features. If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current consumption. 3.2.2.4. READY Mode READY Mode is designed to give a fast transition time to TX mode with reasonable current consumption. In this mode the Crystal oscillator remains enab led reducing the time required to swit ch to TX mode by eliminating the crystal start-up time. READY mode is entered by setting xton = 1 in "Register 07h. Operating Mode and Function Control 1". To achieve the lowest curr ent consumption state the crystal osc illator buffer should be disabled in “Register 62h. Crystal Oscillator Control and Test.” 3.2.2.5. TUNE Mode In TUNE Mode the PLL remains enabled in addition to the other blocks enabled in the IDLE modes. This will give the fastest response to TX mode as the PLL will re main locked but it results in the highest current consumption. This mode of operation is designed for frequency hopp ing spread spectrum syste ms (FHSS). TUNE mode is entered by setting pllon = 1 in "Register 07h. Operating Mode and Function Control 1". It is not necessary to set xton to 1 for this mode, the internal state machine automatically enables the crystal oscillator. Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

3.2.3. TX State The TX state may be entered from any of the IDLE modes when the txon bit is set to 1 in "Register 07h. Operating Mode and Function Control 1". A built-in sequencer takes care of all the actions re quired to transition between states from enabling the crystal o scillator to ramping up the PA. The following sequence of events will occur automatically when going from STANDBY mode to TX mode by setting the txon bit. 1. Enable the main digital LDO and the Analog LDOs. 2. Start up crystal oscillator and wait unt il ready (controlled by an internal timer). 3. Enable PLL. 4. Calibrate VCO (this action is skipped when the vcocal bit is “0”, default value is “1”). 5. Wait until PLL settles to required transmit frequency (controlled by timer). 6. Activate power amplifier and wait until power ramping is completed (controlled by an internal timer). 7. Transmit packet. Steps in this sequence may be eliminated depending on which IDLE mode the chip is configured to prior to setting the txon bit. By default, the VCO and PLL are calibrated every time the PLL is enabled. 3.2.4. Device Status The operational status of the chip can be read from "Register 02h. Device Status". Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

02 R Device Status ffovfl ffunfl Reser ved Reserved freqerr cps[1] cps[0] —

Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

3.3. Interrupts The RFM42B/43B is capable of generating an interrupt sign al when certain events occur. The chip notifies the microcontroller that an interrupt event has occurred by setting the nIRQ output pin LOW = 0. This interrupt signal will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits) shown below occur. The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Register(s) (Registers 03h–04h) containing the active Interrupt Status bit. The nIRQ output signal will then be reset until the next change in status is detected. The interrupts must be enabled by the corresponding enable bit in the Interrupt Enable Registers (Registers 05h–06h). All enabled interrupt bits will be cleare d when the microcontroller reads the interrupt status register. If the interrupt is not enabled when the event occurs it will not trigger the nIRQ pin, but the status may still be read at anytime in the Interrupt Status registers. See “RFM42B/43B Register Descriptions” for a complete list of interrupts. Add R/W Function/Descript ion D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

03 R Interrupt Status 1 ifferr itxffafull itx ffaem Reserved iext ipksent Reserved Reserved —

04 R Interrupt Status 2 Reserved Reserved Reserved Reserved iwut ilbd ichiprdy ipor —

05 R/W Interrupt Enable 1 enfferr entxffafull entxf faem Reserved enext enpksent Reserved Reserved 00h

06 R/W Interrupt Enable 2 Reserved Reserved R eserved Reserved enwut enlbd enchiprdy enpor 01h

Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

and the internal sequencer will properly transition the part from its current mode. Figure 6. TX Timing

3.5. Frequency Control For calculating the nec essary frequency register settings it is re commended that custom ers use the HOPERF Register Calculator worksheet (in Microsoft Excel) available on r a simple method to quickly determi ne the correct settings based on the application requirements. The following information can be used to calculated these values manually. 3.5.1. Frequency Programming In order to transmit an RF signal, the desired channel frequency, f carrier , m ust be programmed into the RFM42B/43B . Note that this frequency is the center frequency of the desired channel. The carrier frequency is generated by a Fractional-N Synthesi zer, using 10 MHz both as the reference frequency and the clock of the (3 rd order) ΔΣ modulator. This modulator uses modulo 64000 accumulators. This design was made to obtain the desired frequency resolution of the synthesizer. The overall division ratio of the feedback loop consist of an integer part (N) and a fractional part (F).In a generic sense, the output frequency of the synthesizer is as follows: The fractional part (F) is determined by three differ ent values, Carrier Frequency (fc[15:0]), Frequency Offset (fo[8:0]), and Frequency Deviation (fd[7:0]). Due to the fi ne resolution and high loop bandwidth of the synthesizer, FSK modulation is applied inside the loop and is done by varying F according to the incoming data; this is discussed further in "3.5.4. Frequency Deviation" . Also, a fixed offset can be added to fine-tune the carrier frequency and counteract crystal tolerance errors. For simplicity assume that only the fc[15:0] register will determine the fractional component. The equation for selection of the carrier frequency is shown below: The integer part (N) is determined by fb[4:0]. Additio nally, the output frequency can be halved by connecting a ÷2 divider to the output. This divider is not inside the loop and is controlled by the hbsel bit in "Register 75h. Frequency Band Select". This effect ively partitions the entire 240–960 MHz frequency range into two separate bands: High Band (HB) for hbsel = 1, and Low Band (LB) for hbsel = 0. The valid range of fb[4:0] is from 0 to 23. If a higher value is written into the regist er, it will default to a value of 23. Th e integer part has a fixed offset of 24 added to it as shown in the formula above. Table 11 demonstrates the selection of fb[4:0] for the corresponding frequency band. After selection of the fb (N) the fractional component may be solved with the following equation: fb and fc are the actual numbers stored in the corresponding registers. Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

73 R/W Frequency Offset 1 fo[7] fo[6] fo[5] fo[4] fo[3] fo[2] fo[1] fo[0] 00h

74 R/W Frequency Offset 2 fo[9] fo[8] 00h

75 R/W Frequency Band Select sbsel hbsel fb[4] fb[3] fb[2] fb[1] fb[0] 35h

76 R/W Nominal Carrier

fc[15] fc[14] fc[13] fc[12] fc[11] fc[10] fc[9] fc[8] BBh

77 R/W Nominal Carrier

fc[7] fc[6] fc[5] fc[4] fc[3] fc[2] fc[1] fc[0] 80h ) ( 10F N MHzf OUT ) ( ) 1 ( 10F NhbselMHzf carrier 64000 ] 0 : 15 [24 ] 0 : 4 [ ( * ) 1 ( * 10fcfbhbselMHzf TX   ffc TX Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com the product website. These methods offe

Table 11. Frequency Band Selection

3.5.2. Easy Frequency Programming for FHSS While Registers 73h–77h may be used to program the carrie r frequency of the RFM42B/43B , it is often easier to think in terms of “channels” or “channel numbers” rather than an absolute frequency value in Hz. Also, there may be some timing-critical applications (such as for Frequen cy Hopping Systems) in whic h it is desirable to change frequency by programming a single register. Once the chan nel step size is set, the frequency may be changed by a single register corresponding to the channel number. A nominal frequency is first set using Registers 73h–77h, as described above. Registers 79h and 7Ah are then used to set a channel step size and channel number, relative to the nominal setting. The Frequency Hopping Step Size (fhs[7:0]) is set in increments of 10 kHz with a maximum channel step size of 2.56 MHz. The Frequency Hopping Channel Select Register then selects channels based on multiples of the step size. For example, if the nominal frequency is set to 900 MHz using Registers 73h–77h, the channel step size is set to 1 MHz using "Register 7Ah. Frequency Hopping Step Si ze," and "Register 79h. Frequency Hopping Channel Select" is set to 5d, the resulting carrier frequency would be 905 MHz. Once the nominal frequency and channel step size are programmed in the registers, it is only necessary to program the fhch[7:0] register in order to change the frequency. 3.5.3. Automatic State Transition for Frequency Change If registers 79h or 7Ah are changed in TX mode, the state ma chine will automatically tr ansition the chip back to TUNE and change the frequency. This fe ature is useful to reduce the number of SPI commands required in a Frequency Hopping System. This in tu rn reduces microcontroller activity, reducing current consumption. The exception to this is during TX FIFO mode. If a frequency change is initiated during a TX packet, then the part will complete the current TX packet and will only change the frequency for subsequent packets. 3.5.4. Frequency Deviation The peak frequency deviation is configurable from ±0.625 to ±320 kHz. The Frequency Deviation ( Δf) is controlled by the Frequency Deviation Register (fd), address 71 and 72h, and is independent of the carrier frequency setting. When enabled, regardless of the setting of the hbsel bit (high band or low band), the resolution of the frequency deviation will remain in increm ents of 625 Hz. When using frequency modu lation the carrier frequency will deviate from the nominal center channel carrier frequency by ±Δf: Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

79 R/W Frequency Hopping Channel

fhch[7] fhch[6] fhch[5 ] fhch[4] fhch[3] fhch[2] fhch[1] fhch[0] 00h 7A R/W Frequency Hopping Step Size fhs[7] fhs[6] fhs[5] fhs[4] fh s[3] fhs[2] fhs[1] fhs[0] 00h ) 10 ] 0 : 7 [ ( ] 0 : 7 [kHzfhchfhs FnomF carrier Hz ffd 625] 0 : 8 [ f peak deviation Hzfd f 625 ] 0 : 8 [ Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

Figure 7. Frequency Deviation see "4.1. Modulation Type" for further details.

72 R/W Frequency Deviation fd[7] fd[6] f d[5] fd[4] fd[3] fd[2] fd[1] fd[0] 20h

3.5.5. Frequency Offset Adjustment A frequency offset can be adjusted manually by fo[9:0] in registers 73h and 74h. The frequency offset adjustment is implemented by shifting the Synthesizer Local Oscillator frequency. This register is a signed register so in order to get a negative offset it is necessary to take the twos co mplement of the positive offs et number. The offset can be calculated by the following: The adjustment range in high band is ±160 kHz and in low band it is ±80 kHz. For example to compute an offset of +50 kHz in high band mode fo[9:0] should be set to 0A0h. For an offset of –50 kHz in high band mode the fo[9:0] register should be set to 360h. 3.5.6. TX Data Rate Generator The data rate is configurable between 0.123–256 kbps. For data rates below 30 kbps the ”txdtrtscale” bit in register 70h should be set to 1. When higher data rates are used this bit should be set to 0. The TX date rate is determined by the following formula in kbps: Add R/W Function/Descript ion D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

73 R/W Frequency Offset fo[7] fo[6] fo[5] fo[4] fo[3] fo[2] fo[1] fo[0] 00h

74 R/W Frequency Offset fo[9] fo[8] 00h

Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def. 6E R/W TX Data Rate 1 txdr[15] txdr[14] txdr[13] txdr[12] txdr[11] txdr[10] txdr[9] txdr[8] 0Ah 6F R/W TX Data Rate 0 txdr[7] txdr[6] txdr[ 5] txdr[4] txdr[3] txdr[2] txdr[1] txdr[0] AAh ] 0 : 9 [ ) 1 ( 25 . 156fohbsel HzsetDesiredOff ) 1 ( 25 . 156] 0 : 9 [   hbsel Hz setDesiredOfffo DR_TX (kbps) txdr 15:0 1 MHz 16 5 txdtrtscale+ txdr[15:0] DR_TX(kbps) 2 16 5 txdtrtscale+ Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

FSK and GFSK for a Data Rate of 64 kbps. The time domain plots demonstrate the effects of the Gaussian filtering. obtain an unmodulated carrier signal by setting modtyp[1:0] = 00. Figure 8. FSK vs. GFSK Spectrums

00 Unmodulated Carrier

01 OOK

10 FSK

11 GFSK (enable TX Data CLK when direct mode is used)

4.2. Modulation Data Source The RFM42B/43B may be configured to obtain its modulation data from one of three different sources:FIFO mode, Direct Mode, and from a PN9 mode. In Direct Mode, the TX modulation data may be obtained from several different input pins. These options are set through the dtm od[1:0] field in "Register 7 1h. Modulation Mode Control 2." 4.2.1. FIFO Mode In FIFO mode, the transmit data is stored in integrat ed FIFO register memory. The FIFOs are accessed via "Register 7Fh. FIFO Access," and are most efficiently ac cessed with burst read/write operation as discussed in "3.1. Serial Peripheral Interface (SPI)". In TX mode, the data bytes stored in FIFO memory ar e "packaged" together with other fields and bytes of information to construct the final transmit packet structure. These other potential fields include the Preamble, Sync word, Header, CRC checksum, et c. The configuration of the packet struct ure in TX mode is determined by the Automatic Packet Handler (if enabled), in conjunction with a variety of Packet Handler Registers (see Table12). If the Automatic Packet Handle r is disabled, the entire desired pack et structure should be loaded into FIFO memory; no other fields (such as Preamble or Sync word are automatically added to the bytes stored in FIFO memory). For further information on the configuration of the FIFOs for a specific application or packet size, see "6. Data Handling and Packet Handler" . When in FIFO mode, the chip will auto matically exit the TX Stat e when either the ipksent or ipkvalid interrupt occurs. The chip will return to the ID LE mode state progr ammed in "Register 07h. Op erating Mode and Function Control 1". For example, the chip may be placed into TX mode by setting the txon bit, but with the pllon bit additionally set. The chip will transmit all of the contents of the FIFO and the ipksent interrupt will occur. When this interrupt event occurs, the chip will clear the txon bit and return to TUNE mode, as indicated by the set state of the pllon bit. If no other bits are additionally set in register 07h (besides txon initially), then the chip will return to the STANDBY state. Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

71 R/W Modulation Mode

trclk[1] trclk[0] dtmod[1] dtmod[0] eninv fd[8] modtyp[1] modtyp[0] 00h dtmod[1:0] Data Source

00 Direct Mode using TX Data via GPIO pin (GPIO configuration required)

01 Direct Mode using TX Data via SDI pin (only when nSEL is high)

10 FIFO Mode

11 PN9 (internally generated)

Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

4.2.2. Direct Mode For legacy systems that perform packet handling within an MCU or other baseband chip, it may not be desirable to use the FIFO. For this scenario, a Direct Mode is provided which bypasses the FIFOs entirely. In TX direct mode, the TX modulation data is applied to an input pin of the chip and processed in "real time" (i.e., not stored in a register for transmission at a later time). A variety of pins may be configured for use as the TX Data input function. Furthermore, an additional pin may be required for a TX Clock output function if GFSK modulation is desired (only the TX Data input pin is required for FSK). Two options for the source of the TX Data are available in the dtmod[1:0] field, and various configurations for the source of the TX Data Clock may be selected through the trclk[1:0] field. The eninv bit in SPI Register 71h will in vert the TX Data; this is most likely useful for diagnostic and testing purposes. 4.2.2.1. Direct Synchronous Mode In TX direct mode, the chip may be configured for synchronous or asynchronous modes of modulation. In direct synchronous mode, the RFIC is configured to provide a TX Clock signal as an output to the external device that is providing the TX Data stream. This TX Clock signal is a square wave with a frequency equal to the programmed data rate. The external modulation so urce (e.g., MCU) must a ccept this TX Clock signal as an input and respond by providing one bit of TX Data back to the RFIC, syn chronous with one edge of the TX Clock signal. In this fashion, the rate of the TX Data input stream from the external source is controlled by the programmed data rate of the RFIC; no TX Data bits are made available at the inpu t of the RFIC until requested by another cycle of the TX Clock signal. The TX Data bits supplied by the external source are transmitted directly in real-time (i.e., not stored internally for later transmission). All modulation types (FSK/GFSK/ OOK) are valid in TX direct synchronous mode. As will be discussed in the next section, there are limits on modulation types in TX direct asynchronous mode. 4.2.2.2. Direct Asynchronous Mode In TX direct asynchronous mode, the RFIC no longer cont rols the data rate of the TX Data input stream. Instead, the data rate is controlled only by the external TX Data source; the RFIC simply accepts the data applied to its TX Data input pin, at whatever rate it is supplied. This means that there is no longer a need for a TX Clock output signal from the RFIC, as there is no synchronous "hand shaking" between the RFIC a nd the external data source. The TX Data bits supplied by the external source are transm itted directly in real-time (i.e., not stored internally for later transmission). It is not necessary to program the data rate parameter wh en operating in TX direct asynchronous mode. The chip still internally samples the in coming TX Data stream to determine when edge transitions occu r; however, rather than sampling the data at a pre-programmed data rate, the chip now internally samples the incoming TX Data stream at its maximum possible oversampling rate. This allows the chip to accurately determine the timing of the bit edge transitions without prio r knowledge of the data rate. (Of course, it is still necessary to program the desired peak frequency deviation.) Only FSK and OOK modulation types are valid in TX Direct Asynchronous Mode; GFSK modulation is not available in asynchronous mode. This is because the RFIC does not have knowledge of the supplied data rate, and thus cannot determine the appropriate Gaussian lowpass filter function to apply to the incoming data. One advantage of this mode that it saves a microcontroller pin because no TX Clock output function is required. The primary disadvantage of this mode is the increase in occupied spectral bandwidth with FSK (as compared to GFSK). trclk[1:0] TX Data Clock Configuration

00 No TX Clock (only for FSK)

01 TX Data Clock is available via GPIO (G PIO needs programming accordingly as well)

10 TX Data Clock is available via SDO pin (only when nSEL is high)

11 TX Data Clock is available via the nIRQ pin

Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

then the nIRQ pin can also be used as the TX data clock. Figure 9. Microcontroller Connections purpose of this mode is for use as a test mode to observe the modulated spectrum without having to provide data.

1. Internal Functional Blocks

This section provides an overview some of the key blocks of the internal radio architecture. can be programmed between ±1–320 kHz. These parameters may be adjusted via registers as shown in "3.5. Figure 10. PLL Synthesizer Block Diagram 312.5 Hz anywhere in the range between 240–960 MHz. so no external VCO components are required. be desirable so the VCO calibration may be skipped by setting the appropriate register. and +20dBm. The RFM43B contains a PA which is capable of transmitting output levels between –8 to +13 dBm. efficiency will not be constant. The PA output is ramped up and down to prevent unwanted spectral splatter.

5.2.1. Output Power Selection With the RFM42B,the output power is configurable in 3 dB steps with the tx pow[2:0] field in "Register 6Dh. TX Power." Extra output power can allow the use of a cheaper, smaller antenna reducing the overall BOM cost. The higher power setting of the chip achiev es maximum possible range, but of cour se comes at the cost of higher TX current consumption. However, depending on the duty cycle of the system, the effect on battery life may be insignificant. Contact HOPERF Support for help in evaluating this tradeoff. The +13 dBm output power of the RF43B is targeted at systems that require lower output power. The PA still offers high efficiency and a range of output power from –8 to +13 dBm. Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def. 6D R/W TX Power txpow[2] txpow[1] txpow[0] 07h txpow[2:0] RFM42B Output Power 000 +1 dBm 001 +2 dBm 010 +5 dBm 011 +8 dBm 100 +11 dBm 101 +14 dBm 110 +17 dBm 111 +20 dBm 000 –8 dBm 001 –5 dBm 010 –2 dBm 011 +1 dBm 100 +4 dBm 101 +7 dBm 110 +10 dBm 111 +13 dBm txpow[2:0] RFM43B Output Power Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

5.3. Crystal Oscillator The RFM42B/43B in cludes an integrated 30 MHz crystal oscillator with a fast start-up time of less than 600 µs e design is differential with the required capacitance integrated on-chip to minimize the number of external components. The crystal load capacitance can be digitally programme d to accommodate crystals with various load capacitance requirements and to adjust the frequency of the crystal oscillator. The tuning of t he crystal load capacitance is programmed through the xlc[6: 0] field of "Register 09h. 30 MHz Crysta l Oscillator Load Capacitance." The total internal capacitance is 12.5 pF and is adjustable in appr oximately 127 steps (97fF/step). The xtalshift bit is a coarse shift in frequency but is not binary with xlc[6:0]. The crystal frequency adjustment can be used to compensate for crystal production tolerances. Utilizing the on- chip temperature sensor and suitable control softwa re, the temperature depende ncy of the crystal can be canceled. The typical value of the total on-chip capacitance Cint can be calculated as follows: Cint = 1.8 pF + 0.085 pF x xlc[6:0] + 3.7 pF x xtalshift Note that the coarse shift bit xtalshift is not binary with xlc[6:0]. The total load capacitance Cload seen by the crystal can be calculated by adding the sum of all external parasitic PCB capacitances Cext to Cint. If the maximum value of Cint (16.3pF) is not sufficient, an external capacitor can be added for exact tuning. The crystal oscillator frequency is divided down internally and may be output to the microcontroller through one of the GPIO pins for use as the System Clock. In this fashion, only one crysta l oscillator is required for the entire system and the BOM cost is reduced. The available clo ck frequencies and GPIO configuration are discussed further in "7.2. Microcontroller Clock" . 5.4. Regulators There are a total of four regulators integrated onto the RFM42B/43B.With the exception of the digital regulator, all regulators are designed to operate with only internal de coupling. input supply voltage from +1.8 to +3.6V. A supply voltage should only be connected to the VDD pins. Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

09 R/W Crystal Oscillator Load

xtalshift xlc[6] xlc[5] xlc[4] xlc[3] xlc[2] xlc[1] xlc[0] 40h Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com A parallel resonant 30MHz crystal is used on the module. Th crystal load All regulators are designed to operate with an

1. Data Handling and Packet Handler

will write data to the TX FIFO. Figure 11. FIFO Threshold

interrupt on the nIRQ pin but the bits will still be read correctly in the Interrupt Status registers. reduces the required computational power of the microcontroller. lengths to accommodate different applications. The most common CRC polynominals are available for selection. Figure 12. Packet Structure An overview of the packet handler configuration registers is shown in Table 12. the packet length is set to three bytes.

08 R/W Operating &

Figure 13. Multiple Packets in TX Packet Handler Table 12. Packet Handler Registers Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

30 R/W Data Access Control Reserved lsbfrst cr cdonly skip2ph enpactx encrc crc[1] crc[0] 8Dh

31 R EzMAC status 0 Reserved Reserved Reserved Reserved Reserved pktx pksent —

32 Reserved

36 R/W Sync Word 3 sync[31] sync[30] sync[29] sync[28] sync[27] sync[26] sync[25] sync[24] 2Dh

37 R/W Sync Word 2 sync[23] sync[22] sync[21] sync[20] sync[19] sync[18] sync[17] sync[16] D4h

38 R/W Sync Word 1 sync[15] sync[14] sync[13] sync[12] sync[11] sync[10] sync[9] sync[8] 00h

39 R/W Sync Word 0 sync[7] sync[6] sync[5] s ync[4] sync[3] sync[2] sync[1] sync[0] 00h

6.6. TX Retransmission and Auto TX The RFM42B/43B is capable of automatically retransmit ting the last packet loaded in the TX FIFO. Automatic retransmission is set by entering the TX state with the txon bit without reloading the TX FIFO. This feature is useful for beacon transmission or when retransmission is requ ired due to the absence of a valid acknowledgement. Only packets that fit completely in the TX FIFO can be automatically retransmitted. An automatic transmission function is available, allowing the radio to automatically start or stop a transmission depending on the amount of data in the TX FIFO. When autotx is set in “Register 08. Operating & Function Control 2," the transceiver will automatically enter the TX state when the TX FIFO almost full threshold is exceed ed. Packets will be transmitted according to the configured packet length. To stop transmitting, clear the packet sent or TX FIFO almost empty interrupts must be cleared by reading register. Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

Figure 16. POR Glitch Parameters Table 13. POR Parameters

7.2. Microcontroller Clock The 30 MHz crystal oscillator frequency is divided down internally and may be output to the microcontroller through GPIO2. This feature is useful to lower BOM cost by using only one crystal in the system. The system clock frequency is selectable from one of 8 options, as shown below. Except for the 32.768 kHz option, all other frequencies are derived by dividing the crystal oscillator frequency. The 32.768 kHz clock signal is derived from an internal RC oscillator or an external 32 kHz crystal. The default setting for GPIO2 is to output the microcontroller clock signal with a frequency of 1 MHz. If the microcontroller clock option is being used there ma y be the need of a system clock for the microcontroller while the RFM42B/43B is in SLEEP mode. Since the crystal oscillator is disabled in SLEEP mode in order to save current, the low-power 32.768 kHz clock can be automatically switched to become the microcontroller clock. This feature is called enable low frequency clock and is enabled by the enlfc bit in “Register 0Ah. Microcontroller Output Clock." When enlfc = 1 and the chip is in SLEEP mode then the 32.768 k Hz clock will be provided to the microcontroller as the system clock, regardless of the setting of mclk[2:0]. For example, if mclk[2:0] = 000, 30 MHz will be provided through the GPIO output pin to the microcontroller as the system clock in all IDLE or TX states. When the chip enters SLEEP mode, the system clock will automatically switch to 32.768 kHz from the RC oscillator or 32.768 XTAL. Another available feature for the microcontroller clock is the clock tail, clkt[1:0] in “Register 0Ah. Microcontroller Output Clock." If the low frequency clock feature is not enabled (enlfc = 0), then the system clock to the microcontroller is disabled in SLEEP mode. However, it may be usef ul to provide a few extra cycles for the microcontroller to complete its operation prior to the shutdo wn of the system clock signal. Setting the clkt[1:0] field will provide additional cycles of the system clock before it shuts off. If an interrupt is triggered, the microcontroller clock will remain enabled regardless of the selected mode. As soon as the interrupt is read the state machine will then move to the selected mode. The minimum current consumption will not be achieved until the interrup t is read. For instance, if the ch ip is commanded to SLEEP mode but an interrupt has occurred the 30 MHz XTAL will not be disabled until the interrupt has been cleared. Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def. 0A R/W Microcontroller Output Clock clkt[1] clkt[0] enlfc mclk[2] mclk[1] mclk[0] 0Bh mclk[2:0] Clock Frequency 000 30 MHz 001 15 MHz 010 10 MHz 011 4 MHz 100 3 MHz 101 2 MHz 110 1 MHz 111 32.768 kHz clkt[1:0] Clock Tail 00 0 cycles 01 128 cycles 10 256 cycles 11 512 cycles Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

configure the ADC operation. dependent offset voltage can be added using soffs[3:0] in register 10h. Figure 17. General Purpose ADC Architecture Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

10 R/W Sensor Offset soffs[3] soffs[2] soffs[1] soffs[0] 00h

11 R ADC Value adc[7] adc[6] adc[5] adc[4] adc[3] adc[2] adc[1] adc[0] —

sensor is configurable. Table 14 lists the settings for the different temperature ranges and performance.

1. Set the input for ADC to the temperature sensor, "Register 0Fh. ADC Configuration"—adcsel[2:0] = 000
2. Set the reference for ADC, "Register 0Fh. ADC Configuration"—adcref[1:0] = 00
3. Set the temperature range for ADC, "Register 12h. Temperature Sensor Calibration"—tsrange[1:0]
4. Set entsoffs = 1, "Register 12h. Temperature Sensor Calibration"
5. Trigger ADC reading, "Register 0Fh. ADC Configuration"—adcstart = 1
6. Read temperature value—Read contents of "Register 11h. ADC Value"

calibration is necessary. The temperature sensor may be calibrated by setting entsoffs = 1 in “Register 12h. ±3 °C absolute accuracy may be achieved. may be translated to a temperature reading by ADC8 Value x ADC8 LSB + Lowest Temperature in Temp Range. For instance for a tsrange = 00, Temp = ADC8Value x 0.5 – 64.

12 R/W Temperature

13 R/W Temperature Value Offset

Table 14. Temperature Sensor Range

Figure 18. Temperature Ranges using ADC8

7.5. Low Battery Detector A low battery detector (LBD) with digital read-out is integrated into the chip. A digital threshold may be programmed into the lbdt[4:0] field in "Registe r 1Ah. Low Battery Detector Threshol d." When the digitized battery voltage reaches this threshold an interrupt will be generated on the nIRQ pin to the microcontroller. The microcontroller can confirm source of the interrupt by reading "Register 03h. Interrupt/Status 1" and “Register 04h. Interrupt/Status 2,” If the LBD is enabled while the chip is in SLEEP mode, it will automatically enable th e RC oscillator which will periodically turn on the LBD circuit to measure the battery voltage. The battery voltage may also be read out through "Register 1Bh. Battery Voltage Level" at any time when the LBD is enabled. The low battery detect function is enabled by setting enlbd=1 in "Register 07h. Operating Mode and Function Control 1". The LBD output is digitized by a 5-bit ADC. When th e LBD function is enabled, enlbd = 1 in "Register 07h. Operating Mode and Function Control 1", the battery volt age may be read at anytime by reading "Register 1Bh. Battery Voltage Level." A battery voltage threshold may be programmed in “Register 1Ah. Low Battery Detector Threshold." When the battery voltage level drops below the battery voltage threshold an interrupt will be generated on the nIRQ pin to the microcontroller if the LBD interrupt is enabled in “Register 06h. Interrupt Enable 2,” The microcontroller will then need to verify the interrupt by reading the interrupt status register, addresses 03 and 04h. The LSB step size for the LBD ADC is 50 mV, with the ADC range demonstrated in the table below. If the LBD is enabled the LBD and ADC will automatically be enabled every 1 s for approximately 250 µs to measure the voltage which minimizes the current consumption in Sensor mode. Before an interrupt is activated four consecutive readings are required. Ad R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def. 1A R/W Low Battery Detector Threshold lbdt[4] lbdt[3] lbdt[2] lbdt[1] lbdt[0] 14h 1B R Battery Voltage Level 0 0 0 vbat[4] vbat[3] vbat[2] vbat[1] vbat[0] — ADC Value VDD Voltage [V] 0< 1.7 1 1.7–1.75 2 1.75–1.8 29 3.1–3.15 30 3.15–3.2 31 > 3.2 ADCValuemVtageBatteryVol 50 7 . 1 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

7.6. Wake-Up Timer The chip contains an integrated wake-up timer which can be used to periodically wake the chip from SLEEP mode. The wake-up timer runs from the internal 32.768 kHz RC Oscillator. The wake-up timer can be configured to run when in SLEEP mode. If enwt = 1 in "Register 07h. Operating Mode and Function Control 1" when entering SLEEP mode, the wake-up timer will c ount for a time specified def ined in Registers 14–16h, "Wake Up Timer Period." At the expiration of this period an interr upt will be generated on the nIRQ pin if this interrupt is enabled. The microcontroller will then need to verify the interrupt by reading the Registers 03h–04h, "Interrupt Status 1 & 2". The wake-up timer value may be read at any time by the wtv[15:0] read only registers 13h–14h. The formula for calculating the Wake-Up Period is the following: Use of the D variable in the formula is only necessary if fi ner resolution is required than can be achieved by using the R value. There are two different methods for utilizing the wake-up timer (WUT) depending on if the WUT interrupt is enabled in “Register 06h. Interrupt Enable 2,”. If the WUT interrupt is enabled then nIRQ pin will go low when the timer expires. The chip will also change state so that the 30 MHz XTAL is enabled so that the microcontroller clock output is available for the microc ontroller to use to process the interrupt. The other method of use is to not enable the WUT interrupt and use the WUT GPIO setting. In this mode of operation the chip will not change state until commanded by the microcontroller. The different modes of operating the WUT and the current consumption impacts are demonstrated in Figure 19. A 32 kHz XTAL may also be used for better timing accuracy. By setting the x32 ksel bit in “Register 07h. Operating & Function Control 1," GPIO0 is automatically reconfigured so that an external 32 kHz XTAL may be connected to this pin. In this mode, the GPIO0 is extremely sensitiv e to parasitic capacitance, so only the XTAL should be connected to this pin with the XTAL physically located as close to the pin as possible. Once the x32 ksel bit is set, all internal functions such as WUT, microcontroller clock, and LDC mode will use the 32 kHz XTAL and not the 32 kHz RC oscillator. WUT Register Description wtr[3:0] R Value in Formula wtd[1:0] D Value in Formula wtm[15:0] M Value in Formula Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

14 R/W Wake-Up Timer Period 1 wtr[3] wtr[2] wtr[1] wtr[0] wtd[1] wtd[0] 00h

15 R/W Wake-Up Timer Period 2 wtm[15] wtm[14] w tm[13] wtm[12] wtm[11] wtm[10] wtm[9] wtm[8] 00h

16 R/W Wake-Up Timer Period 3 wtm[7] wtm[6 ] wtm[5] wtm[4] wtm[3] wtm[2] wtm[1] wtm[0] 00h

17 R Wake-Up Timer Value 1 wtv[15] wtv[14] w tv[13] wtv[12] wtv[11] w tv[10] wtv[9] wtv[8] —

18 R Wake-Up Timer Value 2 wtv[7] wtv[6] w tv[5] wtv[4] wtv[3] wtv[2] wtv[1] wtv[0] —

R 768 . 32 2 4  Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

Figure 19. WUT Interrupt and WUT Operation

7.7. GPIO Configuration Three general purpose IOs (GPIOs) are available. Numerous functions such as specific interrupts, TRSW control, Microcontroller Output, etc. can be routed to the GPIO pins as shown in the tables below. When in Shutdown mode all the GPIO pads are pulled low. Note: The ADC should not be selected as an input to the GPIO in Standby or Sleep Modes and will cause excess current con- sumption. The GPIO settings for GPIO1 and GPIO2 are the same as for GPIO0 with the except ion of the 00000 default setting. The default settings for each GPIO are listed below: For a complete list of the available GPIO's see “RFM42B/43B Register Descriptions.” The GPIO drive strength may be adjusted with the gpioXdrv[1:0] bits. Setting a higher va lue will increase the drive strength and current capability of the GPIO by changing the driver size. Special care should be taken in setting the drive strength and loading on GPIO2 wh en the microcontroller clock is used. Excess loading or inadequate drive may contribute to increased spurious emissions. Add R/W Function/ D7 D6 D5 D4 D3 D2 D1 D0 POR Def. 0B R/W GPIO0 Configuration gpio0drv[1] gpio0drv[0] pup0 gpio0[4] gpio0[3] gpio0[2] gpio0[1] gpio0[0] 00h 0C R/W GPIO1 Configuration gpio1drv[1] gpio1drv[0] pup1 gpio1[4] gpio1[3] gpio1[2] gpio1[1] gpio1[0] 00h 0D R/W GPIO2 Configuration gpio2drv[1] gpio2drv[0] pup2 gpio2[4] gpio2[3] gpio2[2] gpio2[1] gpio2[0] 00h 0E R/W I/O Port Configuration extitst[2] extitst[1] extitst[0] itsdo dio2 dio1 dio0 00h GPIO 00000—Default Setting GPIO0 POR GPIO1 POR Inverted GPIO2 Microcontroller Clock Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

1. Register Table and Descriptions

Table 15. Register Descriptions

01 R Device Version 0 0 0 vc[4] vc[3] vc[2] vc[1] vc[0] 06h

02 R Device Status ffovfl ffunfl Reserved reserved reserved cps[1] cps[0] —

03 R Interrupt Status 1 ifferr itxffafull itxffaem Reserved iext ipksent Reserved Reserved —

05 R/W Interrupt Enable 1 enfferr entxffafull entxffaem Reserved enext enpksent Reserved Reserved 00h

06 R/W Interrupt Enable 2 Reserved Reserved Reserved Reserved enwut enlbd enchiprdy enpor 03h

07 R/W Operating & Function Control 1 swres enlbd enwt x32ksel txon Reserved pllon xton 01h

11 R ADC Value adc[7] adc[6] adc[5] a dc[4] adc[3] adc[2] adc[1] adc[0] —

14 R/W Wake-Up Timer Period 1 Reserved Reserved Reserved wtr[4] wtr[3] wtr[2] wtr[1] wtr[0] 03h

15 R/W Wake-Up Timer Period 2 wtm[15] wtm[14] wtm[13] wtm[12] wtm[11] wtm[10] wtm[9] wtm[8] 00h

16 R/W Wake-Up Timer Period 3 wtm[7] wtm[6] wtm[5] wtm[4] wtm[3] wtm[2] wtm[1] wtm[0] 01h

17 R Wake-Up Timer Value 1 wtv[15] wtv[14] wtv[13] wtv[12] wtv[11] wtv[10] wtv[9] wtv[8] —

18 R Wake-Up Timer Value 2 wtv[7] wtv[6] wtv[5] wtv[4] wtv[3] wtv[2] wtv[1] wtv[0] —

19 Reserved

30 R/W Data Access Control Reserved lsbfrst crcdonly Reserved enpactx encrc crc[1] crc[0] 8Dh

38 R/W Sync Word 1 sync[15] sync[14] sync[13] sync[12] sync[11] sync[ 10] sync[9] sync[8] 00h

39 R/W Sync Word 0 sync[7] sync[6] sync[5] sync[4] sync[3] sync[2] sync[1] sync[0] 00h

60 Reserved

62 R/W Crystal Oscillator/Control Test pwst[2] pwst[1] pwst[0] clkhyst enbias2x enamp2x bufovr enbuf 24h

71 R/W Modulation Mode Control 2 trclk[1] trclk[0] dtmod[1] dtmod[0] eninv fd[8] modtyp[1] modtyp[0] 00h

72 R/W Frequency Deviation fd[7] fd[6] fd[5] fd[4] fd[3] fd[2] fd[1] fd[0] 20h

74 R/W Frequency Offset 2 Reserved Reserved Res erved Reserved Reserved Reserved fo[9] fo[8] 00h

75 R/W Frequency Band Select Reserved sbsel hbsel fb[4] fb[3] fb[2] fb[1] fb[0] 75h

76 R/W Nominal Carrier Frequency 1 fc[15] fc[14] fc[13] fc[12] fc[11] fc[10] fc[9] fc[8] BBh

77 R/W Nominal Carrier Frequency 0 fc[7] fc[6] fc[5] fc[4] fc[3] fc[2] fc[1] fc[0] 80h

Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com 10. Pin Descriptions: RFM42B/43B R F M 4 2 B / 4 3 B - S 1 R F M 4 2 B / 4 3 B - S 2 RFM42B/43B-D RFM42B/43B

Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com VCC S +1.8 to +3.6 V supply voltage. The recommended V CC supply voltage is +3.3 V. GND S Ground reference. GPIO_0 I/O GPIO_1 I/O GPIO_2 I/O General Purpose Digital I/O that may be configured through the registers to perform various functions including: Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery Detect, TRSW, AntDiversity control, etc. See the SPI GPIO Configuration Registers, Address 0Bh, 0Ch, and 0Dh for more information. SDO O 0–V CC V digital output that provides a serial readback function of the internal control registers. SDI I Serial Data input. 0–V CC V digital input. This pin provides the serial data stream for the 4-line serial data bus. SCLK I Serial Clock input. 0–V DD V digital input. This pin provides the serial data clock function for the 4-line serial data bus. Data is clocked into the RFM42/43 on positive edge transitions. nSEL I Serial Interface Select input. 0– V CC V digital input. This pin provides the Select/Enable function for the 4-line serial data bus. The signal is also used to signify burst read/write mode. nIRQ O General Microcontroller Interrupt Status outpu t. When the RFM42/43 exhibits anyone of the Interrupt Events the nIRQ pin will be set low=0. Please see the Control Logic registers section for more information on the Interrupt Events. The Microcontroller can then determine the state of the interrupt by reading a corresponding SPI Interrupt Status Registers, Address 03h and 04h. SDN I Shutdown input pin. 0–V CC V digital input. SDN should be = 0 in all modes except Shutdown mode. When SDN =1 the chip will be completely shutdown and the contents of the registers will be lost. ANT I/O RF signal output/input.(50 OHM output /input Impedance NC No Connection RFM42B/43B

Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com 12. Mechanical Dimension:RFM42B/43B SMD PACKAGE（S1） SMD PACKAGE（S2） RFM42B/43B

Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com DIP PACKAGE（D） RFM42B/43B

Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com 13. Ordering Information Part Number module type—operation band—package type RFM42B/43B —433 module type operation band Package example：1，RFM43B module at 433MHz band, DIP : RFM43B-433-D。 2 ，RFM42B module at 868MHZ band, SMD, thickness at 4.9mm: RFM42B-868-S1。 RFM42B/43B

Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com RFM42B/43B 14. IC Information

Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com RFM42B/43B 15. Pin Descriptions

Table 17. PCB Land Pattern Dimensions

1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal

walls should be used to assure good solder paste release.

1. The stencil thickness should be 0.125 mm (5 mils).
2. The ratio of stencil aperture to land pad size should be 1:1 for the
3. A 2x2 array of 1.10 x 1.10 mm openings on 1.30 mm pitch should be

used for the center ground pad.

1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020

specification for small body components.

HOPE MICROELECTRONICS CO.,LTD Add:4/F, Block B3, East Industrial Area, Huaqiaocheng, Shenzhen, Guangdong, China Tel: 86-755-82973805 Fax: 86-755-82973550 Email: sales@hoperf.com t rade@hoperf.com Website: http://www.hoperf.com http://hoperf.en.alibaba.com This document may contain preliminary information and is subject to change by Hope Microelectronics without notice. Hope Microelectronics assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of Hope Microelectronics or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in the direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MECHANTABILITY OR FITNESS FOR A ARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT. ©2006, HOPE MICROELECTRONICS CO.,LTD. All rights reserved. Tel: +86-755-82973805 Fax: +86-755-82973550 E-ma il: sales@hoperf.com ht tp://www.hoperf.com RFM42B/43B