RFM31B-433-D

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ISM receiver module. and support for frequency hopping can be used to further extend range and Addi tional system features such as an automatic wake-up timer, low battery detector, 64 byte RX FIFO, automatic pa cket handling, and preamble detection reduce overall current c onsumption and allow the us e of a lower-cost system MCU. An integrated temp erature sensor, general purpose ADC, power-on-reset (POR), and GPIOs further reduce overall system cost and size. The RFM31B's digital receive architecture features a high-performance ADC and DSP based modem which performs demodula tion, filtering, and packet handling for increased flexibility and performance. An easy-to-use calculator is provided to quickly configure the radio settings, simplifying customer's system design and reducing time to market.  Freq uency Range  Sensitivity = –121 dBm  Low Power Consumption 18.5 mA receive  Data Rate = 0.123 to 256 kbps  FSK, GFSK, and OOK modul ation  Power Supply = 1.8 to 3.6 V  Ultra low power shut down mode  Dig ital RSSI  W ake-up timer  Auto-frequency cal ibration (AFC)  Clear channel assessment Programmabl e RX BW 2.6–620 kHz  Programmable pa cket handler  Programmab le GPIOs  Embedd ed antenna diversity algorithm  Confi gurable packet handler  Preamble detector  RX 64 byte FIFO  Low ba ttery detector  Tempera ture sensor and 8-bit ADC  –40 to +8 5 °C temperature range  Inte grated voltage regulators  Fre quency hopping capability  On -chip crystal tuning  Low BOM  Power-on-reset (POR)  Remote control  Home security & alarm  Tele metry  Personal data logg ing  Toy c ontrol  Tire pressure monitoring  Wireless PC p eripherals  Remote meter r eading  Remote keyless entry  Home automa tion  Industrial cont rol  Sensor ne tworks  Health monitors  Tag readers RFM31B Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com 433/868/915MHz ISM bands 14-PIN DIP & 16-PIN SMD p ackage HopeRF's RFM31B are highly integrated, low cost,433/868/915MHZ wireless V1.0 The low receive sensitivity (–121dBm) ensures extended range and improved link performance. Built-in antenna diversity enhance performance.

T ABLE OF C ONTENTS Section Page Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com 24. . .25 . .36 .10 . 4

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1. Electrical Specifications

Table 1. DC Characteristic

T able 2. Synthesizer AC Electrical Characteristics Paramete r Symbol Conditions Min Typ Max Units Synthesizer Frequency Range FSYN Syn thesizer Frequency Resolution FRES-LB 433M Hz Band — 156.25 — Hz FRES-H B 868/915MHz Band — 312.5 — Hz Reference Frequency Input Level f REF_L V When u sing external reference signal driving XOUT pin, instead of using crystal. Measured peak-to-peak (VPP) 0.7 — 1.6 V Synthesizer Settling Time tLOCK Measu red from exiting Ready mode with XOSC running to any frequency. Including VCO calibration. —2 0 0— µ s Residual FM FRMS Integr ated over 250 kHz bandwidth (500 Hz lower bound of integration) —2 4 k H z RMS Phase No ise L(fM) F = 1 0 kHz — –80 — dBc/Hz F = 100 kHz — –90 — dBc/Hz F = 1 MHz — –115 — dBc/Hz F = 10 MHz — –130 — dBc/Hz Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com 848

888 MHz

Table 3. Rece RSSI Resolution RES RSSI —± 0 .

1 Meas

T able 4. Auxiliary Block Specifications Paramete r Symbol Conditions Min Typ Max Units Temperature Sensor Accuracy TSA After c alibrated via sensor offset register tvoffs[7:0] —0 . 5 — ° C Temperature Sensor Sensitivity TS S —5 — m V / ° C Low Battery Detector Resolution LBD RES —5 0 — m V Low Battery Detector Conversion Time LBD CT —2 5 0 — µ s Microcontroller Clock Output Frequency F MC Configurab le to 30 MHz,

15 MHz, 10 MHz, 4 MHz,

3M H z , 2M H z , 1M H z , o r 32.768 kHz 32.768K — 30M Hz General Purpose ADC Resolution ADC ENB —8 — b i t General Purpose ADC Bit Resolution ADC RES —4 — m V / b i t Temp Sensor & General Purpose ADC Conversion Time ADC CT —3 0 5 — µ s

30 MHz XTAL Start-Up time t 30M —6

0 0 — µ s

30 MHz XTAL Cap

RES —9 7 — f F 32 kHz XTAL Start-Up Time t32k —6 — s e c 32 kHz XTAL Accuracy using 32 kHz XTAL 32K RES — 100 — ppm 32 kHz Accuracy using Internal RC Oscillator 32KRC RES —2 5 0 0 — p p m POR Reset Time tPOR —1 6 — m s Software Reset Time tsoft —1 0 0 — µ s Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

Table 6. GPI Logic Low Level Input Voltage V IL —— 0 .

Table 7. Absolute Maxim device reliability. Caution: ESD sensitive device.

1. Functional Description The wide operating voltage range of 1.8–3.6V and low current consumption solution for battery powered applications. The RFM31B uses a single-conversion mixe r to downconvert the 2-level FSK/GFSK/OOK modulated r eceive signal to a low IF frequency. Following a programmable gain amplifier (PGA) the signal is converted to the digital domain by a high performance  ADC allowing filtering, demodulation, slicing, and packet handling to be performed in the built-in DSP incr easing the receiver’s performance and flexibility versus analog based architectures. The demodulated signal is then output to the system MCU through a programmable GPIO or via the standard SPI bus by reading the 64-byte RX FIFO. A high precision local oscillator (LO) is generated by an integrated VCO and  Fractional-N PLL synthesizer. The synthesizer is designed to support co nfigurable data rates, output freque ncy and frequency deviation . The RFM31B is designed to work with a microcontroller to create a very low integrated on-chip which allows for a wide operating supply voltage range from SPI bus is used to communicate with an external microcontroller. Three are available. A complete list of the available GPIO functions is shown in "8. Auxiliary Functions" and includes microcontroller clock output, Antenna Diversi ty, Antenna Switch, POR, and various interrupts. A complete list of the available GPIO functions is shown in "RFM31B Register Descriptions.” Figure 1.RFM31B Application Example

30 MHz

D_RF SCLK 161 SDI SDO VDD_DRXn NC RFp GPIO0 GP IO1 VR_DIG nIRQ SDN XOUT nSEL GPIO2 5NC 6ANT1 NC XIN GP5 1 u RF31B Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com HopeRF's RFM31B are highly integrated, low cost, 433/868/915MHz wireless ISM receivers module . makes the RFM31B an ideal cost system. Voltage regulators are +1.8 to +3.6V. A standard 4-pin configurable general purpose I/Os RFM31B module

and power consumption can be achieved. (Auxiliary Blocks) includes the temperature sensor, general purpose ADC, and low-battery detector. Table 8. Operating Modes

flexible with a maximum rate of 10 MHz. Figure 2. SPI Timing data bit clocked out (D0). When nSEL goes high the SDO output pin will be pulled high by internal pullup. Table 9. Serial Interface Timing Parameters

configurations/options for the IDLE state which can be sele cted to optimize the chip to the applications needs. modes. The main digital regulator is automatically enabled in all other modes. Table 10. Operating Modes Response Time

3.2.1. SHUTDOWN State The SHUTDOWN state is the lowest current consumption state of the device with nominally less than 15 nA of current consumption. The SHUTDOWN state may be entere d by driving the SDN pin high. The SDN pin should be held low in all states e xcept the SHUTDOWN state. In the SHUTDOWN state, the contents of the registers are lost and there is no SPI access. When the chip is connected to the power supply, a POR will be initiated after the falling edge of SDN. 3.2.2. IDLE State There are five different modes in the IDLE state which may be selected by "Register 07h. Operating Mode and Function Control 1". All modes have a tradeoff between cu rrent consumption and response time to RX mode. This tradeoff is shown in Table 10. After the POR event, SWRESET, or exiting from the SHUTDOWN state the chip will default to the IDLE-READY mode. After a POR event the inte rrupt registers must be read to properly enter the SLEEP , SENSOR, or STANDBY mode and to control the 32 kHz clock correctly. 3.2.2.1. STANDBY Mode STANDBY mode has the lowest current consumption of th e five IDLE states with only the LPLDO enabled to maintain the register values. In this mode the regist ers can be accessed in both read and write mode. The STANDBY mode can be entered by writ ing 0h to "Register 07h. Operating Mode and Function Control 1". If an interrupt has occurred (i.e., the nIRQ pin = 0) the interr upt registers must be read to achieve the minimum current consumption. Additionally, the ADC should not be selected as an input to th e GPIO in this mode as it will cause excess current consumption. 3.2.2.2. SLEEP Mode In SLEEP mode the LPLDO is enabled along with the Wake -Up-Timer, which can be used to accurately wake-up the radio at specified intervals. See "8.6. Wake-U p Timer and 32kHz Clock Source" for more information on the Wake-Up-Timer. SLEEP mode is entered by setting enwt = 1 (40h) in "Register 07h. Operating Mode and Function Control 1". If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current consumption. Also, the ADC should not be selected as an input to the GPIO in this mode as it will cause excess current consumption. 3.2.2.3. SENSOR Mode In SENSOR Mode either the Low Battery Detector, Temperature Sensor, or both may be enabled in addition to the LPLDO and Wake-Up-Timer. The Low Battery Detector can be enabled by setting enlbd = 1 in "Register 07h. Detector" for more information on these featur es. If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current consumption. 3.2.2.4. READY Mode READY Mode is designed to give a fast transition time to RX mode with reasonable current consumption. In this mode the Crystal oscillator remains enabled reducing the time required to switch to RX mode by eliminating the crystal start-up time. READY mode is entered by setting xton = 1 in "Register 07h. Operating Mode and Function Control 1". To achieve the lowest curr ent consumption state the crystal oscillator buffer should be disabled in “Register 62h. Crystal Oscillator Control and Test.” To exit ready mode, bufo vr (bit 1) of this register must be set back to 0. 3.2.2.5. TUNE Mode In TUNE Mode the PLL remains enabled in addition to the other blocks enabled in the IDLE modes. This will give the fastest response to RX mode as the PLL will remain locked but it results in the highest current consumption. This mode of operation is designed for frequency hopp ing spread spectrum syste ms (FHSS). TUNE mode is entered by setting pllon = 1 in "Register 07h. Operating Mode and Function Control 1". It is not necessary to set xton to 1 for this mode, the internal state machine automatically enables the crystal oscillator. Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

3.2.3. RX State The RX state may be entered from any of the IDLE modes when the rxon bit is set to 1 in "Register 07h. Operating Mode and Function Control 1". A built-in sequencer takes ca re of all the actions required to transition from one of the IDLE modes to the RX state. The following sequence of events will occur automatically to get the chip into RX mode when going from STANDBY mode to RX mode by setting the rxon bit: 1. Enable the main digital LDO and the Analog LDOs. 2. Start up crystal oscillator and wait until ready (controlled by an internal timer). 3. Enable PLL. 4. Calibrate VCO (this action is skipped when the vcocal bit is “0”, default value is “1”). 5. Wait until PLL settles to required receive frequency (controlled by an internal timer). 6. Enable receive circuits: LNA, mixers, and ADC. 7. Enable receive mode in the digital modem. Depending on the configuration of the radio all or some of the following functions will be performed automatically by the digital modem: AGC, AFC (optional), update status registers, bit synchronization, packet handling (optional) including sync word, header check, and CRC. 3.2.4. Device Status The operational status of the chip can be read from "Register 02h. Device Status". Add R/W Function/Description D 7 D6 D5 D4 D3 D2 D1 D0 POR Def.

02 R Device Status ffovfl ffunfl rxffem headerr freqerr cps[1] cps[0] —

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3.3. Interrup ts The RFM31B is capable of generating an interrupt signal when certain events occur.The chip notifies the m icrocontroller that an interrupt event has occurred by setting the nIRQ output pin LOW = 0. This interrupt signal will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits) shown below occur. The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Register(s) (Registers 03h–04h) containing the active Interrupt Status bit. The nIRQ output signal will then be reset until the next change in status is detected. The interrupts must be enabled by the corresponding enable bit in the Interrupt Enable Registers (Registers 05h–06h). All enabled interrupt bits will be cleare d when the microcontroller reads the interrupt status register. If the interrupt is not enabled when the event occurs it will not trigger the nIRQ pin, but the status may still be read at anytime in the Interrupt Status registers. For a complete descriptions of each interrupt, see “RFM31B Register Descriptions.” Add R/W Function/Descript ion D7 D 6 D5 D4 D3 D2 D1 D0 POR Def.

03 R Interrupt Status 1 ifferr Reserved Reser ved irxffafull iext Reserved ipkvalid icrcerror —

04 R Interrupt Status 2 iswdet ipreaval ipreainval irssi iwut ilbd ichiprdy ipor —

05 R/W Interrupt Enable 1 enfferr Reserved Reserv ed enrxffafull enext Reserved enpkvalid encrcerror 00h

06 R/W Interrupt Enable 2 enswdet enpreaval en preainval enrssi enwut enlbd enchiprdy enpor 01h

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3.4. System T iming The system timing for RX mode is shown in Figure 7. The user only needs to program the desired mode, and the internal sequencer will properly transition the part from its current mode. The VCO will automatically calibrate at every frequency change or power up. The PLL T0 time is to allow for bias settling of the VCO. The PLL TS time is for the settling time of the PLL, which has a default setting of 100 µs. The total time for PLL T0, PLL CAL, and PLL TS under all co nditions is 200 µs. Under certain applications, the PLL T0 time and the PLL CAL may be skipped for faster turn-around time. Contact applications support if faster turnaround time is desired. Figure 7. RX Timing RX Pa cketXTAL Settling Time PLL T0 PLL CAL PLLTS 600us Config urable 0-70us, Default =50us 50us, May be skipped Configurab le 0-310us, Recommend 100us Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

3.5. Freq uency Control For calculating the nece s sary frequency register settings it is re commended that custom Calculator worksheet (in Microsoft Excel) available on r a simple method to quickly determi ne the correct settings based on the application requirements. The following information can be used to calculated these values manually. 3.5.1. Frequency Programming In order to receive an RF signal,the desired channel frequency,fcarri er, must be programmed into the RFM31B.Note tha t this frequency is the center frequency of the desir ed channel and not an LO frequency. The carrier frequency is generated by a Fractional-N Synthesizer, using 10 MHz both as the reference frequency and the clock of the (3rd order ) ΔΣ modulator. This modulator uses modulo 64000 accumulators. This design was made to obtain the desired frequency resolution of the synthesizer. The overall division ratio of the feedback loop consist of an integer part (N) and a fractional part (F). In a generic sense, the output frequency of the synthesizer is as follows: The fractional part (F) is determined by three differ ent values, Carrier Frequency (fc[15:0]), Frequency Offset (fo[8:0]), and Frequency Deviation (fd[7:0]). Due to the fi ne resolution and high loop bandwidth of the synthesizer, FSK modulation is applied inside the loop and is done by varying F according to the incoming data; this is discussed further in "3.5.4. Frequency Offset Adjustment ". Also, a fixed offset can be added to fine- tune the carrier frequency and counteract crystal toleranc e errors. For simplicity assume that only the fc[15:0] register will determine the fractional component. The equation for selectio n of the carrier frequency is shown below: The integer part (N) is determined by fb[4:0]. Additional ly, the frequency can be halved by connecting a ÷2 divider to the output. This divider is not inside the loop and is controlled by the hbsel bit in "Register 75h. Frequency Band Select." This effectively partitions the entire 240–960 MHz frequency range into two separate bands: High Band (HB) for hbsel = 1, and Low Band (LB) for hbsel = 0. The valid range of fb[4:0] is from 0 to 23. If a higher value is written into the register, it will default to a value of 23. The integer part has a fixed offset of 24 added to it as shown in the formula above. Table 11 demonstrates the selection of fb[4:0] for the corresponding frequency band. After selection of the fb (N) the fractional component may be solved with the following equation: fb and fc are the actual numbers stored in the corresponding registers. Add R/W Function/Description D7 D 6 D5 D4 D3 D2 D1 D0 POR Def.

73 R/W Frequency Offset 1 fo[7] fo[6] fo[5] fo[4] fo[3] fo[2] fo[1] fo[0] 00h

74 R/W Frequency Offset 2 Reserved Reserved Res erved Reserved Reserved Reserved fo[9] fo[8] 00h

75 R/W Frequency Band Select Reserved sbsel hbsel fb[4] fb[3] fb[2] fb[1] fb[0] 35h

76 R/W Nominal Carrier

fc[15] fc[14] fc[13] fc[12] fc[11] fc[10] fc[9] fc[8] BBh

77 R/W Nominal Carrier

fc[7] fc[6] fc[5] fc[4] fc[3] fc[2] fc[1] fc[0] 80h ( 10 F N MHzfOUT  ( ) 1 ( 10F NhbselMHzfcarrier  )64000 ] 0: 15 [24 ] 0 : 4 [ ( * ) 1 ( * 10fcfbhbselMHzfcarrier   64000 *24 ffc carrier Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com ers use HOPERF Register the product website. These methods offe

The chip will automatically shif t the frequency of the Synthesizer down by 937.5 kHz (30 MHz ÷ 32) to achieve the correct Intermediate Frequency (IF) when RX mode is entered. Low-side injection is used in the RX Mixing architecture. T able 11. Frequency Band Selection fb [4:0] Value N Frequency Band hbsel=0 hbsel=1 0 24 240–249.9 MHz 480–499.9 MHz 1 25 250–259.9 MHz 500–519.9 MHz 2 26 260–269.9 MHz 520–539.9 MHz 3 27 270–279.9 MHz 540–559.9 MHz 4 28 280–289.9 MHz 560–579.9 MHz 5 29 290–299.9 MHz 580–599.9 MHz 6 30 300–309.9 MHz 600–619.9 MHz 7 31 310–319.9 MHz 620–639.9 MHz 8 32 320–329.9 MHz 640–659.9 MHz 9 33 330–339.9 MHz 660–679.9 MHz 10 34 340–349.9 MHz 680–699.9 MHz 11 35 350–359.9 MHz 700–719.9 MHz 12 36 360–369.9 MHz 720–739.9 MHz 13 37 370–379.9 MHz 740–759.9 MHz 14 38 380–389.9 MHz 760–779.9 MHz 15 39 390–399.9 MHz 780–799.9 MHz 16 40 400–409.9 MHz 800–819.9 MHz 17 41 410–419.9 MHz 820–839.9 MHz 18 42 420–429.9 MHz 840–859.9 MHz 19 43 430–439.9 MHz 860–879.9 MHz 20 44 440–449.9 MHz 880–899.9 MHz 21 45 450–459.9 MHz 900–919.9 MHz 22 46 460–469.9 MHz 920–939.9 MHz 23 47 470–479.9 MHz 940–960 MHz Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

3.5 .2. Easy Frequency Programming for FHSS While Registers 73h–77h may be used to program the carrier frequency of the RFM31B,it is often easier to think in terms of “channels” or “channel numbers” rather than an absolute frequency value in Hz. Also, there may be some timing-critical applications (such as for Frequency Hoppin g Systems) in which it is desirable to change frequency by programming a single register. Once the channel step size is set, the frequency may be changed by a single register corresponding to the channel number. A nominal frequency is first set using Registers 73h–77h, as described above. Registers 79h and 7Ah are then used to set a channel step size and channel number, relative to the nominal setting. The Frequency Hopping Step Size (fhs [7:0]) is set in incremen ts of 10 kHz with a maximum channel step size of 2.56 MHz. The Frequency Hopping Channel Select Register then selects channels based on multiples of the step size. For example, if the nominal frequency is set to 900 MHz using Registers 73h–77h, the channel step size is set to 1 MHz using "Register 7Ah. Frequency Hopping Step Si ze," and "Register 79h. Frequency Hopping Channel Select" is set to 5d, the resulting carrier frequency would be 905 MHz. Once the nominal frequency and channel step size are programmed in the registers, it is only necessary to program the fhch[7:0] register in order to change the frequency. 3.5.3. Automatic State Transition for Frequency Change If registers 79h or 7Ah are changed in RX mode, the st ate machine will automatically transition the chip back to TUNE and change the frequency. This fe ature is useful to reduce the number of SPI commands required in a Frequency Hopping System. This in turn reduces microcontroller activity, reducing current consumption. Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

79 R/W Frequency Hopping Channel

fhch[7] fhch[6] fhch[5 ] fhch[4] fhch[3] fhch[2] fhch[1] fhch[0] 00h 7A R/W Frequency Hopping Step Size fhs[7] fhs[6] fhs[5] fhs[4] fh s[3] fhs[2] fhs[1] fhs[0] 00h 10 ] 0 : 7 [ ( ] 0 : 7 [kHzfhchfhs FnomFcarrier  Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

3.5.4. Frequency Offset Adjustment When the AFC is disabled the frequency offset can be adjust ed manually by fo[9:0] in registers 73h and 74h. It is not possible to have both AFC and offset as internally they share the same register. The frequency offset adjustment and the AFC both are implemented by shifting the Synthesizer Local Oscillator frequency. This register is a signed register so in order to ge t a negative offset it is necessary to take the twos complement of the positive offset number. The offset can be calculated by the following: The adjustment range in high band is ±160 kHz and in low band it is ±80 kHz. For example to compute an offset of +50 kHz in high band mode fo[9:0] should be set to 0A0h. For an offset of –50 kHz in high band mode the fo[9:0] register should be set to 360h. 3.5.5. Automatic Frequency Control (AFC) All AFC settings can be easily obtained from the settings calculator. This is the recommended method to program all AFC settings. This section is intended to describe the operation of the AFC in more detail to help understand the trade-offs of using AFC. The receiver supports automa tic frequency control (AFC) to compensate for frequency differences between the transmitter and receiver reference frequencies. These differences can be caused by the absolute accuracy and temperature dependencies of the reference crystals. Due to frequency offset compensation in the modem, the receiver is tolerant to frequency offs ets up to 0.25 times the IF bandwidth when the AFC is disabled. When the AFC is enabled, the received signal will be centered in the pass-band of the IF filter, providing optimal sensitivity and selectivity over a wider range of frequency offsets up to 0.35 times the IF bandwidth. The trade-off of receiver sensitivity (at 1% PER) versus carrier offset and the impact of AFC are illustrated in Figure 9. Figure 8. Sensitivity at 1% PER vs. Carrier Frequency Offset Add R /W Function/Descripti on D

7 D6 D5 D4 D3 D2 D1 D0 POR

Def.

73 R/W Frequency Offset fo[7] fo[6] fo [5] fo[4] fo[3] fo[2] fo[1] fo[0] 00h

74 R/W Frequency Offset Reserved Reserved Reserved Reserved Reserved Reserved fo[9] fo[8] 00h

] 0: 9 [ ) 1 ( 25 . 156fohbsel HzsetDesiredOff  1 ( 25 . 156] 0 : 9 [   hbsel Hz setDesiredOfffo Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

abled, the preamble length needs to be long enough to settle the AFC. In general, one byte of preamble is sufficient to settle the AFC. Disabling the AFC allows the preamble to be shortened from 40 bits to 32 bits. Note that with the AFC disabled, the preamble leng th must still be long enough to settle the receiver and to detect the preamble (see "6.6. Preamble Length" ). The AFC corrects the detected frequency offset by changing the frequency of the Fracti onal-N PLL. When the pr eamble is detected, the AFC will freeze for the remainder of the packet. In multi-packet mode, the AFC is reset at the end of every packet and will re-acquire the frequency offset for the next packet. The AFC loop in cludes a bandwidth limiting mechanism improving the rejection of out of band signals. When the AFC loop is enabled, its pull-in-range is determined by the bandwidth limiter value (AFCLimiter) which is located in register 2Ah. AFC_pull_in_range = ±AFCLimiter[7:0] x (hbsel+1) x 625 Hz The AFC Limiter register is an unsigned register and its value can be obtained from the Register Calculator Frequency Correction AFC disabled Freq Offset Register AFC enabled AFC Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com spreadsheet.

1. Modulation Options 4.1. FIFO Mode In F IF O mode, the receive data is stored in integrated FIFO register memory. The FIFOs are accessed via "Register 7Fh. FIFO Access," and are most efficiently ac cessed with burst read/write operation as discussed in "3.1. Serial Peripheral Interface (SPI)" . In RX mode, only the bytes of the received packet struct ure that are considered to be "data bytes" are stored in FIFO memory. Which bytes of the received packet are considered "data bytes" is determined by the Automatic Packet Handler (if enabled), in conjunction with the Pack et Handler Registers (see Table12). If the Automatic Packet Handler is disabled, all bytes following the Sync word are considered data bytes and are stored in FIFO memory. Thus, even if Automatic Packet Handling operation is not desired, the preamble detection threshold and Sync word still need to be programmed so that th e RX Modem knows when to start filling data into the FIFO. When the FIFO is being used in RX mode, all of the received data may still be observed directly (in real- time) by properly programming a GPIO pin as the RXDATA ou tput pin; this can be quite useful during application development. When in FIFO mode, the chip will automatically exit the RX State when either the ipks ent or ipkvalid interrupt occurs. The chip will return to any of the other states based on the settings in "Register 07h. Operating Mode and Function Control 1." In RX mode, the rxon bit will be cleared if ipkvalid occurs and the rxmpk bit (RX Multi-Packet bit, SPI Register 08h bit [4]) is not set. When the rxmpk bit is set, the part will not exit the RX state after successfully receiving a packet, but will remain in RX mode. The micr ocontroller will need to decide on the appropriat e subsequent action, depending upon information such as an interrupt generated by CRC, packet valid, or preamble detect. Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

1. Inter nal Functional Blocks This section p rovides an overview some of the key blocks of the internal radio architecture. 5.1. RX LNA The input frequency range for the LNA is 433/868/915MHz band.The LNA provides gain with a noise figure low e nough to suppress the noise of the following stages. The LNA has one step of gain control which is controlled by the analog gain control (AGC) algorithm. The AGC algorithm adjusts the gain of the LNA and PGA so the receiver can handle signal levels from sensitivity to +5 dBm with optimal performance. 5.2. RX I-Q Mixer The outp ut of the LNA is fed internally to the input of the receive mixer. The receive mixer is implemented as an I-Q mixer that provides both I and Q channel outputs to the programmable gain amplifier. The mixer consists of two double-balanced mixers whose RF inputs are driven in parallel, local oscillator (LO) inputs are driven in quadrature, and separate I and Q I nt ermediate Fre quency (IF) outputs drive the prog rammable gain amplifier. The receive LO signal is supplied by an integrated VCO and PLL syn thesizer operating between 240–960 MHz. The necessary quadrature LO signals are derived from the divider at the VCO output. 5.3. Pr ogrammable Gain Amplifier The pr ogrammable gain amplifier (PGA) provides the necessary gain to boost the signal level into the dynamic range of the ADC. The PGA must also have enough gain switching to allow for large input signals to ensure a linear RSSI range up to –20 dBm. The PGA has steps of 3 dB which are controlled by the AGC algorithm in the digital modem. 5.4. ADC Th e amplified IQ IF signals are digitized using an Analog -to-Digital Converter (ADC), which allows for low current consumption and high dynamic range. The bandpass response of the ADC provides exceptional rejection of out of band blockers. 5.5. Digit al Modem Using high-performance ADCs allows channel filtering, image rejection, and demodulation to be performed in the digital domain, resulting in reduced area while increa sing flexibility. The digital modem performs the following functions:  Channel selection filter  RX demodulation  AGC  Preamble de tector  Invalid preamble detect or  Radio si gnal strength indicator (RSSI)  Automatic frequency compensation (AFC)  Packet handling includ ing EZMacTM features  Cyclic redundancy chec k (CRC) The digital channel filter and demodulator are optimized for ultra low power consumption and are highly configurable. Supported modulation types are GFSK, F SK, and OOK. The channel filter can be configured to support bandwidths ranging from 620 kHz down to 2.6 kHz . A large variety of data rates are supported ranging from 0.123 up to 256 kbps. The AGC algorithm is implement ed digitally using an advanced control loop optimized for fast response time. The configurable preamble detector is used to improve the relia bility of the sync-word de tection. The sync-word detector is only enabled when a valid preamble is detected, significantly reducing the probability of false detection. The received signal strength indicato r (RSSI) provides a measure of the si gnal strength received on the tuned channel. The resolution of the RSSI is 0.5 dB. This high resolution RSSI enables accurate channel power Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

nts for clear channel assessment (CCA), and carrier sense (CS) functionality. Frequency mistuning caused by crystal inaccuracies c an be compensated by enabling the digital automatic frequency control (AFC) in receive mode. A comprehensive programmable packet handler including key features of EZMac TM is integrated to crea te a variety of communication topologies ranging from peer-to-peer networks to mesh networks. The extensive programmability of the packet header allows for advanced packet filtering which in turn enables a mix of broadcast, group, and point-to-point communication. A wireless communication channel can be corrupted by no ise and interference, and it is therefore important to know if the received data is free of errors. A cyclic redundancy check (CRC) is us ed to detect the presence of erroneous bits in each packet. A CRC is computed an d appended at the end of each transmitted packet and verified by the receiver to confirm that no errors ha ve occurred. The packet handler and CRC can significantly reduce the load on the system microcontroller allowing for a simpler and cheaper microcontroller. 5.6. Synthesizer An integr ated Sigma Delta (ΣΔ) Fractional-N PLL synthesizer capable of operating from 240–960 MHz is provided on-chip. Using a ΣΔ synthesizer has many advantages; it provides flexibility in choosing data rate, deviation, channel frequency, and channel spacing. The PLL and  - modulator scheme is designed to support any desired frequency and channel spacing in the range from 240–960 MHz with a frequency resolution of 156.25 Hz (Low band) or 312.5 Hz (High band). Figure 9. PLL Synthesizer Block Diagram The reference frequency to the PLL is 10 MHz. The PLL utilizes a differential L-C VCO, with integrated on-chip inductors. The output of the VCO is fo llowed by a configurable divider whic h will divide down the signal to the desired output frequency band. The modu lus of the variable divide-by-N divi der stage is controlled dynamically by the output from the - modulator. The tuning resolution is sufficient to tune to the commanded frequency with a maximum accuracy of 312.5 Hz anywhere in the range between 240–960 MHz. 5.6.1. VCO The output of the VCO is automatically divided down to the correct output frequency depending on the hbsel and fb[4:0] fields in "Register 75h. Frequency Band Select." In receive mode, the LO frequency is automatically shifted downwards by the IF frequency of 937.5 kHz, allowing receive operation on the same frequency. The VCO integrates the resonator inductor and tuning varactor, so no external VCO components are required. The VCO uses a capacitance bank to cover the wide frequency range sp ecified. The capacitance bank will automatically be calibrated every time the synthesizer is enabled. In certain fast hopping applications this might not be desirable so the VCO calibration may be skipped by setting the appropriate register. N LPFCPPFDFref = 10 M VCO Sel ectable Divider RX Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

5.7. Cryst al Oscillator Th e crystal load capacitance can be digitally programme d to accommodate crystals with various load capacitance requirements and to adjust the frequency of the crystal oscillator. The tuning of t he crystal load capacitance is programmed through the xlc[6: 0] field of "Register 09h. 30 MHz Crysta l Oscillator Load Capacitance." The total internal capacitance is 12.5 pF and is adjustable in approximately 127 steps (97fF/step). The xtalshift bit provides a coarse shift in frequency but is not binary with xlc[6:0]. The crystal frequency adjustment can be used to compensate for crystal production tolerances. Utilizing the on- chip temperature sensor and suitable control softwa re, the temperature depende ncy of the crystal can be canceled. The typical value of the total on-chip capacitance Cint can be calculated as follows: Cint = 1.8 pF + 0.085 pF x xlc[6:0] + 3.7 pF x xtalshift Note that the coarse shift bit xtalshift is not binary with xlc[6:0]. The total load capacitance Cload seen by the crystal can be calculated by adding the sum of all external parasitic PCB capacitances Cext to Cint. If the maximum value of Cint (16.3 pF) is not sufficient, an external capacito r can be added for exact tuning. Additional information on calculating Cext and crystal selecti If AFC is disabled then the synthesizer frequency may be further adjusted by programming the Frequency Offset field fo[9:0]in "Register 73h. Frequen cy Offset 1" and "Register 74h. Frequen cy Offset 2", as discussed in "3.5. Frequency Control" The crystal oscillator frequency is divided down internally and may be output to the microcontroller through one of the GPIO pins for use as the System Clock. In this fashion, only one crysta l oscillator is required for the entire system and the BOM cost is reduced. The available clo ck frequencies and GPIO configuration are discussed further in "8.2. Microcontroller Clock" 5.8. Regulato rs Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

09 R/W Crystal Oscillator Load

xtalshift xlc[6] xlc[5] xlc[4] xlc[3] xlc[2] xlc[1] xlc[0] 7Fh Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com on guidelines is provided. The RFM31B includes an integrated 30MHz crystal oscillator with a fast st art-up time of less than 600s. A parallel resonant 30MHz crystal is used on the module. Th e design is differential with the required capacitance integrated on-chip to minimize the number of external components. crystal load There are a total of six regulators integrated onto the RFM31B . With the exce ption of the digital regulator, all regulators are designed to operate with only internal de coupling. input supply voltage from +1.8 to +3.6V. A supply voltage should only be connected to the VDD pins. All regulators are designed to operate with an

1. Dat a Handling and Packet Handler The interna l modem is designed to operate with a packet including a 10101... preamble structure. To configure the modem to operate with packet formats without a preamble or other legacy packet st ructures contact customer support. 6.1. RX FIFO A 64 b yte FIFO is integrated into the chip for RX, as shown in Figure 11. "Register 7Fh. FIFO Access" is used to access the FIFO. A burst read, as described in "3.1. Serial Peripheral Interface (SPI)" , from address 7Fh will read data from the RX FIFO. Figure 10. FIFO Threshold The RX FIFO h a s one programmable threshold called the FIFO Almost Full Threshold, rxafthr[5:0]. When the incoming RX data crosses the Almost Full Threshold an interrupt will be gene rated to the microcontroller via the nIRQ pin. The microcontroller will then need to read the data from the RX FIFO. The RX FIFO may be cleared or reset with the ffclrrx bit in “Register 08h. Operating Mode and Function Control 2,”. All interrupts may be enabled by setting the Interrupt Enabled bits in "Register 05h. Interrupt Enable 1" and “Register 06h. Interrupt Enable 2,”. If the interrupts are not enabled the function will not generate an interrupt on the nIRQ pin but the bits will still be read correctly in the Interrupt Status registers. Add R/W Function/D escription D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

08 R/W Operating &

antdiv[2] antdiv[1] antdiv[0] rxmpk Reserved enldm ffclrrx Reserved 00h Add R /W Function/De scription D6 D5 D4 D3 D2 D1 D0 POR Def. 7E R/W RX FIFO Control Reserved Reserved rxafthr[5] rxafthr[4] rxaf thr[3] rxafthr[2] rxafthr[1] rxafthr[0] 37h RX FI FO RX FI FO Almost Full Threshold Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

lengths to accommodate different applications. The most common CRC polynominals are available for selection. rview of the packet handler configuration registers is shown in Table 13. Figure 12. Re demonstrates the operation of fixed packet length and correct/incorrect packets.

4 Bytes

T able 12. Packet Handler Registers Add R /W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def. 30 R /W Data Access Control enpacrx lsbfrst crcdonly *Reserved Reserved encrc crc[1] crc[0] 1Dh

31 R EzMAC status Reserved rxcrc1 pksrch pkrx pkvalid crcerror Reserved Reserved —

32 R/W Header Control 1 bcen[3] enbcast[2] enbcast[1 ] enbcast[0] hdch[3] hdch[2] hdch[1] hdch[0] 0Ch

33 R/W Header Control 2 skipsyn hdlen[2] hdlen[1] hdl en[0] fixpklen synclen[1] synclen[0] prealen[8] 22h 34 R/W Preamble Length prealen[7] prealen[6] prealen[5] prealen[4] prealen[3] prealen[2] prealen[1] prealen[0] 07h 35 R/W Preamble Detection Control preath[4] preath[3] preath[2] preath[1] preath[0] Reserved Reserved Reserved 20h

36 R/W Sync Word 3 sync[31] sync[30] sync[29] sync[28] sync[27] sync[26] sync[25] sync[24] 2Dh

37 R/W Sync Word 2 sync[23] sync[22] sync[21] sync[20] sync[19] sync[18] sync[17] sync[16] D4h

38 R/W Sync Word 1 sync[15] sync[14] sync[13] sync[12] sync[11] sync[10] sync[9] sync[8] 00h

39 R/W Sync Word 0 sync[7] sync[6] sync[5] s ync[4] sync[3] sync[2] sync[1] sync[0] 00h

3A–3E R/W Reserved Reserved 3F R/W Check Header 3 chhd[31] chhd[30] chhd[29] chhd[28] chhd[27] chhd[26] chhd[25] chhd[24] 00h

40 R/W Check Header 2 chhd[23] chhd[22] chhd[21] chhd[20] chhd[19] chhd[18] chhd[17] chhd[16] 00h

41 R/W Check Header 1 chhd[15] chhd[14] chhd[13] chhd[12] chhd[11] chhd[10] chhd[9] chhd[8] 00h

42 R/W Check Header 0 chhd[7] chhd[6] chhd[5] chhd[4] chhd[3] chhd[2] chhd[1] chhd[0] 00h

43 R/W Header Enable 3 hden[31] hden[30] hden[29] hden[28] hden[27] hden[26] hden[25] hden[24] FFh

44 R/W Header Enable 2 hden[23] hden[22] hden[21] hden[20] hden[19] hden[18] hden[17] hden[16] FFh

45 R/W Header Enable 1 hden[15] hden[14] hden[13] hden[12] hden[11] hden[10] hden[9] hden[8] FFh

46 R/W Header Enable 0 hden[7] hden[6] hden[5] hden[4] hden[3] hden[2] hden[1] hden[0] FFh

47 R Received Header 3 rxhd[31] rxhd[30] rxhd[ 29] rxhd[28] rxhd[27] rxhd[26] rxhd[25] rxhd[24] —

48 R Received Header 2 rxhd[23] rxhd[22] rxhd[ 21] rxhd[20] rxhd[19] rxhd[18] rxhd[17] rxhd[16] —

49 R Received Header 1 rxhd[15] rxhd[14] rxhd[ 13] rxhd[12] rxhd[11] rxhd[10] rxhd[9] rxhd[8] —

4A R Received Header 0 rxhd[7] rxhd[6] rxhd[5 ] rxhd[4] rxhd[3] rxhd[2] rxhd[1] rxhd[0] — 4B R Received Packet Length rxplen[7 ] rxplen[6] rxplen[5] rxplen[4] rxplen[3] rxplen[2] rxplen[1] rxplen[0] — Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

preamble detection threshold and preamble length for various modes. support for further details. be shortened when occasional packet errors are tolerable. "Register 03h. Interrupt/Status 1" and “Register 04h. Interrupt/Status 2” . [1:0] = 00—Expected Synchronization Word (sync word) 3. [1:0] = 01—Expected Synchronization Word 3 first, followed by sync word 2. [1:0] = 10—Expected Synchronization Word 3 first, followed by sync word 2, followed by sync word 1. Table 13. Minimum

d. The timeout period after preamble detections is defined as the value programmed into the sync word length plus four additional bits. 6.9. Receive Header Check The he ader check is designed to support 1–4 bytes and broadcast headers. The header length needs to be set in register 33h, hdlen[2:0]. The headers to be checked need to be set in register 32h, hdch[3:0]. For instance, there can be four bytes of header in the packet structure but on ly one byte of the header is set to be checked (i.e., header 3). For the headers that are set to be checked, the expected value of the header should be programmed in chhd[31:0] in Registers 3F–42. The individual bits within the selected bytes to be checked can be enabled or disabled with the header enables, hden[31:0] in Registers 43–46. For example, if you want to check all bits in header 3 then hden[31:24] should be set to FF but if only the last 4 bits are desired to be checked then it should be set to 00001111 (0F). Broadcast headers can also be programmed by setting bcen[3:0] in Register 32h. For broadcast header check the value may be either “FFh” or the value stored in the Check Header register. A logic equivalent of the header check for Header 3 is shown in Figure 17. A similar logic check will be done for Header 2, Header 1, and Header 0 if enabled. F igure 17. Header BIT WIS E rxhd[31:24] BIT WIS E chhd[31:24] hden[31:24] = FFh hdch[3 header 3_ok Exampl e for Header 3 Equi valence comparison rxhd[31 : 24] E quivalence comparison bcen[ Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

1. RX Modem Configuration A Mi cr osoft Excel (WDS) parameter calculator or Wirele ss Development Suite (WDS) calculator is provided to determine the proper settings for the modem. The calculator can be found on www.silabs.com or on the CD provided with the demo kits. An application note is available to describe how to use the calculator and to provide advanced descriptions of the modem settings and calculations. 7.1. Modem Settings for FSK and GFSK The modem performs channel selection and demodulation in the digital domain. The channel filter bandwidth is configurable from 2.6 to 620 kHz. The receiver channel bandwidth is set depending on the data rate and modulation index via registers 1C–25h. The modulation index is equal to 2 times the peak deviation divided by the data rate (Rb). When Manchester coding is disabled, the required channel filter bandwidth is calculated as BW = 2Fd + Rb where Fd is the frequency deviation and Rb is the data rate. Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

Table 14. POR Parameters

8.2. Microcontroller Clock The 30 MHz cryst al oscillator frequency is divided down internally and may be output to the microcontroller through GPIO2. This feature is useful to lower BOM cost by using only one crystal in the system. The system clock frequency is selectable from one of 8 options, as shown below. Except for the 32.768 kHz option, all other frequencies are derived by dividing the crystal oscillator frequency. The 32.768 kHz clock signal is derived from an internal RC oscillator or an external 32 kHz crystal. The default setting for GPIO2 is to output the microcontroller clock signal with a frequency of 1 MHz. If the microcontroller clock option is being used there ma y be the need of a system clock for the microcontroller while the RFM31B is in SLEEP mode. Since the crystal oscillator is disabled in SLEEP mode in order to save current, the low-power 32.768 kHz clock can be automatically switched to become the microcontroller clock. This feature is called enable low frequency clock and is enabled by the en lfc bit in “Register 0Ah. Microcontroller Output Clock." When enlfc = 1 and the chip is in SLEEP mode then the 32.768 kHz clock will be provided to the microcontroller as the system clock, regardless of the setting of mclk[2:0]. For example, if mclk[2:0] = 000, 30 MHz will be provided through the GPIO output pin to the microcontroller as the system clock in all IDLE or RX states. When the chip enters SLEEP mode, the system clock will automatically switch to 32.768 kH z from the RC oscillator or 32.768 XTAL. Another available feature for the microcontroller clock is the clock tail, clkt[1:0] in “Register 0Ah. Microcontroller Output Clock." If the low frequency clock feature is not enabled (enlfc = 0), then the system clock to the microcontroller is disabled in SLEEP mode. However, it may be usef ul to provide a few extra cycles for the microcontroller to complete its operation prior to the shutdo wn of the system clock signal. Setting the clkt[1:0] field will provide additional cycles of the system clock before it shuts off. If an interrupt is triggered, the microcontroller clock will remain enabled regardless of the selected mode. As soon as the interrupt is read the state machine will then move to the selected mode. The minimum current consumption will not be achieved until the interrup t is read. For instance, if the ch ip is commanded to SLEEP mode but an interrupt has occurred the 30 MHz XTAL will not be disabled until the interrupt has been cleared. Add R/W Function/Description D7 D6 D 5 D4 D3 D2 D1 D0 POR Def. 0A R/W Microcontroller Output Clock clkt[1] clkt[0] enlfc mclk[2] mclk[1] mclk[0] 06h mclk[2:0] C lock Frequency 000 30 MHz 001 15 MHz 010 10 MHz 011 4 MHz 100 3 MHz 101 2 MHz 110 1 MHz 111 32.768 kHz clkt [1:0] Clock Tail 00 0 cycles 01 128 cycles 10 256 cycles 1 512 cycles Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

8.3. General Purpose ADC An 8-bit SAR ADC is integrated for general purpose use, as well as for digitizing the on-chip temperature sensor reading. Registers 0Fh "ADC Confi guration", 10h "Sensor Offset" and 4Fh "Amplifier Offset" can be used to configure the ADC operation. Every time an ADC conversion is desir ed, bit 7 "adcstart/adcbusy" in “Reg ister 1Fh. Clock Recovery Gearshift Override” must be set to 1. This is a self clearing bit that will be reset to 0 at the end of the conversion cycle of the ADC. The conversion time for the ADC is 350 µs. After this time or when the "adcstart/adcbusy" bit is cleared, then the ADC value may be read out of register 11h "ADC Value". The architecture of the ADC is shown in Figure 19. The signal and reference inputs of the ADC are selected by adcsel[2:0] and adcref[1:0] in “Register 0Fh. ADC Configuration,” respectively. The default setting is to read out the temperature sensor using the bandgap voltage (VBG) as reference. With the VBG reference the input range of the ADC is from 0–1.02 V with an LSB resolution of 4 mV (1.02/255). Changing the ADC reference will change the LSB resolution accordingly. A differential multiplexer and amplifier are provided for interfacing external bridge sensors. The gain of the amplifier is selectable by adcgain[1:0] in Register 0Fh. The majority of sensor bridges have supply voltage (VDD) dependent gain and offset. The reference voltage of the ADC can be changed to either V DD/2 or VDD/3. A pro grammable VDD depende nt offset voltage can be added using soffs[3:0] in register 10h. See “General Purpose ADC Configuration” for mo re details on the usage of the general purpose ADC. Figure 19. General Purpose ADC Architecture Add R /W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def. R/W ADC Configuration adcstart/adcbusy adcsel[2] adcsel[1] adcsel[0] adcref[1] adcref[0] adcgain[1] adcgain[0] 00h

10 R/W Sensor Offset soffs[3] soffs[2] soffs[1] soffs[0] 00h

11 R ADC Value adc[7] adc[6] adc[5] adc[4] adc[3] adc[2] adc[1] adc[0] —

…… …… D iff. MUX Diff. Amp. Input MUX Ref MUX Vin Vref adcsel [2:0] aoffs [4:0] adcgain [1:0] adcsel [2:0] adcref [1:0] adc [7:0] VDD / 3 VDD / 2 GPIO GPIO0 GPIO2 Temperature Sensor VBG (1.2V 8-bit ADC 0 -1020mV / 0-255 soffs [3:0] Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

sensor is configurable. Table 15 lists the settings for the different temperature ranges and performance.

1. Set the input for ADC to the temperature sensor, "Register 0Fh. ADC Configuration"—adcsel[2:0] = 000
2. Set the reference for ADC, "Register 0Fh. ADC Configuration"—adcref[1:0] = 00
3. Set the temperature range for ADC, "Register 12h. Temperature Sensor Calibration"—tsrange[1:0]
4. Set entsoffs = 1, "Register 12h. Temperature Sensor Calibration"
5. Trigger ADC reading, "Register 0Fh. ADC Configuration"—adcstart = 1
6. Read temperature value—Read contents of "Register 11h. ADC Value"

calibration is necessary. The temperature sensor may be calibrated by setting entsoffs = 1 in “Register 12h. ±3 °C absolute accuracy may be achieved. may be translated to a temperature reading by ADC8 Value x ADC8 LSB + Lowest Temperature in Temp Range. For instance for a tsrange = 00, Temp = ADC8Value x 0.5 – 64.

12 R/W Temperature

13 R/W Temperature Value Offset tvoff

Table 15. T

Figure 20. Temperature Ranges using ADC8 Temp erature Measurement with ADC8 100 150 250 300 -40 -20 0 20 40 60 80 10 0 T emperature [Celsius] Sens or Range 0 Sens or Range 1 Sens or Range 2 Sens or Range 3 ADC Value Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

8.5. Lo w Battery Detector A low batter y detector (LBD) with digital read-out is integrated into the chip. A digital threshold may be programmed into the lbdt[4:0] field in "Registe r 1Ah. Low Battery Detector Threshol d." When the digitized battery voltage reaches this threshold an interrupt will be generated on the nIRQ pin to the microcontroller. The microcontroller can confirm source of the interrupt by reading "Register 03h. Interrupt/Status 1" and “Register 04h. Interrupt/Status 2,”. If the LBD is enabled while the chip is in SLEEP mode, it will automatically enable th e RC oscillator which will periodically turn on the LBD circuit to measure the battery voltage. The battery voltage may also be read out through "Register 1Bh. Battery Voltage Level" at any time when the LBD is enabled. The low battery detect function is enabled by setting enlbd=1 in "Register 07h. Operating Mode and Function Control 1". The LBD output is digitized by a 5-bit ADC. When th e LBD function is enabled, enlbd = 1 in "Register 07h. Operating Mode and Function Control 1", the battery volt age may be read at anytime by reading "Register 1Bh. Battery Voltage Level." A battery voltage threshold may be programmed in “Register 1Ah. Low Battery Detector Threshold." When the battery voltage level drops below the battery voltage threshold an interrupt will be generated on the nIRQ pin to the microcontroller if the LBD interrupt is enabled in “Register 06h. Interrupt Enable 2,” The microcontroller will then need to verify the interrupt by reading the interrupt status register, addresses 03 and 04h. The LSB step size for the LBD ADC is 50 mV, with the ADC range demonstrated in the table below. If the LBD is enabled the LBD and ADC will automatically be enabled every 1 s for approximately 250 µs to measure the voltage which minimizes the current consumption in Sensor mode. Before an interrupt is activated four consecutive readings are required. Ad R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def. 1A R/W Low Battery Detector Threshold lbdt[4] lbdt[3] lbdt[2] lbdt[1] lbdt[0] 14h 1B R Battery Voltage Level 0 0 0 vbat[4] vbat[3] vbat[2] vbat[1] vbat[0] — ADC Va lue VDD Voltage [V] 0< 1.7 1 1.7–1.7 2 1.75–1.8 29 3.1–3.15 30 3.15–3.2 31 > 3.2 ADCValuemVtageBatteryVol  50 7. Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

8.6. W ake-Up Timer and 32 kHz Clock Source The chip contains an integrated wa ke-up timer which can be used to periodically wake the chip from SLEEP mode. The wake-up timer runs from the internal 32.768 kHz RC Oscillator. The wake-up timer can be configured to run when in SLEEP mode. If enwt = 1 in "Register 07h. Operating Mode and Function Control 1" when entering SLEEP mode, the wake-up timer will c ount for a time specified defined in Registers 14–16h, "Wake Up Timer Period". At the expiration of this period an interr upt will be generated on the nIRQ pin if this interrupt is enabled. The microcontroller will then need to verify the interrupt by reading the Registers 03h–04h, "Interrupt Status 1 & 2". The wake-up timer value may be read at any time by the wtv[15:0] read only registers 13h–14h. The formula for calculating the Wake-Up Period is the following: Use of the D variable in the formula is only necessary if fi ner resolution is required than can be achieved by using the R value. There are two different methods for utilizing the wake-up timer (WUT) depending on if the WUT interrupt is enabled in “Register 06h. InterruptEnable 2,”. If the WUT interrupt is enabled then nIRQ pin will go low when the timer expires. The chip will also change state so that the 30 MHz XTAL is enabled so that the microcontroller clock output is available for the microc ontroller to use to process the interrupt. The other method of use is to not enable the WUT interrupt and use the WUT GPIO setting. In this mode of operation the chip will not change state until commanded by the microcontroller. The different modes of operating the WUT and the current consumption impacts are demonstrated in Figure 21. A 32 kHz XTAL may also be used for better timing accuracy. By setting the x32 ksel bit in “Register 07h. Operating & Function Control 1," GPIO0 is automatically reconfigured so that an external 32 kHz XTAL may be connected to this pin. In this mode, the GPIO0 is extremely sensitiv e to parasitic capacitance, so only the XTAL should be connected to this pin with the XTAL physically located as close to the pin as possible. Once the x32 ksel bit is set, all internal functions such as WUT, micro-controller clock, and LDC mode will use the 32 kHz XTAL and not the 32 kHz RC oscillator. WUT Register

Description

wtr[3:0] R Value in Formula wtd[1:0] D Value in Formula wtm[15:0] M Value in Formula Add R /W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

14 R/W Wake-Up Timer Period 1 wtr[3] wtr[2] wtr[1] wtr[0] wtd[1] wtd[0] 00h

15 R/W Wake-Up Timer Period 2 wtm[15] wtm[14] w tm[13] wtm[12] wtm[11] wtm[10] wtm[9] wtm[8] 00h

16 R/W Wake-Up Timer Period 3 wtm[7] wtm[6 ] wtm[5] wtm[4] wtm[3] wtm[2] wtm[1] wtm[0] 00h

17 R Wake-Up Timer Value 1 wtv[15] wtv[14] w tv[13] wtv[12] wtv[11] w tv[10] wtv[9] wtv[8] —

18 R Wake-Up Timer Value 2 wtv[7] wtv[6] w tv[5] wtv[4] wtv[3] wtv[2] wtv[1] wtv[0] —

R 768 .32 2 4 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

Figure 21. W

8.7. Lo w Duty Cycle Mode The Low Duty Cy cle Mode is available to automatically wake-up the receiver to check if a valid signal is available. The basic operation of the low duty cycle mode is demonstrated in the figure below. If a valid preamble or sync word is not detected the chip will return to sleep mode until the beginning of a new WUT period. If a valid preamble and sync are detected the receiver on period will be extended for the low duty cycl e mode duration (TLDC) to receive all of the packet. The WUT period must be set in conjunction with the low duty cycle mode duration. The R value (Reg 14h) is shared between the WUT and the TLDC. Th e ldc[7:0] bits are located in “Register 19h. Low Duty Cycle Mode Duration.” The time of the TLDC is determined by the formula below: Figure 22. Low Duty Cycle Mode msldcTLDC R 768 .32 2 4]0 : 7 [  Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

8.8. GPIO Configurat ion Three g eneral purpose IOs (GPIOs) are available. Nume rous functions such as s pecific interrupts, Antenna Diversity Switch control, Microcontroller Output, etc. can be routed to the GPIO pins as shown in the tables below. When in Shutdown mode all the GPIO pads are pulled low. Note : The ADC should not be selected as an input to the GPIO in Standby or Sleep Modes and will cause excess current con- sumption. The GPIO settings for GPIO1 and GPIO2 are the same as for GPIO0 with the except ion of the 00000 default setting. The default settings for each GPIO are listed below: This application uses antenna diversity so a GPIO is used to control the antenna switch. For a complete list of the available GPIO's see “ RFM31B Register Descriptions.” The GPIO drive strength may be adjusted with the gpioXdrv[1:0] bits. Setting a higher va lue will increase the drive strength and current capability of the GPIO by changing the driver size. Special care should be taken in setting the drive strength and loading on GPIO2 wh en the microcontroller clock is used. Excess loading or inadequate drive may contribute to increased spurious emissions. Add R /W Function/Des cription D7 D 6 D5 D4 D3 D2 D1 D0 POR Def. 0B R/W GPIO0 Configuration gpio0drv[1] gpio0drv[0] pup0 gpio0[4] gpio0[3] gpio0[2] gpio0[1] gpio0[0] 00h 0C R/W GPIO1 Configuration gpio1drv[1] gpio1drv[0] pup1 gpio1[4] gpio1[3] gpio1[2] gpio1[1] gpio1[0] 00h 0D R/W GPIO2 Configuration gpio2drv[1] gpio2drv[0] pup2 gpio2[4] gpio2[3] gpio2[2] gpio2[1] gpio2[0] 00h 0E R/W I/O Port Configuration extitst[2] extitst[1] extitst[0] itsdo dio2 dio1 dio0 00h GPIO 000 00—Default Setting GPIO

0 POR

GPIO2 Microcontroller Clock Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com

preamble length to obtain optimal antenna selection for synchronous mode is 4 bytes.

08 R/W Operating & Function

Table 16. Antenna Div

100 Antenna Diversity Algorithm 0 0

101 Antenna Diversity Algorithm 1 1

110 Antenna Diversity Algorithm in Beacon Mode 0 0

111 Antenna Diversity Algorithm in Beacon Mode 1 1

paragraph for Clear Channel Assessment (CCA). the GPIO configuration register to GPIOx[3:0] = 1110. Figure 23. RSSI V

26 R Received

1. Reference Design Figure 24.RFM31B Reference Design Schematic Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com RFM31B

1. Register Table and Descriptions

Table 17. Register Desc

01 R Device Version 0 0 0 vc[4] vc[3] vc[2] vc[1] vc[0] 06h

02 R Device Status ffovfl ffunfl rxffem headerr reserved reserved cps[1] cps[0] —

05 R/W Interrupt Enable 1 enfferr Reserved Reserved enrxffafull enext Reserved enpkvalid encrcerror 00h

06 R/W Interrupt Enable 2 enswdet enpreaval enpreainval enrssi enwut enlbd enchiprdy enpor 03h

07 R/W Operating & Function Control 1 swres enlbd enwt x32ksel Reserved rxon pllon xton 01h

11 R ADC Value adc[7] adc[6] adc[5] a dc[4] adc[3] adc[2] adc[1] adc[0] —

14 R/W Wake-Up Timer Period 1 Reserved Reserved Reserved wtr[4] wtr[3] wtr[2] wtr[1] wtr[0] 03h

15 R/W Wake-Up Timer Period 2 wtm[15] wtm[14] wtm[13] wtm[12] wtm[11] wtm[10] wtm[9] wtm[8] 00h

16 R/W Wake-Up Timer Period 3 wtm[7] wtm[6] wtm[5] wtm[4] wtm[3] wtm[2] wtm[1] wtm[0] 01h

17 R Wake-Up Timer Value 1 wtv[15] wtv[14] wtv[13] wtv[12] wtv[11] wtv[10] wtv[9] wtv[8] —

18 R Wake-Up Timer Value 2 wtv[7] wtv[6] wtv[5] wtv[4] wtv[3] wtv[2] wtv[1] wtv[0] —

19 R/W Low-Duty Cycle Mode Duration ldc[7] ldc[6] ldc[5] ldc[4] ldc[3] ldc[2] ldc[1] ldc[0] 00h

20 R/W Clock Recovery Oversampling

24 R/W Clock Recovery Timing Loop

25 R/W Clock Recovery Timing Loop

26 R Received Signal Strength Indi-

27 R/W RSSI Threshold for Clear

30 R/W Data Access Control enpacrx lsbfrst crc donly skip2ph Reserved encrc crc[1] crc[0] 8Dh

31 R EzMAC status 0 rxcrc1 pksrch pkrx pk valid crcerror Reserved Reserved —

32 R/W Header Control 1 bcen[3:0] hdch[3:0] 0Ch

33 R/W Header Control 2 skipsyn hdlen[2] hdlen[1] hdlen[0] fixpklen synclen[1] synclen[0] prealen[8] 22h

38 R/W Sync Word 1 sync[15] sync[14] sync[13] sync[12] sync[11] sync[ 10] sync[9] sync[8] 00h

39 R/W Sync Word 0 sync[7] sync[6] sync[5] sync[4] sync[3] sync[2] sync[1] sync[0] 00h

47 R Received Header 3 rxhd[31] rxhd[30] rxhd[29] rxhd[28] rxhd[27] rxhd[26] rxhd[25] rxhd[24] —

48 R Received Header 2 rxhd[23] rxhd[22] rxhd[21] rxhd[20] rxhd[19] rxhd[18] rxhd[17] rxhd[16] —

49 R Received Header 1 rxhd[15] rxhd[14] rxhd[13] rxhd[12] rxhd[11] rxhd[10] rxhd[9] rxhd[8] —

60 R/W Channel Filter Coefficient

61 Reserved

62 R/W Crystal Oscillator/Control Test pwst[2] pwst[1] pwst[0] clkhyst enbias2x enamp2x bufovr enbuf 24h

69 R/W AGC Override 1 Reserved sgi agcen lnagain pga3 pga2 pga1 pga0 20h

70 R/W Modulation Mode Control 1 Reserved Reserved enphpwdn manppol enmaninv enmanch enwhite 0Ch

71 R/W Modulation Mode Control 2 trclk[1] trclk[0] dtmod[1] dtmod[0] eninv fd[8] modtyp[1] modtyp[0] 00h

Table 17. Registe

76 R/W Nominal Carrier Frequency 1 fc[15] fc[14] fc[13] fc[12] fc[11] fc[10] fc[9] fc[8] BBh

77 R/W Nominal Carrier Frequency 0 fc[7] fc[6] fc[5] fc[4] fc[3] fc[2] fc[1] fc[0] 80h

78 Reserved

Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com 11. Pin Descriptions: RFM31B R F M 3 1 B - S 1 RFM31B-S2 R F M 3 1 B - D IC RFM31B

Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com VCC S +1.8 to +3.6 V supply voltage. The recommended V CC supply voltage is +3.3 V. GND S Ground reference. GPIO_0 I/O GPIO_1 I/O GPIO_2 I/O General Purpose Digital I/O that may be configured through the registers to perform various functions including: Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery Detect, TRSW, AntDiversity control, etc. See the SPI GPIO Configuration Registers, Address 0Bh, 0Ch, and 0Dh for more information. SDO O 0–V CC V digital output that provides a serial readback function of the internal control registers. SDI I Serial Data input. 0–V CC V digital input. This pin provides the serial data stream for the 4-line serial data bus. SCLK I Serial Clock input. 0–V DD V digital input. This pin provides the serial data clock function for the 4-line serial data bus. Data is clocked into the RFM31 on positive edge transitions. nSEL I Serial Interface Select input. 0– V CC V digital input. This pin provides the Select/Enable function for the 4-line serial data bus. The signal is also used to signify burst read/write mode. nIRQ O General Microcontroller Interrupt Status outpu t. When the RFM31 exhibits anyone of the Interrupt Events the nIRQ pin will be set low=0. Please see the Control Logic registers section for more information on the Interrupt Events. The Microcontroller can then determine the state of the interrupt by reading a corresponding SPI Interrupt Status Registers, Address 03h and 04h. SDN I Shutdown input pin. 0–V CC V digital input. SDN should be = 0 in all modes except Shutdown mode. When SDN =1 the chip will be completely shutdown and the contents of the registers will be lost. ANT I/O RF signal input.(50 OHM input Impedance NC No Connection RFM31B

Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com 12. Mechanical Dimension: RFM31B SMD PACKAGE（S1） SMD PACKAGE（S2） RFM31B

Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com DIP PACKAGE（D） RFM31B

Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com 13. Ordering Information Part Number module type—operation band—package type RFM31B —433 module type operation band Package example：1，RFM31B module at 433MHz band, DIP : RFM31B-433-D。 2 ，RFM31B module at 868MHZ band, SMD, thickness at 4.9mm: RFM31B-868-S1。 RFM31B

Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com RFM31B 14. IC Information

Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com RFM31B

Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com RFM31B 15. Pin Descriptions

Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com RFM31B 17. PCB Land Pattern Figure 26 illustrates the PCB land pattern details for the IC using in the module. Table 24 lists the values for the dimensions shown in the illustration.

Table 19. PCB Land Pattern Dimensions

1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal

walls should be used to assure good solder paste release.

1. The stencil thickness should be 0.125 mm (5 mils).
2. The ratio of stencil aperture to land pad size should be 1:1 for the
3. A 2x2 array of 1.10 x 1.10 mm openings on 1.30 mm pitch should be

used for the center ground pad.

1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020

specification for small body components.

HOPE MICROELECTRONICS CO.,LTD Add:4/F, Block B3, East Industrial Area, Huaqiaocheng, Shenzhen, Guangdong, China Tel: 86-755-82973805 Fax: 86-755-82973550 Email: sales@hoperf.com t rade@hoperf.com Website: http://www.hoperf.com http://hoperf.en.alibaba.com This document may contain preliminary information and is subject to change by Hope Microelectronics without notice. Hope Microelectronics assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of Hope Microelectronics or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in the direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MECHANTABILITY OR FITNESS FOR A ARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT. ©2006, HOPE MICROELECTRONICS CO.,LTD. All rights reserved. Tel: +86-755-82973805 Fax: +86-755-82973550 E-ma il: sales@hoperf.com ht tp://www. hoperf.com 5 57 RFM31B