RFM26W

RFM26W HOPE | Alldatasheet

Document overview

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Technical content

Features

„ Frequency range = 142–1050 MHz „ Power supply = 1.8 to 3.6 V „ Receive sensitivity = –126 dBm „ Modulation z (G)FSK & 4(G)FSK z OOK & ASK „ +20 dBmMax output power „ PA support for +27dBm „ Low active power consumption z 10/13 mA RX „ Excellent selectivity performance z 50 dB adjacent channel „ > 73 dB blocking at 1 MHz „ Antenna diversity and T/R switch control „ Highly configurable packet handler „ TX and RX 64 byte FIFOs „ Auto frequency control (AFC) „ Automatic gain control (AGC) „ Low Battery Detector „ Ultra low current powerdown modes z 30 nA shutdown, 50 nA standby „ Data rate = 0.123 kbps to 1Mbps „ Fast wake and hop times „ Low BOM „ Temperature Sensor

Applications

„ Smart metering (802.15.4g & Mbus) „ Remote keyless entry „ Remote control „ Home security and alarm „ Telemetry „ Garage and gate openers „ Home automation „ Industrial control „ Sensor networks „ Health monitors

Description

The RFM26W module is high-performance, low current transceiver covering the sub-GHz frequency bands from 142 to1050 MHz. It offers outstanding sensitivity of –126 dBm while achieving extremely low active and standby current consumption. The RFM26W offers continuous frequency coverage across the entire sub-GHz band from 142–1050 MHz with extremely fine frequency resolution. The RFM26W includes optimal phase noise, blocking, and selectivity performance for narrow band and licensed band applications such as FCC Part90 and 169 MHz wireless Mbus. The 50 dB adjacent channel selectivity with 25 kHz channel spacing ensures robust receive operation in harsh RF conditions, which is particularly important for narrowband operation. The RFM26W offers exceptional output power of up to +20 dBm with outstanding TX efficiency. The high output power and sensitivity results in an industry leading link budget of 146 dB allowing extended ranges and highly robust communication links. The RFM26W can achieve up to +27 dBm output power with built in ramping control of a low-cost, external FET. The devices are compliant with all worldwide regulatory standards:The module is compliant with all worldwide regulatory standards: FCC, ETSI, and ARIB. All devices are designed to be compliant with 802.15.4g and WMbus smart metering standards. RFM26W

T el: +86-755-82973805 F ax: +86-755-82973550 E -mail: sales@hoperf.com http:// www.hoperf.com RFM26W Functional Block Diagram

T el: +86-755-82973805 F ax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM26W TABLE OF C ONTENT S Section Page

1. Electrical Specifications

Table 1. DC Characteristics1 tained, and all other blocks OFF.

1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are

listed in the "Production Test Conditions" section of "1.1. Definition of Test Conditions" on page 11.

1. Guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test Conditions" section in "1.1.

Definition of Test Conditions" on page 11.

Table 2. Synthesizer AC Electrical Characteristics1

1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits

are listed in the "Production Test Conditions" section in "1.1. Definition of Test Conditions" on page 11.

1. Guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test Conditions" section in

"1.1.Definition of Test Conditions" on page 11.

Table 3. Receiver AC Electrical Characteristics1

1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are

listed in the "Production Test Conditions" section in "1.1. Definition of Test Conditions" on page 11.

1. Guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test Conditions" section in "1.1.

Definition of Test Conditions" on page 11.

Table 3. Receiver AC Electrical Characteristics1 (Continued) Table 4. Transmitter AC Electrical Characteristics1

1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are

listed in the "Production Test Conditions" section in "1.1. Definition of Test Conditions" on page 11.

1. Guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test Conditions" section in "1.1.

Definition of Test Conditions" on page 11.

1. Output power is dependent on matching components and board layout.
2. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are

listed in the "Production Test Conditions" section in "1.1. Definition of Test Conditions" on page 11.

1. Guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test Conditions" section in "1.1.

Definition of Test Conditions" on page 11.

Table 4. Transmitter AC Electrical Characteristics1 (Continued)

1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are

listed in the "Production Test Conditions" section in "1.1. Definition of Test Conditions" on page 11.

1. Guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test Conditions" section in "1.1.

Definition of Test Conditions" on page 11.

1. Output power is dependent on matching components and board layout.

Table 5. Auxiliary Block Specifications1

15 MHz, 10 MHz, 4 MHz,

3 MHz, 2 MHz, 1 MHz, or

32 MHz

30 MHz XTAL Start-Up time t30M Using XTAL and board layout in

30 MHz XTAL Cap

1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are

listed in the "Production Test Conditions" section in "1.1. Definition of Test Conditions" on page 11.

1. Guaranteed by qualification. Qualification test conditions are listed in the "Qualification Test Conditions" section in "1.1.

Definition of Test Conditions" on page 11.

Table 6. Digital IO Specifications (GPIO_x, SCLK, SDO, SDI, nSEL, nIRQ) Table 7. Absolute Maximum Ratings

T el: +86-755-82973805 F ax: +86-755-82973550 E -mail: sales@hoperf.com http:// www.hoperf.com RFM26W 1.1. Definition of Test Conditions Production Test Conditions: „ TA = +25 °C „ VDD = +3.3 VDC „ Sensitivity measured at 919 MHz „ TX output power measured at 915 MHz „ External reference signal (XOUT) = 1.0 VPP at 30 MHz, centered around 0.8 VDC „ Production test schematic (unless noted otherwise) „ All RF input and output levels referred to the pins of the RFM26W module Qualification Test Conditions: „ TA = –40 to +85 °C „ VDD = +1.8 to +3.6 VDC „ Using TX/RX Split Antenna reference design or production test schematic „ All RF input and output levels referred to the pins of the RFM26W Module

T el: +86-755-82973805 F ax: +86-755-82973550 E -mail: sales@hoperf.com http:// www.hoperf.com RFM26W 2. Functional Description The RFM26W module is high-performance, low-current, wireless ISM transceivers that cover the sub-GHz bands. The wide operating voltage range of 1.8–3.6 V and low current consumption make the RFM26W an ideal solution for battery powered applications. The RFM26W operates as a time division duplexing (TDD) transceiver where the device alternately transmits and receives data pa ckets. The device uses a single-conversion mixer to downconvert the 2/4-level FSK/GFSK or OOK/ASK modulated re ceive signal to a low IF frequency. Following a programmable gain amplifier (PGA) the signal is conv erted to the digital domain by a high performance ∆Σ ADC allowing filtering, demodulation, slicing, and packet handling to be performed in the built-in DSP increasing the receiver’s performance and flexibility versus analog based architectures. The demodulated signal is output to the system MCU through a programmable GPIO or via the standard SPI bus by reading the 64-byte RX FIFO. A single high precision local oscillator (LO) is used fo r both transmit and receive modes since the transmitter and receiver do not operate at the same time. The LO is generated by an integrated VCO and ∆Σ Fractional-N PLL synthesizer. The synthesizer is designed to support configurable data rates from 0.123 kbps to 1 Mbps. The RFM26W operates in the frequency bands of 142–175, 283–350, 425–525, and 850–1050 MHz with a maximum accuracy of 57.22 Hz frequency accuracy. The transmit FSK data is modulated directly into the ∆Σ data stream and can be shaped by a Gaussian low-pass filter to reduce unwanted spectral content. The RFM26W contains a power amplifier (PA) that supports output power up to +20 dBm with very high efficiency, consuming only 70 mA at 169 MHz and 85 mA at 915 MHz. The integrated +20 dBm power amplifier can also be used to compensate for the reduced performance of a lower cost, lower performance antenna or antenna with size constraints due to a small form-factor. Competing solutions require large and expensive external PAs to achieve comparable performance. Class-E matching provides optimal current consumption, while switched-current matching demonstrates the best performance over varying battery voltage with slightly higher current consumption. The PA is single-ended to allow for easy antenna matching and low BOM cost. The PA incorporates automatic ramp-up and ramp-down control to reduce unwanted spectral spreading. The RFM26W supports frequency hopping, TX/RX switch control, and ante nna diversity switch control to extend the link range and improve performance. Built-in antenna diversity and support for frequency hopping can be used to further extend range and enhance performance. Antenna diversity is completely integrated into the RFM26W and can improve the system link budget by 8–10 dB, resulting in substantial range increases under adverse environmental conditions. A highly configurable packet handler allows for autonomous encoding/decoding of nearly any packet structure. Additional system features , such as an automatic wake-up timer, low battery detector, 64 byte TX/RX FIFOs, and preamble detection, reduce overall current consumption and allows for the use of lower-cost system MCUs. An integrated temperat ure sensor, power-on-reset (POR), and GPIOs further reduce overall system cost and size. The RFM26W is designed to work with an MCU, crystal, and a few passives to create a very low-cost system.

aligned with the center of the SDI data. Table 8. Serial Interface Timing Parameters Figure 3. SPI Write Command should process the SDO data on the rising edge of SCLK.

“FRR_CTL_X_MODE” properties. There are four primary states in the Si446x radio state machine: SHUTDOWN, IDLE, TX, and RX (see Figure 6). to reach either RX or TX mode as well as the current consumption of each mode. Figure 6. State Machine Diagram Table 9. Operating Modes Response Time and Current Consumption

T el: +86-755-82973805 F ax: +86-755-82973550 E -mail: sales@hoperf.com http:// www.hoperf.com RFM26W 3.3.1. SHUTDOWN State The SHUTDOWN state is the lowest current consumption st ate of the device with nominally less than 20 nA of current consumption. The shutdown state may be entered by driving the SDN pin (Pin 1) high. The SDN pin should be held low in all states except the SHUTDOWN state. In the SHUTDOWN state, the contents of the registers are lost and there is no SPI access. When coming out of the SHUTDOWN state a power on reset (POR) will be initiated along with the internal calibrations. 3.3.2. IDLE States There are five different modes in the IDLE state which may be commanded. All modes have a tradeoff between current consumption and response time to TX/RX mode. This tradeoff is shown in Table 9. After the POR event, SWRESET, or exiting from the SHUTDOWN state the chip will default to the IDLE-READY mode. 3.3.3. STANDBY Mode STANDBY mode has the lowest current consumption of the fi ve IDLE states. In this state the register values are maintained with all other blocks disabled. The SPI is ac cessible during this mode but an SPI event will enable an internal boot oscillator and automatically move the part to SPI ACTIVE mode. After an SPI event the host will need to re-command the device back to STANDBY mode through the “Change State” API command to achieve the 100 nA current consumption. If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current consumption of this mode. 3.3.4. SLEEP Mode In SLEEP mode the Wake-Up-Timer and a 32 kHz clock sour ce are enabled. The source of the 32 kHz clock can either be an internal 32 kHz RC oscillator which is periodica lly calibrated or a 32 kHz oscillator using an external XTAL.The SPI is accessible during this mode but an SPI event will enable an internal boot oscillator and automatically move the part to SPI ACTIVE mode. After an SPI event the host will need to re-command the device back to SLEEP. If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt regi sters must be read to achieve the minimum current consumption of this mode. 3.3.5. SPI ACTIVE Mode In SPI ACTIVE mode the SPI and a boot up oscillator are enabled. After SPI transactions during either STANDBY or SLEEP mode the device will not automatically return to these modes. A “Change State” API command will be required to return to either the STANDBY or SLEEP modes. 3.3.6. READY Mode READY Mode is designed to give a fast transition time to TX or RX state with reasonable current consumption. In this mode the Crystal oscillator remains enabled reducing th e time required to switch to TX or RX mode by eliminating the crystal start-up time. 3.3.7. TX State The TX state may be entered from any of the IDLE modes by using the “Start TX” or “Change State” API command. A built-in sequencer takes care of all the actions required to transition between states from enabling the crystal oscillator to ramping up the PA. The following sequence of events will occur automatically when going from STANDBY mode to TX mode. 1. Enable the digital LDO and the analog LDOs. 2. Start up crystal oscillator and wait until ready (controlled by an internal timer). 3. Enable PLL. 4. Calibrate VCO/PLL. 5. Wait until PLL settles to required transmit frequency (controlled by an internal timer). 6. Activate power amplifier and wait until power ramping is completed (controlled by an internal timer). 7. Transmit packet. Steps in this sequence may be eliminated depending on which IDLE mode the chip is configured to prior to commanding to TX. By default, the VCO and PLL are calibrat ed every time the PLL is enabled. When the “Start TX” API command is utilized the next state may be defined to ensure optimal timing and turnaround.

T el: +86-755-82973805 F ax: +86-755-82973550 E -mail: sales@hoperf.com http:// www.hoperf.com RFM26W 3.3.8. RX State The RX state may be entered from any of the IDLE modes by using the “Start RX” or “Change State” API command. A built-in sequencer takes care of all the actions required to transition from one of the IDLE modes to the RX state. The following sequence of events will occu r automatically to get the chip into RX mode when going from STANDBY mode to RX mode: 1. Enable the digital LDO and the analog LDOs. 2. Start up crystal oscillator and wait until ready (controlled by an internal timer). 3. Enable PLL. 4. Calibrate VCO 5. Wait until PLL settles to required receive frequency (controlled by an internal timer). 6. Enable receiver circuits: LNA, mixers, and ADC. 7. Enable receive mode in the digital modem. Depending on the configuration of the radio all or some of the following functions will be performed automatically by the digital modem: AGC, AFC (optional), update status registers, bit synchronizati on, packet handling (optional) including sync word, header check, and CRC. Similar to the TX state the next state after RX may be defined in the “Start RX” API command.

commands are shown in Table 10. Table 10. API Commands

arguments unless it is desired to change these arguments. Figure 9. Start TX Command Description

T el: +86-755-82973805 F ax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM26W 3.5. Interrupts The RFM26W is capable of generating an interrupt signal when certain events occur. The chip notifies the microcontroller that an interrupt event has occurred by setting the nIRQ output pin LOW = 0. This interrupt signal will be generated when any one (or more) of the interr upt events (corresponding to the Interrupt Status bits) occur. The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Registers. The nIRQ output signal will then be reset until the next change in status is detected. The interrupts sources are grouped into three groups: Packet Handler, Chip Status, and Modem. The individual interrupts in these groups can be enabled/disabled in the interrupt property registers, 0101, 0102, and 0103. An interrupt must be enabled for it to trigger an event on the nIRQ pin. The interrupt group must be enabled as well as the individual interrupts in API property 0100. Once an interrupt event occurs and the nIRQ pin is low there are two ways to read and clear the interrupts. All of the interrupts may be read and cleared in the “Get INT Status” API command. By default all interrupts will be cleared once read. If only specific interrupts want to be read in the fastest possible method the individual interrupt groups (Packet Handler, Chip Status, Modem) may be read and cleared by the “Get Modem Status”, “Get PH (packet handler) Status, and “Get Chip Status” API commands. The instantaneous status of a specific function maybe read if the specific interrupt is enabled or disabled. The status results are provided after the interrupts and can be read with the same commands as the interrupts. The fast response registers can also give information about the interrupt groups but reading the fast response registers will not clear the interrupt and reset the nIRQ pin.

1. Modulation and Hardware Configuration Options

set in API property, MODEM_MOD_TYPE. Figure 10. Modulation and Hardware Configuration Options be selected to be a pseudo-random source for evaluation purposes. configurations options of these three main methods that will be described in the individual subsections. „ FIFO Mode—Utilizes the internal 64byte TX and RX FIFO’s. Permits use of the internal packet handler. „ RAW Direct Mode—Data is programmed directly onto a GPIO but a 101010.. preamble is NOT used.

T el: +86-755-82973805 F ax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM26W 4.2.1. FIFO Mode In FIFO mode, the transmit and receive data is stored in integrated FIFO register memory. The TX FIFO is accessed by writing command 66h followed directly by the data /clk that the host wants to write into the TX FIFO. The RX FIFO is accessed by writing command 77h followe d by the number of clock cycles of data the host would like to read out of the RX FIFO. The RX data will be clocked out onto the SDO pin. In TX mode if the packet handler is enabled, the data by tes stored in FIFO memory are "packaged" together with other fields and bytes of information to construct the fina l transmit packet structure. These other potential fields include the Preamble, Sync word, Header, CRC checksum, et c. The configuration of th e packet structure in TX mode is determined by the Automatic Packet Handler (if en abled), in conjunction with a variety of Packet Handler properties. If the Automatic Packet Handler is disabled, the entire desired packet structure should be loaded into FIFO memory; no other fields (such as Preamble or Sync word will be automat ically added to the bytes stored in FIFO memory). For further information on the configuration of the FIFOs for a specific application or packet size, see "6. Data Handling and Packet Handler" on page 29. In RX mode, only the bytes of the received packet structure that are considered to be "data bytes" are stored in FIFO memory. Which bytes of the received packet are considered "data bytes" is determined by the Automatic Packet Handler (if enabled), in conjunction with the Packet Handler configuration. If the Automatic Packet Handler is disabled, all bytes following the Sync word are considered data bytes and are stored in FIFO memory. Thus, even if Automatic Packet Handling operation is not desired, the preamble detection threshold and Sync wo rd still need to be programmed so that the RX Modem knows when to start filling data into the FIFO. When the FI FO is being used in RX mode, all of the received data may still be observed directly (in realtime) by properly programming a GPIO pin as the RXDATA output pin; this can be quite useful during application development. When in FIFO mode, the chip will automatically exit the TX or RX State when either the ipksent or ipkvalid interrupt occurs. The chip will return to the IDLE state programmed in the argument of the “START TX” or “START RX” API command, TXCOMPLETE_STATE[3:0] or RXCOMPLETE_STATE[3:0]. For example, the chip may be placed into TX mode by sending the “START TX” command and by writing the 30h to the TXCOMPLETE_STA TE[3:0] argument. The chip will transmit all of the contents of the FIFO and the ipksent interrupt will occur. When this event occurs, the chip will return to the READY state as defined by TXCOMPLETE_STATE[3:0] = 30h. 4.2.2. Direct Mode For legacy systems that perform packet handling within t he host MCU or other baseband chip, it may not be desirable to use the FIFO. For this scenario, a Direct Mode is provided which bypasses the FIFOs entirely. In TX direct mode, the TX modulation data is applied to an input pin of the chip and processed in "real time" (i.e., not stored in a register for transmission at a later time). An y of the GPIO may be configured for use as the TX Data input function. Furthermore, an additional pin may be requir ed for a TX Clock output function if GFSK modulation is desired (only the TX Data input pin is required for F SK). To achieve direct mode the GPIO must be configured in “GPIO_PIN_CFG” API command as well as the “MODEM_MOD_TYPE” API property. For GFSK “TX_DIRECT_MODE_TYPE” must be set to synchronous. For ASK or FSK direct mode type should be set to asynchronous. The MOD_SOURCE[1:0] should be set to 01h for are all direct mode configurations. In RX direct mode, the RX Data and RX Clock can be programmed fo r direct (real-time) output to GPIO pins. The microcontroller may then process the RX data without using the FIFO or packet handler functions of the RFIC. In RX direct mode, the chip must still acquire bit timi ng during the Preamble, and thus the preamble detection threshold must still be programmed. On ce the preamble is detected, certai n bit timing functions within the RX Modem change their operation for optimized performance over the remainder of the packet. It is not required that a Sync word be present in the packet in RX Direct mode; however, if the Sync word is absent then the skipsyn bit must be set, or else the bit timing and tracking function within the RX Modem will not be configured for optimum performance. 4.2.3. RAW Direct Mode The only difference between RAW Direct Mode and Direct Mode is the structure of the packet being used. In a conventional packet structure there is a 101010 preamble pattern which the internal modem uses to perform such functions as clock recovery. Many legacy applications do not have a 101010 preamble pattern so a special demodulator has been designed into the Si446x family to handle these types of application scenarios. The RAW mode demodulator will result in slightly less perfor mance than the standard demodulator with a conventional preamble pattern but it will still provide glitch-less, stab le, low jitter data. To achieve RAW mode the device should be configured as described in “4.2.2. Direct Mode” and also the RAW mode options should be selected in the calculator API.

T el: +86-755-82973805 F ax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM26W 5. Internal Functional Blocks The following sections provide an overview to the key internal blocks and features. 5.1. RX Chain The internal low-noise amplifier (LNA) is designed to be a wide-band LNA that can be matched with three external discrete components to cover any common range of frequencies in the sub-GHz band. The LNA has extremely low noise to suppress the noise of the following stages to achi eve optimal sensitivity so no external gain or front-end modules are necessary. The LNA has gain control which is controlled by the internal automatic gain control (AGC) algorithm. The LNA is followed by an I-Q mixer, filt er, programmable gain amplifier (PGA), and ADC. The I-Q mixers downconvert the signal to an intermediate frequency. The PGA then boosts the gain to be within dynamic range of the ADC. The ADC rejects out of band blockers and converts the signal to the digital domain where filtering, demodulation, and processing is performed. Peak detectors are integrated at the output of the LNA and PGA for use in the AGC algorithm. 5.2. RX Modem Using high-performance ADCs allows channel filtering, image rejection, and demodulation to be performed in the digital domain which allows for large amounts of flexibility to optimize the device for a particular application. The digital modem performs the following functions: „ Channel selection filter „ TX modulation „ RX demodulation „ Automatic Gain Control (AGC) „ Preamble detection „ Invalid preamble detection „ Radio signal strength indicator (RSSI) „ Automatic frequency compensation (AFC) „ Packet handling including EZMAC® features „ Cyclic redundancy check (CRC) The digital channel filter and demodulator are optim ized for ultra low power consumption and are highly configurable. Supported modulation types are GFSK, FSK, 4GFSK, 4FSK, ASK, and OOK. The channel filter can be configured to support bandwidths ranging from 850 dow n to 1.1 kHz. A large variety of data rates are supported ranging from 0.123 up to 1 Mbps. The configurabl e preamble detector is used to improve the reliability of the sync-word detection. The sync-word detector is only enabled when a valid preamble is detected, significantly reducing the probability of false detection. The received signal strength indicator (RSSI) provides a measure of the signal strength received on the tuned channel. The resolution of the RSSI is 0.5 dB. This high resolution RSSI enables accurate channel power measur ements for clear channel assessment (CCA), carrier sense (CS), and listen before talk (LBT) functionality. T he extensive programmability of the packet header allows for advanced packet filtering which in turn enables a mix of broadcast, group, and point-to-point communication. A wireless communication channel can be corrupted by noise a nd interference, and it is therefore important to know if the received data is free of errors. A cyclic redundancy check (CRC) is used to detect the presence of erroneous bits in each packet. A CRC is computed and appended at the end of each transmitted packet and verified by the receiver to confirm that no errors have occurred. The packet handler and CRC can significantly reduce the load on the system microcontroller allowing for a simpler and cheaper microcontroller. The digital modem includes the TX modulator which converts the TX data bits into the co rresponding stream of digital modulation values to be summed with the fractional input to the sigma-delta modulator. This modulation approach results in highly accurate resolution of the frequency deviation. A Gaussian filter is im plemented to support GFSK and 4GFSK, considerably reducing the energy in the adjacent channels. The default bandwidth-time product (BT) is 0.5 for all programmed data rates, but it may be adjusted to other values.

T el: +86-755-82973805 F ax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM26W 5.2.1. Automatic Gain Control (AGC) The AGC algorithm is implemented digitally using an advanced control loop optimized for fast response time. The AGC occurs within a single bit or in less than 2 µs. Peak detectors at the output of the LNA and PGA allow for optimal adjustment of the LNA gain and PGA gain to optimize IM3, selectivity, and sensitivity performance. 5.2.2. Auto Frequency Correction (AFC) Frequency mistuning caused by crystal inaccuracies ca n be compensated by enabling the digital automatic frequency control (AFC) in receive mode. There are two types of integrated frequency compensation, modem frequency compensation, and AFC by adjusting the PLL frequency. With AFC disabled the modem compensation can correct for frequency offsets up to ±0.25 times the IF bandwidth. When the AFC is enabled, the received signal will be centered in the pass-band of the IF filter, providi ng optimal sensitivity and selectivity over a wider range of frequency offsets up to ±0.35 times the IF bandwidth. When AFC is enabled, the preamble length needs to be long enough to settle the AFC. In general, one byte of preamble is sufficient to settle the AFC. 5.2.3. Image Rejection and Calibration Since the receiver utilizes a low-IF architecture the selectivity will be affected by the image frequency. The IF frequency is 468.75kHz and the image frequency will be at 937.5kHz below the RF frequency. The native image rejection of the RFM26W is 35dB. The calibration is perfor med during the initial cold boot and does not require an external signal source. Also available in the Si4464/63 is the option to shift the IF frequency. With this option the IF frequency can be shifted to the adjacent channel putting the image frequency in the alternate channel. 5.2.4. Received Signal Strength Indicator The received signal strength indicator (RSSI) is an estima te of the signal strength in the channel to which the receiver is tuned. The RSSI measurement is done after the channel filter so it is only a measurement of the in-band signal power, desired or undesired. There are multiple options for reading the RSSI which are configured in “MODEM_RSSI_CONTROL”. The RSSI can be set to update every bit or averaged over a four bit period. A latched version of the RSSI may be saved and read after the packet. The current RSSI value or latched RSSI value are read by readying the “GET_MODEM_STATUS” API command. The RSSI value can also be programmed into one of the fast response registers. Clear channel assessment (CCA) may also be performed by programming an RSSI threshold in “MODEM_RSSI_THRESH” and enabling this interrupt or programming a GPIO for this function. To minimize the amount of time associated with reading the RSSI for frequency hopping applications automatic hop control is available based on an RSSI threshold. Automatic hop features are available to hop based on the availability of preamble or not, see the section for fast frequency hopping for more details on this feature.

T el: +86-755-82973805 F ax: +86-755-82973550 E -mail: sales@hoperf.com http:// www.hoperf.com RFM26W 5.3. Synthesizer An integrated Sigma Delta (Σ∆) Fractional-N PLL synthesizer capable of operating over the bands from 142–175, 283-350MHz, 425–525, and 850–1050 MHz. Using a Σ∆ synthesizer has many advantages; it provides flexibility in choosing data rate, deviation, channel frequency, and channel spacing. The transmit modulation is applied directly to the loop in the digital domain through the fractional di vider which results in very precise accuracy and control over the transmit deviation. The frequency resolution in the 850–1050 MHz band is 57.22 Hz with more resolution in the other bands. The nominal reference frequency to the PLL is 30 MHz but any XTAL frequency from 25MHz to 32MHz may be used. The configuration calculator will automatically account for the XTAL frequency being used. The PLL utilizes a differential LC VCO, with integrated on -chip inductors. The output of the VCO is followed by a configurable divider which will divide down the signal to the desired output frequency band. 5.3.1. Synthesizer Frequency Control 5.3.1.1. EZ Frequency Programming 5.3.1.2. Fast Frequency Hopping

T el: +86-755-82973805 F ax: +86-755-82973550 E -mail: sales@hoperf.com http://www.hoperf.com RFM26W 5.4. Transmitter (TX) The RFM26W is designed to supply +10dBm output power for less than 20mA for applications which require operation from a single coin cell battery. The RFM26W can also operate with either class-E or switched current matching. All PA options are single-ended to allow for easy antenna matching and low BOM cost. Automatic ramp-up and ramp-down is automatically performed to reduce unwanted spectral spreading. 5.5. Crystal Oscillator The RFM26W includes an integrated crystal oscillator with a fast start-up time of less than 250 μs. The design is differential with the required crystal load capacitance integrated on-chip to minimize the number of external components. By default, all that is required off-chip is t he crystal. The default crystal is 30MHz but the circuit is designed to handle any XTAL from 25 to 32 MHz. If a crystal different than 30MHz is used the “GLOBAL_CLK_XTAL_ADJUST” API property must be modifi ed. The crystal load capacitance can be digitally programmed to accommodate crystals with various load ca pacitance requirements and to adjust the frequency of the crystal oscillator. The tuning of the crystal load ca pacitance is programmed through “XXX” API property. The total internal capacitance is 12.7 pF and is adjustable in 127 steps (100 fF/step). The crystal frequency adjustment can be used to compensate for crystal production tolerances. Utilizing the on-chip temperature sensor and suitable control software, the temperature dependency of the crystal can be canceled. A TCXO or external signal source can easily be used in lieu of a conventional XTAL and should be connected to the XIN pin. The incoming signal is ac coupled internally to a squaring buffer so no external ac coupling or dc bias is required. If dc is provide it should be set to 500 mV. The incoming signal amplitude is should be set in the range from 500–900 mV. The internal capacitor bank will create a capacitive divider when an external source is used so the XTAL capacitor bank should be set to 0.

T el: +86-755-82973805 F ax: +86-755-82973550 E -mail: sales@hoperf.com http:// www.hoperf.com RFM26W 7. RX Modem Configuration The RFM26W can easily be configured for different datarate, deviation, frequency, etc. by using the WDS settings calculator which will generate an initialization file to be used by the host MCU. 8. Auxiliary Blocks 8.1. Temperature Sensor 8.2. Low Battery Detector 8.3. Wake-up Timer and 32 kHz Clock Source 8.4. Low Duty Cycle Mode (Auto RX Wake-Up) 8.5. Antenna Diversity

T el: +86-755-82973805 F ax: +86-755-82973550 E -mail: sales@hoperf.com http:// www.hoperf.com RFM26W 9. Reference Design RFM26W Reference Design Schematic 1

T el: +86-755-82973805 F ax: +86-755-82973550 E -mail: sales@hoperf.com http:// www.hoperf.com RFM26W 10. Pin Descriptions RFM26W-S2 Pin Name I/0 Description GND GND Connect to PCB ground. SDN I Shutdown Input Pin. 0–VCC V digital input. SDN should be = 0 in all modes except Shutdown mode. When SDN =1 the chip will be completely shutdown and the contents of the registers will be lost. NIRQ I General Microcontroller Interrupt Status Output. When the Si4463/62/61 exhibits anyone of the interrupt events the nIRQ pin will be set low=0. The Microcontroller can then determine the state of the interrupt by reading the interrupt status. No external resistor pull-up is required but it may be NSEL I Serial Interface Select Input. 0–VCC V digital input. This pin provides the Select/Enable function for the 4-line serial data bus. SCK I Serial Clock Input. 0–VCC V digital input. This pin provides the serial data clock function for the 4-line serial data bus. Data is clocked into the Si4463/62/61 on positive edge SDI I Serial Data Input. 0–VCC V digital input. This pin provides the serial data stream for the 4-line serial data bus. SDO O 0–VCC V Digital Output. Provides a serial readback function of the internal control registers.

T el: +86-755-82973805 F ax: +86-755-82973550 E -mail: sales@hoperf.com http:// www.hoperf.com RFM26W GPIO_3 I/O General Purpose Digital I/O. May be configured through the registers to perform various functions includ ing: Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery Detect, TRSW, AntDiversity control, etc. GPIO_2 I/O General Purpose Digital I/O. May be configured through the registers to perform various functions includ ing: Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery Detect, TRSW, AntDiversity control, etc. GPIO_1 I/O General Purpose Digital I/O. May be configured through the registers to perform various functions includ- ing: Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery Detect, TRSW, AntDiversity control, etc. GPIO_0 I/O General Purpose Digital I/O. May be configured through the registers to perform various functions includ- ing: Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery Detect, TRSW, AntDiversity control, etc. TX-ANT I Tx Atenna select input pin ,when RFM24 is in Tx state,the pin should be low,and RX-ANT should be high. RX-ANT I Rx Atenna select input pin ,when RFM24 is in Rx state,the pin should be low,and TX-ANT should be high. ANT ANT RF signal output/input.

T el: +86-755-82973805 F ax: +86-755-82973550 E -mail: sales@hoperf.com http:// www.hoperf.com RFM26W 11. Mechanical Dimension:RFM26W SMD PACKAGE(S2) I

T el: +86-755-82973805 F ax: +86-755-82973550 E -mail: sales@hoperf.com http:// www.hoperf.com RFM26W 12. Ordering Information Part Number=module type—operation band—package type RFM26W—433—S2 module type operation band Package example：1，RFM26W module at 433MHz band, SMD : RFM26W-433-S2 HOPE MICROELECTRONICS CO.,LTD Add: 2/F, Building 3, Pingshan Private Enterprise Science and Technology Park, Lishan Road, XiLi Town, Nanshan District, Shenzhen, Guangdong, China Tel: 86-755-82973805 Fax: 86-755-82973550 Email: sales@hoperf.com Website: http://www.hoperf.com http://www.hoperf.cn This document may contain preliminary information and is subject to change by Hope Microelectronics without notice. Hope Microelectronics assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of Hope Microelectronics or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in the direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MECHANTABILITY OR FITNESS FOR A ARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT. ©2006, HOPE MICROELECTRONICS CO.,LTD. All rights reserved.