RFM23BP

RFM23BP ETC2 | Alldatasheet

Document overview

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Technical content

Features

V2.0 „ Frequency Range z 433/868/915MHz ISM bands „ Sensitivity = –120 dBm „ Output power range z +30 dBm Max (RFM23BP) „ Low Power Consumption z 25 mA receive z 550 mA @ +30 dBm transmit „ Data Rate = 0.123 to 256 kbps „ FSK, GFSK, and OOK modulation „ Power Supply = 3.3 to 6 V „ Ultra low power shutdown mode „ Digital RSSI

Applications

„ Wake-up timer „ Auto-frequency calibration (AFC) „ Power-on-reset (POR) „ Antenna diversity and TR switch control „ Configurable packet handler „ Preamble detector „ TX and RX 64 byte FIFOs „ Low battery detector „ Temperature sensor and 8-bit ADC „ –40 to +85 °C temperature range „ Integrated voltage regulators „ Frequency hopping capability „ On-chip crystal tuning „ 16-PIN SMD package „ Low cost „ Remote control „ Home security & alarm „ Telemetry „ Personal data logging „ Toy control „ Tire pressure monitoring „ Wireless PC peripherals

Description

„ Remote meter reading „ Remote keyless entry „ Home automation „ Industrial control „ Sensor networks „ Health monitors „ Tag readers HopeRF's RFM23BP are highly integrated, low cost,433/868/915MHZ wireless ISM transceivers module. The low receive sensitivity (–120dBm) coupled with industry leading +30dBm output power ensures extended range and improved link performance. Built-in antenna diversity and support for frequency hopping can be us ed to further extend range and enhance performance. Additional system features such as an automatic wake-up timer, low battery detector, 64 byte TX/RX FIFOs, automatic packet handling, and preamble detection reduce overall current consum ption and allow the use of lower-cost system MCUs. An integrated temperatur e sensor, general purpose ADC, power- on-reset (POR), and GPIOs further reduce overall system cost and size. The RFM23BP digital receive archit ecture features a high-performance ADC and DSP based modem which performs dem odulation, filtering, and packet handling for increased flexibility and performance. The direct digital transmit modulation and automatic PA power rampin g ensure precise transmit modulation and reduced spectral spreading ensuring compliance with global regulations including FCC, ETSI. An easy-to-use calculator is provided to quickly configure the radio settings, simplifying customer's system design and reducing time to market. RFM23BP

Tel: +86-755-82973805 Fax: +86-755-82973550 E-ma il: sales@hoperf.com http://www.hoperf.com

Tel: +86-755-82973805 Fax: +86-755-82973550 E-ma il: sales@hoperf.com http://www.hoperf.com

1. Electrical Specifications

Table 1. DC Characteristics

Table 2. Synthesizer AC Electrical Characteristics XOSC running to any frequency.

Table 3. Receiver AC Electrical Characteristics Desired Ref Signal 3 dB above sensitivity. Image Rejection ImREJ Rejection at the image frequency.

Table 4. Transmitter AC Electrical Characteristics

Table 5. Auxiliary Block Specifications

15 MHz, 10 MHz, 4 MHz,

3 MHz, 2 MHz, 1 MHz, or

30 MHz XTAL Start-Up time t30M — 600 — µs

30 MHz XTAL Cap

Table 6. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ) Table 7. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2)

Table 8. Absolute Maximum Ratings matching network design will influence TX VRF-peak on TX output pin. Caution: ESD sensitive device.

Tel: +86-755-82973805 Fax: +86-755-82973550 E- mail: sales@hoperf.com http://www.hoperf.com 11 RFM23BP 2. Functional Description HopeRF's RFM23BP are highly integrated,low cost,433/868/915MHz wireless ISM transceivers module . The wide operating voltage range of 3.3–6V and low current consumption makes theRFM23BP an ideal solution for battery powered applications. The RFM23BP operates as a time division duplexing (TDD) transceiver where the device alternately transmits and receives data packets. The device uses a single-conversion mixer to downconvert the 2-level FSK/GFSK/OOK modulated receive signal to a low IF frequency. Following a programmable gain amplifier (PGA) the signal is converted to the digital domain by a high performance ΔΣ ADC allowing filtering, demodulation, slicing, and packet handling to be performed in the built-in DSP increasing t he receiver’s performance and flexibility versus analog based architectures. The demodulated signal is then output to the system MCU through a programmable GPIO or via the standard SPI bus by reading the 64-byte RX FIFO. A single high precision local oscillator (LO) is used for both transmit and receive modes since the transmitter and receiver do not operate at the same time. The LO is generated by an integrated VCO and ΔΣ Fractional-N PLL synthesizer. The synthesizer is designed to support configurable data rates, output frequency and frequency deviation at 433MHz,868MHz,915MHz band. The transmit FSK data is modulated directly into the ΔΣ data stream and can be shaped by a Gaussian low-pass filter to reduce unwanted spectral content. The RFM23BP PA output power can be configured between +10 and +30 dBm , . The RFM23BP supports frequency hopping, TX/RX switch control, and antenna diversity switch control to extend the link range and improve performance The RFM23BP is designed to work with a microcontroller to create a very low cost system as shown Figure 1. Voltage regula tors are integrated on-chip which allows for a wide operating supply voltage range from +3.3to +6 V. A standard 4-pin SPI bus is used to communicate with an external microcontroller. Three configurable general purpose I/Os are available. A complete list of the available GPIO functions is shown in "8. Auxiliary Functions"and includes microcontroller clock output, Antenna Diversity, POR, and various interrupts.

2.1. Operating Modes The RFM23BP provides several operating modes whic h can be used to optimize the power consumption for a given application. Depending upon the system communication protocol, an optimal trade-off between the radio wake time and power consumption can be achieved. Table 9 summarizes the operating modes of the RFM23BP. In general, any given operating mode may be classified as an active mode or a power saving mode. The table indicates which block(s) are enabled (active) in each corresponding mode. With the exception of the SHUTDOWN mode, all can be dynamically selected by sending the appropriate commands over the SPI. An “X” in any cell means that, in the given mode of operation, that block can be independently programmed to be either ON or OFF, without noticeably impacting the current consumption. The SPI circuit block includes the SPI interface hardware and the device register space. The 32 kHz OSC block includes the 32.768 kHz RC oscillator or 32. 768 kHz crystal oscillator and wake-up timer. AUX (Auxiliary Blocks) includes the temperature sensor, general purpose ADC, and low-battery detector. Table 9. Operating Modes

contents

retained) ON X X ON ON OFF ON 18.5 mA *Note: Using RFM23BP at +30 dBm using recommended reference design. Tel: +86-755-82973805 Fax: +86-755-82973550 E-ma il: sales@hoperf.com http://www.hoperf.com

The RFM23BP communicates with the host MCU over a standard 3-wire SPI interface: SCLK, SDI, and nSEL. SCLK rate is flexible with a maximum rate of 10 MHz. Figure 3. SPI Timing Table 10. Serial Interface Timing Parameters read from the selected regi ster will be available on the SDO output pin. The READ func tion is shown in Figure 4. last data bit clocked out (D0). When nSEL goes high the SDO output pin will be pulled high by internal pullup.

Tel: +86-755-82973805 Fax: +86-755-82973550 E- mail: sales@hoperf.com http://www.hoperf.com 17 RFM23BP 3.2.1. SHUTDOWN State The SHUTDOWN state is the lowest current consumption st ate of the device with nominally less than 15 nA of current consumption. The shutdown state may be en tered by driving the SDN pin high. The SDN pin should be held low in all states except the SHUTDOWN state. In the SHUTDOWN st ate, the contents of the registers are lost and there is no SPI access. When the chip is connected to the power supply, a POR will be initiated after the falling edge of SDN. 3.2.2. IDLE State There are five different modes in the IDLE state which may be selected by "Register 07h. Operating Mode and Function Control 1". All modes have a tradeoff between current consumption and response time to TX/RX mode. This tradeoff is shown in Table 11. After the POR event, SWRESET, or exiting from the SHUTDOWN state the chip will default to the IDLE-READY mode. After a POR event the interrupt registers must be read to properly enter the SLEEP , SENSOR, or STANDBY mode and to control the 32 kHz clock correctly. 3.2.2.1. STANDBY Mode STANDBY mode has the lowest current consumption of th e five IDLE states with only the LPLDO enabled to maintain the register values. In this mode the registers can be accessed in both read and write mode. The STANDBY mode can be entered by writing 0h to "Register 07h. Operating Mode and Function Control 1". If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current consumption. Additionally, the ADC should not be selected as an input to the GPIO in this mode as it will cause excess current consumption. 3.2.2.2. SLEEP Mode In SLEEP mode the LPLDO is enabled along with the Wake-Up-Timer, which can be used to accurately wake-up the radio at specified intervals. See "8.6. Wa ke-Up Timer and 32 kHz Clock Source for more information on the Wake -Up-Timer. SLEEP mode is entered by setting enwt = 1 (40h) in "Register 07h. Operating Mode and Function Control 1". If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current consumption. Also, the ADC should not be selected as an input to the GPIO in this mode as it will cause excess current consumption. 3.2.2.3. SENSOR Mode In SENSOR mode either the Low Battery Detector, Temperature Sensor, or both may be enabled in addition to the LPLDO and Wake-Up-Timer. The Low Battery Detector can be enabled by setting enlbd = 1 in "Register 07h. Detector" for more information on these features. If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current consumption. 3.2.2.4. READY Mode READY Mode is designed to give a fast transition time to TX mode with reasonable current consumption. In this mode the Crystal oscillator remains enabled reducing the time required to switch to TX or RX mode by eliminating the crystal start-up time. READY mode is entered by setting xton = 1 in "Register 07h. Operating Mode and Function Control 1". To achieve the lowest current cons umption state the crystal oscillator buffer should be disabled in “Register 62h. Crystal Oscillator Control and Test.” To exit READY mode, bufovr (bit 1) of this register must be set back to 0. 3.2.2.5. TUNE Mode In TUNE mode the PLL remains enabled in addition to the other blocks enabled in the IDLE modes. This will give the fastest response to TX mode as the PLL will remain lo cked but it results in the highest current consumption. This mode of operation is designed for frequency h opping spread spectrum system s (FHSS). TUNE mode is entered by setting pllon = 1 in "Register 07h. Operating Mo de and Function Control 1". It is not necessary to set xton to 1 for this mode, the internal state machine automatically enables the crystal oscillator.

Tel: +86-755-82973805 Fax: +86-755-82973550 E-ma il: sales@hoperf.com http://www.hoperf.com RFM23BP 3.2.3. TX State The TX state may be entered from any of the IDLE modes when the txon bit is set to 1 in "Register 07h. Operating Mode and Function Control 1". A built-in sequencer takes ca re of all the actions required to transition between states from enabling the crystal oscillator to ramping up the PA. The following sequence of events will occur automatically when going from STANDBY mode to TX mode by setting the txon bit. 1. Enable the main digital LDO and the Analog LDOs. 2. Start up crystal oscillator and wait until ready (controlled byan internal timer). 3. Enable PLL. 4. Calibrate VCO (this action is skipped when the vcocal bit is “0”, default value is “1”). 5. Wait until PLL settles to required transmit frequency (controlled by an internal timer). 6. Activate power amplifier and wait until power ramping is completed (controlled by an internal timer). 7. Transmit packet. Steps in this sequence may be eliminated depending on which IDLE mode the chip is configured to prior to setting the txon bit. By default, the VCO and PLL are calibrated every time the PLL is enabled. 3.2.4. RX State The RX state may be entered from any of the IDLE modes when the rxon bit is set to 1 in "Register 07h. Operating Mode and Function Control 1". A built-in sequencer takes care of all the actions required to transition from one of the IDLE modes to the RX state. The following sequence of events will occur automatically to get the chip into RX mode when going from STANDBY mode to RX mode by setting the rxon bit: 1. Enable the main digital LDO and the Analog LDOs. 2. Start up crystal oscillator and wait until ready (controlled by an internal timer). 3. Enable PLL. 4. Calibrate VCO (this action is skipped when the vcocal bit is “0”, default value is “1”). 5. Wait until PLL settles to required receive frequency (controlled by an internal timer). 6. Enable receive circuits: LNA, mixers, and ADC. 7. Enable receive mode in the digital modem. Depending on the configuration of the radio all or some of the following functions will be performed automatically by the digital modem: AGC, AFC (optional), update status registers, bit synchronization, packet handling (optional) including sync word, header check, and CRC. 3.2.5. Device Status Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

02 R Device Status ffovfl ffunfl rxffem headerr freqerr cps[1] cps[0] —

The operational status of the chip can be read from "Register 02h. Device Status".

Tel: +86-755-82973805 Fax: +86-755-82973550 E- mail: sales@hoperf.com http://www.hoperf.com 19 RFM23BP 3.3. Interrupts The RFM23BP is capable of generating an interrupt signal when certain events occur. The chip notifies the microcontroller that an interrupt event has occurred by setting the nIRQ output pin LOW = 0. This interrupt signal will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits) shown below occur. The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Register(s) (Registers 03h–04h) containing the active Interrupt Status bit. The nIRQ output signal will then be reset until the next change in status is detected. The interrupts must be enabled by the corresponding enable bit in the Interrupt Enable Registers (Registers 05h–06h). All enabled interrupt bits will be cleared when the microcontroller reads the interrupt status register. If the interrupt is not enabled when the event occurs it will not trigger the nIRQ pin, but the status may still be read at anytime in the Interrupt Status registers. Add R/W Function/Descript ion D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

03 R Interrupt Status 1 ifferr itxffafull itxffaem irxffafull iext ipksent ipkvalid icrcerror —

04 R Interrupt Status 2 iswdet ipreaval ipreainval irssi iwut ilbd ichiprdy ipor —

05 R/W Interrupt Enable 1 enfferr entxffafull entxffaem enrxffafull enext enpksent enpkvalid encrcerror 00h

06 R/W Interrupt Enable 2 enswdet enpreaval enpreainval enrssi enwut enlbd enchiprdy enpor 01h

3.5. Frequency Control For calculating the necessary frequency register settings it is recommended that customers use the HOPERF Register Calculator worksheet (in Microsoft Excel) available on the product website. These methods offer a simple method to quickly determi ne the correct settings based on the application requirements. The following information can be used to calculated these values manually. 3.5.1. Frequency Programming In order to receive or transmit an RF signal, the desired channel frequency, fcarrier, must be programmed into the RFM23BP. The carrier frequency is generated by a Fractional-N Synthesizer, using 10 MHz both as the reference frequency and the clock of the (3 rd order) ΔΣ modulator. This modulator uses modulo 64000 accumulators. This design was made to obtain the desired frequency resolution of the synthesizer. The overall division ratio of the feedback loop consist of an integer part (N) and a fractional part (F).In a generic sense, the output frequency of the synthesizer is as follows: fOUT = 10MHz × ( N + F ) The fractional part (F) is determined by three differ ent values, Carrier Frequency (fc[15:0]), Frequency Offset (fo[8:0]), and Frequency Deviation (fd[7:0]). Due to the fine resolution and high loop bandwidth of the synthesizer, FSK modulation is applied inside the loop and is done by varying F according to the incoming data; this is discussed further in "3.5.4. Frequency Deviation" Al so, a fixed offset can be added to fine-tune the carrier frequency and counteract crystal tolerance errors. For simplicity assume that only the fc[15:0] register will determine the fractional component. The equation for selection of the carrier frequency is shown below: fcarrier = 10MHz × (hbsel + 1) × ( N + F ) fTX 64000 Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

73 R/W Frequency Offset 1 fo[7] fo[6] fo[5] fo[4] fo[3] fo[2] fo[1] fo[0] 00h

74 R/W Frequency Offset 2 fo[9] fo[8] 00h

75 R/W Frequency Band Select sbsel hbsel fb[4] fb[3] fb[2] fb[1] fb[0] 35h

76 R/W Nominal Carrier

fc[15] fc[14] fc[13] fc[12] fc[11] fc[10] fc[9] fc[8] BBh

77 R/W Nominal Carrier

fc[7] fc[6] fc[5] fc[4] fc[3] fc[2] fc[1] fc[0] 80h The integer part (N) is determined by fb[4:0]. Additionally, the output frequency can be halved by connecting a ÷2 divider to the output. This divider is not inside the loop and is controlled by the hbsel bit in "Register 75h. Frequency Band Select." This effectively partitions the entire 240–960 MHz frequency range into two separate bands: High Band (HB) for hbsel = 1, and Low Band (LB) for hbsel = 0. The valid range of fb[4:0] is from 0 to 23. If a higher value is written into the register, it will default to a value of 23. The integer part has a fixed offset of 24 added to it as shown in the formula above. Table 12 demonstrates the selection of fb[4:0] for the corresponding frequency band. After selection of the fb (N) the fractional component may be solved with the following equation: ⎛ f ⎞ ⎝ 10MHz * (hbsel + 1) ⎠ fb and fc are the actual numbers stored in the corresponding registers. Tel: +86-755-82973805 Fax: +86-755-82973550 E-ma il: sales@hoperf.com http://www.hoperf.com

Table 12. Frequency Band Selection

3.5.2. Easy Frequency Programming for FHSS While Registers 73h–77h may be used to program the carrier frequency of the RFM23BP, it is often easier to think in terms of “channels” or “channel numbers” rather than an absolute frequency value in Hz. Also, there may be some timing-critical applications (such as for Frequency Hopping Systems) in which it is desirable to change frequency by programming a single register. Once the channel step size is set, the frequency may be changed by a single register corresponding to the channel number. A nominal frequency is first set using Registers 73h–77h, as described above. Registers 79h and 7Ah are then used to set a channel step size and channel number, relative to the nominal setting. The Frequency Hopping Step Size (fhs[7:0]) is set in increments of 10 kHz with a maximum channel step size of 2.56 MHz. The Frequency Hopping Channel Select Register then selects channels based on multiples of the step size. Fcarrier = Fnom + fhs[7 : 0]× ( fhch[7 : 0]×10kHz) For example, if the nominal frequency is set to 900 MHz using Registers 73h–77h, the channel step size is set to 1 MHz using "Register 7Ah. Frequency Hopping Step Size," and "Register 79h. Frequency Hopping Channel Select" is set to 5d, the resulting carrier frequency would be 905 MHz. Once the nominal frequency and channel step size are programmed in the registers, it is only necessary to program the fhch[7:0] register in order to change the frequency. Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

79 R/W Frequency Hopping Channel

fhch[7] fhch[6] fhch[5] fhch[4] fhch[3] fhch[2] fhch[1] fhch[0] 00h 7A R/W Frequency Hopping Step Size fhs[7] fhs[6] fhs[5] fhs[4] fhs[3] fhs[2] fhs[1] fhs[0] 00h 3.5.3. Automatic State Transition for Frequency Change If registers 79h or 7Ah are changed in either TX or mode, the state machine will automatically transition the chip back to TUNE, change the frequency, and automatically go back to either TX or RX. This feature is useful to reduce the number of SPI commands required in a Frequency Hopp ing System. This in turn reduces microcontroller activity, reducing current consumption. The exception to this is during TX FIFO mode. If a frequency change is initiated during a TX packet, then the part will complete the current TX packet and will only change the frequency for subsequent packets. 3.5.4. Frequency Deviation The peak frequency deviation is configurable from ±0.625 to ±320 kHz. The Frequency Deviation ( Δf) is controlled by the Frequency Deviation Register (fd), address 71 and 72h, and is independent of the carrier frequency setting. When enabled, regardless of the setting of the hbsel bit (high band or low band), the resolution of the frequency deviation will remain in increments of 625 Hz. When using frequency modulation the carrier frequency will deviate from the nominal center channel carrier frequency by ±Δf: Δf = fd[8 : 0]× 625Hz fd[8 : 0] = Δf 625Hz Δf = peak deviation Tel: +86-755-82973805 Fax: +86-755-82973550 E-ma il: sales@hoperf.com http://www.hoperf.com

Figure 10. Frequency Deviation see "4.1. Modulation Type" for further details. Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

71 R/W Modulation Mode Control 2 trclk[1] trclk[0] dtmod[1] dtmod[0] eninv fd[8] modtyp[1] modtyp[0] 00h

72 R/W Frequency Deviation fd[7] fd[6] fd[5] fd[4] fd[3] fd[2] fd[1] fd[0] 20h

register should be set to 360h.

73 R/W Frequency Offset fo[7] fo[6] fo[5] fo[4] fo[3] fo[2] fo[1] fo[0] 00h

74 R/W Frequency Offset fo[9] fo[8] 00h

trade-off of receiver sensitivity (at 1% PER) versus carrier offset and the impact of AFC are illustrated in Figure 11. Figure 11. Sensitivity at 1% PER vs. Carrier Frequency Offset

Tel: +86-755-82973805 Fax: +86-755-82973550 E-ma il: sales@hoperf.com http://www.hoperf.com RFM23BP When AFC is enabled, the preamble length needs to be lo ng enough to settle the AFC. In general, one byte of preamble is sufficient to settle the AFC. Disabling the AFC allows the preamble to be shortened from 40 bits to 32 bits. Note that with the AFC disabled, the preamble length must still be long enough to settle the receiver and to detect the preamble (see "6.7. Preamble Length" . The AFC corrects the detected frequency offset by changing the frequency of the Fracti onal-N PLL. When the preamble is det ected, the AFC will freeze for the remainder of the packet. In multi-packet mode the AFC is reset at the end of every packet and will re-acquire the frequency offset for the next packet. The AFC loop includes a bandwidth limiting mechanism improving the rejection of out of band signals. When the AFC loop is enabled, its pull-in-range is determined by the bandwidth limiter value (AFCLimiter) which is located in register 2Ah. AFC_pull_in_range = ±AFCLimiter[7:0] x (hbsel+1) x 625 Hz The AFC Limiter register is an unsigned register and its value can be obtained from the HOPERF Register Calculator spreadsheet. The amount of error correction feedback to the Fractional-N PLL before the preamble is detected is controlled from afcgearh[2:0]. The default value 000 relates to a feedback of 100% from the measured frequency error and is advised for most applications. Every bit added will half the feedback but will require a longer preamble to settle. The AFC operates as follows. The frequency error of the incoming signal is measured over a period of two bit times, after which it corrects the local oscillator via the Fractional-N PLL. After this correction, some time is allowed to settle the Fractional-N PLL to the new frequency before the next frequency error is measured. The duration of the AFC cycle before the preamble is detected can be programmed with shwait[2:0]. It is advised to use the default value 001, which sets the AFC cycle to 4 bit times (2 for measurement and 2 for settling). If shwait[2:0] is programmed to 3'b000, there is no AFC correction output. It is advised to use the default value 001, which sets the AFC cycle to 4 bit times (2 for measurement and 2 for settling). The AFC correction value may be read from register 2Bh. The value read can be converted to kHz with the following formula: AFC Correction = 156.25Hz x (hbsel +1) x afc_corr[7: 0] Frequency Correction RX TX AFC disabled Freq Offset Register Freq Offset Register AFC enabled AFC Freq Offset Register

Tel: +86-755-82973805 Fax: +86-755-82973550 E- mail: sales@hoperf.com http://www.hoperf.com 27 DR_TX (kbps) = RFM23BP 3.5.7. TX Data Rate Generator The data rate is configurable between 0.123–256 kbps. For data rates below 30 kbps the ”txdtrtscale” bit in register 70h should be set to 1. When higher data rates are used this bit should be set to 0. The TX date rate is determined by the following formula in kbps: 216 + 5 × t xd tr ts cale txdr[15:0] DR_TX(kbps) × 2 16 + 5 × t xd tr ts cale

1 MHz

For data rates higher than 100 kbps, Register 58h should be changed from its default of 80h to C0h. Non-optimal modulation and increased eye closure will result if this setting is not made for data rates higher than 100 kbps. The txdr register is only applicable to TX mode and does not need to be programmed for RX mode. The RX bandwidth which is partly determined from the data rate is programmed separately. Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def. 6E R/W TX Data Rate 1 txdr[15] txdr[14] txdr[13] txdr[12] txdr[11] txdr[10] txdr[9] txdr[8] 0Ah 6F R/W TX Data Rate 0 txdr[7] txdr[6] txdr[5] txdr[4] txdr[3] txdr[2] txdr[1] txdr[0] 3Dh

FSK and GFSK for a Data Rate of 64 kbps. The time domain plots demonstrate the effects of the Gaussian filtering. obtain an unmodulated carrier signal by setting modtyp[1:0] = 00.

00 Unmodulated Carrier

01 OOK

10 FSK

11 GFSK (enable TX Data CLK when direct mode is used)

Figure 12. FSK vs GFSK Spectrums

Tel: +86-755-82973805 Fax: +86-755-82973550 E- mail: sales@hoperf.com http://www.hoperf.com 29 RFM23BP 4.2. Modulation Data Source The RFM23BP may be configured to obtain its modulation data from one of three different sources: FIFO mode, Direct Mode, and from a PN9 mode. In Direct Mode, the TX modulation data may be obtained from several different input pins. These options are set through the dtm od[1:0] field in "Register 71h. Modulation Mode Control 2". Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

71 R/W Modulation Mode

trclk[1] trclk[0] dtmod[1] dtmod[0] eninv fd[8] modtyp[1] modtyp[0] 00h dtmod[1:0] Data Source

00 Direct Mode using TX/RX Data via GPIO pin (GPIO configuration required)

01 Direct Mode using TX/RX Data via SDI pin (only when nSEL is high)

10 FIFO Mode

11 PN9 (internally generated)

4.2.1. FIFO Mode In FIFO mode, the transmit and receive data is stored in integrated FIFO register memory. The FIFOs are accessed via "Register 7Fh. FIFO Access," and are most efficiently accessed with burst read/write operation as discussed in "3.1. Serial Peripheral Interface (SPI)" . In TX mode, the data bytes stored in FIFO memory are "packaged" together with other fields and bytes of information to construct the final transmit packet structure. These other potential fields include the Preamble, Sync word, Header, CRC checksum, etc. The configuration of t he packet structure in TX mode is determined by the Automatic Packet Handler (if enabled), in conjunction with a variety of Packet Handler Registers (see Table 13). If the Automatic Packet Handler is disabled, the en tire desired packet structure should be loaded into FIFO memory; no other fields (such as Preamble or Sync word are automatically added to the bytes stored in FIFO memory). For further information on the configuration of the FIFOs for a specific application or packet size, see "6. Data Handling and Packet Handler" . In RX mode, only the bytes of the received packet structure that are considered to be "data bytes" are stored in FIFO memory. Which bytes of the received packet are considered "data bytes" is determined by the Automatic Packet Handler (if enabled), in conjunction with the Packet Handler Registers (see Table 13 ). If the Automatic Packet Handler is disabled, all bytes following the Sync word are considered data bytes and are stored in FIFO memory. Thus, even if Automatic Packet Handling operation is not desired, the preamble detection threshold and Sync word still need to be programmed so that the RX Modem knows when to start filling data into the FIFO. When the FIFO is being used in RX mode, all of the received data may still be observed directly (in real- time) by properly programming a GPIO pin as the RXDATA output pin; this can be quite useful during application development. When in FIFO mode, the chip will automatically exit the TX or RX State when either the ipksent or ipkvalid interrupt occurs. The chip will return to the IDLE mode state programmed in "Register 07h. Operating Mode and Function Control 1". For example, the chip may be placed into TX mode by setting the txon bit, but with the pllon bit additionally set. The chip will transmit all of the contents of the FIFO and the ipksent interrupt will occur. When this interrupt event occurs, the chip will clear the txon bit and return to TUNE mode, as indicated by the set state of the pllon bit. If no other bits are additionally set in register 07h (besides txon initially), then the chip will return to the STANDBY state. In RX mode, the rxon bit will be cleared if ipkvalid occurs and the rxmpk bit (RX Multi-Packet bit, SPI Register 08h bit [4]) is not set. When the rxmpk bit is set, the part will not exit the RX state after successfully receiving a packet, but will remain in RX mode. The microcontroller will need to decide on the appropriate subsequent action, depending upon information such as an interrupt generated by CRC, packet valid, or preamble detect.

Tel: +86-755-82973805 Fax: +86-755-82973550 E-ma il: sales@hoperf.com http://www.hoperf.com30 RFM23BP 4.2.2. Direct Mode For legacy systems that perform packet handling within an MCU or other baseband chip, it may not be desirable to use the FIFO. For this scenario, a Direct Mode is provided which bypasses the FIFOs entirely. In TX direct mode, the TX modulation data is applied to an input pin of the chip and processed in "real time" (i.e., not stored in a register for transmission at a later time). A variety of pins may be configured for use as the TX Data input function. Furthermore, an additional pin may be required for a TX Clock output function if GFSK modulation is desired (only the TX Data input pin is required for FSK). Two options for the source of the TX Data are available in the dtmod[1:0] field, and various configurations for the source of the TX Data Clock may be selected through the trclk[1:0] field. trclk[1:0] TX/RX Data Clock Configuration

00 No TX Clock (only for FSK)

01 TX/RX Data Clock is available via GPIO (GPIO needs programming accordingly as well)

10 TX/RX Data Clock is available via SDO pin (only when nSEL is high)

11 TX/RX Data Clock is available via the nIRQ pin

The eninv bit in SPI Register 71h will invert the TX Data; this is most lik ely useful for dia gnostic and testing purposes. In RX direct mode, the RX Data and RX Clock can be prog rammed for direct (real-time) output to GPIO pins. The microcontroller may then process the RX data without using the FIFO or packet handler functions of the RFIC. In RX direct mode, the chip must still acquire bit timi ng during the Preamble, and thus the preamble detection threshold (SPI Register 35h) must still be programmed. Once the preamble is detected, certain bit timing functions within the RX Modem change their operation for optimized pe rformance over the remainder of the packet. It is not required that a Sync word be present in the packet in RX Direct mode; however, if the Sync word is absent then the skipsyn bit in SPI Register 33h must be set, or else t he bit timing and tracking function within the RX Modem will not be configured for optimum performance. 4.2.2.1. Direct Synchronous Mode In TX direct mode, the chip may be configured for synchronous or asynchronous modes of modulation. In direct synchronous mode, the RFIC is configured to provide a TX Clock signal as an output to the external device that is providing the TX Data stream. This TX Clock signal is a square wave with a frequency equal to the programmed data rate. The external modulation source (e.g., MCU) must accept this TX Clock sign al as an input and respond by providing one bit of TX Data back to the RFIC, synchr onous with one edge of the TX Clock signal. In this fashion, the rate of the TX Data input stream from the external source is controlled by the programmed data rate of the RFIC; no TX Data bits are made available at the in put of the RFIC until requeste d by another cycle of the TX Clock signal. The TX Data bits supplied by the external sour ce are transmitted directly in real-time (i.e., not stored internally for later transmission). All modulation types (FSK/GFSK/OOK) are valid in TX dire ct synchronous mode. As will be discussed in the next section, there are limits on modulation types in TX direct asynchronous mode. 4.2.2.2. Direct Asynchronous Mode In TX direct asynchronous mode, the RFIC no longer controls the data rate of the TX Data input stream. Instead, the data rate is controlled only by the external TX Data source; the RFIC simply accepts the data applied to its TX Data input pin, at whatever rate it is supplied. This means that there is no longer a need for a TX Clock output signal from the RFIC, as there is no synchronous "handshaking" between the RFIC and the external data source. The TX Data bits supplied by the external source are trans mitted directly in real-time (i.e., not stored internally for later transmission). It is not necessary to program the data rate parameter when operating in TX direct asynchronous mode. The chip still internally samples the incoming TX Data stream to determine when edge transitions occur; however, rather than sampling the data at a pre-programmed data rate, the chip now internally samples the incoming TX Data stream at its maximum possible oversampling rate. This allows the chip to accurately determine the timing of the bit edge transitions without prior knowledge of the data rate. (Of course, it is still necessary to program the desired peak frequency deviation.)

Figure 15. Microcontroller Connections purpose of this mode is for use as a test mode to observe the modulated spectrum without having to provide data.

1. Internal Functional Blocks This section provides an overview some of the key blocks of the internal radio architecture. 5.1. RX LNA The LNA provides gain with a noise figure low enough to suppress the noise of t he following stages. The LNA has one step of gain control which is controlled by the analog gain control (AGC) algorithm. The AGC algorithm adjusts the gain of the LNA and PGA so the receiver can handle signal levels fr om om sensitivity to +5 dBm with optimal performance. For the RFM23BP, The direct tie is used, The lna_sw bit in “Register 6Dh. TX Power” must be set. 5.2. RX I-Q Mixer The output of the LNA is fed internally to the input of the receive mixer. The receive mixer is implemented as an I-Q mixer that provides both I and Q channel outputs to the programmable gain amplifier. The mixer consists of two double-balanced mixers whose RF inputs are driven in parallel, local oscillator (LO) inputs are driven in quadrature, and separate I and Q Intermediate F requency (IF) outputs drive the programmable gain amplifier. The receive LO signal is supplied by an integrated VCO and PLL synthesizer operating between 240–960 MHz. The necessary quadrature LO signals are derived from the divider at the VCO output. 5.3. Programmable Gain Amplifier The programmable gain amplifier (PGA) provides the necessary gain to boost the signal level into the dynamic range of the ADC. The PGA must also have enough gain switching to allow for large input signals to ensure a linear RSSI range up to –20 dBm. The PGA has steps of 3 dB which are controlled by the AGC algorithm in the digital modem. 5.4. ADC The amplified IQ IF signals are digitized using an Analog-to-Digital Converter (ADC), which allows for low current consumption and high dynamic range. The bandpass response of the ADC provides exceptional rejection of out of band blockers. 5.5. Digital Modem Using high-performance ADCs allows channel filtering, image rejection, and demodulation to be performed in the digital domain, resulting in reduced area while increasi ng flexibility. The digital modem performs the following functions: „ Channel selection filter „ TX modulation „ RX demodulation „ AGC „ Preamble detector „ Invalid preamble detector „ Radio signal strength indicator (RSSI) „ Automatic frequency compensation (AFC) „ Packet handling including EZMAC® features „ Cyclic redundancy check (CRC) The digital channel filter and demodulator are optimized for ultra low power consumption and are highly configurable. Supported modulation types are GFSK, FSK, and OOK. The channel filter can be configured to support bandwidths ranging from 620 kHz down to 2.6 kHz. A large variety of data rates are supported ranging from 0.123 up to 256 kbps. The AGC algorithm is implemented digitally using an advanced control loop optimized for fast response time. Tel: +86-755-82973805 Fax: +86-755-82973550 E-ma il: sales@hoperf.com http://www.hoperf.com

detector is only enabled when a valid preamble is detected, significantly reducing the probability of false detection. measurements for clear channel assessment (CCA), carrier sense (CS), and listen before talk (LBT) functionality. frequency control (AFC) in receive mode. group, and point-to-point communication. reduce the load on the system microcontroller allowing for a simpler and cheaper microcontroller. (BT) is 0.5 for all programmed data rates, but it may not be adjusted to other values. through the fractional divider which results in very precise accuracy and control over the transmit deviation. can be programmed between ±1–320 kHz. These parameters may be adjusted via registers as shown in "3.5. Figure 16. PLL Synthesizer Block Diagram

the output from the Δ-Σ modulator. The tuning resolution is sufficient to tune to the commanded frequency with a maximum accuracy of 312.5 Hz anywhere in the range between 240–960 MHz. 5.6.1. VCO The output of the VCO is automatically divided down to the correct output frequency depending on the hbsel and fb[4:0] fields in "Register 75h. Frequency Band Select." In receive mode, the LO frequency is automatically shifted downwards by the IF frequency of 937.5 kHz, allowing transmit and receive operation on the same frequency. The VCO integrates the resonator inductor and tuning varactor, so no external VCO components are required. The VCO uses a capacitance bank to cover the wide frequency range specified. The capacitance bank will automatically be calibrated every time the synthesizer is enabled. In certain fast hopping applications this might not be desirable so the VCO calibration may be skipped by setting the appropriate register. 5.7. Power Amplifier The RFM23BP contains an internal integrated power amplifier(PA) capable of transmitting at output levels between – 1 and +30 dBm. The PA design is single-ended and is implemented as a two stage class fcc amplifier with a high efficiency when transmitting at maximum power. The PA efficiency can only be optimized at one power level. Changing the output power by adjusting txpow[2:0] will scale both the output power and current but the efficiency will not remain constant. The PA output is ramped up and down to prevent unwanted spectral splatter. For the RFM23BP, The direct tie is used, The lna_sw bit in “Register 6Dh. TX Power” must be set. 5.7.1. Output Power Selection The output power is configurable in 3 dB steps with the tx pow[2:0] field in "Register 6Dh. TX Power." Extra output power can allow the use of a cheaper smaller antenna, greatly reducing the overall BOM cost. The higher power setting of the chip achieves maximum possible range, bu t of course comes at the cost of higher TX current consumption. However, depending on the duty cycle of the system, the effect on batte ry life may be insignificant. Contact HOPERF Support for help in evaluating this tradeoff. Add R/W Function/D escription D7 D6 D5 D4 D3 D2 D1 D0 POR Def. 6D R/W TX Power papeakval papeaken papeaklv[1] papeaklv[0] lna_sw txpow[2] txpow[1] txpow[0] 18h txpow[2:0] RFM23BP Output Power

000 TBD

001 TBD

010 TBD

011 TBD

100 TBD

Tel: +86-755-82973805 Fax: +86-755-82973550 E-ma il: sales@hoperf.com http://www.hoperf.com 35

Tel: +86-755-82973805 Fax: +86-755-82973550 E-ma il: sales@hoperf.com http://www.hoperf.com RFM23BP 5.8. Crystal Oscillator The RFM23BP includes an integrated 30 MHz crystal oscillator with a fast start-up time of less than 600 Es. A parallel resonant 30MHz crystal is used on the module. Th e design is differential with the required crystal load capacitance integrated on-chip to minimize the number of external components. The crystal load capacitance can be digitally programmed to accommodate crystals with various load capacitance requirements and to adjust the frequency of the crystal osc illator. The tuning of the crystal load capacitance is programmed through the xlc[6:0] field of "Register 09h. 30 MHz Crystal Os cillator Load Capacitance." The total internal capacitance is 12.5 pF and is adjustable in approximately 127 steps (97fF/step). The xtalshift bit provides a coarse shift in frequency but is not binary with xlc[6:0]. The crystal frequency adjustment can be used to compensa te for crystal production tolerances. Utilizing the on- chip temperature sensor and suitable control software, the temperature dependency of the crystal can be canceled. The typical value of the total on-chip capacitance Cint can be calculated as follows: Cint = 1.8 pF + 0.085 pF x xlc[6:0] + 3.7 pF x xtalshift Note that the coarse shift bit xtalshift is not binary with xlc[6:0]. The total load capacitance Cload seen by the crystal can be calculated by adding the sum of all external parasitic PCB capacitances Cext to Cint. If the maximum value of Cint (16.3 pF) is not sufficient, an exte rnal capacitor can be added for exact tuning. If AFC is disabled then the synthesizer frequency may be further adjusted by programming the Frequency Offset field fo[9:0]in "Register 73h. Frequency Offset 1" and "Register 74h. Frequency Offset 2", as discussed in "3.5. Frequency Control" . The crystal oscillator frequency is divided down internally and may be output to the microcontroller through one of the GPIO pins for use as the System Clock. In this fa shion, only one crystal oscillator is required for the entire system and the BOM cost is reduced. The available clock frequencies and GPIO configuration are discussed further in "8.2. Microcontroller Clock" . Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

09 R/W Crystal Oscillator Load

xtalshift xlc[6] xlc[5] xlc[4] xlc[3] xlc[2] xlc[1] xlc[0] 7Fh 5.9. Regulators There are a total of six regulators integrated onto the RF M23BPS . With the exception of the di gital regulator, all regulators are designed to operate with only internal decoupling. All regulators are designed to operate with an input supply voltage from +3.3 to +6V. A supply voltage should only be connected to the VDD pins.

1. Data Handling and Packet Handler

Two 64 byte FIFOs are integrated into the chip, one for RX and one for TX, as shown in Figure 17. "Register 7Fh. to address 7Fh will write da ta to the TX FIFO. A burst read from address 7Fh will read data from the RX FIFO. Figure 17. FIFO Thresholds

08 R/W Operating &

nIRQ pin. The microcontroller will then need to read the data from the RX FIFO. correctly in the Interrupt Status registers. When using the FIFOs, automatic packet handling may be enabled for TX mode, RX mode, or both. "Register 30h. lengths to accommodate different applications. The most common CRC polynominals are available for selection. Figure 18. Packet Structure An overview of the packet handler configuration registers is shown in Table 13.

Figure 22. Multiple Packets in RX with CRC or Header Error

Table 13. Packet Handler Registers Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

30 R/W Data Access Control enpacrx lsbfrst crcdonly skip2ph enpactx encrc crc[1] crc[0] 8Dh

31 R EzMAC status 0 rxcrc1 pksrch pkrx pkvalid crcerror pktx pksent —

32 R/W Header Control 1 bcen[3:0] hdch[3:0] 0Ch

33 R/W Header Control 2 skipsyn hdlen[2] hdlen[1] hdlen[0] fixpklen synclen[1] synclen[0] prealen[8] 22h

36 R/W Sync Word 3 sync[31] sync[30] sync[29] sync[28] sync[27] sync[26] sync[25] sync[24] 2Dh

37 R/W Sync Word 2 sync[23] sync[22] sync[21] sync[20] sync[19] sync[18] sync[17] sync[16] D4h

38 R/W Sync Word 1 sync[15] sync[14] sync[13] sync[12] sync[11] sync[10] sync[9] sync[8] 00h

39 R/W Sync Word 0 sync[7] sync[6] sync[5] sync[4] sync[3] sync[2] sync[1] sync[0] 00h

40 R/W Check Header 2 chhd[23] chhd[22] chhd[21] chhd[20] chhd[19] chhd[18] chhd[17] chhd[16] 00h

41 R/W Check Header 1 chhd[15] chhd[14] chhd[13] chhd[12] chhd[11] chhd[10] chhd[9] chhd[8] 00h

42 R/W Check Header 0 chhd[7] chhd[6] chhd[5] chhd[4] chhd[3] chhd[2] chhd[1] chhd[0] 00h

43 R/W Header Enable 3 hden[31] hden[30] hden[29] hden[28] hden[27] hden[26] hden[25] hden[24] FFh

44 R/W Header Enable 2 hden[23] hden[22] hden[21] hden[20] hden[19] hden[18] hden[17] hden[16] FFh

45 R/W Header Enable 1 hden[15] hden[14] hden[13] hden[12] hden[11] hden[10] hden[9] hden[8] FFh

46 R/W Header Enable 0 hden[7] hden[6] hden[5] hden[4] hden[3] hden[2] hden[1] hden[0] FFh

47 R Received Header 3 rxhd[31] rxhd[30] rxhd[29] rxhd[28] rxhd[27] rxhd[26] rxhd[25] rxhd[24] —

48 R Received Header 2 rxhd[23] rxhd[22] rxhd[21] rxhd[20] rxhd[19] rxhd[18] rxhd[17] rxhd[16] —

49 R Received Header 1 rxhd[15] rxhd[14] rxhd[13] rxhd[12] rxhd[11] rxhd[10] rxhd[9] rxhd[8] —

preamble detection threshold and preamble length for various modes. support for further details. Table 14. Minimum Receiver Settling Time be shortened when occasional packet errors are tolerable. „ synclen[1:0] = 00—Expected/Transmitted Synchronization Word (sync word) 3. „ synclen[1:0] = 01—Expected/Transmitted Synchronization Word 3 first, followed by sync word 2.

length plus four additional bits. Header 1, and Header 0 if enabled. Figure 25. Header packets that fit completely in the TX FIFO can be automatically retransmitted. depending on the amount of data in the TX FIFO.

1. RX Modem Configuration A Microsoft Excel (WDS) parameter calculator or Wireless Development Suite (WDS) calculator is provided to determine the proper settings for the modem. The calculator can be found on www.hoperf.com or on the CD provided with the demo kits. An application note is availabl e to describe how to use the calculator and to provide advanced descriptions of the modem settings and calculations. 7.1. Modem Settings for FSK and GFSK The modem performs channel selection and demodulation in the digital domain. The channel filter bandwidth is configurable from 2.6 to 620 kHz. The receiver data-rate, modulation index, and bandwidth are set via registers 1C–25h. The modulation index is equal to 2 times the peak deviation divided by the data rate (Rb). When Manchester coding is disabled, the required channel filter bandwidth is calculated as BW = 2Fd + Rb where Fd is the frequency deviation and Rb is the data rate. Tel: +86-755-82973805 Fax: +86-755-82973550 E-ma il: sales@hoperf.com http://www.hoperf.com

Figure 26. POR Glitch Parameters Table 15. POR Parameters

Tel: +86-755-82973805 Fax: +86-755-82973550 E- mail: sales@hoperf.com http://www.hoperf.com 47 RFM23BP 8.2. Microcontroller Clock The 30 MHz crystal oscillator frequency is divided down internally and may be output to the microcontroller through GPIO2. This feature is useful to lower BOM cost by using only one crystal in the system. The system clock frequency is selectable from one of 8 options, as sh own below. Except for the 32.768 kHz option, all other frequencies are derived by dividing the crystal oscillator frequency. The 32.768 kHz clock signal is derived from an internal RC oscillator or an external 32 kHz crystal. The default setting for GPIO2 is to output the microcontroller clock signal with a frequency of 1 MHz. Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def. 0A R/W Microcontroller Output Clock clkt[1] clkt[0] enlfc mclk[2] mclk[1] mclk[0] 06h mclk[2:0] Clock Frequency 000 30 MHz 001 15 MHz 010 10 MHz 011 4 MHz 100 3 MHz 101 2 MHz 110 1 MHz 111 32.768 kHz If the microcontroller clock option is being used there may be the need of a system clock for the microcontroller while the RFM23BP is in SLEEP mode. Since the crystal oscillator is disabled in SLEEP mode in order to save current, the low-power 32.768 kHz clock can be automatically switched to become the microcontroller clock. This feature is called enable low frequency clock and is enabled by the enlfc bit in “Register 0Ah. Microcontroller Output Clock." When enlfc = 1 and the chip is in SLEEP m ode then the 32.768 kHz clock will be provided to the microcontroller as the system clock, regardless of the setting of mclk[2:0]. For example, if mclk[2:0] = 000, 30 MHz will be provided through the GPIO output pin to the microcontroller as the system clock in all IDLE, TX, or RX states. When the chip enters SLEEP mode, the system clock will automatically switch to 32.768 kHz from the RC oscillator or 32.768 XTAL. Another available feature for the microcontroller clock is t he clock tail, clkt[1:0] in “Register 0Ah. Microcontroller Output Clock." If the low frequency clock feature is not enabled (enlfc = 0), then the system clock to the microcontroller is disabled in SLEEP mode. However, it may be useful to provide a few extra cycles for the microcontroller to complete its operation prior to the shutdo wn of the system clock signal. Setting the clkt[1:0] field will provide additional cycles of the system clock before it shuts off. clkt[1:0] Clock Tail 00 0 cycles 01 128 cycles 10 256 cycles 11 512 cycles If an interrupt is triggered, the microcontroller clock will remain enabled regardless of the selected mode. As soon as the interrupt is read the state machine will then move to the selected mode. The minimum current consumption will not be achieved until the interrupt is read. For in stance, if the chip is commanded to SLEEP mode but an interrupt has occurred the 30 MHz XTAL will not be disabled until the interrupt has been cleared.

configure the ADC operation. dependent offset voltage can be added using soffs[3:0] in register 10h. Figure 27. General Purpose ADC Architecture Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

10 R/W Sensor Offset soffs[3] soffs[2] soffs[1] soffs[0] 00h

11 R ADC Value adc[7] adc[6] adc[5] adc[4] adc[3] adc[2] adc[1] adc[0] —

sensor is configurable. Table 16 lists the settings for the different temperature ranges and performance.

1. Set the input for ADC to the temperature sensor, "Register 0Fh. ADC
2. Set the reference for ADC, "Register 0Fh. ADC Configuration"—adcref[1:0] = 00
3. Set the temperature range for ADC, "Register 12h. Temperature Sensor Calibration"—tsrange[1:0]
4. Set entsoffs = 1, "Register 12h. Temperature Sensor Calibration"
5. Trigger ADC reading, "Register 0Fh. ADC Configuration"—adcstart = 1
6. Read temperature value—Read contents of "Register 11h. ADC Value"

Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

12 R/W Temperature

Table 16. Temperature Sensor Range calibration is necessary. The temperature sensor may be calibrated by setting entsoffs = 1 in “Register 12h. ±3 °C absolute accuracy may be achieved. may be translated to a temperature reading by ADC8Value x ADC8 LSB + Lowest Temperature in Temp Range. For instance for a tsrange = 00, Temp = ADC8Value x 0.5 – 64.

Figure 28. Temperature Ranges using ADC8

Tel: +86-755-82973805 Fax: +86-755-82973550 E- mail: sales@hoperf.com http://www.hoperf.com 51 RFM23BP 8.5. Low Battery Detector A low battery detector (LBD) with digital read-out is integrated into the chip. A digital threshold may be programmed into the lbdt[4:0] field in "Register 1Ah. Low Battery Detector Threshold." When the digitized battery voltage reaches this threshold an interrupt will be generated on the nIRQ pin to the microcontroller. The microcontroller can confirm source of the interrupt by reading "Register 03h. Interrupt/Status 1" and “Register 04h. Interrupt/Status 2.” If the LBD is enabled while the chip is in SLEEP mode, it will automatically enable the RC oscillator which will periodically turn on the LBD circuit to measure the battery voltage. The battery voltage may also be read out through "Register 1Bh. Battery Voltage Level" at any time when the LBD is enabled. The low battery detect function is enabled by setting enlbd=1 in "Register 07h. Operating Mode and Function Control 1". Ad R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def. 1A R/W Low Battery Detector Threshold lbdt[4] lbdt[3] lbdt[2] lbdt[1] lbdt[0] 14h 1B R Battery Voltage Level 0 0 0 vbat[4] vbat[3] vbat[2] vbat[1] vbat[0] — The LBD output is digitized by a 5-bit ADC. When the LBD function is enabled (enlbd = 1 in "Register 07h. Operating Mode and Function Control 1") the battery voltage may be read at anytime by reading "Register 1Bh. Battery Voltage Level." A battery voltage threshold may be programmed in “Register 1Ah. Low Battery Detector Threshold." When the battery voltage level drops below the battery voltage threshold an interrupt will be generated on the nIRQ pin to the microcontroller if the LBD interrupt is enabled in “Register 06h. Interrupt Enable 2.” The microcontroller will then need to verify the interrupt by reading the interrupt status register, addresses 03 and 04h. The LSB step size for the LBD ADC is 50 mV, with the ADC range demonstrated in the table below. If the LBD is enabled the LBD and ADC will automatically be enabled every 1 s for approximately 250 µs to measure the voltage which minimizes the current consumption in Sensor mode. Before an interrupt is activated four consecutive readings are required. BatteryVoltage = 1.7 + 50mV × ADCValue ADC Value VDD Voltage [V] 0 < 1.7 1 1.7–1.75 2 1.75–1.8 … … 29 3.1–3.15 30 3.15–3.2 31 > 3.2

Tel: +86-755-82973805 Fax: +86-755-82973550 E-ma il: sales@hoperf.com http://www.hoperf.com52 R RFM23BP 8.6. Wake-Up Timer and 32 kHz Clock Source The chip contains an integrated wake-up timer which can be used to periodically wake the chip from SLEEP mode. The wake-up timer runs from the internal 32.768 kHz RC O scillator. The wake-up timer can be configured to run when in SLEEP mode. If enwt = 1 in "Register 07h. Operating Mode and Function Control 1" when entering SLEEP mode, the wake-up timer will count for a time specified defined in Registers 14–16h, "Wake Up Timer Period." At the expiration of this period an in terrupt will be generated on the nIRQ pin if this interrupt is enabled. The microcontroller will then need to verify the interrupt by reading the Registers 03h–04h, "Interrupt Status 1 & 2". The wake-up timer value may be read at any time by the wtv[15:0] read only registers 17h–18h. The formula for calculating the Wake-Up Period is the following: WUT = 4 × M × 2 ms 32 .768 WUT Register Description wtr[4:0] R Value in Formula wtm[15:0] M Value in Formula Use of the D variable in the formula is only necessary if finer resolution is required than can be achieved by using the R value. Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

14 R/W Wake-Up Timer Period 1 wtr[4] wtr[3] wtr[2] wtr[1] wtr[0] 03h

15 R/W Wake-Up Timer Period 2 wtm[15] wtm[14] wtm[13] wtm[12] wtm[11] wtm[10] wtm[9] wtm[8] 00h

16 R/W Wake-Up Timer Period 3 wtm[7] wtm[6] wtm[5] wtm[4] wtm[3] wtm[2] wtm[1] wtm[0] 00h

17 R Wake-Up Timer Value 1 wtv[15] wtv[14] wtv[13] wtv[12] wtv[11] wtv[10] wtv[9] wtv[8] —

18 R Wake-Up Timer Value 2 wtv[7] wtv[6] wtv[5] wtv[4] wtv[3] wtv[2] wtv[1] wtv[0] —

There are two different methods for utilizing the wake-up timer (WUT) depending on if the WUT interrupt is enabled in “Register 06h. Interrupt Enable 2.” If the WUT interrupt is enabled then nIRQ pin will go low when the timer expires. The chip will also change stat e so that the 30 MHz XTAL is enabled so that the microcontroller clock output is available for the microcontroller to use to process the interrupt. The other method of use is to not enable the WUT interrupt and use the WUT GPIO setting. In this mode of operation the chip will not change state until commanded by the microcontroller. The different modes of operating the WUT and the current consumption impacts are demonstrated in Figure 29. A 32 kHz XTAL may also be used for better timing accuracy. By setting the x32 ksel bit in Register 07h "Operating & Function Control 1", GPIO0 is automatically reconfigured so that an external 32 kHz XTAL may be connected to this pin. In this mode, the GPIO0 is extremely sensitive to parasitic capacitance, so only the XTAL should be connected to this pin with the XTAL physically located as close to the pin as possible. Once the x32 ksel bit is set, all internal functions such as WUT, micro-controller clock, and LDC mode will use the 32 kHz XTAL and not the 32 kHz RC oscillator.

Figure 29. WUT Interrupt and WUT Operation

The Low Duty Cycle Mode is available to automatically wake-up the receiver to check if a valid signal is available. Figure 30. Low Duty Cycle Mode

8.8. GPIO Configuration Three general purpose IOs (GPIOs) are available. Numerous functions such as specific interrupts, TRSW control, Microcontroller Output, etc. can be routed to the GPIO pins as shown in the tables below. When in Shutdown mode all the GPIO pads are pulled low. Note: The ADC should not be selected as an input to the GPIO in standby or sleep modes and will cause excess current con- sumption. Add R/W Function/Des cription D7 D6 D5 D4 D3 D2 D1 D0 POR Def. 0B R/W GPIO0 Configuration gpio0drv[1] gpio0drv[0] pup0 gpio0[4] gpio0[3] gpio0[2] gpio0[1] gpio0[0] 00h 0C R/W GPIO1 Configuration gpio1drv[1] gpio1drv[0] pup1 gpio1[4] gpio1[3] gpio1[2] gpio1[1] gpio1[0] 00h 0D R/W GPIO2 Configuration gpio2drv[1] gpio2drv[0] pup2 gpio2[4] gpio2[3] gpio2[2] gpio2[1] gpio2[0] 00h 0E R/W I/O Port Configuration extitst[2] extitst[1] extitst[0] itsdo dio2 dio1 dio0 00h The GPIO settings for GPIO1 and GPIO2 are the same as for GPIO0 with the exception of the 00000 default setting. The default settings for each GPIO are listed below: GPIO 00000—Default Setting GPIO0 POR GPIO1 POR Inverted GPIO2 Microcontroller Clock The GPIO drive strength may be adjusted with the gpioXdrv[1:0] bits. Setting a higher value will increase the drive strength and current capability of the GPIO by changing the driver size. Special care should be taken in setting the drive strength and loading on GPIO2 when the microcontroller clock is used. Excess loading or inadequate drive may contribute to increased spurious emissions. Tel: +86-755-82973805 Fax: +86-755-82973550 E-ma il: sales@hoperf.com http://www.hoperf.com

that RX packet. The same antenna will also be used for the next corresponding TX packet. preamble length to obtain optimal antenna selection for synchronous mode is 4 bytes. Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def.

08 R/W Operating & Function

Table 17. Antenna Diversity Control

100 Antenna Diversity Algorithm 0 0

101 Antenna Diversity Algorithm 1 1

110 Antenna Diversity Algorithm in Beacon Mode 0 0

111 Antenna Diversity Algorithm in Beacon Mode 1 1

paragraph for Clear Channel Assessment (CCA). Add R/W Function/Description D7 D6 D5 D4 D3 D2 D1 D0 POR Def. the GPIO configuration register to GPIOx[3:0] = 1110. Figure 31. RSSI Value vs. Input Power

Tel: +86-755-82973805 Fax: +86-755-82973550 E-ma il: sales@hoperf.com http://www.hoperf.com58 RFM23BP 9. Reference Design Figure32A.RFM23BP Reference Design Schematic

1. Register Table and Descriptions

Table 18. Register Descriptions

00 R Device Type 0 0 0 dt[4] dt[3] dt[2] dt[1] dt[0] 00111

01 R Device Version 0 0 0 vc[4] vc[3] vc[2] vc[1] vc[0] 06h

02 R Device Status ffovfl ffunfl rxffem headerr reserved reserved cps[1] cps[0] —

06 R/W Interrupt Enable 2 enswdet enpreaval enpreainval enrssi enwut enlbd enchiprdy enpor 03h

07 R/W Operating & Function Control 1 swres enlbd enwt x32ksel txon rxon pllon xton 01h

14 R/W Wake-Up Timer Period 1 Reserved Reserved Reserved wtr[4] wtr[3] wtr[2] wtr[1] wtr[0] 03h

16 R/W Wake-Up Timer Period 3 wtm[7] wtm[6] wtm[5] wtm[4] wtm[3] wtm[2] wtm[1] wtm[0] 01h

19 R/W Low-Duty Cycle Mode Duration ldc[7] ldc[6] ldc[5] ldc[4] ldc[3] ldc[2] ldc[1] ldc[0] 00h

20 R/W Clock Recovery Oversampling

24 R/W Clock Recovery Timing Loop

25 R/W Clock Recovery Timing Loop

26 R Received Signal Strength Indi-

27 R/W RSSI Threshold for Clear

Table 18. Register Descriptions (Continued)

60 R/W Channel Filter Coefficient

61 Reserved

62 R/W Crystal Oscillator/Control Test pwst[2] pwst[1] pwst[0] clkhyst enbias2x enamp2x bufovr enbuf 24h

69 R/W AGC Override 1 Reserved sgi agcen lnagain pga3 pga2 pga1 pga0 20h

74 R/W Frequency Offset 2 Reserved Reserved Reserved Reserved Reserved Reserved fo[9] fo[8] 00h

75 R/W Frequency Band Select Reserved sbsel hbsel fb[4] fb[3] fb[2] fb[1] fb[0] 75h

76 R/W Nominal Carrier Frequency 1 fc[15] fc[14] fc[13] fc[12] fc[11] fc[10] fc[9] fc[8] BBh

77 R/W Nominal Carrier Frequency 0 fc[7] fc[6] fc[5] fc[4] fc[3] fc[2] fc[1] fc[0] 80h

78 Reserved

Tel: +86-755-82973805 Fax: +86-755-82973550 E-ma il: sales@hoperf.com http://www.hoperf.com 60 RFM23B P VCC S +3.3 to +6 V supply voltage. The recommended VCC supply voltage is +5V. GND S Ground reference. GPIO_0 I/O GPIO_1 I/O GPIO_2 I/O General Purpose Digital I/O that may be configured through the registers to perform various functions including: Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery Detect, TRSW, AntDiversity control, etc. See the SPI GPIO Configuration Registers, Address 0Bh, 0Ch, and 0Dh for more information. SDO O 0–VCC V digital output that provides a serial readback function of the internal control registers. SDI I Serial Data input. 0–VCC V digital input. This pin provides the serial data stream for the 4-line serial data bus. SCLK I Serial Clock input. 0–V DD V digital input. This pin provides the serial data clock function for the 4-line serial data bus. Data is clocked into the RFM23PS on positive edge transitions. nSEL I Serial Interface Select input. 0– V CC V digital input. This pin provides the Select/Enable function for the 4-line serial data bus. The signal is also used to signify burst read/write mode. nIRQ O General Microcontroller Interrupt Status outpu t. When the RFM23PS exhibits anyone of the Interrupt Events the nIRQ pin will be set low=0. Please see the Control Logic registers section for more information on the Interrupt Events. The Microcontroller can then determine the state of the interrupt by reading a corresponding SPI Interrupt Status Registers, Address 03h and 04h. SDN I Shutdown input pin. 0–VCC V digital input. SDN should be = 0 in all modes except Shutdown mode. When SDN =1 the chip will be completely shutdown and the contents of the registers will be lost. TX_ON I Tx ON select input pin, When RFM23BP is TX state,TX_ON should be = 0, RX_ON should be = 1 RX_ON I Rx ON select input pin, When RFM2 3BPS is RX state,RX_ON should be = 0, TX_ON should be = 1 ANT I/O RF signal output/input.(50 OHM output /input Impedance)

Tel: +86-755-82973805 Fax: +86-755-82973550 E-ma il: sales@hoperf.com http://www.hoperf.com RFM23BP

12.2 Mechanical Dimension:RFM23BP

SMD PACKAGE（S2）

HOPE MICROELECTRONICS CO.,LTD Add:4/F, Block B3, East Industrial Area, Huaqiaocheng, Shenzhen, Guangdong, China Tel: 86-755-82973805 Fax: 86-755-82973550 Email: sales@hoperf.com trade@hoperf.com Website: http://www.hoperf.com http://hoperf.en.alibaba.com This document may contain preliminary information and is subject to change by Hope Microelectronics without notice. Hope Microelectronics assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of Hope Microelectronics or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in the direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MECHANTABILITY OR FITNESS FOR A ARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT. ©2011, HOPE MICROELECTRONICS CO.,LTD. All rights reserved. Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com