RFL1N08 INTERSIL | Alldatasheet
Document overview
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Technical content
Features
- 1A, 80V and 100V
- r DS(ON) = 1.200Ω
Description
These are N-channel enhancement mode silicon-gate power field-effect transistors designed for applications such as switching regulators, switching converters, motor drivers, relay drivers and drivers for high-power bipolar switching transistors requiring high speed and low gate-drive power. These types can be operated directly from integrated cir- cuits. Formerly developmental type TA09282. Symbol Packaging JEDEC TO-204AA
Ordering Information
NOTE: When ordering, use the entire part number. D G S SOURCEDRAIN (CASE) GATE CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper ESD Handling Procedures. Copyright © Harris Corporation 1998 File Number 1385.2 RFL1N08, RFL1N10 1A, 80V and 100V, 1.200 Ohm, N-Channel, Power MOSFETs [ /Title (RFL1N 08, RFL1N1 /Subject (1A, 80V and 100V , 1.200 Ohm, N- Chan- nel, Power MOS- FETs) /Author /Key- words (Harris Semi- conduc- tor, N- Chan- nel, Power MOS- FETs, TO- 204AA) /Creator /DOCIN FO pdf-
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFL1N08 RFL1N10 UNITS Maximum Temperature for Soldering CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical SpecificationsTC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BV DSS ID = 250µA, VGS = 0V RFL1N08 80 - - V RFL1N10 100 - - V Gate Threshold Voltage V GS(TH) VDS = VGS , ID = 250µA, (Figure 8) 2 - 4 V Zero Gate Voltage Drain Current I DSS VGS = Rated BVDSS , VGS = 0V - - 1 µA VDS = 0.8 x Rated BVDSS , VGS = 0V, TJ = 125oC- - 2 5 µA On-State Drain Current (Note 2) I D(ON) VDS > ID(ON) x rDS(ON)MAX , VGS = 10V 1 - - A Gate to Source Leakage Current I GSS VGS =±20V - - ±100 nA Drain to Source On Resistance r DS(ON) ID = 5.6A, VGS = 10V, (Figures 6, 7) 1.200 Ω Turn-On Delay Time t d(ON) VDD = 50V, VGS = 10V, ID ≈ 1A, RG = 50Ω , R L = 50Ω (Figures 10, 11, 12) MOSFET Switching Times are Essentially Inde- pendent of Operating Temperature -1 7 2 5 n s Rise Time t r -3 0 4 5 n s Turn-Off Delay Time t d(OFF) -3 0 4 5 n s Fall Time t f -3 0 5 0 n s Input Capacitance C ISS VDS = 25V, VGS = 0V, f = 1MHz (Figure 9) - - 200 pF Output Capacitance C OSS - - 80 pF Reverse Transfer Capacitance C RSS - - 25 pF Thermal Resistance Junction to Case R θJC -- oC/W Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage (Note 2) VSD TJ = 25oC, ISD = 1A, VGS = 0V - - 1.4 V Reverse Recovery Time t rr TJ = 25oC, ISD = 1A, dISD /dt = 100A/µs - 100 - ns NOTES: 2. Pulse test: pulse width≤ 300µs, duty cycle≤ 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. RFL1N08, RFL1N10
FIGURE 7. NORMALIZED DRAIN TO SOURCE ON FIGURE 8. NORMALIZED GATE THRESHOLD VOLTAGE vs FIGURE 9. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE NOTE: Refer to Harris Application Notes AN7254 and AN7260. FIGURE 10. NORMALIZED SWITCHING WAVEFORMS FOR FIGURE 11. SWITCHING TIME TEST CIRCUIT FIGURE 12. RESISTIVE SWITCHING WAVEFORMS